added adxl372 to adalogger pcb using raw ic

pcb/impact-logger-adalogger.ko

@@ -28,7 +28,7 @@ class feather(Component):
                 'RST','3V3','VREFA','GND','A0','A1','A2','A3','A4','A5','SCK','MOSI','MISO','RXD0','TXD0','GND2',
                 'SDA','SCL','5','6','9','10','11','12','13','VBUS','EN','VBAT'
             ]
-    os=.02
+    os=.05
     pins = [Pin(-.4-os*(-1)**i,.75-.1*i,_pad,names[i]) for i in range(16)]
     pins += [Pin(.4-os*(-1)**i,-.75+.1*i,_pad,names[16+i]) for i in range(12)]
     shadow = filleted_rectangle(-.45,.45,-1,1,.08)
@@ -81,42 +81,23 @@ class AAA(Component):
         Via(-1.21+.25,.209,circle(0,0,.039))
     ]
 
-class ATxmegaE5(Component):
-    _padh = chamfered_rectangle(-.025,.025,-.007,.007,.002)
-    _padv = chamfered_rectangle(-.007,.007,-.025,.025,.002)
-    c=.18
-    d = 0.8/25.4
-    names = [
-        '1 GND','PA4','PA3','PA2','PA1','PA0','PDI/DATA','RST/CLK',
-        'PC7','PC6','PC5','PC4','PC3','PC2','PC1','PC0',
-        'VCC','GND','PR1','PR0','PD7','PD6','PD5','PD4',
-        'PD3','PD2','PD1','PD0','PA7','PA6','PA5','AVCC'
-    ]
-    pins = [Pin(-c,(3.5-i)*d,_padh,n,label_size=.025) for i,n in enumerate(names[:8])]
-    pins += [Pin((-3.5+i)*d,-c,_padv,n,label_size=.025,label_rot=-90) for i,n in enumerate(names[8:16])]
-    pins += [Pin(c,(-3.5+i)*d,_padh,n,label_size=.025) for i,n in enumerate(names[16:24])]
-    pins += [Pin((3.5-i)*d,c,_padv,n,label_size=.025,label_rot=-90) for i,n in enumerate(names[24:])]
-    vias = []
-    shadow = rectangle(-c+d,c-d,-c+d,c-d)
+class ADXL372Z(Component):
+    names = ['VIO','NC','RES','SCLK','RES2','MOSI','MISO','CS','INT2','RES3','INT1','GND','GND2','VS','NC2','GND3']
+    p = .5/25.4
+    w = 2.5/25.4
+    h = 2.5/25.4
+    padhw = .125/25.4
+    pad1 = rectangle(-.7/25.4,.36/25.4,-padhw,padhw)
+    pad2 = rectangle(-padhw,padhw,-.7/25.4,.4/25.4,)
+    pad3 = rectangle(-.36/25.4,.7/25.4,-padhw,padhw)
+    pad4 = rectangle(-padhw,padhw,-.4/25.4,.7/25.4,)
+    pins = [Pin(-.5*w, p*(2-i),pad1,names[i],label_size=.01) for i in range(5)]
+    pins += [Pin(p*(-1+i),-.5*h,pad2,names[i+5],label_size=.01,label_rot=90) for i in range(3)]
+    pins += [Pin(.5*w, p*(-2+i),pad3,names[i+8],label_size=.01) for i in range(5)]
+    pins += [Pin(p*(1-i),.5*h,pad4,names[i+13],label_size=.01,label_rot=90) for i in range(3)]
 
-class ATxmega16A4U(Component):
-    _padh = chamfered_rectangle(-.024,.024,-.007,.007,.003)
-    _padv = chamfered_rectangle(-.007,.007,-.024,.024,.003)
-    c= 11/25.4/2.
-    d = 0.8/25.4
-    names = [
-        'PA5','PA6','PA7','PB0','PB1','PB2','PB3','GND','VCC','PC0','PC1',
-        'PC2','PC3','PC4','PC5','PC6','PC7','GND2','VCC2','PD0','PD1','PD2',
-        'PD3','PD4','PD5','PD6','PD7','PE0','PE1','GND3','VCC3','PE2','PE3',
-        'PDI/DATA','RST/CLK','PR0','PR1','GND4','AVCC','PA0','PA1','PA2','PA3','PA4'
-    ]
-    n_side = 11
-    pins = [Pin(-c,(5-i)*d,_padh,n,label_size=.025) for i,n in enumerate(names[:n_side])]
-    pins += [Pin((-5+i)*d,-c,_padv,n,label_size=.025,label_rot=-90) for i,n in enumerate(names[n_side:2*n_side])]
-    pins += [Pin(c,(-5+i)*d,_padh,n,label_size=.025) for i,n in enumerate(names[2*n_side:3*n_side])]
-    pins += [Pin((5-i)*d,c,_padv,n,label_size=.025,label_rot=-90) for i,n in enumerate(names[3*n_side:])]
     vias = []
-    shadow = rectangle(-c+d,c-d,-c+d,c-d)
+    shadow = rectangle(-1.75/25.4, 1.75/25.4, -1.68/25.4, 1.68/25.4)
 
 class ADXL372Z_EVAL(Component):
     names = ['VS','VIO','GND','INT2','INT1','CS','MISO','MOSI','SCLK','GND2']
@@ -169,7 +150,7 @@ holes += rotate(holes,90) + rotate(holes,180) + rotate(holes,-90)
 holes = rotate(holes,45)
 pcb.custom_cutout = board-holes
 
-pcb.custom_cutout = filleted_rectangle(-1.2,.8,-.48,.48,.1)
+pcb.custom_cutout = filleted_rectangle(-.8,1.2,-.5,.5,.15)
 
 def connectG(pin,dx,dy,width=.014):
     '''
@@ -185,28 +166,37 @@ def connectM(pin1,pin2,dx,width=.014):
 #pcb.custom_cutout += chamfered_rectangle(0,.6*width,0,height,.12)
 
 
-f = feather(-.2,0,90,'feather')
+f = feather(0.2,0,90)
 pcb += f
 
 
 #ADXL372
-adxl = ADXL372Z_EVAL(0,0,0,'adxl372')
+#adxl = ADXL372Z_EVAL(0,0,0,'adxl372')
 #pcb.custom_cutout = adxl.shadow
-pcb += adxl
-
+#pcb += adxl
 
-pcb.connectD(adxl['MISO'],[adxl['MISO'].x-.05,adxl['MISO'].y+.0],[f['MISO'].x-.19,f['MISO'].y+.18],[f['MISO'].x-.03,f['MISO'].y+.14],f['MISO'])
-pcb.connectD(adxl['MOSI'],[adxl['MOSI'].x-.05,adxl['MOSI'].y],[f['MOSI'].x-.16,f['MOSI'].y+.15],f['MOSI'])
-pcb.connectD(adxl['SCLK'],[adxl['SCLK'].x-.05,adxl['SCLK'].y],[f['SCK'].x-.11,f['SCK'].y+.17],f['SCK'])
-pcb.connectD(adxl['GND'],[adxl['GND'].x+.05,adxl['GND'].y],adxl['GND2'],width=.03)
-pcb.connectD(f['GND'],[f['GND'].x,f['GND'].y+.05],adxl['GND'],width=.03)
-pcb.connectD(f['3V3'],[f['3V3'].x,f['3V3'].y+.05],adxl['VIO'],width=.03)
-pcb.connectV(adxl['VIO'],adxl['VS'],width=.03)
-
-pcb.connectD(f['A1'],[f['A1'].x,f['A1'].y+.05],adxl['INT2'])
-pcb.connectD(adxl['INT1'],[adxl['INT1'].x,adxl['INT1'].y-.05],[f['A5'].x-.02,f['A5'].y],f['A5'])
-pcb.connectD(f['6'],[f['6'].x,f['6'].y-.08],[adxl['CS'].x+.1,adxl['CS'].y+.05],adxl['CS'])
+adxl = ADXL372Z(0,0,90,'adxl372')
+pcb += adxl
 
+pcb.connectH(adxl['VIO'],[adxl['VS'].x-.05,adxl['VS'].y],adxl['VS'],width=.01)
+pcb.connectH(adxl['GND3'],[adxl['GND'].x+.0005,adxl['GND'].y],adxl['GND'],width=.009)
+pcb.connectH(adxl['GND2'],adxl['GND'],width=.01)
+pcb.connectH(adxl['NC'],[adxl['GND'].x+.0005,adxl['GND'].y],adxl['GND'],width=.009)
+
+
+pcb.connectD(adxl['SCLK'],[adxl['SCLK'].x,adxl['SCLK'].y-.06],[adxl['SCLK'].x+.05,adxl['SCLK'].y-.06],[f['SCK'].x-.05,f['SCK'].y+.2],f['SCK'],width=[.01,.01,.02,.02,.02,.02,.02,.02])
+pcb.connectD(adxl['MOSI'],[adxl['MOSI'].x+.05,adxl['MOSI'].y],[f['MOSI'].x-.08,f['MOSI'].y+.16],f['MOSI'],width=[.01,.01,.02,.02,.02,.02])
+pcb.connectD(adxl['MISO'],[adxl['MISO'].x+.1,adxl['MISO'].y],[f['MISO'].x-.15,f['MISO'].y+.32],f['MISO'],width=[.01,.01,.02,.02,.02,.02])
+pcb.connectD(adxl['CS'],[adxl['CS'].x+.05,adxl['CS'].y],f['11'],width=[.01,.01,.02,.02])
+pcb.connectD(adxl['INT2'],[adxl['INT2'].x,adxl['INT2'].y+.05],f['12'],width=[.01,.01,.02,.02])
+pcb.connectD(adxl['INT1'],[adxl['INT1'].x,adxl['INT1'].y+.08],f['13'],width=[.01,.01,.02,.02])
+pcb.connectD(f['3V3'],[f['3V3'].x,f['3V3'].y+.15],[adxl['VIO'].x-.07,adxl['VIO'].y],adxl['VIO'],width=[.02,.02,.02,.02,.02,.01])
+pcb.connectD(f['GND'],[f['GND'].x,f['GND'].y+.2],[adxl['NC'].x,adxl['NC'].y-.06],adxl['NC'],width=[.02,.02,.02,.02,.01,.01,.01])
+
+C1 = C_1206(adxl.x-.14,adxl.y-.07,90,'C1\n.1uF',label_size=.04)
+pcb += C1
+C2 = C_1206(C1.x-.1,C1.y,90,'C2\n1uF',label_size=.04)
+pcb += C2
 
 cad.shapes = pcb.layout()
 #cad.shape = pcb.traces+(pcb.cutout-pcb.cutout)