diff --git a/as5013-test/nrf52-as5013-interior.png b/as5013-test/nrf52-as5013-interior.png
index 8144b66cd67228fff89796ceed0ef047336f2a27..5d29256bbfe89da8533c5b41081b7a9eb10fc300 100644
Binary files a/as5013-test/nrf52-as5013-interior.png and b/as5013-test/nrf52-as5013-interior.png differ
diff --git a/as5013-test/nrf52-as5013-layout.png b/as5013-test/nrf52-as5013-layout.png
index 61da6d7911dbf31cdbd35a5558681448330d0c19..7ccc0bb3516737e244f7d8f0fefa4770114c0c81 100644
Binary files a/as5013-test/nrf52-as5013-layout.png and b/as5013-test/nrf52-as5013-layout.png differ
diff --git a/as5013-test/nrf52-as5013-traces.png b/as5013-test/nrf52-as5013-traces.png
index f7a1f8a4f493ace3ba6082761a20f338d924a8ad..c519b27c7c82498e22b44e990535df815f37b7a8 100644
Binary files a/as5013-test/nrf52-as5013-traces.png and b/as5013-test/nrf52-as5013-traces.png differ
diff --git a/as5013-test/nrf52-as5013.ko b/as5013-test/nrf52-as5013.ko
index a8994636505dfd434ff3e470ae5dc2cec36914ba..2d189d9f39855beb3fddc3d3553d343919556fd3 100644
--- a/as5013-test/nrf52-as5013.ko
+++ b/as5013-test/nrf52-as5013.ko
@@ -283,17 +283,14 @@ h = .16
 hall = AS5013(.5*width,h,-180)
 pcb += hall
 
-#TODO: check bolt holes
 
-pcb.connectD(hall['SDA'],[hall['SDA'].x+.07,hall['SDA'].y],bc['XL2'],width=.014)
-pcb.connectD(hall['SCL'],[hall['SCL'].x+.05,hall['SCL'].y],bc['XL1'],width=.014)
 
 #pcb.connectH(hall['SCL'],[hall['SCL'].x,hall['SCL'].y+.06],bc['XL1'])
 #pcb.connectV(hall['RST'],[C2[0].x,C2[0].y-.06],C2[0])
 
-RSDA = R_1206(bc['XL2'].x+.09,bc['XL2'].y-.08,0,'RSDA')
+RSDA = R_1206(bc['XL2'].x+.12,bc['XL2'].y-.08,0,'RSDA')
 pcb += RSDA
-RSCL = R_1206(bc['XL1'].x+.045,RSDA.y-.1,0,'RSCL')
+RSCL = R_1206(RSDA[1].x,RSDA.y-.09,0,'RSCL')
 pcb += RSCL
 pcb.connectH(RSCL[0],RSDA[0])
 pcb.connectH(RSDA[0],bc['VDD'])
@@ -308,7 +305,16 @@ pcb.connectD(C_hall[1],[C_hall[1].x,C_hall[1].y-.05],[hall['VSS'].x,hall['VSS'].
 pcb.connectD(C_hall[0],[C_hall[0].x,C_hall[0].y+.1],C2[0])
 pcb.connectD(C_hall[1],[C_hall[1].x,C_hall[1].y+.15],C_out[1])
 
-pcb.connectV(C_hall[0],[C_hall.x-.15,C_hall.y+.1],[bc['VDD'].x,C_hall.y-.12],bc['VDD']).add_jumper([C_hall[1].x,C_hall.y+.1])
+
+pcb.connectD(hall['SDA'],[RSDA[1].x-.07,hall['SDA'].y],RSDA[1],width=.014)
+pcb.connectD(RSDA[1],[RSDA[1].x-.05,RSDA[1].y],bc['XL2'])
+pcb.connectD(hall['SCL'],[RSCL[1].x-.03,hall['SCL'].y],RSCL[1],width=.014)
+pcb.connectD(RSCL[1],bc['XL1'])
+
+pcb.connectD(hall['RST'],[hall['RST'].x+.04,hall['RST'].y],[hall['RST'].x+.05,hall['RST'].y+.05],bc['A1'],width=.014)
+
+
+pcb.connectD(C_hall[0],[C_hall[0].x,C_hall.y+.1],[C_hall.x-.15,C_hall.y+.1],[C_hall.x-.15,C_hall.y-.08],[bc['VDD'].x-.2,C_hall.y-.12],bc['VDD']).add_jumper([C_hall[1].x,C_hall.y+.1])
 
 #pow = Header_Power(reg.x-.2,reg.y,0,'pow')
 #pcb += pow