PDITarget.c 8.91 KB
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/*
             LUFA Library
     Copyright (C) Dean Camera, 2009.
              
  dean [at] fourwalledcubicle [dot] com
      www.fourwalledcubicle.com
*/

/*
  Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, and distribute this software
  and its documentation for any purpose and without fee is hereby
  granted, provided that the above copyright notice appear in all
  copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaim all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

/** \file
 *
 *  Target-related functions for the PDI Protocol decoder.
 */

#define  INCLUDE_FROM_PDITARGET_C
#include "PDITarget.h"

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#if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)

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/** Flag to indicate if the USART is currently in Tx or Rx mode. */
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volatile bool     IsSending;
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#if !defined(PDI_VIA_HARDWARE_USART)
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/** Software USART raw frame bits for transmission/reception. */
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volatile uint16_t SoftUSART_Data;
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/** Bits remaining to be sent or received via the software USART - set as a GPIOR for speed. */
#define SoftUSART_BitCount   GPIOR2
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/** ISR to manage the software USART when bit-banged USART mode is selected. */
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ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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{
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	/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
	BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;
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	/* If not sending or receiving, just exit */
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	if (!(SoftUSART_BitCount))
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	  return;
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	/* Check to see if we are at a rising or falling edge of the clock */
	if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)
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	{
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		/* If at rising clock edge and we are in send mode, abort */
		if (IsSending)
		  return;
		  
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		/* Wait for the start bit when receiving */
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		if ((SoftUSART_BitCount == BITS_IN_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
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		  return;
	
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		if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
		  SoftUSART_Data |= (1 << BITS_IN_FRAME);
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		SoftUSART_Data >>= 1;
		SoftUSART_BitCount--;
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	}
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	else
	{
		/* If at falling clock edge and we are in receive mode, abort */
		if (!IsSending)
		  return;

		if (SoftUSART_Data & 0x01)
		  BITBANG_PDIDATA_PORT |=  BITBANG_PDIDATA_MASK;
		else
		  BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;		  

		SoftUSART_Data >>= 1;
		SoftUSART_BitCount--;
	}
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}
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#endif
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/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
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void PDITarget_EnableTargetPDI(void)
{
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#if defined(PDI_VIA_HARDWARE_USART)
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	/* Set Tx and XCK as outputs, Rx as input */
	DDRD |=  (1 << 5) | (1 << 3);
	DDRD &= ~(1 << 2);
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	/* Set DATA line high for at least 90ns to disable /RESET functionality */
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	PORTD |= (1 << 3);
	asm volatile ("NOP"::);
	asm volatile ("NOP"::);
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	/* Set up the synchronous USART for XMEGA communications - 
	   8 data bits, even parity, 2 stop bits */
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	UBRR1  = (F_CPU / 1000000UL);
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	UCSR1B = (1 << TXEN1);
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	UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);

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	/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
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	PDITarget_SendBreak();
	PDITarget_SendBreak();
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#else
	/* Set DATA and CLOCK lines to outputs */
	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
	BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
	
	/* Set DATA line high for at least 90ns to disable /RESET functionality */
	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
	asm volatile ("NOP"::);
	asm volatile ("NOP"::);

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	/* Fire timer compare ISR every 100 cycles to manage the software USART */
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	OCR1A   = 80;
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	TCCR1B  = (1 << WGM12) | (1 << CS10);
	TIMSK1  = (1 << OCIE1A);
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	PDITarget_SendBreak();
	PDITarget_SendBreak();
#endif
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}

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/** Disables the target's PDI interface, exits programming mode and starts the target's application. */
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void PDITarget_DisableTargetPDI(void)
{
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#if defined(PDI_VIA_HARDWARE_USART)
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	/* Turn off receiver and transmitter of the USART, clear settings */
	UCSR1A |= (1 << TXC1) | (1 << RXC1);
	UCSR1B  = 0;
	UCSR1C  = 0;
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	/* Set all USART lines as input, tristate */
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	DDRD  &= ~((1 << 5) | (1 << 3));
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	PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
	/* Set DATA and CLOCK lines to inputs */
	BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;
	BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;
	
	/* Tristate DATA and CLOCK lines */
	BITBANG_PDIDATA_PORT  &= ~BITBANG_PDIDATA_MASK;
	BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;

	TCCR0B  = 0;
#endif
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}

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/** Sends a byte via the USART.
 *
 *  \param[in] Byte  Byte to send through the USART
 */
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void PDITarget_SendByte(uint8_t Byte)
{
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#if defined(PDI_VIA_HARDWARE_USART)
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	/* Switch to Tx mode if currently in Rx mode */
	if (!(IsSending))
	{
		PORTD  |=  (1 << 3);
		DDRD   |=  (1 << 3);
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		UCSR1B |=  (1 << TXEN1);
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		UCSR1B &= ~(1 << RXEN1);
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		IsSending = true;
	}
	
	/* Wait until there is space in the hardware Tx buffer before writing */
	while (!(UCSR1A & (1 << UDRE1)));
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	UCSR1A |= (1 << TXC1);
	UDR1    = Byte;
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#else
	/* Switch to Tx mode if currently in Rx mode */
	if (!(IsSending))
	{
		BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
		BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;

		IsSending = true;
	}

	bool    EvenParityBit = false;
	uint8_t ParityData    = Byte;

	/* Compute Even parity bit */
	for (uint8_t i = 0; i < 8; i++)
	{
		EvenParityBit ^= ParityData & 0x01;
		ParityData    >>= 1;
	}

	while (SoftUSART_BitCount);

	/* Data shifted out LSB first, START DATA PARITY STOP STOP */
	SoftUSART_Data     = ((uint16_t)EvenParityBit << 9) | ((uint16_t)Byte << 1) | (1 << 10) | (1 << 11);
	SoftUSART_BitCount = BITS_IN_FRAME;
#endif
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}

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/** Receives a byte via the software USART, blocking until data is received.
 *
 *  \return Received byte from the USART
 */
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uint8_t PDITarget_ReceiveByte(void)
{
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#if defined(PDI_VIA_HARDWARE_USART)
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	/* Switch to Rx mode if currently in Tx mode */
	if (IsSending)
	{
		while (!(UCSR1A & (1 << TXC1)));
		UCSR1A |=  (1 << TXC1);
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		UCSR1B &= ~(1 << TXEN1);
		UCSR1B |=  (1 << RXEN1);

		DDRD   &= ~(1 << 3);
		PORTD  &= ~(1 << 3);
		
		IsSending = false;
	}

	/* Wait until a byte has been received before reading */
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	while (!(UCSR1A & (1 << RXC1)));
	return UDR1;
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#else
	/* Switch to Rx mode if currently in Tx mode */
	if (IsSending)
	{
		while (SoftUSART_BitCount);

		BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
		BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;

		IsSending = false;
	}

	/* Wait until a byte has been received before reading */
	SoftUSART_BitCount = BITS_IN_FRAME;
	while (SoftUSART_BitCount);
	
	/* Throw away the start, parity and stop bits to leave only the data */
	return (uint8_t)(SoftUSART_Data >> 1);
#endif
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}

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/** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
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void PDITarget_SendBreak(void)
{
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#if defined(PDI_VIA_HARDWARE_USART)
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	/* Switch to Tx mode if currently in Rx mode */
	if (!(IsSending))
	{
		PORTD  |=  (1 << 3);
		DDRD   |=  (1 << 3);

		UCSR1B &= ~(1 << RXEN1);
		UCSR1B |=  (1 << TXEN1);
		
		IsSending = true;
	}
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	/* Need to do nothing for a full frame to send a BREAK */
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	for (uint8_t i = 0; i <= BITS_IN_FRAME; i++)
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	{
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		/* Wait for a full cycle of the clock */
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		while (PIND & (1 << 5));
		while (!(PIND & (1 << 5)));
	}
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#else
	/* Switch to Tx mode if currently in Rx mode */
	if (!(IsSending))
	{
		BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
		BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;

		IsSending = true;
	}
	
	while (SoftUSART_BitCount);

	/* Need to do nothing for a full frame to send a BREAK */
	SoftUSART_Data     = 0x0FFF;
	SoftUSART_BitCount = BITS_IN_FRAME;
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#endif
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}

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/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC
 *  calculation.
 *
 *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
 */
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bool PDITarget_WaitWhileNVMBusBusy(void)
{
	TCNT0 = 0;

	/* Poll the STATUS register to check to see if NVM access has been enabled */
	while (TCNT0 < PDI_NVM_TIMEOUT_MS)
	{
		/* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
		PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
		if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
		  return true;
	}
	
	return false;
}

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#endif