NVMTarget.c 7.47 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
/*
             LUFA Library
     Copyright (C) Dean Camera, 2009.
              
  dean [at] fourwalledcubicle [dot] com
      www.fourwalledcubicle.com
*/

/*
  Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, and distribute this software
  and its documentation for any purpose and without fee is hereby
  granted, provided that the above copyright notice appear in all
  copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaim all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

/** \file
 *
 *  Target-related functions for the target's NVM module.
 */

#define  INCLUDE_FROM_NVMTARGET_C
#include "NVMTarget.h"

#if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)

41
42
43
44
/** Sends the given NVM register address to the target.
 *
 *  \param[in] Register  NVM register whose absolute address is to be sent
 */
45
46
void NVMTarget_SendNVMRegAddress(uint8_t Register)
{
47
	/* Determine the absolute register address from the NVM base memory address and the NVM register address */
48
49
	uint32_t Address = XPROG_Param_NVMBase | Register;

50
	/* Send the calculated 32-bit address to the target, LSB first */
51
	PDITarget_SendByte(Address &  0xFF);
52
53
54
55
56
	PDITarget_SendByte(Address >> 8);
	PDITarget_SendByte(Address >> 16);
	PDITarget_SendByte(Address >> 24);
}

57
58
59
60
/** Sends the given 32-bit absolute address to the target.
 *
 *  \param[in] AbsoluteAddress  Absolute address to send to the target
 */
61
62
void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
{
63
	/* Send the given 32-bit address to the target, LSB first */
64
65
66
67
	PDITarget_SendByte(AbsoluteAddress &  0xFF);
	PDITarget_SendByte(AbsoluteAddress >> 8);
	PDITarget_SendByte(AbsoluteAddress >> 16);
	PDITarget_SendByte(AbsoluteAddress >> 24);
68
69
}

70
71
72
73
74
/** Waits while the target's NVM controller is busy performing an operation, exiting if the
 *  timeout period expires.
 *
 *  \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
 */
75
bool NVMTarget_WaitWhileNVMControllerBusy(void)
76
{
77
	TCNT0 = 0;
78
79

	/* Poll the NVM STATUS register while the NVM controller is busy */
80
	while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
81
	{
82
		/* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
83
		PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
84
85
		NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
		
86
		/* Check to see if the BUSY flag is still set */
87
		if (!(PDITarget_ReceiveByte() & (1 << 7)))
88
		  return true;
89
	}
90
91
	
	return false;
92
93
}

94
95
96
97
98
99
100
/** Retrieves the CRC value of the given memory space.
 *
 *  \param[in] CRCCommand  NVM CRC command to issue to the target
 *
 *  \return 24-bit CRC value for the given address space
 */
uint32_t NVMTarget_GetMemoryCRC(uint8_t CRCCommand)
101
102
103
{
	uint32_t MemoryCRC;

104
105
	NVMTarget_WaitWhileNVMControllerBusy();

106
	/* Set the NVM command to the correct CRC read command */
107
	PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
108
	NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
109
	PDITarget_SendByte(CRCCommand);
110
111

	/* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
112
	PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
113
114
115
116
	NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
	PDITarget_SendByte(1 << 0);

	/* Wait until the NVM bus and controller is no longer busy */
117
	PDITarget_WaitWhileNVMBusBusy();
118
119
	NVMTarget_WaitWhileNVMControllerBusy();
	
120
	/* Read the first generated CRC byte value */
121
	PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
122
123
	NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
	MemoryCRC  = PDITarget_ReceiveByte();
124

125
	/* Read the second generated CRC byte value */
126
127
	PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
	NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
128
	MemoryCRC |= ((uint16_t)PDITarget_ReceiveByte() << 8);
129

130
	/* Read the third generated CRC byte value */
131
132
	PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
	NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
133
134
135
136
137
	MemoryCRC |= ((uint32_t)PDITarget_ReceiveByte() << 16);
	
	return MemoryCRC;
}

138
139
140
141
142
143
/** Reads memory from the target's memory spaces.
 *
 *  \param[in]  ReadAddress  Start address to read from within the target's address space
 *  \param[out] ReadBuffer   Buffer to store read data into
 *  \param[in]  ReadSize     Number of bytes to read
 */
144
145
146
void NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
{
	NVMTarget_WaitWhileNVMControllerBusy();
147
148
	
	/* Send the READNVM command to the NVM controller for reading of an aribtrary location */
149
150
151
152
	PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
	NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
	PDITarget_SendByte(NVM_CMD_READNVM);

153
154
155
156
157
158
159
160
	/* Send the address of the first location to read from - this also primes the internal address
	 * counters so that we can use the REPEAT command later to save on overhead for multiple bytes */
	PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
	NVMTarget_SendAddress(ReadAddress);
	*(ReadBuffer++) = PDITarget_ReceiveByte();

	/* Check to see if we are reading more than a single byte */
	if (ReadSize > 1)
161
	{
162
163
164
165
166
167
168
169
170
171
172
173
		/* Decrement the ReadSize counter as we have already read once byte of memory */
		ReadSize--;
	
		/* Send the REPEAT command with the specified number of bytes remaining to read */
		PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_2BYTES);
		PDITarget_SendByte(ReadSize &  0xFF);
		PDITarget_SendByte(ReadSize >> 8);
		
		/* Send a LD command with indirect access and postincrement to read out the remaining bytes */
		PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
		for (uint16_t i = 1; i < ReadSize; i++)
		  *(ReadBuffer++) = PDITarget_ReceiveByte();
174
175
176
	}
}

177
178
179
180
181
/** Erases a specific memory space of the target.
 *
 *  \param[in] EraseCommand  NVM erase command to send to the device
 *  \param[in] Address  Address inside the memory space to erase
 */
182
183
184
185
186
187
188
189
void NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
{
	NVMTarget_WaitWhileNVMControllerBusy();

	PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
	NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
	PDITarget_SendByte(EraseCommand);
	
190
	/* Chip erase is handled seperately, since it's procedure is different to other erase types */
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
	if (EraseCommand == NVM_CMD_CHIPERASE)
	{
		/* Set CMDEX bit in NVM CTRLA register to start the chip erase */
		PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
		NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
		PDITarget_SendByte(1 << 0);		
	}
	else
	{
		/* Other erase modes just need us to address a byte within the target memory space */
		PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
		NVMTarget_SendAddress(Address);	
		PDITarget_SendByte(0x00);
	}
	
206
207
	/* Wait until both the NVM bus and NVM controller are ready again */
	PDITarget_WaitWhileNVMBusBusy();
208
209
210
	NVMTarget_WaitWhileNVMControllerBusy();
}

211
#endif