From b634ec50a0646a1575d89add8ac851f7d8a66332 Mon Sep 17 00:00:00 2001
From: Dean Camera <dean@fourwalledcubicle.com>
Date: Thu, 25 Nov 2010 03:20:01 +0000
Subject: [PATCH] Changed the XPLAINBridge software UART to use the regular CTC
mode instead of the alternative CTC mode via the Input Capture register, to
reduce user confusion.
---
LUFA/ManPages/ChangeLog.txt | 5 +++--
Projects/Webserver/Lib/uip/clock.c | 2 +-
Projects/XPLAINBridge/Lib/SoftUART.c | 12 ++++++------
Projects/XPLAINBridge/Lib/SoftUART.h | 4 ++--
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/LUFA/ManPages/ChangeLog.txt b/LUFA/ManPages/ChangeLog.txt
index b5d36c9b7..402865fe7 100644
--- a/LUFA/ManPages/ChangeLog.txt
+++ b/LUFA/ManPages/ChangeLog.txt
@@ -11,13 +11,14 @@
* - Core:
* - None
* - Library Applications:
- * - None
+ * - Added new incomplete MIDIToneGenerator project
*
* <b>Changed:</b>
* - Core:
* - None
* - Library Applications:
- * - None
+ * - Changed the XPLAINBridge software UART to use the regular CTC mode instead of the alternative CTC mode
+ * via the Input Capture register, to reduce user confusion
*
* <b>Fixed:</b>
* - Core:
diff --git a/Projects/Webserver/Lib/uip/clock.c b/Projects/Webserver/Lib/uip/clock.c
index 0906e6125..71eaf2b28 100644
--- a/Projects/Webserver/Lib/uip/clock.c
+++ b/Projects/Webserver/Lib/uip/clock.c
@@ -11,7 +11,7 @@
volatile clock_time_t clock_datetime = 0;
//Overflow interrupt
-ISR(TIMER1_COMPA_vect)
+ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{
clock_datetime += 1;
}
diff --git a/Projects/XPLAINBridge/Lib/SoftUART.c b/Projects/XPLAINBridge/Lib/SoftUART.c
index 4b38a0bd2..9df42c596 100644
--- a/Projects/XPLAINBridge/Lib/SoftUART.c
+++ b/Projects/XPLAINBridge/Lib/SoftUART.c
@@ -67,11 +67,11 @@ void SoftUART_Init(void)
SoftUART_SetBaud(9600);
/* Setup reception timer compare ISR */
- TIMSK1 = (1 << ICIE1);
+ TIMSK1 = (1 << OC1E1A);
/* Setup transmission timer compare ISR and start the timer */
- TIMSK3 = (1 << ICIE3);
- TCCR3B = ((1 << CS30) | (1 << WGM33) | (1 << WGM32));
+ TIMSK3 = (1 << OC1E3A);
+ TCCR3B = ((1 << CS30) | (1 << WGM32));
}
/** ISR to detect the start of a bit being sent to the software UART. */
@@ -90,12 +90,12 @@ ISR(INT0_vect, ISR_BLOCK)
EIMSK = 0;
/* Start the reception timer */
- TCCR1B = ((1 << CS10) | (1 << WGM13) | (1 << WGM12));
+ TCCR1B = ((1 << CS10) | (1 << WGM12));
}
}
/** ISR to manage the reception of bits to the software UART. */
-ISR(TIMER1_CAPT_vect, ISR_BLOCK)
+ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{
/* Cache the current RX pin value for later checking */
uint8_t SRX_Cached = (SRXPIN & (1 << SRX));
@@ -125,7 +125,7 @@ ISR(TIMER1_CAPT_vect, ISR_BLOCK)
}
/** ISR to manage the transmission of bits via the software UART. */
-ISR(TIMER3_CAPT_vect, ISR_BLOCK)
+ISR(TIMER3_COMPA_vect, ISR_BLOCK)
{
/* Check if transmission has finished */
if (TX_BitsRemaining)
diff --git a/Projects/XPLAINBridge/Lib/SoftUART.h b/Projects/XPLAINBridge/Lib/SoftUART.h
index 6dedf6149..803e1e5a6 100644
--- a/Projects/XPLAINBridge/Lib/SoftUART.h
+++ b/Projects/XPLAINBridge/Lib/SoftUART.h
@@ -60,8 +60,8 @@
{
uint16_t BitTime = ((F_CPU / Baud) - 1);
- ICR1 = BitTime;
- ICR3 = BitTime;
+ OCR1A = BitTime;
+ OCR3A = BitTime;
}
/* Function Prototypes: */
--
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