interrupt_sam_nvic.h 5.11 KB
 Jake Read committed Nov 28, 2017 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 /** * \file * * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) * * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved. * * \asf_license_start * * \page License * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. The name of Atmel may not be used to endorse or promote products derived * from this software without specific prior written permission. * * 4. This software may only be redistributed and used in connection with an * Atmel microcontroller product. * * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * \asf_license_stop * */ /* * Support and FAQ: visit Atmel Support */ #ifndef UTILS_INTERRUPT_INTERRUPT_H #define UTILS_INTERRUPT_INTERRUPT_H #include #include #ifdef __cplusplus extern "C" { #endif /** * \weakgroup interrupt_group * * @{ */ /** * \name Interrupt Service Routine definition * * @{ */ /** * \brief Define service routine * * \note For NVIC devices the interrupt service routines are predefined to * add to vector table in binary generation, so there is no service * register at run time. The routine collections are in exceptions.h. * * Usage: * \code ISR(foo_irq_handler) { // Function definition ... } \endcode * * \param func Name for the function. */ # define ISR(func) \ void func (void) /** * \brief Initialize interrupt vectors * * For NVIC the interrupt vectors are put in vector table. So nothing * to do to initialize them, except defined the vector function with * right name. * * This must be called prior to \ref irq_register_handler. */ # define irq_initialize_vectors() \ do { \ } while(0) /** * \brief Register handler for interrupt * * For NVIC the interrupt vectors are put in vector table. So nothing * to do to register them, except defined the vector function with * right name. * * Usage: * \code irq_initialize_vectors(); irq_register_handler(foo_irq_handler); \endcode * * \note The function \a func must be defined with the \ref ISR macro. * \note The functions prototypes can be found in the device exception header * files (exceptions.h). */ # define irq_register_handler(int_num, int_prio) \ NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ NVIC_EnableIRQ( (IRQn_Type)int_num); \ //@} # define cpu_irq_enable() \ do { \ g_interrupt_enabled = true; \ __DMB(); \ __enable_irq(); \ } while (0) # define cpu_irq_disable() \ do { \ __disable_irq(); \ __DMB(); \ g_interrupt_enabled = false; \ } while (0) typedef uint32_t irqflags_t; #if !defined(__DOXYGEN__) extern volatile bool g_interrupt_enabled; #endif #define cpu_irq_is_enabled() (__get_PRIMASK() == 0) static volatile uint32_t cpu_irq_critical_section_counter; static volatile bool cpu_irq_prev_interrupt_state; static inline irqflags_t cpu_irq_save(void) { volatile irqflags_t flags = cpu_irq_is_enabled(); cpu_irq_disable(); return flags; } static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) { return (flags); } static inline void cpu_irq_restore(irqflags_t flags) { if (cpu_irq_is_enabled_flags(flags)) cpu_irq_enable(); } void cpu_irq_enter_critical(void); void cpu_irq_leave_critical(void); /** * \weakgroup interrupt_deprecated_group * @{ */ #define Enable_global_interrupt() cpu_irq_enable() #define Disable_global_interrupt() cpu_irq_disable() #define Is_global_interrupt_enabled() cpu_irq_is_enabled() //@} //@} #ifdef __cplusplus } #endif #endif /* UTILS_INTERRUPT_INTERRUPT_H */