Jake Read
coclocking

Repository

not(y,x);
module TinyFPGA_A2 (
  inout pin1,
  inout pin2,
  inout pin3_sn,
  inout pin4_mosi,
  inout pin5,
  inout pin6,
  inout pin7_done,
  inout pin8_pgmn,
  inout pin9_jtgnb,
  inout pin10_sda,
  inout pin11_scl,
  //inout pin12_tdo,
  //inout pin13_tdi,
  //inout pin14_tck,
  //inout pin15_tms,
  inout pin16,
  inout pin17,
  inout pin18_cs,
  inout pin19_sclk,
  inout pin20_miso,
  inout pin21,
  inout pin22
);

  // left side of board
  assign pin1 = 1'bz;
  assign pin2 = 1'bz;
  assign pin3_sn = 1'bz;
  assign pin4_mosi = 1'bz;
  assign pin5 = 1'bz;
  assign pin6 = 1'bz;
  assign pin7_done = 1'bz;
  assign pin8_pgmn = 1'bz;
  //assign pin9_jtgnb = 1'bz;
  //assign pin10_sda = 1'bz;
  //assign pin11_scl = 1'bz;

  // right side of board
  //assign pin12_tdo = 1'bz;
  //assign pin13_tdi = 1'bz;
  //assign pin14_tck = 1'bz;
  //assign pin15_tms = 1'bz;
  assign pin16 = 1'bz;
  assign pin17 = 1'bz;
  assign pin18_cs = 1'bz;
  assign pin19_sclk = 1'bz;
  assign pin20_miso = 1'bz;
  assign pin21 = 1'bz;
  assign pin22 = 1'bz;

  wire clk;

  OSCH #(
	  .NOM_FREQ("2.08")
  ) internal_oscillator_inst (
	  .STDBY(1'b0),
	  .OSC(clk)
  );

  reg[23:0] led_timer;

  always @(posedge clk) begin
	  led_timer <= led_timer + 1;
  end

  assign pin9_jtgnb = led_timer[23];
  assign pin10_sda = led_timer[22];
  assign pin11_scl = led_timer[21];

endmodule
module TinyFPGA_A2 (
  input pin21,
  output pin22
);

 assign pin22 =! pin21;

endmodule
module TinyFPGA_A2 (
	input [3:0] DIN,
	output SO,
	output CLK
);

	wire clk;

	reg [3:0] din; // 4-bit wide input port
	reg [2:0] counter; // counts to 8
	reg out; // out data
	reg outclk; // shows counter edge

	OSCH #( // setup the oscillator
		.NOM_FREQ("2.08")
	) internal_oscillator_inst (
		.STDBY(1'b0),
		.OSC(clk) // oscillator bangs the clk wire back-and-forth
	);

	always @(posedge clk) begin // every time the clk wire has a positive edge, do:
		counter <= counter + 1; // increment the counter
		if(counter == 0) begin // on a new cycle,
			din = DIN; // read data in from port
			outclk = 1'b1; // expose counter clock
			end
		else begin
			outclk = 1'b0; // counter clock low
			end

		out <= din[counter]; // set the out wire to be equal to the i-th element in the data in port
	end

	assign SO = out; // serial output is the out value
	assign CLK = outclk; // CLK output is the outclk value

endmodule
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;

//LOCATE COMP "pin1" SITE "13" ;
//LOCATE COMP "pin2" SITE "14" ;

LOCATE COMP "CLK" SITE "13" ; // pin1
LOCATE COMP "SO" SITE "14" ; // pin2

LOCATE COMP "pin3_sn" SITE "16" ;
LOCATE COMP "pin4_mosi" SITE "17" ;
LOCATE COMP "pin5" SITE "20" ;
LOCATE COMP "pin6" SITE "21" ;
LOCATE COMP "pin7_done" SITE "23" ;
LOCATE COMP "pin8_pgmn" SITE "25" ;
LOCATE COMP "pin9_jtgnb" SITE "26" ;
LOCATE COMP "pin10_sda" SITE "27" ;
LOCATE COMP "pin11_scl" SITE "28" ;

//LOCATE COMP "pin16" SITE "4" ;
//LOCATE COMP "pin17" SITE "5" ;
//LOCATE COMP "pin18_cs" SITE "8" ;
//LOCATE COMP "pin19_sclk" SITE "9" ;
//LOCATE COMP "pin20_miso" SITE "10" ;

LOCATE COMP "DIN[0]" SITE "4" ; // pin16
LOCATE COMP "DIN[1]" SITE "5" ; // pin17
LOCATE COMP "DIN[2]" SITE "8" ; // pin18
LOCATE COMP "DIN[3]" SITE "9" ; // pin19
//LOCATE COMP "DIN[4]" SITE "10" ; // pin 20

LOCATE COMP "pin21" SITE "11" ;
LOCATE COMP "pin22" SITE "12" ;

int main (void)
{
  sysclk_init();
  irq_initialize_vectors();
  cpu_irq_enable();
  board_init();

  usb_init();

  PORTD.DIRSET = PIN3_bm | PIN4_bm; // set output (leds)
  PORTD.DIRCLR = PIN5_bm; // set input (button)

  PORTA.DIRSET = PIN0_bm | PIN1_bm | PIN2_bm | PIN3_bm | PIN4_bm | PIN5_bm | PIN6_bm | PIN7_bm;

  uint8_t counter = 0;
  while(1){
    if(counter > 255){
      counter = 0;
    }
    PORTA.OUTSET = counter;
    PORTA.OUTCLR = ~counter;
    counter ++;
    delay_ms(15);
  }
}
module TinyFPGA_A2 (
  input [7:0] DIN, // parallel data in port
  output DOUT, // serial data out
  output CLKOUT, // literal clock
  output TRGOUT // starts frame
);

  wire clk;

  reg [7:0] din; // 8-bit wide input port
  reg [2:0] counter; // counts to 8
  reg dout; // out data
  reg clkout; // shows counter edge

  OSCH #( // setup the oscillator
    .NOM_FREQ("2.08") // 2.08, 10.23, 19.00, 44.33, 66.50, 88.67, 133
  ) oscillator_instance (
    .STDBY(1'b0),
    .OSC(clk) // oscillator bangs the clk wire back-and-forth
  );

  always @(posedge clk) begin // every time the clk wire has a positive edge, do:
    dout <= din[counter-1]; // set the out wire to be equal to the i-th element in the data in port
    if(counter == 7) begin // on a new cycle,
      din <= DIN; // read data in from port
      clkout <= 1'b1; // expose counter clock
      end
    else begin
      clkout <= 1'b0; // counter clock low
      end
    counter <= counter + 1; // increment the counter
    end

  assign DOUT = dout; // serial output is the out value
  assign CLKOUT = clk; // CLK output is the outclk value
  assign TRGOUT = clkout;

endmodule
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;

// pins 12 -> 15 are JTAG

//LOCATE COMP "pin1" SITE "13" ;
//LOCATE COMP "pin2" SITE "14" ;

LOCATE COMP "DIN[0]" SITE "13" ; // pin1 (lsb)
LOCATE COMP "DIN[1]" SITE "14" ; // pin2
LOCATE COMP "DIN[2]" SITE "16" ; // pin3
LOCATE COMP "DIN[3]" SITE "17" ; // pin4
LOCATE COMP "DIN[4]" SITE "20" ; // pin5
LOCATE COMP "DIN[5]" SITE "21" ; // pin6
LOCATE COMP "DIN[6]" SITE "23" ; // pin7
LOCATE COMP "DIN[7]" SITE "25" ; // pin8 (msb)

LOCATE COMP "NDIN" SITE "27" ; // pin10 (new data in)
LOCATE COMP "NDREADY" SITE "28" ; // pin11 (ready for new data)

LOCATE COMP "DOUT" SITE "12" ; // pin22
LOCATE COMP "TRGOUT" SITE "11" ; // pin21
LOCATE COMP "CLKOUT" SITE "10" ; // pin20
module TinyFPGA_A2 (
  output [7:0] DOUT, // parallel data in port
  input DIN, // serial data out
  input CLKIN, // literal clock
  input TRGIN // starts frame
);

  reg dhold;
  reg [7:0] dout; // 8-bit wide input port
  reg [3:0] counter; // counts to 8

  always @(posedge CLKIN) begin // every time the clk wire has a positive edge, do:
    if(TRGIN) begin // signals new block
      counter <= 0;
      end
    dout[counter] <= DIN; // shift in new data
    counter <= counter + 1;
    end

  assign DOUT = dout; // serial output is the out value

endmodule
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;

// pins 12 -> 15 are JTAG

//LOCATE COMP "pin1" SITE "13" ;
//LOCATE COMP "pin2" SITE "14" ;

LOCATE COMP "DOUT[0]" SITE "13" ; // pin1 (lsb)
LOCATE COMP "DOUT[1]" SITE "14" ; // pin2
LOCATE COMP "DOUT[2]" SITE "16" ; // pin3
LOCATE COMP "DOUT[3]" SITE "17" ; // pin4
LOCATE COMP "DOUT[4]" SITE "20" ; // pin5
LOCATE COMP "DOUT[5]" SITE "21" ; // pin6
LOCATE COMP "DOUT[6]" SITE "23" ; // pin7
LOCATE COMP "DOUT[7]" SITE "25" ; // pin8 (msb)

LOCATE COMP "NDIN" SITE "27" ; // pin10 (new data in)
LOCATE COMP "NDREADY" SITE "28" ; // pin11 (ready for new data)

LOCATE COMP "DIN" SITE "12" ; // pin22
LOCATE COMP "TRGIN" SITE "11" ; // pin21
LOCATE COMP "CLKIN" SITE "10" ; // pin20