diff --git a/FabFTDI-Attiny102.b#1 b/FabFTDI-Attiny102.b#1 index 64e22804c6b3f6c7584516a97d30337db9ad5ebc..c364a76ae5d02a9dfa5ff7adfd9a8fd12ab0d2e0 100755 --- a/FabFTDI-Attiny102.b#1 +++ b/FabFTDI-Attiny102.b#1 @@ -8,19 +8,19 @@ </settings> <grid distance="10" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="5" altunitdist="mil" altunit="mil"/> <layers> -<layer number="1" name="Top" color="4" fill="1" visible="no" active="yes"/> -<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="yes"/> <layer number="17" name="Pads" color="2" fill="1" visible="no" active="yes"/> <layer number="18" name="Vias" color="2" fill="1" visible="no" active="yes"/> <layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="yes"/> <layer number="20" name="Dimension" color="24" fill="1" visible="no" active="yes"/> -<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="yes"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/> <layer number="22" name="bPlace" color="7" fill="1" visible="no" active="yes"/> -<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="yes"/> +<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/> <layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="yes"/> <layer number="25" name="tNames" color="7" fill="1" visible="no" active="yes"/> <layer number="26" name="bNames" color="7" fill="1" visible="no" active="yes"/> -<layer number="27" name="tValues" color="7" fill="1" visible="no" active="yes"/> +<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/> <layer number="28" name="bValues" color="7" fill="1" visible="no" active="yes"/> <layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/> <layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/> @@ -209,7 +209,7 @@ chip</description> <smd name="2" x="1.422" y="0" dx="1.6" dy="1.803" layer="1"/> <smd name="1" x="-1.422" y="0" dx="1.6" dy="1.803" layer="1"/> <text x="-1.397" y="1.143" size="1.27" layer="25">>NAME</text> -<text x="-1.397" y="-2.413" size="1.27" layer="27">>VALUE</text> +<text x="-1.397" y="-1.143" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.6891" y1="-0.8763" x2="-0.9525" y2="0.8763" layer="51"/> <rectangle x1="0.9525" y1="-0.8763" x2="1.6891" y2="0.8763" layer="51"/> <rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/> @@ -272,7 +272,7 @@ chip</description> <smd name="CATHODE" x="-1.7" y="0" dx="1.6" dy="0.8" layer="1"/> <smd name="ANODE" x="1.7" y="0" dx="1.6" dy="0.8" layer="1"/> <text x="-1.905" y="1.905" size="1.27" layer="25">>NAME</text> -<text x="-1.905" y="-3.175" size="1.27" layer="27">>VALUE</text> +<text x="-1.905" y="-0.635" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.9558" y1="-0.3048" x2="-1.3716" y2="0.3048" layer="51" rot="R180"/> <rectangle x1="1.3716" y1="-0.3048" x2="1.9558" y2="0.3048" layer="51" rot="R180"/> <rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/> @@ -470,7 +470,7 @@ design rules under a new name.</description> <elements> <element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="32.258" y="14.097" rot="R270"/> <element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102" x="22.606" y="19.685"/> -<element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPISMD" x="8.89" y="20.828" rot="R180"/> +<element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPI" x="8.89" y="20.828" rot="R180"/> <element name="R1" library="fabPatil" package="1206" value="1K" x="10.16" y="14.097" rot="R180"/> <element name="R2" library="fabPatil" package="1206" value="499" x="16.51" y="13.843" rot="R90"/> <element name="U$2" library="fabPatil" package="USB-MICROB" value="FAB_USB" x="4.318" y="9.271" rot="R270"/> @@ -479,7 +479,7 @@ design rules under a new name.</description> <element name="R3" library="fabPatil" package="1206" value="499" x="20.574" y="10.033"/> <element name="R4" library="fabPatil" package="1206" value="499" x="20.701" y="12.954"/> <element name="C1" library="fabPatil" package="1206" value="0.1uF" x="26.162" y="7.239" rot="R180"/> -<element name="R5" library="fabPatil" package="1206" value="" x="20.701" y="7.239"/> +<element name="R5" library="fabPatil" package="1206" value="4.7K" x="20.701" y="7.239"/> </elements> <signals> <signal name="GND"> diff --git a/FabFTDI-Attiny102.b#3 b/FabFTDI-Attiny102.b#3 index ec30d7cd713fbe6ef0d898b658c9cc333f14ebb4..64e22804c6b3f6c7584516a97d30337db9ad5ebc 100755 --- a/FabFTDI-Attiny102.b#3 +++ b/FabFTDI-Attiny102.b#3 @@ -8,20 +8,20 @@ </settings> <grid distance="10" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="5" altunitdist="mil" altunit="mil"/> <layers> -<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="yes"/> <layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/> -<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/> -<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/> -<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/> -<layer number="20" name="Dimension" color="24" fill="1" visible="yes" active="yes"/> -<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/> -<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/> -<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/> -<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/> +<layer number="17" name="Pads" color="2" fill="1" visible="no" active="yes"/> +<layer number="18" name="Vias" color="2" fill="1" visible="no" active="yes"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="yes"/> +<layer number="20" name="Dimension" color="24" fill="1" visible="no" active="yes"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="yes"/> +<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="yes"/> +<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="yes"/> +<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="yes"/> <layer number="25" name="tNames" color="7" fill="1" visible="no" active="yes"/> <layer number="26" name="bNames" color="7" fill="1" visible="no" active="yes"/> -<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/> -<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/> +<layer number="27" name="tValues" color="7" fill="1" visible="no" active="yes"/> +<layer number="28" name="bValues" color="7" fill="1" visible="no" active="yes"/> <layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/> <layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/> <layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/> @@ -32,20 +32,20 @@ <layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/> <layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/> <layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/> -<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/> -<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/> -<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/> -<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/> -<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/> +<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="yes"/> +<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="yes"/> +<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="yes"/> +<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="yes"/> +<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/> <layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/> <layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/> <layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/> <layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/> -<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/> -<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/> +<layer number="48" name="Document" color="7" fill="1" visible="no" active="yes"/> +<layer number="49" name="Reference" color="7" fill="1" visible="no" active="yes"/> <layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/> -<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/> -<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/> +<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="yes"/> +<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="yes"/> <layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/> <layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/> <layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/> @@ -61,55 +61,55 @@ <layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/> <layer number="99" name="SpiceOrder" color="7" fill="1" visible="no" active="no"/> <layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/> -<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/> -<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/> -<layer number="103" name="tMap" color="7" fill="1" visible="yes" active="yes"/> -<layer number="104" name="Name" color="7" fill="1" visible="yes" active="yes"/> -<layer number="105" name="tPlate" color="7" fill="1" visible="yes" active="yes"/> -<layer number="106" name="bPlate" color="7" fill="1" visible="yes" active="yes"/> -<layer number="107" name="Crop" color="7" fill="1" visible="yes" active="yes"/> -<layer number="108" name="tplace-old" color="10" fill="1" visible="yes" active="yes"/> -<layer number="109" name="ref-old" color="11" fill="1" visible="yes" active="yes"/> -<layer number="110" name="fp0" color="7" fill="1" visible="yes" active="yes"/> -<layer number="111" name="LPC17xx" color="7" fill="1" visible="yes" active="yes"/> -<layer number="112" name="tSilk" color="7" fill="1" visible="yes" active="yes"/> -<layer number="113" name="IDFDebug" color="4" fill="1" visible="yes" active="yes"/> -<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/> -<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/> -<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/> -<layer number="123" name="tTestmark" color="7" fill="1" visible="yes" active="yes"/> -<layer number="124" name="bTestmark" color="7" fill="1" visible="yes" active="yes"/> -<layer number="125" name="_tNames" color="7" fill="1" visible="yes" active="yes"/> -<layer number="126" name="_bNames" color="7" fill="1" visible="yes" active="yes"/> -<layer number="127" name="_tValues" color="7" fill="1" visible="yes" active="yes"/> -<layer number="128" name="_bValues" color="7" fill="1" visible="yes" active="yes"/> -<layer number="131" name="tAdjust" color="7" fill="1" visible="yes" active="yes"/> -<layer number="132" name="bAdjust" color="7" fill="1" visible="yes" active="yes"/> -<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/> -<layer number="150" name="Notes" color="7" fill="1" visible="yes" active="yes"/> -<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/> -<layer number="152" name="_bDocu" color="7" fill="1" visible="yes" active="yes"/> +<layer number="101" name="Patch_Top" color="12" fill="4" visible="no" active="yes"/> +<layer number="102" name="Vscore" color="7" fill="1" visible="no" active="yes"/> +<layer number="103" name="tMap" color="7" fill="1" visible="no" active="yes"/> +<layer number="104" name="Name" color="7" fill="1" visible="no" active="yes"/> +<layer number="105" name="tPlate" color="7" fill="1" visible="no" active="yes"/> +<layer number="106" name="bPlate" color="7" fill="1" visible="no" active="yes"/> +<layer number="107" name="Crop" color="7" fill="1" visible="no" active="yes"/> +<layer number="108" name="tplace-old" color="10" fill="1" visible="no" active="yes"/> +<layer number="109" name="ref-old" color="11" fill="1" visible="no" active="yes"/> +<layer number="110" name="fp0" color="7" fill="1" visible="no" active="yes"/> +<layer number="111" name="LPC17xx" color="7" fill="1" visible="no" active="yes"/> +<layer number="112" name="tSilk" color="7" fill="1" visible="no" active="yes"/> +<layer number="113" name="IDFDebug" color="4" fill="1" visible="no" active="yes"/> +<layer number="116" name="Patch_BOT" color="9" fill="4" visible="no" active="yes"/> +<layer number="121" name="_tsilk" color="7" fill="1" visible="no" active="yes"/> +<layer number="122" name="_bsilk" color="7" fill="1" visible="no" active="yes"/> +<layer number="123" name="tTestmark" color="7" fill="1" visible="no" active="yes"/> +<layer number="124" name="bTestmark" color="7" fill="1" visible="no" active="yes"/> +<layer number="125" name="_tNames" color="7" fill="1" visible="no" active="yes"/> +<layer number="126" name="_bNames" color="7" fill="1" visible="no" active="yes"/> +<layer number="127" name="_tValues" color="7" fill="1" visible="no" active="yes"/> +<layer number="128" name="_bValues" color="7" fill="1" visible="no" active="yes"/> +<layer number="131" name="tAdjust" color="7" fill="1" visible="no" active="yes"/> +<layer number="132" name="bAdjust" color="7" fill="1" visible="no" active="yes"/> +<layer number="144" name="Drill_legend" color="7" fill="1" visible="no" active="yes"/> +<layer number="150" name="Notes" color="7" fill="1" visible="no" active="yes"/> +<layer number="151" name="HeatSink" color="7" fill="1" visible="no" active="yes"/> +<layer number="152" name="_bDocu" color="7" fill="1" visible="no" active="yes"/> <layer number="153" name="FabDoc1" color="6" fill="1" visible="no" active="no"/> <layer number="154" name="FabDoc2" color="2" fill="1" visible="no" active="no"/> <layer number="155" name="FabDoc3" color="7" fill="15" visible="no" active="no"/> -<layer number="199" name="Contour" color="7" fill="1" visible="yes" active="yes"/> -<layer number="200" name="200bmp" color="1" fill="10" visible="yes" active="yes"/> -<layer number="201" name="201bmp" color="2" fill="10" visible="yes" active="yes"/> -<layer number="202" name="202bmp" color="3" fill="10" visible="yes" active="yes"/> -<layer number="203" name="203bmp" color="4" fill="10" visible="yes" active="yes"/> -<layer number="204" name="204bmp" color="5" fill="10" visible="yes" active="yes"/> -<layer number="205" name="205bmp" color="6" fill="10" visible="yes" active="yes"/> -<layer number="206" name="206bmp" color="7" fill="10" visible="yes" active="yes"/> -<layer number="207" name="207bmp" color="8" fill="10" visible="yes" active="yes"/> -<layer number="208" name="208bmp" color="9" fill="10" visible="yes" active="yes"/> -<layer number="209" name="209bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="210" name="210bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="211" name="211bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="212" name="212bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="213" name="213bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="214" name="214bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="215" name="215bmp" color="7" fill="1" visible="yes" active="yes"/> -<layer number="216" name="216bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="199" name="Contour" color="7" fill="1" visible="no" active="yes"/> +<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="yes"/> +<layer number="201" name="201bmp" color="2" fill="10" visible="no" active="yes"/> +<layer number="202" name="202bmp" color="3" fill="10" visible="no" active="yes"/> +<layer number="203" name="203bmp" color="4" fill="10" visible="no" active="yes"/> +<layer number="204" name="204bmp" color="5" fill="10" visible="no" active="yes"/> +<layer number="205" name="205bmp" color="6" fill="10" visible="no" active="yes"/> +<layer number="206" name="206bmp" color="7" fill="10" visible="no" active="yes"/> +<layer number="207" name="207bmp" color="8" fill="10" visible="no" active="yes"/> +<layer number="208" name="208bmp" color="9" fill="10" visible="no" active="yes"/> +<layer number="209" name="209bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="210" name="210bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="211" name="211bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="212" name="212bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="213" name="213bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="214" name="214bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="215" name="215bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="216" name="216bmp" color="7" fill="1" visible="no" active="yes"/> <layer number="217" name="217bmp" color="18" fill="1" visible="no" active="no"/> <layer number="218" name="218bmp" color="19" fill="1" visible="no" active="no"/> <layer number="219" name="219bmp" color="20" fill="1" visible="no" active="no"/> @@ -118,18 +118,18 @@ <layer number="222" name="222bmp" color="23" fill="1" visible="no" active="no"/> <layer number="223" name="223bmp" color="24" fill="1" visible="no" active="no"/> <layer number="224" name="224bmp" color="25" fill="1" visible="no" active="no"/> -<layer number="248" name="Housing" color="7" fill="1" visible="yes" active="yes"/> -<layer number="249" name="Edge" color="7" fill="1" visible="yes" active="yes"/> +<layer number="248" name="Housing" color="7" fill="1" visible="no" active="yes"/> +<layer number="249" name="Edge" color="7" fill="1" visible="no" active="yes"/> <layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/> <layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/> -<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/> +<layer number="254" name="cooling" color="7" fill="1" visible="no" active="yes"/> </layers> <board> <plain> -<wire x1="0" y1="0" x2="39.548" y2="0" width="0" layer="20"/> -<wire x1="39.548" y1="0" x2="39.548" y2="28.692" width="0" layer="20"/> -<wire x1="39.548" y1="28.692" x2="0" y2="28.692" width="0" layer="20"/> -<wire x1="0" y1="28.692" x2="0" y2="0" width="0" layer="20"/> +<wire x1="1.27" y1="1.524" x2="38.278" y2="1.27" width="0" layer="20"/> +<wire x1="38.278" y1="1.27" x2="38.278" y2="27.93" width="0" layer="20"/> +<wire x1="38.278" y1="27.93" x2="1.27" y2="27.93" width="0" layer="20"/> +<wire x1="1.27" y1="27.93" x2="1.27" y2="1.524" width="0" layer="20"/> </plain> <libraries> <library name="fabPatil"> diff --git a/FabFTDI-Attiny102.b#4 b/FabFTDI-Attiny102.b#4 index b6b62239b0916c277a7f5b96fa473d71428b70cc..ec30d7cd713fbe6ef0d898b658c9cc333f14ebb4 100755 --- a/FabFTDI-Attiny102.b#4 +++ b/FabFTDI-Attiny102.b#4 @@ -126,10 +126,10 @@ </layers> <board> <plain> -<wire x1="0" y1="0" x2="37.262" y2="0" width="0" layer="20"/> -<wire x1="37.262" y1="0" x2="37.262" y2="25.898" width="0" layer="20"/> -<wire x1="37.262" y1="25.898" x2="0" y2="25.898" width="0" layer="20"/> -<wire x1="0" y1="25.898" x2="0" y2="0" width="0" layer="20"/> +<wire x1="0" y1="0" x2="39.548" y2="0" width="0" layer="20"/> +<wire x1="39.548" y1="0" x2="39.548" y2="28.692" width="0" layer="20"/> +<wire x1="39.548" y1="28.692" x2="0" y2="28.692" width="0" layer="20"/> +<wire x1="0" y1="28.692" x2="0" y2="0" width="0" layer="20"/> </plain> <libraries> <library name="fabPatil"> @@ -468,18 +468,18 @@ design rules under a new name.</description> </pass> </autorouter> <elements> -<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="31.242" y="12.065" rot="R270"/> -<element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102" x="21.59" y="17.653"/> -<element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPISMD" x="7.874" y="18.796" rot="R180"/> -<element name="R1" library="fabPatil" package="1206" value="1K" x="9.144" y="12.065" rot="R180"/> -<element name="R2" library="fabPatil" package="1206" value="499" x="15.494" y="11.811" rot="R90"/> -<element name="U$2" library="fabPatil" package="USB-MICROB" value="FAB_USB" x="3.302" y="7.239" rot="R270"/> -<element name="D1" library="fabPatil" package="SOD123" value="3.3V" x="12.7" y="7.239" rot="R270"/> -<element name="D2" library="fabPatil" package="SOD123" value="3.3V" x="15.367" y="5.588" rot="R270"/> -<element name="R3" library="fabPatil" package="1206" value="499" x="19.558" y="8.001"/> -<element name="R4" library="fabPatil" package="1206" value="499" x="19.685" y="10.922"/> -<element name="C1" library="fabPatil" package="1206" value="0.1uF" x="25.146" y="5.207" rot="R180"/> -<element name="R5" library="fabPatil" package="1206" value="" x="19.685" y="5.207"/> +<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="32.258" y="14.097" rot="R270"/> +<element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102" x="22.606" y="19.685"/> +<element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPISMD" x="8.89" y="20.828" rot="R180"/> +<element name="R1" library="fabPatil" package="1206" value="1K" x="10.16" y="14.097" rot="R180"/> +<element name="R2" library="fabPatil" package="1206" value="499" x="16.51" y="13.843" rot="R90"/> +<element name="U$2" library="fabPatil" package="USB-MICROB" value="FAB_USB" x="4.318" y="9.271" rot="R270"/> +<element name="D1" library="fabPatil" package="SOD123" value="3.3V" x="13.716" y="9.271" rot="R270"/> +<element name="D2" library="fabPatil" package="SOD123" value="3.3V" x="16.383" y="7.62" rot="R270"/> +<element name="R3" library="fabPatil" package="1206" value="499" x="20.574" y="10.033"/> +<element name="R4" library="fabPatil" package="1206" value="499" x="20.701" y="12.954"/> +<element name="C1" library="fabPatil" package="1206" value="0.1uF" x="26.162" y="7.239" rot="R180"/> +<element name="R5" library="fabPatil" package="1206" value="" x="20.701" y="7.239"/> </elements> <signals> <signal name="GND"> @@ -490,48 +490,48 @@ design rules under a new name.</description> <contactref element="C1" pad="1"/> <contactref element="JP1" pad="6"/> <contactref element="IC1" pad="8"/> -<wire x1="12.7" y1="3.888" x2="15.367" y2="3.888" width="0.4064" layer="1"/> -<wire x1="12.7" y1="3.888" x2="12.7" y2="5.539" width="0.4064" layer="1"/> -<wire x1="12.7" y1="5.539" x2="12.3" y2="5.939" width="0.3556" layer="1"/> -<wire x1="12.3" y1="5.939" x2="5.952" y2="5.939" width="0.3556" layer="1"/> -<wire x1="19.685" y1="22.352" x2="19.685" y2="20.807" width="0.3556" layer="1"/> -<wire x1="19.685" y1="22.352" x2="19.685" y2="22.86" width="0.3556" layer="1"/> -<wire x1="19.685" y1="22.86" x2="4.826" y2="22.86" width="0.3556" layer="1"/> -<wire x1="4.826" y1="22.86" x2="4.826" y2="21.336" width="0.3556" layer="1"/> -<wire x1="4.826" y1="21.336" x2="4.954" y2="21.336" width="0.3556" layer="1"/> -<wire x1="27.076" y1="5.715" x2="26.568" y2="5.207" width="0.4064" layer="1"/> -<wire x1="19.685" y1="23.876" x2="19.685" y2="22.352" width="0.4064" layer="1"/> -<wire x1="26.568" y1="5.207" x2="26.67" y2="5.207" width="0.4064" layer="1"/> -<wire x1="26.568" y1="5.715" x2="29.892" y2="5.715" width="0.4064" layer="1"/> -<wire x1="26.568" y1="5.715" x2="26.568" y2="5.207" width="0.4064" layer="1"/> -<wire x1="29.892" y1="5.715" x2="33.274" y2="5.715" width="0.4064" layer="1"/> -<wire x1="33.274" y1="5.715" x2="33.274" y2="19.812" width="0.4064" layer="1"/> -<wire x1="33.274" y1="19.812" x2="28.448" y2="19.812" width="0.4064" layer="1"/> -<wire x1="28.448" y1="19.812" x2="24.638" y2="23.876" width="0.4064" layer="1"/> -<wire x1="24.638" y1="23.876" x2="19.685" y2="23.876" width="0.4064" layer="1"/> -<wire x1="26.568" y1="5.207" x2="26.568" y2="4.216" width="0.4064" layer="1"/> -<wire x1="26.568" y1="4.216" x2="24.384" y2="2.032" width="0.4064" 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y1="23.368" x2="5.97" y2="23.368" width="0.3556" layer="1"/> +<wire x1="28.092" y1="7.747" x2="27.584" y2="7.239" width="0.4064" layer="1"/> +<wire x1="20.701" y1="25.908" x2="20.701" y2="24.384" width="0.4064" layer="1"/> +<wire x1="27.584" y1="7.239" x2="27.686" y2="7.239" width="0.4064" layer="1"/> +<wire x1="27.584" y1="7.747" x2="30.908" y2="7.747" width="0.4064" layer="1"/> +<wire x1="27.584" y1="7.747" x2="27.584" y2="7.239" width="0.4064" layer="1"/> +<wire x1="30.908" y1="7.747" x2="34.29" y2="7.747" width="0.4064" layer="1"/> +<wire x1="34.29" y1="7.747" x2="34.29" y2="21.844" width="0.4064" layer="1"/> +<wire x1="34.29" y1="21.844" x2="29.464" y2="21.844" width="0.4064" layer="1"/> +<wire x1="29.464" y1="21.844" x2="25.654" y2="25.908" width="0.4064" layer="1"/> +<wire x1="25.654" y1="25.908" x2="20.701" y2="25.908" width="0.4064" layer="1"/> +<wire x1="27.584" y1="7.239" x2="27.584" y2="6.248" width="0.4064" layer="1"/> +<wire x1="27.584" y1="6.248" x2="25.4" y2="4.064" width="0.4064" layer="1"/> +<wire x1="16.51" y1="4.064" x2="25.4" y2="4.064" width="0.4064" layer="1"/> +<wire x1="16.51" y1="4.064" x2="16.383" y2="4.064" width="0.4064" layer="1"/> +<wire x1="16.383" y1="5.92" x2="16.383" y2="4.191" width="0.4064" layer="1"/> +<wire x1="16.383" y1="4.191" x2="16.51" y2="4.064" width="0.4064" layer="1"/> </signal> <signal name="N$2"> <contactref element="IC1" pad="7"/> <contactref element="JP1" pad="2"/> -<wire x1="20.955" y1="22.86" x2="20.955" y2="20.807" width="0.4064" layer="1"/> -<wire x1="23.876" y1="22.86" x2="20.955" y2="22.86" width="0.4064" layer="1"/> -<wire x1="29.892" y1="15.875" x2="27.432" y2="15.875" width="0.4064" layer="1"/> -<wire x1="27.432" y1="15.875" x2="27.432" y2="19.304" width="0.4064" layer="1"/> -<wire x1="27.432" y1="19.304" x2="23.876" y2="22.86" width="0.4064" layer="1"/> +<wire x1="21.971" y1="24.892" x2="21.971" y2="22.839" width="0.4064" layer="1"/> +<wire x1="24.892" y1="24.892" x2="21.971" y2="24.892" width="0.4064" layer="1"/> +<wire x1="30.908" y1="17.907" x2="28.448" y2="17.907" width="0.4064" layer="1"/> +<wire x1="28.448" y1="17.907" x2="28.448" y2="21.336" width="0.4064" layer="1"/> +<wire x1="28.448" y1="21.336" x2="24.892" y2="24.892" width="0.4064" layer="1"/> </signal> <signal name="N$3"> <contactref element="IC1" pad="6"/> <contactref element="JP1" pad="3"/> -<wire x1="25.4" y1="13.335" x2="29.892" y2="13.335" width="0.3556" layer="1"/> -<wire x1="22.225" y1="20.807" x2="22.225" y2="19.431" width="0.3556" layer="1"/> -<wire x1="22.225" y1="19.431" x2="25.4" y2="16.256" width="0.3556" layer="1"/> -<wire x1="25.4" y1="16.256" x2="25.4" y2="13.335" width="0.3556" layer="1"/> +<wire x1="26.416" y1="15.367" x2="30.908" y2="15.367" width="0.3556" layer="1"/> +<wire x1="23.241" y1="22.839" x2="23.241" y2="21.463" width="0.3556" layer="1"/> +<wire x1="23.241" y1="21.463" x2="26.416" y2="18.288" width="0.3556" layer="1"/> +<wire x1="26.416" y1="18.288" x2="26.416" y2="15.367" width="0.3556" layer="1"/> </signal> <signal name="VCC"> <contactref element="U$2" pad="VBUS"/> @@ -539,125 +539,124 @@ design rules under a new name.</description> <contactref element="U$1" pad="2"/> <contactref element="R5" pad="1"/> <contactref element="IC1" pad="1"/> -<wire x1="7.722" y1="12.065" x2="7.722" y2="8.539" width="0.3556" layer="1"/> -<wire x1="7.722" y1="8.539" x2="5.952" y2="8.539" width="0.3556" layer="1"/> -<wire x1="7.722" y1="12.065" x2="4.954" y2="14.833" width="0.3556" layer="1"/> -<wire x1="4.954" y1="14.833" x2="4.954" y2="16.256" width="0.3556" layer="1"/> -<wire x1="19.685" y1="15.24" x2="19.685" y2="14.499" width="0.3556" layer="1"/> -<wire x1="19.685" y1="15.24" x2="14.478" y2="15.24" width="0.3556" layer="1"/> -<wire x1="14.478" y1="15.24" x2="12.954" y2="13.716" width="0.3556" layer="1"/> -<wire x1="9.373" y1="13.716" x2="7.722" y2="12.065" width="0.3556" layer="1"/> -<wire x1="12.954" y1="13.716" x2="9.373" y2="13.716" width="0.3556" layer="1"/> -<wire x1="19.685" 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layer="1"/> +<wire x1="16.51" y1="12.421" x2="16.51" y2="12.446" width="0.3556" layer="1"/> +<wire x1="6.968" y1="9.921" x2="12.461" y2="9.921" width="0.3556" layer="1"/> +<wire x1="12.461" y1="9.921" x2="13.716" y2="11.176" width="0.3556" layer="1"/> +<wire x1="19.279" y1="12.954" x2="18.746" y2="12.421" width="0.3556" layer="1"/> +<wire x1="16.764" y1="12.421" x2="18.746" y2="12.421" width="0.3556" layer="1"/> +<wire x1="16.764" y1="12.421" x2="16.51" y2="12.421" width="0.3556" layer="1"/> +<wire x1="13.716" y1="10.971" x2="15.166" y2="12.421" width="0.4064" layer="1"/> +<wire x1="15.166" y1="12.421" x2="16.764" y2="12.421" width="0.4064" layer="1"/> </signal> <signal name="DELTE"> <contactref element="U$2" pad="D+"/> <contactref element="D2" pad="CATHODE"/> <contactref element="R3" pad="1"/> -<wire x1="15.24" y1="7.239" x2="5.952" y2="7.239" width="0.3556" layer="1"/> -<wire x1="15.24" y1="7.239" x2="15.318" y2="7.239" width="0.3556" layer="1"/> -<wire x1="15.318" y1="7.239" x2="15.367" y2="7.288" width="0.4064" layer="1" curve="90"/> -<wire x1="18.136" y1="8.001" x2="15.24" y2="8.001" width="0.3556" layer="1"/> -<wire x1="15.24" y1="8.001" x2="15.24" y2="7.239" width="0.3556" layer="1"/> +<wire x1="16.256" y1="9.271" x2="6.968" y2="9.271" width="0.3556" layer="1"/> +<wire x1="16.256" y1="9.271" x2="16.334" y2="9.271" width="0.3556" layer="1"/> +<wire x1="16.334" y1="9.271" x2="16.383" y2="9.32" width="0.4064" layer="1" curve="90"/> +<wire x1="19.152" y1="10.033" x2="16.256" y2="10.033" width="0.3556" layer="1"/> +<wire x1="16.256" y1="10.033" x2="16.256" y2="9.271" width="0.3556" layer="1"/> </signal> <signal name="N$1"> <contactref element="R2" pad="2"/> <contactref element="R1" pad="1"/> -<wire x1="15.494" y1="13.233" x2="14.326" y2="12.065" width="0.4064" layer="1"/> -<wire x1="14.326" y1="12.065" x2="10.566" y2="12.065" width="0.4064" layer="1"/> +<wire x1="16.51" y1="15.265" x2="15.342" y2="14.097" width="0.4064" layer="1"/> +<wire x1="15.342" y1="14.097" x2="11.582" y2="14.097" width="0.4064" layer="1"/> </signal> <signal name="N$4"> <contactref element="R3" pad="2"/> <contactref element="IC1" pad="3"/> <contactref element="U$1" pad="1"/> -<wire x1="10.414" y1="17.272" x2="10.414" y2="16.256" width="0.3556" layer="1"/> -<wire x1="22.86" y1="8.001" x2="20.98" y2="8.001" width="0.4064" layer="1"/> -<wire x1="22.215" y1="16.139" x2="22.215" y2="14.499" width="0.3556" layer="1"/> -<wire x1="22.215" y1="16.139" x2="21.082" y2="17.272" width="0.3556" layer="1"/> -<wire x1="21.082" y1="17.272" x2="10.414" y2="17.272" width="0.3556" layer="1"/> -<wire x1="22.215" y1="14.499" x2="22.215" y2="12.837" width="0.4064" layer="1"/> -<wire x1="22.215" y1="12.837" x2="22.86" y2="12.192" width="0.4064" layer="1"/> -<wire x1="22.86" y1="12.192" x2="22.86" y2="8.001" width="0.4064" layer="1"/> +<wire x1="11.43" y1="19.304" x2="11.43" y2="18.288" width="0.3556" layer="1"/> +<wire x1="23.876" y1="10.033" x2="21.996" y2="10.033" width="0.4064" layer="1"/> +<wire x1="23.231" y1="18.171" x2="23.231" y2="16.531" width="0.3556" layer="1"/> +<wire x1="23.231" y1="18.171" x2="22.098" y2="19.304" width="0.3556" layer="1"/> +<wire x1="22.098" y1="19.304" x2="11.43" y2="19.304" width="0.3556" layer="1"/> +<wire x1="23.231" y1="16.531" x2="23.231" y2="14.869" width="0.4064" layer="1"/> +<wire x1="23.231" y1="14.869" x2="23.876" y2="14.224" width="0.4064" layer="1"/> +<wire x1="23.876" y1="14.224" x2="23.876" y2="10.033" width="0.4064" layer="1"/> </signal> <signal name="N$12"> <contactref element="R4" pad="2"/> <contactref element="IC1" pad="2"/> <contactref element="U$1" pad="3"/> -<wire x1="7.874" y1="14.732" x2="7.874" y2="18.796" width="0.3556" layer="1"/> -<wire x1="7.874" y1="18.796" x2="10.414" y2="18.796" width="0.3556" layer="1"/> -<wire x1="13.208" y1="16.002" x2="11.938" y2="14.732" width="0.3556" layer="1"/> -<wire x1="11.938" y1="14.732" x2="7.874" y2="14.732" width="0.3556" layer="1"/> -<wire x1="21.107" y1="10.922" x2="20.945" y2="10.922" width="0.3556" layer="1"/> -<wire x1="20.945" y1="10.922" x2="20.945" y2="14.499" width="0.3556" layer="1"/> -<wire x1="20.945" y1="14.499" x2="20.945" y2="15.631" width="0.3556" layer="1"/> -<wire x1="20.945" y1="15.631" x2="20.32" y2="16.256" width="0.3556" layer="1"/> -<wire x1="20.32" y1="16.256" x2="13.462" y2="16.256" width="0.3556" layer="1"/> -<wire x1="13.462" y1="16.256" x2="13.208" y2="16.002" width="0.3556" layer="1"/> +<wire x1="8.89" y1="16.764" x2="8.89" y2="20.828" width="0.3556" layer="1"/> +<wire x1="8.89" y1="20.828" x2="11.43" y2="20.828" width="0.3556" layer="1"/> +<wire x1="14.478" y1="18.288" x2="12.954" y2="16.764" width="0.3556" layer="1"/> +<wire x1="12.954" y1="16.764" x2="8.89" y2="16.764" width="0.3556" layer="1"/> +<wire x1="22.123" y1="12.954" x2="21.961" y2="12.954" width="0.3556" layer="1"/> +<wire x1="21.961" y1="12.954" x2="21.961" y2="16.531" width="0.3556" layer="1"/> +<wire x1="21.961" y1="16.531" x2="21.961" y2="17.663" width="0.3556" layer="1"/> +<wire x1="21.961" y1="17.663" x2="21.336" y2="18.288" width="0.3556" layer="1"/> +<wire x1="21.336" y1="18.288" x2="14.478" y2="18.288" width="0.3556" layer="1"/> </signal> <signal name="N$5"> <contactref element="U$1" pad="5"/> <contactref element="IC1" pad="4"/> <contactref element="R5" pad="2"/> <contactref element="C1" pad="2"/> -<wire x1="16.51" y1="18.796" x2="16.51" y2="21.336" width="0.3556" layer="1"/> -<wire x1="16.51" y1="21.336" x2="10.414" y2="21.336" width="0.3556" layer="1"/> -<wire x1="21.107" y1="5.207" x2="23.724" y2="5.207" width="0.3556" layer="1"/> -<wire x1="23.724" y1="5.207" x2="23.876" y2="5.461" width="0.4064" layer="1"/> -<wire x1="23.876" y1="11.938" x2="23.876" y2="5.461" width="0.4064" layer="1"/> -<wire x1="23.876" y1="11.938" x2="23.876" y2="14.108" width="0.4064" layer="1"/> -<wire x1="23.485" y1="14.499" x2="23.485" y2="16.393" width="0.3556" layer="1"/> -<wire x1="23.485" y1="16.393" x2="21.082" y2="18.796" width="0.3556" layer="1"/> -<wire x1="21.082" y1="18.796" x2="16.51" y2="18.796" width="0.3556" layer="1"/> -<wire x1="23.876" y1="14.108" x2="23.485" y2="14.499" width="0.4064" layer="1"/> +<wire x1="17.526" y1="20.828" x2="17.526" y2="23.368" width="0.3556" layer="1"/> +<wire x1="17.526" y1="23.368" x2="11.43" y2="23.368" width="0.3556" layer="1"/> +<wire x1="22.123" y1="7.239" x2="24.74" y2="7.239" width="0.3556" layer="1"/> +<wire x1="24.74" y1="7.239" x2="24.892" y2="7.493" width="0.4064" layer="1"/> +<wire x1="24.892" y1="13.97" x2="24.892" y2="7.493" width="0.4064" layer="1"/> +<wire x1="24.892" y1="13.97" x2="24.892" y2="16.14" width="0.4064" layer="1"/> +<wire x1="24.501" y1="16.531" x2="24.501" y2="18.425" width="0.3556" layer="1"/> +<wire x1="24.501" y1="18.425" x2="22.098" y2="20.828" width="0.3556" layer="1"/> +<wire x1="22.098" y1="20.828" x2="17.526" y2="20.828" width="0.3556" layer="1"/> +<wire x1="24.892" y1="16.14" x2="24.501" y2="16.531" width="0.4064" layer="1"/> <contactref element="JP1" pad="5"/> -<wire x1="29.892" y1="8.255" x2="32.258" y2="8.255" width="0.4064" layer="1"/> -<wire x1="32.258" y1="8.255" x2="32.258" y2="11.938" width="0.4064" layer="1"/> -<wire x1="32.258" y1="11.938" x2="23.876" y2="11.938" width="0.4064" layer="1"/> +<wire x1="30.908" y1="10.287" x2="33.274" y2="10.287" width="0.4064" layer="1"/> +<wire x1="33.274" y1="10.287" x2="33.274" y2="13.97" width="0.4064" layer="1"/> +<wire x1="33.274" y1="13.97" x2="24.892" y2="13.97" width="0.4064" layer="1"/> </signal> <signal name="N$6"> <contactref element="JP1" pad="1"/> <contactref element="IC1" pad="5"/> -<wire x1="26.416" y1="17.886" x2="26.416" y2="14.732" width="0.4064" layer="1"/> -<wire x1="26.416" y1="14.732" x2="32.258" y2="14.732" width="0.4064" layer="1"/> -<wire x1="32.258" y1="14.732" x2="32.258" y2="17.272" width="0.4064" layer="1"/> -<wire x1="32.258" y1="17.272" x2="31.242" y2="18.288" width="0.4064" layer="1"/> -<wire x1="31.242" y1="18.288" x2="30.019" y2="18.288" width="0.4064" layer="1"/> -<wire x1="30.019" y1="18.288" x2="29.892" y2="18.415" width="0.4064" layer="1"/> -<wire x1="23.495" y1="20.807" x2="26.416" y2="17.886" width="0.4064" layer="1"/> +<wire x1="27.432" y1="19.918" x2="27.432" y2="16.764" width="0.4064" layer="1"/> +<wire x1="27.432" y1="16.764" x2="33.274" y2="16.764" width="0.4064" layer="1"/> +<wire x1="33.274" y1="16.764" x2="33.274" y2="19.304" width="0.4064" layer="1"/> +<wire x1="33.274" y1="19.304" x2="32.258" y2="20.32" width="0.4064" layer="1"/> +<wire x1="32.258" y1="20.32" x2="31.035" y2="20.32" width="0.4064" layer="1"/> +<wire x1="31.035" y1="20.32" x2="30.908" y2="20.447" width="0.4064" layer="1"/> +<wire x1="24.511" y1="22.839" x2="27.432" y2="19.918" width="0.4064" layer="1"/> </signal> <signal name="N$7"> <polygon width="0.4064" layer="16"> -<vertex x="27.178" y="0.508"/> -<vertex x="29.21" y="3.048"/> -<vertex x="36.576" y="3.048"/> -<vertex x="36.322" y="21.336"/> -<vertex x="29.21" y="21.336"/> -<vertex x="25.908" y="25.146"/> -<vertex x="1.016" y="25.146"/> -<vertex x="1.27" y="0.508"/> +<vertex x="27.686" y="2.286"/> +<vertex x="30.226" y="5.08"/> +<vertex x="37.592" y="5.08"/> +<vertex x="37.338" y="23.368"/> +<vertex x="30.226" y="23.368"/> +<vertex x="26.924" y="27.178"/> +<vertex x="2.032" y="27.178"/> +<vertex x="2.286" y="2.286"/> </polygon> </signal> </signals> diff --git a/FabFTDI-Attiny102.b#5 b/FabFTDI-Attiny102.b#5 index 0b1478cddcab4103631d51dde72f6d0e6b48454c..b6b62239b0916c277a7f5b96fa473d71428b70cc 100755 --- a/FabFTDI-Attiny102.b#5 +++ b/FabFTDI-Attiny102.b#5 @@ -126,10 +126,10 @@ </layers> <board> <plain> -<wire x1="0" y1="0" x2="100" y2="0" width="0" layer="20"/> -<wire x1="100" y1="0" x2="100" y2="80" width="0" layer="20"/> -<wire x1="100" y1="80" x2="0" y2="80" width="0" layer="20"/> -<wire x1="0" y1="80" x2="0" y2="0" width="0" layer="20"/> +<wire x1="0" y1="0" x2="37.262" y2="0" width="0" layer="20"/> +<wire x1="37.262" y1="0" x2="37.262" y2="25.898" width="0" layer="20"/> +<wire x1="37.262" y1="25.898" x2="0" y2="25.898" width="0" layer="20"/> +<wire x1="0" y1="25.898" x2="0" y2="0" width="0" layer="20"/> </plain> <libraries> <library name="fabPatil"> diff --git a/FabFTDI-Attiny102.b#7 b/FabFTDI-Attiny102.b#7 index fc763f927a31079abdb52becb6e007520aaecbb3..0b1478cddcab4103631d51dde72f6d0e6b48454c 100755 --- a/FabFTDI-Attiny102.b#7 +++ b/FabFTDI-Attiny102.b#7 @@ -469,7 +469,7 @@ design rules under a new name.</description> </autorouter> <elements> <element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="31.242" y="12.065" rot="R270"/> -<element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102/104" x="21.59" y="17.653"/> +<element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102" x="21.59" y="17.653"/> <element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPISMD" x="7.874" y="18.796" rot="R180"/> <element name="R1" library="fabPatil" package="1206" value="1K" x="9.144" y="12.065" rot="R180"/> <element name="R2" library="fabPatil" package="1206" value="499" x="15.494" y="11.811" rot="R90"/> diff --git a/FabFTDI-Attiny102.b#8 b/FabFTDI-Attiny102.b#8 index 0eafb26c524e26b633e6ab730ad5a289f0d8df14..fc763f927a31079abdb52becb6e007520aaecbb3 100755 --- a/FabFTDI-Attiny102.b#8 +++ b/FabFTDI-Attiny102.b#8 @@ -505,9 +505,9 @@ design rules under a new name.</description> <wire x1="26.568" y1="5.715" x2="29.892" y2="5.715" width="0.4064" layer="1"/> <wire x1="26.568" y1="5.715" x2="26.568" y2="5.207" width="0.4064" layer="1"/> <wire x1="29.892" y1="5.715" x2="33.274" y2="5.715" width="0.4064" layer="1"/> -<wire x1="33.274" y1="5.715" x2="33.274" y2="20.828" width="0.4064" layer="1"/> -<wire x1="33.274" y1="20.828" x2="27.686" y2="20.828" width="0.4064" layer="1"/> -<wire x1="27.686" y1="20.828" x2="24.638" y2="23.876" width="0.4064" layer="1"/> +<wire x1="33.274" y1="5.715" x2="33.274" y2="19.812" width="0.4064" layer="1"/> +<wire x1="33.274" y1="19.812" x2="28.448" y2="19.812" width="0.4064" layer="1"/> +<wire x1="28.448" y1="19.812" x2="24.638" y2="23.876" width="0.4064" layer="1"/> <wire x1="24.638" y1="23.876" x2="19.685" y2="23.876" width="0.4064" layer="1"/> <wire x1="26.568" y1="5.207" x2="26.568" y2="4.216" width="0.4064" layer="1"/> <wire x1="26.568" y1="4.216" x2="24.384" y2="2.032" width="0.4064" layer="1"/> @@ -519,12 +519,11 @@ design rules under a new name.</description> <signal name="N$2"> <contactref element="IC1" pad="7"/> <contactref element="JP1" pad="2"/> -<wire x1="32.258" y1="15.875" x2="29.892" y2="15.875" width="0.4064" layer="1"/> <wire x1="20.955" y1="22.86" x2="20.955" y2="20.807" width="0.4064" layer="1"/> -<wire x1="32.258" y1="19.812" x2="26.924" y2="19.812" width="0.4064" layer="1"/> -<wire x1="32.258" y1="19.812" x2="32.258" y2="15.875" width="0.4064" layer="1"/> <wire x1="23.876" y1="22.86" x2="20.955" y2="22.86" width="0.4064" layer="1"/> -<wire x1="26.924" y1="19.812" x2="23.876" y2="22.86" width="0.4064" layer="1"/> +<wire x1="29.892" y1="15.875" x2="27.432" y2="15.875" width="0.4064" layer="1"/> +<wire x1="27.432" y1="15.875" x2="27.432" y2="19.304" width="0.4064" layer="1"/> +<wire x1="27.432" y1="19.304" x2="23.876" y2="22.86" width="0.4064" layer="1"/> </signal> <signal name="N$3"> <contactref element="IC1" pad="6"/> @@ -641,8 +640,25 @@ design rules under a new name.</description> <signal name="N$6"> <contactref element="JP1" pad="1"/> <contactref element="IC1" pad="5"/> -<wire x1="29.892" y1="18.415" x2="25.887" y2="18.415" width="0.4064" layer="1"/> -<wire x1="25.887" y1="18.415" x2="23.495" y2="20.807" width="0.4064" layer="1"/> +<wire x1="26.416" y1="17.886" x2="26.416" y2="14.732" width="0.4064" layer="1"/> +<wire x1="26.416" y1="14.732" x2="32.258" y2="14.732" width="0.4064" layer="1"/> +<wire x1="32.258" y1="14.732" x2="32.258" y2="17.272" width="0.4064" layer="1"/> +<wire x1="32.258" y1="17.272" x2="31.242" y2="18.288" width="0.4064" layer="1"/> +<wire x1="31.242" y1="18.288" x2="30.019" y2="18.288" width="0.4064" layer="1"/> +<wire x1="30.019" y1="18.288" x2="29.892" y2="18.415" width="0.4064" layer="1"/> +<wire x1="23.495" y1="20.807" x2="26.416" y2="17.886" width="0.4064" layer="1"/> +</signal> +<signal name="N$7"> +<polygon width="0.4064" layer="16"> +<vertex x="27.178" y="0.508"/> +<vertex x="29.21" y="3.048"/> +<vertex x="36.576" y="3.048"/> +<vertex x="36.322" y="21.336"/> +<vertex x="29.21" y="21.336"/> +<vertex x="25.908" y="25.146"/> +<vertex x="1.016" y="25.146"/> +<vertex x="1.27" y="0.508"/> +</polygon> </signal> </signals> </board> diff --git a/FabFTDI-Attiny102.b#9 b/FabFTDI-Attiny102.b#9 index 57cdd45cf56a11f720e1b390b0f00af128608cd4..0eafb26c524e26b633e6ab730ad5a289f0d8df14 100755 --- a/FabFTDI-Attiny102.b#9 +++ b/FabFTDI-Attiny102.b#9 @@ -135,16 +135,16 @@ <library name="fabPatil"> <packages> <package name="1X06-SMD"> -<wire x1="7.62" y1="6.33" x2="-7.62" y2="6.33" width="0.127" layer="51"/> -<wire x1="-7.62" y1="6.33" x2="-7.62" y2="-1.25" width="0.127" layer="51"/> -<wire x1="-7.62" y1="-1.25" x2="7.62" y2="-1.25" width="0.127" layer="51"/> -<wire x1="7.62" y1="-1.25" x2="7.62" y2="6.33" width="0.127" layer="51"/> -<smd name="4" x="1.27" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="5" x="3.81" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="6" x="6.35" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="3" x="-1.27" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="2" x="-3.81" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="1" x="-6.35" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<wire x1="7.62" y1="5.06" x2="-7.62" y2="5.06" width="0.127" layer="51"/> +<wire x1="-7.62" y1="5.06" x2="-7.62" y2="-3.79" width="0.127" layer="51"/> +<wire x1="-7.62" y1="-3.79" x2="7.62" y2="-3.79" width="0.127" layer="51"/> +<wire x1="7.62" y1="-3.79" x2="7.62" y2="5.06" width="0.127" layer="51"/> +<smd name="4" x="1.27" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="5" x="3.81" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="6" x="6.35" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="3" x="-1.27" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="2" x="-3.81" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="1" x="-6.35" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> </package> <package name="SOIC8" urn="urn:adsk.eagle:footprint:4165/1" locally_modified="yes"> <description><B>Wide Plastic Gull Wing Small Outline Package</B></description> @@ -468,7 +468,7 @@ design rules under a new name.</description> </pass> </autorouter> <elements> -<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="29.972" y="12.065" rot="R270"/> +<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="31.242" y="12.065" rot="R270"/> <element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102/104" x="21.59" y="17.653"/> <element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPISMD" x="7.874" y="18.796" rot="R180"/> <element name="R1" library="fabPatil" package="1206" value="1K" x="9.144" y="12.065" rot="R180"/> @@ -502,11 +502,11 @@ design rules under a new name.</description> <wire x1="27.076" y1="5.715" x2="26.568" y2="5.207" width="0.4064" layer="1"/> <wire x1="19.685" y1="23.876" x2="19.685" y2="22.352" width="0.4064" layer="1"/> <wire x1="26.568" y1="5.207" x2="26.67" y2="5.207" width="0.4064" layer="1"/> -<wire x1="26.568" y1="5.715" x2="34.972" y2="5.715" width="0.4064" layer="1"/> +<wire x1="26.568" y1="5.715" x2="29.892" y2="5.715" width="0.4064" layer="1"/> <wire x1="26.568" y1="5.715" x2="26.568" y2="5.207" width="0.4064" layer="1"/> -<wire x1="34.972" y1="5.715" x2="38.354" y2="5.715" width="0.4064" layer="1"/> -<wire x1="38.354" y1="5.715" x2="38.354" y2="20.828" width="0.4064" layer="1"/> -<wire x1="38.354" y1="20.828" x2="27.686" y2="20.828" width="0.4064" layer="1"/> +<wire x1="29.892" y1="5.715" x2="33.274" y2="5.715" width="0.4064" layer="1"/> +<wire x1="33.274" y1="5.715" x2="33.274" y2="20.828" width="0.4064" layer="1"/> +<wire x1="33.274" y1="20.828" x2="27.686" y2="20.828" width="0.4064" layer="1"/> <wire x1="27.686" y1="20.828" x2="24.638" y2="23.876" width="0.4064" layer="1"/> <wire x1="24.638" y1="23.876" x2="19.685" y2="23.876" width="0.4064" layer="1"/> <wire x1="26.568" y1="5.207" x2="26.568" y2="4.216" width="0.4064" layer="1"/> @@ -519,17 +519,17 @@ design rules under a new name.</description> <signal name="N$2"> <contactref element="IC1" pad="7"/> <contactref element="JP1" pad="2"/> -<wire x1="37.338" y1="15.875" x2="34.972" y2="15.875" width="0.4064" layer="1"/> +<wire x1="32.258" y1="15.875" x2="29.892" y2="15.875" width="0.4064" layer="1"/> <wire x1="20.955" y1="22.86" x2="20.955" y2="20.807" width="0.4064" layer="1"/> -<wire x1="37.338" y1="19.812" x2="26.924" y2="19.812" width="0.4064" layer="1"/> -<wire x1="37.338" y1="19.812" x2="37.338" y2="15.875" width="0.4064" layer="1"/> +<wire x1="32.258" y1="19.812" x2="26.924" y2="19.812" width="0.4064" layer="1"/> +<wire x1="32.258" y1="19.812" x2="32.258" y2="15.875" width="0.4064" layer="1"/> <wire x1="23.876" y1="22.86" x2="20.955" y2="22.86" width="0.4064" layer="1"/> <wire x1="26.924" y1="19.812" x2="23.876" y2="22.86" width="0.4064" layer="1"/> </signal> <signal name="N$3"> <contactref element="IC1" pad="6"/> <contactref element="JP1" pad="3"/> -<wire x1="25.4" y1="13.335" x2="34.972" y2="13.335" width="0.3556" layer="1"/> +<wire x1="25.4" y1="13.335" x2="29.892" y2="13.335" width="0.3556" layer="1"/> <wire x1="22.225" y1="20.807" x2="22.225" y2="19.431" width="0.3556" layer="1"/> <wire x1="22.225" y1="19.431" x2="25.4" y2="16.256" width="0.3556" layer="1"/> <wire x1="25.4" y1="16.256" x2="25.4" y2="13.335" width="0.3556" layer="1"/> @@ -553,7 +553,7 @@ design rules under a new name.</description> <wire x1="19.685" y1="5.207" x2="18.263" y2="5.207" width="0.3556" layer="1"/> <wire x1="19.685" y1="5.207" x2="19.685" y2="3.175" width="0.3556" layer="1"/> <contactref element="JP1" pad="4"/> -<wire x1="25.146" y1="10.795" x2="34.972" y2="10.795" width="0.4064" layer="1"/> +<wire x1="25.146" y1="10.795" x2="29.892" y2="10.795" width="0.4064" layer="1"/> <wire x1="19.685" y1="3.175" x2="24.003" y2="3.175" width="0.4064" layer="1"/> <wire x1="24.003" y1="3.175" x2="25.146" y2="4.318" width="0.4064" layer="1"/> <wire x1="25.146" y1="4.318" x2="25.146" y2="10.795" width="0.4064" layer="1"/> @@ -627,22 +627,21 @@ design rules under a new name.</description> <wire x1="16.51" y1="21.336" x2="10.414" y2="21.336" width="0.3556" layer="1"/> <wire x1="21.107" y1="5.207" x2="23.724" y2="5.207" width="0.3556" layer="1"/> <wire x1="23.724" y1="5.207" x2="23.876" y2="5.461" width="0.4064" layer="1"/> -<wire x1="23.876" y1="11.684" x2="23.876" y2="5.461" width="0.4064" layer="1"/> +<wire x1="23.876" y1="11.938" x2="23.876" y2="5.461" width="0.4064" layer="1"/> <wire x1="23.876" y1="11.938" x2="23.876" y2="14.108" width="0.4064" layer="1"/> <wire x1="23.485" y1="14.499" x2="23.485" y2="16.393" width="0.3556" layer="1"/> <wire x1="23.485" y1="16.393" x2="21.082" y2="18.796" width="0.3556" layer="1"/> <wire x1="21.082" y1="18.796" x2="16.51" y2="18.796" width="0.3556" layer="1"/> <wire x1="23.876" y1="14.108" x2="23.485" y2="14.499" width="0.4064" layer="1"/> <contactref element="JP1" pad="5"/> -<wire x1="34.972" y1="8.255" x2="37.338" y2="8.255" width="0.4064" layer="1"/> -<wire x1="37.338" y1="8.255" x2="37.338" y2="11.938" width="0.4064" layer="1"/> -<wire x1="37.338" y1="11.938" x2="23.876" y2="11.938" width="0.4064" layer="1"/> -<wire x1="23.876" y1="11.938" x2="23.876" y2="11.684" width="0.4064" layer="1"/> +<wire x1="29.892" y1="8.255" x2="32.258" y2="8.255" width="0.4064" layer="1"/> +<wire x1="32.258" y1="8.255" x2="32.258" y2="11.938" width="0.4064" layer="1"/> +<wire x1="32.258" y1="11.938" x2="23.876" y2="11.938" width="0.4064" layer="1"/> </signal> <signal name="N$6"> <contactref element="JP1" pad="1"/> <contactref element="IC1" pad="5"/> -<wire x1="34.972" y1="18.415" x2="25.887" y2="18.415" width="0.4064" layer="1"/> +<wire x1="29.892" y1="18.415" x2="25.887" y2="18.415" width="0.4064" layer="1"/> <wire x1="25.887" y1="18.415" x2="23.495" y2="20.807" width="0.4064" layer="1"/> </signal> </signals> diff --git a/FabFTDI-Attiny102.brd b/FabFTDI-Attiny102.brd index c364a76ae5d02a9dfa5ff7adfd9a8fd12ab0d2e0..51a105a90a06f545e1bedfd1bddfb8cbf5718afa 100755 --- a/FabFTDI-Attiny102.brd +++ b/FabFTDI-Attiny102.brd @@ -10,42 +10,42 @@ <layers> <layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> <layer number="16" name="Bottom" color="1" fill="1" visible="no" active="yes"/> -<layer number="17" name="Pads" color="2" fill="1" visible="no" active="yes"/> -<layer number="18" name="Vias" color="2" fill="1" visible="no" active="yes"/> -<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="yes"/> -<layer number="20" name="Dimension" color="24" fill="1" visible="no" active="yes"/> +<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/> +<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/> +<layer number="20" name="Dimension" color="24" fill="1" visible="yes" active="yes"/> <layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/> -<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="yes"/> +<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/> <layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/> -<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="yes"/> -<layer number="25" name="tNames" color="7" fill="1" visible="no" active="yes"/> -<layer number="26" name="bNames" color="7" fill="1" visible="no" active="yes"/> +<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/> +<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/> +<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/> <layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/> -<layer number="28" name="bValues" color="7" fill="1" visible="no" active="yes"/> -<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/> -<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/> -<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/> -<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/> -<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/> -<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/> -<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/> -<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/> -<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/> -<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/> -<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="yes"/> -<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="yes"/> -<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="yes"/> -<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="yes"/> -<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/> -<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/> -<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/> -<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/> -<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/> -<layer number="48" name="Document" color="7" fill="1" visible="no" active="yes"/> -<layer number="49" name="Reference" color="7" fill="1" visible="no" active="yes"/> +<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/> +<layer number="29" name="tStop" color="7" fill="3" visible="yes" active="yes"/> +<layer number="30" name="bStop" color="7" fill="6" visible="yes" active="yes"/> +<layer number="31" name="tCream" color="7" fill="4" visible="yes" active="yes"/> +<layer number="32" name="bCream" color="7" fill="5" visible="yes" active="yes"/> +<layer number="33" name="tFinish" color="6" fill="3" visible="yes" active="yes"/> +<layer number="34" name="bFinish" color="6" fill="6" visible="yes" active="yes"/> +<layer number="35" name="tGlue" color="7" fill="4" visible="yes" active="yes"/> +<layer number="36" name="bGlue" color="7" fill="5" visible="yes" active="yes"/> +<layer number="37" name="tTest" color="7" fill="1" visible="yes" active="yes"/> +<layer number="38" name="bTest" color="7" fill="1" visible="yes" active="yes"/> +<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/> +<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/> +<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/> +<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/> +<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/> +<layer number="44" name="Drills" color="7" fill="1" visible="yes" active="yes"/> +<layer number="45" name="Holes" color="7" fill="1" visible="yes" active="yes"/> +<layer number="46" name="Milling" color="3" fill="1" visible="yes" active="yes"/> +<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="yes"/> +<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/> +<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/> <layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/> -<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="yes"/> -<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="yes"/> +<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/> +<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/> <layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/> <layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/> <layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/> @@ -61,55 +61,55 @@ <layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/> <layer number="99" name="SpiceOrder" color="7" fill="1" visible="no" active="no"/> <layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/> -<layer number="101" name="Patch_Top" color="12" fill="4" visible="no" active="yes"/> -<layer number="102" name="Vscore" color="7" fill="1" visible="no" active="yes"/> -<layer number="103" name="tMap" color="7" fill="1" visible="no" active="yes"/> -<layer number="104" name="Name" color="7" fill="1" visible="no" active="yes"/> -<layer number="105" name="tPlate" color="7" fill="1" visible="no" active="yes"/> -<layer number="106" name="bPlate" color="7" fill="1" visible="no" active="yes"/> -<layer number="107" name="Crop" color="7" fill="1" visible="no" active="yes"/> -<layer number="108" name="tplace-old" color="10" fill="1" visible="no" active="yes"/> -<layer number="109" name="ref-old" color="11" fill="1" visible="no" active="yes"/> -<layer number="110" name="fp0" color="7" fill="1" visible="no" active="yes"/> -<layer number="111" name="LPC17xx" color="7" fill="1" visible="no" active="yes"/> -<layer number="112" name="tSilk" color="7" fill="1" visible="no" active="yes"/> -<layer number="113" name="IDFDebug" color="4" fill="1" visible="no" active="yes"/> -<layer number="116" name="Patch_BOT" color="9" fill="4" visible="no" active="yes"/> -<layer number="121" name="_tsilk" color="7" fill="1" visible="no" active="yes"/> -<layer number="122" name="_bsilk" color="7" fill="1" visible="no" active="yes"/> -<layer number="123" name="tTestmark" color="7" fill="1" visible="no" active="yes"/> -<layer number="124" name="bTestmark" color="7" fill="1" visible="no" active="yes"/> -<layer number="125" name="_tNames" color="7" fill="1" visible="no" active="yes"/> -<layer number="126" name="_bNames" color="7" fill="1" visible="no" active="yes"/> -<layer number="127" name="_tValues" color="7" fill="1" visible="no" active="yes"/> -<layer number="128" name="_bValues" color="7" fill="1" visible="no" active="yes"/> -<layer number="131" name="tAdjust" color="7" fill="1" visible="no" active="yes"/> -<layer number="132" name="bAdjust" color="7" fill="1" visible="no" active="yes"/> -<layer number="144" name="Drill_legend" color="7" fill="1" visible="no" active="yes"/> -<layer number="150" name="Notes" color="7" fill="1" visible="no" active="yes"/> -<layer number="151" name="HeatSink" color="7" fill="1" visible="no" active="yes"/> -<layer number="152" name="_bDocu" color="7" fill="1" visible="no" active="yes"/> +<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/> +<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/> +<layer number="103" name="tMap" color="7" fill="1" visible="yes" active="yes"/> +<layer number="104" name="Name" color="7" fill="1" visible="yes" active="yes"/> +<layer number="105" name="tPlate" color="7" fill="1" visible="yes" active="yes"/> +<layer number="106" name="bPlate" color="7" fill="1" visible="yes" active="yes"/> +<layer number="107" name="Crop" color="7" fill="1" visible="yes" active="yes"/> +<layer number="108" name="tplace-old" color="10" fill="1" visible="yes" active="yes"/> +<layer number="109" name="ref-old" color="11" fill="1" visible="yes" active="yes"/> +<layer number="110" name="fp0" color="7" fill="1" visible="yes" active="yes"/> +<layer number="111" name="LPC17xx" color="7" fill="1" visible="yes" active="yes"/> +<layer number="112" name="tSilk" color="7" fill="1" visible="yes" active="yes"/> +<layer number="113" name="IDFDebug" color="4" fill="1" visible="yes" active="yes"/> +<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/> +<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/> +<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/> +<layer number="123" name="tTestmark" color="7" fill="1" visible="yes" active="yes"/> +<layer number="124" name="bTestmark" color="7" fill="1" visible="yes" active="yes"/> +<layer number="125" name="_tNames" color="7" fill="1" visible="yes" active="yes"/> +<layer number="126" name="_bNames" color="7" fill="1" visible="yes" active="yes"/> +<layer number="127" name="_tValues" color="7" fill="1" visible="yes" active="yes"/> +<layer number="128" name="_bValues" color="7" fill="1" visible="yes" active="yes"/> +<layer number="131" name="tAdjust" color="7" fill="1" visible="yes" active="yes"/> +<layer number="132" name="bAdjust" color="7" fill="1" visible="yes" active="yes"/> +<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/> +<layer number="150" name="Notes" color="7" fill="1" visible="yes" active="yes"/> +<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/> +<layer number="152" name="_bDocu" color="7" fill="1" visible="yes" active="yes"/> <layer number="153" name="FabDoc1" color="6" fill="1" visible="no" active="no"/> <layer number="154" name="FabDoc2" color="2" fill="1" visible="no" active="no"/> <layer number="155" name="FabDoc3" color="7" fill="15" visible="no" active="no"/> -<layer number="199" name="Contour" color="7" fill="1" visible="no" active="yes"/> -<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="yes"/> -<layer number="201" name="201bmp" color="2" fill="10" visible="no" active="yes"/> -<layer number="202" name="202bmp" color="3" fill="10" visible="no" active="yes"/> -<layer number="203" name="203bmp" color="4" fill="10" visible="no" active="yes"/> -<layer number="204" name="204bmp" color="5" fill="10" visible="no" active="yes"/> -<layer number="205" name="205bmp" color="6" fill="10" visible="no" active="yes"/> -<layer number="206" name="206bmp" color="7" fill="10" visible="no" active="yes"/> -<layer number="207" name="207bmp" color="8" fill="10" visible="no" active="yes"/> -<layer number="208" name="208bmp" color="9" fill="10" visible="no" active="yes"/> -<layer number="209" name="209bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="210" name="210bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="211" name="211bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="212" name="212bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="213" name="213bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="214" name="214bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="215" name="215bmp" color="7" fill="1" visible="no" active="yes"/> -<layer number="216" name="216bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="199" name="Contour" color="7" fill="1" visible="yes" active="yes"/> +<layer number="200" name="200bmp" color="1" fill="10" visible="yes" active="yes"/> +<layer number="201" name="201bmp" color="2" fill="10" visible="yes" active="yes"/> +<layer number="202" name="202bmp" color="3" fill="10" visible="yes" active="yes"/> +<layer number="203" name="203bmp" color="4" fill="10" visible="yes" active="yes"/> +<layer number="204" name="204bmp" color="5" fill="10" visible="yes" active="yes"/> +<layer number="205" name="205bmp" color="6" fill="10" visible="yes" active="yes"/> +<layer number="206" name="206bmp" color="7" fill="10" visible="yes" active="yes"/> +<layer number="207" name="207bmp" color="8" fill="10" visible="yes" active="yes"/> +<layer number="208" name="208bmp" color="9" fill="10" visible="yes" active="yes"/> +<layer number="209" name="209bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="210" name="210bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="211" name="211bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="212" name="212bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="213" name="213bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="214" name="214bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="215" name="215bmp" color="7" fill="1" visible="yes" active="yes"/> +<layer number="216" name="216bmp" color="7" fill="1" visible="yes" active="yes"/> <layer number="217" name="217bmp" color="18" fill="1" visible="no" active="no"/> <layer number="218" name="218bmp" color="19" fill="1" visible="no" active="no"/> <layer number="219" name="219bmp" color="20" fill="1" visible="no" active="no"/> @@ -118,18 +118,18 @@ <layer number="222" name="222bmp" color="23" fill="1" visible="no" active="no"/> <layer number="223" name="223bmp" color="24" fill="1" visible="no" active="no"/> <layer number="224" name="224bmp" color="25" fill="1" visible="no" active="no"/> -<layer number="248" name="Housing" color="7" fill="1" visible="no" active="yes"/> -<layer number="249" name="Edge" color="7" fill="1" visible="no" active="yes"/> +<layer number="248" name="Housing" color="7" fill="1" visible="yes" active="yes"/> +<layer number="249" name="Edge" color="7" fill="1" visible="yes" active="yes"/> <layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/> <layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/> -<layer number="254" name="cooling" color="7" fill="1" visible="no" active="yes"/> +<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/> </layers> <board> <plain> -<wire x1="1.27" y1="1.524" x2="38.278" y2="1.27" width="0" layer="20"/> -<wire x1="38.278" y1="1.27" x2="38.278" y2="27.93" width="0" layer="20"/> -<wire x1="38.278" y1="27.93" x2="1.27" y2="27.93" width="0" layer="20"/> -<wire x1="1.27" y1="27.93" x2="1.27" y2="1.524" width="0" layer="20"/> +<wire x1="1.27" y1="1.524" x2="49.2" y2="1.27" width="0" layer="20"/> +<wire x1="49.2" y1="1.27" x2="48.946" y2="35.55" width="0" layer="20"/> +<wire x1="48.946" y1="35.55" x2="1.016" y2="35.55" width="0" layer="20"/> +<wire x1="1.016" y1="35.55" x2="1.27" y2="1.524" width="0" layer="20"/> </plain> <libraries> <library name="fabPatil"> @@ -214,46 +214,6 @@ chip</description> <rectangle x1="0.9525" y1="-0.8763" x2="1.6891" y2="0.8763" layer="51"/> <rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/> </package> -<package name="USB-MICROB"> -<description>Micro USB Package</description> -<wire x1="-3.4" y1="-2.15" x2="-3" y2="-2.15" width="0.127" layer="51"/> -<wire x1="3" y1="-2.15" x2="3.4" y2="-2.15" width="0.127" layer="51"/> -<wire x1="-3.4" y1="-2.15" x2="-3.4" y2="-1.45" width="0.127" layer="51"/> -<wire x1="-3.4" y1="-1.45" x2="-3.4" y2="2.85" width="0.127" layer="51"/> -<wire x1="3.4" y1="2.85" x2="2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="3.4" y1="2.85" x2="3.4" y2="-1.45" width="0.127" layer="51"/> -<wire x1="3.4" y1="-1.45" x2="3.4" y2="-2.15" width="0.127" layer="51"/> -<wire x1="-3.4" y1="-1.45" x2="3.4" y2="-1.45" width="0.127" layer="51"/> -<wire x1="-3.4" y1="1.25" x2="-3.4" y2="2.85" width="0.2032" layer="21"/> -<wire x1="-3.4" y1="2.85" x2="-2.2" y2="2.85" width="0.2032" layer="21"/> -<wire x1="3.4" y1="2.85" x2="2.2" y2="2.85" width="0.2032" layer="21"/> -<wire x1="3.4" y1="1.25" x2="3.4" y2="2.85" width="0.2032" layer="21"/> -<wire x1="-3.4" y1="-1.45" x2="3.4" y2="-1.45" width="0.2032" layer="21"/> -<wire x1="-2.2" y1="1.45" x2="2.2" y2="1.45" width="0.127" layer="51"/> -<wire x1="2.2" y1="1.45" x2="2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="-2.2" y1="1.45" x2="-2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="-3.4" y1="2.85" x2="-2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="-2.2" y1="2.85" x2="-2.2" y2="1.45" width="0.2032" layer="21"/> -<wire x1="-2.2" y1="1.45" x2="2.2" y2="1.45" width="0.2032" layer="21"/> -<wire x1="2.2" y1="1.45" x2="2.2" y2="2.85" width="0.2032" layer="21"/> -<wire x1="-3.4" y1="-2.15" x2="-4" y2="-2.75" width="0.2032" layer="51"/> -<wire x1="3.4" y1="-2.15" x2="4" y2="-2.75" width="0.2032" layer="51"/> -<wire x1="-3" y1="-2.15" x2="-3" y2="-2.55" width="0.127" layer="51"/> -<wire x1="-2.8" y1="-2.8" x2="2.75" y2="-2.8" width="0.127" layer="51"/> -<wire x1="3" y1="-2.6" x2="3" y2="-2.15" width="0.127" layer="51"/> -<wire x1="-3" y1="-2.55" x2="-2.8" y2="-2.8" width="0.127" layer="51" curve="84.547378"/> -<wire x1="2.75" y1="-2.8" x2="3" y2="-2.6" width="0.127" layer="51" curve="84.547378"/> -<smd name="VBUS" x="-1.3" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="GND" x="1.3" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="D-" x="-0.65" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="D+" x="0" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="ID" x="0.65" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="MT1" x="-4" y="0" dx="1.8" dy="1.9" layer="1"/> -<smd name="MT2" x="4" y="0" dx="1.8" dy="1.9" layer="1"/> -<text x="-1.6" y="-4.16" size="0.762" layer="25">>NAME</text> -<smd name="P$1" x="-1.27" y="0" dx="1.9" dy="1.9" layer="1"/> -<smd name="P$2" x="1.27" y="0" dx="1.9" dy="1.9" layer="1"/> -</package> <package name="SOD123"> <description><b>SMALL OUTLINE DIODE</b></description> <wire x1="-2.973" y1="0.983" x2="2.973" y2="0.983" width="0.0508" layer="39"/> @@ -277,6 +237,21 @@ chip</description> <rectangle x1="1.3716" y1="-0.3048" x2="1.9558" y2="0.3048" layer="51" rot="R180"/> <rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/> </package> +<package name="USB_PCB"> +<description>Card-edge USB A connector. + +For boards designed to be plugged directly into a USB slot. If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="D-" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="D+" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> </packages> </library> </libraries> @@ -468,184 +443,186 @@ design rules under a new name.</description> </pass> </autorouter> <elements> -<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="32.258" y="14.097" rot="R270"/> -<element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102" x="22.606" y="19.685"/> -<element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPI" x="8.89" y="20.828" rot="R180"/> -<element name="R1" library="fabPatil" package="1206" value="1K" x="10.16" y="14.097" rot="R180"/> -<element name="R2" library="fabPatil" package="1206" value="499" x="16.51" y="13.843" rot="R90"/> -<element name="U$2" library="fabPatil" package="USB-MICROB" value="FAB_USB" x="4.318" y="9.271" rot="R270"/> -<element name="D1" library="fabPatil" package="SOD123" value="3.3V" x="13.716" y="9.271" rot="R270"/> -<element name="D2" library="fabPatil" package="SOD123" value="3.3V" x="16.383" y="7.62" rot="R270"/> -<element name="R3" library="fabPatil" package="1206" value="499" x="20.574" y="10.033"/> -<element name="R4" library="fabPatil" package="1206" value="499" x="20.701" y="12.954"/> -<element name="C1" library="fabPatil" package="1206" value="0.1uF" x="26.162" y="7.239" rot="R180"/> -<element name="R5" library="fabPatil" package="1206" value="4.7K" x="20.701" y="7.239"/> +<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="41.656" y="15.621" rot="R270"/> +<element name="IC1" library="fabPatil" package="SOIC8" value="ATTINY102" x="32.004" y="21.209"/> +<element name="U$1" library="fabPatil" package="2X03SMD" value="AVRTPI" x="18.288" y="22.352" rot="R180"/> +<element name="R1" library="fabPatil" package="1206" value="1K" x="19.558" y="15.621" rot="R180"/> +<element name="R2" library="fabPatil" package="1206" value="499" x="25.908" y="15.367" rot="R90"/> +<element name="D1" library="fabPatil" package="SOD123" value="3.3V" x="23.114" y="10.795" rot="R270"/> +<element name="D2" library="fabPatil" package="SOD123" value="3.3V" x="25.781" y="9.144" rot="R270"/> +<element name="R3" library="fabPatil" package="1206" value="499" x="29.972" y="11.557"/> +<element name="R4" library="fabPatil" package="1206" value="499" x="30.099" y="14.478"/> +<element name="C1" library="fabPatil" package="1206" value="0.1uF" x="35.56" y="8.763" rot="R180"/> +<element name="R5" library="fabPatil" package="1206" value="4.7K" x="30.099" y="8.763"/> +<element name="U$3" library="fabPatil" package="USB_PCB" value="USB_PCB" x="5.08" y="10.414"/> </elements> <signals> <signal name="GND"> -<contactref element="U$2" pad="GND"/> <contactref element="D1" pad="ANODE"/> <contactref element="D2" pad="ANODE"/> <contactref element="U$1" pad="6"/> <contactref element="C1" pad="1"/> <contactref element="JP1" pad="6"/> <contactref element="IC1" pad="8"/> -<wire x1="13.716" y1="5.92" x2="16.383" y2="5.92" width="0.4064" layer="1"/> -<wire x1="13.716" y1="5.92" x2="13.716" y2="7.571" width="0.4064" layer="1"/> -<wire x1="13.716" y1="7.571" x2="13.316" y2="7.971" width="0.3556" layer="1"/> -<wire x1="13.316" y1="7.971" x2="6.968" y2="7.971" width="0.3556" layer="1"/> -<wire x1="20.701" y1="24.384" x2="20.701" y2="22.839" width="0.3556" layer="1"/> -<wire x1="20.701" y1="24.384" x2="20.701" y2="24.892" width="0.3556" layer="1"/> -<wire x1="20.701" y1="24.892" x2="5.842" y2="24.892" width="0.3556" layer="1"/> -<wire x1="5.842" y1="24.892" x2="5.842" y2="23.368" width="0.3556" layer="1"/> -<wire x1="5.842" y1="23.368" x2="5.97" y2="23.368" width="0.3556" layer="1"/> -<wire x1="28.092" y1="7.747" x2="27.584" y2="7.239" width="0.4064" layer="1"/> -<wire x1="20.701" y1="25.908" x2="20.701" y2="24.384" width="0.4064" layer="1"/> -<wire x1="27.584" y1="7.239" x2="27.686" y2="7.239" width="0.4064" layer="1"/> -<wire x1="27.584" y1="7.747" x2="30.908" y2="7.747" width="0.4064" layer="1"/> -<wire x1="27.584" y1="7.747" x2="27.584" y2="7.239" width="0.4064" layer="1"/> -<wire x1="30.908" y1="7.747" x2="34.29" y2="7.747" width="0.4064" layer="1"/> -<wire x1="34.29" y1="7.747" x2="34.29" y2="21.844" width="0.4064" layer="1"/> -<wire x1="34.29" y1="21.844" x2="29.464" y2="21.844" width="0.4064" layer="1"/> -<wire x1="29.464" y1="21.844" x2="25.654" y2="25.908" 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width="0.3556" layer="1"/> +<wire x1="34.138" y1="8.763" x2="34.29" y2="9.017" width="0.4064" layer="1"/> +<wire x1="34.29" y1="15.494" x2="34.29" y2="9.017" width="0.4064" layer="1"/> +<wire x1="34.29" y1="15.494" x2="34.29" y2="17.664" width="0.4064" layer="1"/> +<wire x1="33.899" y1="18.055" x2="33.899" y2="19.949" width="0.3556" layer="1"/> +<wire x1="33.899" y1="19.949" x2="31.496" y2="22.352" width="0.3556" layer="1"/> +<wire x1="31.496" y1="22.352" x2="26.924" y2="22.352" width="0.3556" layer="1"/> +<wire x1="34.29" y1="17.664" x2="33.899" y2="18.055" width="0.4064" layer="1"/> <contactref element="JP1" pad="5"/> -<wire x1="30.908" y1="10.287" x2="33.274" y2="10.287" width="0.4064" layer="1"/> -<wire x1="33.274" y1="10.287" x2="33.274" y2="13.97" width="0.4064" layer="1"/> -<wire x1="33.274" y1="13.97" x2="24.892" y2="13.97" width="0.4064" layer="1"/> +<wire x1="40.306" y1="11.811" x2="42.672" y2="11.811" width="0.4064" layer="1"/> +<wire x1="42.672" y1="11.811" x2="42.672" y2="15.494" width="0.4064" layer="1"/> +<wire x1="42.672" y1="15.494" x2="34.29" y2="15.494" width="0.4064" layer="1"/> </signal> <signal name="N$6"> <contactref element="JP1" pad="1"/> <contactref element="IC1" pad="5"/> -<wire x1="27.432" y1="19.918" x2="27.432" y2="16.764" width="0.4064" layer="1"/> -<wire x1="27.432" y1="16.764" x2="33.274" y2="16.764" width="0.4064" layer="1"/> -<wire x1="33.274" y1="16.764" x2="33.274" y2="19.304" width="0.4064" layer="1"/> -<wire x1="33.274" y1="19.304" x2="32.258" y2="20.32" width="0.4064" layer="1"/> -<wire x1="32.258" y1="20.32" x2="31.035" y2="20.32" width="0.4064" layer="1"/> -<wire x1="31.035" y1="20.32" x2="30.908" y2="20.447" width="0.4064" layer="1"/> -<wire x1="24.511" y1="22.839" x2="27.432" y2="19.918" width="0.4064" layer="1"/> +<wire x1="36.83" y1="21.442" x2="36.83" y2="18.288" width="0.4064" layer="1"/> +<wire x1="36.83" y1="18.288" x2="42.672" y2="18.288" width="0.4064" layer="1"/> +<wire x1="42.672" y1="18.288" x2="42.672" y2="20.828" width="0.4064" layer="1"/> +<wire x1="42.672" y1="20.828" x2="41.656" y2="21.844" width="0.4064" layer="1"/> +<wire x1="41.656" y1="21.844" x2="40.433" y2="21.844" width="0.4064" layer="1"/> +<wire x1="40.433" y1="21.844" x2="40.306" y2="21.971" width="0.4064" layer="1"/> +<wire x1="33.909" y1="24.363" x2="36.83" y2="21.442" width="0.4064" layer="1"/> </signal> <signal name="N$7"> <polygon width="0.4064" layer="16"> diff --git a/FabFTDI-Attiny102.s#1 b/FabFTDI-Attiny102.s#1 index e4bd0547c5a8e45e14c1992423b8203d88b837b2..9532096d087177ed119e1ac6ae3ca0056a9e446d 100755 --- a/FabFTDI-Attiny102.s#1 +++ b/FabFTDI-Attiny102.s#1 @@ -203,7 +203,7 @@ chip</description> <smd name="2" x="1.422" y="0" dx="1.6" dy="1.803" layer="1"/> <smd name="1" x="-1.422" y="0" dx="1.6" dy="1.803" layer="1"/> <text x="-1.397" y="1.143" size="1.27" layer="25">>NAME</text> -<text x="-1.397" y="-2.413" size="1.27" layer="27">>VALUE</text> +<text x="-1.397" y="-1.143" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.6891" y1="-0.8763" x2="-0.9525" y2="0.8763" layer="51"/> <rectangle x1="0.9525" y1="-0.8763" x2="1.6891" y2="0.8763" layer="51"/> <rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/> @@ -282,7 +282,7 @@ chip</description> <smd name="CATHODE" x="-1.7" y="0" dx="1.6" dy="0.8" layer="1"/> <smd name="ANODE" x="1.7" y="0" dx="1.6" dy="0.8" layer="1"/> <text x="-1.905" y="1.905" size="1.27" layer="25">>NAME</text> -<text x="-1.905" y="-3.175" size="1.27" layer="27">>VALUE</text> +<text x="-1.905" y="-0.635" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.9558" y1="-0.3048" x2="-1.3716" y2="0.3048" layer="51" rot="R180"/> <rectangle x1="1.3716" y1="-0.3048" x2="1.9558" y2="0.3048" layer="51" rot="R180"/> <rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/> @@ -612,7 +612,7 @@ high speed (Philips)</description> <parts> <part name="IC1" library="fabPatil" deviceset="ATTINY102/104" device="" value="ATTINY102"/> <part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> -<part name="U$1" library="fabPatil" deviceset="AVRTPI" device="SMD"/> +<part name="U$1" library="fabPatil" deviceset="AVRTPI" device="SMD" value="AVRTPI"/> <part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> <part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> <part name="U$2" library="fabPatil" deviceset="FAB_USB" device=""/> @@ -627,7 +627,7 @@ high speed (Philips)</description> <part name="GND3" library="fabPatil" deviceset="GND" device=""/> <part name="P+3" library="FAB_Hello" deviceset="VCC" device=""/> <part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> -<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206"/> +<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206" value="4.7K"/> <part name="GND4" library="fabPatil" deviceset="GND" device=""/> <part name="GND5" library="fabPatil" deviceset="GND" device=""/> <part name="P+4" library="FAB_Hello" deviceset="VCC" device=""/> diff --git a/FabFTDI-Attiny102.s#3 b/FabFTDI-Attiny102.s#3 index eb9e7d6487f786b327eec6081645a3c11df8386f..e4bd0547c5a8e45e14c1992423b8203d88b837b2 100755 --- a/FabFTDI-Attiny102.s#3 +++ b/FabFTDI-Attiny102.s#3 @@ -304,8 +304,8 @@ chip</description> <pin name="PB3(RXD)" x="35.56" y="7.62" length="middle" rot="R180"/> <pin name="PB2(TXD)" x="35.56" y="5.08" length="middle" rot="R180"/> <pin name="PB1" x="35.56" y="2.54" length="middle" rot="R180"/> -<text x="0" y="12.7" size="1.27" layer="95">>NAME</text> -<text x="0" y="-2.54" size="1.27" layer="96">ATTINY102/104</text> +<text x="0" y="12.7" size="1.27" layer="95">AT102</text> +<text x="0" y="-2.54" size="1.27" layer="96">>VALUE</text> </symbol> <symbol name="ARDUINO_SERIAL_PROGRAM"> <wire x1="1.27" y1="-7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> @@ -610,7 +610,7 @@ high speed (Philips)</description> </class> </classes> <parts> -<part name="IC1" library="fabPatil" deviceset="ATTINY102/104" device=""/> +<part name="IC1" library="fabPatil" deviceset="ATTINY102/104" device="" value="ATTINY102"/> <part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> <part name="U$1" library="fabPatil" deviceset="AVRTPI" device="SMD"/> <part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> diff --git a/FabFTDI-Attiny102.s#4 b/FabFTDI-Attiny102.s#4 index b95a99a8ebbc7fc86756ed704815972f317e1732..eb9e7d6487f786b327eec6081645a3c11df8386f 100755 --- a/FabFTDI-Attiny102.s#4 +++ b/FabFTDI-Attiny102.s#4 @@ -169,16 +169,16 @@ <rectangle x1="-2.08" y1="-3.4" x2="-1.73" y2="-2.5" layer="51"/> </package> <package name="1X06-SMD"> -<wire x1="7.62" y1="6.33" x2="-7.62" y2="6.33" width="0.127" layer="51"/> -<wire x1="-7.62" y1="6.33" x2="-7.62" y2="-1.25" width="0.127" layer="51"/> -<wire x1="-7.62" y1="-1.25" x2="7.62" y2="-1.25" width="0.127" layer="51"/> -<wire x1="7.62" y1="-1.25" x2="7.62" y2="6.33" width="0.127" layer="51"/> -<smd name="4" x="1.27" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="5" x="3.81" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="6" x="6.35" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="3" x="-1.27" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="2" x="-3.81" y="5" dx="3" dy="1" layer="1" rot="R90"/> -<smd name="1" x="-6.35" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<wire x1="7.62" y1="5.06" x2="-7.62" y2="5.06" width="0.127" layer="51"/> +<wire x1="-7.62" y1="5.06" x2="-7.62" y2="-3.79" width="0.127" layer="51"/> +<wire x1="-7.62" y1="-3.79" x2="7.62" y2="-3.79" width="0.127" layer="51"/> +<wire x1="7.62" y1="-3.79" x2="7.62" y2="5.06" width="0.127" layer="51"/> +<smd name="4" x="1.27" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="5" x="3.81" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="6" x="6.35" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="3" x="-1.27" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="2" x="-3.81" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="1" x="-6.35" y="-1.35" dx="3" dy="1" layer="1" rot="R90"/> </package> <package name="2X03SMD"> <smd name="1" x="-2.54" y="2.54" dx="2.54" dy="1.27" layer="1"/> diff --git a/FabFTDI-Attiny102.s#5 b/FabFTDI-Attiny102.s#5 index 9c9ea1bd23f7ab35ed9d58dd1d8718518c0fd123..b95a99a8ebbc7fc86756ed704815972f317e1732 100755 --- a/FabFTDI-Attiny102.s#5 +++ b/FabFTDI-Attiny102.s#5 @@ -656,9 +656,9 @@ high speed (Philips)</description> <instance part="P+3" gate="VCC" x="-17.78" y="15.24"/> <instance part="C1" gate="1" x="2.54" y="7.62" rot="R180"/> <instance part="R5" gate="G$1" x="-10.16" y="7.62"/> -<instance part="GND4" gate="1" x="58.42" y="5.08"/> +<instance part="GND4" gate="1" x="81.28" y="5.08"/> <instance part="GND5" gate="1" x="50.8" y="30.48"/> -<instance part="P+4" gate="VCC" x="50.8" y="17.78"/> +<instance part="P+4" gate="VCC" x="81.28" y="22.86"/> <instance part="P+5" gate="VCC" x="0" y="33.02"/> </instances> <busses> @@ -695,8 +695,8 @@ high speed (Philips)</description> <segment> <pinref part="JP1" gate="G$1" pin="GND"/> <pinref part="GND4" gate="1" pin="GND"/> -<wire x1="60.96" y1="12.7" x2="58.42" y2="12.7" width="0.1524" layer="91"/> -<wire x1="58.42" y1="12.7" x2="58.42" y2="7.62" width="0.1524" layer="91"/> +<wire x1="60.96" y1="12.7" x2="81.28" y2="12.7" width="0.1524" layer="91"/> +<wire x1="81.28" y1="12.7" x2="81.28" y2="7.62" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC1" gate="G$1" pin="GND"/> @@ -746,12 +746,10 @@ high speed (Philips)</description> <wire x1="-17.78" y1="7.62" x2="-17.78" y2="12.7" width="0.1524" layer="91"/> </segment> <segment> -<pinref part="JP1" gate="G$1" pin="VCC"/> -<wire x1="60.96" y1="17.78" x2="55.88" y2="17.78" width="0.1524" layer="91"/> -<wire x1="55.88" y1="17.78" x2="55.88" y2="12.7" width="0.1524" layer="91"/> -<wire x1="55.88" y1="12.7" x2="50.8" y2="12.7" width="0.1524" layer="91"/> <pinref part="P+4" gate="VCC" pin="VCC"/> -<wire x1="50.8" y1="12.7" x2="50.8" y2="15.24" width="0.1524" layer="91"/> +<wire x1="81.28" y1="17.78" x2="81.28" y2="20.32" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="81.28" y1="17.78" x2="60.96" y2="17.78" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC1" gate="G$1" pin="VCC"/> @@ -826,9 +824,24 @@ high speed (Philips)</description> <pinref part="C1" gate="1" pin="2"/> <wire x1="-5.08" y1="7.62" x2="-2.54" y2="7.62" width="0.1524" layer="91"/> <wire x1="-2.54" y1="7.62" x2="0" y2="7.62" width="0.1524" layer="91"/> -<wire x1="-2.54" y1="17.78" x2="-2.54" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="17.78" x2="-2.54" y2="12.7" width="0.1524" layer="91"/> <junction x="-2.54" y="17.78"/> <junction x="-2.54" y="7.62"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="-2.54" y1="12.7" x2="-2.54" y2="7.62" width="0.1524" layer="91"/> +<wire x1="60.96" y1="15.24" x2="48.26" y2="15.24" width="0.1524" layer="91"/> +<wire x1="48.26" y1="15.24" x2="45.72" y2="12.7" width="0.1524" layer="91"/> +<wire x1="45.72" y1="12.7" x2="-2.54" y2="12.7" width="0.1524" layer="91"/> +<junction x="-2.54" y="12.7"/> +</segment> +</net> +<net name="N$6" class="0"> +<segment> +<pinref part="JP1" gate="G$1" pin="DTR"/> +<wire x1="60.96" y1="25.4" x2="53.34" y2="25.4" width="0.1524" layer="91"/> +<wire x1="53.34" y1="25.4" x2="45.72" y2="17.78" width="0.1524" layer="91"/> +<pinref part="IC1" gate="G$1" pin="PB1"/> +<wire x1="45.72" y1="17.78" x2="43.18" y2="17.78" width="0.1524" layer="91"/> </segment> </net> </nets> diff --git a/FabFTDI-Attiny102.s#6 b/FabFTDI-Attiny102.s#6 index e5314ea66f47b9bbd00a4e15964329e063e8f1f2..9c9ea1bd23f7ab35ed9d58dd1d8718518c0fd123 100755 --- a/FabFTDI-Attiny102.s#6 +++ b/FabFTDI-Attiny102.s#6 @@ -466,12 +466,12 @@ prashant.patil@cba.mit.edu <devices> <device name="SMD" package="2X03SMD"> <connects> -<connect gate="G$1" pin="(NC)" pad="5"/> +<connect gate="G$1" pin="(NC)" pad="4"/> <connect gate="G$1" pin="GND" pad="6"/> -<connect gate="G$1" pin="RESET" pad="3"/> -<connect gate="G$1" pin="TPICLK" pad="2"/> +<connect gate="G$1" pin="RESET" pad="5"/> +<connect gate="G$1" pin="TPICLK" pad="3"/> <connect gate="G$1" pin="TPIDATA" pad="1"/> -<connect gate="G$1" pin="VCC" pad="4"/> +<connect gate="G$1" pin="VCC" pad="2"/> </connects> <technologies> <technology name=""/> diff --git a/FabFTDI-Attiny102.s#7 b/FabFTDI-Attiny102.s#7 index a1cabd7f4bf583f2103683ced1b7e22733cae359..e5314ea66f47b9bbd00a4e15964329e063e8f1f2 100755 --- a/FabFTDI-Attiny102.s#7 +++ b/FabFTDI-Attiny102.s#7 @@ -631,6 +631,7 @@ high speed (Philips)</description> <part name="GND4" library="fabPatil" deviceset="GND" device=""/> <part name="GND5" library="fabPatil" deviceset="GND" device=""/> <part name="P+4" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="P+5" library="FAB_Hello" deviceset="VCC" device=""/> </parts> <sheets> <sheet> @@ -658,6 +659,7 @@ high speed (Philips)</description> <instance part="GND4" gate="1" x="58.42" y="5.08"/> <instance part="GND5" gate="1" x="50.8" y="30.48"/> <instance part="P+4" gate="VCC" x="50.8" y="17.78"/> +<instance part="P+5" gate="VCC" x="0" y="33.02"/> </instances> <busses> </busses> @@ -751,6 +753,12 @@ high speed (Philips)</description> <pinref part="P+4" gate="VCC" pin="VCC"/> <wire x1="50.8" y1="12.7" x2="50.8" y2="15.24" width="0.1524" layer="91"/> </segment> +<segment> +<pinref part="IC1" gate="G$1" pin="VCC"/> +<pinref part="P+5" gate="VCC" pin="VCC"/> +<wire x1="2.54" y1="25.4" x2="0" y2="25.4" width="0.1524" layer="91"/> +<wire x1="0" y1="25.4" x2="0" y2="30.48" width="0.1524" layer="91"/> +</segment> </net> <net name="N$11" class="0"> <segment> diff --git a/FabFTDI-Attiny102.s#8 b/FabFTDI-Attiny102.s#8 index 09d990eaff24a324509ad15d100bbbf8f8cc7182..a1cabd7f4bf583f2103683ced1b7e22733cae359 100755 --- a/FabFTDI-Attiny102.s#8 +++ b/FabFTDI-Attiny102.s#8 @@ -393,6 +393,18 @@ Symbol used in AVR TPI device. <pin name="A" x="-2.54" y="0" visible="off" length="short" direction="pas"/> <pin name="C" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/> </symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> </symbols> <devicesets> <deviceset name="ATTINY102/104"> @@ -542,6 +554,23 @@ high speed (Philips)</description> </device> </devices> </deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> </devicesets> </library> <library name="FAB_Hello"> @@ -593,15 +622,24 @@ high speed (Philips)</description> <part name="D2" library="fabPatil" deviceset="DIODE" device="SOD123" value="3.3V"/> <part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> <part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND2" library="fabPatil" deviceset="GND" device=""/> +<part name="GND3" library="fabPatil" deviceset="GND" device=""/> +<part name="P+3" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206"/> +<part name="GND4" library="fabPatil" deviceset="GND" device=""/> +<part name="GND5" library="fabPatil" deviceset="GND" device=""/> +<part name="P+4" library="FAB_Hello" deviceset="VCC" device=""/> </parts> <sheets> <sheet> <plain> </plain> <instances> -<instance part="IC1" gate="G$1" x="-2.54" y="15.24"/> -<instance part="JP1" gate="G$1" x="55.88" y="20.32" rot="R180"/> -<instance part="U$1" gate="G$1" x="7.62" y="-10.16"/> +<instance part="IC1" gate="G$1" x="7.62" y="15.24"/> +<instance part="JP1" gate="G$1" x="66.04" y="20.32" rot="R180"/> +<instance part="U$1" gate="G$1" x="7.62" y="35.56"/> <instance part="R1" gate="G$1" x="-33.02" y="43.18" rot="R90"/> <instance part="R2" gate="G$1" x="-33.02" y="30.48" rot="R90"/> <instance part="U$2" gate="G$1" x="-45.72" y="12.7"/> @@ -611,22 +649,21 @@ high speed (Philips)</description> <instance part="D2" gate="G$1" x="-27.94" y="10.16" rot="R90"/> <instance part="R3" gate="G$1" x="-15.24" y="20.32"/> <instance part="R4" gate="G$1" x="-22.86" y="22.86"/> +<instance part="P+1" gate="VCC" x="38.1" y="50.8"/> +<instance part="GND2" gate="1" x="38.1" y="33.02"/> +<instance part="GND3" gate="1" x="12.7" y="2.54"/> +<instance part="P+3" gate="VCC" x="-17.78" y="15.24"/> +<instance part="C1" gate="1" x="2.54" y="7.62" rot="R180"/> +<instance part="R5" gate="G$1" x="-10.16" y="7.62"/> +<instance part="GND4" gate="1" x="58.42" y="5.08"/> +<instance part="GND5" gate="1" x="50.8" y="30.48"/> +<instance part="P+4" gate="VCC" x="50.8" y="17.78"/> </instances> <busses> </busses> <nets> <net name="GND" class="0"> <segment> -<pinref part="JP1" gate="G$1" pin="GND"/> -<wire x1="50.8" y1="12.7" x2="45.72" y2="12.7" width="0.1524" layer="91"/> -<label x="45.72" y="12.7" size="1.778" layer="95"/> -</segment> -<segment> -<pinref part="IC1" gate="G$1" pin="GND"/> -<wire x1="33.02" y1="25.4" x2="40.64" y2="25.4" width="0.1524" layer="91"/> -<label x="35.56" y="25.4" size="1.778" layer="95"/> -</segment> -<segment> <pinref part="U$2" gate="G$1" pin="GND"/> <pinref part="GND1" gate="1" pin="GND"/> <wire x1="-40.64" y1="15.24" x2="-38.1" y2="15.24" width="0.1524" layer="91"/> @@ -641,33 +678,49 @@ high speed (Philips)</description> <wire x1="-27.94" y1="5.08" x2="-33.02" y2="5.08" width="0.1524" layer="91"/> <junction x="-33.02" y="5.08"/> </segment> +<segment> +<pinref part="GND2" gate="1" pin="GND"/> +<wire x1="38.1" y1="35.56" x2="38.1" y2="38.1" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="GND"/> +<wire x1="38.1" y1="38.1" x2="33.02" y2="38.1" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C1" gate="1" pin="1"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="7.62" y1="7.62" x2="12.7" y2="7.62" width="0.1524" layer="91"/> +<wire x1="12.7" y1="7.62" x2="12.7" y2="5.08" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<pinref part="GND4" gate="1" pin="GND"/> +<wire x1="60.96" y1="12.7" x2="58.42" y2="12.7" width="0.1524" layer="91"/> +<wire x1="58.42" y1="12.7" x2="58.42" y2="7.62" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC1" gate="G$1" pin="GND"/> +<wire x1="43.18" y1="25.4" x2="45.72" y2="25.4" width="0.1524" layer="91"/> +<wire x1="45.72" y1="25.4" x2="45.72" y2="35.56" width="0.1524" layer="91"/> +<pinref part="GND5" gate="1" pin="GND"/> +<wire x1="45.72" y1="35.56" x2="50.8" y2="35.56" width="0.1524" layer="91"/> +<wire x1="50.8" y1="35.56" x2="50.8" y2="33.02" width="0.1524" layer="91"/> +</segment> </net> <net name="N$2" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="PB3(RXD)"/> <pinref part="JP1" gate="G$1" pin="RXI"/> -<wire x1="33.02" y1="22.86" x2="50.8" y2="22.86" width="0.1524" layer="91"/> +<wire x1="43.18" y1="22.86" x2="60.96" y2="22.86" width="0.1524" layer="91"/> </segment> </net> <net name="N$3" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="PB2(TXD)"/> <pinref part="JP1" gate="G$1" pin="TXO"/> -<wire x1="33.02" y1="20.32" x2="50.8" y2="20.32" width="0.1524" layer="91"/> +<wire x1="43.18" y1="20.32" x2="60.96" y2="20.32" width="0.1524" layer="91"/> </segment> </net> <net name="VCC" class="0"> <segment> -<pinref part="JP1" gate="G$1" pin="VCC"/> -<wire x1="50.8" y1="17.78" x2="45.72" y2="17.78" width="0.1524" layer="91"/> -<label x="45.72" y="17.78" size="1.778" layer="95"/> -</segment> -<segment> -<pinref part="IC1" gate="G$1" pin="VCC"/> -<wire x1="-7.62" y1="25.4" x2="-10.16" y2="25.4" width="0.1524" layer="91"/> -<label x="-10.16" y="25.4" size="1.778" layer="95"/> -</segment> -<segment> <pinref part="U$2" gate="G$1" pin="VBUS"/> <pinref part="P+2" gate="VCC" pin="VCC"/> <wire x1="-40.64" y1="25.4" x2="-38.1" y2="25.4" width="0.1524" layer="91"/> @@ -678,41 +731,25 @@ high speed (Philips)</description> <wire x1="-33.02" y1="50.8" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> <junction x="-38.1" y="50.8"/> </segment> -</net> -<net name="N$5" class="0"> -<segment> -<pinref part="U$1" gate="G$1" pin="TPIDATA"/> -<wire x1="2.54" y1="-2.54" x2="-2.54" y2="-2.54" width="0.1524" layer="91"/> -</segment> -</net> -<net name="N$6" class="0"> -<segment> -<pinref part="U$1" gate="G$1" pin="TPICLK"/> -<wire x1="2.54" y1="-5.08" x2="-2.54" y2="-5.08" width="0.1524" layer="91"/> -</segment> -</net> -<net name="N$7" class="0"> -<segment> -<pinref part="U$1" gate="G$1" pin="RESET"/> -<wire x1="2.54" y1="-7.62" x2="-2.54" y2="-7.62" width="0.1524" layer="91"/> -</segment> -</net> -<net name="N$8" class="0"> <segment> <pinref part="U$1" gate="G$1" pin="VCC"/> -<wire x1="33.02" y1="-2.54" x2="38.1" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="33.02" y1="43.18" x2="38.1" y2="43.18" width="0.1524" layer="91"/> +<wire x1="38.1" y1="43.18" x2="38.1" y2="48.26" width="0.1524" layer="91"/> </segment> -</net> -<net name="N$9" class="0"> <segment> -<pinref part="U$1" gate="G$1" pin="(NC)"/> -<wire x1="33.02" y1="-5.08" x2="38.1" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="R5" gate="G$1" pin="1"/> +<pinref part="P+3" gate="VCC" pin="VCC"/> +<wire x1="-15.24" y1="7.62" x2="-17.78" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="7.62" x2="-17.78" y2="12.7" width="0.1524" layer="91"/> </segment> -</net> -<net name="N$10" class="0"> <segment> -<pinref part="U$1" gate="G$1" pin="GND"/> -<wire x1="33.02" y1="-7.62" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="60.96" y1="17.78" x2="55.88" y2="17.78" width="0.1524" layer="91"/> +<wire x1="55.88" y1="17.78" x2="55.88" y2="12.7" width="0.1524" layer="91"/> +<wire x1="55.88" y1="12.7" x2="50.8" y2="12.7" width="0.1524" layer="91"/> +<pinref part="P+4" gate="VCC" pin="VCC"/> +<wire x1="50.8" y1="12.7" x2="50.8" y2="15.24" width="0.1524" layer="91"/> </segment> </net> <net name="N$11" class="0"> @@ -751,13 +788,39 @@ high speed (Philips)</description> <pinref part="R3" gate="G$1" pin="2"/> <pinref part="IC1" gate="G$1" pin="PA1(TPIDATA)"/> <wire x1="-10.16" y1="20.32" x2="-7.62" y2="20.32" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="TPIDATA"/> +<wire x1="-7.62" y1="20.32" x2="2.54" y2="20.32" width="0.1524" layer="91"/> +<wire x1="2.54" y1="43.18" x2="-7.62" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="43.18" x2="-7.62" y2="20.32" width="0.1524" layer="91"/> +<junction x="-7.62" y="20.32"/> </segment> </net> <net name="N$12" class="0"> <segment> <pinref part="R4" gate="G$1" pin="2"/> <pinref part="IC1" gate="G$1" pin="PA0(TPICLK)"/> -<wire x1="-17.78" y1="22.86" x2="-7.62" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="22.86" x2="-5.08" y2="22.86" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="TPICLK"/> +<wire x1="-5.08" y1="22.86" x2="2.54" y2="22.86" width="0.1524" layer="91"/> +<wire x1="2.54" y1="40.64" x2="-5.08" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="40.64" x2="-5.08" y2="22.86" width="0.1524" layer="91"/> +<junction x="-5.08" y="22.86"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="RESET"/> +<wire x1="2.54" y1="38.1" x2="-2.54" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="38.1" x2="-2.54" y2="17.78" width="0.1524" layer="91"/> +<pinref part="IC1" gate="G$1" pin="PA2(RESET)"/> +<wire x1="-2.54" y1="17.78" x2="2.54" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R5" gate="G$1" pin="2"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-5.08" y1="7.62" x2="-2.54" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="7.62" x2="0" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="17.78" x2="-2.54" y2="7.62" width="0.1524" layer="91"/> +<junction x="-2.54" y="17.78"/> +<junction x="-2.54" y="7.62"/> </segment> </net> </nets> diff --git a/FabFTDI-Attiny102.s#9 b/FabFTDI-Attiny102.s#9 index 715f72fac5768d644771044fab6d8af4fbe8f351..09d990eaff24a324509ad15d100bbbf8f8cc7182 100755 --- a/FabFTDI-Attiny102.s#9 +++ b/FabFTDI-Attiny102.s#9 @@ -584,31 +584,33 @@ high speed (Philips)</description> <part name="IC1" library="fabPatil" deviceset="ATTINY102/104" device=""/> <part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> <part name="U$1" library="fabPatil" deviceset="AVRTPI" device="SMD"/> -<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206"/> -<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206"/> -<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> <part name="U$2" library="fabPatil" deviceset="FAB_USB" device=""/> <part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> <part name="GND1" library="fabPatil" deviceset="GND" device=""/> -<part name="D1" library="fabPatil" deviceset="DIODE" device="SOD123"/> -<part name="D2" library="fabPatil" deviceset="DIODE" device="SOD123"/> +<part name="D1" library="fabPatil" deviceset="DIODE" device="SOD123" value="3.3V"/> +<part name="D2" library="fabPatil" deviceset="DIODE" device="SOD123" value="3.3V"/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> </parts> <sheets> <sheet> <plain> </plain> <instances> -<instance part="IC1" gate="G$1" x="0" y="15.24"/> +<instance part="IC1" gate="G$1" x="-2.54" y="15.24"/> <instance part="JP1" gate="G$1" x="55.88" y="20.32" rot="R180"/> <instance part="U$1" gate="G$1" x="7.62" y="-10.16"/> -<instance part="R1" gate="G$1" x="-25.4" y="45.72" rot="R90"/> -<instance part="R2" gate="G$1" x="-25.4" y="33.02" rot="R90"/> -<instance part="P+1" gate="VCC" x="-30.48" y="58.42"/> +<instance part="R1" gate="G$1" x="-33.02" y="43.18" rot="R90"/> +<instance part="R2" gate="G$1" x="-33.02" y="30.48" rot="R90"/> <instance part="U$2" gate="G$1" x="-45.72" y="12.7"/> -<instance part="P+2" gate="VCC" x="-38.1" y="45.72"/> -<instance part="GND1" gate="1" x="-38.1" y="2.54"/> -<instance part="D1" gate="G$1" x="-33.02" y="12.7" rot="R90"/> -<instance part="D2" gate="G$1" x="-27.94" y="12.7" rot="R90"/> +<instance part="P+2" gate="VCC" x="-38.1" y="55.88"/> +<instance part="GND1" gate="1" x="-38.1" y="0"/> +<instance part="D1" gate="G$1" x="-33.02" y="10.16" rot="R90"/> +<instance part="D2" gate="G$1" x="-27.94" y="10.16" rot="R90"/> +<instance part="R3" gate="G$1" x="-15.24" y="20.32"/> +<instance part="R4" gate="G$1" x="-22.86" y="22.86"/> </instances> <busses> </busses> @@ -621,37 +623,37 @@ high speed (Philips)</description> </segment> <segment> <pinref part="IC1" gate="G$1" pin="GND"/> -<wire x1="35.56" y1="25.4" x2="40.64" y2="25.4" width="0.1524" layer="91"/> +<wire x1="33.02" y1="25.4" x2="40.64" y2="25.4" width="0.1524" layer="91"/> <label x="35.56" y="25.4" size="1.778" layer="95"/> </segment> <segment> <pinref part="U$2" gate="G$1" pin="GND"/> <pinref part="GND1" gate="1" pin="GND"/> <wire x1="-40.64" y1="15.24" x2="-38.1" y2="15.24" width="0.1524" layer="91"/> -<wire x1="-38.1" y1="15.24" x2="-38.1" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="15.24" x2="-38.1" y2="5.08" width="0.1524" layer="91"/> <pinref part="D1" gate="G$1" pin="A"/> -<wire x1="-38.1" y1="7.62" x2="-38.1" y2="5.08" width="0.1524" layer="91"/> -<wire x1="-33.02" y1="10.16" x2="-33.02" y2="7.62" width="0.1524" layer="91"/> -<wire x1="-33.02" y1="7.62" x2="-38.1" y2="7.62" width="0.1524" layer="91"/> -<junction x="-38.1" y="7.62"/> +<wire x1="-38.1" y1="5.08" x2="-38.1" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="7.62" x2="-33.02" y2="5.08" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="5.08" x2="-38.1" y2="5.08" width="0.1524" layer="91"/> +<junction x="-38.1" y="5.08"/> <pinref part="D2" gate="G$1" pin="A"/> -<wire x1="-27.94" y1="10.16" x2="-27.94" y2="7.62" width="0.1524" layer="91"/> -<wire x1="-27.94" y1="7.62" x2="-33.02" y2="7.62" width="0.1524" layer="91"/> -<junction x="-33.02" y="7.62"/> +<wire x1="-27.94" y1="7.62" x2="-27.94" y2="5.08" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="5.08" x2="-33.02" y2="5.08" width="0.1524" layer="91"/> +<junction x="-33.02" y="5.08"/> </segment> </net> <net name="N$2" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="PB3(RXD)"/> <pinref part="JP1" gate="G$1" pin="RXI"/> -<wire x1="35.56" y1="22.86" x2="50.8" y2="22.86" width="0.1524" layer="91"/> +<wire x1="33.02" y1="22.86" x2="50.8" y2="22.86" width="0.1524" layer="91"/> </segment> </net> <net name="N$3" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="PB2(TXD)"/> <pinref part="JP1" gate="G$1" pin="TXO"/> -<wire x1="35.56" y1="20.32" x2="50.8" y2="20.32" width="0.1524" layer="91"/> +<wire x1="33.02" y1="20.32" x2="50.8" y2="20.32" width="0.1524" layer="91"/> </segment> </net> <net name="VCC" class="0"> @@ -662,23 +664,19 @@ high speed (Philips)</description> </segment> <segment> <pinref part="IC1" gate="G$1" pin="VCC"/> -<wire x1="-5.08" y1="25.4" x2="-10.16" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="25.4" x2="-10.16" y2="25.4" width="0.1524" layer="91"/> <label x="-10.16" y="25.4" size="1.778" layer="95"/> </segment> <segment> -<pinref part="P+1" gate="VCC" pin="VCC"/> -<wire x1="-30.48" y1="25.4" x2="-30.48" y2="53.34" width="0.1524" layer="91"/> -<pinref part="R1" gate="G$1" pin="2"/> -<wire x1="-30.48" y1="53.34" x2="-30.48" y2="55.88" width="0.1524" layer="91"/> -<wire x1="-25.4" y1="50.8" x2="-25.4" y2="53.34" width="0.1524" layer="91"/> -<wire x1="-25.4" y1="53.34" x2="-30.48" y2="53.34" width="0.1524" layer="91"/> -<junction x="-30.48" y="53.34"/> -</segment> -<segment> <pinref part="U$2" gate="G$1" pin="VBUS"/> <pinref part="P+2" gate="VCC" pin="VCC"/> <wire x1="-40.64" y1="25.4" x2="-38.1" y2="25.4" width="0.1524" layer="91"/> -<wire x1="-38.1" y1="25.4" x2="-38.1" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="25.4" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="50.8" x2="-38.1" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="48.26" x2="-33.02" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="50.8" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> +<junction x="-38.1" y="50.8"/> </segment> </net> <net name="N$5" class="0"> @@ -717,41 +715,51 @@ high speed (Philips)</description> <wire x1="33.02" y1="-7.62" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> </segment> </net> -<net name="N$1" class="0"> -<segment> -<pinref part="R2" gate="G$1" pin="1"/> -<wire x1="-25.4" y1="22.86" x2="-25.4" y2="27.94" width="0.1524" layer="91"/> -</segment> -</net> -<net name="N$4" class="0"> -<segment> -<pinref part="R2" gate="G$1" pin="2"/> -<pinref part="R1" gate="G$1" pin="1"/> -<wire x1="-25.4" y1="38.1" x2="-25.4" y2="40.64" width="0.1524" layer="91"/> -</segment> -</net> <net name="N$11" class="0"> <segment> <pinref part="U$2" gate="G$1" pin="D-"/> -<pinref part="IC1" gate="G$1" pin="PA0(TPICLK)"/> <wire x1="-40.64" y1="22.86" x2="-33.02" y2="22.86" width="0.1524" layer="91"/> -<pinref part="D1" gate="G$1" pin="C"/> -<wire x1="-33.02" y1="22.86" x2="-5.08" y2="22.86" width="0.1524" layer="91"/> -<wire x1="-33.02" y1="15.24" x2="-33.02" y2="22.86" width="0.1524" layer="91"/> <junction x="-33.02" y="22.86"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="25.4" x2="-33.02" y2="22.86" width="0.1524" layer="91"/> +<pinref part="D1" gate="G$1" pin="C"/> +<wire x1="-33.02" y1="22.86" x2="-33.02" y2="12.7" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="22.86" x2="-27.94" y2="22.86" width="0.1524" layer="91"/> </segment> </net> <net name="DELTE" class="0"> <segment> <pinref part="U$2" gate="G$1" pin="D+"/> -<pinref part="IC1" gate="G$1" pin="PA1(TPIDATA)"/> <wire x1="-40.64" y1="20.32" x2="-27.94" y2="20.32" width="0.1524" layer="91"/> <pinref part="D2" gate="G$1" pin="C"/> -<wire x1="-27.94" y1="20.32" x2="-5.08" y2="20.32" width="0.1524" layer="91"/> -<wire x1="-27.94" y1="15.24" x2="-27.94" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="12.7" x2="-27.94" y2="20.32" width="0.1524" layer="91"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="-27.94" y1="20.32" x2="-20.32" y2="20.32" width="0.1524" layer="91"/> <junction x="-27.94" y="20.32"/> </segment> </net> +<net name="N$1" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="35.56" x2="-33.02" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R3" gate="G$1" pin="2"/> +<pinref part="IC1" gate="G$1" pin="PA1(TPIDATA)"/> +<wire x1="-10.16" y1="20.32" x2="-7.62" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$12" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="2"/> +<pinref part="IC1" gate="G$1" pin="PA0(TPICLK)"/> +<wire x1="-17.78" y1="22.86" x2="-7.62" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> </nets> </sheet> </sheets> diff --git a/FabFTDI-Attiny102.sch b/FabFTDI-Attiny102.sch index 9532096d087177ed119e1ac6ae3ca0056a9e446d..3cb45540ac1508a35b9384379a678b68202e07a3 100755 --- a/FabFTDI-Attiny102.sch +++ b/FabFTDI-Attiny102.sch @@ -224,46 +224,6 @@ chip</description> <rectangle x1="0.2588" y1="-0.3048" x2="0.5588" y2="0.2951" layer="51"/> <rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/> </package> -<package name="USB-MICROB"> -<description>Micro USB Package</description> -<wire x1="-3.4" y1="-2.15" x2="-3" y2="-2.15" width="0.127" layer="51"/> -<wire x1="3" y1="-2.15" x2="3.4" y2="-2.15" width="0.127" layer="51"/> -<wire x1="-3.4" y1="-2.15" x2="-3.4" y2="-1.45" width="0.127" layer="51"/> -<wire x1="-3.4" y1="-1.45" x2="-3.4" y2="2.85" width="0.127" layer="51"/> -<wire x1="3.4" y1="2.85" x2="2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="3.4" y1="2.85" x2="3.4" y2="-1.45" width="0.127" layer="51"/> -<wire x1="3.4" y1="-1.45" x2="3.4" y2="-2.15" width="0.127" layer="51"/> -<wire x1="-3.4" y1="-1.45" x2="3.4" y2="-1.45" width="0.127" layer="51"/> -<wire x1="-3.4" y1="1.25" x2="-3.4" y2="2.85" width="0.2032" layer="21"/> -<wire x1="-3.4" y1="2.85" x2="-2.2" y2="2.85" width="0.2032" layer="21"/> -<wire x1="3.4" y1="2.85" x2="2.2" y2="2.85" width="0.2032" layer="21"/> -<wire x1="3.4" y1="1.25" x2="3.4" y2="2.85" width="0.2032" layer="21"/> -<wire x1="-3.4" y1="-1.45" x2="3.4" y2="-1.45" width="0.2032" layer="21"/> -<wire x1="-2.2" y1="1.45" x2="2.2" y2="1.45" width="0.127" layer="51"/> -<wire x1="2.2" y1="1.45" x2="2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="-2.2" y1="1.45" x2="-2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="-3.4" y1="2.85" x2="-2.2" y2="2.85" width="0.127" layer="51"/> -<wire x1="-2.2" y1="2.85" x2="-2.2" y2="1.45" width="0.2032" layer="21"/> -<wire x1="-2.2" y1="1.45" x2="2.2" y2="1.45" width="0.2032" layer="21"/> -<wire x1="2.2" y1="1.45" x2="2.2" y2="2.85" width="0.2032" layer="21"/> -<wire x1="-3.4" y1="-2.15" x2="-4" y2="-2.75" width="0.2032" layer="51"/> -<wire x1="3.4" y1="-2.15" x2="4" y2="-2.75" width="0.2032" layer="51"/> -<wire x1="-3" y1="-2.15" x2="-3" y2="-2.55" width="0.127" layer="51"/> -<wire x1="-2.8" y1="-2.8" x2="2.75" y2="-2.8" width="0.127" layer="51"/> -<wire x1="3" y1="-2.6" x2="3" y2="-2.15" width="0.127" layer="51"/> -<wire x1="-3" y1="-2.55" x2="-2.8" y2="-2.8" width="0.127" layer="51" curve="84.547378"/> -<wire x1="2.75" y1="-2.8" x2="3" y2="-2.6" width="0.127" layer="51" curve="84.547378"/> -<smd name="VBUS" x="-1.3" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="GND" x="1.3" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="D-" x="-0.65" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="D+" x="0" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="ID" x="0.65" y="2.65" dx="1.4" dy="0.35" layer="1" rot="R90"/> -<smd name="MT1" x="-4" y="0" dx="1.8" dy="1.9" layer="1"/> -<smd name="MT2" x="4" y="0" dx="1.8" dy="1.9" layer="1"/> -<text x="-1.6" y="-4.16" size="0.762" layer="25">>NAME</text> -<smd name="P$1" x="-1.27" y="0" dx="1.9" dy="1.9" layer="1"/> -<smd name="P$2" x="1.27" y="0" dx="1.9" dy="1.9" layer="1"/> -</package> <package name="SOD123"> <description><b>SMALL OUTLINE DIODE</b></description> <wire x1="-2.973" y1="0.983" x2="2.973" y2="0.983" width="0.0508" layer="39"/> @@ -287,6 +247,21 @@ chip</description> <rectangle x1="1.3716" y1="-0.3048" x2="1.9558" y2="0.3048" layer="51" rot="R180"/> <rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/> </package> +<package name="USB_PCB"> +<description>Card-edge USB A connector. + +For boards designed to be plugged directly into a USB slot. If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="D-" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="D+" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> </packages> <symbols> <symbol name="ATTINY102/104"> @@ -361,22 +336,6 @@ Symbol used in AVR TPI device. <pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> <pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> </symbol> -<symbol name="FAB_USB"> -<wire x1="0" y1="0" x2="0" y2="15.24" width="0.254" layer="94"/> -<wire x1="0" y1="15.24" x2="-5.08" y2="15.24" width="0.254" layer="94"/> -<wire x1="0" y1="0" x2="-5.08" y2="0" width="0.254" layer="94"/> -<pin name="GND" x="5.08" y="2.54" visible="off" length="middle" rot="R180"/> -<pin name="ID" x="5.08" y="5.08" visible="off" length="middle" rot="R180"/> -<pin name="D+" x="5.08" y="7.62" visible="off" length="middle" rot="R180"/> -<pin name="D-" x="5.08" y="10.16" visible="off" length="middle" rot="R180"/> -<pin name="VBUS" x="5.08" y="12.7" visible="off" length="middle" rot="R180"/> -<text x="-7.62" y="5.08" size="2.54" layer="94" rot="MR90">USB</text> -<text x="-5.08" y="12.7" size="1.27" layer="95">VUSB</text> -<text x="-2.54" y="10.16" size="1.27" layer="95">D-</text> -<text x="-2.54" y="7.62" size="1.27" layer="95">D+</text> -<text x="-2.54" y="5.08" size="1.27" layer="95">ID</text> -<text x="-5.08" y="2.54" size="1.27" layer="95">GND</text> -</symbol> <symbol name="DGND"> <wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> <text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> @@ -405,6 +364,20 @@ Symbol used in AVR TPI device. <pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> <pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> </symbol> +<symbol name="USB_PCB"> +<pin name="GND" x="5.08" y="2.54" visible="off" length="middle" rot="R180"/> +<pin name="D+" x="5.08" y="5.08" visible="off" length="middle" rot="R180"/> +<pin name="D-" x="5.08" y="7.62" visible="off" length="middle" rot="R180"/> +<pin name="VUSB" x="5.08" y="10.16" visible="off" length="middle" rot="R180"/> +<wire x1="-5.08" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<wire x1="0" y1="0" x2="0" y2="12.7" width="0.1524" layer="94"/> +<wire x1="0" y1="12.7" x2="-5.08" y2="12.7" width="0.1524" layer="94"/> +<text x="-5.08" y="10.16" size="1.27" layer="95">VUSB</text> +<text x="-2.54" y="7.62" size="1.27" layer="95">D-</text> +<text x="-2.54" y="5.08" size="1.27" layer="95">D+</text> +<text x="-5.08" y="2.54" size="1.27" layer="95">GND</text> +<text x="-5.08" y="2.54" size="2.54" layer="94" rot="R90">USB</text> +</symbol> </symbols> <devicesets> <deviceset name="ATTINY102/104"> @@ -504,25 +477,6 @@ prashant.patil@cba.mit.edu </device> </devices> </deviceset> -<deviceset name="FAB_USB"> -<gates> -<gate name="G$1" symbol="FAB_USB" x="-10.16" y="7.62"/> -</gates> -<devices> -<device name="" package="USB-MICROB"> -<connects> -<connect gate="G$1" pin="D+" pad="D+"/> -<connect gate="G$1" pin="D-" pad="D-"/> -<connect gate="G$1" pin="GND" pad="GND"/> -<connect gate="G$1" pin="ID" pad="ID"/> -<connect gate="G$1" pin="VBUS" pad="VBUS"/> -</connects> -<technologies> -<technology name=""/> -</technologies> -</device> -</devices> -</deviceset> <deviceset name="GND" prefix="GND"> <description><b>SUPPLY SYMBOL</b></description> <gates> @@ -571,6 +525,24 @@ high speed (Philips)</description> </device> </devices> </deviceset> +<deviceset name="USB_PCB"> +<gates> +<gate name="G$1" symbol="USB_PCB" x="-2.54" y="-7.62"/> +</gates> +<devices> +<device name="" package="USB_PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VUSB" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> </devicesets> </library> <library name="FAB_Hello"> @@ -615,7 +587,6 @@ high speed (Philips)</description> <part name="U$1" library="fabPatil" deviceset="AVRTPI" device="SMD" value="AVRTPI"/> <part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> <part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> -<part name="U$2" library="fabPatil" deviceset="FAB_USB" device=""/> <part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> <part name="GND1" library="fabPatil" deviceset="GND" device=""/> <part name="D1" library="fabPatil" deviceset="DIODE" device="SOD123" value="3.3V"/> @@ -632,6 +603,7 @@ high speed (Philips)</description> <part name="GND5" library="fabPatil" deviceset="GND" device=""/> <part name="P+4" library="FAB_Hello" deviceset="VCC" device=""/> <part name="P+5" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="U$3" library="fabPatil" deviceset="USB_PCB" device=""/> </parts> <sheets> <sheet> @@ -643,7 +615,6 @@ high speed (Philips)</description> <instance part="U$1" gate="G$1" x="7.62" y="35.56"/> <instance part="R1" gate="G$1" x="-33.02" y="43.18" rot="R90"/> <instance part="R2" gate="G$1" x="-33.02" y="30.48" rot="R90"/> -<instance part="U$2" gate="G$1" x="-45.72" y="12.7"/> <instance part="P+2" gate="VCC" x="-38.1" y="55.88"/> <instance part="GND1" gate="1" x="-38.1" y="0"/> <instance part="D1" gate="G$1" x="-33.02" y="10.16" rot="R90"/> @@ -660,16 +631,15 @@ high speed (Philips)</description> <instance part="GND5" gate="1" x="50.8" y="30.48"/> <instance part="P+4" gate="VCC" x="81.28" y="22.86"/> <instance part="P+5" gate="VCC" x="0" y="33.02"/> +<instance part="U$3" gate="G$1" x="-45.72" y="15.24"/> </instances> <busses> </busses> <nets> <net name="GND" class="0"> <segment> -<pinref part="U$2" gate="G$1" pin="GND"/> <pinref part="GND1" gate="1" pin="GND"/> -<wire x1="-40.64" y1="15.24" x2="-38.1" y2="15.24" width="0.1524" layer="91"/> -<wire x1="-38.1" y1="15.24" x2="-38.1" y2="5.08" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="17.78" x2="-38.1" y2="5.08" width="0.1524" layer="91"/> <pinref part="D1" gate="G$1" pin="A"/> <wire x1="-38.1" y1="5.08" x2="-38.1" y2="2.54" width="0.1524" layer="91"/> <wire x1="-33.02" y1="7.62" x2="-33.02" y2="5.08" width="0.1524" layer="91"/> @@ -679,6 +649,8 @@ high speed (Philips)</description> <wire x1="-27.94" y1="7.62" x2="-27.94" y2="5.08" width="0.1524" layer="91"/> <wire x1="-27.94" y1="5.08" x2="-33.02" y2="5.08" width="0.1524" layer="91"/> <junction x="-33.02" y="5.08"/> +<pinref part="U$3" gate="G$1" pin="GND"/> +<wire x1="-38.1" y1="17.78" x2="-40.64" y2="17.78" width="0.1524" layer="91"/> </segment> <segment> <pinref part="GND2" gate="1" pin="GND"/> @@ -723,15 +695,15 @@ high speed (Philips)</description> </net> <net name="VCC" class="0"> <segment> -<pinref part="U$2" gate="G$1" pin="VBUS"/> <pinref part="P+2" gate="VCC" pin="VCC"/> -<wire x1="-40.64" y1="25.4" x2="-38.1" y2="25.4" width="0.1524" layer="91"/> <wire x1="-38.1" y1="25.4" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> <pinref part="R1" gate="G$1" pin="2"/> <wire x1="-38.1" y1="50.8" x2="-38.1" y2="53.34" width="0.1524" layer="91"/> <wire x1="-33.02" y1="48.26" x2="-33.02" y2="50.8" width="0.1524" layer="91"/> <wire x1="-33.02" y1="50.8" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> <junction x="-38.1" y="50.8"/> +<pinref part="U$3" gate="G$1" pin="VUSB"/> +<wire x1="-38.1" y1="25.4" x2="-40.64" y2="25.4" width="0.1524" layer="91"/> </segment> <segment> <pinref part="U$1" gate="G$1" pin="VCC"/> @@ -760,8 +732,6 @@ high speed (Philips)</description> </net> <net name="N$11" class="0"> <segment> -<pinref part="U$2" gate="G$1" pin="D-"/> -<wire x1="-40.64" y1="22.86" x2="-33.02" y2="22.86" width="0.1524" layer="91"/> <junction x="-33.02" y="22.86"/> <pinref part="R2" gate="G$1" pin="1"/> <wire x1="-33.02" y1="25.4" x2="-33.02" y2="22.86" width="0.1524" layer="91"/> @@ -769,16 +739,18 @@ high speed (Philips)</description> <wire x1="-33.02" y1="22.86" x2="-33.02" y2="12.7" width="0.1524" layer="91"/> <pinref part="R4" gate="G$1" pin="1"/> <wire x1="-33.02" y1="22.86" x2="-27.94" y2="22.86" width="0.1524" layer="91"/> +<pinref part="U$3" gate="G$1" pin="D-"/> +<wire x1="-33.02" y1="22.86" x2="-40.64" y2="22.86" width="0.1524" layer="91"/> </segment> </net> <net name="DELTE" class="0"> <segment> -<pinref part="U$2" gate="G$1" pin="D+"/> -<wire x1="-40.64" y1="20.32" x2="-27.94" y2="20.32" width="0.1524" layer="91"/> <pinref part="D2" gate="G$1" pin="C"/> <wire x1="-27.94" y1="12.7" x2="-27.94" y2="20.32" width="0.1524" layer="91"/> <pinref part="R3" gate="G$1" pin="1"/> <wire x1="-27.94" y1="20.32" x2="-20.32" y2="20.32" width="0.1524" layer="91"/> +<pinref part="U$3" gate="G$1" pin="D+"/> +<wire x1="-27.94" y1="20.32" x2="-40.64" y2="20.32" width="0.1524" layer="91"/> <junction x="-27.94" y="20.32"/> </segment> </net> diff --git a/eagle.epf b/eagle.epf index e5315b0e1a187e4d59ad3a630fbb887d9fa7324c..32448b1d3062ce4ddfec6a0f24e3a6334f23115f 100755 --- a/eagle.epf +++ b/eagle.epf @@ -355,100 +355,6 @@ UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Librar UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/usb_con-update.lbr" [Win_1] -Type="Schematic Editor" -Loc="0 0 1919 1017" -State=1 -Number=1 -File="FabFTDI-Attiny102.sch" -View="-74.7312 -3.13624 122.144 51.6766" -WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524" -PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" -PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6" -ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0" -ViaDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" -HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" -TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778" -PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27" -PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" 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39.5244 29.803" -WireWidths=" 0.1016 0.127 0.15 0.2 0.2032 0.254 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524 0.3048 0.3556 0.4064" -PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" -PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6" -ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0" -ViaDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" -HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" -TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778" -PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27" -PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" -MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0" 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3e9269cb6434b9b2113a914d77c268610a90cad9..ef69a0287aa50788897622d092fa341f343f2f4c 100755 --- a/index.htm +++ b/index.htm @@ -15,16 +15,16 @@ xmlns="http://www.w3.org/TR/REC-html40"> <o:Author>Prashant Patil</o:Author> <o:Template>Normal</o:Template> <o:LastAuthor>Prashant Patil</o:LastAuthor> - <o:Revision>14</o:Revision> - <o:TotalTime>1380</o:TotalTime> + <o:Revision>17</o:Revision> + <o:TotalTime>1395</o:TotalTime> <o:Created>2017-09-18T23:10:00Z</o:Created> - <o:LastSaved>2017-09-26T23:09:00Z</o:LastSaved> + <o:LastSaved>2017-10-02T02:58:00Z</o:LastSaved> <o:Pages>1</o:Pages> - <o:Words>298</o:Words> - <o:Characters>1704</o:Characters> - <o:Lines>14</o:Lines> - <o:Paragraphs>3</o:Paragraphs> - <o:CharactersWithSpaces>1999</o:CharactersWithSpaces> + <o:Words>417</o:Words> + <o:Characters>2380</o:Characters> + <o:Lines>19</o:Lines> + <o:Paragraphs>5</o:Paragraphs> + <o:CharactersWithSpaces>2792</o:CharactersWithSpaces> <o:Version>16.00</o:Version> </o:DocumentProperties> <o:OfficeDocumentSettings> @@ -675,7 +675,7 @@ xmlns="http://www.w3.org/TR/REC-html40"> margin-right:0in; margin-bottom:8.0pt; margin-left:0in; - line-height:106%; + line-height:105%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri",sans-serif; @@ -698,7 +698,7 @@ h1 margin-bottom:0in; margin-left:0in; margin-bottom:.0001pt; - line-height:106%; + line-height:105%; mso-pagination:widow-orphan lines-together; page-break-after:avoid; mso-outline-level:1; @@ -809,7 +809,8 @@ p.MsoTitleCxSpLast, li.MsoTitleCxSpLast, div.MsoTitleCxSpLast letter-spacing:-.5pt; mso-font-kerning:14.0pt;} a:link, span.MsoHyperlink - {mso-style-priority:99; + {mso-style-noshow:yes; + mso-style-priority:99; color:#0563C1; mso-themecolor:hyperlink; text-decoration:underline; @@ -830,7 +831,7 @@ p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph margin-bottom:8.0pt; margin-left:.5in; mso-add-space:auto; - line-height:106%; + line-height:105%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri",sans-serif; @@ -853,7 +854,7 @@ p.MsoListParagraphCxSpFirst, li.MsoListParagraphCxSpFirst, div.MsoListParagraphC margin-left:.5in; margin-bottom:.0001pt; mso-add-space:auto; - line-height:106%; + line-height:105%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri",sans-serif; @@ -876,7 +877,7 @@ p.MsoListParagraphCxSpMiddle, li.MsoListParagraphCxSpMiddle, div.MsoListParagrap margin-left:.5in; margin-bottom:.0001pt; mso-add-space:auto; - line-height:106%; + line-height:105%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri",sans-serif; @@ -898,7 +899,7 @@ p.MsoListParagraphCxSpLast, li.MsoListParagraphCxSpLast, div.MsoListParagraphCxS margin-bottom:8.0pt; margin-left:.5in; mso-add-space:auto; - line-height:106%; + line-height:105%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri",sans-serif; @@ -1112,12 +1113,12 @@ href="http://ww1.microchip.com/downloads/en/appnotes/atmel-42678-getting-started <p class=MsoNormal>Possible Troubles</p> -<p class=MsoListParagraph style='text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span +<p class=MsoListParagraph style='text-indent:-.25in;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='mso-bidi-font-family:Calibri;mso-bidi-theme-font:minor-latin'><span style='mso-list:Ignore'>1.<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]>TPIDATA and TPICLK pins are shared with USB -D+/D- which have zerner diode to limit it to 3.3V. This may create some -problems. </p> +D+/D- which have zerner diode to limit it to 3.3V. This may create some problems. +</p> <p class=MsoNormal><o:p> </o:p></p> @@ -1143,6 +1144,25 @@ dioes are right. </p> <p class=MsoNormal><o:p> </o:p></p> +<p class=MsoNormal>Update 10-01-2017</p> + +<p class=MsoNormal>Today made the circuit and tried to program it. However, it +failed. Then I removed the 49ohm resistor to disconnect USB line and was able +to program the board. Therefore, the problem is with sharing the TPI pins with +USB. (I swaped the USB pins and RX/TX pins but later realized that it can not +be done as the Rx/Tx pins are fixed and should only be used for Rx/Tx.</p> + +<p class=MsoNormal>I also realized that D- pin is pulled up using 15K resistor +which was connected to TPICLK. Since the D- pin is pulled up and connected to +TPICLK the microcontroller must be receiving any clock and therefore failed to +go into the program mode. The solution is to use the D- pin for one of the +remaining pin which is PB1 and D+ to TPIDATA.</p> + +<p class=MsoNormal>D- is pulled up to indicate to the host that it is a +low-speed device. </p> + +<p class=MsoNormal><o:p> </o:p></p> + </div> </body> diff --git a/old version editing/Board.PNG b/old version editing/Board.PNG new file mode 100755 index 0000000000000000000000000000000000000000..02ca3ba6ccd3c3fa552c889089ea3908386f1078 Binary files /dev/null and b/old version editing/Board.PNG differ diff --git a/old version editing/FabFTDI.b#1 b/old version editing/FabFTDI.b#1 new file mode 100755 index 0000000000000000000000000000000000000000..8a67221329e7c4add82a8f48e21d3ba5da8bbd1f --- /dev/null +++ b/old version editing/FabFTDI.b#1 @@ -0,0 +1,670 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="8.3.2"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting keepoldvectorfont="yes"/> +<setting verticaltext="up"/> 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Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="16mil"/> +<param name="mdWirePad" value="16mil"/> +<param name="mdWireVia" value="16mil"/> +<param name="mdPadPad" value="16mil"/> +<param name="mdPadVia" value="16mil"/> +<param name="mdViaVia" value="16mil"/> +<param name="mdSmdPad" value="16mil"/> +<param name="mdSmdVia" value="16mil"/> +<param name="mdSmdSmd" value="16mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="AutoGrid" value="1"/> +<param name="Efforts" value="0"/> +<param name="TopRouterVariant" value="1"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" 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+<signal name="N$10"> +<contactref element="U$1" pad="6"/> +<contactref element="R5" pad="1"/> +<wire x1="33.888" y1="7.747" x2="38.608" y2="7.747" width="0.4064" layer="1"/> +<wire x1="38.608" y1="7.747" x2="38.608" y2="12.7" width="0.4064" layer="1"/> +<wire x1="38.608" y1="12.7" x2="37.186" y2="12.7" width="0.4064" layer="1"/> +</signal> +<signal name="N$11"> +<contactref element="R6" pad="1"/> +<contactref element="U$1" pad="7"/> +<wire x1="33.888" y1="9.017" x2="37.186" y2="9.017" width="0.4064" layer="1"/> +<wire x1="37.186" y1="9.017" x2="37.186" y2="9.906" width="0.4064" layer="1"/> +</signal> +<signal name="N$12"> +<contactref element="U$1" pad="5"/> +<contactref element="JP1" pad="1"/> +<wire x1="44.276" y1="6.604" x2="44.149" y2="6.477" width="0.4064" layer="1"/> +<wire x1="44.149" y1="6.477" x2="33.888" y2="6.477" width="0.4064" layer="1"/> +</signal> +</signals> +</board> +</drawing> +<compatibility> +<note version="8.3" severity="warning"> +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. +</note> +</compatibility> +</eagle> diff --git a/old version editing/FabFTDI.b#2 b/old version editing/FabFTDI.b#2 new file mode 100755 index 0000000000000000000000000000000000000000..d08d2c15afeaeebd9ce8bc228a63d12cab2f2557 --- /dev/null +++ b/old version editing/FabFTDI.b#2 @@ -0,0 +1,659 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.3"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="10" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="mil"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" 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rot="R180"/> +<rectangle x1="-0.4001" y1="-0.7" x2="0.4001" y2="0.7" layer="35"/> +</package> +<package name="1206"> +<description><b>RESISTOR</b><p> +chip</description> +<wire x1="0.9525" y1="-0.8128" x2="-0.9652" y2="-0.8128" width="0.1524" layer="51"/> +<wire x1="0.9525" y1="0.8128" x2="-0.9652" y2="0.8128" width="0.1524" layer="51"/> +<wire x1="-2.3206" y1="0.983" x2="2.3206" y2="0.983" width="0.0508" layer="39"/> +<wire x1="2.3206" y1="0.983" x2="2.3206" y2="-0.983" width="0.0508" layer="39"/> +<wire x1="2.3206" y1="-0.983" x2="-2.3206" y2="-0.983" width="0.0508" layer="39"/> +<wire x1="-2.3206" y1="-0.983" x2="-2.3206" y2="0.983" width="0.0508" layer="39"/> +<smd name="2" x="1.422" y="0" dx="1.6" dy="1.803" layer="1"/> +<smd name="1" x="-1.422" y="0" dx="1.6" dy="1.803" layer="1"/> +<text x="-1.397" y="1.143" size="1.27" layer="25">>NAME</text> +<text x="-1.397" y="-2.413" size="1.27" layer="27">>VALUE</text> +<rectangle x1="-1.6891" y1="-0.8763" x2="-0.9525" y2="0.8763" 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layer="51"/> +<wire x1="7.62" y1="-1.25" x2="7.62" y2="6.33" width="0.127" layer="51"/> +<smd name="4" x="1.27" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="5" x="3.81" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="6" x="6.35" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="3" x="-1.27" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="2" x="-3.81" y="5" dx="3" dy="1" layer="1" rot="R90"/> +<smd name="1" x="-6.35" y="5" dx="3" dy="1" layer="1" rot="R90"/> +</package> +<package name="USB-A-PCB"> +<description>Card-edge USB A connector. + +For boards designed to be plugged directly into a USB slot. If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="USB_M" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="USB_P" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +</packages> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<designrules name="default"> +<description language="de"><b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" value="1"/> +<param name="cfBase.14" value="1"/> +<param name="cfBase.15" value="1"/> +<param name="cfBase.16" value="0"/> +<param name="mnVias" value="20"/> +<param name="mnSegments" value="9999"/> +<param name="mnExtdSteps" value="9999"/> +<param name="mnRipupLevel" value="10"/> +<param name="mnRipupSteps" value="100"/> +<param name="mnRipupTotal" value="100"/> +</pass> +<pass name="Follow-me" refer="Default" active="yes"> +</pass> +<pass name="Busses" refer="Default" active="yes"> +<param name="cfNonPref" value="4"/> +<param name="cfBusImpact" value="4"/> +<param name="cfHugging" value="0"/> +<param name="mnVias" value="0"/> +</pass> +<pass name="Route" refer="Default" active="yes"> +</pass> +<pass name="Optimize1" refer="Default" active="yes"> +<param name="cfVia" value="99"/> +<param name="cfExtdStep" value="10"/> +<param name="cfHugging" value="1"/> +<param name="mnExtdSteps" value="1"/> +<param name="mnRipupLevel" value="0"/> +</pass> +<pass name="Optimize2" refer="Optimize1" active="yes"> +<param name="cfNonPref" value="0"/> +<param name="cfChangeDir" value="6"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="2"/> +<param name="cfMalusStep" value="2"/> +<param name="cfPadImpact" value="2"/> +<param name="cfSmdImpact" value="2"/> +<param name="cfHugging" value="0"/> +</pass> +<pass name="Optimize3" refer="Optimize2" active="yes"> +<param name="cfChangeDir" value="8"/> +<param name="cfPadImpact" value="0"/> +<param name="cfSmdImpact" value="0"/> +</pass> +<pass name="Optimize4" refer="Optimize3" active="yes"> +<param name="cfChangeDir" value="25"/> +</pass> +</autorouter> +<elements> +<element name="U1" library="fabPatil" package="SO08-EIAJ" value="Tiny45" x="30.607" y="8.636" rot="R270"> +<attribute name="PROD_ID" value="IC-08922" x="30.607" y="8.636" size="1.778" layer="27" rot="R270" display="off"/> +<attribute name="VALUE" value="Tiny45-20-SMT" x="30.607" y="8.636" size="1.778" layer="27" rot="R270" display="off"/> +</element> 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="USB_M" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="USB_P" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +</packages> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<designrules name="default"> +<description language="de"><b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> 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Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> 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Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" value="1"/> +<param name="cfBase.14" value="1"/> +<param name="cfBase.15" value="1"/> +<param name="cfBase.16" value="0"/> +<param name="mnVias" value="20"/> +<param name="mnSegments" value="9999"/> +<param name="mnExtdSteps" value="9999"/> +<param name="mnRipupLevel" value="10"/> +<param name="mnRipupSteps" value="100"/> +<param name="mnRipupTotal" value="100"/> +</pass> +<pass name="Follow-me" refer="Default" active="yes"> +</pass> +<pass name="Busses" refer="Default" active="yes"> +<param name="cfNonPref" value="4"/> +<param name="cfBusImpact" value="4"/> +<param name="cfHugging" value="0"/> +<param name="mnVias" value="0"/> +</pass> +<pass name="Route" refer="Default" active="yes"> +</pass> +<pass name="Optimize1" refer="Default" active="yes"> +<param name="cfVia" value="99"/> +<param name="cfExtdStep" value="10"/> +<param name="cfHugging" value="1"/> +<param name="mnExtdSteps" value="1"/> +<param name="mnRipupLevel" value="0"/> +</pass> +<pass name="Optimize2" refer="Optimize1" active="yes"> +<param name="cfNonPref" value="0"/> +<param name="cfChangeDir" value="6"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="2"/> +<param name="cfMalusStep" value="2"/> +<param name="cfPadImpact" value="2"/> +<param name="cfSmdImpact" value="2"/> +<param name="cfHugging" value="0"/> +</pass> +<pass name="Optimize3" refer="Optimize2" active="yes"> +<param name="cfChangeDir" value="8"/> +<param name="cfPadImpact" value="0"/> +<param name="cfSmdImpact" value="0"/> +</pass> +<pass name="Optimize4" refer="Optimize3" active="yes"> +<param name="cfChangeDir" value="25"/> +</pass> +</autorouter> +<elements> +<element name="U1" library="fabPatil" package="SO08-EIAJ" value="Tiny45-20-SMT" x="30.607" y="8.636" rot="R270"> +<attribute name="PROD_ID" value="IC-08922" x="30.607" y="8.636" size="1.778" layer="27" rot="R270" display="off"/> +<attribute name="VALUE" value="Tiny45-20-SMT" x="30.607" y="8.636" size="1.778" layer="27" rot="R270" display="off"/> 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="USB_M" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="USB_P" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +</packages> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<designrules name="default"> +<description language="de"><b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="USB_M" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="USB_P" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +</packages> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<designrules name="default"> +<description language="de"><b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" 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Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-5" y1="6" x2="3.7" y2="6" width="0.127" layer="51"/> +<wire x1="3.7" y1="6" x2="3.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="3.7" y1="-6" x2="-5" y2="-6" width="0.127" layer="51"/> +<wire x1="-5" y1="-6" x2="-5" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="-0.2" y="-3.5" dx="7.5" dy="1.5" layer="1"/> +<smd name="USB_M" x="0.3" y="-1" dx="6.5" dy="1" layer="1"/> +<smd name="USB_P" x="0.3" y="1" dx="6.5" dy="1" layer="1"/> +<smd name="GND" x="-0.2" y="3.5" dx="7.5" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +<text x="-6.35" y="-3.81" size="1.016" layer="48" rot="R90">Card edge</text> +</package> +</packages> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<designrules name="default"> +<description language="de"><b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" value="1"/> +<param name="cfBase.14" value="1"/> +<param name="cfBase.15" value="1"/> +<param name="cfBase.16" value="0"/> +<param name="mnVias" value="20"/> +<param name="mnSegments" value="9999"/> +<param name="mnExtdSteps" value="9999"/> +<param name="mnRipupLevel" value="10"/> +<param name="mnRipupSteps" value="100"/> +<param name="mnRipupTotal" value="100"/> +</pass> +<pass name="Follow-me" refer="Default" active="yes"> +</pass> +<pass name="Busses" refer="Default" active="yes"> +<param name="cfNonPref" value="4"/> +<param name="cfBusImpact" value="4"/> +<param name="cfHugging" value="0"/> +<param name="mnVias" value="0"/> +</pass> +<pass name="Route" refer="Default" active="yes"> +</pass> +<pass name="Optimize1" refer="Default" active="yes"> +<param name="cfVia" value="99"/> +<param name="cfExtdStep" value="10"/> +<param name="cfHugging" value="1"/> +<param name="mnExtdSteps" value="1"/> +<param name="mnRipupLevel" value="0"/> +</pass> +<pass name="Optimize2" refer="Optimize1" active="yes"> +<param name="cfNonPref" value="0"/> +<param name="cfChangeDir" value="6"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="2"/> +<param name="cfMalusStep" value="2"/> +<param name="cfPadImpact" value="2"/> +<param name="cfSmdImpact" value="2"/> +<param name="cfHugging" value="0"/> +</pass> +<pass name="Optimize3" refer="Optimize2" active="yes"> +<param name="cfChangeDir" value="8"/> +<param name="cfPadImpact" value="0"/> +<param name="cfSmdImpact" value="0"/> +</pass> +<pass name="Optimize4" refer="Optimize3" active="yes"> +<param name="cfChangeDir" value="25"/> +</pass> +</autorouter> +<elements> +<element name="U1" library="fabPatil" package="SO08-EIAJ" value="Tiny45-20-SMT" x="30.607" y="8.636" rot="R270"> +<attribute name="PROD_ID" value="IC-08922" x="30.607" y="8.636" size="1.778" layer="27" rot="R270" display="off"/> +<attribute name="VALUE" value="Tiny45-20-SMT" x="30.607" y="8.636" size="1.778" layer="27" rot="R270" display="off"/> +</element> +<element name="D1" library="fabPatil" package="SOD123" value="" x="14.605" y="14.986" rot="R90"/> +<element name="D2" library="fabPatil" package="SOD123" value="" x="17.653" y="12.827" rot="R90"/> +<element name="R1" library="fabPatil" package="1206" value="49" x="22.225" y="11.049"/> +<element name="R2" library="fabPatil" package="1206" value="49" x="14.478" y="8.763" rot="R270"/> +<element name="R3" library="fabPatil" package="1206" value="499" x="22.225" y="14.859"/> +<element name="R4" library="fabPatil" package="1206" value="1K" x="22.225" y="18.542" rot="R180"/> +<element name="U$2" library="fabPatil" package="2X03SMD" value="AVRISPSMD" x="30.734" y="17.272" rot="R270"/> +<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="44.196" y="12.954" rot="R90"/> +<element name="C1" library="fabPatil" package="1206" value="0.1uF" x="17.526" y="20.066" rot="R90"/> +<element name="JP2" library="fabPatil" package="USB-A-PCB" value="USBPCB" x="2.286" y="13.97"/> +</elements> +<signals> +<signal name="GND"> +<contactref element="U1" pad="4"/> +<contactref element="D1" pad="ANODE"/> +<contactref element="D2" pad="ANODE"/> +<contactref element="U$2" pad="6"/> +<contactref element="JP1" pad="6"/> +<wire x1="39.196" y1="19.304" x2="39.37" y2="19.304" width="0.4064" layer="1"/> +<contactref element="C1" pad="1"/> +<contactref element="JP2" pad="GND"/> +<wire x1="28.194" y1="14.352" x2="28.194" y2="12.954" width="0.4064" layer="1"/> +<wire x1="28.194" y1="12.954" x2="22.352" y2="12.954" width="0.4064" layer="1"/> +<wire x1="22.352" y1="12.954" x2="22.352" y2="16.764" width="0.4064" layer="1"/> +<wire x1="17.653" y1="14.527" x2="17.653" y2="16.764" width="0.4064" layer="1"/> +<wire x1="17.653" y1="16.764" x2="14.429" y2="16.764" width="0.4064" layer="1"/> +<wire x1="14.429" y1="16.764" x2="14.605" y2="16.686" width="0.4064" layer="1" curve="90"/> +<wire x1="27.2288" y1="6.731" x2="22.352" y2="6.731" width="0.4064" layer="1"/> +<wire x1="22.352" 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="D-" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="D+" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +<package name="SOIC8" urn="urn:adsk.eagle:footprint:4165/1" locally_modified="yes"> +<description><B>Wide Plastic Gull Wing Small Outline Package</B></description> +<wire x1="-2.6" y1="2.25" x2="-2.35" y2="2.5" width="0.1524" layer="21" curve="-90"/> +<wire x1="2.35" y1="2.5" x2="2.6" y2="2.25" width="0.1524" layer="21" curve="-90"/> +<wire x1="2.35" y1="-2.5" x2="2.6" y2="-2.25" width="0.1524" layer="21" curve="90"/> +<wire x1="-2.6" y1="-2.25" x2="-2.35" y2="-2.5" width="0.1524" layer="21" curve="90"/> +<wire x1="2.36" y1="-2.5" x2="-2.34" y2="-2.5" width="0.1524" layer="51"/> +<wire x1="-2.34" y1="2.5" x2="2.36" y2="2.5" width="0.1524" layer="51"/> +<wire x1="-2.21" y1="2.5" x2="-2.34" y2="2.5" width="0.1524" layer="21"/> +<wire x1="-1.59" y1="2.5" x2="-0.95" y2="2.5" width="0.1524" layer="21"/> +<wire x1="-0.32" y1="2.5" x2="0.32" y2="2.5" width="0.1524" layer="21"/> +<wire x1="0.95" y1="2.5" x2="1.59" y2="2.5" width="0.1524" layer="21"/> +<wire x1="2.21" y1="2.5" x2="2.36" y2="2.5" width="0.1524" layer="21"/> +<wire x1="2.2" y1="-2.5" x2="2.33" y2="-2.5" width="0.1524" layer="21"/> +<wire x1="1.59" y1="-2.5" x2="0.94" y2="-2.5" width="0.1524" layer="21"/> +<wire x1="0.32" y1="-2.5" x2="-0.33" y2="-2.5" width="0.1524" layer="21"/> +<wire x1="-0.95" y1="-2.5" x2="-1.59" y2="-2.5" width="0.1524" layer="21"/> +<wire x1="-2.21" y1="-2.5" x2="-2.34" y2="-2.5" width="0.1524" layer="21"/> +<wire x1="-2.6" y1="2.25" x2="-2.6" y2="-2.24" width="0.1524" layer="21"/> +<wire x1="2.6" y1="-2.25" x2="2.6" y2="2.25" width="0.1524" layer="21"/> +<circle x="-1.42" y="-1.115" radius="0.5" width="0.0508" layer="21"/> +<smd name="1" x="-1.905" y="-3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="2" x="-0.645" y="-3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="3" x="0.625" y="-3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="4" x="1.895" y="-3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="8" x="-1.905" y="3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="7" x="-0.635" y="3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="6" x="0.635" y="3.154" dx="0.5" dy="2.2" layer="1"/> +<smd name="5" x="1.905" y="3.154" dx="0.5" dy="2.2" layer="1"/> +<text x="-2.8575" y="-2.159" size="1.27" layer="25" ratio="10" rot="R90">>NAME</text> +<text x="4.064" y="-2.159" size="1.27" layer="27" ratio="10" rot="R90">>VALUE</text> +<rectangle x1="-2.08" y1="2.5" x2="-1.73" y2="3.4" layer="51"/> +<rectangle x1="-0.81" y1="2.5" x2="-0.46" y2="3.4" layer="51"/> +<rectangle x1="0.46" y1="2.5" x2="0.81" y2="3.4" layer="51"/> +<rectangle x1="1.73" y1="2.5" x2="2.08" y2="3.4" layer="51"/> +<rectangle x1="1.72" y1="-3.4" x2="2.07" y2="-2.5" layer="51"/> +<rectangle x1="0.45" y1="-3.4" x2="0.8" y2="-2.5" layer="51"/> +<rectangle x1="-0.82" y1="-3.4" x2="-0.47" y2="-2.5" layer="51"/> +<rectangle x1="-2.08" y1="-3.4" x2="-1.73" y2="-2.5" layer="51"/> +</package> +<package name="2X03SMD"> +<smd name="1" x="-2.54" y="2.54" dx="2.54" dy="1.27" layer="1"/> +<smd name="3" x="-2.54" y="0" dx="2.54" dy="1.27" layer="1"/> +<smd name="5" x="-2.54" y="-2.54" dx="2.54" dy="1.27" layer="1"/> +<smd name="2" x="2.92" y="2.54" dx="2.54" dy="1.27" layer="1"/> +<smd name="4" x="2.92" y="0" dx="2.54" dy="1.27" layer="1"/> +<smd name="6" x="2.92" y="-2.54" dx="2.54" dy="1.27" layer="1"/> +<text x="-5.08" y="2.54" size="1.27" layer="27">1</text> +<text x="-3.81" y="3.81" size="1.27" layer="21">>NAME</text> +<text x="-3.81" y="-5.08" size="1.27" layer="21">>VALUE</text> +</package> +</packages> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<designrules name="Patil"> +<description language="de"><b>EAGLE Design Rules</b> +<p> +Die Standard-Design-Rules sind so gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="16mil"/> +<param name="mdWirePad" value="16mil"/> +<param name="mdWireVia" value="16mil"/> +<param name="mdPadPad" value="16mil"/> +<param name="mdPadVia" value="16mil"/> +<param name="mdViaVia" value="16mil"/> +<param name="mdSmdPad" value="16mil"/> +<param name="mdSmdVia" value="16mil"/> +<param name="mdSmdSmd" value="16mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="24mil"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="AutoGrid" value="1"/> +<param name="Efforts" value="0"/> +<param name="TopRouterVariant" value="1"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" value="1"/> +<param name="cfBase.14" value="1"/> +<param name="cfBase.15" value="1"/> +<param name="cfBase.16" value="0"/> +<param name="mnVias" value="20"/> +<param name="mnSegments" value="9999"/> +<param name="mnExtdSteps" value="9999"/> +<param name="mnRipupLevel" value="10"/> +<param name="mnRipupSteps" value="100"/> +<param name="mnRipupTotal" value="100"/> +</pass> +<pass name="Follow-me" refer="Default" active="yes"> +</pass> +<pass name="Busses" refer="Default" active="yes"> +<param name="cfNonPref" value="4"/> +<param name="cfBusImpact" value="4"/> +<param name="cfHugging" value="0"/> +<param name="mnVias" value="0"/> +</pass> +<pass name="Route" refer="Default" active="yes"> +</pass> +<pass name="Optimize1" refer="Default" active="yes"> +<param name="cfVia" value="99"/> +<param name="cfExtdStep" value="10"/> +<param name="cfHugging" value="1"/> +<param name="mnExtdSteps" value="1"/> +<param name="mnRipupLevel" value="0"/> +</pass> +<pass name="Optimize2" refer="Optimize1" active="yes"> +<param name="cfNonPref" value="0"/> +<param name="cfChangeDir" value="6"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="2"/> +<param name="cfMalusStep" value="2"/> +<param name="cfPadImpact" value="2"/> +<param name="cfSmdImpact" value="2"/> +<param name="cfHugging" value="0"/> +</pass> +<pass name="Optimize3" refer="Optimize2" active="yes"> +<param name="cfChangeDir" value="8"/> +<param name="cfPadImpact" value="0"/> +<param name="cfSmdImpact" value="0"/> +</pass> +<pass name="Optimize4" refer="Optimize3" active="yes"> +<param name="cfChangeDir" value="25"/> +</pass> +</autorouter> +<elements> +<element name="D1" library="fabPatil" package="SOD123" value="3.3V" x="14.605" y="14.986" rot="R90"/> +<element name="D2" library="fabPatil" package="SOD123" value="3.3V" x="17.653" y="12.827" rot="R90"/> +<element name="R1" library="fabPatil" package="1206" value="49" x="22.352" y="9.525"/> +<element name="R2" library="fabPatil" package="1206" value="49" x="14.478" y="8.763" rot="R270"/> +<element name="R3" library="fabPatil" package="1206" value="499" x="22.225" y="13.589"/> +<element name="R4" library="fabPatil" package="1206" value="1K" x="22.352" y="18.288" rot="R90"/> +<element name="JP1" library="fabPatil" package="1X06-SMD" value="" x="42.164" y="13.97" rot="R90"/> +<element name="C1" library="fabPatil" package="1206" value="0.1uF" x="17.526" y="20.066" rot="R90"/> +<element name="JP2" library="fabPatil" package="USB_PCB" value="USBPCB" x="1.27" y="13.97"/> +<element name="R5" library="fabPatil" package="1206" value="470" x="38.608" y="12.7"/> +<element name="R6" library="fabPatil" package="1206" value="470" x="38.608" y="9.906"/> +<element name="U$1" library="fabPatil" package="SOIC8" value="ATTINY102/104" x="29.845" y="8.255" rot="R90"/> +<element name="U$2" library="fabPatil" package="2X03SMD" value="AVRTPISMD" x="30.48" y="16.51" rot="R90"/> +</elements> +<signals> +<signal name="GND"> +<contactref element="D1" pad="ANODE"/> +<contactref element="D2" pad="ANODE"/> +<contactref element="JP1" pad="6"/> +<contactref element="C1" pad="1"/> +<contactref element="JP2" pad="GND"/> +<wire x1="17.653" y1="16.764" x2="17.653" y2="14.527" width="0.4064" layer="1"/> +<wire x1="17.653" y1="16.764" x2="14.429" y2="16.764" width="0.4064" layer="1"/> +<wire x1="14.429" y1="16.764" x2="14.605" y2="16.686" width="0.4064" layer="1" curve="90"/> +<wire x1="17.653" y1="16.764" x2="17.678" y2="16.789" width="0.4064" layer="1"/> +<wire x1="17.678" y1="16.789" x2="17.678" y2="18.644" width="0.4064" layer="1"/> +<wire x1="17.678" y1="18.644" x2="17.526" y2="18.644" width="0.4064" layer="1"/> +<wire x1="41.91" y1="23.368" x2="14.605" y2="23.368" width="0.4064" layer="1"/> +<wire x1="14.605" y1="23.368" x2="14.605" y2="17.526" width="0.4064" layer="1"/> +<wire x1="14.605" y1="17.526" x2="14.605" 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severity="warning"> +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. +</note> +</compatibility> +</eagle> diff --git a/old version editing/FabFTDI.s#1 b/old version editing/FabFTDI.s#1 new file mode 100755 index 0000000000000000000000000000000000000000..7209479a2159d196a088371b5d423248338bc1c8 --- /dev/null +++ b/old version editing/FabFTDI.s#1 @@ -0,0 +1,1514 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="8.3.2"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting keepoldvectorfont="yes"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" 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layer="95">>NAME</text> +<text x="-3.81" y="-3.302" size="1.778" layer="96">>VALUE</text> +<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +</symbol> +<symbol name="ARDUINO_SERIAL_PROGRAM"> +<wire x1="1.27" y1="-7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="0" x2="0" y2="0" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-2.54" x2="0" y2="-2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-5.08" x2="0" y2="-5.08" width="0.6096" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="1.27" y1="-7.62" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="5.08" x2="0" y2="5.08" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="2.54" x2="0" y2="2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="7.62" x2="0" y2="7.62" width="0.6096" layer="94"/> +<text x="-5.08" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="10.922" size="1.778" layer="95">>NAME</text> +<pin name="DTR" x="5.08" y="-5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="RXI" x="5.08" y="-2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="TXO" x="5.08" y="0" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="VCC" x="5.08" y="2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="CTS" x="5.08" y="5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="GND" x="5.08" y="7.62" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="USB-1"> +<wire x1="5.08" y1="8.89" x2="0" y2="8.89" width="0.254" layer="94"/> +<wire x1="0" y1="8.89" x2="0" y2="-1.27" width="0.254" layer="94"/> +<wire x1="0" y1="-1.27" x2="5.08" y2="-1.27" width="0.254" layer="94"/> +<text x="3.81" y="0" size="2.54" layer="94" rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +<symbol name="ATTINY102/104"> +<description><h3> ATTINY102/104 </h3> +<p> Symbol for Atmel Attiny102/104</p></description> +<wire x1="0" y1="0" x2="0" y2="12.7" width="0.254" layer="94"/> +<wire x1="0" y1="12.7" x2="30.48" y2="12.7" width="0.254" layer="94"/> +<wire x1="30.48" y1="12.7" x2="30.48" y2="0" width="0.254" layer="94"/> +<wire x1="30.48" y1="0" x2="0" y2="0" width="0.254" layer="94"/> +<pin name="VCC" x="-5.08" y="10.16" length="middle"/> +<pin name="PA0(TPICLK)" x="-5.08" y="7.62" length="middle"/> +<pin name="PA1(TPIDATA)" x="-5.08" y="5.08" length="middle"/> +<pin name="PA2(RESET)" x="-5.08" y="2.54" length="middle"/> +<pin name="GND" x="35.56" y="10.16" length="middle" rot="R180"/> +<pin name="PB3(RXD)" x="35.56" y="7.62" length="middle" rot="R180"/> +<pin name="PB2(TXD)" x="35.56" y="5.08" length="middle" rot="R180"/> +<pin name="PB1" x="35.56" y="2.54" length="middle" rot="R180"/> +<text x="0" y="12.7" size="1.27" layer="95">AT102</text> +<text x="0" y="-2.54" size="1.27" layer="96">>VALUE</text> +</symbol> +<symbol name="DGND"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +<symbol name="AVRTPI"> +<description><h3>Symbol for ATMEL TPI Connector </h3> +<p> +Symbol used in AVR TPI device. + +- Prashant Patil </p></description> +<wire x1="0" y1="0" x2="20.32" y2="0" width="0.4064" layer="94"/> +<wire x1="20.32" y1="0" x2="20.32" y2="10.16" width="0.4064" layer="94"/> +<wire x1="20.32" y1="10.16" x2="0" y2="10.16" width="0.4064" layer="94"/> +<wire x1="0" y1="10.16" x2="0" y2="0" width="0.4064" layer="94"/> +<text x="1.27" y="10.795" size="1.778" layer="95">>NAME</text> +<text x="1.27" y="-2.54" size="1.778" layer="96">AVRTPI</text> +<pin name="TPIDATA" x="-5.08" y="7.62" visible="pin" length="middle"/> +<pin name="TPICLK" x="-5.08" y="5.08" visible="pin" length="middle"/> +<pin name="RESET" x="-5.08" y="2.54" visible="pin" length="middle"/> +<pin name="VCC" x="25.4" y="7.62" visible="pin" length="middle" rot="R180"/> +<pin name="(NC)" x="25.4" y="5.08" visible="pin" length="middle" rot="R180"/> +<pin name="GND" x="25.4" y="2.54" visible="pin" length="middle" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><b>USB Connectors</b> +<p>USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278 +<p>USB-miniB is fully proven SKU : PRT-00587 +<p>USB-A-PCB is untested. +<p>USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437 +<p>USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up. +<p>USB-A-S has not been used/tested +<p>USB-MB-H has not been used/tested +<P>USB-MICROB has been used. CONN-09505</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D-"/> +<connect gate="G$1" pin="D-" pad="D+"/> +<connect gate="G$1" pin="GND" pad="VBUS"/> +<connect gate="G$1" pin="VBUS" pad="GND"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-H" package="USB-MB-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH" package="USB-B-PTH"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08278" constant="no"/> +<attribute name="VALUE" value="USB-B" constant="no"/> +</technology> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB-A-PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="USB_P"/> +<connect gate="G$1" pin="D-" pad="USB_M"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH-VERTICAL" package="USB-B-PTH-VERTICAL"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="USB-A-S-NOSILK" package="USB-A-S-NOSILK"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-SMD" package="USB-A-S-NOSILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09520"/> +</technology> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_" package="USB-A-S-SILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +<device name="A-SMD-MALE" package="USB-A-SMT-MALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="A-SMD-MALE-LOCKING" package="USB-A-SMT-MALE-LOCKING"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ATTINY102/104"> +<description><h3>ATTINY102/104</h3> +<p>Device for ATTINY102/104 </p></description> +<gates> +<gate name="G$1" symbol="ATTINY102/104" x="-15.24" y="-5.08"/> +</gates> +<devices> +<device name="" package="SOIC8"> +<connects> +<connect gate="G$1" pin="GND" pad="8"/> +<connect gate="G$1" pin="PA0(TPICLK)" pad="2"/> +<connect gate="G$1" pin="PA1(TPIDATA)" pad="3"/> +<connect gate="G$1" pin="PA2(RESET)" pad="4"/> +<connect gate="G$1" pin="PB1" pad="5"/> +<connect gate="G$1" pin="PB2(TXD)" pad="6"/> +<connect gate="G$1" pin="PB3(RXD)" pad="7"/> +<connect gate="G$1" pin="VCC" pad="1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="DGND" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRTPI"> +<description><h3> ATMEL-ICE TPI Connector SMD</h3> +<p> + +This is a TPI programming connector to program Atiny102/104 micro-controllers +prashant.patil@cba.mit.edu + +</p></description> +<gates> +<gate name="G$1" symbol="AVRTPI" x="-2.54" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="(NC)" pad="4"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RESET" pad="5"/> +<connect gate="G$1" pin="TPICLK" pad="3"/> +<connect gate="G$1" pin="TPIDATA" pad="1"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="JP2" library="fabPatil" deviceset="USB" device="PCB"/> +<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +<part name="R6" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +<part name="U$1" library="fabPatil" deviceset="ATTINY102/104" device=""/> +<part name="P+3" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="P+4" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND4" library="fabPatil" deviceset="GND" device=""/> +<part name="GND5" library="fabPatil" deviceset="GND" device=""/> +<part name="U$2" library="fabPatil" deviceset="AVRTPI" device="SMD"/> +<part name="P+5" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND6" library="fabPatil" deviceset="GND" device=""/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="P+1" gate="VCC" x="-38.1" y="-10.16" rot="R90"/> +<instance part="GND1" gate="1" x="-17.78" y="-10.16" rot="R90"/> +<instance part="GND2" gate="1" x="-71.12" y="22.86" rot="R270"/> +<instance part="D1" gate="1" x="-60.96" y="0" rot="R90"/> +<instance part="D2" gate="1" x="-66.04" y="0" rot="R90"/> +<instance part="GND3" gate="1" x="-71.12" y="-7.62" rot="R270"/> +<instance part="R1" gate="G$1" x="-55.88" y="10.16"/> +<instance part="R2" gate="G$1" x="-53.34" y="7.62"/> +<instance part="P+2" gate="VCC" x="-53.34" y="38.1" rot="R270"/> +<instance part="R3" gate="G$1" x="-63.5" y="17.78" rot="R90"/> +<instance part="R4" gate="G$1" x="-63.5" y="30.48" rot="R90"/> +<instance part="JP1" gate="G$1" x="43.18" y="7.62" rot="R180"/> +<instance part="C1" gate="1" x="-30.48" y="-10.16" rot="R180"/> +<instance part="JP2" gate="G$1" x="-76.2" y="15.24" rot="R180"/> +<instance part="R5" gate="G$1" x="15.24" y="7.62"/> +<instance part="R6" gate="G$1" x="22.86" y="10.16"/> +<instance part="U$1" gate="G$1" x="-30.48" y="2.54"/> +<instance part="P+3" gate="VCC" x="55.88" y="10.16"/> +<instance part="P+4" gate="VCC" x="-38.1" y="20.32"/> +<instance part="GND4" gate="1" x="10.16" y="17.78"/> +<instance part="GND5" gate="1" x="55.88" y="-7.62"/> +<instance part="U$2" gate="G$1" x="-30.48" y="22.86"/> +<instance part="P+5" gate="VCC" x="-2.54" y="38.1"/> +<instance part="GND6" gate="1" x="-2.54" y="20.32"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="GND1" gate="1" pin="GND"/> +<label x="-22.86" y="-7.62" size="1.778" layer="95" rot="R90"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-20.32" y1="-10.16" x2="-25.4" y2="-10.16" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="-68.58" y1="15.24" x2="-68.58" y2="22.86" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +<pinref part="JP2" gate="G$1" pin="GND"/> +<wire x1="-73.66" y1="15.24" x2="-68.58" y2="15.24" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="-60.96" y1="-2.54" x2="-60.96" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="-60.96" y1="-7.62" x2="-66.04" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="-66.04" y1="-7.62" x2="-68.58" y2="-7.62" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="-2.54" x2="-66.04" y2="-7.62" width="0.1524" layer="91"/> +<junction x="-66.04" y="-7.62"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="38.1" y1="0" x2="35.56" y2="0" width="0.1524" layer="91"/> +<pinref part="GND5" gate="1" pin="GND"/> +<wire x1="38.1" y1="0" x2="55.88" y2="0" width="0.1524" layer="91"/> +<wire x1="55.88" y1="0" x2="55.88" y2="-5.08" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="GND"/> +<wire x1="5.08" y1="12.7" x2="5.08" y2="20.32" width="0.1524" layer="91"/> +<pinref part="GND4" gate="1" pin="GND"/> +<wire x1="5.08" y1="20.32" x2="10.16" y2="20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<pinref part="GND6" gate="1" pin="GND"/> +<wire x1="-5.08" y1="25.4" x2="-2.54" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="25.4" x2="-2.54" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="-55.88" y1="38.1" x2="-63.5" y2="38.1" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="-63.5" y1="38.1" x2="-63.5" y2="35.56" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="12.7" x2="-66.04" y2="12.7" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="12.7" x2="-66.04" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="38.1" x2="-63.5" y2="38.1" width="0.1524" layer="91"/> +<junction x="-63.5" y="38.1"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<pinref part="P+3" gate="VCC" pin="VCC"/> +<wire x1="38.1" y1="5.08" x2="55.88" y2="5.08" width="0.1524" layer="91"/> +<wire x1="55.88" y1="5.08" x2="55.88" y2="7.62" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="VCC"/> +<pinref part="P+4" gate="VCC" pin="VCC"/> +<wire x1="-35.56" y1="12.7" x2="-38.1" y2="12.7" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="12.7" x2="-38.1" y2="17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<pinref part="P+5" gate="VCC" pin="VCC"/> +<wire x1="-5.08" y1="30.48" x2="-2.54" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="30.48" x2="-2.54" y2="35.56" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-33.02" y1="-10.16" x2="-35.56" y2="-10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<wire x1="-73.66" y1="10.16" x2="-66.04" y2="10.16" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="-66.04" y1="2.54" x2="-66.04" y2="10.16" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="-66.04" y1="10.16" x2="-60.96" y2="10.16" width="0.1524" layer="91"/> +<junction x="-66.04" y="10.16"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="-63.5" y1="12.7" x2="-66.04" y2="10.16" width="0.1524" layer="91"/> +<pinref part="JP2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="-60.96" y1="2.54" x2="-60.96" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="7.62" x2="-60.96" y2="7.62" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="-58.42" y1="7.62" x2="-60.96" y2="7.62" width="0.1524" layer="91"/> +<junction x="-60.96" y="7.62"/> +<pinref part="JP2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<pinref part="U$1" gate="G$1" pin="PA0(TPICLK)"/> +<wire x1="-35.56" y1="10.16" x2="-43.18" y2="10.16" width="0.1524" layer="91"/> +<pinref part="U$2" gate="G$1" pin="TPICLK"/> +<wire x1="-43.18" y1="10.16" x2="-50.8" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-35.56" y1="27.94" x2="-43.18" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="27.94" x2="-43.18" y2="10.16" width="0.1524" layer="91"/> +<junction x="-43.18" y="10.16"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="-63.5" y1="25.4" x2="-63.5" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<pinref part="U$1" gate="G$1" pin="PA1(TPIDATA)"/> +<wire x1="-35.56" y1="7.62" x2="-45.72" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U$2" gate="G$1" pin="TPIDATA"/> +<wire x1="-45.72" y1="7.62" x2="-48.26" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-35.56" y1="30.48" x2="-45.72" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="30.48" x2="-45.72" y2="7.62" width="0.1524" layer="91"/> +<junction x="-45.72" y="7.62"/> +</segment> +</net> +<net name="N$7" class="0"> +<segment> +<pinref part="R6" gate="G$1" pin="2"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="27.94" y1="10.16" x2="38.1" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$8" class="0"> +<segment> +<pinref part="R5" gate="G$1" pin="2"/> +<pinref part="JP1" gate="G$1" pin="TXO"/> +<wire x1="20.32" y1="7.62" x2="38.1" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$9" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RESET"/> +<wire x1="-35.56" y1="25.4" x2="-40.64" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="25.4" x2="-40.64" y2="5.08" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="PA2(RESET)"/> +<wire x1="-40.64" y1="5.08" x2="-35.56" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$10" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="PB2(TXD)"/> +<pinref part="R5" gate="G$1" pin="1"/> +<wire x1="5.08" y1="7.62" x2="10.16" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$11" class="0"> +<segment> +<pinref part="R6" gate="G$1" pin="1"/> +<pinref part="U$1" gate="G$1" pin="PB3(RXD)"/> +<wire x1="17.78" y1="10.16" x2="5.08" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$12" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="PB1"/> +<wire x1="5.08" y1="5.08" x2="27.94" y2="5.08" width="0.1524" layer="91"/> +<wire x1="27.94" y1="5.08" x2="35.56" y2="12.7" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="DTR"/> +<wire x1="35.56" y1="12.7" x2="38.1" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +<compatibility> +<note version="8.3" severity="warning"> +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. +</note> +</compatibility> +</eagle> diff --git a/old version editing/FabFTDI.s#2 b/old version editing/FabFTDI.s#2 new file mode 100755 index 0000000000000000000000000000000000000000..889aa097592850ecb9fdca6000862a55e98fd6c9 --- /dev/null +++ b/old version editing/FabFTDI.s#2 @@ -0,0 +1,1506 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.3"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> +<layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/> +<layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/> +<layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/> +<layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/> +<layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/> +<layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/> +<layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/> +<layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/> +<layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/> +<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/> +<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/> +<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/> +<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/> +<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/> +<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/> +<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/> +<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/> +<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/> +<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/> +<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/> 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Mini-B Surface Mounted</b></description> +<wire x1="-1.5" y1="3.8" x2="0.9" y2="3.8" width="0.127" layer="21"/> +<wire x1="3.3" y1="3.1" x2="3.3" y2="2.1" width="0.127" layer="21"/> +<wire x1="3.3" y1="-2.1" x2="3.3" y2="-3.1" width="0.127" layer="21"/> +<wire x1="1" y1="-3.8" x2="-1.5" y2="-3.8" width="0.127" layer="21"/> +<wire x1="-5.9" y1="3.8" x2="-5.9" y2="-3.8" width="0.127" layer="51"/> +<wire x1="-5.9" y1="-3.8" x2="-4.5" y2="-3.8" width="0.127" layer="51"/> +<wire x1="-5.9" y1="3.8" x2="-4.5" y2="3.8" width="0.127" layer="51"/> +<smd name="1" x="-3" y="-4.5" dx="2.5" dy="2" layer="1"/> +<smd name="2" x="-3" y="4.5" dx="2.5" dy="2" layer="1"/> +<smd name="3" x="3" y="-4.5" dx="3.5" dy="2" layer="1"/> +<smd name="4" x="3" y="4.5" dx="3.5" dy="2" layer="1"/> +<smd name="D+" x="3" y="0" dx="3.5" dy="0.5" layer="1"/> +<smd name="D-" x="3" y="0.8" dx="3.5" dy="0.5" layer="1"/> +<smd name="VBUS" x="3.01" y="1.61" dx="3.5" dy="0.5" layer="1"/> +<smd name="ID" x="3" y="-0.8" dx="3.5" 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name="3" x="1" y="-4.7" dx="1" dy="4.6" layer="1"/> +<smd name="4" x="3" y="-4.7" dx="1" dy="4.6" layer="1"/> +<smd name="P$1" x="-5.4" y="0.5" dx="3.4" dy="1.6" layer="1" rot="R90"/> +<smd name="P$2" x="5.4" y="0.5" dx="3.4" dy="1.6" layer="1" rot="R90"/> +</package> +<package name="USB-MINIB"> +<description><b>USB Series Mini-B Surface Mounted</b></description> +<wire x1="-1.3" y1="3.8" x2="0.8" y2="3.8" width="0.2032" layer="21"/> +<wire x1="3.3" y1="3.1" x2="3.3" y2="2.2" width="0.2032" layer="21"/> +<wire x1="3.3" y1="-2.2" x2="3.3" y2="-3.1" width="0.2032" layer="21"/> +<wire x1="0.8" y1="-3.8" x2="-1.3" y2="-3.8" width="0.2032" layer="21"/> +<wire x1="-5.9" y1="3.8" x2="-5.9" y2="-3.8" width="0.2032" layer="51"/> +<wire x1="-5.9" y1="-3.8" x2="-4.5" y2="-3.8" width="0.2032" layer="51"/> +<wire x1="-5.9" y1="3.8" x2="-4.5" y2="3.8" width="0.2032" layer="51"/> +<smd name="D+" x="2.5" y="0" dx="2.5" dy="0.5" layer="1"/> +<smd name="D-" x="2.5" y="0.8" dx="2.5" dy="0.5" layer="1"/> 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="USB_M" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="USB_P" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +<package name="USB-B-PTH-VERTICAL"> +<description><b>USB Series B Hole Mounted</b></description> +<wire x1="0" y1="0" x2="11.938" y2="0" width="0.254" layer="21"/> +<wire x1="11.938" y1="0" x2="11.938" y2="11.303" width="0.254" layer="21"/> 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y2="2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="7.62" x2="0" y2="7.62" width="0.6096" layer="94"/> +<text x="-5.08" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="10.922" size="1.778" layer="95">>NAME</text> +<pin name="DTR" x="5.08" y="-5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="RXI" x="5.08" y="-2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="TXO" x="5.08" y="0" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="VCC" x="5.08" y="2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="CTS" x="5.08" y="5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="GND" x="5.08" y="7.62" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> 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rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><b>USB Connectors</b> +<p>USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278 +<p>USB-miniB is fully proven SKU : PRT-00587 +<p>USB-A-PCB is untested. +<p>USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437 +<p>USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up. +<p>USB-A-S has not been used/tested +<p>USB-MB-H has not been used/tested +<P>USB-MICROB has been used. CONN-09505</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D-"/> +<connect gate="G$1" pin="D-" pad="D+"/> +<connect gate="G$1" pin="GND" pad="VBUS"/> +<connect gate="G$1" pin="VBUS" pad="GND"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-H" package="USB-MB-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH" package="USB-B-PTH"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08278" constant="no"/> +<attribute name="VALUE" value="USB-B" constant="no"/> +</technology> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB-A-PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="USB_P"/> +<connect gate="G$1" pin="D-" pad="USB_M"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH-VERTICAL" package="USB-B-PTH-VERTICAL"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="USB-A-S-NOSILK" package="USB-A-S-NOSILK"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-SMD" package="USB-A-S-NOSILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09520"/> +</technology> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_" package="USB-A-S-SILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +<device name="A-SMD-MALE" package="USB-A-SMT-MALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="A-SMD-MALE-LOCKING" package="USB-A-SMT-MALE-LOCKING"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD" value="ISP"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="JP2" library="fabPatil" deviceset="USB" device="PCB"/> +<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +<part name="R6" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-17.78" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-7.62" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="-5.08" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-15.24" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-15.24" rot="R180"/> +<instance part="U$2" gate="G$1" x="73.66" y="-15.24"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +<instance part="C1" gate="1" x="-12.7" y="10.16" rot="R90"/> +<instance part="JP2" gate="G$1" x="30.48" y="-27.94" rot="R270"/> +<instance part="R5" gate="G$1" x="45.72" y="12.7"/> +<instance part="R6" gate="G$1" x="55.88" y="15.24"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-7.62" y1="2.54" x2="-12.7" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="2.54" x2="-12.7" y2="5.08" width="0.1524" layer="91"/> +<junction x="-7.62" y="2.54"/> +</segment> +<segment> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +<pinref part="JP2" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-25.4" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-17.78" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-17.78" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<junction x="53.34" y="-17.78"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="78.74" y1="-17.78" x2="88.9" y2="-17.78" width="0.1524" layer="91"/> +<label x="83.82" y="-17.78" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +<wire x1="-7.62" y1="15.24" x2="-12.7" y2="15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="15.24"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-12.7" y1="15.24" x2="-12.7" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-15.24" x2="10.16" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-25.4" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<junction x="7.62" y="-15.24"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="78.74" y1="-12.7" x2="88.9" y2="-12.7" width="0.1524" layer="91"/> +<label x="83.82" y="-12.7" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<wire x1="35.56" y1="-25.4" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-17.78" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-17.78" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<junction x="35.56" y="-17.78"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-15.24" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="JP2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="38.1" y1="-25.4" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-10.16" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<junction x="38.1" y="-12.7"/> +<pinref part="JP2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" y1="-2.54" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB3(ADC3)"/> +<wire x1="35.56" y1="7.62" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="20.32" y1="-15.24" x2="22.86" y2="-15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MISO" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MISO"/> +<wire x1="71.12" y1="-12.7" x2="60.96" y2="-12.7" width="0.1524" layer="91"/> +<label x="60.96" y="-12.7" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB1(MISO)"/> +<label x="27.94" y="12.7" size="1.778" layer="95"/> +<pinref part="R5" gate="G$1" pin="1"/> +<wire x1="40.64" y1="12.7" x2="25.4" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SCK" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="SCK"/> +<wire x1="71.12" y1="-15.24" x2="60.96" y2="-15.24" width="0.1524" layer="91"/> +<label x="60.96" y="-15.24" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB2(SCK/ADC1)"/> +<label x="27.94" y="10.16" size="1.778" layer="95"/> +<wire x1="25.4" y1="10.16" x2="38.1" y2="10.16" width="0.1524" layer="91"/> +<wire x1="38.1" y1="10.16" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<pinref part="R6" gate="G$1" pin="1"/> +<wire x1="50.8" y1="15.24" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="RST" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RST"/> +<wire x1="71.12" y1="-17.78" x2="60.96" y2="-17.78" width="0.1524" layer="91"/> +<label x="60.96" y="-17.78" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB5(NRES)"/> +<label x="27.94" y="2.54" size="1.778" layer="95"/> +<wire x1="25.4" y1="2.54" x2="53.34" y2="2.54" width="0.1524" layer="91"/> +<wire x1="53.34" y1="2.54" x2="53.34" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="53.34" y1="7.62" x2="63.5" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MOSI" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MOSI"/> +<wire x1="78.74" y1="-15.24" x2="88.9" y2="-15.24" width="0.1524" layer="91"/> +<label x="83.82" y="-15.24" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB0(MOSI)"/> +<wire x1="25.4" y1="15.24" x2="35.56" y2="15.24" width="0.1524" layer="91"/> +<label x="27.94" y="15.24" size="1.778" layer="95"/> +<wire x1="35.56" y1="15.24" x2="35.56" y2="17.78" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="DTR"/> +<wire x1="35.56" y1="17.78" x2="63.5" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<wire x1="38.1" y1="0" x2="38.1" y2="5.08" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB4(ADC2)"/> +<wire x1="38.1" y1="5.08" x2="25.4" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$7" class="0"> +<segment> +<pinref part="R6" gate="G$1" pin="2"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="60.96" y1="15.24" x2="63.5" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$8" class="0"> +<segment> +<pinref part="R5" gate="G$1" pin="2"/> +<pinref part="JP1" gate="G$1" pin="TXO"/> +<wire x1="50.8" y1="12.7" x2="63.5" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> diff --git a/old version editing/FabFTDI.s#3 b/old version editing/FabFTDI.s#3 new file mode 100755 index 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rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><b>USB Connectors</b> +<p>USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278 +<p>USB-miniB is fully proven SKU : PRT-00587 +<p>USB-A-PCB is untested. +<p>USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437 +<p>USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up. +<p>USB-A-S has not been used/tested +<p>USB-MB-H has not been used/tested +<P>USB-MICROB has been used. CONN-09505</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D-"/> +<connect gate="G$1" pin="D-" pad="D+"/> +<connect gate="G$1" pin="GND" pad="VBUS"/> +<connect gate="G$1" pin="VBUS" pad="GND"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-H" package="USB-MB-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH" package="USB-B-PTH"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08278" constant="no"/> +<attribute name="VALUE" value="USB-B" constant="no"/> +</technology> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB-A-PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="USB_P"/> +<connect gate="G$1" pin="D-" pad="USB_M"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH-VERTICAL" package="USB-B-PTH-VERTICAL"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="USB-A-S-NOSILK" package="USB-A-S-NOSILK"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-SMD" package="USB-A-S-NOSILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09520"/> +</technology> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_" package="USB-A-S-SILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +<device name="A-SMD-MALE" package="USB-A-SMT-MALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="A-SMD-MALE-LOCKING" package="USB-A-SMT-MALE-LOCKING"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="JP2" library="fabPatil" deviceset="USB" device="PCB"/> +<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +<part name="R6" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-17.78" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-7.62" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="-5.08" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-15.24" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-15.24" rot="R180"/> +<instance part="U$2" gate="G$1" x="40.64" y="33.02"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +<instance part="C1" gate="1" x="-12.7" y="10.16" rot="R90"/> +<instance part="JP2" gate="G$1" x="30.48" y="-27.94" rot="R270"/> +<instance part="R5" gate="G$1" x="45.72" y="12.7"/> +<instance part="R6" gate="G$1" x="55.88" y="15.24"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-7.62" y1="2.54" x2="-12.7" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="2.54" x2="-12.7" y2="5.08" width="0.1524" layer="91"/> +<junction x="-7.62" y="2.54"/> +</segment> +<segment> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +<pinref part="JP2" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-25.4" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-17.78" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-17.78" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<junction x="53.34" y="-17.78"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="45.72" y1="30.48" x2="55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +<wire x1="-7.62" y1="15.24" x2="-12.7" y2="15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="15.24"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-12.7" y1="15.24" x2="-12.7" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-15.24" x2="10.16" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-25.4" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<junction x="7.62" y="-15.24"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-4" y1="6" x2="7.7" y2="6" width="0.127" layer="51"/> +<wire x1="7.7" y1="6" x2="7.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="7.7" y1="-6" x2="-4" y2="-6" width="0.127" layer="51"/> +<wire x1="-4" y1="-6" x2="-4" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="1.55" y="-3.5" dx="11" dy="1.5" layer="1"/> +<smd name="USB_M" x="2.05" y="-1" dx="10" dy="1" layer="1"/> +<smd name="USB_P" x="2.05" y="1" dx="10" dy="1" layer="1"/> +<smd name="GND" x="1.55" y="3.5" dx="11" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +</package> +<package name="USB-B-PTH-VERTICAL"> +<description><b>USB Series B Hole Mounted</b></description> +<wire x1="0" y1="0" x2="11.938" y2="0" width="0.254" layer="21"/> +<wire x1="11.938" y1="0" x2="11.938" y2="11.303" width="0.254" layer="21"/> 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layer="94"/> +<wire x1="8.89" y1="5.08" x2="-6.35" y2="5.08" width="0.4064" layer="94"/> +<wire x1="-6.35" y1="5.08" x2="-6.35" y2="-5.08" width="0.4064" layer="94"/> +<text x="-6.35" y="5.715" size="1.778" layer="95">>NAME</text> +<text x="-6.35" y="-7.62" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="3.175" size="1.27" layer="95">MISO</text> +<text x="-5.08" y="0.635" size="1.27" layer="95">SCK</text> +<text x="-5.08" y="-1.905" size="1.27" layer="95">RST</text> +<text x="7.62" y="3.175" size="1.27" layer="95" rot="MR0">VCC</text> +<text x="7.62" y="0.635" size="1.27" layer="95" rot="MR0">MOSI</text> +<text x="7.62" y="-1.905" size="1.27" layer="95" rot="MR0">GND</text> +<pin name="MISO" x="-2.54" y="2.54" visible="off" length="short" direction="pas" function="dot"/> +<pin name="VCC" x="5.08" y="2.54" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="SCK" x="-2.54" y="0" visible="off" length="short" direction="pas" function="dot"/> +<pin name="MOSI" x="5.08" y="0" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="RST" x="-2.54" y="-2.54" visible="off" length="short" direction="pas" function="dot"/> +<pin name="GND" x="5.08" y="-2.54" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +</symbol> +<symbol name="ARDUINO_SERIAL_PROGRAM"> +<wire x1="1.27" y1="-7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="0" x2="0" y2="0" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-2.54" x2="0" y2="-2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-5.08" x2="0" y2="-5.08" width="0.6096" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="1.27" y1="-7.62" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="5.08" x2="0" y2="5.08" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="2.54" x2="0" y2="2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="7.62" x2="0" y2="7.62" width="0.6096" layer="94"/> +<text x="-5.08" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="10.922" size="1.778" layer="95">>NAME</text> +<pin name="DTR" x="5.08" y="-5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="RXI" x="5.08" y="-2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="TXO" x="5.08" y="0" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="VCC" x="5.08" y="2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="CTS" x="5.08" y="5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="GND" x="5.08" y="7.62" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="USB-1"> +<wire x1="5.08" y1="8.89" x2="0" y2="8.89" width="0.254" layer="94"/> +<wire x1="0" y1="8.89" x2="0" y2="-1.27" width="0.254" layer="94"/> +<wire x1="0" y1="-1.27" x2="5.08" y2="-1.27" width="0.254" layer="94"/> +<text x="3.81" y="0" size="2.54" layer="94" rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><b>USB Connectors</b> +<p>USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278 +<p>USB-miniB is fully proven SKU : PRT-00587 +<p>USB-A-PCB is untested. +<p>USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437 +<p>USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up. +<p>USB-A-S has not been used/tested +<p>USB-MB-H has not been used/tested +<P>USB-MICROB has been used. CONN-09505</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D-"/> +<connect gate="G$1" pin="D-" pad="D+"/> +<connect gate="G$1" pin="GND" pad="VBUS"/> +<connect gate="G$1" pin="VBUS" pad="GND"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-H" package="USB-MB-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH" package="USB-B-PTH"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08278" constant="no"/> +<attribute name="VALUE" value="USB-B" constant="no"/> +</technology> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB-A-PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="USB_P"/> +<connect gate="G$1" pin="D-" pad="USB_M"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH-VERTICAL" package="USB-B-PTH-VERTICAL"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="USB-A-S-NOSILK" package="USB-A-S-NOSILK"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-SMD" package="USB-A-S-NOSILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09520"/> +</technology> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_" package="USB-A-S-SILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +<device name="A-SMD-MALE" package="USB-A-SMT-MALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="A-SMD-MALE-LOCKING" package="USB-A-SMT-MALE-LOCKING"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> 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layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-15.24" x2="10.16" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-25.4" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<junction x="7.62" y="-15.24"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<wire x1="35.56" y1="-25.4" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-17.78" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-17.78" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<junction x="35.56" y="-17.78"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-15.24" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="JP2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="38.1" y1="-25.4" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-10.16" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<junction x="38.1" y="-12.7"/> +<pinref part="JP2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" 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y1="33.02" x2="27.94" y2="33.02" width="0.1524" layer="91"/> +<label x="27.94" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB2(SCK/ADC1)"/> +<label x="27.94" y="10.16" size="1.778" layer="95"/> +<wire x1="25.4" y1="10.16" x2="38.1" y2="10.16" width="0.1524" layer="91"/> +<wire x1="38.1" y1="10.16" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="38.1" y1="15.24" x2="63.5" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="RST" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RST"/> +<wire x1="38.1" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/> +<label x="27.94" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB5(NRES)"/> +<label x="27.94" y="2.54" size="1.778" layer="95"/> +<wire x1="25.4" y1="2.54" x2="53.34" y2="2.54" width="0.1524" layer="91"/> +<wire x1="53.34" y1="2.54" x2="53.34" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="53.34" y1="7.62" x2="63.5" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MOSI" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MOSI"/> +<wire x1="45.72" y1="33.02" x2="55.88" y2="33.02" width="0.1524" layer="91"/> +<label x="50.8" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB0(MOSI)"/> +<wire x1="25.4" y1="15.24" x2="35.56" y2="15.24" width="0.1524" layer="91"/> +<label x="27.94" y="15.24" size="1.778" layer="95"/> +<wire x1="35.56" y1="15.24" x2="35.56" y2="17.78" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="DTR"/> +<wire x1="35.56" y1="17.78" x2="63.5" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<wire x1="38.1" y1="0" x2="38.1" y2="5.08" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB4(ADC2)"/> +<wire x1="38.1" y1="5.08" x2="25.4" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> diff --git a/old version editing/FabFTDI.s#5 b/old version editing/FabFTDI.s#5 new file mode 100755 index 0000000000000000000000000000000000000000..34b145705ac1cf1ed9122571d270092f17f9a2c9 --- /dev/null +++ b/old version editing/FabFTDI.s#5 @@ -0,0 +1,1489 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.3"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" 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drill="1.4"/> +<hole x="0" y="-2.25" drill="1.4"/> +</package> +<package name="USB-MINIB-OLD"> +<description><b>USB Series Mini-B Surface Mounted</b></description> +<wire x1="-1.5" y1="3.8" x2="0.9" y2="3.8" width="0.127" layer="21"/> +<wire x1="3.3" y1="3.1" x2="3.3" y2="2.1" width="0.127" layer="21"/> +<wire x1="3.3" y1="-2.1" x2="3.3" y2="-3.1" width="0.127" layer="21"/> +<wire x1="1" y1="-3.8" x2="-1.5" y2="-3.8" width="0.127" layer="21"/> +<wire x1="-5.9" y1="3.8" x2="-5.9" y2="-3.8" width="0.127" layer="51"/> +<wire x1="-5.9" y1="-3.8" x2="-4.5" y2="-3.8" width="0.127" layer="51"/> +<wire x1="-5.9" y1="3.8" x2="-4.5" y2="3.8" width="0.127" layer="51"/> +<smd name="1" x="-3" y="-4.5" dx="2.5" dy="2" layer="1"/> +<smd name="2" x="-3" y="4.5" dx="2.5" dy="2" layer="1"/> +<smd name="3" x="3" y="-4.5" dx="3.5" dy="2" layer="1"/> +<smd name="4" x="3" y="4.5" dx="3.5" dy="2" layer="1"/> +<smd name="D+" x="3" y="0" dx="3.5" dy="0.5" layer="1"/> +<smd name="D-" x="3" y="0.8" dx="3.5" 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layer="51"/> +<smd name="1" x="-3" y="-4.7" dx="1" dy="4.6" layer="1"/> +<smd name="2" x="-1" y="-4.7" dx="1" dy="4.6" layer="1"/> +<smd name="3" x="1" y="-4.7" dx="1" dy="4.6" layer="1"/> +<smd name="4" x="3" y="-4.7" dx="1" dy="4.6" layer="1"/> +<smd name="P$1" x="-5.4" y="0.5" dx="3.4" dy="1.6" layer="1" rot="R90"/> +<smd name="P$2" x="5.4" y="0.5" dx="3.4" dy="1.6" layer="1" rot="R90"/> +</package> +<package name="USB-MINIB"> +<description><b>USB Series Mini-B Surface Mounted</b></description> +<wire x1="-1.3" y1="3.8" x2="0.8" y2="3.8" width="0.2032" layer="21"/> +<wire x1="3.3" y1="3.1" x2="3.3" y2="2.2" width="0.2032" layer="21"/> +<wire x1="3.3" y1="-2.2" x2="3.3" y2="-3.1" width="0.2032" layer="21"/> +<wire x1="0.8" y1="-3.8" x2="-1.3" y2="-3.8" width="0.2032" layer="21"/> +<wire x1="-5.9" y1="3.8" x2="-5.9" y2="-3.8" width="0.2032" layer="51"/> +<wire x1="-5.9" y1="-3.8" x2="-4.5" y2="-3.8" width="0.2032" layer="51"/> +<wire x1="-5.9" y1="3.8" x2="-4.5" y2="3.8" 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If possible, ensure that your PCB is about 2.4mm thick to fit snugly.</description> +<wire x1="-5" y1="6" x2="3.7" y2="6" width="0.127" layer="51"/> +<wire x1="3.7" y1="6" x2="3.7" y2="-6" width="0.127" layer="51" style="shortdash"/> +<wire x1="3.7" y1="-6" x2="-5" y2="-6" width="0.127" layer="51"/> +<wire x1="-5" y1="-6" x2="-5" y2="6" width="0.127" layer="51"/> +<smd name="5V" x="-0.2" y="-3.5" dx="7.5" dy="1.5" layer="1"/> +<smd name="USB_M" x="0.3" y="-1" dx="6.5" dy="1" layer="1"/> +<smd name="USB_P" x="0.3" y="1" dx="6.5" dy="1" layer="1"/> +<smd name="GND" x="-0.2" y="3.5" dx="7.5" dy="1.5" layer="1"/> +<text x="-1.27" y="5.08" size="0.4064" layer="25">>Name</text> +<text x="-1.27" y="-5.08" size="0.4064" layer="27">>Value</text> +<text x="-6.35" y="-3.81" size="1.016" layer="48" rot="R90">Card edge</text> +</package> +<package name="USB-B-PTH-VERTICAL"> +<description><b>USB Series B Hole Mounted</b></description> +<wire x1="0" y1="0" x2="11.938" y2="0" width="0.254" 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name="SCK" x="-2.54" y="0" visible="off" length="short" direction="pas" function="dot"/> +<pin name="MOSI" x="5.08" y="0" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="RST" x="-2.54" y="-2.54" visible="off" length="short" direction="pas" function="dot"/> +<pin name="GND" x="5.08" y="-2.54" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +</symbol> +<symbol name="ARDUINO_SERIAL_PROGRAM"> +<wire x1="1.27" y1="-7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="0" x2="0" y2="0" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-2.54" x2="0" y2="-2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-5.08" x2="0" y2="-5.08" width="0.6096" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="1.27" y1="-7.62" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-1.27" 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name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="USB-1"> +<wire x1="5.08" y1="8.89" x2="0" y2="8.89" width="0.254" layer="94"/> +<wire x1="0" y1="8.89" x2="0" y2="-1.27" width="0.254" layer="94"/> +<wire x1="0" y1="-1.27" x2="5.08" y2="-1.27" width="0.254" layer="94"/> +<text x="3.81" y="0" size="2.54" layer="94" rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><b>USB Connectors</b> +<p>USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278 +<p>USB-miniB is fully proven SKU : PRT-00587 +<p>USB-A-PCB is untested. +<p>USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437 +<p>USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up. +<p>USB-A-S has not been used/tested +<p>USB-MB-H has not been used/tested +<P>USB-MICROB has been used. CONN-09505</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D-"/> +<connect gate="G$1" pin="D-" pad="D+"/> +<connect gate="G$1" pin="GND" pad="VBUS"/> +<connect gate="G$1" pin="VBUS" pad="GND"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-H" package="USB-MB-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH" package="USB-B-PTH"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08278" constant="no"/> +<attribute name="VALUE" value="USB-B" constant="no"/> +</technology> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB-A-PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="USB_P"/> +<connect gate="G$1" pin="D-" pad="USB_M"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH-VERTICAL" package="USB-B-PTH-VERTICAL"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="USB-A-S-NOSILK" package="USB-A-S-NOSILK"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-SMD" package="USB-A-S-NOSILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09520"/> +</technology> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_" package="USB-A-S-SILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +<device name="A-SMD-MALE" package="USB-A-SMT-MALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="A-SMD-MALE-LOCKING" package="USB-A-SMT-MALE-LOCKING"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="JP2" library="fabPatil" deviceset="USB" device="PCB"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-17.78" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-7.62" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="-5.08" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-15.24" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-15.24" rot="R180"/> +<instance part="U$2" gate="G$1" x="40.64" y="33.02"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +<instance part="C1" gate="1" x="-12.7" y="10.16" rot="R90"/> +<instance part="JP2" gate="G$1" x="30.48" y="-27.94" rot="R270"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-7.62" y1="2.54" x2="-12.7" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="2.54" x2="-12.7" y2="5.08" width="0.1524" layer="91"/> +<junction x="-7.62" y="2.54"/> +</segment> +<segment> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +<pinref part="JP2" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-25.4" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-17.78" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-17.78" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<junction x="53.34" y="-17.78"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="45.72" y1="30.48" x2="55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +<wire x1="-7.62" y1="15.24" x2="-12.7" y2="15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="15.24"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-12.7" y1="15.24" x2="-12.7" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-15.24" x2="10.16" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-25.4" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<junction x="7.62" y="-15.24"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<wire x1="35.56" y1="-25.4" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-17.78" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-17.78" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<junction x="35.56" y="-17.78"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-15.24" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="JP2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="38.1" y1="-25.4" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-10.16" x2="38.1" y2="-12.7" width="0.1524" layer="91"/> +<junction x="38.1" y="-12.7"/> +<pinref part="JP2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" y1="-2.54" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB3(ADC3)"/> +<wire x1="35.56" y1="7.62" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="20.32" y1="-15.24" x2="22.86" y2="-15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MISO" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MISO"/> +<wire x1="38.1" y1="35.56" x2="27.94" y2="35.56" width="0.1524" layer="91"/> +<label x="27.94" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB1(MISO)"/> +<label x="27.94" y="12.7" size="1.778" layer="95"/> +<pinref part="JP1" gate="G$1" pin="TXO"/> +<wire x1="63.5" y1="12.7" x2="25.4" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SCK" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="SCK"/> +<wire x1="38.1" y1="33.02" x2="27.94" y2="33.02" width="0.1524" layer="91"/> +<label x="27.94" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB2(SCK/ADC1)"/> +<label x="27.94" y="10.16" size="1.778" layer="95"/> +<wire x1="25.4" y1="10.16" x2="38.1" y2="10.16" width="0.1524" layer="91"/> +<wire x1="38.1" y1="10.16" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="38.1" y1="15.24" x2="63.5" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="RST" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RST"/> +<wire x1="38.1" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/> +<label x="27.94" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB5(NRES)"/> +<label x="27.94" y="2.54" size="1.778" layer="95"/> +<wire x1="25.4" y1="2.54" x2="53.34" y2="2.54" width="0.1524" layer="91"/> +<wire x1="53.34" y1="2.54" x2="53.34" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="53.34" y1="7.62" x2="63.5" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MOSI" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MOSI"/> +<wire x1="45.72" y1="33.02" x2="55.88" y2="33.02" width="0.1524" layer="91"/> +<label x="50.8" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB0(MOSI)"/> +<wire x1="25.4" y1="15.24" x2="35.56" y2="15.24" width="0.1524" layer="91"/> +<label x="27.94" y="15.24" size="1.778" layer="95"/> +<wire x1="35.56" y1="15.24" x2="35.56" y2="17.78" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="DTR"/> +<wire x1="35.56" y1="17.78" x2="63.5" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<wire x1="38.1" y1="0" x2="38.1" y2="5.08" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB4(ADC2)"/> +<wire x1="38.1" y1="5.08" x2="25.4" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> diff --git a/old version editing/FabFTDI.s#6 b/old version editing/FabFTDI.s#6 new file mode 100755 index 0000000000000000000000000000000000000000..f3a503df49391b99d2d56135f6078a9f935a9a27 --- /dev/null +++ b/old version editing/FabFTDI.s#6 @@ -0,0 +1,1488 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.3"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> +<layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/> +<layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/> +<layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/> +<layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/> +<layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/> +<layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/> +<layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/> +<layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/> +<layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/> +<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/> 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y2="-1.27" width="0.254" layer="94"/> +<text x="3.81" y="0" size="2.54" layer="94" rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><b>USB Connectors</b> +<p>USB-B-PTH is fully proven SKU : PRT-00139/CONN-08278 +<p>USB-miniB is fully proven SKU : PRT-00587 +<p>USB-A-PCB is untested. +<p>USB-A-H is throughly reviewed, but untested. Spark Fun Electronics SKU : PRT-00437 +<p>USB-B-SMT is throughly reviewed, but untested. Needs silkscreen touching up. +<p>USB-A-S has not been used/tested +<p>USB-MB-H has not been used/tested +<P>USB-MICROB has been used. CONN-09505</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D-"/> +<connect gate="G$1" pin="D-" pad="D+"/> +<connect gate="G$1" pin="GND" pad="VBUS"/> +<connect gate="G$1" pin="VBUS" pad="GND"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-H" package="USB-MB-H"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH" package="USB-B-PTH"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08278" constant="no"/> +<attribute name="VALUE" value="USB-B" constant="no"/> +</technology> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB-A-PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="USB_P"/> +<connect gate="G$1" pin="D-" pad="USB_M"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH-VERTICAL" package="USB-B-PTH-VERTICAL"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="USB-A-S-NOSILK" package="USB-A-S-NOSILK"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-SMD" package="USB-A-S-NOSILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09520"/> +</technology> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_" package="USB-A-S-SILK-FEMALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +<device name="A-SMD-MALE" package="USB-A-SMT-MALE"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="A-SMD-MALE-LOCKING" package="USB-A-SMT-MALE-LOCKING"> +<connects> +<connect gate="G$1" pin="D+" pad="D+1"/> +<connect gate="G$1" pin="D-" pad="D-1"/> +<connect gate="G$1" pin="GND" pad="GND1"/> +<connect gate="G$1" pin="VBUS" pad="VBUS1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="JP2" library="fabPatil" deviceset="USB" device="PCB"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-7.62" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-2.54" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="0" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-12.7" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-12.7" rot="R180"/> +<instance part="U$2" gate="G$1" x="40.64" y="33.02"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +<instance part="C1" gate="1" x="-12.7" y="10.16" rot="R90"/> +<instance part="JP2" gate="G$1" x="30.48" y="-27.94" rot="R270"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-7.62" y1="2.54" x2="-12.7" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="2.54" x2="-12.7" y2="5.08" width="0.1524" layer="91"/> +<junction x="-7.62" y="2.54"/> +</segment> +<segment> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +<pinref part="JP2" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-25.4" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-7.62" x2="53.34" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-7.62" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<junction x="53.34" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="45.72" y1="30.48" x2="55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +<wire x1="-7.62" y1="15.24" x2="-12.7" y2="15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="15.24"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-12.7" y1="15.24" x2="-12.7" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-12.7" x2="10.16" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-25.4" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<junction x="7.62" y="-12.7"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<wire x1="35.56" y1="-25.4" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-12.7" x2="35.56" y2="-7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="-12.7"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="JP2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-7.62" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<wire x1="38.1" y1="-25.4" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-5.08" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<junction x="38.1" y="-7.62"/> +<pinref part="JP2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" y1="2.54" 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x1="1.27" y1="-7.62" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="5.08" x2="0" y2="5.08" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="2.54" x2="0" y2="2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="7.62" x2="0" y2="7.62" width="0.6096" layer="94"/> +<text x="-5.08" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="10.922" size="1.778" layer="95">>NAME</text> +<pin name="DTR" x="5.08" y="-5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="RXI" x="5.08" y="-2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="TXO" x="5.08" y="0" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="VCC" x="5.08" y="2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="CTS" x="5.08" y="5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="GND" x="5.08" y="7.62" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB_MINIB"> +<gates> +<gate name="G$1" symbol="USB" x="0" y="0"/> +</gates> +<devices> +<device name="" package="USB_MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="U$1" library="fabPatil" deviceset="USB_MINIB" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="1uF"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="U$1" gate="G$1" x="35.56" y="-25.4" rot="R270"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-7.62" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-2.54" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="0" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-12.7" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-12.7" rot="R180"/> +<instance part="U$2" gate="G$1" x="40.64" y="33.02"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +<instance part="C1" gate="1" x="-12.7" y="10.16" rot="R90"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-7.62" y1="2.54" x2="-12.7" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="2.54" x2="-12.7" y2="5.08" width="0.1524" layer="91"/> +<junction x="-7.62" y="2.54"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-22.86" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-7.62" x2="53.34" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-7.62" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<junction x="53.34" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="45.72" y1="30.48" x2="55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +<wire x1="-7.62" y1="15.24" x2="-12.7" y2="15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="15.24"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-12.7" y1="15.24" x2="-12.7" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-12.7" x2="10.16" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="VBUS"/> +<wire x1="33.02" y1="-22.86" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<junction x="7.62" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="D-"/> +<wire x1="35.56" y1="-22.86" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-12.7" x2="35.56" y2="-7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="-12.7"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-7.62" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="D+"/> +<wire x1="38.1" y1="-22.86" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-5.08" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<junction x="38.1" y="-7.62"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" y1="2.54" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB3(ADC3)"/> +<wire x1="35.56" y1="7.62" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="63.5" y1="7.62" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="7.62"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<pinref part="U1" gate="G$1" pin="PB4(ADC2)"/> +<wire x1="38.1" y1="5.08" x2="25.4" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="20.32" y1="-12.7" x2="22.86" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MISO" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MISO"/> +<wire x1="38.1" y1="35.56" x2="27.94" y2="35.56" width="0.1524" layer="91"/> +<label x="27.94" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB1(MISO)"/> +<label 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editing/FabFTDI.s#8 b/old version editing/FabFTDI.s#8 new file mode 100755 index 0000000000000000000000000000000000000000..a011ffb7173843363de4bd0b33defb06041066d7 --- /dev/null +++ b/old version editing/FabFTDI.s#8 @@ -0,0 +1,875 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.3"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> +<layer number="6" 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function="dot" rot="R180"/> +<pin name="SCK" x="-2.54" y="0" visible="off" length="short" direction="pas" function="dot"/> +<pin name="MOSI" x="5.08" y="0" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="RST" x="-2.54" y="-2.54" visible="off" length="short" direction="pas" function="dot"/> +<pin name="GND" x="5.08" y="-2.54" visible="off" length="short" direction="pas" function="dot" rot="R180"/> +</symbol> +<symbol name="ARDUINO_SERIAL_PROGRAM"> +<wire x1="1.27" y1="-7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="0" x2="0" y2="0" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-2.54" x2="0" y2="-2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="-5.08" x2="0" y2="-5.08" width="0.6096" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="1.27" y1="-7.62" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="10.16" x2="1.27" y2="10.16" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="5.08" x2="0" y2="5.08" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="2.54" x2="0" y2="2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="7.62" x2="0" y2="7.62" width="0.6096" layer="94"/> +<text x="-5.08" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="10.922" size="1.778" layer="95">>NAME</text> +<pin name="DTR" x="5.08" y="-5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="RXI" x="5.08" y="-2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="TXO" x="5.08" y="0" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="VCC" x="5.08" y="2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="CTS" x="5.08" y="5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="GND" x="5.08" y="7.62" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB_MINIB"> +<gates> +<gate name="G$1" symbol="USB" x="0" y="0"/> +</gates> +<devices> +<device name="" package="USB_MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="U$1" library="fabPatil" deviceset="USB_MINIB" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="U$1" gate="G$1" x="35.56" y="-25.4" rot="R270"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-7.62" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-2.54" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="0" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-12.7" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-12.7" rot="R180"/> +<instance part="U$2" gate="G$1" x="40.64" y="33.02"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +<instance part="C1" gate="1" x="-12.7" y="10.16" rot="R90"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-7.62" y1="2.54" x2="-12.7" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="2.54" x2="-12.7" y2="5.08" width="0.1524" layer="91"/> +<junction x="-7.62" y="2.54"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-22.86" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-7.62" x2="53.34" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-7.62" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<junction x="53.34" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="45.72" y1="30.48" x2="55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +<wire x1="-7.62" y1="15.24" x2="-12.7" y2="15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="15.24"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-12.7" y1="15.24" x2="-12.7" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-12.7" x2="10.16" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="VBUS"/> +<wire x1="33.02" y1="-22.86" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<junction x="7.62" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="D-"/> +<wire x1="35.56" y1="-22.86" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-12.7" x2="35.56" y2="-7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="-12.7"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-7.62" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="D+"/> +<wire x1="38.1" y1="-22.86" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-5.08" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<junction x="38.1" y="-7.62"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" y1="2.54" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB3(ADC3)"/> +<wire x1="35.56" y1="7.62" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="63.5" y1="7.62" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="7.62"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<pinref part="U1" gate="G$1" pin="PB4(ADC2)"/> +<wire x1="38.1" y1="5.08" x2="25.4" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="20.32" y1="-12.7" x2="22.86" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MISO" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MISO"/> +<wire x1="38.1" y1="35.56" x2="27.94" y2="35.56" width="0.1524" layer="91"/> +<label x="27.94" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB1(MISO)"/> +<label x="27.94" y="12.7" size="1.778" layer="95"/> +<pinref part="JP1" gate="G$1" pin="TXO"/> +<wire x1="63.5" y1="12.7" x2="25.4" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SCK" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="SCK"/> +<wire x1="38.1" y1="33.02" x2="27.94" y2="33.02" width="0.1524" layer="91"/> +<label x="27.94" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB2(SCK/ADC1)"/> +<label x="27.94" y="10.16" size="1.778" layer="95"/> +<wire x1="25.4" y1="10.16" x2="38.1" y2="10.16" width="0.1524" layer="91"/> +<wire x1="38.1" y1="10.16" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="38.1" y1="15.24" x2="63.5" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="RST" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RST"/> +<wire x1="38.1" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/> +<label x="27.94" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB5(NRES)"/> +<wire x1="25.4" y1="2.54" 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rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATTINY45" prefix="U" uservalue="yes"> +<description>Atmel 8-pin 2/4/8kB flash uC</description> +<gates> +<gate name="G$1" symbol="ATTINY13" x="0" y="0"/> +</gates> +<devices> +<device name="TINY45-20-SMT" package="SO08-EIAJ"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-08922"/> +<attribute name="VALUE" value="Tiny45-20-SMT" constant="no"/> +</technology> +</technologies> +</device> +<device name="TINY45-20-DIP" package="DIP08"> +<connects> +<connect gate="G$1" pin="GND" pad="4"/> +<connect gate="G$1" pin="PB0(MOSI)" pad="5"/> +<connect gate="G$1" pin="PB1(MISO)" pad="6"/> +<connect gate="G$1" pin="PB2(SCK/ADC1)" pad="7"/> +<connect gate="G$1" pin="PB3(ADC3)" pad="2"/> +<connect gate="G$1" pin="PB4(ADC2)" pad="3"/> +<connect gate="G$1" pin="PB5(NRES)" pad="1"/> +<connect gate="G$1" pin="VCC" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="IC-09439"/> +<attribute name="VALUE" value="TINY45-20-DIP" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB_MINIB"> +<gates> +<gate name="G$1" symbol="USB" x="0" y="0"/> +</gates> +<devices> +<device name="" package="USB_MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="DO41Z10" package="DO41Z10"> +<connects> +<connect gate="1" pin="ANODE" pad="A"/> +<connect gate="1" pin="CATHODE" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRISP"> +<gates> +<gate name="G$1" symbol="AVRISP" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="MISO" pad="1"/> +<connect gate="G$1" pin="MOSI" pad="4"/> +<connect gate="G$1" pin="RST" pad="5"/> +<connect gate="G$1" pin="SCK" pad="3"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="fabPatil" deviceset="ATTINY45" device="TINY45-20-SMT" value="Tiny45-20-SMT"/> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="U$1" library="fabPatil" deviceset="USB_MINIB" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206"/> +<part name="U$2" library="fabPatil" deviceset="AVRISP" device="SMD"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="12.7" y="7.62"/> +<instance part="P+1" gate="VCC" x="-7.62" y="25.4"/> +<instance part="GND1" gate="1" x="-7.62" y="-7.62"/> +<instance part="U$1" gate="G$1" x="35.56" y="-25.4" rot="R270"/> +<instance part="GND2" gate="1" x="22.86" y="-22.86"/> +<instance part="D1" gate="1" x="45.72" y="-7.62" rot="R180"/> +<instance part="D2" gate="1" x="45.72" y="-12.7" rot="R180"/> +<instance part="GND3" gate="1" x="53.34" y="-22.86"/> +<instance part="R1" gate="G$1" x="35.56" y="-2.54" rot="R90"/> +<instance part="R2" gate="G$1" x="38.1" y="0" rot="R90"/> +<instance part="P+2" gate="VCC" x="7.62" y="-5.08"/> +<instance part="R3" gate="G$1" x="27.94" y="-12.7" rot="R180"/> +<instance part="R4" gate="G$1" x="15.24" y="-12.7" rot="R180"/> +<instance part="U$2" gate="G$1" x="40.64" y="33.02"/> +<instance part="JP1" gate="G$1" x="68.58" y="12.7" rot="R180"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="-2.54" y1="2.54" x2="-7.62" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="2.54" x2="-7.62" y2="-5.08" width="0.1524" layer="91"/> +<label x="-7.62" y="2.54" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="GND"/> +<wire x1="30.48" y1="-22.86" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="30.48" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="48.26" y1="-7.62" x2="53.34" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="53.34" y1="-7.62" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<junction x="53.34" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<wire x1="45.72" y1="30.48" x2="55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="63.5" y1="5.08" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-7.62" y1="22.86" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="VCC"/> +<wire x1="-7.62" y1="15.24" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<label x="-7.62" y="15.24" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="7.62" y1="-12.7" x2="10.16" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="VBUS"/> +<wire x1="33.02" y1="-22.86" x2="33.02" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-12.7" width="0.1524" layer="91"/> +<junction x="7.62" y="-12.7"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<wire x1="45.72" y1="35.56" x2="55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="D-"/> +<wire x1="35.56" y1="-22.86" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-12.7" x2="35.56" y2="-7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="-12.7"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="33.02" y1="-12.7" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="43.18" y1="-7.62" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="D+"/> +<wire x1="38.1" y1="-22.86" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="38.1" y1="-5.08" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<junction x="38.1" y="-7.62"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="35.56" y1="2.54" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="PB3(ADC3)"/> +<wire x1="35.56" y1="7.62" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="CTS"/> +<wire x1="63.5" y1="7.62" x2="35.56" y2="7.62" width="0.1524" layer="91"/> +<junction x="35.56" y="7.62"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<pinref part="U1" gate="G$1" pin="PB4(ADC2)"/> +<wire x1="38.1" y1="5.08" x2="25.4" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="20.32" y1="-12.7" x2="22.86" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MISO" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MISO"/> +<wire x1="38.1" y1="35.56" x2="27.94" y2="35.56" width="0.1524" layer="91"/> +<label x="27.94" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB1(MISO)"/> +<label x="27.94" y="12.7" size="1.778" layer="95"/> +<pinref part="JP1" gate="G$1" pin="TXO"/> +<wire x1="63.5" y1="12.7" x2="25.4" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SCK" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="SCK"/> +<wire x1="38.1" y1="33.02" x2="27.94" y2="33.02" width="0.1524" layer="91"/> +<label x="27.94" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB2(SCK/ADC1)"/> +<label x="27.94" y="10.16" size="1.778" layer="95"/> +<wire x1="25.4" y1="10.16" x2="38.1" y2="10.16" width="0.1524" layer="91"/> +<wire x1="38.1" y1="10.16" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="38.1" y1="15.24" x2="63.5" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="RST" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RST"/> +<wire x1="38.1" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/> +<label x="27.94" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB5(NRES)"/> +<wire x1="25.4" y1="2.54" x2="33.02" y2="2.54" width="0.1524" layer="91"/> +<label x="27.94" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="MOSI" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="MOSI"/> +<wire x1="45.72" y1="33.02" x2="55.88" y2="33.02" width="0.1524" layer="91"/> +<label x="50.8" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PB0(MOSI)"/> +<wire x1="25.4" y1="15.24" x2="35.56" y2="15.24" width="0.1524" layer="91"/> +<label x="27.94" y="15.24" size="1.778" layer="95"/> +<wire x1="35.56" y1="15.24" x2="35.56" y2="17.78" width="0.1524" layer="91"/> +<pinref part="JP1" gate="G$1" pin="DTR"/> +<wire x1="35.56" y1="17.78" x2="63.5" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> diff --git a/old version editing/FabFTDI.sch b/old version editing/FabFTDI.sch new file mode 100755 index 0000000000000000000000000000000000000000..faeb77463fd95381dc0d4439b48f6045f74c9667 --- /dev/null +++ b/old version editing/FabFTDI.sch @@ -0,0 +1,1091 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="8.3.2"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting keepoldvectorfont="yes"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> 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y2="10.16" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="5.08" x2="0" y2="5.08" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="2.54" x2="0" y2="2.54" width="0.6096" layer="94"/> +<wire x1="-1.27" y1="7.62" x2="0" y2="7.62" width="0.6096" layer="94"/> +<text x="-5.08" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-5.08" y="10.922" size="1.778" layer="95">>NAME</text> +<pin name="DTR" x="5.08" y="-5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="RXI" x="5.08" y="-2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="TXO" x="5.08" y="0" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="VCC" x="5.08" y="2.54" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="CTS" x="5.08" y="5.08" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +<pin name="GND" x="5.08" y="7.62" visible="pin" length="middle" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="CAP-NP"> +<wire x1="-1.778" y1="1.524" x2="-1.778" y2="0" width="0.254" layer="94"/> +<wire x1="-1.778" y1="0" x2="-1.778" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.762" y1="1.524" x2="-0.762" y2="0" width="0.254" layer="94"/> +<wire x1="-0.762" y1="0" x2="-0.762" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.778" y2="0" width="0.1524" layer="94"/> +<wire x1="-0.762" y1="0" x2="0" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="2.54" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.81" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +<symbol name="USB-1"> +<wire x1="5.08" y1="8.89" x2="0" y2="8.89" width="0.254" layer="94"/> +<wire x1="0" y1="8.89" x2="0" y2="-1.27" width="0.254" layer="94"/> +<wire x1="0" y1="-1.27" x2="5.08" y2="-1.27" width="0.254" layer="94"/> +<text x="3.81" y="0" size="2.54" layer="94" rot="R90">USB</text> +<pin name="D+" x="-2.54" y="7.62" visible="pad" length="short"/> +<pin name="D-" x="-2.54" y="5.08" visible="pad" length="short"/> +<pin name="VBUS" x="-2.54" y="2.54" visible="pad" length="short"/> +<pin name="GND" x="-2.54" y="0" visible="pad" length="short"/> +</symbol> +<symbol name="ATTINY102/104"> +<description><h3> ATTINY102/104 </h3> +<p> Symbol for Atmel Attiny102/104</p></description> +<wire x1="0" y1="0" x2="0" y2="12.7" width="0.254" layer="94"/> +<wire x1="0" y1="12.7" x2="30.48" y2="12.7" width="0.254" layer="94"/> +<wire x1="30.48" y1="12.7" x2="30.48" y2="0" width="0.254" layer="94"/> +<wire x1="30.48" y1="0" x2="0" y2="0" width="0.254" layer="94"/> +<pin name="VCC" x="-5.08" y="10.16" length="middle"/> +<pin name="PA0(TPICLK)" x="-5.08" y="7.62" length="middle"/> +<pin name="PA1(TPIDATA)" x="-5.08" y="5.08" length="middle"/> +<pin name="PA2(RESET)" x="-5.08" y="2.54" length="middle"/> +<pin name="GND" x="35.56" y="10.16" length="middle" rot="R180"/> +<pin name="PB3(RXD)" x="35.56" y="7.62" length="middle" rot="R180"/> +<pin name="PB2(TXD)" x="35.56" y="5.08" length="middle" rot="R180"/> +<pin name="PB1" x="35.56" y="2.54" length="middle" rot="R180"/> +<text x="0" y="12.7" size="1.27" layer="95">AT102</text> +<text x="0" y="-2.54" size="1.27" layer="96">>VALUE</text> +</symbol> +<symbol name="DGND"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +<symbol name="AVRTPI"> +<description><h3>Symbol for ATMEL TPI Connector </h3> +<p> +Symbol used in AVR TPI device. + +- Prashant Patil </p></description> +<wire x1="0" y1="0" x2="20.32" y2="0" width="0.4064" layer="94"/> +<wire x1="20.32" y1="0" x2="20.32" y2="10.16" width="0.4064" layer="94"/> +<wire x1="20.32" y1="10.16" x2="0" y2="10.16" width="0.4064" layer="94"/> +<wire x1="0" y1="10.16" x2="0" y2="0" width="0.4064" layer="94"/> +<text x="1.27" y="10.795" size="1.778" layer="95">>NAME</text> +<text x="1.27" y="-2.54" size="1.778" layer="96">AVRTPI</text> +<pin name="TPIDATA" x="-5.08" y="7.62" visible="pin" length="middle"/> +<pin name="TPICLK" x="-5.08" y="5.08" visible="pin" length="middle"/> +<pin name="RESET" x="-5.08" y="2.54" visible="pin" length="middle"/> +<pin name="VCC" x="25.4" y="7.62" visible="pin" length="middle" rot="R180"/> +<pin name="(NC)" x="25.4" y="5.08" visible="pin" length="middle" rot="R180"/> +<pin name="GND" x="25.4" y="2.54" visible="pin" length="middle" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="ZENER_DIODE" prefix="D" uservalue="yes"> +<description>zener diode</description> +<gates> +<gate name="1" symbol="ZENER" x="0" y="0"/> +</gates> +<devices> +<device name="SOD123" package="SOD123"> +<connects> +<connect gate="1" pin="ANODE" pad="ANODE"/> +<connect gate="1" pin="CATHODE" pad="CATHODE"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FTDI_CONNECTOR" prefix="JP" uservalue="yes"> +<description>FTDI connector smd</description> +<gates> +<gate name="G$1" symbol="ARDUINO_SERIAL_PROGRAM" x="0" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="1X06-SMD"> +<connects> +<connect gate="G$1" pin="CTS" pad="5"/> +<connect gate="G$1" pin="DTR" pad="1"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RXI" pad="2"/> +<connect gate="G$1" pin="TXO" pad="3"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="UNPOLARIZED_CAPACITOR" prefix="C" uservalue="yes"> +<description>unpolarized_capacitor</description> +<gates> +<gate name="1" symbol="CAP-NP" x="1.27" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="1" pin="1" pad="1"/> +<connect gate="1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="JP"> +<description><h3> USB Connector </h3> + +Connector for USB-microB (orAB), USB-mini, and USB-PCB. For USB-micro use Digikey Part# 609-4052-1-ND (typeB) or 609-4052-1-ND (typeAB).</description> +<gates> +<gate name="G$1" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-B-S" package="USB-B-SMT"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VUSB"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OLD" package="USB-MINIB-OLD"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-JST-2MM-SMT" package="S4B-PH"> +<connects> +<connect gate="G$1" pin="D+" pad="2"/> +<connect gate="G$1" pin="D-" pad="3"/> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="VBUS" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD" package="USB-MINIB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08193" constant="no"/> +</technology> +</technologies> +</device> +<device name="PCB" package="USB_PCB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="5V"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-SMD-NS" package="USB-MINIB-NOSTOP"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MICROB" package="USB-MICROB"> +<connects> +<connect gate="G$1" pin="D+" pad="D+"/> +<connect gate="G$1" pin="D-" pad="D-"/> +<connect gate="G$1" pin="GND" pad="GND MT1 MT2"/> +<connect gate="G$1" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09505"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ATTINY102/104"> +<description><h3>ATTINY102/104</h3> +<p>Device for ATTINY102/104 </p></description> +<gates> +<gate name="G$1" symbol="ATTINY102/104" x="-15.24" y="-5.08"/> +</gates> +<devices> +<device name="" package="SOIC8"> +<connects> +<connect gate="G$1" pin="GND" pad="8"/> +<connect gate="G$1" pin="PA0(TPICLK)" pad="2"/> +<connect gate="G$1" pin="PA1(TPIDATA)" pad="3"/> +<connect gate="G$1" pin="PA2(RESET)" pad="4"/> +<connect gate="G$1" pin="PB1" pad="5"/> +<connect gate="G$1" pin="PB2(TXD)" pad="6"/> +<connect gate="G$1" pin="PB3(RXD)" pad="7"/> +<connect gate="G$1" pin="VCC" pad="1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="DGND" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVRTPI"> +<description><h3> ATMEL-ICE TPI Connector SMD</h3> +<p> + +This is a TPI programming connector to program Atiny102/104 micro-controllers +prashant.patil@cba.mit.edu + +</p></description> +<gates> +<gate name="G$1" symbol="AVRTPI" x="-2.54" y="0"/> +</gates> +<devices> +<device name="SMD" package="2X03SMD"> +<connects> +<connect gate="G$1" pin="(NC)" pad="4"/> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="RESET" pad="5"/> +<connect gate="G$1" pin="TPICLK" pad="3"/> +<connect gate="G$1" pin="TPIDATA" pad="1"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="FAB_Hello"> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +<symbol name="GND-1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND-1" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="P+1" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND1" library="FAB_Hello" deviceset="GND" device=""/> +<part name="GND2" library="FAB_Hello" deviceset="GND" device=""/> +<part name="D1" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123" value="3.3V"/> +<part name="D2" library="fabPatil" deviceset="ZENER_DIODE" device="SOD123" value="3.3V"/> +<part name="GND3" library="FAB_Hello" deviceset="GND" device=""/> +<part name="R1" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="R2" library="fabPatil" deviceset="RESISTOR" device="1206" value="49"/> +<part name="P+2" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="R3" library="fabPatil" deviceset="RESISTOR" device="1206" value="499"/> +<part name="R4" library="fabPatil" deviceset="RESISTOR" device="1206" value="1K"/> +<part name="JP1" library="fabPatil" deviceset="FTDI_CONNECTOR" device="SMD"/> +<part name="C1" library="fabPatil" deviceset="UNPOLARIZED_CAPACITOR" device="1206" value="0.1uF"/> +<part name="JP2" library="fabPatil" deviceset="USB" device="PCB"/> +<part name="R5" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +<part name="R6" library="fabPatil" deviceset="RESISTOR" device="1206" value="470"/> +<part name="U$1" library="fabPatil" deviceset="ATTINY102/104" device=""/> +<part name="P+3" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="P+4" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND4" library="fabPatil" deviceset="GND" device=""/> +<part name="GND5" library="fabPatil" deviceset="GND" device=""/> +<part name="U$2" library="fabPatil" deviceset="AVRTPI" device="SMD"/> +<part name="P+5" library="FAB_Hello" deviceset="VCC" device=""/> +<part name="GND6" library="fabPatil" deviceset="GND" device=""/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="P+1" gate="VCC" x="-38.1" y="-10.16" rot="R90"/> +<instance part="GND1" gate="1" x="-17.78" y="-10.16" rot="R90"/> +<instance part="GND2" gate="1" x="35.56" y="-5.08" rot="R90"/> +<instance part="D1" gate="1" x="25.4" y="17.78" rot="R270"/> +<instance part="D2" gate="1" x="30.48" y="17.78" rot="R270"/> +<instance part="GND3" gate="1" x="35.56" y="25.4" rot="R90"/> +<instance part="R1" gate="G$1" x="20.32" y="7.62" rot="R180"/> +<instance part="R2" gate="G$1" x="17.78" y="10.16" rot="R180"/> +<instance part="P+2" gate="VCC" x="17.78" y="-20.32" rot="R90"/> +<instance part="R3" gate="G$1" x="27.94" y="0" rot="R270"/> +<instance part="R4" gate="G$1" x="27.94" y="-12.7" rot="R270"/> +<instance part="JP1" gate="G$1" x="-83.82" y="10.16"/> +<instance part="C1" gate="1" x="-30.48" y="-10.16" rot="R180"/> +<instance part="JP2" gate="G$1" x="40.64" y="2.54"/> +<instance part="R5" gate="G$1" x="-55.88" y="10.16" rot="R180"/> +<instance part="R6" gate="G$1" x="-63.5" y="7.62" rot="R180"/> +<instance part="U$1" gate="G$1" x="-30.48" y="2.54"/> +<instance part="P+3" gate="VCC" x="-96.52" y="7.62" rot="R180"/> +<instance part="P+4" gate="VCC" x="-38.1" y="20.32"/> +<instance part="GND4" gate="1" x="10.16" y="17.78"/> +<instance part="GND5" gate="1" x="-96.52" y="25.4" rot="R180"/> +<instance part="U$2" gate="G$1" x="-30.48" y="22.86"/> +<instance part="P+5" gate="VCC" x="-2.54" y="38.1"/> +<instance part="GND6" gate="1" x="-2.54" y="20.32"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="GND1" gate="1" pin="GND"/> +<label x="-22.86" y="-7.62" size="1.778" layer="95" rot="R90"/> +<pinref part="C1" gate="1" pin="1"/> +<wire x1="-20.32" y1="-10.16" x2="-25.4" y2="-10.16" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="33.02" y1="2.54" x2="33.02" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="GND2" gate="1" pin="GND"/> +<pinref part="JP2" gate="G$1" pin="GND"/> +<wire x1="38.1" y1="2.54" x2="33.02" y2="2.54" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D1" gate="1" pin="ANODE"/> +<wire x1="25.4" y1="20.32" x2="25.4" y2="25.4" width="0.1524" layer="91"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="25.4" y1="25.4" x2="30.48" y2="25.4" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="ANODE"/> +<wire x1="30.48" y1="25.4" x2="33.02" y2="25.4" width="0.1524" layer="91"/> +<wire x1="30.48" y1="20.32" x2="30.48" y2="25.4" width="0.1524" layer="91"/> +<junction x="30.48" y="25.4"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="-78.74" y1="17.78" x2="-76.2" y2="17.78" width="0.1524" layer="91"/> +<pinref part="GND5" gate="1" pin="GND"/> +<wire x1="-78.74" y1="17.78" x2="-96.52" y2="17.78" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="17.78" x2="-96.52" y2="22.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="GND"/> +<wire x1="5.08" y1="12.7" x2="5.08" y2="20.32" width="0.1524" layer="91"/> +<pinref part="GND4" gate="1" pin="GND"/> +<wire x1="5.08" y1="20.32" x2="10.16" y2="20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="GND"/> +<pinref part="GND6" gate="1" pin="GND"/> +<wire x1="-5.08" y1="25.4" x2="-2.54" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="25.4" x2="-2.54" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="20.32" y1="-20.32" x2="27.94" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +<wire x1="27.94" y1="-20.32" x2="27.94" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="38.1" y1="5.08" x2="30.48" y2="5.08" width="0.1524" layer="91"/> +<wire x1="30.48" y1="5.08" x2="30.48" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="30.48" y1="-20.32" x2="27.94" y2="-20.32" width="0.1524" layer="91"/> +<junction x="27.94" y="-20.32"/> +<pinref part="JP2" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="VCC"/> +<pinref part="P+3" gate="VCC" pin="VCC"/> +<wire x1="-78.74" y1="12.7" x2="-96.52" y2="12.7" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="12.7" x2="-96.52" y2="10.16" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$1" gate="G$1" pin="VCC"/> +<pinref part="P+4" gate="VCC" pin="VCC"/> +<wire x1="-35.56" y1="12.7" x2="-38.1" y2="12.7" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="12.7" x2="-38.1" y2="17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U$2" gate="G$1" pin="VCC"/> +<pinref part="P+5" gate="VCC" pin="VCC"/> +<wire x1="-5.08" y1="30.48" x2="-2.54" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="30.48" x2="-2.54" y2="35.56" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<pinref part="C1" gate="1" pin="2"/> +<wire x1="-33.02" y1="-10.16" x2="-35.56" y2="-10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<wire x1="38.1" y1="7.62" x2="30.48" y2="7.62" width="0.1524" layer="91"/> +<pinref part="D2" gate="1" pin="CATHODE"/> +<wire x1="30.48" y1="15.24" x2="30.48" y2="7.62" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="30.48" y1="7.62" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +<junction x="30.48" y="7.62"/> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="27.94" y1="5.08" x2="30.48" y2="7.62" width="0.1524" layer="91"/> +<pinref part="JP2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="D1" gate="1" pin="CATHODE"/> +<wire x1="25.4" y1="15.24" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<wire x1="38.1" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="22.86" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<junction x="25.4" y="10.16"/> +<pinref part="JP2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="PA0(TPICLK)"/> +<wire x1="-35.56" y1="10.16" x2="-43.18" y2="10.16" width="0.1524" layer="91"/> +<pinref part="U$2" gate="G$1" pin="TPICLK"/> +<wire x1="-35.56" y1="27.94" x2="-43.18" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="27.94" x2="-43.18" y2="10.16" width="0.1524" layer="91"/> +<pinref part="R5" gate="G$1" pin="1"/> +<wire x1="-43.18" y1="10.16" x2="-50.8" y2="10.16" width="0.1524" layer="91"/> +<junction x="-43.18" y="10.16"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="27.94" y1="-7.62" x2="27.94" y2="-5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="PA1(TPIDATA)"/> +<wire x1="-35.56" y1="7.62" x2="-45.72" y2="7.62" width="0.1524" layer="91"/> +<pinref part="U$2" gate="G$1" pin="TPIDATA"/> +<wire x1="-35.56" y1="30.48" x2="-45.72" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="30.48" x2="-45.72" y2="7.62" width="0.1524" layer="91"/> +<pinref part="R6" gate="G$1" pin="1"/> +<wire x1="-45.72" y1="7.62" x2="-58.42" y2="7.62" width="0.1524" layer="91"/> +<junction x="-45.72" y="7.62"/> +</segment> +</net> +<net name="N$7" class="0"> +<segment> +<pinref part="R6" gate="G$1" pin="2"/> +<pinref part="JP1" gate="G$1" pin="RXI"/> +<wire x1="-68.58" y1="7.62" x2="-78.74" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$8" class="0"> +<segment> +<pinref part="R5" gate="G$1" pin="2"/> +<pinref part="JP1" gate="G$1" pin="TXO"/> +<wire x1="-60.96" y1="10.16" x2="-78.74" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$9" class="0"> +<segment> +<pinref part="U$2" gate="G$1" pin="RESET"/> +<wire x1="-35.56" y1="25.4" x2="-40.64" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="25.4" x2="-40.64" y2="5.08" width="0.1524" layer="91"/> +<pinref part="U$1" gate="G$1" pin="PA2(RESET)"/> +<wire x1="-40.64" y1="5.08" x2="-35.56" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$10" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="PB3(RXD)"/> +<pinref part="R2" gate="G$1" pin="2"/> +<wire x1="5.08" y1="10.16" x2="12.7" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$11" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="PB2(TXD)"/> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="5.08" y1="7.62" x2="15.24" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +<compatibility> +<note version="8.3" severity="warning"> +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. +</note> +</compatibility> +</eagle> diff --git a/old version editing/FabFTDIBG.png b/old version editing/FabFTDIBG.png new file mode 100755 index 0000000000000000000000000000000000000000..c5aa93d876b4e0a5d504bdd6538eaea7d8783185 Binary files /dev/null and b/old version editing/FabFTDIBG.png differ diff --git a/old version editing/FabFTDIBoard.png b/old version editing/FabFTDIBoard.png new file mode 100755 index 0000000000000000000000000000000000000000..a5280baad1a4eaf648dc1a320a8dc3e14351573c Binary files /dev/null and b/old version editing/FabFTDIBoard.png differ diff --git a/old version editing/FabFTDITrace.png b/old version editing/FabFTDITrace.png new file mode 100755 index 0000000000000000000000000000000000000000..f056408ed77ea614250556c8e51ca325b934967e Binary files /dev/null and b/old version editing/FabFTDITrace.png differ diff --git a/old version editing/IMG_0260.jpg b/old version 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version editing/Schematic.PNG b/old version editing/Schematic.PNG new file mode 100755 index 0000000000000000000000000000000000000000..fd1fafad4b5c6879515473dfc98a2e2276c73a60 Binary files /dev/null and b/old version editing/Schematic.PNG differ diff --git a/old version editing/eagle.epf b/old version editing/eagle.epf new file mode 100755 index 0000000000000000000000000000000000000000..df906a1b4573d12da48dc3a19fe5b1edd7c79e7b --- /dev/null +++ b/old version editing/eagle.epf @@ -0,0 +1,42 @@ +[Eagle] +Version="08 03 02" +Platform="Windows" +Globals="Globals" +Desktop="Desktop" + +[Globals] +AutoSaveProject=1 +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/FAB_Hello.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/fab.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/fabPatil.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/ng.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/usb_con-update.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/Adafruit/adafruit.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/LilyPad-Wearables.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Aesthetics.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-AnalogIC.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Boards.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Capacitors.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Connectors.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-DigitalIC.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-DiscreteSemi.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Displays.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Electromechanical.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-FreqCtrl.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-LED.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Passives.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-PowerIC.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-RF.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Resistors.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Retired.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Sensors.lbr" + +[Win_1] +Type="Control Panel" +Loc="0 0 1919 1017" +State=1 +Number=0 + +[Desktop] +Screen="1920 1080" +Window="Win_1" diff --git a/old version/eagle.epf b/old version/eagle.epf index f0200c3a4489371504dd731917ab0da5fad45f70..641e4104cf2331ad93afa54ddc69afa8f0bf0793 100755 --- a/old version/eagle.epf +++ b/old version/eagle.epf @@ -6,12 +6,12 @@ Desktop="Desktop" [Globals] AutoSaveProject=1 -UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/Adafruit/adafruit.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/FAB_Hello.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/fab.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/fabPatil.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/ng.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/fablab/usb_con-update.lbr" +UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/Adafruit/adafruit.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/LilyPad-Wearables.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Aesthetics.lbr" UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-AnalogIC.lbr" @@ -32,11 +32,58 @@ UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Librar UsedLibrary="C:/Users/Prashant Patil/Dropbox (MIT)/Documents/eagle/Custom Libraries/SparkFun Library/SparkFun-Sensors.lbr" [Win_1] +Type="Board Editor" +Loc="-8 -8 1911 1009" +State=1 +Number=2 +File="FabFTDI.brd" +View="-5.80992 0.766063 52.9459 26.9709" +WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524" +PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6" +ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0" +ViaDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" +HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" +TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778" +PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27" +PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0" +DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13" +DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0" +DimensionExtLengths=" 1.27 2.54 1 2 3 0" +DimensionExtOffsets=" 1.27 2.54 1 2 3 0" +SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635" +WireBend=1 +WireBendSet=0 +WireCap=1 +MiterStyle=0 +PadShape=0 +ViaShape=1 +PolygonPour=0 +PolygonRank=1 +PolygonThermals=1 +PolygonOrphans=0 +TextRatio=8 +DimensionUnit=1 +DimensionPrecision=2 +DimensionShowUnit=0 +PinDirection=3 +PinFunction=0 +PinLength=2 +PinVisible=3 +SwapLevel=0 +ArcDirection=0 +AddLevel=2 +PadsSameType=0 +Layer=1 + +[Win_2] Type="Control Panel" -Loc="652 321 1251 720" +Loc="0 0 1919 1017" State=1 Number=0 [Desktop] Screen="1920 1080" Window="Win_1" +Window="Win_2"