Commit 8809cfc1 authored by Jake Read's avatar Jake Read

hello circuit doc

parent 2c3eb649
**.l#*
**archive/
**.b#*
**.s#*
......@@ -6,83 +6,68 @@ Notes for beginners and reference for experts on the nuts and bolts of circuit d
## Schematics and Boards
two representations!
No matter what software you're using, it's important to understand the two representations we use to describe circuits.
## Symbols and Footprints
parts: straddling the divide
### Parts: Reference Designators
## Libraries
The ```schematic``` is a nonphysical space where we can describe which outputs or inputs from our various components are connected to one another. In a schematic, we find part ```symbols``` that pave ```pins```, these are connected to one another on ```nets```.
Here is perhaps the best place to keep tabs on circuits: happening, desires, etc...
![labelled_schem](eagle/examples/xmega-demo/schematic.png)
https://github.com/sparkfun/SparkFun-Eagle-Libraries
Critically, we can connect nets to one another by simply assigning them the same name. This is a useful trick that you will probably encounter many times in the wild. Also important to note are ```supply``` components, like the **gnd** and **v+** or **+3v3** etc symbols, which are simply symbolic representations of similarely named nets.
## The Design Process
It's not-not useful to recall that schematics are also nice visual diagrams of what we want our circuits to do. There's no harm in making them look medium-nice. :bowtie:
Nonlinear!
The ```board``` representation is where our design meets the physical world. Here we find ```footprints``` that have ```pads``` that are connected to one another via ```traces, vias, and pours``` i.e. copper.
### Schematic
![labelled_board](eagle/examples/xmega-demo/routed.png)
### Roughing
In Eagle, `boards` and `schematics` should be automatically associated with one another. This is referred to as 'forward/back annotation' - but typically goes one way: from the schematic to the board. It's best, while we're starting, to treat this relationship as a directional one. I.E. when you're deleting a component, do so in the schematic, otherwise you will introduce inconsistencies and Eagle might abandon you.
### Routing
### Planes
- no power planes, double layer gnd planes
- at high frequency, gnd plane not a gnd plane, consider lowest energy field generated for return current
- rs-422 and use power ground to clamp down (rs485 is rs422 for busses, not point to point links)
## Manufacturing
KiCAD uses a different system, where we save a `netlist` from our schematic, and open that in a board editor. This is partially an opinion about the division between the two practices, and partially a historic artefact of KiCAD's development as a collection of not-unrelated softwares.
Trace / Space
Drill Size
Distance from Cutout
## Symbols and Footprints
Eagle - design rules.
Our circuit assemblies are made of `schematics` that are diagrams of our `boards`, and so the components we use to put them together have a similar split; we call them `symbols` and `footprints`.
- 6mil Traces / 6mil Spacing on 1oz copper (0.15mm is the actual unit they use)
- 8mil Traces / 8mil Spacing on 2oz copper (0.2mm for spacing)
A `symbol` is a diagram of a part, and the `footprint` is the 'landing' that we need in order for the part to be successfully included in our circuit. The matching copper for us to hook the IC to.
- 0.3mm min hole size -> 11.1811 mil
![mosfet](images/parts-mosfet-sot23.png)
![mosfet](images/parts-mosfet-to252.png)
- 24mil text is absolute lower bound, not very pretty !
Symbols can have multiple footprints: the same or similar silicon divices can be packaged in varying sizes for circuit integration.
drc: tented vias, or not ? 'limit'
![micro](images/parts-xmega-tqfp.png)
![micro](images/parts-xmega-qfn.png)
save .drl file for 'lowcostfab' for 'fancyfab4lr' and 'fancyfab'
To make your own symbols or footprints, I can recommend [Autodesk's Tutorial, starting here](https://www.autodesk.com/products/eagle/blog/library-basics-part-1-creating-first-package-autodesk-eagle/) and for KiCAD, the [symbol](https://www.youtube.com/watch?v=LaUd8WfFooU), [footprint](https://www.youtube.com/watch?v=LaUd8WfFooU), and [the association](https://www.youtube.com/watch?v=IIPKGoW0VBY).
| Include | Tables | one per mfg | for known design rules |
## Libraries
| Include | order-of-mag tables | for current carrying | in traces |
To organize collections of parts, we use `libraries` of devices: paired symbols and footprints. For eagle, I've included our CBA libraries in the [**eagle/parts** directory](eagle/parts) of this repo. I've also included the [sparkfun libraries](https://github.com/sparkfun/SparkFun-Eagle-Libraries) as I commonly use their connectors library for pin-headers. Parts in the `fablab` library *should* all be available in fab labs, but it's best to check with actual inventory before designing a circuit. It's also likely that parts in the inventory are not yet in the library: if you find this to be the case, and you make a footprint for a part you would like to use (or find one online) please push a merge request, or raise an issue in this repo!
| Include | PDF | for | gndplanes |
The [fablab inventory](https://docs.google.com/spreadsheets/u/1/d/1U-jcBWOJEjBT5A0N84IUubtcHKMEMtndQPLCkZCkVsU/pub?single=true&gid=0&output=html) includes all of the circuit components that *should* be available in the lab.
### Fab Manufacture
## Manufacturing
Particular DRL rules ! milling limits, rivet vias, etc.
Different methods of circuit manufacture have different constraints. We commonly call these `design rules` - they define a variety of things, the most important being the `trace/space` dimension: how thin can we make a trace, and how much gap must we leave between each different signal? The next important question is about how small our minimum drill size is: this sets the diameter of our vias.
This will help you make sure that traces are not too close together!
For 'most' fabricators, a lenient (easy to fab) trace/space is `8/8mil` (mil: 1/1000 of an inch: 8mil: 0.2032mm), with a 0.35mm minimum sized hole (that's 13.8mil). For some reason, we commonly refer to 'mil' for traces and mm for holes. The world is full of idiosyncrasies. Fabricators who can't do this are really, really not worth the time.
In this folder, find ``` fabcity-designrules.dru ```
For the circuit milling we do in the lab, we set our space by the width of our end-mills: the 1/64th endmills are 15.625mil in diameter, so for some error band I use a 16mil space, and to avoid accidentally milling traces away, I typically set a 12mil trace. 12/16 means it is occasionally difficult to mill footprints for newer component packages like a QFN. Drilling holes under 1/32" is also a pain, so I'll normally set my minimum drill to 32mil.
In Eagle, in the Board Window, find ``` edit >> design rules ```
In any case, if you'd rather not think about any of this, I've included some Eagle design rules files in this repo in the [**eagle/design-rules** folder](eagle/design-rules). You can load these into eagle in the board-design window through `edit >> design rules`, or the `drc` command. Once you've done this, you can run the 'drc' command to check if your design violates any of the rules.
On the first tab, use 'load' and load this .dru file.
TODO: want to keep a list of manufacturer design-rules files or board templates (grid etc) for two- and four- layer fab at factory.
Now you can use the 'DRC' command to check!
#### Automating the generation of trace.png and cutout.png files
#### Automate the generation of trace.png and cutout.png files
Matt Keeter wrote a Python script that opens up Eagle and exports a number of pngs using ImageMagick.
Matt Keeter wrote a Python script that opens up Eagle and exports a number of pngs using ImageMagick. Last I know, this is tested for Eagle 7- or 8.
To get this script to run, use the following steps:
* Save eagle_png.py into the folder where you keep your Eagle project folders containing .brd and .sch files
* Save [eagle/scripts/eagle_png.py](eagle/scripts/eagle_png.py) into the folder where you keep your Eagle project folders containing .brd and .sch files
* Install [ImageMagick](https://www.imagemagick.org/script/index.php)
* Create a polygon over your .brd design on the Milling layer (number 46)
* Set the isolate value for the polygon to a number greater than 16, this will ensure there's enough black space for mods to generate toolpaths in (see image below)
![eagle/scripts/isolate.png](eagle/scripts/isolate.png)
* Save your .brd file and close Eagle
* Run eagle_png using the following command `python eagle_png.py board_folder/board_name.brd`
* The script should have saved several .png files into the folder where the .brd file is
......@@ -91,10 +76,15 @@ To get this script to run, use the following steps:
### SMT Manufacture
[go adafruit](https://learn.adafruit.com/smt-manufacturing/overview)
TODO: doc here for more advanced manufacture; particularly the simple step to stencil and reflowing boards!
[Adafruit already has some great notes on SMT manufacturing.](https://learn.adafruit.com/smt-manufacturing/overview)
#### L1: boardfab, solder by hand
#### Export
Making Gerbers
#### L2: paste, stencils, and tweezers
#### L3: diy pnp
......@@ -106,13 +96,9 @@ For assembly, some miters tips are
- tempo automation
- maybe worth trying jlc/easyeda - just have to constrain boards to parts they have (probably)
#### Export
eagle fabrication routines here,
# Parts
# Component Notes
The fab inventory keeps a list of components [here](spreadsheet),
Half the struggle of EE (in practice) is finding the right components to assemble your circuits with. Below are my own very rough notes on parts-that-I-have-once-used-or-thought-about, that I will be maintaining here to help in the search.
## LEDs
......
......@@ -9,12 +9,12 @@ mdWireVia = 16mil
mdPadPad = 16mil
mdPadVia = 16mil
mdViaVia = 16mil
mdSmdPad = 6mil
mdSmdVia = 6mil
mdSmdSmd = 6mil
mdSmdPad = 0mil
mdSmdVia = 0mil
mdSmdSmd = 0mil
mdViaViaSameLayer = 6mil
mnLayersViaInSmd = 2
mdCopperDimension = 16mil
mdCopperDimension = 20mil
mdDrill = 16mil
mdSmdStop = 0mil
msWidth = 10mil
......
<b>User Projects</b>
<p>
This folder contains user Projects files.
\ No newline at end of file
[Eagle]
Version="09 05 00"
Platform="Windows"
Globals="Globals"
Desktop="Desktop"
[Globals]
AutoSaveProject=1
UsedLibrary="G:/Dropbox/CBA/doc/circuits/eagle/parts/fablab.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/circuits/eagle/parts/sensor.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/circuits/eagle/parts/supply1.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/comm.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/connector.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/dfet.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/lights.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/microcontrollers.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/motors.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/passives.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/power.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/sensor.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/tag-connect-2030.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/tag-connect-2050.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/libraries/eagle/usbraw.lbr"
UsedLibrary="G:/Dropbox/CBA/doc/circuits/eagle/parts/SparkFun-Eagle-Libraries/SparkFun-Connectors.lbr"
[Win_1]
Type="Library Editor"
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File="G:/Dropbox/CBA/doc/circuits/eagle/parts/fablab.lbr"
View="-4.87147 -4.54581 4.75717 5.34532"
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PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0"
ViaDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35"
HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35"
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DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
DimensionExtLengths=" 1.27 2.54 1 2 3 0"
DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
SmdSizes=" 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635 0.4 0.3 0.4 0.4"
WireBend=4
WireBendSet=0
WireCap=1
MiterStyle=1
PadShape=0
ViaShape=1
PolygonPour=0
PolygonRank=0
PolygonThermals=1
PolygonOrphans=0
TextRatio=8
DimensionUnit=1
DimensionPrecision=2
DimensionShowUnit=0
PinDirection=3
PinFunction=0
PinLength=2
PinVisible=3
SwapLevel=0
ArcDirection=0
AddLevel=2
PadsSameType=0
Layer=21
Package="SOIC8_PAD"
[Win_2]
Type="Board Editor"
Number=2
File="xmega-demo.brd"
View="-3.61015 11.4415 59.1391 40.466"
WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524 0.3048"
PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0"
ViaDrills=" 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35 0.8128"
HoleDrills=" 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35 3.1"
TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
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MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
DimensionExtLengths=" 1.27 2.54 1 2 3 0"
DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
WireBend=3
WireBendSet=0
WireCap=1
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PadShape=0
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PolygonThermals=1
PolygonOrphans=0
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DimensionUnit=1
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PinDirection=3
PinFunction=0
PinLength=2
PinVisible=3
SwapLevel=0
ArcDirection=0
AddLevel=2
PadsSameType=0
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[Win_3]
Type="Schematic Editor"
Number=1
File="xmega-demo.sch"
View="-66.371 -19.8182 253.157 185.593"
WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524"
PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0"
ViaDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35"
HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35"
TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
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PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
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DimensionExtLengths=" 1.27 2.54 1 2 3 0"
DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
WireBend=0
WireBendSet=31
WireCap=1
MiterStyle=1
PadShape=0
ViaShape=1
PolygonPour=0
PolygonRank=0
PolygonThermals=1
PolygonOrphans=0
TextRatio=8
DimensionUnit=1
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DimensionShowUnit=0
PinDirection=3
PinFunction=0
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PinVisible=3
SwapLevel=0
ArcDirection=0
AddLevel=2
PadsSameType=0
Layer=91
Views=" 1: -66.371 -19.8182 253.157 185.593"
Sheet="1"
[Win_4]
Type="Control Panel"
Number=0
[Desktop]
Screen="3840 1080"
Window="Win_1"
Window="Win_2"
Window="Win_3"
Window="Win_4"
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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.1.1">
<eagle version="9.5.0">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
......@@ -36,9 +36,9 @@
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
<layer number="29" name="tStop" color="7" fill="3" visible="yes" active="yes"/>
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
<layer number="31" name="tCream" color="7" fill="4" visible="yes" active="yes"/>
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
......@@ -488,6 +488,21 @@ Source: www.austriamicrosystems.com .. AS5040DataSheetRev12.pdf</description>
<text x="0" y="1.778" size="0.6096" layer="25" font="vector" ratio="20" align="bottom-center">&gt;NAME</text>
<text x="0" y="-1.778" size="0.6096" layer="27" font="vector" ratio="20" align="top-center">&gt;VALUE</text>
</package>
<package name="BME680">
<smd name="P$1" x="1.2" y="1.2" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$2" x="1.2" y="0.4" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$3" x="1.2" y="-0.4" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$4" x="1.2" y="-1.2" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$5" x="-1.2" y="-1.2" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$6" x="-1.2" y="-0.4" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$7" x="-1.2" y="0.4" dx="0.4" dy="0.4" layer="1"/>
<smd name="P$8" x="-1.2" y="1.2" dx="0.4" dy="0.4" layer="1"/>
<wire x1="-1.6" y1="1.6" x2="1.6" y2="1.6" width="0.1016" layer="51"/>
<wire x1="1.6" y1="1.6" x2="1.6" y2="-1.6" width="0.1016" layer="51"/>
<wire x1="1.6" y1="-1.6" x2="-1.6" y2="-1.6" width="0.1016" layer="51"/>
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<circle x="1.7" y="1.7" radius="0.1" width="0.1016" layer="21"/>
</package>
</packages>
<symbols>
<symbol name="AS5304-6">
......@@ -663,6 +678,20 @@ Source: www.austriamicrosystems.com .. AS5040DataSheetRev12.pdf</description>
<text x="-5.08" y="10.16" size="1.778" layer="95">&gt;NAME</text>
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<symbol name="SENS_BME680">
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<pin name="VDDIO" x="-17.78" y="0" length="middle"/>
<pin name="VDDA" x="-17.78" y="7.62" length="middle"/>
<pin name="SDI_SDA_MOSI" x="27.94" y="7.62" length="middle" rot="R180"/>
<pin name="SDO_GND_MISO" x="27.94" y="2.54" length="middle" rot="R180"/>
<pin name="CSB_VDD_CS" x="27.94" y="-7.62" length="middle" rot="R180"/>
<pin name="SCK_SCL_SCK" x="27.94" y="-2.54" length="middle" rot="R180"/>
<wire x1="-12.7" y1="10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>
<wire x1="-12.7" y1="-10.16" x2="22.86" y2="-10.16" width="0.254" layer="94"/>
<wire x1="22.86" y1="-10.16" x2="22.86" y2="10.16" width="0.254" layer="94"/>
<wire x1="22.86" y1="10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
<text x="-10.16" y="-12.7" size="1.27" layer="95">&gt;NAME</text>
</symbol>
</symbols>
<devicesets>
<deviceset name="AS5304-6">
......@@ -910,6 +939,27 @@ Source: www.austriamicrosystems.com .. AS5040DataSheetRev12.pdf</description>
</device>
</devices>
</deviceset>
<deviceset name="SENS_TEMP-HUMIDITY_BME680" prefix="U">
<gates>
<gate name="G$1" symbol="SENS_BME680" x="-15.24" y="-7.62"/>
</gates>
<devices>
<device name="" package="BME680">
<connects>
<connect gate="G$1" pin="CSB_VDD_CS" pad="P$2"/>
<connect gate="G$1" pin="GND" pad="P$1 P$7"/>
<connect gate="G$1" pin="SCK_SCL_SCK" pad="P$4"/>
<connect gate="G$1" pin="SDI_SDA_MOSI" pad="P$3"/>
<connect gate="G$1" pin="SDO_GND_MISO" pad="P$5"/>
<connect gate="G$1" pin="VDDA" pad="P$8"/>
<connect gate="G$1" pin="VDDIO" pad="P$6"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
......
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#!/usr/bin/env python
import os
import sys
import platform
import glob
import subprocess
import hashlib
def find_eagle():
if platform.uname()[0] == 'Darwin':
try:
eagle_dir = glob.glob('/Applications/EAGLE*')[-1]
except IndexError:
sys.stderr.write("Error: EAGLE not found.\n")
sys.exit(1)
return eagle_dir + '/EAGLE.app/Contents/MacOS/EAGLE'
else:
if subprocess.call(['which','eagle'],
stdout = open(os.devnull, 'w')):
sys.stderr.write("Error: EAGLE not found.\n")
sys.exit(1)
return 'eagle'
def create_images(name, resolution = 1500):
for img in ['top','bottom','cutout','holes','vias']:
file = '%s.%s.png' % (name, img)
if os.path.isfile(file):
os.remove(file)
script = '''
ratsnest; write;
set palette black; window;
display none top vias pads;
export image '{name}.top.png' monochrome {resolution};
display none bottom vias pads;
export image '{name}.bottom.png' monochrome {resolution};
display none milling;
export image '{name}.cutout.png' monochrome {resolution};
display none holes;
export image '{name}.holes.png' monochrome {resolution};
display none vias pads;
export image '{name}.vias.png' monochrome {resolution};
quit'''.format(name = name, resolution = resolution)
subprocess.call([find_eagle(), '-C', script, name + '.brd'])
def md5(filename):
with open(filename,'rb') as f:
m = hashlib.md5()
for chunk in iter(lambda: f.read(m.block_size*128), ''):
m.update(chunk)
return m.digest()
def clean_up(name):
preserve = ['top','bottom','cutout']
for img in ['top','bottom','cutout','holes','vias']:
file = '%s.%s.png' % (name, img)
file_ = '%s.%s_.png' % (name, img)
if os.path.isfile(file) and img not in preserve:
os.remove(file)
if os.path.isfile(file_):
os.remove(file_)
def print_help():
print """command line: eagle_png [options] target.brd
target.brd = EAGLE brd file to render
The board outline should be a solid polygon on the 'milling' layer
Internal cutouts should be solid shapes on the 'holes' layer
Valid options:
--resolution NUM : sets output image resolution
--doublesided : forces double-sided mode"""
sys.exit(1)
if __name__ == '__main__':
if len(sys.argv) == 1:
print_help()
sys.exit(1)
# Parse arguments
sys.argv = sys.argv[1:]
resolution = 1500
force_doublesided = False
while sys.argv:
if sys.argv[0] == '--resolution':
try:
resolution = sys.argv[1]
sys.argv = sys.argv[2:]
except IndexError:
sys.stderr.write("Error: No resolution provided.\n")
sys.exit(1)
try:
resolution = int(resolution)
except ValueError:
sys.stderr.write("Error: Invalid resolution.\n")
sys.exit(1)
elif sys.argv[0] == '--doublesided':
force_doublesided = True
sys.argv = sys.argv[1:]
elif len(sys.argv) == 1:
break
else:
sys.stderr.write("Error: No filename provided.\n")
sys.exit(1)
name = sys.argv[0].replace('.brd','')
if not os.path.isfile(name+'.brd'):
sys.stderr.write("Error: .brd file does not exist.\n")
sys.exit(1)
vias = name + '.vias.png'
cutout = name + '.cutout.png'
top = name + '.top.png'
bottom = name + '.bottom.png'
holes = name + '.holes.png'
print "Rendering images."
create_images(name, resolution)
# Check to make sure that imagemagick is installed.
if subprocess.call(['which','convert'], stdout = open(os.devnull, 'w')):
sys.stderr.write("""Error: 'convert' not found.
ImageMagick command-line tools must be installed to use eagle_png.""")
sys.exit(1)
print "Processing images."
# The following command is a set of ImageMagick instructions that
# combine all of the images.
# The following steps take place:
# - Perform a white flood fill on the vias image, starting in the upper
# left corner. This makes the via image a set of black holes on
# a uniform white background
# - Multiply the vias and cutout images, to cut the via holes from
# the cutout region.
# - Invert the cutout image.
# - Lighten the top and bottom traces with the inverted cutout. This
# ensures that we don't waste time milling traces in regions that
# will be cut out of the PCB.
# - Subtract the holes image from the original cutout image
# - Save this combined cutout image
command = [ 'convert',
vias, '-fill', 'white', '-draw', 'color 0,0 floodfill',
cutout, '-compose', 'Darken', '-composite',
'-compose','Lighten',
'(',
'+clone',
'-negate'
]
# If this is a two-sided board, then process the bottom layer
if md5(bottom) != md5(vias) or force_doublesided:
command += [
'(',
'+clone', bottom, '-composite',
'-flop', '-write', bottom, '+delete',
')'
]
else:
os.remove(bottom)
# Process the top layer
command += [
top, '-composite', '-write', top,
'+delete',
')',
holes, '-compose', 'Minus_Src', '-composite', cutout
]
# Execute this whole mess
subprocess.call(command)
os.remove(vias)
os.remove(holes)
if bottom in command:
print "Generated %s, %s, %s." % (top, bottom, cutout)
else:
print "Generated %s, %s." % (top, cutout)
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