Commit 3e683b61 authored by Sam Calisch's avatar Sam Calisch
Browse files

update bc832 with rts programming reset

parent 09bb616f
Pipeline #575 canceled with stage
bc832-ftdi/bc832-nrf-ftdi-interior.png

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bc832-ftdi/bc832-nrf-ftdi-interior.png
bc832-ftdi/bc832-nrf-ftdi-interior.png
bc832-ftdi/bc832-nrf-ftdi-interior.png
bc832-ftdi/bc832-nrf-ftdi-interior.png
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bc832-ftdi/bc832-nrf-ftdi-layout.png

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bc832-ftdi/bc832-nrf-ftdi-layout.png

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bc832-ftdi/bc832-nrf-ftdi-layout.png
bc832-ftdi/bc832-nrf-ftdi-layout.png
bc832-ftdi/bc832-nrf-ftdi-layout.png
bc832-ftdi/bc832-nrf-ftdi-layout.png
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bc832-ftdi/bc832-nrf-ftdi-traces.png

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bc832-ftdi/bc832-nrf-ftdi-traces.png
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......@@ -83,7 +83,7 @@ class Crystal_FC135(Component):
class Header_FTDI(Component):
''' FTDI cable header
'''
_pad_header = chamfered_rectangle(-0.06, 0.08,-0.035, 0.035,.007)
_pad_header = chamfered_rectangle(-0.06, 0.08,-0.025, 0.025,.007)
pins = [
Pin(0, -0.25, _pad_header, 'RTS'),
Pin(0, -0.15, _pad_header, 'RX'),
......@@ -212,8 +212,8 @@ class Hole(Component):
width = .9
height = .71
pcb = PCB(0,0,width,height,chamfer_distance=.04)
height = .69
pcb = PCB(0,0,width,height,chamfer_distance=.02)
def connectG(pin,dx,dy,width=.012):
......@@ -232,15 +232,15 @@ def connectM(pin1,pin2,dx,width=.012):
ftdi = Header_FTDI(.2,.32,180,'ftdi')
pcb += ftdi
reg = Regulator_SOT23(ftdi.x+.13,ftdi['GND'].y+.04,-90,'3.3v')
reg = Regulator_SOT23(ftdi.x+.13,ftdi['GND'].y+.03,-90,'3.3v')
pcb += reg
pcb.connectV(ftdi['GND'],reg['GND'],width=.02)
pcb.connectD(reg['IN'],[reg['IN'].x,ftdi['VCC'].y-.03],ftdi['VCC'],width=.02)
C_in = C_0805(reg.x-.01,reg.y+.16,180,'Cin\n.1uF',label_size=.02)
C_in = C_0805(reg.x-.01,reg.y+.165,180,'Cin\n.1uF',label_size=.02)
pcb += C_in
C_out = C_0805(reg.x+.09,reg.y-.0,90,'Cout\n.1uF',label_size=.02)
C_out = C_0805(reg.x+.09,reg.y-.01,90,'Cout\n.1uF',label_size=.02)
pcb += C_out
pcb.connectD(C_in[1],[C_in[1].x,C_in[1].y-.02],reg['GND'])
pcb.connectV(reg['IN'],C_in[0],width=.02)
......@@ -252,16 +252,26 @@ mdb = BC832(ftdi.x+.5,ftdi.y+.1,-90,'Fanstel\nBC832\nNRF52')
pcb += mdb
pcb.connectD(mdb['P8'],[mdb['P8'].x-.01,mdb['P8'].y],[ftdi['TX'].x+.31,ftdi['TX'].y+.03],[ftdi['TX'].x+.03,ftdi['TX'].y-.031],ftdi['TX'],width=.014)
pcb.connectD(mdb['P6'],[mdb['P6'].x,mdb['P6'].y+.02],[mdb['P6'].x-.07,mdb['P6'].y+.035],[ftdi['RX'].x+.28,ftdi['RX'].y-.05],[ftdi['RX'].x+.1,ftdi['RX'].y-.1],[ftdi['RX'].x+.09,ftdi['RX'].y-.03],ftdi['RX'],width=.012)
connectG(mdb['GND'],0,.09,width=.016)
pcb.connectD(mdb['P8'],[mdb['P8'].x-.01,mdb['P8'].y],[ftdi['TX'].x+.31,ftdi['TX'].y+.03],[ftdi['TX'].x+.03,ftdi['TX'].y-.019],ftdi['TX'],width=.014)
pcb.connectD(mdb['P6'],[mdb['P6'].x,mdb['P6'].y+.02],[mdb['P6'].x-.07,mdb['P6'].y+.035],[ftdi['RX'].x+.28,ftdi['RX'].y-.043],[ftdi['RX'].x+.1,ftdi['RX'].y-.088],[ftdi['RX'].x+.09,ftdi['RX'].y-.03],ftdi['RX'],width=.012)
connectG(mdb['GND'],0,.07,width=.016)
swd = TagConnectSWD(ftdi.x+.17,mdb.y+.1,-90,'swd')
pcb += swd
pcb.connectD(swd['SWDCLK'],[swd['SWDCLK'].x+.02,swd['SWDCLK'].y],[mdb['SWDCLK'].x-.24,mdb['SWDCLK'].y+.01],[mdb['SWDCLK'].x-.02,mdb['SWDCLK'].y+.055],mdb['SWDCLK'],width=.014)
pcb.connectD(swd['SWDIO'],[swd['SWDIO'].x+.02,swd['SWDIO'].y],[mdb['SWDIO'].x-.32,mdb['SWDIO'].y+.04],[mdb['SWDIO'].x-.03,mdb['SWDIO'].y+.087],mdb['SWDIO'],width=.014)
pcb.connectD(ftdi['RTS'],[ftdi['RTS'].x,ftdi['RTS'].y+.03],[mdb['DFU'].x-.05,mdb['DFU'].y+.12],mdb['DFU'],width=.014)
#pcb.connectD(ftdi['RTS'],[ftdi['RTS'].x,ftdi['RTS'].y+.03],[mdb['DFU'].x-.05,mdb['DFU'].y+.12],mdb['DFU'],width=.014)
Rrts1 = R_0805(ftdi.x-.13,ftdi['RTS'].y+.07,0,'2k')
pcb += Rrts1
Rrts2 = R_0805(Rrts1.x+.13,Rrts1.y,0,'1k')
pcb += Rrts2
pcb.connectV(mdb['RESET'],[ftdi.x-.11,ftdi['TX'].y-.05],Rrts1[0],width=.014)
pcb.connectV(Rrts1[0],Rrts2[1])
pcb.connectV(Rrts2[0],ftdi['RTS'])
pcb.connectV(Rrts1[1],ftdi['GND'])
C2 = C_0805(C_out.x,C_out.y+.13,-90,'C2\n10uF',label_size=.02)
......@@ -302,5 +312,5 @@ connectG(swd[1],-.04,.05)
cad.shapes = pcb.layout()
#cad.shape = pcb.traces+(pcb.cutout-pcb.cutout)
#cad.shape = pcb.cutout+(pcb.traces-pcb.traces)
cad.shape = pcb.traces+(pcb.cutout-pcb.cutout)
cad.shape = pcb.cutout+(pcb.traces-pcb.traces)
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