diff --git a/eagle/README.md b/eagle/README.md
index 42a7fc01f48bcfbae6ecba5f0d8562c41d1594a1..1e2c24f8aa9f8c57054ed1f673908c5db6a12092 100644
--- a/eagle/README.md
+++ b/eagle/README.md
@@ -1,3 +1,15 @@
+## Use Fab Design Rules in Eagle
+
+This will help you make sure that traces are not too close together!
+
+In this folder, find ``` fabcity-designrules.dru ```
+
+In Eagle, in the Board Window, find ``` edit >> design rules ``` 
+
+On the first tab, use 'load' and load this .dru file.
+
+Now you can use the 'DRC' command to check!
+
 ## Automate the generation of trace.png and cutout.png files
 Matt Keeter wrote a Python script that opens up Eagle and exports a number of pngs using ImageMagick.
 
diff --git a/eagle/fabcity-designrules.dru b/eagle/fabcity-designrules.dru
new file mode 100644
index 0000000000000000000000000000000000000000..927b5c59f835fbe767b090e4b7d4eea286ba5404
--- /dev/null
+++ b/eagle/fabcity-designrules.dru
@@ -0,0 +1,73 @@
+description[de] = <b>EAGLE Design Rules</b>\n<p>\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
+description[en] = <b>EAGLE Design Rules</b>\n<p>\nThe default Design Rules have been set to cover\na wide range of applications. Your particular design\nmay have different requirements, so please make the\nnecessary adjustments and save your customized\ndesign rules under a new name.
+layerSetup = (1*16)
+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
+mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
+mdWireWire = 16mil
+mdWirePad = 16mil
+mdWireVia = 16mil
+mdPadPad = 16mil
+mdPadVia = 16mil
+mdViaVia = 16mil
+mdSmdPad = 6mil
+mdSmdVia = 6mil
+mdSmdSmd = 6mil
+mdViaViaSameLayer = 6mil
+mnLayersViaInSmd = 2
+mdCopperDimension = 16mil
+mdDrill = 16mil
+mdSmdStop = 0mil
+msWidth = 10mil
+msDrill = 32mil
+msMicroVia = 9.99mm
+msBlindViaRatio = 0.500000
+rvPadTop = 0.250000
+rvPadInner = 0.250000
+rvPadBottom = 0.250000
+rvViaOuter = 0.250000
+rvViaInner = 0.250000
+rvMicroViaOuter = 0.250000
+rvMicroViaInner = 0.250000
+rlMinPadTop = 10mil
+rlMaxPadTop = 20mil
+rlMinPadInner = 10mil
+rlMaxPadInner = 20mil
+rlMinPadBottom = 10mil
+rlMaxPadBottom = 20mil
+rlMinViaOuter = 8mil
+rlMaxViaOuter = 20mil
+rlMinViaInner = 8mil
+rlMaxViaInner = 20mil
+rlMinMicroViaOuter = 4mil
+rlMaxMicroViaOuter = 20mil
+rlMinMicroViaInner = 4mil
+rlMaxMicroViaInner = 20mil
+psTop = -1
+psBottom = -1
+psFirst = -1
+psElongationLong = 100
+psElongationOffset = 100
+mvStopFrame = 1.000000
+mvCreamFrame = 0.000000
+mlMinStopFrame = 4mil
+mlMaxStopFrame = 4mil
+mlMinCreamFrame = 0mil
+mlMaxCreamFrame = 0mil
+mlViaStopLimit = 0mil
+srRoundness = 0.000000
+srMinRoundness = 0mil
+srMaxRoundness = 0mil
+slThermalIsolate = 16mil
+slThermalsForVias = 0
+dpMaxLengthDifference = 10mm
+dpGapFactor = 2.500000
+checkAngle = 0
+checkFont = 1
+checkRestrict = 1
+checkStop = 0
+checkValues = 0
+checkNames = 1
+checkWireStubs = 1
+checkPolygonWidth = 0
+useDiameter = 13
+maxErrors = 50