Commit 29bf37e5 authored by Neil Gershenfeld's avatar Neil Gershenfeld
Browse files

wip

parent 51ca019d
Pipeline #12193 passed with stage
in 1 second
......@@ -22,10 +22,10 @@
#output = "top, labels, and exterior"
#output = "top, labels, holes, and exterior"
#output = "top, bottom, labels, and exterior"
#output = "top, bottom, labels, holes, and exterior"
output = "top traces"
output = "top, bottom, labels, holes, and exterior"
#output = "top traces"
#output = "top traces and exterior"
output = "bottom traces reversed"
#output = "bottom traces reversed"
#output = "bottom traces reversed and exterior"
#output = "holes"
#output = "interior"
......@@ -7958,12 +7958,6 @@ mask = .004 # solder mask size
pcb = PCB(x,y,width,height,mask)
pcb = wire(pcb,w,
point(x,y,zb),
point(x,y+height,zb))
'''
IC1 = ATtiny44_SOICN('IC1\nt44')
pcb = IC1.add(pcb,x+.49,y+.56)
......@@ -8115,8 +8109,6 @@ pcb = wire(pcb,w,
point(V7.x,V6.y,zb),
V7.pad[2])
'''
############################################################
# select output
############################################################
......
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