Commit 90d7befd authored by Neil Gershenfeld's avatar Neil Gershenfeld
Browse files

fix wire cylinder roundoff

parent 804ffb2b
Pipeline #12195 passed with stage
in 1 second
......@@ -1049,7 +1049,8 @@ def wire(pcb,width,*points):
x0 = points[0].x
y0 = points[0].y
z0 = points[0].z
pcb.board = add(pcb.board,cylinder(x0,y0,z0,z0,width/2))
roundoff = 1e-6
pcb.board = add(pcb.board,cylinder(x0,y0,z0-roundoff,z0+roundoff,width/2))
for i in range(1,len(points)):
x0 = points[i-1].x
y0 = points[i-1].y
......@@ -1058,7 +1059,7 @@ def wire(pcb,width,*points):
y1 = points[i].y
z1 = points[i].z
pcb.board = add(pcb.board,line(x0,y0,x1,y1,z1,width))
pcb.board = add(pcb.board,cylinder(x1,y1,z1,z1,width/2))
pcb.board = add(pcb.board,cylinder(x1,y1,z1-roundoff,z1+roundoff,width/2))
return pcb
def wirer(pcb,width,*points):
......
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