Commit 9b978ea2 authored by Neil Gershenfeld's avatar Neil Gershenfeld
Browse files

wip

parent 151d45bc
Pipeline #17793 passed with stage
in 1 second
......@@ -25,6 +25,7 @@ output = "top, labels, holes, and exterior"
#output = "top, bottom, labels, holes, and exterior"
#output = "top traces"
#output = "top traces and exterior"
#output = "bottom traces"
#output = "bottom traces reversed"
#output = "bottom traces reversed and exterior"
#output = "holes"
......@@ -8298,6 +8299,9 @@ elif (output == "top traces"):
elif (output == "top traces and exterior"):
outputs["function"] = color(White,add(pcb.board,pcb.exterior))
outputs["layers"] = [zt]
elif (output == "bottom traces"):
outputs["function"] = color(White,pcb.board)
outputs["layers"] = [zb]
elif (output == "bottom traces reversed"):
outputs["function"] = color(White,
reflect_x(pcb.board,2*x+width))
......
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