From e9d4ebf4b0bf06c1ec2936c9f42706107c7d0d1f Mon Sep 17 00:00:00 2001
From: Neil Gershenfeld <gersh@cba.mit.edu>
Date: Sat, 16 Jan 2021 08:58:54 -0500
Subject: [PATCH] wip
---
GPIO/ATSAME54/astudio/demo.atsln | 17 +
GPIO/ATSAME54/astudio/demo.cproj | 590 ++++
GPIO/ATSAME54/e54-tests.pdf | Bin 0 -> 429068 bytes
GPIO/ATSAME54/hal_gpio.h | 126 +
GPIO/ATSAME54/include/component/ac.h | 598 ++++
GPIO/ATSAME54/include/component/adc.h | 871 +++++
GPIO/ATSAME54/include/component/aes.h | 375 ++
GPIO/ATSAME54/include/component/can.h | 3193 ++++++++++++++++++
GPIO/ATSAME54/include/component/ccl.h | 228 ++
GPIO/ATSAME54/include/component/cmcc.h | 357 ++
GPIO/ATSAME54/include/component/dac.h | 544 +++
GPIO/ATSAME54/include/component/dmac.h | 1416 ++++++++
GPIO/ATSAME54/include/component/dsu.h | 1244 +++++++
GPIO/ATSAME54/include/component/eic.h | 497 +++
GPIO/ATSAME54/include/component/evsys.h | 587 ++++
GPIO/ATSAME54/include/component/freqm.h | 233 ++
GPIO/ATSAME54/include/component/gclk.h | 272 ++
GPIO/ATSAME54/include/component/gmac.h | 2593 ++++++++++++++
GPIO/ATSAME54/include/component/hmatrixb.h | 84 +
GPIO/ATSAME54/include/component/i2s.h | 747 ++++
GPIO/ATSAME54/include/component/icm.h | 582 ++++
GPIO/ATSAME54/include/component/mclk.h | 484 +++
GPIO/ATSAME54/include/component/nvmctrl.h | 861 +++++
GPIO/ATSAME54/include/component/osc32kctrl.h | 303 ++
GPIO/ATSAME54/include/component/oscctrl.h | 793 +++++
GPIO/ATSAME54/include/component/pac.h | 690 ++++
GPIO/ATSAME54/include/component/pcc.h | 251 ++
GPIO/ATSAME54/include/component/pdec.h | 726 ++++
GPIO/ATSAME54/include/component/picop.h | 1321 ++++++++
GPIO/ATSAME54/include/component/pm.h | 261 ++
GPIO/ATSAME54/include/component/port.h | 414 +++
GPIO/ATSAME54/include/component/qspi.h | 528 +++
GPIO/ATSAME54/include/component/ramecc.h | 178 +
GPIO/ATSAME54/include/component/rstc.h | 115 +
GPIO/ATSAME54/include/component/rtc.h | 2098 ++++++++++++
GPIO/ATSAME54/include/component/sdhc.h | 2599 ++++++++++++++
GPIO/ATSAME54/include/component/sercom.h | 1680 +++++++++
GPIO/ATSAME54/include/component/supc.h | 554 +++
GPIO/ATSAME54/include/component/tal.h | 1842 ++++++++++
GPIO/ATSAME54/include/component/tc.h | 851 +++++
GPIO/ATSAME54/include/component/tcc.h | 1762 ++++++++++
GPIO/ATSAME54/include/component/trng.h | 172 +
GPIO/ATSAME54/include/component/usb.h | 1777 ++++++++++
GPIO/ATSAME54/include/component/wdt.h | 300 ++
GPIO/ATSAME54/include/core_cm4.h | 1802 ++++++++++
GPIO/ATSAME54/include/core_cmFunc.h | 637 ++++
GPIO/ATSAME54/include/core_cmInstr.h | 880 +++++
GPIO/ATSAME54/include/core_cmSimd.h | 697 ++++
GPIO/ATSAME54/include/instance/ac.h | 79 +
GPIO/ATSAME54/include/instance/adc0.h | 99 +
GPIO/ATSAME54/include/instance/adc1.h | 100 +
GPIO/ATSAME54/include/instance/aes.h | 105 +
GPIO/ATSAME54/include/instance/can0.h | 139 +
GPIO/ATSAME54/include/instance/can1.h | 139 +
GPIO/ATSAME54/include/instance/ccl.h | 57 +
GPIO/ATSAME54/include/instance/cmcc.h | 61 +
GPIO/ATSAME54/include/instance/dac.h | 88 +
GPIO/ATSAME54/include/instance/dmac.h | 596 ++++
GPIO/ATSAME54/include/instance/dsu.h | 121 +
GPIO/ATSAME54/include/instance/eic.h | 73 +
GPIO/ATSAME54/include/instance/evsys.h | 723 ++++
GPIO/ATSAME54/include/instance/freqm.h | 59 +
GPIO/ATSAME54/include/instance/gclk.h | 191 ++
GPIO/ATSAME54/include/instance/gmac.h | 263 ++
GPIO/ATSAME54/include/instance/hmatrix.h | 133 +
GPIO/ATSAME54/include/instance/i2s.h | 81 +
GPIO/ATSAME54/include/instance/icm.h | 77 +
GPIO/ATSAME54/include/instance/mclk.h | 61 +
GPIO/ATSAME54/include/instance/nvmctrl.h | 75 +
GPIO/ATSAME54/include/instance/osc32kctrl.h | 59 +
GPIO/ATSAME54/include/instance/oscctrl.h | 130 +
GPIO/ATSAME54/include/instance/pac.h | 69 +
GPIO/ATSAME54/include/instance/pcc.h | 58 +
GPIO/ATSAME54/include/instance/pdec.h | 80 +
GPIO/ATSAME54/include/instance/picop.h | 147 +
GPIO/ATSAME54/include/instance/pm.h | 59 +
GPIO/ATSAME54/include/instance/port.h | 184 +
GPIO/ATSAME54/include/instance/pukcc.h | 57 +
GPIO/ATSAME54/include/instance/qspi.h | 72 +
GPIO/ATSAME54/include/instance/ramecc.h | 54 +
GPIO/ATSAME54/include/instance/rstc.h | 48 +
GPIO/ATSAME54/include/instance/rtc.h | 156 +
GPIO/ATSAME54/include/instance/sdhc0.h | 147 +
GPIO/ATSAME54/include/instance/sdhc1.h | 147 +
GPIO/ATSAME54/include/instance/sercom0.h | 181 +
GPIO/ATSAME54/include/instance/sercom1.h | 181 +
GPIO/ATSAME54/include/instance/sercom2.h | 181 +
GPIO/ATSAME54/include/instance/sercom3.h | 181 +
GPIO/ATSAME54/include/instance/sercom4.h | 181 +
GPIO/ATSAME54/include/instance/sercom5.h | 181 +
GPIO/ATSAME54/include/instance/sercom6.h | 181 +
GPIO/ATSAME54/include/instance/sercom7.h | 181 +
GPIO/ATSAME54/include/instance/supc.h | 64 +
GPIO/ATSAME54/include/instance/tal.h | 541 +++
GPIO/ATSAME54/include/instance/tc0.h | 109 +
GPIO/ATSAME54/include/instance/tc1.h | 109 +
GPIO/ATSAME54/include/instance/tc2.h | 109 +
GPIO/ATSAME54/include/instance/tc3.h | 109 +
GPIO/ATSAME54/include/instance/tc4.h | 109 +
GPIO/ATSAME54/include/instance/tc5.h | 109 +
GPIO/ATSAME54/include/instance/tc6.h | 109 +
GPIO/ATSAME54/include/instance/tc7.h | 109 +
GPIO/ATSAME54/include/instance/tcc0.h | 125 +
GPIO/ATSAME54/include/instance/tcc1.h | 115 +
GPIO/ATSAME54/include/instance/tcc2.h | 106 +
GPIO/ATSAME54/include/instance/tcc3.h | 99 +
GPIO/ATSAME54/include/instance/tcc4.h | 99 +
GPIO/ATSAME54/include/instance/trng.h | 51 +
GPIO/ATSAME54/include/instance/usb.h | 343 ++
GPIO/ATSAME54/include/instance/wdt.h | 55 +
GPIO/ATSAME54/include/pio/same54n19a.h | 2693 +++++++++++++++
GPIO/ATSAME54/include/pio/same54n20a.h | 2693 +++++++++++++++
GPIO/ATSAME54/include/pio/same54p19a.h | 3015 +++++++++++++++++
GPIO/ATSAME54/include/pio/same54p20a.h | 3015 +++++++++++++++++
GPIO/ATSAME54/include/same54.h | 50 +
GPIO/ATSAME54/include/same54n19a.h | 1149 +++++++
GPIO/ATSAME54/include/same54n20a.h | 1149 +++++++
GPIO/ATSAME54/include/same54p19a.h | 1149 +++++++
GPIO/ATSAME54/include/same54p20a.h | 1149 +++++++
GPIO/ATSAME54/linker/same54p20a.ld | 103 +
GPIO/ATSAME54/main.c | 124 +
GPIO/ATSAME54/make/Makefile | 78 +
GPIO/ATSAME54/startup_same54.c | 398 +++
index.html | 7 +
124 files changed, 65207 insertions(+)
create mode 100644 GPIO/ATSAME54/astudio/demo.atsln
create mode 100644 GPIO/ATSAME54/astudio/demo.cproj
create mode 100644 GPIO/ATSAME54/e54-tests.pdf
create mode 100644 GPIO/ATSAME54/hal_gpio.h
create mode 100644 GPIO/ATSAME54/include/component/ac.h
create mode 100644 GPIO/ATSAME54/include/component/adc.h
create mode 100644 GPIO/ATSAME54/include/component/aes.h
create mode 100644 GPIO/ATSAME54/include/component/can.h
create mode 100644 GPIO/ATSAME54/include/component/ccl.h
create mode 100644 GPIO/ATSAME54/include/component/cmcc.h
create mode 100644 GPIO/ATSAME54/include/component/dac.h
create mode 100644 GPIO/ATSAME54/include/component/dmac.h
create mode 100644 GPIO/ATSAME54/include/component/dsu.h
create mode 100644 GPIO/ATSAME54/include/component/eic.h
create mode 100644 GPIO/ATSAME54/include/component/evsys.h
create mode 100644 GPIO/ATSAME54/include/component/freqm.h
create mode 100644 GPIO/ATSAME54/include/component/gclk.h
create mode 100644 GPIO/ATSAME54/include/component/gmac.h
create mode 100644 GPIO/ATSAME54/include/component/hmatrixb.h
create mode 100644 GPIO/ATSAME54/include/component/i2s.h
create mode 100644 GPIO/ATSAME54/include/component/icm.h
create mode 100644 GPIO/ATSAME54/include/component/mclk.h
create mode 100644 GPIO/ATSAME54/include/component/nvmctrl.h
create mode 100644 GPIO/ATSAME54/include/component/osc32kctrl.h
create mode 100644 GPIO/ATSAME54/include/component/oscctrl.h
create mode 100644 GPIO/ATSAME54/include/component/pac.h
create mode 100644 GPIO/ATSAME54/include/component/pcc.h
create mode 100644 GPIO/ATSAME54/include/component/pdec.h
create mode 100644 GPIO/ATSAME54/include/component/picop.h
create mode 100644 GPIO/ATSAME54/include/component/pm.h
create mode 100644 GPIO/ATSAME54/include/component/port.h
create mode 100644 GPIO/ATSAME54/include/component/qspi.h
create mode 100644 GPIO/ATSAME54/include/component/ramecc.h
create mode 100644 GPIO/ATSAME54/include/component/rstc.h
create mode 100644 GPIO/ATSAME54/include/component/rtc.h
create mode 100644 GPIO/ATSAME54/include/component/sdhc.h
create mode 100644 GPIO/ATSAME54/include/component/sercom.h
create mode 100644 GPIO/ATSAME54/include/component/supc.h
create mode 100644 GPIO/ATSAME54/include/component/tal.h
create mode 100644 GPIO/ATSAME54/include/component/tc.h
create mode 100644 GPIO/ATSAME54/include/component/tcc.h
create mode 100644 GPIO/ATSAME54/include/component/trng.h
create mode 100644 GPIO/ATSAME54/include/component/usb.h
create mode 100644 GPIO/ATSAME54/include/component/wdt.h
create mode 100644 GPIO/ATSAME54/include/core_cm4.h
create mode 100644 GPIO/ATSAME54/include/core_cmFunc.h
create mode 100644 GPIO/ATSAME54/include/core_cmInstr.h
create mode 100644 GPIO/ATSAME54/include/core_cmSimd.h
create mode 100644 GPIO/ATSAME54/include/instance/ac.h
create mode 100644 GPIO/ATSAME54/include/instance/adc0.h
create mode 100644 GPIO/ATSAME54/include/instance/adc1.h
create mode 100644 GPIO/ATSAME54/include/instance/aes.h
create mode 100644 GPIO/ATSAME54/include/instance/can0.h
create mode 100644 GPIO/ATSAME54/include/instance/can1.h
create mode 100644 GPIO/ATSAME54/include/instance/ccl.h
create mode 100644 GPIO/ATSAME54/include/instance/cmcc.h
create mode 100644 GPIO/ATSAME54/include/instance/dac.h
create mode 100644 GPIO/ATSAME54/include/instance/dmac.h
create mode 100644 GPIO/ATSAME54/include/instance/dsu.h
create mode 100644 GPIO/ATSAME54/include/instance/eic.h
create mode 100644 GPIO/ATSAME54/include/instance/evsys.h
create mode 100644 GPIO/ATSAME54/include/instance/freqm.h
create mode 100644 GPIO/ATSAME54/include/instance/gclk.h
create mode 100644 GPIO/ATSAME54/include/instance/gmac.h
create mode 100644 GPIO/ATSAME54/include/instance/hmatrix.h
create mode 100644 GPIO/ATSAME54/include/instance/i2s.h
create mode 100644 GPIO/ATSAME54/include/instance/icm.h
create mode 100644 GPIO/ATSAME54/include/instance/mclk.h
create mode 100644 GPIO/ATSAME54/include/instance/nvmctrl.h
create mode 100644 GPIO/ATSAME54/include/instance/osc32kctrl.h
create mode 100644 GPIO/ATSAME54/include/instance/oscctrl.h
create mode 100644 GPIO/ATSAME54/include/instance/pac.h
create mode 100644 GPIO/ATSAME54/include/instance/pcc.h
create mode 100644 GPIO/ATSAME54/include/instance/pdec.h
create mode 100644 GPIO/ATSAME54/include/instance/picop.h
create mode 100644 GPIO/ATSAME54/include/instance/pm.h
create mode 100644 GPIO/ATSAME54/include/instance/port.h
create mode 100644 GPIO/ATSAME54/include/instance/pukcc.h
create mode 100644 GPIO/ATSAME54/include/instance/qspi.h
create mode 100644 GPIO/ATSAME54/include/instance/ramecc.h
create mode 100644 GPIO/ATSAME54/include/instance/rstc.h
create mode 100644 GPIO/ATSAME54/include/instance/rtc.h
create mode 100644 GPIO/ATSAME54/include/instance/sdhc0.h
create mode 100644 GPIO/ATSAME54/include/instance/sdhc1.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom0.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom1.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom2.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom3.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom4.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom5.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom6.h
create mode 100644 GPIO/ATSAME54/include/instance/sercom7.h
create mode 100644 GPIO/ATSAME54/include/instance/supc.h
create mode 100644 GPIO/ATSAME54/include/instance/tal.h
create mode 100644 GPIO/ATSAME54/include/instance/tc0.h
create mode 100644 GPIO/ATSAME54/include/instance/tc1.h
create mode 100644 GPIO/ATSAME54/include/instance/tc2.h
create mode 100644 GPIO/ATSAME54/include/instance/tc3.h
create mode 100644 GPIO/ATSAME54/include/instance/tc4.h
create mode 100644 GPIO/ATSAME54/include/instance/tc5.h
create mode 100644 GPIO/ATSAME54/include/instance/tc6.h
create mode 100644 GPIO/ATSAME54/include/instance/tc7.h
create mode 100644 GPIO/ATSAME54/include/instance/tcc0.h
create mode 100644 GPIO/ATSAME54/include/instance/tcc1.h
create mode 100644 GPIO/ATSAME54/include/instance/tcc2.h
create mode 100644 GPIO/ATSAME54/include/instance/tcc3.h
create mode 100644 GPIO/ATSAME54/include/instance/tcc4.h
create mode 100644 GPIO/ATSAME54/include/instance/trng.h
create mode 100644 GPIO/ATSAME54/include/instance/usb.h
create mode 100644 GPIO/ATSAME54/include/instance/wdt.h
create mode 100644 GPIO/ATSAME54/include/pio/same54n19a.h
create mode 100644 GPIO/ATSAME54/include/pio/same54n20a.h
create mode 100644 GPIO/ATSAME54/include/pio/same54p19a.h
create mode 100644 GPIO/ATSAME54/include/pio/same54p20a.h
create mode 100644 GPIO/ATSAME54/include/same54.h
create mode 100644 GPIO/ATSAME54/include/same54n19a.h
create mode 100644 GPIO/ATSAME54/include/same54n20a.h
create mode 100644 GPIO/ATSAME54/include/same54p19a.h
create mode 100644 GPIO/ATSAME54/include/same54p20a.h
create mode 100644 GPIO/ATSAME54/linker/same54p20a.ld
create mode 100644 GPIO/ATSAME54/main.c
create mode 100644 GPIO/ATSAME54/make/Makefile
create mode 100644 GPIO/ATSAME54/startup_same54.c
diff --git a/GPIO/ATSAME54/astudio/demo.atsln b/GPIO/ATSAME54/astudio/demo.atsln
new file mode 100644
index 0000000..f9190a2
--- /dev/null
+++ b/GPIO/ATSAME54/astudio/demo.atsln
@@ -0,0 +1,17 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Atmel Studio Solution File, Format Version 11.00
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "demo", "demo.cproj", "{22CBC4AC-0DB7-F32F-F866-38AB515616EC}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Release|ARM = Release|ARM
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {22CBC4AC-0DB7-F32F-F866-38AB515616EC}.Release|ARM.ActiveCfg = Release|ARM
+ {22CBC4AC-0DB7-F32F-F866-38AB515616EC}.Release|ARM.Build.0 = Release|ARM
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/GPIO/ATSAME54/astudio/demo.cproj b/GPIO/ATSAME54/astudio/demo.cproj
new file mode 100644
index 0000000..7cf2b32
--- /dev/null
+++ b/GPIO/ATSAME54/astudio/demo.cproj
@@ -0,0 +1,590 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <PropertyGroup>
+ <SchemaVersion>2.0</SchemaVersion>
+ <ProjectVersion>7.0</ProjectVersion>
+ <ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
+ <ProjectGuid>{22CBC4AC-0DB7-F32F-F866-38AB515616EC}</ProjectGuid>
+ <avrdevice>ATSAME54P20A</avrdevice>
+ <avrdeviceseries>none</avrdeviceseries>
+ <OutputType>Executable</OutputType>
+ <Language>C</Language>
+ <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+ <OutputFileExtension>.elf</OutputFileExtension>
+ <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+ <AssemblyName>Demo</AssemblyName>
+ <Name>Demo</Name>
+ <RootNamespace>Demo</RootNamespace>
+ <ToolchainFlavour>Native</ToolchainFlavour>
+ <KeepTimersRunning>true</KeepTimersRunning>
+ <OverrideVtor>false</OverrideVtor>
+ <CacheFlash>true</CacheFlash>
+ <ProgFlashFromRam>true</ProgFlashFromRam>
+ <RamSnippetAddress>0x20000000</RamSnippetAddress>
+ <UncachedRange />
+ <OverrideVtorValue>exception_table</OverrideVtorValue>
+ <BootSegment>2</BootSegment>
+ <eraseonlaunchrule>1</eraseonlaunchrule>
+ <AsfFrameworkConfig>
+ <framework-data>
+ <options />
+ <configurations />
+ <files />
+ <documentation help="" />
+ <offline-documentation help="" />
+ <dependencies>
+ <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.25.0" />
+ </dependencies>
+ </framework-data>
+ </AsfFrameworkConfig>
+ <avrtool>com.atmel.avrdbg.tool.edbg</avrtool>
+ <avrtoolinterface>SWD</avrtoolinterface>
+ <com_atmel_avrdbg_tool_edbg>
+ <ToolOptions>
+ <InterfaceProperties>
+ <JtagEnableExtResetOnStartSession>false</JtagEnableExtResetOnStartSession>
+ <SwdClock>2000000</SwdClock>
+ </InterfaceProperties>
+ <InterfaceName>SWD</InterfaceName>
+ </ToolOptions>
+ <ToolType>com.atmel.avrdbg.tool.edbg</ToolType>
+ <ToolNumber>ATML2748051800001669</ToolNumber>
+ <ToolName>EDBG</ToolName>
+ </com_atmel_avrdbg_tool_edbg>
+ <preserveEEPROM>true</preserveEEPROM>
+ <avrtoolserialnumber>ATML2748051800001669</avrtoolserialnumber>
+ <avrdeviceexpectedsignature>0x61840000</avrdeviceexpectedsignature>
+ <avrtoolinterfaceclock>2000000</avrtoolinterfaceclock>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+ <ToolchainSettings>
+ <ArmGcc>
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.general.ChangeDefaultCharTypeUnsigned>True</armgcc.compiler.general.ChangeDefaultCharTypeUnsigned>
+ <armgcc.compiler.general.ChangeDefaultBitFieldUnsigned>True</armgcc.compiler.general.ChangeDefaultBitFieldUnsigned>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>__SAME54P20A__</Value>
+ <Value>DONT_USE_CMSIS_INIT</Value>
+ <Value>F_CPU=120000000</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>../../include</Value>
+ <Value>../..</Value>
+ </ListValues>
+ </armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+ <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+ <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+ <armgcc.linker.general.GenerateMAPFile>False</armgcc.linker.general.GenerateMAPFile>
+ <armgcc.linker.libraries.LibrarySearchPaths>
+ <ListValues>
+ <Value>%24(ProjectDir)\Device_Startup</Value>
+ </ListValues>
+ </armgcc.linker.libraries.LibrarySearchPaths>
+ <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
+ <armgcc.linker.memorysettings.ExternalRAM />
+ <armgcc.linker.miscellaneous.LinkerFlags>-Wl,--script=../../linker/same54p20a.ld</armgcc.linker.miscellaneous.LinkerFlags>
+ <armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
+ <armgcc.preprocessingassembler.general.IncludePaths>
+ <ListValues>
+ <Value>../../include</Value>
+ <Value>../..</Value>
+ </ListValues>
+ </armgcc.preprocessingassembler.general.IncludePaths>
+</ArmGcc>
+ </ToolchainSettings>
+ <OutputFileName>Demo</OutputFileName>
+ <OutputFileExtension>.elf</OutputFileExtension>
+ </PropertyGroup>
+ <ItemGroup>
+ <Compile Include="..\include\component\ac.h">
+ <SubType>compile</SubType>
+ <Link>include\component\ac.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\adc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\adc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\aes.h">
+ <SubType>compile</SubType>
+ <Link>include\component\aes.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\can.h">
+ <SubType>compile</SubType>
+ <Link>include\component\can.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\ccl.h">
+ <SubType>compile</SubType>
+ <Link>include\component\ccl.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\cmcc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\cmcc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\dac.h">
+ <SubType>compile</SubType>
+ <Link>include\component\dac.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\dmac.h">
+ <SubType>compile</SubType>
+ <Link>include\component\dmac.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\dsu.h">
+ <SubType>compile</SubType>
+ <Link>include\component\dsu.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\eic.h">
+ <SubType>compile</SubType>
+ <Link>include\component\eic.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\evsys.h">
+ <SubType>compile</SubType>
+ <Link>include\component\evsys.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\freqm.h">
+ <SubType>compile</SubType>
+ <Link>include\component\freqm.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\gclk.h">
+ <SubType>compile</SubType>
+ <Link>include\component\gclk.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\gmac.h">
+ <SubType>compile</SubType>
+ <Link>include\component\gmac.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\hmatrixb.h">
+ <SubType>compile</SubType>
+ <Link>include\component\hmatrixb.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\i2s.h">
+ <SubType>compile</SubType>
+ <Link>include\component\i2s.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\icm.h">
+ <SubType>compile</SubType>
+ <Link>include\component\icm.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\mclk.h">
+ <SubType>compile</SubType>
+ <Link>include\component\mclk.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\nvmctrl.h">
+ <SubType>compile</SubType>
+ <Link>include\component\nvmctrl.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\osc32kctrl.h">
+ <SubType>compile</SubType>
+ <Link>include\component\osc32kctrl.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\oscctrl.h">
+ <SubType>compile</SubType>
+ <Link>include\component\oscctrl.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\pac.h">
+ <SubType>compile</SubType>
+ <Link>include\component\pac.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\pcc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\pcc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\pdec.h">
+ <SubType>compile</SubType>
+ <Link>include\component\pdec.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\picop.h">
+ <SubType>compile</SubType>
+ <Link>include\component\picop.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\pm.h">
+ <SubType>compile</SubType>
+ <Link>include\component\pm.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\port.h">
+ <SubType>compile</SubType>
+ <Link>include\component\port.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\qspi.h">
+ <SubType>compile</SubType>
+ <Link>include\component\qspi.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\ramecc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\ramecc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\rstc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\rstc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\rtc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\rtc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\sdhc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\sdhc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\sercom.h">
+ <SubType>compile</SubType>
+ <Link>include\component\sercom.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\supc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\supc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\tal.h">
+ <SubType>compile</SubType>
+ <Link>include\component\tal.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\tc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\tc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\tcc.h">
+ <SubType>compile</SubType>
+ <Link>include\component\tcc.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\trng.h">
+ <SubType>compile</SubType>
+ <Link>include\component\trng.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\usb.h">
+ <SubType>compile</SubType>
+ <Link>include\component\usb.h</Link>
+ </Compile>
+ <Compile Include="..\include\component\wdt.h">
+ <SubType>compile</SubType>
+ <Link>include\component\wdt.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\ac.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\ac.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\adc0.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\adc0.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\adc1.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\adc1.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\aes.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\aes.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\can0.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\can0.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\can1.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\can1.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\ccl.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\ccl.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\cmcc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\cmcc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\dac.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\dac.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\dmac.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\dmac.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\dsu.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\dsu.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\eic.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\eic.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\evsys.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\evsys.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\freqm.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\freqm.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\gclk.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\gclk.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\gmac.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\gmac.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\hmatrix.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\hmatrix.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\i2s.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\i2s.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\icm.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\icm.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\mclk.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\mclk.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\nvmctrl.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\nvmctrl.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\osc32kctrl.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\osc32kctrl.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\oscctrl.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\oscctrl.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\pac.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\pac.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\pcc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\pcc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\pdec.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\pdec.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\picop.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\picop.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\pm.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\pm.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\port.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\port.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\pukcc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\pukcc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\qspi.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\qspi.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\ramecc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\ramecc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\rstc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\rstc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\rtc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\rtc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sdhc0.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sdhc0.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sdhc1.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sdhc1.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom0.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom0.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom1.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom1.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom2.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom2.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom3.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom3.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom4.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom4.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom5.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom5.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom6.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom6.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\sercom7.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\sercom7.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\supc.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\supc.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tal.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tal.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc0.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc0.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc1.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc1.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc2.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc2.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc3.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc3.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc4.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc4.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc5.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc5.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc6.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc6.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tc7.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tc7.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tcc0.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tcc0.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tcc1.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tcc1.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tcc2.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tcc2.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tcc3.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tcc3.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\tcc4.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\tcc4.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\trng.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\trng.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\usb.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\usb.h</Link>
+ </Compile>
+ <Compile Include="..\include\instance\wdt.h">
+ <SubType>compile</SubType>
+ <Link>include\instance\wdt.h</Link>
+ </Compile>
+ <Compile Include="..\include\pio\same54n19a.h">
+ <SubType>compile</SubType>
+ <Link>include\pio\same54n19a.h</Link>
+ </Compile>
+ <Compile Include="..\include\pio\same54n20a.h">
+ <SubType>compile</SubType>
+ <Link>include\pio\same54n20a.h</Link>
+ </Compile>
+ <Compile Include="..\include\pio\same54p19a.h">
+ <SubType>compile</SubType>
+ <Link>include\pio\same54p19a.h</Link>
+ </Compile>
+ <Compile Include="..\include\pio\same54p20a.h">
+ <SubType>compile</SubType>
+ <Link>include\pio\same54p20a.h</Link>
+ </Compile>
+ <Compile Include="..\include\core_cm4.h">
+ <SubType>compile</SubType>
+ <Link>include\core_cm4.h</Link>
+ </Compile>
+ <Compile Include="..\include\core_cmFunc.h">
+ <SubType>compile</SubType>
+ <Link>include\core_cmFunc.h</Link>
+ </Compile>
+ <Compile Include="..\include\core_cmInstr.h">
+ <SubType>compile</SubType>
+ <Link>include\core_cmInstr.h</Link>
+ </Compile>
+ <Compile Include="..\include\core_cmSimd.h">
+ <SubType>compile</SubType>
+ <Link>include\core_cmSimd.h</Link>
+ </Compile>
+ <Compile Include="..\include\same54.h">
+ <SubType>compile</SubType>
+ <Link>include\same54.h</Link>
+ </Compile>
+ <Compile Include="..\include\same54n19a.h">
+ <SubType>compile</SubType>
+ <Link>include\same54n19a.h</Link>
+ </Compile>
+ <Compile Include="..\include\same54n20a.h">
+ <SubType>compile</SubType>
+ <Link>include\same54n20a.h</Link>
+ </Compile>
+ <Compile Include="..\include\same54p19a.h">
+ <SubType>compile</SubType>
+ <Link>include\same54p19a.h</Link>
+ </Compile>
+ <Compile Include="..\include\same54p20a.h">
+ <SubType>compile</SubType>
+ <Link>include\same54p20a.h</Link>
+ </Compile>
+ <Compile Include="..\startup_same54.c">
+ <SubType>compile</SubType>
+ <Link>startup_same54.c</Link>
+ </Compile>
+ <Compile Include="..\main.c">
+ <SubType>compile</SubType>
+ <Link>main.c</Link>
+ </Compile>
+ <Compile Include="..\hal_gpio.h">
+ <SubType>compile</SubType>
+ <Link>hal_gpio.h</Link>
+ </Compile>
+ </ItemGroup>
+ <ItemGroup>
+ <Folder Include="include" />
+ <Folder Include="include\component" />
+ <Folder Include="include\instance" />
+ <Folder Include="include\pio" />
+ </ItemGroup>
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/GPIO/ATSAME54/e54-tests.pdf b/GPIO/ATSAME54/e54-tests.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..7caf5b108fea960401b8994706ee5d0a1f4c221b
GIT binary patch
literal 429068
zcmaI7b8sclvo4y6v*Tok6MM(DIWZ@;Z5tC!Y}>YN+qN^Yd4H$QJ@4K3Ue)_+t?qBF
zuI{RDRj=-<CRY#@r(>e$003Bt7>Vo*Edf-L#wNDT7S0|ZfQhZ~e`(nM2NC*@X!3ul
zIsdnsmlwbwZei_g;z-0GZf)RfB5Gn}XKVsskTJ0}b2cYpW@Kk!W&9tJiHMDpk&TTR
zz@Xw`Z$iYN?CfY_U<2Ui2RQxr&OP(83r1gisELE$>3VCsX??q+Fv(R-(`9VFyr!IP
zf;qlI+gO{CoxWAS7x<Hrt?>^g9ylBv*=W7Bv9(lh0NL&z7)UfUShzz}SSf#nK%t83
z$t)cUlZoNjPKN96Z`QlZ>*>w3HkOl2E~ny6t3Rm1o-ca}dOm7S3zsWTQzH8#%&7H<
zY>Ue?id)YsVz7jp5wYj{A?wZUZ+f52n0o;^#AGkB%040ob9$Y3(EI!q62D$biZxg|
z(gl2vAjkwY!h9aKimR{I2}gH&aQ8~C#jN{U%v^)vuY7xGe-eLSxm)hkH%Tw&I9*KB
z{#o{h#Nh0{{E(eKm+;&cIfZUz=yV)<Ygq9;*;<D|)%@lcM*FuW&0Z}bei(3qEaLmP
zc4DpNVDwECI?J&_`Y?b&^PWQceG+JsBK&&N`?;TllE-Q7gWCTryxQUTuege^OCd1;
z1zo~?Dah)LBa;TJoIuFk3X*uP;-pfm`EWU>x(j|UeMj)A%__xOCy4&hG3E6&O0
zyO_L1ul?EEJO;f#C8xvK=9|z`FOsNJIa=ZH{PBX_7PldHOQFXu?%{&tq2`<RDIyBi
zCY1a9dvrll{cGfkreR0Dvit)(Z7{5Lz;EjouTL$#W%BD|X^x~!gBN~Y3MHsC$Xhs3
z@TJuG`lN<nhmP%@yohTdh-^4Ms5@xU9Ltcn1UFcbQ25TT-wCI6!jWzgbvIJoK7$A#
zwhpSFDUiS>6OWV{ti>B)-qfOEeS*Bx1sjt3wf0X(jxzAccY2OHtb6Ju3pOUs>k=KD
z+yXRyn26rg*8^_*g^4rUGY4mUy8giU{&aX#hWEa^cm{dLGV$$_#ds^A<vU&{AhM)9
z>=$@=Dsb3JLH0TBAvI_Fq`_)8?zQ93pLD!>K^ZE4v`WyJ(SiP$sj{7g{)+Q>HWBzf
zoNxzkPH-Gib`LnX*)%Ke9_jkqKBs1XNktdxh413jjec5-v?QB$0&bl4FbOkvWcJ2e
z4Xg3TOW~%_9qDz==$Gq!L$$>3g#K?q*;5+sY7Cvhr~DU{XHl&D)?bnP!sK1Z7Fv`?
z7<tJo9?(wY%y2oP6ycC*t$M{eH6q0<V+_3Rre_pK7BGl@6Js+(CU6hv4*6oEko9(4
zOyA))vco!w?ZY|wY<j9Nzntb&ZZByP#@kL+UKeuQ=DVKCJf2KU;#`?}(zNL_V$w^-
zN!=|RdG8+%9mI0Qp|A272(5nM3L)T#di9$5czDJ`pSK}q<r(=!KLpD6vU4$gNsNwt
zfuG6$Ma~ORP8#Bk{+kvv$6HL01fI+?lk51wThHu9LVC}Y9@<in=G{)Y`{rHFk~Ty1
zIZ_%qBXLL6>!=bQBf>vAunFU6E+lshv)dDjU|)ms`MnvSP5ME}`mcDaF~jvc$3+Hp
zJ>n~c`<SE=`XfGJ-)m0uW}=&RD~<DMe(az&Y;ySm^tI!<`B@s|fq&VAe1<*wNX+w&
z)Rmnm7e3y*gV0Th!ya_a1KOfk9Qc6MSnDcH__Kx;m$DUvnUfmb^)tzT2ijMaITObB
zEM>XoEArwbtK8QbdrBX2bQnRACkID}z|{WSLt=c-Oo8X6*pHmS2`renCPpL1ot`Bl
zE?pz)PF}{Z`0T&^)foANta?$K&~HM&V7kO@O!C0~h%%=k<j>eIG~4!d#B-QTVwAuY
zbp77}F4(Tic35!yceD#v-x?|WBZmWH9>?x4G?Ogh8QErX|2O>qIBUE9d4k`K_<!8~
zf5HDjo_ofbE)@A+xOR=k?7_S*dLD6T6hJS!H?m{)*xn~;M+6;&|Gx(Q$Fcv@^f#&P
zCF*~<|Gg0{>q+yOQ+R`j5=i69v42AmRw}_nCWxmEibZczWTzGsE5%#N6$eWEGe^=4
zo)+4e(`5}q+Vj?`rrS|9r)e0<L_6_3F+C}o)|tNWp7EKEy8V_{sZXQ@3I!`jA&gTN
zIp>j^BXV<8CH~R`Wn^M;Gq~x(7ZFiG#rW_(QFNqbO%MbK`~*2)R@KQXBjRcev)BJF
zJ*`nI{1OMZyYhA75VpJWbXp-aC34>XPJ^mO!MInCl*;2T`SLSXa^v<Fb_4qzDaaw9
z`6t;3x}p|0qYmF}Ps5!+H*BWw;^y^5*c+o8S1-t}x8(rh1?~g=gVh&WV5AN&bY~Yb
zGZuZ12x*T(`>$3UieG=q_n4&1V3_0=gFXUxR{>W*$t4FR$y&r}!~%NVbsg#D4%m*F
z0Co%y&A%^v-WkREVA!MRopN~^XieX7%S=(!yPmo|mm4ps^4#yOXubyHKN)7aRJu%C
z3&r-|3w($}xL6FDt@>Y`+u2uKIt@H#Q<vs;RyG#V9Bk~1D@)6R<rStXs);E{$v~`N
z5sx+v-<*{LS8NtG%Oqinq%bkzA0y1zN9^vn@0k!^-9M(U!$<Catu{cCBo~T3AaW9y
zJ2<BQFeA*F<l-_xP^#u6Hi;~bj4BzlG$SvcoN!@x&x9B`=bJX*t!aR%uBm!{;D!-@
zxp4hTzrX(h1*uIxx@XN;UFn9j%WpOyc<@T|%=)k-;_+@g&n>Uh!^(j5FJXLF30e(8
zBm42)UKQh*A+<8(&IbXFX4D8qU2h=%2%>@83-_FkUX6h;^!%kB`i~0)NjL2YwUU{0
zlat;Rx>q%hYC(~Y(5vIj9XY%w^eTC*1@cC%*$f6m`mSJei7%1YyOy}Q<F{aSNw)#f
zX+XcGS&RS}GOV{{jMK~rEcG>xhn?eOym91g$rpB<^!%U$bKmD8TVT5oVxA8@R@ubT
z08=9n9D;|(%X~FFSrb~37Vi>Y|7|pjQpwGE>u`E{G3)lyhXBjqw}{@|&MQq61WyY0
zy<@=JhXCP6(EId{<((GiHK{=9w`ceB3((f_1H$0>9!WFV+H#0b9Aly0JWQ0j*y!vU
z3(8X^;poHSJS55<8L#@%(tw$y>Ce&1pMpLU@omukh>wN3(;<95kBxzawDM*%#6Wy6
zBfY$ZdI5k=eafPdpdO6OEyv}VMz>+_oS6pFU0eT}kptqOXMlHCcJ`NUKY5HN(L17h
zW`rL}4*a^S@VScNykngF<)s0wHNzgJDCf_;5oIknj>TSj{$HG$T4$Gin2A!*@{+|w
zY6;^3U>6k;30kycnpiEZo;r(J#Zt+}S&-d795gj7!?0`6eWpPb;>rmC6P}-M7Yo#!
zWeP&|fn)Q<)s!OUao&uFDCn-k$}Q@I587cyx!C-F?dMMM1RFB>vVG-iV2r8QD?%Hi
zX46mXtWrvvoOF?A{uL%prUCPxr7g_C+IC&3dlv%`*rDk_&3Ahg{JaE_Irbe~E*otU
zmlprlMF7ua@S<|3LbK+1Jsx9AML5B;Y(IrMJaALoGcC;yvdIUGcv7y`up<6x?98^*
zXD04h=ys1REGb*;U2u1t2v4})l_D(u)jC-`J_@`l+dAn}bG?e#qv<$)#8V<Y>~xfy
zAqq-s?_S^b(QRFE8ii}miZS^`8&39v5-v90R77yHqy_IUabrTy#4W0~`x>LTcP1xB
z=v=))$Z(mm1HzyKEB){YDvS(sH6&V4yNx|P<>lI3hoih6!<qIk<jOyO?qFW!vtS2h
z>!CP#-h$_6HTba}mXh9V;Wfp#!e|WOeZ8ItgT&kx@;NXMKv)&zdVT7@w4iw|UUv49
z5tm8k`3rDGEihl*8Gka^cD-Gz0B703XCdc>-f0u*UwjH~$YV5jYz!Arb+Q<+lIbvH
z3V~!A;DzRg_b3j3WG4JMdIkBv<zNvmFY!+i<3pb+&yR*Q`26>?9rbzWly@nS0nb-s
zH^3Vo^!C6-H>e+Qi-<0dv)J&Edj?&Jzeu<iz0+W9=`NhWo46V);YG8~mCAyLAA+O~
zKR!ECG~+o?Eif+<K!p(TC_vcn(I#5a_QGDu^M6H2Cn9QO=)Da~5X_}<0#S)$2!i;n
zOETx+-_`!*@r44!L(WJAYuQz~8o!EO<3;Vg1oy0T!N+rsQ-mT*Sd%nlod3{j3@hT&
zkkF+-Y-#Ld?$up;HMh-c>sE&%Ac-=@9ihOopKm!C4)%WN>sG%EszVWWnZ>9xxj;)X
z)EVLtqajMI_AIZia-+NgnxTDbOi53XZV>iY88wl7(O*(}ovaBmAlNg5reqCcr*LRp
z+zCT>yLLl+8;s-y3n^#a!+L7De_AEiC6y*t32s?)>Eq~w^x=rq|5&5y6YB$KAx@#4
ze{d^u0O|{As)>6p5j>HFF;GrS?&t7s5d40pBKSaNi=<hDEd}|(^TIbF3F6{5z<nI;
z+ChJ#y~OlJ<el46)uCjE5!awA@entmOF0W8Q6Acp5Z|xmZXIKresP&2gL`wE&p^HW
z=^p{|=Rbc5i4ZEi`1ij9zvTApSdU<XpUn^TK%LTi_yE7W8}{Ju;u|x79pXAUnBDwr
z4%LUlZ1Rtr;oK?6n@}Mw>|GZ?jp7Sm@Xj1r&HSt#=p&?`2B=$nV+CMPbdT$Y2YyBL
z-vfQc_EH+rMyPlt_A~%JxiOzyvac+F83p(Bet8gH(G4(|67=z>A00?gV!|)Jr-<wE
zr{4e&qrfR@klH^0L{j1uGzjbW1q1<~5H;b!ps9FS&7;6SQu|}5cz^Bv00`hU9z%Ti
z_kXhPJcGPr`h9>`MK?Nt=h@4hyxNrhEnv6o9zDQqKL0w`o@dJUXRw{(3q`ONXjAxp
zOJ<J(z@hX49sH9@TYisQ^P!3LoefxBTpQZ|8(3Y4Q=MCz(N7OZQErXwFA7Q)_Lru*
zEVO3|j-b;1WdIWlPi0+F8`ZB0(4xweH(&{t1+pux3hwa&E<lw(S+Ra(N*mAxJ5g2U
z)u#7T186{*vIbDWzJLi3Z9#2fKN`RXh^eeDYCs$e1w2+xmB@3ORRNzB*`ozGft;07
zMe-v0tpQm;Q^i!tydYtoV0J(iP?L&PIZW9+fA&{ifG}S$H=qe<Ni|5NqFkEK7$i&{
z3;-Mf$DyN4z>0uUR6u2_e1%`cQhENu{K2ruv;?dnM8M)WVt@zG5d;Z3R2VIe6(bhx
zlkej&F9o|%x<SAV6YPLNJOZP~JuBSJ)i2R6&@a-@(=XP~*Duu1%`M3-kRL6SpPe5?
z0N?^F0n`8~007_!U<N1w&@_uv1H;4tAXqAUpgI5nO6JF{{|FTsRix5OVE+j)TKOfi
zUjXDiE`aIR-va9=Ln@GegADjT2nZCX>Xg{40d5!FAO-g*xM%QR_rN?7_zNhzTPYxe
zhwK#IlnD8NdI>?DOr<ptF9W&V1pm#!&)n`GyKX^m;{Ix&kK}$k^SK%Y_cY8WE6r7D
zpl;y}INfEBdG`tE<8MC$2(RD<FWAhYTW>bsPj1hw@$SF4$bVfD^rq=wz&fD(AS6Gp
z`TYm;2{L#D#QPsc0wk#Lif>@)-caZ~Q!zgo>E4KfA%G#LK~Kuqg|#vKuKxWZKwp`N
zFVtWd5U=1~DA1R&6rwBQns9Lm%sZ$58QSF^*fZieH`o>a;uPe|Rjw_2FJDkQcCVXx
zd>8B37VB7xMSRC;7mvj_kNK%<`W-u9Cm*L<a&K8^i`HMu{3!#pDY_@FS!6ex$T6F^
zqTFh$umWdKC+mS2TmibonY{ebYRTAuwL9K72?eHxU`h|U%9pwZUTekZ#NT`Lux-M6
zRKz+)UKa|sqsGShRUOH*9qY!K4f&0JBk%90&A!3}>r43Z;|4k4o9Trxzz^jEV%HD$
z3ugBk=G*6H2f~l=#jDQ`>w|B%2f~-(rK8VJt9{;q=VhbU5B`IrZwK&&dBYLZ1NRZN
z+w<cKdQ58MakmD-kM6~)cjZ?qL+XJ!y(41|M71cA_ib*n^GF0VOPIM$eyxLoh^Q4r
z@I6&!No{n08*o{PGqfKUPytd=D#cborz%kp&r1}B3pNCZ0RbRU5D=j}Eb~}7Okp%P
zH!rt1H$S&97aOt|!H5eA2MPoQ2gL+6mm65CiJgJ`!f`{oy94p9c5@x*2ebMLb5j%K
zhxl>b_l@*XvFitK{fhXa)++%0rFbLJO9=f9`_kc$;TA|Z%mXTFLADGVwJR80lQMu0
zz6V(sD@f!e&*y~*M+&nAQv+Dc6I_7IAagi8LycsdNUkfNNE3a>k=%k^4a~WAZNa<<
zM<4bo4a#5*psCVn?yOv1lrT*&CSVG<4@{?GRWi?2knfZ26QjBQ|Gcp&R)yJ-D=<8$
zZ>X1<K0=sp9LATNT>+?XxR;ndKgch_-X-KdKd>*Gn{ULgncW@mZ;BUzfNxU!XY7}g
zUIF+otX)5(FSFg8AK$DmIe`LzFVM}vE+KR@A*3JJ2g=Lm?lsY-nK&qlp|Ccnzg!40
zRoI<8xB;Z0s&HCTo7v9{kOtA_%}N+B1&aYOmDB|d_=7!wo}dQ>&WL_(z!vaW0ah7S
zQRzf+v<RgzR)jc17&90QN&t%RC@Li|G|(ShBA}>Op|?>Yf0fVQXcv9=8~l$C&PPpO
z59F8F4TJwT!_7?4H^z$|cph@V&d?iPN(1qT3Fl!eYj?wYJdCTW9$ruFdp->PWwMUC
zgTX~`<)tuuFBBHP{oXY_@G8vix_dX^-`3{S<iAK~EpO@PWte8?iDv!R*W0NrC-$DE
z*MceQ<72Lj6ua%l*W)P$p+BeFQz98Lwx*#Y*<mKu^i}4YZLc9yG8CI;v!<0KbJbJK
zCI`hYAy-kz)~CnpKwEuk{&oMIRsXb6XkIIk9cXB!e>=NVmSklS?59&v=ZJBLb%>W9
zw=P>3gz77NPFw9RST!A9TL%}A|5<(U?@_dw>Riyo4%%*;w*1s1=1@%$%K8NQA`$E7
zT|(0!`%kZBNZ3PGz<#Jg5UU1HU+KQ~u5Hl>PjtK!s&9AEHa2=mmezPVm>WFj!(h5H
zz)oFcfA@A?Z7aw>YsC86n#;L8LpZf}2xo0I5T0IU<D8#f`M*3VSh;OLRBh4axx3v%
z++JxoYyvGWZS^DY83T!UKD6w1Ec|w+$KI?jY$iQ7el|bbTzX!-s~#J|tEMrq>)Dz9
zz8RP$Oc-$PI<s96p$PcfqknY4;%drx!N$WTBZ|JjTjL=zKs=?3SkSKP(sE9W!K2)y
z{^+)p`q%4MFrgBE^+!^CR+)CCc8T$CDKyh1CKIY2#Ugtu!~f(wEgV%98dK`k3k=R;
zSPa%-;I^PqlXtOqU1pb7w2`Bq>%mTukrD+(@K3*#NXb+tIB{B6!^m1(e+&q_klN|F
zQU1SU$)#Wh-Vo{N*7%rFQ?~dhGwA~UHF!5JaXacKoj>-HAWFTqKeBzW^;SBNSzMf;
zna9?-3AbJTHI1rnaO+>3;}}0*H7z|gBVCfM)M5MaiC3eNogvb%w|X25%l1VHz5M7g
zCmpn2NBDN{y@7A_KyPcXAPpqzQ|62}Bn_DI&X3B#vI}9}g%-6tERZxu%^`c~>9axj
zg26|U>-dfpAsQ7e=O~6JL4}T8h#DS>cp-(#w<Aq#1^uh+BfoK@^aR5fjLFT()yu`2
z6Q~6~=INX|JWzOI`GoO@`qK1sTMw<B?i{0~z%7$Ny+fjrKnNR+jBHDO=wIS1Adfeu
zW)K<gexNfM;TVxp4wKtTAyE2)5{cPz)TVgh>#h&t>JDVs;9@Wm7@eTnj-5Ig-dy+d
z2DcK*8whL!Gv-tq5p5)}a^dI1P7R%L)}yKg)$%L+F|h_7mrik=>DrNWVr&I>1Ud3E
zW~WXuooU`E-Z0w{x1z7WxVMA5qpsw(N%!mqcB(#f98U-y_#Pl0h<4rPx=#5Ye4GXT
z_`xpvp?qTRn<F58!x}#2UkhG76D1dtI3V}!fUSo@&-t=K@)qo=m}Bz=AmxYtK>opj
zTtIrN_<((L3%7fj;Efk987!X_|HU61ou89mGRJaic6vgDGn0QZ%k&`qP*LM@QgXmV
z_Q3nb@Blu#E`7RkYVrVhqkF^m#Q*%!74QYA^t>(k><0nT4Q8z&SN=p*`o!si07(#$
z%StSKWcR#db^l2ry8d}eM=MTf1nm<&y!+SwS~Xjw<<^^QlXSB!rG#Z~L<EHb@9m4z
z&KHvP3-u=9&*<YnN!t(X`6~!O@hJz}l5g4}QqeQ&FA;O0D?I7>{WLPlUtBR!CqBtN
z9HS>*j-88ef9Em3xTCmx<O}w4=KSsx^A-!-C`%=jI-x9JlO%BxEZ!+crOV{+;$I$k
z54S5&d|?^~yaX)*{f@Y9)gGQ+9yi9`Nl)!guTPD>o_!vEoF@3?#t?nL4R#{uB^b#^
zz5>6#!udr;0)q5%=Ne~E;oQU(!QBy{p-mYh(9qS;>pD+r!Qh2T!s{TV>+oo5;|0{n
zx%Z;2KcbHddG0`0k}s(Ul|yN{42Y{?Q>);f3nBkj19VoiTxVE)N8sFeS0jAJygd0!
zEO=`ml(6ULO%GtV!FvvQ)v&AY9f;}s$y*T&?})U)_8eQW_UbUFgr(=WPFr^wCY=;~
zDa@06^wg~2eZ!p1uU7>|EYY7M2@H_;xn8((!_cCBluQpXHLBIZR-slBzC(75@T0Is
zb&cQ?dLf_0`1~on)OCe=2oi9#F^5qPpsI`e#5cFb3|GLhl)yKiMlI}h3(#a3nL%1w
ziMSVy5sDR(`=CXGc)$8<!6j}`r{eYZ&q{4p`myC4+a#U}-`ks&{J>0IWc>{jp0CZ}
z5$faVLVEqps5EJuccp`cdrq0LC`sPz0TPqg4?hQ1O@$#K#v7k4`M?MUW{OJP95~N_
zX|Z8BHrnvzb$99*d!%QYP4(Yu?;l8S2uM}xliZg8y~Q$1n`fX|8dRqGC}1#O(4nft
zOFH5`Maihw5+1wApPgp+Gy(kR78z=MW@i6fK%oDlsIp|7X0te!2|WCznzmy)!!B#C
zTmb|r713vn5zZ!MA?H1IYGaxsM9uaxsY(c%;L!X5WQxQ;$wo6K;kYYU35(j?a)R|3
z`C=wh-eaG+S=BRScRWg<;T4CPH!9j@NbuZL8uX|gK6vh{WHF5yi^Vgmb@b>xessT7
z3MTN_6juzfaTRaL{fSdiQNe;>Qj}f_4cp;9*I(*U2$s<wfr%S~A<EFXf2wHB+ip(W
z6?qs0Ws{~I3URov=dMa7fPMLR_Lyk)W0_p3o}gt%PdgA)fIxzLvHvs{{5Jn#o~ARM
zmBcu63~bKVFJ)Aw8d-r~$}Tq-GZG~AMiYo!p?f?&g{%~<>fJ0=qB-~zf`{B9Qjkzr
zDO2O)`S3gUvI*8f-e1L(2u4!^^v*fY?B;)&k@hnV5+{L<wZD>|LeW(-lFXQx<ttSm
zsd11OtklIHuo@Ekc?3$e9+@bALEWLlf6dsp~3W13rCgd0O^I$)r-;@5nhMI0R
ze9Px)(EBmPHZpy;$wqa>beo3;ztj8f>GrZ9eG4<ktjBZ5j?T?LSvI{*1<&nI#=Sty
zx)s3)$GI2_uctJKfypSQB+-jS?mRKm0&r?$U&u<H?^Qh{YWt2I23ADM3Y-0ks#AoU
zC8XG<$W;6M_1<bC3meXYN?JTs^lA;Hub)zojxTa#q0uq3nf7o|3FTx3C+Oph9pqAF
zf<*sGoKP=-@W0v>WZ^b1Q2+TwI!oY?$1ehFMM@IMqsI|uWj~=U_9@bs1g9@`d0aDf
zpdSFap$QLY7NKbwMxMclYc~0`7`9kAM}SQVrHS1;RBz1r=q^8$>L$$ud-uzz&sgD6
z4%P6DKLhSx3X@wF`@wjcsn&Y2vzMjCk(BB(_t!M8+R^i8iSy<lDPaf`!2(_HDp3&n
z&C1WC=s<q~OEoZzlvwpE0<UJp>{d0)$@-0k$@)J!#mR8NHv?PoKV#Dzsj6Bdgph;h
z>Jl*l3+Zq1Y)=%5$)Xl$sJke+5^}D4h`KmnRB$5G)(i}o+XL=6e~GzD>t)bX$M7A+
zkpRZ=<GU_mv7?AcJ*-N(#Zp0>(lU205mMm<^0m(Eb9;g?4rS6;hQVFEgkkGIxQb1=
zvyxhg&j9cayq=<3F^Dhlj((co(!s(n2F3-1CDm;u%4%?gUpnXM^D6EHqk80?!Sk#X
z%AzD8_UgFIxKjg@cf@wx+VsH@p>Zv(3uGxc$OpXU`sSCP#7&_V6NCg_0>@-(&}^^2
zXZ1ul;|bBY>$&l_4yq`mQWW4DZG?Ul<x!MV2&C8J?3t^eL!I&7*!hf-oqIAWp5<=V
znZ-xmt>a6CXP=zW^2(b=ymX>gWJ+oenQ)TWx(&wlQP`RoKQRt&7!P?Mhgg!zaj`qD
zR@ob;ygg}v7sJgvHP7rQnHN_2kJdcibBr7?gkx6lnsDhw)^nC@RwxP6=R=i`Z2uVA
z7nwR$kgB&zwIjH}bca90bi9Hb6Zu0z{_F2OlBLwHyk6S8ebN9Y14T_8Y<<T=C+zu{
zp@R$~N7<pES~Mh^ib1&q?3%|v$>9i6s)uV3TM^7AF}=yCLIfq5Oh|A$*;qJS;Y1_+
zn$<e}=WTs^6d#5u4h%pUC#$KNYhKkjs*ypbt&wlO_VsFeHc;bt8p)4=zd&Y<LI)v9
zM$E-vGkU$YPSQXIJ%{(TV9(HvOhU)QRFi7j6ylQc9IY(E$jQ^~#kQOEVB(^=>@rsO
z$!6My&GY(G@8D*lt{&7<dYG+u`qA#6F61r@Xn|K-c8jnqO2(tRzjLaTvz2_HIK7=8
zuxD*|&d_8}hr+wFnD5+^Ug!l>@QAlkoDT+3LHJUImx#tUyH|B48HYJBk?_%~w&Trf
zPBP5-fIi3AK>Esk$2csLyk!V+5y2}p1ePr1pC2fs_adQPCt!E))?AGHWkzWEzHcn5
z09BH5AMxJ19~a{<^RTsy1u~zwL%+WMKmj@D!1qg`fQjLc804=-syJ#1>P#Ynw7H$$
zRlh=b{@~jEX6+!^sQeK;;0^JP=~dqgjaCMXL8Qs!fqmq%ePVA?9XF68TN%BUZj9sb
zaZPY5;1sAYAfguAdjFUknB@8uf;XuHGs&DK7ZQ?oVwBd#d_VL9?`7cr)$Wkx;?BXh
zdsO1-$I?W>fO@CAGkZBf8T1+w1FxO20ZyD#?KsQ0xH})>=B^y>wwNpCy?9JCY=vw8
zm%+}n%FMr=*;MRCGqVi`vu}=Mtc&{b&OHr`t3gtnulUjIjQ(I-*#LTVJ%^Jodyi&<
zmEZJ#v04*#1-uG&tZH;nky#UuMu!5<+g`x6M$5j0Pv9t%xeIh{_6HE$_(yj->w4<d
zoG?mZr?6S`dkv1o$YAc<%ttK-*g1MgI|6ZrabN~smtJLjuNZY3<QoB|L=1FzdwyYS
zFvGPmjW&jWzO31Wm+Vn_w(8{7{M%Qt48kpZyPorK*}m#xr3!5#)v%-OyET*FK5SQ&
z$6w|BPxJoTWEl0&rV`ew1?6AkC)KTY!58UC&>d_&y~i9<baK*Poe}HDI?EW0YchsD
z>~X(#Nz{<E$(pVG)$4YSs#YVyF(OEV#*g&>9ABd=(32xBFRbStWwm^~g$!Qs!i?AO
zxavsnqpNu<@1(Qw{apWyd`~`MsLCCT*10?U9i`<3FP?Ik-GqKBbqGSXjE^wASw0y;
zmhOF8BnkJxra><MOl?7~GgYX=^9(i3vDbE-4*HA#lY>s)0PS3k749AuP9ld4!(@Cf
z{$Q8V0nQeMh8&Ml@h^JltqBUbx?#W?Mpc98b&F;v^qH2u0n__Kyr{6@O<bKmhdDWD
zaXTpg9WveExH`0oISopK4jd);6E`a0=djp&)&yc9LxNO{!Ulb2qSM|Xt{nUDL#0ZU
zq&Lip$Py&DQWL4Z<V&AztjJLnF57!Tz5+OfKc>>sV3AU~%s9cV*Zr@5p2OQmm)hi!
zQ&aE%T$AE5F-0}XM^d|phL<=Yiq{Efxy;de^+cuQkP>S~@rIM$Nh;z+2?#?4T_ura
zrTWM`=;%RrGNsa8atR>dTpbVjL8cf{930zRw3C*W+XJTPv8|2cq9#&=|9CGV>b9-h
z*+Vv0SHzv`_gk`t)78tr>SmjJDg8T_a8i9DaJ;mZ2B)hczBa&6g;Lgv_0u_-Mzv_@
z7^TwbQv6G{8AID;@Xw7VRV`E9c$!Rt2ODgRD^k@%IZLr^Hb`;f9&hZLD9O%kbZ6`I
zH1}bOY+c)!H&`AtEq|sD41?I1RCl#oHN}oi;-WzEp&hA88Jz~Zm>F@`gMVcg##^@p
zr5#8X$U^d6R=>)xPOQSiQFnRD_}!7!Pd*AT*ze3o1|inm$N(g$fU#BVNw%1S49I5|
z-v^`9bKzk-nX&8ZJ&PhLS6Gi!tdP6AhoZTWRCxW&Bqp9X0?9NrBS7KIx!VNmvhNh<
z(71bGnFPFe{~vGk-|)Mju;k3-drv$go{2BrJ*w$(dS^?~@DsUwon+WcPCwN=k-ok}
z-dlQl)Cn=#9ePy+rw4g-5|Rt=pWh^TN(_>XdqQnelW@5$VN2Z7;``Zuew$1xkd&LG
z#^h#+J1*-<lL-}`!YDFqjNHCKvcl~^8Yl%vvi$T-i)q9ufb(Ln$`*<Kx!b1gCkdN4
zU<3mAIRGg{B>w`k!J`!Z?u)dwcY-;$Z>J7c!AjrXZ3Z(g)<jywc9?r)>khAfOxVyY
zNyejTr2-6~u~!B4N$Z*?#^=+n`o?a3sSDJ9F5QXO=~B8&nTEf7pjISGc8(^g^4wQa
zv)=+B>U{lHNf2KN$0LIA?sgpg6gUHq0tlfTDgRJ>N9dWWWUAAfM)bTaxnJtLR<G+M
zvw0?hCP2@njt$D6mC&V{0mARvIES$%NfBWFz3LI~CS1_@FRKj;P!vl8e+X(-!7FzN
zZ;a7|b2f3iwowr4&^vc61HW?2B$#!bhAvYLY6nvfTu;)-h`;Y~kQ#LF;PtW+`VfZE
zl%qG$StZ*WoIbf;&W7z4SAQPJK0zjIV}~y%r>QgE54V~vUux)nh*}DP4G-JSrgsQh
zSsG*`8yQjD`<ybm9{ZAsQ7FWfV-S#V1pcOsin4$Y`j|~+&v)ubf8zC8BNy1(nnh?m
zD5E(DN2dGzIb}mrPM2JMG(~4NQW<IW9Kq52TlYziL+9>;W4(gj>*`5^=R`sZ^V<Bh
z+uOI*_*RbDR>aQ-yKn+}S?!Cz=Z5h?5wUEOXukKRbd>>R)CbaK;>bc|TKd2h1E*FV
z+XTV&KP^Gzmrsz_`QG3AtBuz5>m<bt-oueL4V&%tq+7xLppRJgkw#CaMrP@W&hD4D
zp}0Y#GZl=##=$IVGjwMPaFF2;#|muwXBwlQaHnS?CZ)zbgJrh~316e&@s8iI!=N~r
zvC#rOMN$6*2%VVuy3lBDoI-e5=7hi;?IKw?s5wd^Do;NCxLrTAvZLgQnXH3J4XlpC
zl8)iC>KW>1QB}3FrEslb9L69sf14t{4a`cLscFXFx=1oF7zX`y7wK-<3kTDnMc4wF
zi^?o`e_|{!5lk=<dU46<PDH%$ekv_5*u^8{(7PoeSz?c}KD|8RpcuB&9}8}NV!?R`
z>Q4U7fb}Dft5{Ran}yDlg(h>N!R*0u2a(lSONV$PyNRqLk3Qj&cpJ5KZv#E)zaIKg
zQ)fNCCT(q{1+$3<P8A(R`-AeVU*r4tGf}E1r;Q|K{zrwDuNfL9Uy*}D2b125*DfO~
zO_(!Q)JoF-JXpYcn$}azs!-)k_wCZUh3DTdhPO?e{A;R8?@`K4T=8zO-r$qi@3^6r
z#F32ZT^XQ))U}}fhRY3TdGssLA=R+MaU?pB(^BNP)?}Y3_i$$9oywQDx@*nPDw(U)
zM{5n+R0wR(EAEm`u<I>P9wy7i$~oWDHS*e`pe*D3O~jbPY0ZW!!)VT@MyoHb{#8#6
zW8h<DW2k0W<4|XbT#qtKRoO<Y$62|Yz-VjC6`M5CWtbjOxllCC@3N=qq!|XS<u*e<
zT!ro6Q<-am1MB>09|CAO<BSORdv{lB)Ev$YwCi{3wa48?7XKuw`&w*1%B0&qSu7eE
zGa?^u0F4Zx_QHfGnGLxR`~*N#@B3vA^i#P!aK>0fU^6{<tZJC22Sj%SLUN`sr*wP`
z_x_7JHCHV%R8{BbNy~%oDVKZ}nj96D6CyvCzsx5P+NydbFl#PNSVZ!k&?+VgZp}h%
zm^<C>@lO&Z)HZ$L8o1eTqkVg<<idwk=jX;BO7^LIIB6DVqV8bgeuxj(6SoLi&LXn#
z7%HXpE!SX?MP(si)4kv@2y7jlw3i(br5<3GM7cpR!eBDZ093BZPb0;9G-F@NWO8Z7
zVt^aQn`V<Gnf<D%8EUy06M^S4powv3oXZy8wKU@<y~iQ1O5v&`2NIoTm~$*V9(rwr
z#|lv=qxf2tXlhbak3Pl)j0DwjMDgI6gSd`>DyAq!-T9ma!rReRXBIT*n_J6_e&c9c
zm4%B)X5FYF+&<4$Wi~U%0Z1M2q!Mb)wNqulmDx3VX;)o;K6j3I?2BlB`UL!aJ|^g$
z?4Cu=76dCUb;*2nGKoUdAnxQe_7K3XVLNWT9IackG(pLxSMX+-_^O=%I^axG<r`<#
zGxrAuPU88R9>8dP;m?x%ZI2;haN=MtpcM`SS8nV@@cSjX{lyf&H0)()N%s7H<nig-
zwmerO+kz^)XTAzcd)THvd<`{AUfQ^o;U9*t*Qrl=YCwfU2{G|C_@`>A??b6XiIX+~
z2`;gj#7;LUib?+#Ml&t1oJ{*tA*{P5@gD|N)oa^ay-eEiz*m?W=^+^|lx>41`umY3
zh;q?A@P(>-C8G-JU6D?{)3C*;h8g0@*t7#ZBJYUV{8jnGQuYOfnehaP`q1>QI&LLQ
zFk^(wQKCmNb&f%1%)-4f(vEOV0q<H-Il{tGp@|wzqUrDCc)UWm2(f#Jk9KaYSkTZB
zw+HlgR;!J7zdgJ1!4$Y^`0u;HSN+q9!Ahcpltt=PHn+gyF>$fb*!0)kTo&}N*qlyX
zkW1h=Xv0pE{t@}Wkvp7W_xH>%$M#HiEeg#N$b^c-w>d@9EExfwzGTdpC#ZTZk7DSZ
zO!bO|z$h{kdbOWRBy!1Ra@PGYY&f6B$Sl~f=Q?sVY2l&LmAQOHI220=T?1E4QT#I7
z2{yQ1p?o<$!I24^f@(L=<j~j@C&+n%U`fa<h)hi(Y`cEgwFc_CVLeoX!H1W{e=fa&
zm?4&qA$3fq9s^Np@LMbGX{lbx9Wztqn@Aj_C!4m@?7UCnG9a}*_6)_S4Vw`WI+ju2
z5=d~C?Z0CiT*e5LZt;Q6ihg_jL-1qgnw-Cq^QIvH_(vtjCdMaXk2zHcJ-Bl1VT7%T
zrca^~@x^k?AqS6*VbOm)neokLW)O}KO{}D<vo;!!Dn}!2M6{;oAuUOkCf4&U)5Iwf
zHGg7NRj9j2>s^)jupDD%q?bo{iXatfk}1(-P+R&;oec7@H+x1nl{+z4*;dS7a&UIC
z$LM5ib$Rtw;B1#xu&QeRs?3QP-rkGV=NlJdnVpiXmeLstP2*4Pg-)9=LMu$b#A@Rd
zB5V4>#Tl+*3ho)2FSVsPz^a%S{qdZd%h#r^BkTHxU?N$ORJ*^sLThN4mjQPwM{rr%
zE}M2v5~Vw%6<un7_IQ8KosQedtQ@@+XA?hegPOx&n9y-?aiB5rl$n(DqMe|O#U_?N
z^psC7_WJ0N_R>Wc^Do-!<7iFVm>M)9`I|XFLdtEZ5Uz@6UtxN)%g<@;eC<`r%|Uga
z<53o>K~+#bItb&)P)}U!G@9(QlIjM#0S*+0$`fnky|XEebYrE}Dq)Xz6ht*{+{!1A
zV&_Be0Z&A+rzL>v4dPTn>@l`<Z1msZc)^0te`h`m;aJrZw)BOgtkPWS7c2qsR
z?3e+SZFpYKS3b3qbcyzwma~2JyZ6l}9h-YK);2BH#Eyz>`mY(O;Aoq=T=wV5cI2#U
z6tS*9QWuP<5J1<xA4lCfX?Y{{h**vZB`T4~)neF)|9sBrYIR~$#E*-YGsZW?yhet^
zG~*wp6*sIE<;WYN3bSEaYcKBiOIG_X(D&$kXJl<gWZN4~b=KvnufJj^U$e2@8EL+u
zK*gyP*TXG~jwj@<ARYGTyI|-NeIq+{EuUU6EBAgELr3-Xo5wpUriigcLw$tq5s;Kq
z9pO{x=rH*T{%709wsSGjGS2c*^z}hLRF*qPO=FF8R>fZyJGEH41%>!3so4zl2uL=J
z#t3^XnsV|OA5qoY&UK}s8{Ur!+K@h8IyPU;R(ClXuSkjNrYJ(!0TEPLfa=+nqxcj5
z?o}Jsf=VV)%VA3&2&6q$FBz2yR()L4xK5e95U9H*MxCry3bZC5!If!SOb<4_15~o}
z^6=22!9tsJrJra1g*~DnaeXj-7LN!LK9F+VNW`cz!XQ_#4CsYEFy1q!mcC9F2jPD*
z_obWOGw!YDQ_Ki7h<w|-3|+vjP%ALm^3HBnTc9_hHW&s<FO6~Szi=O!_i3Fwgvd4#
zJTlmu8^TFb^<#_Qqo&cNC;dJhN1@Q=50J(DhRjH=d;?hbqbU~C<XocCERGL4;Kfhq
zC}C)vDbd_agjb?#B%$B?;j8-GLg`Y>>_)_wZLSa6p?RdSj|=oo1m4eznUA2X*IQEX
zOwwZiO_@{)EbHc^h?owW{?kL3_T@1!S)A%Dy;0II^Hysj;Z3)<;Mj=GakVo`5d4~D
z)Z-|=DW$78ZdLPhc-d!P+_$Na8<70#Z@|Yxwi$j;U8OJX!>1zRndN~oj1ifn6SLNQ
zNnN<KZ01J-%n-{l-B-UcmA1$G+Jv1po@e|loASF#DanGxBnn)Sp<J;;$oQqr$?(=h
zQ`(=yiN<c`oD$Yt7I$)R3gs$SiSv8;S+lcshGtJJ#uPsD^06we8XB~0x7SUiGU5qU
zG`Y-{S`9MPaA#dBThW5Vh!2*Q>Ry<B@@CqgM#dUqwHo9^kHFu$Nde~l4$Dfir&23v
zz3WQEIH6j7?VfVAn6C!YKFW@GaT?=DEQiK!scR?+mO4@O_5Q)i$A#jGj0WjOXhzb+
zHE;05tU%>v5z2y%d}r7qCoxMD$!=5Bv-h{NWCZ8h+rCu%>vY}$snwIhVe1Z-2{Nmf
z<3Nm+CsVPM?bcQoucAo8zg2e!Llb}RGXmQqFW-cnd>dEK<PbY1G))J7bwnbJuu$J*
zlrgzC*79cybo7)uyQl?>>%@zdE`zJ^z_MGQU>GJV+4QJhjFa2l!@wJWBRf0QwXJIp
z$G-z5E(L<XTS(=mm~0wa`J>k+5bY60GzJ7w9G!#pC*dsm?OwGabBKyG$IR7>2B}8=
zp^=isdSf<FNUZEi>)%I_P4xty&}m}hX*9-GLdB&irItK@FG<`F$Il*co1_HT=cb;-
zhw-KU!~ZNOGBl9=cXu2H0REh?HxzsAlx@;_va2fP{)VYo+36y=L*?;vC<Iv>-rOqK
zuJz-#EazgFw90sf>K3u$vL<a1w%Jb{bl_TXT<aWacTMpW&>(1zvbtuzVn&iAopzGR
zKUf+Q2YHi?PzDnl`Z*-5<)8_r9&jQJlQ@`Va8Kueh<V<OAq8;p`EdEha~cw|HL_Wq
z;!=j3w^-_wSgP$$w=wVO<Y=L2dJoyv!A)P?$UCWDt2Z@wACEVTFPb!eh*sS<+nph>
zn#QGVg|f$}lA%SgcK_YAE=Lm=0ZmPJ3O)*6d{i8V0;z*RV2+l!UJ|WPRP!;-`G_K1
zT-<i4u>~^i`h2?zC30%bhS-rdIOR3e3E3^aKPc59DDGzCliQ+Pg=>?G6}TF?D9U26
znmrEAn`QMGt|6S#Qu&uY9%3uS(F)$p6I;9m6;p2C|1<aDYr)>A@Um2D{0k|&q_!<s
zD}SQ**fwUx>qs&qBO#)&`%>FSw@AW+Wof2m)aErIEZt?fS}eJIK38$fFdQVX0WVV9
zQcaxQl(>Gn_6Sw{5r`(iw0erzro48#X`81&YsliAv{qs)_TE`>eBwY7E=nKg-^|}7
zB;Q8vD^rValG}B9m6u_s+md2`)*C$(q2-wpSK+emvLv*|xPX<=$f>p5w}ZqwdC9Hb
z=yej^b;}cAAhN<*t=Al6FVn!|>$_3jyzMTc)g*&^NFv3&0J6hE`4ZRkj?#(s&M6B&
zIfR`VupFNUZ?D3TO_%t<))J4gzje|cUq{CdkndyMQp5bQ0xAly<}5^<<DRRf;NeQ6
z*47065clCH%{Z}^tXAwZs3RA!@_uT1IB%$*KQTk{Qd0fU=&UTYjiWXJ*BPz?CD1y6
zRePT)9a!z~(zMKxg?5)JgfmB0Pu_uloWn&L%dnj2jWy_0#%2vZnSg{esg>iJa8U~R
zgiq%yhxOvNeCmm^XjPi-t1}4$J7@cBUNwk<rgUUgo*n$a)-(c-k=fYVIyw&zIEmY`
zSM}z(t`OXysUt!LMMaO<T!zfzBhJNR_z~*w>@|2hrq(H93gCX^{=K0>^{482PQIK)
zU;Iu{KS>We{sJ3ZOwDY+qdFDr5A<44w-+ACiifKDdYa1Wqeze;KW>d75d<1^URa?g
zm=Pw{u$n5i12Tkys>LQk^XKBfWb!#q*8aIL3-300kb}W&WSqY>QLs${LRFh-Z4pqW
z)|OP1B;N8G`S=Uy7;L5FgejaU(gN`!=JD}_jeIYkvOMEon*LLIe1WWw$8hT=n7xhv
zs>kOu|4tPeAPe>gJe4nEw5l=Jtu5I4$3HcAb3rZ1eIlCpwf|GF+D?cALC52$J|hL4
zueH0PqWqJVIi9Y=M1!~nx#IBm#IBuB?9D)(&%#^A0S5}s&RXk7<>MdZ@_)BWHt-wk
z2hdI$88MZRO~`3ltWmO}hyW$a*vg4)DY)!P@Dhr~W2^fcng_z;gECf~DU7KPO@BJ!
z6>x8puhIGZMQR|U=KdI8Q!@=`Q1x(G@w}~Bz4(otg3|}K2cD_)MjWO~fyO)TtidrV
znHbV(#8#FZ$<Lv<&1rX@vw$SoY3<z)1qadK-vcj!L4o_NJyU~j11aK|<q}G~&=WYO
zNj<zCEZKYz(=wX#^KnKpcop`^#%3w)K!BQst82J&9^X{ze6vL{Kf?q)IvjSIX6d|!
zix{f+=Jkp1UIaG~AhCEtXHT6p9XJCoFTucl8dk(yv~3g($(aYHk~<*{qOd*!HACod
zvs$Tcs|uIoZ3efU_}|(e=CWdajlbBH|5J~Z7>1YJimb1?C0lxehjhvKC9k>MNVF|N
zpZ@bc)5LhSG(uuS2@;=>eRO}NAE==WPup|&E+^hD>#m8L6SBDp92gzrMQNtiCg)ls
zr!SiS9iOGV4^BYlC1iLiZQR|L1N2CsX^4!Z?<LXUWb7l+GIfCTyF$)nijX7TmO7F=
zm<Hk%8Y%pU6uOvw6?uHzE9cax$qaIqAw(l#Fz>rbuQgBQa#uhP>EX&YINl>($j{~~
zD#W6-`#ZDuuTShYy1Cq4E@PIarDZHb(a5rbj*Ftmf=72H3Ntd&s(nnN?vy*(_OD5O
z4U>4?&oTADqI?<3wLM2FR^v}<+Jp&fs1NEibHk*_q;Qk%&0O2NU%&0^Ed&a9DY=y3
zmeCO(hhUT|wZ=@OYLDc#iQdmeR2>u7p?xk@omYq(Be>jm--aS+mQ~PvfXL8~{JzV-
z9pr{&Lj#;rNO5rL9yT5@Zm?3oI}9CJJLr7dWNJ%ZN$xZlHfBSL*=`%g#N>@kIOVXZ
za`0<xXe{rC*ba&Z-AgK}<<im72QX^w?)+WK3taWQWYXJd<PbtBM<d*S?wPwT7GY56
zO1g;emM%(gc@B%j+uenUj`T5)+q2-q)Ttxvi^?fdt5B23Ii^`j+4@x}O2%#5Y@GZ{
zBP2P<)6T|4E=gpkCck{2jWNq>Ck`E0pdzO@q)iA7lhk0{TrVZZZ*CuBu}#d_4@`8$
zC#=wwa+TWYvBs&t&gnLiH2{}$rrm~g{*Fl2o$p6a7T#G4oQ{%gZznMb6%n_X$3jx8
zCSTa<ql+LV%V$z;3!t2z{aZYA`+AsP#k5~``0sMq-9Za?h~jOSbFDNBad5%dn;hKt
zA3YH*K1Wv}TG{gs@riz5$&B@PR3PtAW75gA7h??>&98{(A<ZxsqU&dO1p~jH&N|A!
zVY&+yNB9G+APSvLf(VI&qoX(8ejF=h`1k}2A0O@2koXU<el@j)I%svrM0+w)m*USx
z6*)Z}r>rv)fv-Ku3JaSPH)u^hDJE&moj<q<6N0*D{S9ZEqZIO0rzgKD)E>mZ)0Xk+
zo8vKjjti74Tjt_;eLSvk%F;U_%aZvMv^(@xdFxzr^5Wq>Sz4xt1xkRJuR>pTf@;XW
zf2Z+`{-^8Q8wmB+DREGaWro$RBXU-!M7@G>KyTMDkr2T;A_sk^mB|k(&)H2`0xtx1
zBOrcwf_5BCqhK<oW1V@U8m##eogC}ph2tn5Q<E)gqtGTlld}!SZ{u)ss=iG9VTqIS
z4qY=vT`OQYJXCH=U^Ly_byIp-bRk8-p`zyB$J*C0m_f}i=u5Wt2USO-=1K7hDYF{M
z0lQUe`IC_|FWJbO^rv)IU5=)i9!sHY;WAd!wMqgyD&f3!wX_8vOH@JHdNNzXYXd#e
z-=z?A!&I-T$1=Y~2a`QD^XcT9YNIhX??!Sa>J+1o1g`s^=&djNbqMhm41$nIvouFa
zo!h&Wo*Ks8qgh&>e$fS4I{d4f$6WHRG(8c(a+*GrXQS0^to1bB6HZ;b3l$ypK!v6M
z&)COTZ4mi#)|b8p{MVhCJa2pbQ=4W;#ZdVIpYNO~6a}B3!FeOpFX8dx2be$lvloaT
znQn&73c{|>f2EbYygebX-&$t{e0_sEH;#}Y6RnvCw+qy2=B?mUwAm<E^AfBI@^+eS
z&JdFAJk9Szt~2qMTS=nzTRBh1KpLJ$mzl0u&F0SG5@u}gQa(5h=^sV>He#KgJ!^Rw
zPYhHSVaD}7aj^~|6-HWW3MDG;kL-k`ramqa)K(lbbT`AE5!y-QP|yRD_CxXhW)@B(
zP+J~KlD7K|FSN?FlZpZhsmjdU91Q)ijRYk+Itu1Dp|ALyv42ih)n*ZD;W3dhSIrPv
zB0^%7!g0sg<4Gn$OjFpgRHo{kvT^UyhC7p&4K`5{Jl6|zj4it~#d&z2h6ixkTbEzb
z^eH^-Xx+DeS&FHlM-}JD-pRUfH=ED%a75;vE^1k^ZTNc24V71uAg(o|j*H!Gy8G$8
zW*SD+6c-c6uG>slT1J{p$Y>x*G%I?}`)b*LX8E+$N6G}R@6N7$aw~=qi|Ea2u&?Os
zD!5$Ys@K1c9?4qTc}(xCJWF@#?j-KCb=Eq&nEj`8nCwyXLtRy3fL$&CZ=`snuR^FS
z3(S<M#d_Lsk~v?@M$|}-kTmq5+ZOjljrQ|dmFb2PoRJTDLC#jZleELhX>4Ti<)mr@
z40gxP>uFvW{!Rr_tXRr5cqjWJQ8kea=du}%+%^Rw6^hWSq`am7$@ak0c*V&Ba@|0|
z7*e>fRDDbw$Aw>uXF6LsX2i?RqGg0Uu+?vLeGYnBRUA93O`c{ebLl#{@?f_s$eW84
zR&_SERpm!I!rGbT$aTdma*!S6c%A<*zRoc^lc?GElVp-iJh3^kZQD+s*tU&{?c|AV
z+qP}nwv#*WxnJ(O>zuRJf3L3np=)=q{iSzx{i>ehWIg5vz+4Kd;xqVQGw6h+6f37g
zT-xJsd>%*oaW=A(i;qoJ#xUmEjr}W3Eb~n=l0T$RNtn9j1>k*tKa!<Ws$f~mep?`A
zZr6k)++(NIb~zX*jRX!PAs{1#;E)n$@Bfw-FXGH*=)Ef?L!@XEe0MIP<gh3~;iOK`
zPeq~n4Yb!we8dfvSd40*VV7Q+z(>|HTg?v7jK3|`?-d>#^29%>0Clpz%RIxO;b=2G
z<|3>Uvi0!ohHbv@l*~F)VLVacAho@B>-I<V^D^<rTcO$~QT|k6%u<h8@K%pWOsmJ8
z!U<?NY^tI=jYIZ#d#X@RGQCy@{bb;Mf*%H<8PVk1*L58=V!glqvLe0ylJ?3Uz)2|4
z;1+#j!M2j&a!dJgPG*{jZ94ZFYYu4{yX;4|!dy}2G<^SO;I62pVJxCLsU-W4Egesn
zQl=|e4P9HYI~Yq{iu51bx;=yg(;|ZDO10Uz5_uf8k@a+3hB+NHnCxLfa-vR)S+ob|
z7R)ELi@7RSE3#gzvz9*MiRR=iWqZGrGM55#EfjK0L<=3Y;H6hTs`PRi^Qk7Tf8sA2
zEu*H~jhat(^?d|u;o_~{y<D}7AvzGF6>$E1_K+l3HJ%)qvfAcpDYRO=@IqZh_G+wZ
z&2a?h8{6)SxeN3!b!3HCkIkqb6;N={5k9sAPX6L#cP3x_`t2(|w4pfG+?mKnoNt3Z
z!TrdQUac<NMr=N{ffcLi-Zt9t@kKdPZuc7H-Szf%q=oU3`BVz=J%CJ6w)?LAimaJO
zS(Bd}8S~sNk=3Hk#O1yhyv#nK|Aq3>DiO60h>ODKU@R|yH&+{@RHNXSCHk`+(5ua0
zPQ9`RIL(;k)G>|?k~O<Aa8NulQ(PABW`2c&<Pt89rzLbuL8dC$lTP3fN=|^JJo>q~
zS4v6KNO>WfFWtjnRnBGvj9(3CW^{chOh_7U^T+BAN0lgWz<ni>y<g#)2$^{@d3YLd
z6%yRvhAWNfT^SCtJE=s%04=b!lr#_y0J2MA0KeBl%8&r@a^-3-bUqy-T~D*12`=C^
zLLL=I5BNnMD6blDp9jN&Ux#IbFaZ{I3UzjK$HE3v->V_sQPq+3_`u4Js&YLa?!072
zgH~a*NN4o+2+-6n%*)J6CNJ=as+0sKCSW<LBQ;fg1j$$3QfPZm=@Ve`B18Rf_^C+-
z7bK~-WPH5Q-H9k+vx3<)^-`dCF%vr-fU7wV{4+gMs>~VEyElb$8p&C>ns7Q|uc6&q
zt26eeH}hWvD(YluSb+jr@Y4)LDaK;PqsV3?y|Pmeoi7BCs%&ZbX4ycQ)Krvh+5NLo
zm!G%HI!c|54M?lDiQ&ez@b+}^`y&(8d%U~tumS;l-L-V2)l%t$k}*B`rrzC$gP!vi
zA|rT&>YMaU;beN3-d#I5E6OX=Z22GpyH5$<+eo&c<f;KjoNLD;ytHFSR+L<|Rmf<!
zV6>i6h%C00n5xn5U(|_P)3#1htv0eImnIXg*wjGbnS&(NCTUcy;Vc?;+~xvCjwQ9Z
z%^CXe#fjIMxsF$^`W~I@UUD*MRq4id=(JV0neqzRF4g&KrL|t@^q7H+^nm~*xb`{a
zyv4f&$2;I@E`$Y3M1=J&mZwo5fQYUz;eI49h0I2&fCwe9JJ^kv;|U9Sb_*o!6~h)q
zSPUi_Z3bLQUfo?cAJ&4zUa5LL!{2+txeiv&fy4xkXSnTcfCa_jBq>vb*9&Qgxx
z&0LkwO#>>!ztW6D!%5FYMyB_Ue4C52;tN!HCzww}ZusscPo%G;JAk=@Oa~N>3&VEW
zx_;=<Xjo?@QEQRtT*F8NhTNICHO-mYT_@;5OGYO|5?;Sp?SSW#VHc%!1xfe)wf<8E
z#9>XC8Zn%E)x#1f5$EC-q{}8(A@gUZv~-l0!QLQ7S4B}=*1n6*8|s$%fb@Hsc_z6W
z-HG1Ei!UXYXlOV)`S^57gkRKB{!y<*RAvc1z{OKu1YV{_q&KaFQ~YOn9(fkj!`8KB
z@(oq<;;`sQa>ogXQVvZwNy)M|?%pTIFiTfeGi?<A9PBj()Pb|F{r7^=$b4oRtn%2v
z2EG6)UEosu;zF;U7(yI#XP&Bl5T7ziMgZp?%dJ~So|wcMuNulUf%nLAm!83GB6^)6
z_($ETLY)DR&qGG>U_qner-Z3qabABibs+QrV<nlg0b#^cnAF_J0JN}$tC@x1ZUmVJ
zd3S$oS7;{>TViP<nR$|^V7XMaBDtK%fSi(U(c1$GmYfsU!`}G}YJe2mBH|lu8!>-i
znTuoPn)EO08{M<(3Yxp~$FICKSrCoZlMR@uPCXKiNbCfiRVN8Ar4Cv>9pPWyj9bFL
zw&&rk%sAy&r?P7cc`~ZB0c71&LLQvB2Xnxx1jSe5V!L9r1tv7z<<aDf6PLOrX|&u&
zv@(eJW48pwF4ia*#Y$JoDoG|U-7zIEWCgA+H+~ZR?h9f&5A@N+7}q$a3l3!I?3MK#
zPLUUkYNg;3S;T{4r|_GQnQ_(pdPrOqrdOK0Mey>Za&%g)N+TLvVQP!}QQ6s?={XVB
z@Wk=;eQTB54>xmjJJPz}NAG($r#5W`&O%(+-3r1naW@}Fn7Bu-;a!~VQ~bKSp7ShE
zFR}xr?tKFe8^~)Hfi!={O#gk$UwmYwofWIPo??sfzgiz`!abQQ|5YV97Owl@ZQl<f
zEpL9G2FB=D%JDiV>9Aux$A$JVPD$^6a2!3xB+j$=jzQ)Hn$u#mHyL?661WCF-veAX
zp=+tx987>C75S)bAR#GbW865kq@=3W=#3O39*Ft?g`H1r`YOifnz{;6J<f|h;MTZw
zfMrTXIMotNHce5-NXSj0DqkgGVjGW7;JD*#U42;_5Cfq`$c`o8IQ<>v%gtyFo#BzY
zF;(-<K(&K}55?@)wwK4*{qM)EIC&o<#$7#(mBW>K?u}_hAJ)@*p9zI$Gk@tURrgD!
zDB1B(hs-oMBhDnjI!&rrvxEHOROyLFhbZA536&Yz=@t9lh?yz~C(AjXhBZdP*4DEO
z{UTb@`ckPRi)b1;005q;H-%`Z%rY&1@+?#umF{28s}G+Zt)8?5?bu>P@3NIyLPKF!
z01hlf!ZrrIoR=EGV-m=l3cr-JNO%U3BTHe7eB#?1|JkCa0|x`Dc)s#l;f_e|i!ErQ
zrKpcjlGx<t7`-QZQZr?@9z@_)!Y_VmFLiKL%=Q@lu3^dv{cJj;xY_{fd!b-mgI}8e
zFo4u~UIB?A+PKIsbN?#VWNFDMB`GNNLkB@sL8Bz62OM?A0SV=TX?6jRDsak>Sz5`%
zKO>VD0-^`T4hHeDh+nY+r1&PlftMJqdJlCBcW%a0dPjmHVFq=Vda<Hf7E4kf(R@Kf
z>|%*eR0nbYJlo@{^!UQ7xbGYpdesUsk5q%XE~EH+bT2JK6Hx3<5{L4t>z%!@lAf%2
zCX^(*i=_9c?qh?fUD58jS-q8mE>_d1r*0WW;Nf3hJK-P`lAHu8l4{O^<xT&~6l{Xx
z2sG;4z&N`YH6*sG`IvMCVZ$t$jef{qR-J~(xg!Fgc;bi^rin#Jhe_!w`-D|wsexpD
z{wnbztCVJIY6(lD4lkjW7yci7Su(g}xl}ZbD}z!9irKeMkPABL_cM@G{WB(!3FBjN
zlSWgK$VjsYK{9b1C5-XDUeI#I2hjIG`E*Sr>iSS*F&U4zwUS<eT!~RM4=+vzDmF|}
zd_7<ai$U#{sXvf~VBjOl8x(wY>maRF`LN$23EDDH4;-KKWF(O94mD5=l7v^rLa}gn
z5=BXi<xAasT~B&O5`eD{jhFFY{`04mZo_Xi9-RjOMVM}$ZbQwpG;ht1`}*#<T!V+$
z!68XyhmAP)GL~O@)cRitp0=R)D$cBt+m6>8tIrc%Tk4EVqtc`a-ekyv;-G$kHTnF4
zNCfdw#QgHVQ7T1hMb1^dD_v?UxynTgSvrVT&@?nZD=M1`ZP%BVEFv0dtNSLtIgYnd
zrPZjLuHQequD?kTxE-%rkF)MCOk0n)&K0ngk>XGcjtLhC=P3uyGdR#v`N+y#*Kj#C
zP^fxsy%8;Ohd=|?cW1J=$XIsCf+SD>I3b+p-RXUC?*AQ7<A}~;7v9ap+dsK=0|xJ3
z4Dr0aI=pY@Mj5+~iKQZzsk&tn`E=sP1=uAZ-Zsb3-k$l5ItNU!A<Xdj*=0@FcaU;+
z&mmiEZfFoSA2{TuaW`w(&Mn!7vQ?Hl`gRX!?x+TJX!#}aR;p64fY^?}I==g_x{J2Y
zS|^@IwW(FDo-wLRt&Km6JF9liAKLwJrTW``JRnKQpQJDdd2qGjXojy-BQ`zYtPIqw
ziss(kG`j@Epj;Y?1%;9LW}j@L$ej+W4WM^!lOfvhVZ1IHzj4TYj8OvYsSWOiZ_+;x
zi~jbfTE`#J(w1o|=zqpdWL(;zylRusdNzsldd)D;;VGne0g-;)DFy}3h94RPgCx3*
zABQ#Crd(3OX|~>M`gF52V^FtceBoIe;wnc{a_HsO4bLjsH*UN%X79L$`$*Ntx&M0e
zhw=ijBYCJXN?t+Bxu=u6D_Lk@V!~J$===$!SR1NQysit^w4JuZE}I^MGf7AJkcuy$
ztm;wc&2L)+V9Ade5e+1sRB{H*+D|91u};JA11c3xCOjJZ^AOh`?$_3i(s(GDLaudH
z{b{d|sR+gr<%1xNmXIo7!pDR{_B1lvw<!$;V^Uesc&jFAY9m!_b`cZDJ@HUr&v|XT
z2CZWcoK>ea)b;NNxGeH%R$rVmrv6GiT~{eK^B5_NObCQ@ZiszHC;OP|ROkulvYZfK
z+!Evm0)mJchVg3-fos~vtuD6ggX5DsEUU_iW$XAs3>RHOE}2t!7-BJllZo1uz%ZLl
z^psySet$`hsWwDc0W|pu)r2I`32DkOwvW<$BIb;;3bO}Hi4T)5o_p<By6&>F+HsJA
z?HhRHnVHW!V6E1F9FMG0266Sn!!HTb(@c0B+A|Q7MT-*Cy?u(Y9$eM|>8y=GLQ$Eh
zM|W7AT+0wm2RXXJ!-K44iDP^P%SsmW>}&YThY%fewgV6y2&s5uxK5EJkfTNy+CKM7
zt$l_G>8<k-ltmGj+|-#He*&ZDD*{nHA2{npy@E9IRVx!y>oTXT>aB{f;Lj@tVa6(g
zSX)y}$Y51bsgln!kGudj(PXu<c|GSe&`@t>WMs>zG}>xciQ<QxTt3Y;;Ga=j18XG~
zWkLT=Eagh_Ff%mDp>z42zwfbUl1o9$ATFcENp?ZQ3J4~Qru*^N3ojz<oc8NPTmi7b
zXdC8MZ8FG7^o8$<$dVeR2Yby)Hd<}T>lsTJut8g&kL{?9eV#I}=3&5!n)v0HkA7|H
zLUbzwzwdY$w%X9aKEzIm$`aKPuUo3|$ySTf4fFQWg2n-~v~F{s@n8sAIx|<3_KK>D
zQ~;18LRt*vj88;RG+6)-3TqRhm1{@Sa2^%i!_nGd7Qx%5P#f8rvO%&?F;g%<UwtiJ
z>2f+%dyg4Hl6&=$)!46J(~xyR_&z=2(xCPoPgmU7$-)cdAK7rini@NDGNUo+(1{s?
zt~x_EhajjNrSSSL<Z&?sF9}kVpNrELtKP}iF}rSyr!V$`Taj?<GzK#On%x=Y@AKPh
z@$?4_RFE}^&B=6T^j`^HOxgSLwFv2l>$#;kU7fRMQao8)QwYWCWj;fD@TYavniu*3
zf{qY>F3|msZqQSdwdaP7Pe8d#Xza(iE8S~Tecc2c5^ZW6oBprU8_UGfJm=evkF~ZA
zi88YQWq3pOFs(N$3E7eocCy6yZEJ#VgEDC9rXM`v+nLac%nG~@)DHs=4`STE20f93
zaX#A;iNOW#uH`3B(o!PCYpon&{E5en@@x}&6DQ#GGd|y5^Ey&hQa)r&M~DC>+V3<;
z)FPdV;T2(gTEbZ(e55h9{g|!u_JF;L$%*?woF3%vbFjW#t#!E*(N}a-5{C@A;erLy
zbxDbHkkCd%O51K-Hgju>vD_{6jT1IUAqvBJWCT=JRIlJl{m;T?$Qgv4W)?2cj>1*~
zdJcN^t`9HWit+{z{ap9(q$Iy2Z?;O^e5|iALj_+MPw*80_ydgC-zDl3%nmVfFc0W!
zh`+oVq|LlJt0(WId}A#OQv4)JHv9cE)OBX(A3>T&?~ZHL>ML#TJ~t#mf6g3_+nJ#~
z7XT{5Ui6*?JXjW(7Fj$U1V|Q`R<|l56-Rc?1oBCiHoa)wpx*p^kSM!|@~a@O($U~%
z#D56Dj1!0NHi^&>{4a#oWKshN?gt?SlonEeyFmdtYl|#P8$TjP!AYd*H;z*1y4y*8
zL|UU@{Vxi208rvs2>xkeXu?LE=~u8_Nde6+bG8yau>5tiYG3|cqTCR7M;nLJLxuz=
z-hRdJKeHs^*-?!@#EI~6BTbDd#{6aD*4Pr?Q;ZF7_s<kukoi(dNT>@Tk<mTdh2N^0
zN69&Snf>zPa7E#FMM!QB4_U7#qA`!eiH{O7Hh^Aqd|5S=Mrc0Vxl#;wS=;GY3L}xc
zno!eA&qdK>Zr86Ym_d;69@dEvoTV*uq<mN#CyN-`LPLn*+3fzi8C*rxDQ!FMxyJW&
z4`SU#>aD^=fKz44h{-~!)4pW<`!xSmoz6A$SbFh?j!CfY3h^@6bfoQci!~KHKWXB)
zGme}(tcrASO3Tt<(-LT>cYWGEk;EnYhY>=_)b~QryGQMW#?l<8>PG*`E%NPhrc2{d
zg2WCF$QTj2yQ!&2&!|Fr-QU_RK^WaY5#jpW;ArUUNYG}alB96sstv|$I;0Al66n|c
zajDHiL^5#zwejGSd>qrxXr+1CsD9O`ZKOJ?MbzBsSY3&Fl&rOVinXYtthTw4NtXIQ
zq7&zex?Zwiff5%YV$uwHF|KwN(J90GFJ%D{Bt<q?C`;bt9Qj5-Z%9RWNF79fjJTUF
zuSga%yUW!|HDmBH$uXQCW3a>rJN9wzzGBiK_K3zZBA|TXOasTmE~HKYE~K9|W^u9(
z=~tj^F@PkYCR5w=_Lmuol{hgdbNH}Was8*Hsv!xhQ=m^QOHU}XZTG}*dm!?#M5f%(
z0c>hW3)pF{^P7k`I;NT_^+jq?#rZ6Phas9QT~rlKxeXoj_yn=dxPwEbG3|{RV~uQ7
z0hIy6cVrN%8853Fg#4bV@u3f$Mj9un+~1kuQyzZ%SW5Ps=a%7FKOuFz(qTv?d5l_j
zZp!soi$JWsKU_M-BWff4F-68zQsAIU%Xud_1Y)#Ee4*XDs8Go*$`b)ds`~J4TJ#7e
zZ^C)bksFDVSY~0;mJB3BFWNC~q)|F7>J7jBFlrTnEeZQG5UGk2JE+8O?DrJ%nsPKg
zY4<28clU7aZaoz@7!N8Cr3FPp@)2T5oME|6<lRF(D?&m~aVTIP<8AZRZyh6)8?QLv
zbdy@5@vmhGZYP<MeL(zQLl=@Bh<Tbf>FoizUhVO#REVRK0>xZrakEtB3lih7^jf!=
zMh_loI-*n){;<+OSj-lcvH@E%5(8E_N#W815<ybY=ECSuFP(yJ@viNLn_q__z5|w)
zEyw9vnnJ#uMv4bi2m2@1C!OBm8HCyX&hV#moosP45eXJkY7#=Fk99f3jXG$szXTaz
z@^QlgyL6<}??Ah1L}cl@{Cjm(phRUFUdo%p;~0=`4mA#>J-JjnxVWr@FW?@sQR!9s
zvnM_8Bx+$>;>%FPKf|>CAkG@39#|rT8dDpUq2ljx;hlKDsqV}Osq8aMZNp0zIxwa5
z5XMNDFh=GV?@P9hG8iSA2OITIn3O&BEziZ*kX8658B@Q=bhV;vQbq$j9i^GMj!`)h
zP^X?CXe4h%+aiFef;zU*AYta2vLv8`+@kX)#j4Wd4{ZYsfoHdh<mI*LHMXepe0hTh
z<A$}S<TP(P6v-fe@1o~>TLh10y~jCAZg~dah3vBa`lg<%n~g~-1L-=Ez<FR;<?93q
zAn1}wMIS}6+S<_JOPz=qU@^oZIa`lj@%i!l7)A4i$QoDKRe(Cx{8+lII8t>uKJCLP
zZn_oDJF`%O(y=^~(2^3EH#WP+2w}#sK7@nSa!_Eyk%(+<EREnC3`Cq17wod!;pd3p
zGb|UbWaqCGrN!?^k6KELORDOdOR8}#ag&zRbk={r!-V9g14f@`>n9S7<chudj4_Ib
zvw`hiOK7TK%$a38B3Dw{>~`~+u8~<Po|29Zl01?m-{rjDDGZ0ecNQ#Pcbk^E>cuyz
zX_iCPoyhQw4ayJApvD%$+aH&D&x*Wb@7%^h+5F<mdEa>hC_*uK%x$P_ijA-I#BP_H
z%c0u6ZX&j<g<D>D#-X6@+c}dFKx%9B^gF@mSndAArlggN!b*~cx%mFqe6(QgC&9e?
zWLx64Xv;|riYuL^?z?+7R`|}_dw{2UX<%H548I)NOg^LscOt%&`@!F>5nf0mb8@z~
zhn!i`W2ipeNiUfi;$0@8LF2-=cmvMMdQzUs=A;H7BbMh#T!JYQomQI>!?@ag-6mnW
zzxuY=I&0TI-%I;bve3l1LI@qVQV%^alnGd&admuB)IUAm5<DJUXJhzzvyLfftU*Ut
z%u@3Gy;yO6yvo0Jxamy(j`=NCBo6sm=(BXe8Hzaj_m9#1jJq>p0D~4f$Zeq3sykZT
zN!2^D91d^B%Jbi)pS1!+$aJ0t+r3oP+%4C)#`I|V#FSu50Q8xA*4*J|*ux?j$VjX+
z4iB)xVzo6le!~Q0e_A1KT8K{TU(*wY%B(r$7D&?>Eaf^A8h3Tt0ulbv6M-j>cnx0z
zjG>A|VM7I<SQ>UO^cLN^#`19jGj+qyxYDG({!{+ool+60mZeE{8&Ja@4jlm+P-xvr
zr$xS_HhvTW@Q1vDep~^_?q;`292Gn>CDwriE@iQ?8TyaX9%#u~0T3_tOrQP}CylGQ
zp0(tch|v)%hhe;_y{7e^QHn;Q?DbWDUlq@a$UJzR|1c}Cu}qs4V1!E&-6mMUIpwyO
zV3*VeV7sdSJ5P-YDHM`ae{g6(rga4`;WSY<Q4hsTmh1zoW(&9uXj@oI6Ubdf*xuAL
zvGr6Y*#+euH*54n>a4GrekqifcyW`X4&}|Tp+jRsk0>#@xs~xer$zg&dRZt#TE$mE
zBFK+&IZYb(J%k|cyT^#DU385|{roiA6w^{BXG~RNZ2S#%&TZV2Lul)={CEj&y(r*r
zXXB{k;-eHcO+5cXnH)Lss0u{maLUUtNS`JUm0DOW>>8_~l0w7$*t)dr>Z<pYjg!J%
z|JcL5cd4jS-2s<MOQN*&wAFt29N5OUW*I)xb{^m7+x%iS=wA1z>Q_nLry6%Qk@z#H
z&fzX{RnH2+vfb)wrLLgrlFFxiw45eHa=ZHVF<Xh9oLr{Ou+80x*B#EIz*bBs-|TjH
zCcd8hZW#bq4$*wQp}zUOqE@+;lZ?^9nlN6XkP^98i17JJbs6LJ{>77yCbE9*ahPm;
zm{k{C1flt8mBh5&zhIb2%8P_=I?fMnSweeO)NhGpT78x?G;6z8wwft38Ntbkrs~<r
z;F95jR}#&_2dUE;J2%_ZU(3R0n}Gn1YHz%GHgp)}>>M?Y8G+;5kyl|UbMs44L3Rw3
zJwvf7x?)~n`JHz5qE)wBN>uBGLl47w7ZIZ?OaSkd|ASX74G<;e#PG@BQ^D{32L7uz
z!bha(S8cr@3!%`WbFoeP)yX7Pc+`;p(&TfsB~E)Cw6B|#a6~~HCQmz-9P!rH^3dca
zgI|FhZ&c)TW%Q$usZ_-R1^OXL)_AcoP~3$*ZBP=CX3oPBn$i@UInUl>AD_<~nPmX&
zVKGvAgOQH+=CIn=)#tv-?~sX`Ge9=&5KIN5p^Q4fWb&(fd-gseIeT?}%bni-3cDQs
zQoV1a@eH^92JF@#b6B*yU~a7U`Jv1@j4V~M!#7g$DWIDNc6OJy3?Z-o;~-m@N|+@<
zmvvPx%VtHa%Zl;-?~x=%`SP_Xz_*Gny`rRhcktZi>)CSb+?HF^2l<-AQgyJrs^YQb
zMK`)BGPBK6;r)_t!`~O(>kzUXZM%ku&-OGrD8f}6F^YPfu;Z~>5hb8&q;tChqZpr0
z{4_D#zTrM+AKC?Vpwh8;<k^rhn<GAS@B`XPy{U#@6abyAt=Mhla7OG_5+Y5X3*8c+
zP(Bc_y%coazz~lZq=pW^;$>24)Ga<iAX?U=OKuj_b)+9V16y{AIVSA;psc|9L**9d
zQ}?&Hqx_^mba_ooer-#ImZ`zOEL9`wzS+3Xt>j(2b4N|ZA6>219hLLG{+Jn|%;ztg
zTD@fYEfQT{H?@kH(dkziEueHot?_58fvj3GY6Y}PRSKqpgz|4>;<}2mq-Eynt@ffG
zR?GSD&l5WKKApqBEL97rcW;Jnp?kpw5*>Y4v=>;Hsc60=L%XyF&M8Ca#%ShY&L#Ne
zZP0%68YqAwNg74Cd@KEY1^e$uv*FWTA%VEiG3?^{Y}TO0EUG-06gpep3T=w(-<1V{
zrgx)`uEityFQo`?1<MJNa~DN;Rdc(3X$bDZOfqj`NmXh;Y%95+qnFB(Y9s@&cnDku
zOb!9e$7Xno8b}PBx5mtMT_p#QrLqT*NKymSsG@&d-iW`Xi`7a2nckIueO@-uYnS3t
z>H#P}Dp|ONl4ig9bNha;Dt#Y;NRCDYEKyRe&e=CS@*4$Ra5N;%DUdd}^R16o8yE1!
zCuoe0biGuaK2%PRR@a7l<LQT`udX}wzvvlX_c^2#k0mOK<hVF{zb4sdR~D78s$-0@
za8}yTZPNB<<`T}HShzg$w&Y&CV|Vdr6*6c@lYl?{6|r$iu_l2TgE>N36{g<*H8&`b
zJ%{E3Nc#88OyIblH)Te5aub%RIv>Qhdt_ngwtJm!_s0(gM~!<?kgiu-%gEGNye(ip
zLSZp=cSkBH(^07pvuH0g^s_~^39kO=-)2@93%D!k)w*4l>cpnEQzSRo@H9g@UXU--
zyb6dbNE1p9C&T+#nNr0+a;Vikwoy6S?3I%pfVzG{#ZPZp*JL6h==L_aare9o6Sq@I
z{-zPP%VFD|s}~Dl=A{~8xSL2$kask5fE&^+8^~{cl#fzp@J*&XJ?B=C2y6(i5dNl@
zui}S``M%`LWROiU{-Pvh+^6@L?6GGMd6I21AAEkpM3_LXr$h?f49~(Q;`zf{!4*D-
zmmcuz^X!M`Kh#^GdJOguscM!iAC=G<dRHIeR3^j9ij7(obu7-hxVny-ViT;M<753N
zV6Czgywl5u_h*zDNpSGhV0<M=BaN>dN@iQ~h6;ddyUd;Arh;&Hz|H;L{l^BR5ACxS
zVuM((1AJIben2|<=e^BThvh;Hc_#R(o784&0fZ5}l0D{I(Fj^;3>sTdy(lwKm@cyg
zQk!LQvU2u!GXBHqDPJGENZ|d{SD>rojG`El=CZp_bT|7?pQ@?>pR32B53MhpHCS4M
zR#-lC-IL=zskYayBkXMKsw+*!vV>Y@7bkaFZ!zz~vs52|m$l>JnbzJBkAFJ)I~Hi?
zHckci-204O<CK-cc_j$;S6j=Xc`a(QUq1SJ(iDL<^XU<+cFmiV8*3-5hox9iwr|4A
zD_dB0^4&He)n~^xp`)_y=S9;w0vzg+*5|}iW(Z^i5`NqGnn9uUAw0m{Qh(H+5z@MS
zx43!Iy5sNwPWR<>t2K%(`)%%xuE~=~%2ut(<{8x1XqC1j3%avWC^7r0@|y32u=6oG
z0R9V%x25@OvC!ju;gUMd3lrP-?%F&-W_%7QX>S>;99f#(BF=&FPOnmQ%4~T=M4iK@
ze7X#Io48*Sofw*;DFl3{F+yZfnWYI5+1sS9*$2Oa75x#W^KnN>gw)=N=BkYC2LCq=
z3NOziozo(z8J6!^$@ayZ)PP31eV&;KfBrr21zMxr0YxzgrJ4iNgnConeo$uozQXy>
zxJ&LeMkLP*Y1lt%`f)(;tKv`4Wj&?!QjMmmvwClSZZ@k$JvXh;)y5;sVCE;+T62;g
z%}YYI|6xe!FVy@pgaPg}`?hEKSmV+U`v-hT839i#oYOt}g$J`n2f3JxZ&tX-q}pv0
z5Bj%ZJlK2Fi@tZ*v~!fH6ol(bX=V$(9qK;ML@bo4lZlVLV69DOq$KH#lOp79Q6J`f
zf+uf|?^4Rw=Rsh{U!H@<G<iYWd2zLwgVyS?iPZ*5h3Lm7&R0_t)|Xr9kHZ@1wZx}=
z+hMpwk0ITL4c=(HJ-k5t;Qf_5du3;WIXE6y!rK!JhPOnq>J2wcU3eI+6=y>g7=$Fo
zdQ;ucNfi<R>+k}Sokf^n#YB}E4MjS@3KOH@_|WLw8X`U2rLcRoRmPlAlZC3gt_h`5
zt<6)#Ps>!fY|<xWGJ#~t$egBCrE5quPR-~(hs~R|L+>1R4W;;ZfV|lk`AI$XD{DO-
zHTv{?z)S1*dv7y`2U%gkMaj)y8=8p-7`m(VJgKMM^ZWL0R(jj<J4_I5pXbkjKhKr0
zq*G^LsJ$5u)udGIjIo-#3iCzhz8%ejfMxeb0NUl-ZL;Rk<>xH=`%{Bw-?$6Sde8SB
z&*+Z2y#mU%chBd`Q?WMZNgt~Eo4wPefG)z-a3h6WUzJZJ#)_%)p0N_=EjtxJVrnyt
z=2x+f+nO2VcXAnutpwau4b|^j@h%u#i1xLsVb_CC7tbEzVzIV^5tK<*d(tR3ga|$s
zTA<W4FD)DRja4z6na)o}R3<ty`;Q4JpFXWW4{nQIF|J87`?+kj)BLu8U%bd)wl|nv
z%k4usm+~CYA73d#acbqPr2{V%B8k;CVrLN%SPqZ47D@)_nQr*z@+|~UW@kcjF_IH;
zIb74%OS91V+5x(21>DVS;YeW^Ck8S_&C0V!{jGzo2V9;Ah_>#4^UdSJkPd`C1h7wC
zk|&@U+k>y<9!=ZyH4QrUDUvJVThA&>|F(wi<}8M)<n8g+Arc3msirKaa6q5dqS|S|
zA;2Sj_9`!+G-jDZl!oMM&~q6j|1iSlj9l@w9z`Q!TmSKlgfpL)N-cAr1`b1*C~h&p
z2MXS>7v50iBeW>so=u@Nl`35Zv*h;^`X6sP;>`y@E?q;e2qZJi=f2skkISg(W6)59
zw6-m`eLp%`6L7lYb|9)fdmCB_Q1ujEmRfF+f%mm6u<f+%%hTns`UjuS?wd@mO6zt+
zOjl{ssf16X_BKxcWs(Zthn>aMm}Ul>Gb@+-;nF@;y;z<S=knqo?#4aEqw;Xo&1nBf
zabtRPNN?}$i6N&|f5}@f>Jh3h@{2msi!EhBOF)pRq_u_4%e0Q}1LhQFnWvDddZ)c#
zXAYNkU~~8Gb5A67lkn>`nY7x7{#-&v$Cs;~r-DJu!cj7Lazbg3?r{#ueJL_Y6U*c3
zineB|v-aEO!Ie8_b7#U2q>^Lr{=oD-($plT!sgzyj7T+kyRzo^T{=Ug7{O>gylQ1j
z+4C|P|Fj(e!D95{5m|xNl7LsI|NZ4?p+uGL<;4JF*5Yv2e!+2Oo>rII3-vME*+HQR
z(WGWd(Dz4opfWJ4_o|O+#f&7Y_bkc{;vGZ7-z9OFci<Yb*K>vMpt#1}-Q{ijM%Ja4
zQOZ4fvUqrkN9F;tzOAzYs{>~{syNA<jt|0c9dn-?JH|Sf?1J~V_79$2ti5%q&{16{
zE6>-gD9C0(KJlZPM(j1121SMd$mY78iACpZhKNP`3^JH$!&z5WFHgh9B_l=i3c_X{
zJ=K&;6HR+hcPrY|v9$mv{a-Qm+KYu@uI5;|eT&VCrK{8{)@Z0jI?_Do*~uAhl0wt@
zcd@(bZ?fT%U0BKchS261;hyky2Z@=!7u#8D>2SfF<W)=56HWX!tgG2@nJ0T-_P-HV
zvt@W2gAKuajBtq?7_DN?bD=Opj2wiqe@B%!$9y|J-r1V`tHJlgil896g2+&fYQx=e
zK18;3gksI@^%*5s71Y|aaT1;AS$=eQD)Z_X9<b<MMGe(?+$Hx^*|s+u^L4o;H+tO<
z*lO#dsHn#9G1{LDVGFDbqS;(7I@+kf<lf1tq0%847pVIk4}mzBkMU}QD^7<e1e?Sp
zyX`Y$tZ*`v(9H{*%DGW!8#C^8$$>?qShHr2!uvZUhk$#1+Vy%@X*m4GR0>cHt3-w9
z117T(k1WVBBP}Y`;x}FbZ{_$X*_D=b8g=(AH1A^~>#<f1+%xA3OU~}{FaGSSz#o>z
zn7D~oiXak45v`LXF6R$_Y0(R@H^M6Zj)yLt-iuB1N@tS*Ux_3_hg?+l>YVZM*rz1i
zE7I|;<EBZZ$M@{tb$TE<N{#Lzu&<#G6v<)<VkeO7|6pT{T&%MwoLRY>#(tUB9Awwt
z##_X6G&xY!p8c)T`|EE|Zd#+y<Pkgk2N0MZaxEG*4g0ZbQ}}1w(k0y)Xq6rG^Q+v}
z+iBnX!y*`e$fX;7@5|Hw3O1fRJ}_>@k643P;ZH3zMd&S6O_l)x%^Y9F{(Fe2Ii|7X
z7fqFa0;wnSC;xD~ldV0uY#Yqo4$c+*R8WjS3}V&=V@+P@vf*JO1PeKaNH0A!yS#ja
zzXghXZbYmwdFus)d*!dnU%umXp8Ri~9k72Ynn;~2{#_MDXD=&AxS6_3D6BAM({33j
z^35o)Xeiye9=*2Kkt}^;#}VA>Ptb2UVasPIr+no3x9zU%eQ=NDe%mk5FTKd^VzM=%
z)RHLS6j|ZC(fjB;Q+vY-zL@JEBx0=$N3g7Z7)0q+6t<W~P{&5)v&fmMhgwk+q$?*5
zW)lwBwi0II{5n{)Ys=rq{n_!S8RZa2=!dk2`z=VN)Cuwl10!P0d3vlyF1UT>ZD!aw
zWVQ5*O2kcKMR5+|)2tS*8b#(Q&lhbLd?uuCqBz(G=#%{kMuS-Ud-f_2hwPK6E&UVj
zAT%fg^C9NsvLI4;<aU;Bj?c&!goBZ=81G*tS=}I<)>x*P=={t*kdav!j;PrBqywW}
zoSVTkBi2veP0^*&5!%(}|BM^jRWfExZ@HRv#*o9+>{clk2$^nt9gqIIr1rJ?UDwqz
zZ5U8KmbVBFU&LaT7paXeqL?So^6OKYYBk^GF%?%`6`fg6)8!8qR8p=`7ast}M^zu|
zne@=i<^v8!0++sYbXM5-Xv#;VVPvPMS~gLD!xPg|@ysTpQs@Oeb^sKwRK#K3uwKn^
z6Q{SwZ0^Dqn}=v&qH1e}x@xHDxjAAKMoPK?mI<-c=_Ns`V%Y`e7(W1i>i)pJ<X=!g
zM2qg8hx=gVGza%cH?WB^BHO6yh;06&o~QWdzDcc!_LgE@*jCjXu@z^81}w9M&5cN9
zo!WwS#y&9YaOXMLZ1dx$B1;|5`RlG#h8$434Lmn(q)i{(uQ98BPC^fa^DEgZNyg%K
zDIV5iG2cM7e(eel;;BEoMgQeBit#Drp*oaF<V4Pry@kA-;txF8?=$j{_L(dsoln*f
zoJvD#Pa%2>!7?u1z#;I|LLMgkQOit~<TY^8De@)XDmGs_L)sN1+hH^cua&Gg=v=XN
z&iszUin<n{YZS%SMZ71_z<G=GJ@{tj5nC11(s+Ye2D_Q2;VO7NaG2P3m)l7nR@C{s
zA6_&f?Z#Hil%8$($DP*}+G>J2aQGkj9lXAKGvw>RvZ|&b-gFB)1k`3)*40H*4ijPC
zf}pBBP(FN<tgCnWy3=!M?9Umk%j3Fj!i?g)ZLbKmKWba`+jEl>YEmv#p>+O77i*KL
zS}03;M)yPaD}`-Ea$b^}1J_aDb>!BmfcjI%0-@Uy-~QX~1tPkAT$VG|Zl-XYp{{tF
z{EK+wEAGNsZmlm%Y1Skpg(B2*uN)sn(EC((7L8kibTrd@6Y##k&@H}?-YDG{J>}9~
z=!BX^F4wEF>TT!EXwKju*t<xlKl1fS^83Sd^&d#9fB^ViZ<Z4&NETKOIruHLgm8=m
zY)i>rNJh3Lt3{6puZF%IR(sye5{xflqRwf3KMHbxrZx04*UJs{2tb5dkSNF7bGprk
z9>%jH^Ejh3SJgT=Ff;pu>J$7eYxI{(sBn$Y2k$p-7v$<Woo_aua1GtdQDg%RUe@6a
zYYep-FXOz6mO0dFB}loVHH=y&NIecq^Oc%{T8r2EM(cVtHD%}B8He$`0jc5F#vEp)
zJEx-+tvChOE7Tk5C+de4OtjwgP?E`}EO;Lb4A;teU{Fv}vX;6yWUZ~_Bw;fZq<_j*
z0SaNQV4GaQj3a&XlmQ%4YT(7EFduDlD2hw@R34y4n^}6sOqCjx(tuu~9C9^rFNq%v
z*A05Oh8t&~Y>zSZb#?|`<(3VDGW+{U_-L&6I8^JA(l}4YwpWhxd|`Rd&vW2992}QX
zl@v{axmD$!sFBK2Yi*;b4qUuqb^_jxD08@~88fO3#B=0$(g9+@BTD$1b-hx<5ICnp
z&$X<ry_|?V94D3j5qMQ>OA=T9)G^{LwV?;SmL2m&EGc%4*0<bvcTU>BJmyR4BN2Y$
z)5u6$|LgXA+MyDbT9(v3b=DKQ-chQvtVJuGUB>q_eP74c^k1@=tm=LfrZ!qWG)sgL
zJ$UlSU>IFn>>rRc@*h-{#kP54r6kkx;J-UR5PgNA@;~^7Q4{YD4V1lxdC?u>Zd7Ih
zefQN(G!w=LkN8sRKi%i$q#I6Y4MwTvZ!Hh`x-M~3kh-M>U-s~+E2pioGqKI79jFQ$
z)QEuU0f((qzlzJt##8m#%wSEN0wgOH$#`eP8W%I`Kj_eDD)tJX8|MxotRs>vf;L7{
z{RzW{LWxK_sWA3D%#FgQ2J_RrJeWSgm*D=ufvxPw#3sn-hIEat5e$<b44kB&cqk4L
zADEq<pZIh@Y8W9pK<8w6ph?RZ4RRy`HKZzkYZIo)Nsz-C7j5i3zA9s?NU<nZE+|^C
zG)7|;G|6+7EboC?pTDC$CdF8nZ=qpfMMXN`ZhqOAD@D`=g-;_*&JBgb4SKJOwriT8
zqEB0#;%zRG*;BXA?WHhvxPKj`0(80F*ZRsKBq6P+R9jU~*OOC#Gf7MXOb4wB&QAA@
zVCBGxP*GEAbr!oz6A8UbEZe_hd`Z5NWF4qtZct06e*&v#e6y(RKJMJ5!Xuyq`fPzW
zmS{do$0WzN`M!2K25BA{-a4P9PbmPy!NFQC`nQsjoRXdxrLa1|7tfB8oSaab;g<|J
z)0y@;<7pm5Dq8A?eE+>YP$$rAX|1qZv6cs1_Q4I6Q0;~s^4t5oJpb(;kTz^2DLd=s
zAA;Ld6LcKQKTEj`YYoznp-G5iU;cDmpbysWkrVe=P(Mh#DLutBsCmTpEwPJsPo%7D
z_utN!8hZTUz$3e!#?1E>q|@`2TP;2DQRRuwiY$j^#59)Y8LQ)*MFyIl{w&N-=sWxK
zMXfuu-`5pcY{Qfpr4w8D_2L~QTkOWCrU2|$pOKBq>SVfT?Z<`=MB-DhRJM2%N#7h-
za*F?=%6;MR>q{V_%eC{DSCi=GpEms#T~uPqhW0HMe~s0NF$9ma3%9F~x2#JGe-QC-
zd~LS0veL_t#i8fxi#CkkMg@lSj`iv5gLM-cI>~$N?(;ewB~QIfGtS@lJ1#HUH5w}<
zNm3c2NTxQsxir+Z<+w{Y3KSHUZ|G>_1VTmpG8t2JZJ0ZUPB8{|1Wr-tWo6dZ4biAt
z95PnM)kESyL=aBz!<j--qAjaXSJ{a#dbFyQ)?<OvS_4(B>nJ<*v%8%L#e2aOTQkLX
ze+DgMgLf+W+`PGMWK=4a%YYOL_P$v6Ui2WU%v36eZ%+F))sZupbdmE!i?F<khyay>
z2w?qh3}H$AMjx&OKGf{aQsIlp#k+^=dXa2LsErN6gz^3`{oDWtVR#3`_2Jxs=dpsn
zpEa+iQWvUQCGNhj>9(mC#WO;KS*p&yCs{zrNG+BPbU3EC^g{SCMnmt|kJ<hu;qti8
znQ##fLN(zdLPKFSu86NA|H!Eu6%MB2#cee<qdfQ2+jK;$UcL(`zapok<*}jE*1@N$
z(9y6#ue|JbmC2eE;X7#Xle##i)Yh0J`DiMm3j5c@u((6{(I>zYrxTM+oEj@4I36SV
z!s*g^mNxkxa0fbnz)K`KE1U%k2_1|<RE!zR-fq5`o&XDbv6g!f?c|*efD+bSG%+?u
zzW$2a?tc?AS~$l9WQ7#ZWM&U<?oKhaJMDeqZQ+Np@jF#-*aky=r$aKMF_0?Dm{WIS
zBwob!tOVE_>B~@21TQmxg^x-yme5Jhhm4LpNqs<+5fKV}vncBzevqr_AVRAo3gzW-
z3wP(wo-&h@-8z0qeM?r(mm**PLH#;B?bDG6>U}fP30IQh!Ap4Icz|%n*oi8Z!3zsk
z_-U=?q#o%XTJ=lGMArKpPm}OFG>#v|9Zc#6A3Jr{g40<iQ;KxlvaSviJ0%nv>QUYF
zPf4lzfDKW=igEnrJ4@>9RdaN32lr~j-NyEVWK{4{hG#Yo{=*vzX*bDiG+y)D1avm~
zxatkXn6Ujj1zMnoTKR7Z-RV9C*|A~vla%O8E>huU6#YIXY_-Z}Q}gVhIS)w$U#BeA
zh|WLLzE}ElM~c2Wk^4PcF!F&_s5FqC&kDd}3MwTz^ORJSEw>3qm4O0U7A*8)ytYc`
z<wxeJ)3T<vGmo?*7ZvsHJeR{(iwOEG%zWL89x13!S8a+97rIUM`6kcn_}tVd&A;;^
zB|w+ZH41d&)oNy61T28OOUHF8v#y#Zvw6ST8T|(-$lnWMwzyh?%h+;cK)Ev3;3J#y
z>0wzrs*Z1!y;`oIVaDRv>%Yzy+EDXa#a@-l6|vdtR{coP`J9}(4bVg7S74MH@7&Cz
z0{e`VuoN0*8NLov1PwYva#3^DrW7>kA5L_9V^hr}YYn26)&OsNiB=}G8Yv^m6aZwn
z$qQAoGN<z{uuMU@XeQ_U+-kRjaeWJzm0=dNRpR=FOPe%NqSPXJ6bKe&U2Zuv!o}}j
zl46548GtFtdbo)&G`7HZc(+zpPts)SrvX*Ogv$d}%A0?qiWzf*2mU2MK|}#D{gyt-
z#N!vsbjww%I8=s07s1k`Wg~he9dw8AVCyS(US_LUwm6n9j8#lh-4|%1czQ@Aq)Id#
z9ZjmLH##Ze!>P#}K{@0oCBN9K776EzUvLB&9y#D3sn|<ij}P;c@x69b;2PX;>tZJZ
z?y+|)R)#2P)JU<MZ+mlNt78JQ9%DhELA)?1>`m;*%W*ZlB{^Efl?9>z8g;zQ%cNbf
zFqBPoQZc2Xgk^g7z7>8xvfcnnye@-N`k0|J0f+}KRShl`1KN2zUjM*-969wiq=JfO
zDsx;hw1|4dV<A>mPa15`9kbM^+f2mQWFS_4({3ay)@nY#IEfLk0aO|`BbgWBpjZb<
zntR|e+Z3h9@kTVqm;O|?P)u%myqD1~l_#}P=`Hz6%k*h=sNUFz!+b*>L&y|O=r<Rh
zX2r0mKs#luRiov4=5(*BjN=q&PxYZhaI6ejVmD)h?RH8#zmNc%P7#TR-Hr3@?J;j=
znayXgpjqe9PtU7a$U1J8FoJF!T3M7|(lJ>+VopNHiDmg$%?@5vX4#I!9mG3_KcTSJ
z&Lmy%y!L3(#F6C@CVY991?0@r3A0|K#yZ(IBaC;@%^DiK=~AQS^5wYcl2NIWi)%-`
z1M;IDdJw914a*4-WN|pgHe<;rW*C(35G2S;si+a@mjW`WVqp|1n~u?tgBw<T_r95x
z12-|3Xe|c59_??v>~C$TS^8>fwVqsOEu`ln$1RW5AYP!Ds%&w4#9=y}-nfFta=y4~
z21E)@H<fV@jwfNkY3npoXcQv?g#N1orw61kHeL)uRqTY~@K-IK_rRCYgh``cRCXY>
z1Z!7SI6LOAc1{exRZ^=TLhAD7wnOsH1B|15QF(@xcYkZ<51qzg^z;4+ir+TIM>Zc6
znGutErux^0Eef`~fz=pAWWp1x@_l}pS))=^>i~8FTGN_i#^O$WbpOH19AvP^SuOK-
zDQ3(pQ~H*pjk1OvSkQOZ5LlXLs$D2#+ab{nenQX1s~3UA=SR;Nlip|dPrfdc(Bsf&
z)1DA+aWvhZT_lHdb~JusQvv-Hv4=k@#{L2h8!_$9Np@&nHN#250dDd-sUY8^JzVHu
zDvf8`N;y?3+rZ#v_nD7sDL)sc)s`%OwnwqLuCzxLq1qp#FugA#^A`6mQqhNUOV3tp
zy1$;_l0n59>la_8@U#%x0eU-Vo~i}A0Vr-EP&nN`zF48U^g%-ydv!U$@!Hvqror6U
zYWza<CW!-0e%(+aaIhU*@ZdX;w918K|KjuH6>bv#a$y+JL|rW0_46{ux|$A5VQiv!
zs`tP1e}|qz<JC4I*MPQbIH42qrN~n8vb+@|!6ku|a+Iv5^UklRx!4|$7;{bTe(lDl
zEP?)JmhS&1fB0<f%MGumD9KQ9r}E>Xy8ecB3kfM(F6&nLT;YSuURYS*R=Hn*9gn0d
z-UT$GHpVRQA_0b63wMj1gWEQLn3~u~_s@EGb|UN)sn;=6r#ssQAnu$6BPh|oUk&Y%
z;`WSBJ{RnsPsT9g|74&0*mJ+xKgyoIojT3B&*$Jv!%ls_akncf>@Wt5-?|h2)jVP{
zm!D#ras~N$JY2N<O*g}NkKcy_dRa-OaSirjf`ykE*u<~tgjJ;fU)ue)U-{D`hwcUi
zTd;d5ZH6w>|L?v2d;OZ3@zH)SzpSQpqS^3By}9T^K%4xzQh!qUkIW$5$qY76`EN80
zA~H`8_k9iOUInX=c)$Xki^d=#F)NiAdM4{4Pvm5KN4^tw5Cf7e-o>v@u5f4EvpKr0
z059GR?xu2wJLY$Cfd9kN9=?v`8?1)v)v_n|0O3anR5X&7tlghpN2o1X$t}UEw&ef#
z_<=9e1^@E10BmLnuctgG=|{sOlHP{uk2Md-8kj0*ejfH?wD@}Tx$<8@<$u>)OH|~K
zv;T7s%*)T2Z8%c^m`>8iZ#y>Q!nWKayq>iKubw6&d_6!Ns-0#X{>|FK=3h4Cj?9B=
z(o;?GQ6Az>HV%jvdI>pVvVTtSz`VHKF>avZ9U0xp7AL7?c>T>{ry>9L{}h9wC2NV>
zY5lpK?uC9MeCPT%hIIM|udIVC@isq}VnFah4k3$~INbj=LCSc4dfDC?_8=2`C+_SQ
z1S1zrj2>u;!yvtI?OfU|fwOc&vP;_~?l|~kLuE<bbdGj|WDy+3ApKh&>jo-k2Hd$T
zKv4eJ_J?IcH>gzrnh?Pv8%Q&WE@TJKt7cDg>_=z8$4}!QUWxHPcm+m55<F6HQRIaz
zU=r5)3YzFkX{7%L(=uSq2V4!Nqd~yh7xY513$7(<4rB|SWIcy9!<Q~mU7(=TU)&Qs
z?g^Uc5><GODzpLc+q;tBO+(<J(f`B}d=`M;@PejieTUl9bTIv+J)RC^D~lWc<=>95
zy#jik{kh+JfLns;67B!H)(O9nd&Ck<LGb0iaBiSx9$jLGvS)1+zyE(3h_r{HUXo&M
z%P@DPtIgW{*L)LnE+Lnv=alMiBmXqs&I3&kZR`Qw%mO}$Eg47i?~ddhC`p7D^1`29
zpcX4I%AcrqDLdr7hd<enxRZB0bEi7_r>{W_J)S^$Y{7UzfHmkR?g*POi5*~S=^tQv
z6^EXF@y$PM$zGddGd%supvYhG{}ML+2wnkQ0cXtMCzOQyfA-D}dw~hWdGD?{*7DhZ
zf^4Q!&l$M~_XW=`<QB?b?*H)hl|gYdUAVXgcMl%iJuJZ;f(3%UK!SU4cM0yUi^~GR
z-Q9I@ch_a{%Xfd>U$<(cyQ+J-&p9(^x~oq=55s$4j6|e8{9><`Z2rIlOxrg%*?ei#
zEzTabz%f)iI(POS+rmB9xIQ%t9HTaYN5GaB6W4!hJ8Cpjz`_CG^v>ptqs2Avhr&zz
zZAXk?T<QJb+(kxOJ^(^PR$_wAJAzccJ#NA+GQ8t)rfi@V4B>stC;xw?<yY@>-MU7I
zzeSbUMx{x_`(W|>IQj)tvC&i|BHvMU&|O_{bzkWJBkG}^zLc*)jsha2;;qSD=?AWM
zV}2Crg7ZdivEmqhq`L~7Qh_mI>`{3`gG$|q9_ZF+3EfiPI^I-|htZ&J#inB=eo*4g
z?UjrV(GZqMJIVR=dP~T|?7pZ<ac40+=1O=(i3P4~{oNDs7YnHXgjiG4<L-KwlHBCK
z_(kZfrGyXIM$k30b$>6B3tWZ!<ns5|M@G;nbQLb@cK;(eP57S$I%hq7!fqo>q$9xY
zBQ5;|`MMHmlo_5_pR&hUIHa9O8`^Fv$Ly&r$D^rPuPPV$CGw~_&W!rinwl;2E=)pK
z!q#j-LRVq`UlY0|$$<O??yS>OkFy?{Rm2_>bycBLkpgv<dSp?Ngs$>L0C)IK7=yY-
zL!3-f|5ru1xuoG63hIgPW@8i*x>8JRSSXf+v$1HFT!p!Wv$*A>H-T{}>M|M~aVcuL
ziV|{TYI?0~hy;!0A@vE|x-7x<3cWgq=$3rR7{7_pw%z7tJt0Wc6JzPBw@wFh?OBh!
z9Oi)kf3`|puNhGyBlWfqUzR|ftK6SCZ2oI`>PbOpnYb0gTXm5Pbv31W-#m6tcHA6#
z87woJ`AI1NCgx-3qRYIepnyb-=T;N4f<4k22ECRhUg6?56|4qCg?b5F(eFbvRxI+4
zn&|WG1SjiKx@ST2!V;*+@5uS%KbrX$kW!0<WC*qe6pLa<OHnMl@T`af|B=_PqMmOF
zx0Yf^EDJf*Q#xHQD}URR%gB|E+f;NvYNHdijvyDbVj!;$;1O&}lrv_I^%f0+D<QZ1
zjhA&!^HN;ch6tiy5X#Kc6o@B9ems@m_*zb4(K~xg55~Z5`4NBWB^N<iPPKAIO{)_n
z6i}e~GiEOqI~xMW#&oWH6EGDEN6_K0k0O_!<1nWvc&vOogZlowjg}*kldCd|#CX(7
zWYyo`Dj}o~{vo&mSEg1FhO=dlQTU9a+$TktwrSXXiXea85QCco<wr)5H3*)CogGD)
z(cqaG)gA7EG)Kre1kbP19u=fs^^chZ>kOdGuP`mKEH1^x<ysX{ogCBNkl>b*`)B#i
zG8-MD#Lv?qHV;tuqF<6RE#K5X;8gUa)EL(2D`|-(od-i?M`mDVTt-12>DN_Pp5)k2
zQo4Tzk_sy7StB?pE5t1^ho11{vJsbNRy=Z6r;L0y^iE53?v};v8jAv-b+`|5!DF1Y
zp-IsYYy;CV3WYy?bImGWc;IBU(Hmmnh}uK>OB&|oZ4kV^z2kSP$CsdgIi@>zLp_(}
zz|Cjo*uwKV{7mkqp@>i+|I>$Q{yWMCSl45_^P{5P`<HxRrVeAVrKB!L;)bX3nLgvv
z)Av^1Mzakxq&#n|+LCusE*$_x$a{4}FWWbHA_AJ6RNAb=QW+D1px}RMFywvAW#0aF
zG<x2@-w_w_2yED?X7wU4s%U=%yVMali3GSB4wmUY3O}P@qy;tv>jEIxE(YT=vf<fS
zI2#^Jg`hrN1C^C6;M5NqOG9p;rEQ5qiHUS7_EhbmZ1^XK7U~{mZqo<s_)~vu9;mKo
z@U9BA%0t|j4~y@W=}8{RSw4D4N26(9L3q5yCs%l};>Z3Xc&pAR{}N`tlWX_8IhUC|
z&zgdz`q_jn<bvbZnl|2uk_Ew4J*5Q<c)f-E8v<W-D5H!XD%Ea9f+y#$rbhYa#GsV9
zcu!|)1uY;ZpTkFTB}mfYoK~_id>UR3kuO60-{ijI899ODSY$c!<951|_H!4NT4n&{
zC$zM~zpC~$Z@oh$cC$_QXtg2L$f;+vGw-wfqq5hq;yj5BC0`2#Obcss`r8b}Ck4wZ
z<l4`0+~uN$)zx#X7H|sERT3_W)lEUSyK9d**uos_cX5IpAyM3(5s=y+BGg!l78FTx
z*<(Z}9{`bO<2dbZ+`39J*y{7%IUC2^UhtESh7@dN!h+^28P$Pb4ON*cwq;p;BsjP&
z*K-&8iYjkrJIELH^;Z7Ka1VZI@AP0f!dcm&h4|+^plo~S9Qmm4qWM<Vt4#kHjqzwB
z#T^v)Mi2VMx*-o$`l-Okw>*|hHT8z<9G~)?ahqbSN;~|1J+Rspb@vih!rCl%SyASQ
zwx1u7l%q;djw5SjDyZ=f_pf<n<w;WR*X@6&Kn8Q+vRR^7yZGAzJq5_2QFPJZ(411I
zhBJmL$?^49C5RLg#SX8SX&+DByrb&J!biN&PpaCcdlFGr)q7G2#n@>LTZL0@o|G%$
zaUx!TM0+8JvgBxW$;#}$B41tDVaxcLW%0^gAzdT35ad14Q|TTlb2ut7RY?^IaUEfo
zpK;%bAn9oINJK`Amhv{fE7KwF<eIre%F&m%F};w3|Ag|hk5qZ;NLJl_4w%e*FsV#C
zI!>qO)GE6BVc>afQqjU$aN-rEb{1A$<WibwGW7i?y4=0JvL?LHs=`DluxMJZF)_<*
zc=z+)#=dlV2VQh1b8!`H1y=k?<cQ*w1m9BBQ8or2awA!htw)FUtp4U@eA$@m8T~I}
zR42V){_kUQWEkI9CDi|A&x>L?>1{QMe+jED4a*vEh?<M0L%TVj2&;e!N!3j=-XyUH
zdb3Y#YnEroM>35b^r(r<Z_;H|1+`|%`=t4<z1bw><QD&F{ANiJj{_nB|HQ&?h@;JF
zBlca*Ta%derPxj{aRqD}^Jg7;SboOeN&&)EdkeAV()W^7(kdCDchhORNFgZ)XUIP;
z^x2brk2$puu7g_X7l&BHa|k8s$9nXyHO2wuLGH>6cy=|KwV%wyJt<%8mBv8X|K+4W
zqE?DW?U;nbe*QhIR_VT%a;n-32g`^G=}I|=OvxY^G~xj!?Om8^`;pYkV;tH!ZK>-b
z?r-KxDiiI2d_lOKqLr&ky6QhBd_rTd8VV;l2zh<-^=sx&!<9G<(C65U%FV7O!diND
z#DxT^o2=a(emR_f(H0Z@$}6}gv?3yiy?^rb)C}2hIhB=dhUCQOY)^=;t7&OWWo+lL
z>7Ra|>Mp2~6xCNeT<lQ>>ThnfZm@%_9V|{cI|KXphW<9gyfH;OoM-z;p0*TE27r1%
z7;z%z4zDoa`Z6zsraB9sOB8VG	FjV>`3UjLr?vBtXRiXY`W<aBX<2cpF5Cnb=nJ
zr#WnucY2*?JQ{SleZa@DqwCq`i6rA$-W;Dp2`ceZR&{ez6#x$%I<1S+8uWEYrisqV
zxJ_A@+i%L%ch*(AO*nAa0TWNDg3<D`Cj)Rwe>c0aH8s|CHQBQ?6}dT!3jDL2urR_B
z_=<84!K{QY$UCx771I}*#(*QHJR+ftaGC(Ft>jG3DEEodt~p>i%!r`bI!8-2$G@q>
zS!*9+7hco9W<JSyh2@O~D8GvKeRnD}PtxS<#lXM{<mYVo?q#&OMQA6Al6rbhb#g|!
z?}^;3#%i7Si5->_Ij^dxVJ&0BrO>1^e<r6^t-0AvQZ)&0=~K)Hf*HJC3rIOnJ;#o<
z6Bhf%f$@raO(c+hWo~)Omb7=`TlDE?^TG$KF92bbPqu@sE>3y=zMX6~Uky%0!UAe?
zwk=ljm^Eyjc#xl4Q~fP!jue3*(h|Oulesi+Gux9FId7BO7->WWi}fxb_%f{RGmtoT
z&o}!ix%%H4+NFQ!ka<V=FtIRWKvWbIq-En%my~Cu5s(s4R4?KqP%jJ#jNyh^wVAQm
zf@Fh16q4YR*(xl%h>7Vxoj?D}lr}Ro^vScw{i@|lleYt&oGnWe>bM0y8SCU=?-AU6
z3`DB=Vk4fK)5Ne$vaiFT5&iF7w>@L&KlA1;H)s5Ey}D$FWNvwEqNT|#2j*JBChV3t
zx0;X(Wdk6NO+x1O3Q8x#0?d)c*wY5+o+QaOK*kHX^@%^=RaIR~5M~kgWMbQZ7AQD>
z^>h9v2LXcFN<~6(alRAHy#P}?plP5b1($DVf%pO!mS}t?x*nv5^n@hRR-#ayNJOAR
zR0Ds~7oiN4#71rP;>>Iwf6D31FT)L4LV%1B4WS*=cmC^iQ@;EXqgF2c?Pf*%j4SPz
z_&koC@*&E!uwYyaArpNtg5D8HxZUykw8;G2`YH(pxnXK->`nfj6*Xwj-!tMTwpjOq
z{#R^6R{vL}FEfFP?STW{3!kroKY0D-k$a-Uy{t<63$k!owaWP`vv79gx&^}XkU?;L
zNF&a&%?*9n(3(hp9uRy^ZIt+rJhkR5GJSYhdl>YhM1<3%Yy$vMTHa)Qd=F?t#fECj
z9J>)oM&vPVWfeIAb(^%rVT=vG;GRV&xZndz-a}Nso;;#KP^52-Ca}f$M5E-{vq$Bz
z(b1sK+a8e(o3WQ%#^LLwL8PBo__t7gSV`K`h(3u0YkuQHik|eqWSFqWZm1j<=3J0u
zhqq=2U0HjdWMcaqN&<tF%}=qVcapCr0!zGKVfydl&{~nHV{mmrC1Buj-9LDy~%
zxI-0t%H+LE2RTtHZvQ#pw|%0T_CgdmV3QW)`$zeJYVBF<ZfA}J>}!6ESK}-;{I1se
z@W=}LpP#kW7GdM0VSPQQBf#2lxS^qm-7;r^GZKA~EqM38V7-<0(lVE88cc<H@Ptu)
zmUZ^T!i3S}gl&!(OD`X*wY9xYbDXv9Va8!Y1Fyh0!`qjql!3a8LjfnA?bgSt=_Y|7
zMv0<GU7@wS?^=KQB=nctLm^KLf|Z%eYqRYZ9>JOG?G^ygAAU{Up@xM94l9t+nmTy0
zfz8g|+F%K0Vk*$;P+%%|9kYse+&ZlbrFH!=ZitUH0N&16!$1+;vfPgA`=-iKg}trb
z#>U!GeYmxiZTbRCIuDuuzt(g%3~!BYO&>*r+jbOz3OhpsQ}~v00xL_#0fdtje!e(X
zi)zfb1r95_?AYZ}`|Pe#3QXGW-_HeiMT(h3{8G)Wkb@AN&vmPM`JSvQ%>~JtaNr61
zE$g0wgJKJWzgxQl=wu9*=?mY%a4u~9MCODs<;C_GN}Hs4AGeoW2kUPtZ>pP=(5_nu
zOm)Yx9>QD`O0hkT(k6|dScd8*Lz-viXZq}8J;b>tv|@XL7b>?381F<sq=141!V~oQ
zfj8`=IB{_ddU*!ex!y@1w2-X_di9;Uk0^><^@zMr!hc%!wV3sDD7)5fNHN%_&f3>*
zblKQBtXkJ@gelmktT>vye-I`SaZzbN<&kihI0D~s0@*&hBL4=$(bW*(1sNe?E-AZE
zXOK#eo{$z6b%xu_YsW=;Vi&%Au>uaxpq)t9Cp?jy09AnECkFNDy{a*_76P*cdU1H?
z;w=^&%;FCPg2GX{(+IkMV+#0=1W#lcr-_9l?0%&bbc{C~0nCs+gImZ%`_{r@xG(d-
z>25PrX<d0;T;|^sJYs)vQ_cK1FkL|w9?l#^Hn<XcT*B~PgZ1`?hq{wP-7%r=s8Dwd
zC{*<7TA-dptvd`3$_Yya*rG-9)`X?13y2Nr9%9}C5<#0uq0KnZW(sIC6%@*T#f9nJ
zj^N$?$-5oV`z8AkJvxo2o)lUGPer{2#6AM$jE0qp1!3`A#bbEmi>pvv&7gT#A_8Or
zVow8NIbf+C;Hj|Ssdl@ExVCl)wsyt*V;{a#O^b!|c88%uhY<k^0kKG1rZ`tKu-<pD
zRNC-VMlb+7WB?@`0J2+>;~$&YJ#^YVl<Oa>n)YlF>JjG3bvcW(1;m9~zyVTVsMfoO
zV6M3Mld-O;xS=(0ADx1~yvxS$W<>&A!I+9%)gnWik^d)#BMMXy>3?EmApzddyy*fI
z_^!5lRk`7)lDmg&woJLMW-z=z!BVaI$7Tk^w)w}}ZyiowX_#~mjdc%Yb`Mbn#HyyZ
zi9;S{%(j5U&{AZ;N<gg2mMIE!3D$cJ&U;NX8Ed)m6X2{{mg$O%%;}?VWC5|F-9ufl
zRI#vBQ!rFw2moJ9?-v{>6sCciOBWVWhl>~x%e@6eh3a7bU!D2K8gvh7`^O>�~}A
z&~^`D`9FdEW5wX9sDO#}Nk0|H(ycAA>Vnu|0T}_Yu3M(GSB?}{j$~KYE?cHzSC05l
z!4DgmFjI{Vka!CQ#42o=vhV4mdfOlZF5m#2@ZM4IR6_x=;DFe71OPyWdMh8}r++N&
z77z!jgXFD`=xqZJutNe|zyc_d06B;NLpXpTJm3uv3KbDnV3~GYiBy^9+A^iQazwnU
zrGzeFdar#5^wGTN*6vXEkiCB_&$!no6M)Ix_)rwOi8*`Bsk*#6bFEJK>jz6^+Yjda
z!r53=%CN3PD#f1)%x~@{aBs>=LTR4|@|56+l19Ijy&O$$!g|-=`klWlOj5zb?MQMc
zXOYyc@z4?U^(+&=Gnz5gLZg14-GhhZ@*^U6s{1xcYQu5sB%2}B3HCkGdDu*1cf$1|
z3<UH=1v*3Nm@ml5e+O0#{d_D;&hB~A`8wEvOe8#9;>vMi+xYb`=0&{pzZrtXa&Vm@
zrcqwD2Se6)_DpKiO8QK2c#?FSGrE!(A$Q-;>ZOvB!re36Hw<&>$Z%~XB~6&<Q#!5(
z$*jR30;jM%Cd<}umB65RHzZs<^L}3X!Fl*cr_hAI%`t*@TpK;{ec5q=UC@4&P;qrg
z4>DEK2vb?FvZKi1Ko{=2%**Qav+H0P34S%K#Q14Dl8NMV4cz37`9-ac2}Pc^cX7M-
z@;|RhT~;Rg+*%!0a~;+}sMJ?Vb7RiW8CyFds(1sbsSo$}0VhQ!!O<Zv0X}(3rs5=n
zfsx|zb<J6tp@o0_Ms<FfC@}OSCmwKDhGczbPF}r=ur=XCA6Xiy!^2zsWuwl(eA%4V
zp;UIZrx_GqoAl|EObzk2{^-ZJ`$bwp@=Aa~`Or6NIRrk3uqXk1`p7^_5a24T&L1?E
zyJtC7LqbBI@(#0i+vRE(5b=Y^B|U|9hfOwsk3k2MpTdbX4YQVFoYs{<D1n*7L?jPB
zM<7R}jLueMZ=A9SH!4g_ZWR*%Q|ni$c|ign8P7velF#)+YDBuEXLfS<SCZ1fXXDPK
zn))E&*4rbMbcB&#-opWDw0N{6ppdl5WhPm?!o6$FrFf<|B^T1S4UyNm7y%gHrE60d
z67*DmwromfWK$YX6%q|4nqs;%_vuOg7UGd2OLVACFAXYxPeep&=x|w*c=j3t4s8T}
zu%qkFQd(Bgp3O?3a9*L*zjGH8&Cg|JE;&haa_kD33kZNn+Y7qdiuvVvDog2R&V?QM
z&PmO;A#ZxzvTww3UvQ`+{xiZ8WMe=g6p6MaW<4{N_$^d+S=b$o@XO&v(A~kKMM_*A
zf9RV9Jf60)K95>W-G7XJq$-emid1v_2LC&U*QMESsko%_;bpLY6mSyimS9Gxbn0<6
zCwCAYgYakw1&18v@)5EvT_p@{95y*19XMV=B8UynXO%_a#R!QaBO-18{i&^c5!yIn
zfYK_Cp1EV-)$N|EP%A8F2hzJTrfN8~Bsjt1!#ZEA!G6Q1k#>4q?vEhax|G^so!R)Q
zPk{2oDwI@+8PePQi#wuLKVt7>PSSkqlIWT9g$|Oq<OriawzO=DM`f>ZAtb_(s_taT
zZHe>d&X$WfC)}n?EsjP4dQ!HTiV&zpRTz|eA*Vg;ziLX)S{>Kx|5+p69D_JHI`plr
z-E$vT(2Xr+rN41^XsQANy}qr)&K=|zb|gQ$x=$P;;8p*XwjGRMm57>}aK|sv!|x$1
zcFjPD48RYE=Z<)8e{&3_$Vop6&!%?$LimM(h4DT<BY>8PKECs+cco!rfiNN=;Y;lm
zk_eIrGXpb2rN%iY&|(F1>c0h*TFC|!CLNQUKx)_i`6U!N1x{&`NHmj3g-Y=Wsq^Ff
z{2rgKo<`#5iDL~siusuAi|qfNoR0Yo(b7CB=ZWj($FD0LAm}DGaS;eY&YIc}_t{Ex
zNeWJBa{d_f{YG*&iJVCZ0wXb)5#j3pDE?dc)+Qmtv{&Y!qtHuDg&ljLIUFYupO-L?
zE)rY39g;22ERJ&@KkBHXM2Bx8$Y2@BFkDoom;jSV@I_NDU&z3>^<{jCgu774Wva}}
z*J%oM3>Cc$k?j1K3%OA@BuV|3PF0BWwyF8Uw=JR7lBCbSLj&kH`pxN~ClRLRL&MAU
z`+)^TxO4+DNomlBetvp%xZ#?0%q>~w*Y~AoLYU0*%lC#Uz+sNaLzY*T*JKNLjf+?Q
zhB!*r)B-o*YiMvB-KF;KtC9pRZUWs1%SYB@pNo!8KA~MA;p1A^<9F^d#rdFabYFGZ
z)cJ0dIMsUk=RwH4x`E32{I(UI!*1dtHCYr}G~4=6cI46Sef+rdXF+%JTO@@}YFbVk
zy!j05AO0yJVLl+?qnW7+BZFv3j?QldJ=fgGLU#$AKAgmaKPCO`xpT3#v~z~*lQTo7
z16gv;sxx98!tSqR8Z_B0rjfFkMZb!gkN>5~)CyR)M4Gx4?`Da}jw}hy<PtQA9mc2U
zRETK^OwtNZCu3&M0bNdJd}q3?7BNa@)mK!{gdMTo&J{)6Pl6=l0m^uiD!GIkS8}@g
zDkX!4=e}a&yROy~k*#W<`5Fw`qEp#DzTR~l{a&grGaXBP`6nW~3w?-8QYX&0&O1dS
zZZ5?0qbdJ1N}3d6RzGZ&|C|Og1rNTZwM|GFb)d{c3;rD5T@b_R8QJ*$u2Y1%?TfAd
z=ehNLC%<3gxMbGN{9+P6|JPipGH_#NbH-Bp7#?g&q$=>WuLkHT9y_)$w9C|i4Z*^%
zI(gvk;+Vzh>V15xh<ujj-ccrVKxm<bpFQ%5d0*!b@1%0p%Ss)1oJID%pDe1JLe{!L
zkKMaCW^;~zUkeCor+C8%cD4uzHzj|^@E;2kaX5~2I})3zPS&RoQ^e2DueDr#`*R4f
zU%iVlGV!HvBC9LKOm%Z?k<sZ2IBuP0*Q0%*4<B2Q)%fBzdi?(L7YC+w7G8hS=Yxr{
z#XCiyk1S^0@hmWDHA23a@3*Uo1fGUoR=_*@WmE2wuSsUa5^KqhUVoDVUduSFB|Nu)
z-F$UJRgB*?R5p2dGDhmnraD-Wl9cj@P(udmkd%s-HGG`!+mRRIYOf+XH7%Aa&iy>b
zvZd#g>v^o5XsgTaqAit~{fQe&EB(6T5z;o^y36wK>f=tR?;(SX@JNxOlvHR$X|f_Q
zqJ+?HzoZl$OlcMt5iR1U{ZTnCCmFOo;p#7w6$-Z8ZS`(qsb?gQYjWP8S>W%Ay+USD
zVK;e|*4uc>^bvWtrt>FGW2}Bk+v~dK3JxJA;O}bou4>+e?jau!Wd9O+JJb-pofOti
zKD!a-#-Ujodt_ENl5`ziX2uPE?GA-kx>7C1-8Z_Ug*>|kx-?HCpZ;i=RQ3RPX3S?3
z2a)+=bk6nv=#+w)YH&9~Vz+ppq$<5`pVB0X*sgXcBX<jE;Yq*g9bu~WMRF2s40fFR
z!#iYg9XKiuiu-=BoabTk7NVa3|HD-Z(yBoPga%z<^o=AcAa#e07^0Sba@huWmJC?9
zqZap>Eun^OA@qgtB-e=tk>$~826$~5-qknj3m`G{jn$BD1gUQQfu@YG#!Q}t-w4~O
zVU|mnS|D{eUIE~5xAC(~0i5FHo~l7~rE7V<T8=`>NtgxZui*kFVIZW5e7w7mo-5XN
zxauBU9rVk-k}Jfl&|4+9u}HTS!8nAb-t4Q-&cOh|pHU${YhX5l`DzeddyJu!zGfME
zhQ0Fq2#EP#*ATIK`lhic!yGxu2z&M75cP}&$OEXhhz`1J#IXhU0@@w$3dLQr{QINv
zB)5dp;H&%8b&#pLDWSNN-}rf^!z#^8Z4TX6)I%k{qY3wY(rzPB&qE*Y-@VPaKUwhC
zy}v9=M5rQNtj-RuVjJBXP-n0+AXbn>Y$nV2rg(&<+U-D$^~V^8HR!$u1JbJo#bK}c
zTCYsL21k&Ow1!o+rACZ4#ghni|6ZfjC&)e8ZTlTBV|IT6_KGgbAN7j49d^u-<`o;#
zqwPS*{?A_z9t)Cz@a3<ipYVJja=(WfF_LNzIwuxkAKDVks<9Y(Q0^9P-BL%@*qu!k
zCGA&fca=OMl#XBqWAD?H^p1A<U}Y3!yh-{sc1{%rUX(I#eevF3y_&tFReBH`GVRD3
zN@Lnyv*0Qe5o}lLvxQcdLp#S;R9PIA&si#hu?_^=guUy*vZzxicLX#xa!Y?}$hN!r
z(<xS;WpHB{vlIkV9k{lcd+&oYQJZisZ03rr%{L8uB|mDYV&^b?m33FkW59b_aXFh+
z=RuVWjtE9XjjTVN`Pc9xfit>>*%;}gb;96m6fYdiv!x<a4qJq6;@<1vM3fS@vt>Sw
zOyy=6mJM}1C3mSjN}5XXrQEpDBTX42mF7?fNwd_A?0dH0Ra7^e3&yWX?on5C+a$fW
z=>~e{PXW`CrFgo**TM3^A*hPDDYTVxIxT-z`6*r(P<c?uaQW$N0+5fl?Pb&Cmx5}j
zw!ih}2h*Ys;i??{?G;ORK-$*t4GC66(Z)5yv7=jCX^_oif1?O)L&b8&d%@}54K6{M
z!ZkzZrIX;u7eB&gz-GW9WKd#Y{rEqaanMG8C`qc9wbxX%hU<n7mjSOB&kUQNcAV~P
z25(3=$2T|#H4G<)np{;d!a-&##$aVXU9maN0d-s9qf&IR9;(~j*;=b!&U$dz|I|oe
z0hb>;eZ0(5RR7bz2HTjc7yrY63c(Agr?~tyHY!V)wI4(58X{xA-k#t-6j_`P!zc+x
zI>2t@_G*Ryp1=s!LutahpjlIOPrDM_w(PxygU9`Nq690E+-Fu9o%k9;V~t*w;B}N|
zY|PK(5`uvapLVJOu7m4PQnBqmuSKMh3I?VT3Q}KKU}X_mz~+a2XRJrrMMcLZJXvnj
zQ>`F2Ml)tM7B<%EB@K2#C4-!;)&(sj)!=<}C_XsR(>S;O0EeAMU!nQ0gXp$duWhgh
z>H{t%%~u8Yz$@PEmN%xd{mRJjrWJ0J@^eX6`^<1lSCrbo>~Ng{_HdmA_CWU%1KipS
z1I%moHX0L`HmCQb8zxtm{#jQf6OuN7$<H=a6QMStohnzde$6&K6OT4BlZ<ub+CWj5
z+P|U*wdJC4*D4<qOg^u#I|dNC{u9XE8<Qmy#HN210@u$CG3oyYaq4%1koN1HV}zGM
z2>Wj!uKm1TL?(z{VkQL7oF-b>s#`F<-1Nq^hfZTJGkQLZ}m!1d=8SLc52m=K-C
z2wB!c{BP|GOu=a<_>!!bg`bOs%EAe<ocozowED|cF#1KZTf-N!Lc`sJlyNFV*q%x>
z<sDb3Q(U>Fi=)%CZjpb%9bivz3RuTH{y=ZNuHakuU5K%RoP-N)^rdOI6lXTI8nds$
z*F_UKh_HZNh4l84rkI|!lOo?2o(wA*<6E8T)%BxaA3jhf_I<I+(_$C9$3cW3Qf|&Z
zqUXPy;5TO%55!w#L>>TvHhz~Z`gTSE0tilFMz5=%Y-H3JDd+D`7t(_&0<KM^p#~*-
zeK*a)<lajTzgNC^`AF}BG_Xp4^7Or*N%KK#pn!hJn^^F}8<LYgtwr8DVlFZ0$`}3A
zV6eSe;UtnJSJuJy`U?n!vd?Atv%a}#%xMOr1L8Fu<Yc>9!5vLIe=0HeO}p{GW_5g>
zE$!(iNuA^?m0qi0x0x5lmdo<w0$v#%ULrVSA7*+x<nft;nTIgWt1!-YEu9B}nHPBI
zyQKbAx6d>R>8|jbufE^=vvAN(s@h!%nS9$dGh0~Dmr1C>Fm?E?>kHLeQYwHe%~?4q
z@AKLnGF{L}R{$=4VCK93uZz+)eg)^tjmuO@cT$-i3u5%C-exgzbLW&>&+j%uNICgz
zL+_}q2y_1lhc9^vtfOs`89u>_{uPJ1ZRgq|26_47-M&!UC@+Q9uo;W=LV_t!L~vbc
zywf-nYj})_dO;tbQyU)S^O^ioWQ~9^Rc~kTD+(3$nJV<lHcamj3NkJx4Y?9ja2vaq
z5hV;4ATJo@Ah?avTY@5s3s4sP>%jZr2+dK3Z~=;f?BK)j_gu!TZ&0`ozanQ7GmaUb
zLqIa8fl`92LYp=DR{^7lU!B9Ul-DqWo-LkVPNax-mW2IJ7}3tYJKsiJ({=~+J0NFj
zM-htDnMk#5{!3CNRb=FKKmLZ!Bd1+`gXS_hcI=QKHz5ySgPFM@sdyA+ibgfXyzMaV
zFbS=^jG>Il>UTrVio|&_CIoVgd8-m`jVHiq7o~dhvoo-hyR*FWsq;rCWhZJUMkjn{
zVup4k_^*YfE=E<vqWEb^^t72pWW)W6?|E=a)v0H}hU8{-?tSJPou9NHn;+4;;QOa{
z*LRXW&K2UikHue^-8e_)*hEHJ)wZubH%g;C98(HBJ(a)sxxCUu#`_MAzeRsb{1*1D
zt2?~Azk8?qsT;Gxe_@!^%C-sfXNgUXvdD-^EqGNVi(iGqJc@_!2!rrb3hEDxMXZ=l
zAgl|l92B##yYD7ngpw#nQTWh*hav^bgfN5=2LA|Y426WL1pm7|@xZ%fI8>g>jBon6
zG2RY;6Ei9zbQ#!Qabq{pCUzOozI^TJZQ||Z?ddJ!T?ZY9!d?S+7>78*jR?B<eEnV`
zpl3CdDxVm`=K4ss&9=v{{I5!{_O1f2%C8o$-mW4XTmy6B(&Dn>a^m8rS*dx9zx9>|
zkD#LC{-FPOrE(o;s6}#fIJk_QI`6zm9y9jG#sxlamU<`NvJE#eZ!UU2-)0Y|W|uND
zFfcF{Gn&!yD~>CX#|bh!I_(7ZYenecJuv3TjZan|s*dMoiHZ8jyqP`n++q!jF~9G<
zpx;!FcJaNxy)fRG6HTMj5z4X08GZ(S<Ixuj@7zZmoy46W7NwR^jhTtupZz_LemE-%
z^O)&B>U1nnEOm+~I<rc&M$qw2LtuKhKJ(nAAVz7>S^CCtcSr1_ALV=GcBJ!;Z-4ht
zM6IiON(g)yE;5}=SY$bP4k=Vjo6*HVXCeHvuka*OY%Pq)d4lVuR}!vdgd5*v6g4bz
zVo>3{e+^p0jo0c<PA;%kE7Gn{)^e3Tb&HOiag(t(GWffA381I~FHr%h!WXR<BWF&B
zjxbE`WVl*O#oE-nGU`n35DSOgOActXb7F>d*^MellP6<O?@61BZ30Ogk)sS=IXk1e
zi8*oV5FI<LgnspyEn&88W0M0<eY@Moe_gYVtgDJ^+eHqqz|(L8qgY~Pe`Sw{SL$^q
z3q3Jwx9(q*ZI9Z4*2v@Uty-K4SOi*cl%zI9R+G(X|M^O4v&Rf0m4WoB;xSHT_Iwgp
zQe}Su4RMy2s{D2nXR4;@22YiXhmO!q?#{WM9`%JUx{jNVE;H?7X53^?DNJKF%RKAf
z9DYRk@}|bz`$6fBuj9~?^MpZfq%%C94LBJ|!ae$kqs}#stxnW+;K_{1&H~{b@Kt22
zo@-Wh(~}K61ZhODB8S;WKsLLh$vDdk6b}aLKQ4twlP}WF5B~fPWm*4m#J`+;;n+&#
zShOnA+E%sLXFEW70TEr>y>mESHTA0pdlCMHs85v_ihREje#Kpmw6>i>#93B!-T$tA
z5j(swp?^GS?lamldoN+Mo(uv%QAP~=9)p~#-1{AiM0Q1;XlS0>79pG1@v$<4uAoQA
zj3cO>*!ICcw9q;({PfGUjfSvh&?k%V(>?yJ3m1Qp1j-8Hc=+{rF$Xs(Oj5G=p!N9Y
zW|4QmMdJi^Q&o<`>IEu}?GET}IN#Lt4wdVvpV;SjJ%*aFOfI9FRH`4h(^r)T5;~ca
ztHRaX&~%WE+;5YENn^X`Pk&y;)@(PoT})p^*6w?*_-0;h-1*N1v`26j^p|Np4N16|
zWMZ#pHRQQGw=G_ei9cXe34z*^ML_Ui7L3;4f7|K!+MrP_^&>sgJJVXd7?)RWSM@ut
z95%v^{W^G)yS|wXQtfcanak?ds7{pk>7>wZM)T~s_LNKb@O72`@@BGKZf=~6?6o)?
zez3`RBxVV%QpEdwre?kNt(e0IyN&Aty<8%5slCE%oW}$aJ!MzfUVJxi6~{4UA<ESi
zjdc%8D_}(@$@VDi3?SW=eX(uMpv~w5m%_;`x8nJ}l2@BDdRV*I(7>!wM8&-AEwjTv
z#@(Z<uF24vb=*<U*lsS|dm(%7z@_;K<u<d;DW9eKW-Ks{h3xG|B!`2ZLjc*X(Vy4$
z=?PdvH`(>mi?7YY(f5&U{-XnoEZUiK0*bi$$1%P17oT2JtS4q=a9V8S>Z?=PVrH5K
zbnDk9tW)eG*;@*h7v6quH%^Ya;yk*BdzMPLVMY*zHq&0)3V3#&uQZKLg#2h}nYA)H
z`&z%!VDB<_G}9%V@LOuZq(P*u%JuM?j~;lqz=sEvz15{^&|2FUE;g8?uzYUNqU9co
z-v8-E>$F}Nu7CLip%6%1{jb?cR;p73S5v4shHTxXchCT*#Zs<vQ-H|ncVb1SqwKvG
zlFx0$y>E2_%eu#|Xw!z?ny`)In5`r5BE=NvvD0hsK~Jg)`b=wjC%p$YI^MnHh#s!8
zOM2~&mZNGmHO~}b^f@{}p=$Nnq7{1jB62ct<YRJo&GpoBwD{WWbVh2Mn#pz9OI*B{
zK?TSr61Dbg&3p<`sB)!`4EH{asa^+RJv8t7#;)dgt^1s16U09g&JA~1(Ve-;LVVpA
zpf*-gln#e&L8jGw<`hmmaecQmH)HPFIj{GmR4(R$Ksy${{g?z(JA1){#xd~4+WUQ|
zzHk58u6wk_>+{6S6Bbk6thu&W7fQk6+w%1ct$;|v6xj#nXm%d*T^Kdz?E38e1S0qe
z9c0fw9z7gsXXsiR$+B*9osb!A_*ZB2o7-;=Z5b!O!IKszb4`r&B-d=dU+TpyC9T~5
z_<w&LNq*HQNvBHBx)_!7oxopCmNXzqCrU5LW}!6=DkI7B1l@fvX8)Vcn0}ISM;Jp&
zFs^rQw1+mX2TtDoC<*+j&-LLVy^C3BS!jz1oQh7-JJfBmoxx;JPZsYdOF{Gci$}7i
zon3OCXKBWsg<_n3^4hLW`}*3HZ4g(PKo+uAr^=7I-YG-j8J1jqBO0PK6EbQz!RdHF
zCtWl45tofm@0HwKp8H2PKZ=MucDknLOzt#?eGLC1j!9L8{B+QX0?^4&5!<TP_(cKu
zt@e8Y@qqVn95S(n$2H#aTu)m^H;<Uor;pTD?8b-*PQUGRa^WnwHo?&|se8<^egbkc
zLtWxAe^Jkn!XZN#8)@hJ#G=LC0cUCF95Sc!Br`**<zztc-x=9GVak<6UiO3M4~KMT
z@%+JQ4y1})w9mlqc+cEFdR<p%lG!A$A}XT-Vzui|ombP80PhPTzdRW%MlM8dbn46z
zcPQ8Ad}Y?<m|@f9SmtaMOIC=SsTew%FunWn;p2`Vtb8H|&m=Q%tPLW%96Un0T@BLp
zIX}MWR=Y=W_m4fDqZizdt{2>kj7c|L8XOkfpLANhUQ}9i$ix!+Sl1iYDb*XY6pQ^n
z;__S|_R*?0WGwbuTqg$_MJ-;&n>h2VygvxeJax1I??V%TP4;UvAFfb4F_i1cW7uaf
zYu#S@lm&7yO70jLOrrKGt*}I~@Lm+0&Gi&hdi~84^v1eB2Yd=ks@AE`dH+?PQ!l97
zRi;{R*lbd7xc6~-`y~0Oj~J`HCCOxmFUp$Bo^rSY?~iBBX*)9Tt2k6*7B^!kt7k*4
zW}ez+cJ)>kX>{Ltd343*IdtDWE$V$eZ9req(v28o2gHt3<!8>X$Ij9&&HIngP4ABW
zET}i)0f&|nMFq4Of|Vc%N4w@6(KAFr?z(cJi)S7dLkx3<dbQVo%Mh-}(7$>rn*t5{
zmj3%i;%wmWGp15IcP0z`>&STgd%%}Y5qFBu!=gIs8AsCnQ#{pQ?T-B{roml>@<RDy
z{P~Jgw>f~2uMt)M%H8PW9&8%USZa0saOxD>pEShVZ!gRb5;|}!YV2WrHL&}hOP^Nn
zyu@d%kM41-PcX2pNrwCt85ZBH6Ud@>zXX-~Njd>*(dp)0Y3+C+G<N)$utT1<oB+m_
z8Nnzg(G#P%H4AdbuJ_s3x6<cV?fA?470s|u<&qR?$Q|rl57-}cX$>JUt;sR1(J`&r
zX%ziu_)$<qhj`JOK;9e}!$AnPAxWSWWePG<ErOC8QXNet%BSDTKY82}e*c@~40QQz
zU`%&9>De=9Lq~=>RTFV0O+40VzS$?}nvxxIxWsWrM9g8g6m&=*yBC0(z<zuch#v>X
zsfH#`?XEV;xE~}xt30cGm7uA~jFwo0Uq-1E?<wD596hgng8oz8uS~2mkunjf*Yjf%
zg3mA4SG0Wv;x#12A}b;)B>FFrSMdp-|Bsl!=gidI{Vkg6(TW~=!$j~e+}z$0PWFcc
zBeQ?Ax|S28Uu=^bD=TLWEvH7AD3W8&eiW6=CKfSwByUu<&uSl!%_hZ)(&``@!5b+;
zvhAA(m!#L{FB2$dsHQ)Hot{^rBJyHT<VRWgLyVCtr)o!_Bkh#w+OM^K<z2H~GfGZ7
zF1zg%wfQfjw!mh!ED;%0AOaR?QIz`EUrGE5x9u`QK=N1t^=M5>{@Ezroc}a=nQy#h
zTH`12q7`K5b2dwDG!GD?%4M{CgVZKU2NR=6WiWh!Giw%;=%lt${4Wf^?3oxMZed~y
z=!A?pkcY#@nXmOmFX}?Z&9MK-_U=GBx>Lr;aNND$J(x%Ui6qGV-*xk~Acyf+%daDf
zq_j~u?MYm-#3LF}GlLd}EAE5tp{ZPhB)jfEP20J0Qh6AN@t{?MQl>Pjd<-Os?jEN9
zxYA2VG@{Ge1G(1ICRs>%qDWr&O;flcOUUY?mtR~>L0qZY+y^AL&<~m%Q`l-7R$jsz
z=0UPSvi9=p;%kPkIrlO5NNt`Jk};^kAet#+wOzYy`@|*xBC)kQhG}+f448L=Yh$}1
z$}QT>!`3vhHo~0vlH~GQc<_1fxgB&Ja1Glv1f7P)fq4MjfSm_YDl)3ur$NR+#`b{g
zvTG)Li!(0B)pL~3AYfxy(1Ls~I@&(k-UDwp$?@-|{l^6Dw)jK7Pk!Bk)-U}7Kf_Z5
ziC%{%>l71k)3pi_%JMXW!J4{Ewn?rE$VFkZipQpOB#6-xGRDAgwQ)Iq1yUxNpSwSR
z?P@*E6V2<*lH<Pz*9U`StbtWC8^gS<#OqOpGE~4^u4!VMPkf<dswBWDuEDy&KZCb}
z=!21iii7y38Q1@~=G+I;Oxvx-1q^uzNg|`^2h~kmYG-xW4*1Du$Q*6#xf)4Vqs|90
zO-pLWmTb@XFo_wXE~74^siLUXMa%|-xgrKz1cNGSkbmlVq#p)0&Aw+PqyE}g!r{}A
zo$7qYdG3GhL|a+JHeE1dVE91@=22PeN*PA`XHxm8Vz~UDZY5xHzDkF2G3ef0(!rH-
zh@qCmhEi|*$G>|U^wl27zrHhKk&(%*l%F;{tCOyElEYahhYn4KcdG44bOb#ug39Hr
z3vnm%%7ujL$Yq)Hs-&zKi8AuLpVh3`8xmXPd<p}Gqv9FlG>VpIB`nM8Wmdk}Cc4Ta
z7XoMHk1L(yy_$O@+hI8RBd_t-xHHG}4>47x7)TCJoeiVSuR_~N?E82;H~{`w`#`8W
zAbn~F9g5rexB4*ikzZ~v5&8)b%W=RGzufC~)$zh9HmQ1h`;YGVm!e7>`slzOx07^B
zxxONZLm*ji_<V1?*|&Q}yJLrvdRYV{HUe;rO*kWaARaY@T7DiebPSS%#E>cdQ(fDo
zdma=G_$QD;rtnXDEs@S^2!nQ+(N1ur(@{15ENEXQ;f&yccVxp6C<lokQ~qba#`ERb
zq@|Y5Yd}=-pWB*Xg3nG4?XrL!j2!eFyMM!x7W=tBTKuD}uM1t~YY5;@BK>EER!GOu
zioi(2B|R840y5ChZ!2zbRdze~TyC%qwFWDJLE8FlW^Jw$j^`PtEBEErU~e!85oA!^
z;>zZH?z!Gz{Z)5{$BucKFY+uy*0p1MrD3VzR2dAS2N~FZl=*Y6d(pUx2JTD-`PjEX
zs+`XCJ_f{t4c1lGU|}%m9%OLY>}u<9?g?(NPP7J_fk6-YZH>*Y9hWN&;b*!ERVmW0
zwsdU(hx3(#mHT{auqzl8tKSB2JzqIqxsR|0vx7mZ25pdL*K?QimBYqWUvTG?{xfDX
zgu?k;WN+o6#TrZmGLY48>vTRBK3Ta>wg&(BXN|nvkg0plxqRPX4R!>B?DgAJnq7T9
z1kAPuGl4;u25l;BuCH4w_dsj#PcSG~ziqO`_4RD!KGIsd(He{h21VMn8T?&h+z??s
zyZylN1u&W9#<oEyXxmg049tf?w*?ChF}85h%b1p=ld2C_uI-|i{Zt2{9`+llV!c$m
zv``IiIzLkLikY<Elm|vvv@eRjNqz&d*VT?@PocS6n>UFsBJ3Of9vSc5Q&&{4I~gi!
zjRqN`*0-&KhYkA_?y?*3=AD3cs!3n?$IpN?vB|J2MyR47xFecp%c?W9djF?4#iaM;
z6~>D}XS{vy&uh^v<jq69N8~p>OBYR<e#EaQu`o%SLz0uXd@ywu`$<d+!-#u&Yq&Hf
zgpMD<tDBBlK|HX(WG7?y{|-xk8*2y=l!@0L!hU!=>`4cw5G>PH{L_x<OV>$sS>_;f
zqFhcIU{)pM-`?)$Pw;NjM|E!btB(i{!7UU|n>zU8SnT(z>uN9-wB6(=lHAp6)Z;U`
z{ilZi_R%{IDiOo;$@7fj>yGgo2Jv?CcJdKCsya30*i?@bdiC*)bv;G+gYo1+-8J!_
zNBysZaGfx**TO@~=+;lLl#)x5+TS_O8FI-Pa`mrg6j(z5>aB8$AkP%$8%>GH?EBp<
zA!4klUFJJP&vHB5c7#M@G?4rN4?KtIBtPEjC4qkaWI)RmGf3^Q56&G!yR3TG>K;Sq
zll_k8J(~{Nn8QFToHoe5k69<$8r%?vc<ONfgb6a)42iBm1=n8o5V}(}_9E9{0D{l2
zaL)W=jXxL|+qN{8FueZbI175cA|dw=azFuu^<5#72XJhE@kSilvKGYL>_&zDXjem2
z>3MJ<_4VhuqRk4)-6DVabhu449E$FM!){z+I@_V{Qx-7)y;aqUj&IO=$G5EP&VOFX
z6Z<wijI+&xsUbmE(YCNLO{;!L9|)Y6_tY6p5;l#QA>fI<n02;ns+V11IZuQr<{G;?
zeix?mVW&vxjEj*oG67vDJ1afu3bXsrW^VzG^^WPlg_ngIvk$YD$H>P~ceDpIV)BQD
zxkb0L9O{kE;;ml{dQtryBmRub;g4%*UhF%*7#ijZ<azIjZv-~&WqY`d%jN9#K^@-6
z{cvs*q+c-J7|a;P9??3Z{f3)vV>!tl(=PXNuMA!^Ix{bO)_zfKPKoUzL&bf={n$4d
zO2$O?V)wIe7;o4gH9VTyWj9zZ6CcKMN09e|Zm1vsJl4E~cuT#h1DO5jsS>+VV#hXz
z8Tah>6K~vZm>#_z>tBMrW!}^PEbnx=iGC?lV_n0`H;9h~-tyNhDZ0{C<r`%`G%nRE
zD%>jg<}<9=8X7b57u8P7A4>1%y%wIV;2ZKib64bSEBVzfwKL1HN+;%#7Y<H7whcEF
ztti+=``KPsi@v#Nij-khq+6LcM6PI^7rSbEm5MGHTG=<mu4tc^016-<@roy=C*NG+
zgmrxMDGC7jm|D4-VP$;_I42q>a`%=lNy54mKmagCD_3i%Y^rQ`;cx-<1pP$nUfLz$
zDM9#Wc7cjkN!i>&>H^7$l1qxPkwIQ(F}tRbHc^><Y2<>y0{w~JiMmUAtG+=#NOSXt
zc3H&&--#}tqCp8rds9uI^s=06LHWe&UeqP>sk2q<_1k)}Z>gQOn7UgjRfWic>b${8
z$%&myY^(Nq$%VF<239HZg5=5JiSa%9efU$6r{=4IXt8e<rFNH^YUyS<<HF^<#>vBp
z<$cyuou}ce^u!O2QlbS#!z=E40+&W%+3bqW@<|Q9?^C5><>m{y-ml)V(5Gk0dyFg5
z1F|EsJ+d>eHG%$zVEfWb`AyDqHCum38vl2)LX1U9aHz!x(|LpOii2%1B#B?$OP8!D
zdU4QV>I3vpenoNRm+fDEt;}L&u;HSa1y94z6_ynn+ZcXrFRjdy39#WDp;fhYWW7NB
zz)I!{?m3%nRZ3CS+@kfR1zEjYL-Y#axz9PgZ6+kY(coEbHQ%T5d>%04YT4E>)xc5D
z(NJAq-C$pTS%29;RnM~$yYlm#@jMGs=W6&YJ+{bhmFhg5&VH<)>LUGcWOO8Z$8isQ
z(thH4wSH}Wi}sax{~=c9SCTv11y(&3J2Jncy03dueG+;#e{Fw@%&9V(<~T`x*)sPX
znR@+abnW$0zIhsZ`}~q&^zi%|Di*tWhy0SV2@!eA6Wg0QjeQ7vMSb&rlk)TRgMG(%
zqkE5j3w+Cb33(BCMt?TCQH7{ptKO^Lsy=j`<!<L5=kEIrh^>kZi4h&HlhGd59O=(~
zw#*3T`I1fTnGW7**v2yq1Ba-3XuQFkZBIN(*2L0mn75N%A|Z3Ci((=_3IZ@Yx9}dN
z1OvIC^w5NY3AMlcMr!p!GBXF(ok<))yS%r#aV*0GB-7~(^4Cm&l!CMm^r5+yLhhU?
zQQ2iKK54cgm06D>D(^lY4*7&jf=ykf>Pyj0p|Vfe23FFC$z~dNF+mB$a~k>Fnn5xb
z_ufd3_55wh<?IVd7uTYPdIutiQ5QL-F^%B7+zjl8a6UK=GtP;847-I1(Nm@z@11EZ
zB$KZ@rLo<_{al36K@ls7pGht)(NP4beamfS)_@&h&8n*kFD2op^`gPg*qdO0<jXga
zaA-cH>WeADK%<PDjrCrUEeAGL7!<TEx%SJVe~)^Qj^UfqS1w}{T!f(OKcKrABYZI+
z@bKOB>}5(y6^E)?fZ;9qdRl$8^n4!k1W0TkrP+?YYm6ja?!|Qyl~25cu$vq19p4Ow
z2-9x(`{A5|Vw^clqS|oRon&LW^a|U^M>r3Z`<JprcC>oNCH4s7D<$^u?>Q@=%M(n#
zJyAQp;|#^>04|KWh}$J=GGkRAxx2Bf<}WTWF%hk0$j*vQF0xoB)S}gt)nWGtqPaPx
zhhX$0fg|~+XixE1hK@MjIzyc<X^sM-g-8RQ1c1l6j#WPiK(Y-K-nw;?X0^wqMC+jS
zYrW8RaRUf#z0bgbXhhX|)%&cNuk>W;SO-V7<J)(=E`)n+pQKs$lNr-)V@Yq6Hdh!y
zv7|Oyl}yC-Vd!gUwrV^psn?{y(SK_WD%tSO&wqM-858~&^F2m%T)3~QlI0Z3(gwzh
zvb<K_294L;z7{J#d0z4aF;?EE@B^unSI(1MMov|(Z`<;i$&xoJIVXOw=hhkVNZK+m
zxUPd&D+5iVWs)szkm91-hH_`%KTOqwqW=guCMv`UrEjzGC&coTm)Si+U#Q8o;S~G_
zSj>~_SSzzMCTkJ)+nsXuZ}Zx83J#g3EK)XaqYj0BOy9Pf)3gonjPQgIJSg3cn-+aV
z|EjoTn^Tk%U72BCXD-q<RX0`_$@g$}eP)W~0k|dqRmFK>^q;M0D(3~3n#RKFlGDBG
zJ!a#e-n?E^)h&aUVy#<yQAg1-gMGO`vMuDt)sO!!Jy<+gYS}hMH%8BV?6vH*8W;4|
z^|F1os*bBh8a@6GPj3O#M*F>gKP_!3P@LjY+@Zmp;_mJ=Sn=WxMT)z-yF+j<4Hg0v
z2@<S$aSsmve1G%KyV?2VBzq?_JDJJed+u{xhr5U5NXi-cXj@%gT+R&Gc06!|czRP^
zv{_U63Hu5+uex*)*!cO^`PVI(ni-j)wyiIWEyPe<T%TWmT{oXU!xIk9`fZ3PIZZt!
z@2*sUqa;_0R$gZq9?V|-p853h?S*ciqHA1vFl|>-sO0&R{T`Q+8(>o;1QmU=OK-*K
zaBXZX8kEcyw>n`5iqe1nDAa$3?liQ2DLJFt4Y!*U`z?-U;h;n>F;+pxa+mfRf~lD7
zTB51mslZ&iQcIxgq!G;|lLl0Dp*LVIO4U|mW>&OCCIr$0pq|ZYiyR2%<q1S%uLITc
zl$ZtTqJ(E;z$6xka}gIoFAV7ejw~)52|R@7C3do1f*u(I<6odtmuB94{R5mAN-tQ9
zp~&?lsDu)9==Hx0Z+Z8i_DTY6>2>X5s;O$sxcvYE8sWn)rzkki<|JXXOxWBmZ$6sK
ze1F3$bLwfCC7|jH5<}iS6ZmDv0WDl=dxn}9h1!xF@%j&bqne!h6d#Hz(NE5d>TncL
zlOE<%;~DH9YuYmFR5QQ^drAS;6xa{4xA_-wS8*3{h`4jnEwaO$<D4x&82=Ridiy~8
z_)V2_f^&m&fph<9;c4Qj+xpjaqLZTls}n*uw@E0Q^-QjhHnc!bmt}n>@4t41362H(
zIHLx^NX#nJkB!#XmDVavPOCv6CyaoG2f{nThqWvA^WGgJQk{hc{}F$)hraW?vw%b4
z{f85Nd-5o{&MkQ-GMY>OdV~DhN@fq&1_K>;$5%LRm8fnHC;tI|{--m<f_L(9p`a)j
zQ5i_&@cUbOL2u-aVsUGkOIiv`*=wm9*1ux2W$u5!1@R^}dDsPq<X1-c)pEj6KZ?!}
z_xwvM?+El(_r>x5SI}1Ywf^?=zf5{h)c(`J^(XVc5RXsWzhGkmp98i6I3;N6HPR)i
z*Im~Q<%iNBUg~2vy{F_YLjoe?LKa{Oj3>Y##}8^^@%4~Bfaysv^P+FTFIR_Op^dLg
z{_Zv6Eni@GlPzB=>Hl=R|5!Wh`9wNzz8r{R58w*KFd(Mr5A`6X?vJ=8rso_GCdL<S
z#JmjiUi{hlEAIP$m%+gA1OY|A6k`9px~1H*d~H1~_*7iH%=tW3^3o^wld+~ai2Md}
zVBCco@ls&(;yAT?+j6k8b{~}gbb0TPG=6zdv)T174?EiXO7_Ak+B_g70F*d!;TSHk
zK9#*lgQy-oT{Uz_OSbRn@$J+Jnlg25Q|mO2S??!8+xrzJo=g<g&GanK@OpFXBNlb$
zdmt5gdu}RfA=lB*-`{iB1UUdypzjR}K~sa)ZJ6wfF|DEy)yCNmZaNC-{>jWgOQl_?
zBD6JG7<E!vlwf5aj&@W^cQwhXQsyuhuu)2>XWrX>AV_2D+AGP_ey5~cwo+C#hpu#;
zcyE!FG$UY}%p;Y}$ey0AWM7IoLulLGq6FupNRL-wEaRT>!CIl!B^D8L<wS{Zf2t*3
z%8W?+w3J$w<e#YXX(?BS?hdCr&JrVCwVA#<&yrO)%F^Bwb&Ri;Ypksneay3#bS%DB
zXiQl*$5PKz4cxA1O1)F2C^BZHs4u@o)WA>*^z)z=1@#0b*Yv&{<6RS><MdWZChC2a
zoY9k>*nwzNSW9A@3D48l!09a#0OF>{E~ciHLi-7TZsAYZj%;y@A!!m0V-T7);0}%v
z$Ow12Q5)P=D*_bO)mh2<eIo6jx%xA6>_qkmV)x0@f)}?NWEd%`|8A2`7uAKUCgwJI
z^G6us9c~8m=7%j#Q#8630=ai^X4-lLOQd}dB^bl><9YEyjQ1EBDjq!Cp6Haqfzpr<
ztu9OLLZa=5r5l2DEMieInSJq)&ZtR-&IrUW-)0%3(Dv0i*<n0A(P3|blWxA^N1}cS
znS4EhA<1~FH);E=vjp-K`ICCK+3D!!Ppp%@8mqPsZMS#!w|6qe#<@qwxySlJqx}tu
zBQ_}+dx;r)$r)xJ`!0pH^FH}7O0SJ6twk}OhK&iMZRh!K=OH_3i+lmabvWyZ{L~=^
zr|57^zLTh(&?nyjI^lVxeEfdO!a6EB$9kb@Kde>r6HOS|=MkqMc)Dx4m{F-L40&QR
zvmt^Hipu}uk3!Kzak%k(Y39}b#Vvj=%J}PoeSSvJoxp2-17fJfJ^X7Ql2mQGtr#<B
zL>fu^<Rcc<4<RC38h*P~?1HujX6~!%v+djO%Lw51=MDgU4>aC0I`tcA|8-OET;iPK
z3_4GtCRs_u96BSe-nf1`5<Yzx$~f-++x@S*G<dkhrqu=R2KPSpaSTC(@M-vI7*(^+
zrrWc&q`{ZrERL;hvdcBc3s~PGT7JWEk1IWuh3oVFsM=Mu%yw1#T??#M*mu=Gcp%;S
zi560>@sN4&)coR%`SE{N*RJ<<zSX9tYO}2WK3*?hxj%XKCI?2C8Z;E^A#W&Z_Pt2D
zHuyjM=5qKAm?RM=+l%v;El#2mHO!oB{V&f<<GYmxSxEpRGd`_9XBCm`^+@T+fZELj
zsrx(~b{+;`-%j>N|F8A`#xJ{Ua2NBf@~v>L9=Gq%BsV|2+Wu(s{?nM(zzsdY$33*d
z7QWY8{xZkBv1eX(exC<zzCE-As7Gx2n?zsUsOL7wxjdUjUtTj$@)ruMCvH9l5bTj@
z<T@+6^hJ5%(mp<QMQQYYl(`;Zs>bFEA%+!v5!REOJ+z$`pAQLA5Z-A?Oz1(|o)EYw
zkqLy#1+qz}XM7sh8oTfty9iI6;)&07*6@$+I5Y_{Jfj5aFeP@sj3746P7{*)Xooov
zsfL=zqp;Tw8{;)@>$vL~O*Whjxt-wo_fa)M+Kegyjs@nu6MquFRg1;t;chE;dbN7r
z5vi3lKrXlH5HI`D?;9Y)pC7yg0l0pfYWhNNLl*pae-YSJmyU`OJ;R^jpVsC!%M3o)
zTeacvaxVm1dUi8RJ?)(3$Rl)*U3Z!C4JYjhxni>ECyXYvK|NX4x}RCI+jG3KVbE^q
z!S1RxCaBzCyw-7^mn;)I6MNe9q0>*1o-B9#VWy#zb0xkF5((!+YgZX<W#?u!)2qS*
zl+pcDvpE1C&`9s>(%P`ND3bqJlJp*MuxgW;YT*|S9)a=*hfW>Yd5*vlJbsdtp!U1>
znY$&sB{)1(+^7<x{ww6Kzq(Zl5?o~chT<lEi|1n;z}%&CBP8IpDG?u!@^k+K{~#i3
z0^(@Co_MDY?V0MqPM#>=4OJiXf8VPEC%1|Z;nH5Vl$=H<fA_b*n^bR+;03$7)!S@A
zylfsXz5CSl*ortZC`Lj=g*_jkdK&>V>j~28sYvN8k(d+tJ8wLfrIGis+Kn7$P$ER8
zy(gk=6LCOZDm0>%hhI5)2d$W>C>q$wo+{0rifG=o*MC9pyq9<v*YWGq8h7hwJMdG*
z!G)aP_jh-VgcCt{bK^Rf;$8itj}Y5=B0~?H)7|)&Sp?abxXW?qoh>?n>kXMv^Ye}m
zWv^<hLLq<9+`yDd(OaHJtpj|&R8|kxuvXSHR*!DaI`Ar)#|s^&N!8T)SNFNQln4Dh
z<A5Ud`o1&!=laW<I`?Br?L9r;KjJR_3wN_}z&vAGk>FvC$;^8<U!;!Md;8h<Fq$9f
z@$}-*=U!&2@;*Xc7VtWJfEeer_<72jK+jI=rCLblg!I7=reJBhDXRLC>VK}d>UP1A
z#Q)5FQNIZ19Dz67p~A%4ZkPl%Q7zWG-!!inh@Mk@`+0<HMi8hJ$$0wG$xb~P`ezwi
z`CNH2jT>`w!l+r0)G|o0wrMn&W<e2;33UVMwT0tzld(9+b1H#BmU;dD^y6*La%8)S
zU`L!l3Uyobs2?qtm&%_Qt0ENlU{m5P>DrR+ps&>rC!uAHEEjDki)enxBBh`B-$^Hb
z$uMwJaT`QNF{;KiCfAbJjIw|Z*g|18D*A5o;U2(MeJZ{mm|tlZiTT#p!df{j*J8av
z2E<K`J{X(q*0^9AYYlL*H2@5>b^&kxQyWv}Q~H$tS&1f{M~OO}OAAK}Iulto!4+u*
zZH}~3ao`4#-y7iBXya&2Ttx0n@PK*n-RNDy-!>KdkZn3z3jw=)gg1|^>A{M-6p>z;
zX}GL8Iyg0%I=D62UNmdAz;qV>Sf)p|s7ujEuN+<+`%GS3d!Uly<|8)H@kls1D>y)I
zkW#x~z5=uI`b4T{${~7j&i}vjS0EA~_mNie-6sSyn%_JVSfexFB3>E*NTywQ3N%~q
znK=c!IZ%?5Oh{<v6Z{*Ihq!ycHv0BD2VxES>A-CCo3Gi?fk=2DzB%QHt((b*P6}P&
zZRwz<0&<E>r;~A@823Ej*8kH-As@nee$d0=49>aq>_KV{P%pmve<&EJxLES1HiImj
z#rc!14`H8`Jkp7eb3!PW5~W;Ubv7Dns;04y!FIY_X*)YtR8MGbl29SPw*eP#e5yr^
zOqn>-7DmZ-9FbYQAO6~6%mrzjER;j)l8Ud&8Z|W)bXb^SX<dr6Wt}ss`^8rp?^u4P
z0w8a!SbQ1(O|lL4$37Y%_uNOLkVhlDr{&j>KRsIUyLmj>UNg39RnnKLAG5uxXL{WD
zCxm&wtyQU9s#0Wo9RM*@e)!q0*~(sG?dH0QzzyD8NpwaU<5@Ku%c@Fcu~dxfXz0ow
zx&&}6Bp;5&sq+y`@s&7mv?mD{9sLm7|JfX|qDC3%`a?vTGT1d!M3FMWmCe_V3!-r0
z?!yN$xDfHdh5Wq0^Pz|A{OiYLS{TpSab#+T2yd@4d5t~n{AR)~(o-uG;V4L+Di)zF
z(ED#kMn>0v;3MZfT*8+5T=7+El%ho0d&r<-v*tT1^tLZTkZ47#G9ieaBKun#CWoYO
zMXgkoMiY3ULz%mJS0Pl}m+46zq4AE1m?-tvqM-m^Y7#`>>NVsXLT4oese-UsQ9?Q)
zl2&MtA&9FLCPW9~YsC$TgXmhJLXIIER^pIe2=xvVgcjnmLjXyEknD&++#oUuA6966
zdMHuKPMSnISgyiEqVhwSQbc}=jxojfXo^%Zjr*|pvXs<rSM65)Y!0ueub_t9=QHH*
zGUfOf`Un*|?2TPreOa2A9pV1ZDrm}l>T{};D6Oc4M*Ml~jk2WRG&hVJW9P$^@swmL
zhDeO)xCX~{?M1Cz*3QzurD)d}n{FE-NM3$#z7!L-cf5CeiO8<tzF_D@%U<pt4a7l5
zvv)uzp}K}pQ46ywiV1&?uJtoS(hk7;)=Hr@*AUk#+fbn{yt&#?sxF30s;+@gVoBby
zyiIaR(y_w2_^8xV>!I+d455cwLSBibBUemb6t6K-LSCV&T~VA{JE^``oLk4CPE=xC
z%AuoIWL#xkMW*4T-d?$^;iTnN?Wb{~i(M(FPN|zv#i)^wqh?YhQe*8$|JU@)7u@R5
zFlFy6#YEv8(ouZC{+E55J-j)xy|kSi!nMZZOrN^HR&8ob?_1-?-E*xmf5~^jC$%)U
zJh+TyMdr-t%%5t~)7$f;fw;uF!jcgL3l9pv+hIBtIF(Mt?@8(9R#&~5L~wi&oa!F!
zCfLC{RdgnV@UCI5u`}`ewflG#uWYOyi~ex!ziC9S8J4W!ugx;4`AqqOH1ZQd1+dQq
z1Sg4Xig`A3JKm(8yS&}}{y6e6mK85zOPoWnUfGy*QbE81<0^xejdhcGa^vS4DSchA
zuB8*ht~C%HUn?_n5WFG@Wk*687Z{DB6_$zY?o40K1Q?2BmQ@A-qw%$JGdIC>_$kWD
zTmbq=W(j39pdy}Da%M6(m8P5kP!_2`&G0jm0H}zsm7O^QPNgpY0I-T=R#G+qLh!WW
zGhM-{w7a@MCwe3_qZH^F(lRf=sf^_!09$Y=Zi=k(TObRLR&ZuCSeve#2GEY{MutR+
zs<IGZAH1RpJw`&A9>{{L6_qI**%^vNm9nxGkOg1sXC@0+o4T9@pc7T42+aepC?KIt
zTTTjqMRvwycK;6tU~R^7A%GXY8$S|Sp_!!MxliQ`0N$u71!Z=i9j;bPCLBD+P|gP+
z0bAmvNGO{C5Ad`yGVj52jOEDuU8L<7Wfb5E?XDOS<;(z;C|gA+3RvU|5<Il!B!G!X
zpTtbmC?p~xeIk*tl~Be28sf}GXX=7mXv%p3by2n|%49$|&TM#Q8@PqOoE>l+Wviy_
z2Nc4Y4bH>@yVI4^0w|*PrIi_hLbxdk$_#)kuscIJHy|%+Ur|{P*o8M6m+1s{r!5x-
ztVZptDyso~@n%yp*T7c{<@|tv$bBhgD&RfdY({1u_=>ii3h)%^6P79We~9u)&6JDs
ziOn2|L?RgcfzJ99AT*Lh8u|%H$++u+g!OxXR3wQcR2>+O$DNw_75stLni%jqibNIq
z9Vm;#9g>L)j-|0C0F*?Ms6f8~W%0SgGXdaO>Rl3G{{JwH$DN+pgfxeQg8l~q;4m(C
zeCA%H&;LN82K5FG<6nvZrv3-~$gD5WH$Vnl?x;)!aE~-p>3^^UGT?J(Wio@6sjblg
zT2WbwP;Fp2E_Ym}Em)b+S_m*3<&%|}@jsA&p`WbZ0l1^G6rjpLYh3P_Oam~K!I}>M
zipr9Lk^^^fxHB?4!BF~L9iZv|u#3x`km&=4GFpoPE~5;-Kwkq1aV|*#4Y){PL>b6K
zC4r`lyB<hb;{swL4WyxD;2sGi*chw<fS4$sluZ8rfga38ZH)$S#=Rs&0+gCr24<tT
zCIO5`8puLjf$8|5+{};Q+E3PR0jyC53Q$Gh8pEz564oC9HIW7~P&=S5J}5hr7hFqi
zjR~-iGEjmV0-GbpXc%HLJ;1fJvW4D8mUy?+Zy^$-rL!rsyq{1GB&5E*o+$j;q4Y)%
z;o;KDs0-bMMhSq})*v)%^BnoZIHw{+r!x3AMv-RPks=1{^}^EiCRUF|HmC=m=3S<6
z|3Ij2^xsMTL5E8)Tou}YA_hJaqgnhzR(@w<fy_DBehf7d=yvr75O5j&HEd~J8g_`O
znZ~kaY$6?M{l;$`g#bKcC;Vk`FBFuo6<2ZD!KOtyHYui+cPEI-f1O}VLZBxCJ}rv$
zD%pbm93gbpBYI)@ar;x@d^~xRh@M_Z4g3!|J%11K7qSoQmCE%axO`imXGW8&Y$IC!
zXRqqYhcqBxwZN==iu>QC^1VpTcPyk5O%II-r%#riXl9T9JrRDNLPyvc`(T;2D@lN<
zYDdU-`VG6k))uK9sysP`#!3$9i|<@d)Cu-X>8{9~f<?j6--|i7(iekVx?xv7aku0i
zZDpc)J2~`*hPh}x?r5&{y;1EuA0|BBB3fV0J}!P}uFC2BQ#by>ZsOMoZ~ek^iQZ=`
z5YBF;Ip4tJ@w>}c(AMOCP?*X>?LOO)+h+AF&Q0#(dS^Yzr3JD$xyiZVY_`lZphGqx
zCdj)Z(6Ezhbv6B=O5*D2O=r7v*d_IdZk3$dH%sh()6n(q8wLUA7~w?xLa~XdAjI>K
z2_ZV&jG0vS)5{U9^a+&p--%$?+c3U;SK&y0ub)htk2OM%_oggB*2wwDipuMeo0Ryq
z_*>Cn;5ya1mPCt!<SAjy`4=ZOG{^Z<HgTjO+)`@?&Cu>)-ChI5)6|lY>T0zq0w`pK
z`Qmi^T>G>$*FcKs%3U*yIzhklvcKIs22{i=@I(l8`bu5!?lt-T!vzG^U(JgLt}C28
znFc(v1WlhetThm$%6w}ObpFS%&g7zfp*q-&CZp;?kFtMcdYUCCc;KJpGqYwFeAeVm
zW-9E}7Dy3z7{5Jgthd}s9dE}LsK++hdwB;5m`d`?H=^Awiq+mO$)XAQ`j`z=<+cIF
zX4`X&u*GV%;Fc&!=XNb<#H@?uM+<Vws$A;0<qJ}|4MgTi84DXdzV&=&#gLgO@9^aF
zIIcZ+UL>*KNPBv@Id*udXtR0fcl4Wlj9GTuT?bD>#al(WU)qiZZ#bQ%I)m_qA0CH1
z5qCL@owuBAZs*7mSV0H3M`!I61)!HrM6QZgtl=$V;BhzUe>-~pFM^y~dTo_E^P{wr
zpR$~DYM`)92mDBzdl?Rc)rmdACwjTK++TQs_+DgDW=%MqMSA|l4{_O@H^f6*c0g3+
z!Tvh!9R9!kL5xr;KX^UYb?m%T!+|5>ml!YXSS#jbua@0~Vm|!GtN|!0h}Ot0->m0`
z%IF2}<?LSWF=$GB<>lt__mkNv)yYec)6*%9!&yRIP-~F)Q;nJ2)6g{^<vLBDRnP55
z8_ItK-fW-hwUPfT>q4g6_L_wjh1_{YH)srvY&~>;I2T11mkl=9FvMuMK55XL$(u`?
zm(DKu3>xg#zF%Xw0O<4tC%?`A5X-<x9};e0P1>8(L^u~J`v*&C+OHW<(fV3f<VTwM
z4oZX0B8#$5nm4FTddf!e>P_}&((*J3?|C=r=6&^n=`RX&+OKRT!W3`OO;qyU%zoud
z&sJSfu`$YwG4QF2z`?H_zUrh8aFQ%o{<I4^shFCGa#k!b`m=}n&&{5NwypIWYYs$M
zn@iqGQkNS%=wAB+7TxBkYDGy?{x;1)!4GGBcveix-94vm0z+d#x{l$b$#GD<wD-1m
zQx8wt@7z!%MJ|7su-_-|a+$W+gtkB9RWN0+T+`2RAeq1haD(fL4(YTnLY>dGt$mN_
zuqV`R5j-Me^tKP(`1SkskM$@UXU%6^O!6dwq$YZ}B^&GOMlGVw&oQFs1EIl$!ReM7
zLrgLCUP>AXj=?4R30L2FYe#0zG#9GfAIBYG{oQgT5B;~Sat0R#ps8=p>~|S;>mp}3
zcPu|oK;P@_yX~ort~9I_PSy_g;LAoYKxf4{F9ENP^&L!3G|nP^0)=4R^kn;Rm16Ox
z)3Sw)lw2KoiJQ~=HhjIZ3)FN}-8Z`L*05^PYq4t4YB4R}&cB^UT|;wt-$S-YyhyM}
z?#<aqe-_x`&|!Q#|J|;`Ux3}1+8E$ZcC4fS#<DJf&2^<0@&4+=75Wv{71|Z%)$hCJ
zpuZYy*Oun`<^u2+ZF9@N`va8&-&V@K1q6+0jJb?ia`8AQ2p3rBYiA$y7n;34FmhoC
z*yq9Gz3*d%8w3yYyuJX*{uaVu2i6|#zWSndrn=5G39y9&8}@cxeb&16I-Pkt`?%J5
zNb|hGVVzek=6v_OtbI!BlJ688*z4@r+R45gecYt8Y(KIjW(4wBb|&+rTy8;Wvs!Mm
zAZm7Q!&q)#lsPK)1ax=gIb<{{!OM;ax?4<!`^M{?)*Tlb?cuFQaL;g)k$U@eiv`eW
z>)|ryQ8*&NleW9yDROl^aE{Vk+#0(Dbt&|C<d_<9iFoty*01=fSadAkVye}wb#Li(
zk?hFpI1a(!2YSly9eRd~IR#l1H1@Zu!Pl26j!utf<F~)dc@m6lt?X;Now!yDdkORA
zW~;JSw54p!xf}@H2wdm-<=v~IR1~=t%#PX~xVv=;i{|F5a#pm@qFT(W?<v@1a{tcS
zhq{`&SPQ%5c23qzio{xt119U-n{z!T-#upR9Jz{lcnbUF_D+h~^j~JV4G8`tcNO!(
z5;hZ%%jL`~`4wi~XAb-v)cEBr++6c)*!<UDm0yy-azcNGw!eva6Z0<SZAxfa2=lLt
zUoB_d8*v*d8#jYgVdCgPcx$2Texb1WgOH>%T#Sc=>tK)noEk$BD(Y|!d%aMIr$smY
zTzf&I+(0No38DSXajKn2%I_h-kI}s~s4*x+jvS`&BUsg<0ubv)`Q32PjX2}sH=Rw#
z<p*VtU15x`@t18N^j!-oLyV*~&>x?LyElY_W`g3sy3EhbT^4cKaM{qPP?b=}2N*YW
zHh9l$z1_UIk1(CloPz^495);r#d~ObP{c4!(N9BA7ExFS>FmpS$9;#g9VeQ04I2zE
zYwzY?AM)B4U3ayP`u;X_=(S~UT5C=>9Irh^7Jp#RlN`z&)?TN0Ox`aEIX?ldjEHJu
z=IO~Ctd%@%x?@&hC)Qr=ev6{Vrk>8-39Ac%!<6>o_6eW@(8x0Pu>pb=;qc(-m(~k6
zwP<Js9eE&p9|{9TpI5{jg1%BU^|vIz&6Y-vFc2~i$tYNEih|6lwiU5j^UQlI2c<$g
zc{~*%TGO2q3SLfLEP`GFX?aN5^Il*@$?TZV;+VUTut{$H<R_cP%MNa^&ve#y&$hB>
zxqw!l?WFsj)t-t?)MYw|hnVQ<ZEGRr6>6M$ej&++H+6*+?jgU-nKJo_sXm}OW0r?6
zM69DZzjwxT#y<TJvkpSnj6rGjPBgqDL^k!BgV@eN_U9n5%CtjGR{la=C$+kjV8c#U
zWXo~8omX?&p;d1S$_V}A;ZCnxS25;1@vDwa3GPTMD%NxPS3SusL@nZ4^IL}vrVO^~
z_Uh2)G3KQYW$cr$lX;i2fhw)#2D5b;btFhVYvOgM$Kw5<5HP@&qP4F%-oVUgq|Uh(
zf4+TQ;ZXQ6brs^|*xs}ZKR!ZuqIQ?8js-4GwiGnW!PS;aj;0aBe%Yd{flK*c`)xU!
z)|)fn<3~FPbicBvsNV7Cxi!brrW^Rf(G$W3@#-P>2^6sQJT&QfAsD3^Sn<OxG-Z3`
zAA!4*E4m=R@XtJ>TpCr4icGB)1y4l*`aA|z){55IVcWwNH@GlGu3X-$NsGxZHno?v
z+><_&B&Q;$%HK`DGYB;Z$AqBd4owQ~+3fXP#-tn@f9DX&2*I(GU>*&1RY&s;vHL^D
zM#e^DN;Zk!fYDF&{Q1%4cD7$ec-Qxk3ciACVZNOg^plx1+G{uiV}7J#m3Q&KCL<g-
zhZ?^%hr|n2G(MU>z`06f|0nO8t_P+r=jqa^ww)&bZxv2Euim;DVQhY$!VC%bv3q@6
z_c$Mi)9BQUE)jWg=Uo$~LprEyaHz{<p4L9|SN4#PmBOi+#lUM|Vt!Q@vty{*(dvsv
zO}z&;LHmJ4yfKYGM=oaCAQ3)6q5YX|!nmi*0YQ-9sexzQDXkih+!_bNNtPus)x)$W
z9wHp;KY_OHkO<exkWSaikHv4&kK+juE%(zm&5QPpN{y_xTc2ESthb$hroHec$m^mu
z3wj-cO+IYdvZr3E#`SAGxvsf0`&zor@fY*TIO+d~9xUyAkp#{GZZ;uw6K>lj(5;6X
zil*%MFInz;vc+ts_dGVaw|lfYa+b3<i9TGK8xN(A=)>QW#~zLs;>sdE{voE_5c(D}
z{lp{^=F;%t!>>`}SF-PBL%n|gGhhAtbOvk`J-JT%3;pY#S#Z<YlVYy$2)Vuas`Kcz
zk@J;oBKvanIdfxoZnL8XXQ=xD99;)+mh5+2FnbLAQb<ytCA?AHX<wM5?}GXc)f5dH
z?@ajesV=5#meQ>MV1FBS(w-@5<}^Nd+Zm=qlH4c?|I&FTc;y%1H6At|5QNz(Jy85)
z<jCpA^y~T$Y(1ui(V{A0FZK2`?ye0e3zG6Qb?AR1OeOCb_#m5j?CQw^UTR-T`_j(3
ztn;g-=4-sA#XCb3a;V6mgeg>rOi~OgNG9<L`hD#uS+2^YwY=+^msog6=EQNxCQU)8
zC3H9bivsc}G7ENrv9T^dD)SQL`>6}HF7ANZq~Sn9FNjklQ+^LTyu*UO-~Ylc9=){3
z46&EirFG4Y%AANawien2&^UiIs2Mdd`|Y5!UF~cz?z;0n>BENN3DMZ2>qVGSCUxY|
zm+g0gf`w5_1*4DBYY}%Lqfa5-p%0;`A*i7dp=NIq-Xy$Bc-xOfi5*BL^6^pZR_aXo
zY~=6K->F|1zmyi=`p9E3Q}YrKUHoiG#6=IQO~gkJmn`Zj3R4eO*ZeoEUi4?8Xt0Q;
z2w1dPw5?vHo~6F@r><yD{Z2hQr$D-SA_1`Q$kQX-BmQV``{maBR{i$!Y~ze*gVx<t
z659LrUuWp~%Ytdp10q_4o+dwySfZckay{l0E3cJcPjtNGN|Q3do(l?9>h#GB^Vt&M
zcY8dAX}3{E@^2juExe=|a`}#@dpC?XzEq0`ttKSdguA-V)xKy_(2t((YNoizY?-s$
zn5Sl0O@+Vls~5$-5DwgXX}V!QQ~9{R?4~-S4);}dJF(3!|G)j6^#5(<uR6z6q@@j=
z((J!>MzO^V(6nQ+#cb06zZwwY{%<oN{Qm;nBpKu<2+wnTTnz_@x;aj6GM>GyC&#j~
zysY!Hd~7Cjy+~)zcRZ^wU`@W7PhGJGYF4F^cZzv3vfp~FH@I4~+4IKd>Sx}lmbWI4
zRb^K)=hp8V@@3TReB+p`n--re`Diy}+^1U%+kAxc8dB8jcdOQnq<y<?CF?LWlsaZO
zA+2lj#PF)~teH<mR<WBLLQS087iT+m5g)ooYj5-pHB#!ok43TFgf*_D5TyHQrtIXG
zf>u&$^iLER#zi&sPojoh)!ftlHZ40DJK1jN5_a;pk;h*nhmN|cMI(m+#zk$Bp_Wz8
zzV+3|xDSX?z8aMl<~FvR-@9!)%XZ5L@cMRG`|3A)%kI_r6$F_P*)m0&pJT7PXQ1Xg
z*v7-+J^X(8-6EuBZ`z%3V%~emzS3Hv(%L1`y9HC5)d?N57<0xk6}&*yZ__2h{*^C=
zp;#fc65)oKr{o95b>~=B&1IjY?fsl_!rDjYL>*f8b_S0tS@B%(F3+LD@R6mhPu4U^
z4pK5&a}j#+`Xc+D@%qD^^7tRFj!8HS4l^d2C|~NR&#tyL=AWn%>^w27Paj{cd)xYH
zL8_(>wtF&N4?A!bZ9Qx~>@+n*se9#BFfZSoby&wco&DVk?r6wepD-_T2)Uj$n>X8i
z_pjlw!ENV0=brK;(6380k1Q43FDqV2_itAFpr)z?SuA41k=DSM5~B$Fp&(^d<ocQU
zXrJlEdYHWQ99ua7)YP!(jS%BhxCayIl2!AH^2y1n{XnpjsCm}Tlb99%8;rg(U;YE`
z0vwOmr#PiLB^k<lnOoJ7+c*8*W~)u_nreuHQ0xfrsJbI$%97;BT=>B~blMbtvNLvD
znnIJ}k|Qo{2k8nyO1})<Ss}4MVJ>uiLaiICKt^z;ZB96>PF%vsTT_TVFGXQS2pjfl
z@k4#~j&M}O0rd2DAPFOa;DMIVEp3hsGd@plWDUmq7w@tyZXG}ozv8w8o2{tPQ=Do@
z(XC5l&=p^T+W>nnk<$o}bhTD*xlc(`v;l|c0Ho3o+gH&r3Z|H<KSN3n^GOX<46^#6
zS-;ZoLHiwZXc{#{-71z#m83ygoq+|LIVE)rLSU86Ws+6(sDZ``N)v<>r20T;&9n@O
z(s0+dKZi4T>OAK?soL;$0*gi`7pf#Iz9}08;tP2-0Z)=+7FQzc_~339@MVX=d`WJj
zs^Nphvdejue!GVLFUQw2OV<t8$nr}offU)Zpf52Tt=AyTW=xAi_ZGDr*~1uweG9>h
z<pVyT=?3L0>#mKsX_2y3RCY!mDS&mVa%Ap=w?W&I^_RM-ssYVnk`>7BSs8^S@|5oI
zC#*mr2|VFqF09A&YAKqA@iq!s?y5p^_tRn^hJ7`qa~4erzq*<+XWOZ=l%y7d!<nQP
zw=znf$es8esH@yFn#r~qThR8$?BAi=Iu>+IK<81s+Z^5N38LOr@42=wbJBSTB`i31
z=a5KKzP{OGMu*A@#|e%ZzSm|im~tx*Y%s>$N!PCZgCDE648Y?Y)s9}<uJ(OnWoMmc
zRBC&=G9~E183!Rt)O#%xz>ty};70iL76MHnsP?$4V!%m6p-WLvaY!^O&i<3*9W<5n
zR>2tlhye|~n{mN-v<0U2bsK`d+SHu=Q9`>?^W>LVlQH`2*n7XGl)vsec3BHvOI$Cc
zN0dJj!c^DN*UMU;`uwBkERPc{ldAFMsyA;Ll~9~X^b~67+lr@V3Dj^UeR>nNNv9Tm
zy(j+izU@XR?z*sTvW=td#Gzbbuixt%Md2^l%p%tB#PfV?U)1B-XXS@FPFo-PmJpMR
ze%l;~I!~E?Rl`alkGdgiURrnRNqFGr$v>}lS=CskScOvqAQg7XCZ!yD1sV%AIWRrg
zYPhj|m9Z|zM{aw$-9lxA^-sI-qqsOnrel7VN=n<Nx;DqMfM-UUW24GG{hToHt4(j$
z6oI^h2a3viP}qu;M;>M=Hq3L4HWYj_bffU|Hux5ogd>nGP<gnS;??%6bEPO+Y)y(v
z+AR5H&7kJk1F?^mZ(%_U$$O3WFUc*YaCtsWb`ZA@$^Bvf_ScK|7tw91en~y$FD5Uj
zUmd3}ugU9nm)aXYeDK@is`D}NSbaWxaj1H10Br%j?JIG@*T2XK2xWhD{twoOZ}ALU
zZ^Sph;cvEBep%84kXV><TkJG4#NCm=BM<};_y)Ob;R?9NO_cNt)3@$3kw59Y{xp&)
z2v@_7=qRd8L1Z?*=k9#+51xE-4PyK)svc<lAzpS-uy<|M<|$MqqBSM~(gDG#htAW_
z*9q&SBZyN1)CiZKba8u>+fX_y1@~cEan=S}F`t-6bhN+<jgMVlT0b<*e6EV}TB#i4
zF--Yb%6HI+dr+5UEPGg2#!_v1K{mH6YL;^EgO)=NG3`=BC!OlpiMtpFSNNB~<<*fT
zM`fTU&Q{Jb_O9xh(x^3qQ)MUE__b?pz`2P#3d74cDgH%?-<G8IvD)f18Y%;-hr&is
zYIN9p*C-BC)_Ho*reJScm%kGk_|AQ<LkRcbf5Wi=H7BLZ!z8K<D#lknNj;GSHH>p=
zRXz6K>ZOR64xb|Z>36doum^_eIvb!}zzJmkVV{<kOu`gY%zM66396n>%F;kdH*q}Y
z`jJmJvq9P?_-+DiBj&R&V~={R@x$LJs#<zA3fzSqkqyH#jFu~oX+8cYFc|d^dXhWX
zH@U9g_6;Z$OPqU&KQ6XSo_vI3D@G`KPp?&Ac(#n?>|`L7FNZ7|g0Rx^N?sVxHH(gV
zgKnK&xt$ihj;@a3e@oR`6FRGQ`3D-8It_5yUMa^4Pj%rMlezA>lY><|>}$%_3b<0Q
z8oSOzCCZ%Z|KukW#aKEKRUh}3G5Bej#r48DWwe97ZjEZW8(+mV#6&0robyn;7;Xf}
zFxsZ_<X@G;&q_*-eI*Sgh7~IIZ@FH9po%`RBI#^NdZRUCnm)acG(OR3)INr5Rk^fN
zjjr2Rf0B7zP;G6?zn_BecCe<oT3sRxY+Xmb`BbmC7?um&pt0(mykR%s^h!=+_6kq8
z6Fy;MU&30+sCDmjYw`EH2uovgF0wL$RLoo)|6Z`Pf>umx*8k<MT<a}puQIE&xkYHV
z!$-YJLD_Zw{7)YPgxB*XF77BDD4{o{7SntF4OHN=Qr)SE`&Pmi8~das_<7Q0_qCU4
zW3-}81l+8JUfJlEzCyL!zwg(V4iy$vb*b|{;zr`tNm$L8#cq(VZC}CCdncs2ZpU<Q
zOIl^va4_UCo7CCps(|tzlCt&JRes;sQ<Qk%TCcwPCWpC=aP^zfJfZWV=})3crJ}9-
z9F0B5Bu4C<6>e<3+OCs~)ig`|5dvVT<f&r=#2CwXyeGo_SNSI%(Mqw6)dHr}*uy8W
z2vu}@5NQfZxZVpg^?b@Q0M+JcH|vp{ep$@-KN_tN(x>X|C)Fq+O7p`O+6t6fWABgp
zIDq}{=%LbI`I*@M2V>*w+fIMOXGyV8SiiOqcfVq%VH5C44SY~g{x8~OY!G5bo!5$*
zmZ*tgALOwJp~|b0ORdDyN@r3^>z_7wK({KpXlYjTku|6jsi-Xj-FiSUAig^Vkp5Ih
zciEThi>_uRAE~9fo~k3AwQ}x9uhb_<H$-D6^P=gZ%2iXa%)dTYw@-bN$!sP)<sbDy
zB6mx~S->7w2cvDnIk{18+meC4)|2FYa{MZW?XliWml@m3j@({B-Pe^$9&IO0Qdah~
zc?gA~+>UCk?c-wZi~hU-AV*-zG`_i=v)+D&aA+-#ps}5{MTD}V?(g7P)cih|WWQ;z
z=2c6JV)p}=n-ap^NTfTaJT?8F+_cvHv>e|TswI=PvN>8&+k>cfyBpqtx>#NhSJf
zqT$zbTbV>nB#atrH5D~`bWq8RH02KSdA=VL@Xuy$U;A_;?+gRN?0*<6$7Qzi4%Qy;
zUQ*-A$`UgUrvCA*m$Rc*HVWJS@tNWpMVo<dT}cHBJ2PE;C(4RJs{3CV4w#$+yat=m
z&ur7__6?F@)ocyA#FPrD3x5+R{~eR=+iSFJO|)kTMe1Mw$*W_boxEr?=X~y`&s=9=
z$^+|}DzkW^uk*;aFIRTHt?cY<u~Zwc;=x2PG=<IQD%ut8hX2X-OA51{=#_nzwm-q-
z%9vm2-kuUyl%+hxdgB(jRC%fUClYOYkeuKU*ETciATw%B*`PDLWmsr1Pf>gacP6f_
z#%=rSQ)FN)+pPGk_{hR{aqapSs}mFbZs+GW#}^TMg~RP(maQ<tR*#BlKOZzdz0`j}
z2z4Hfrv^|RtHRnexbM~1^~=TvvGN%1*u=ilL}wG68L*@sblAQ9ph2U0ErGF5@R#3t
zb)M#}YgjLunm-`fn=1cSlkQw~Wl=%q8YzmLd3s~DHM`!t7O*A5y0$}9>vLMNHK3=x
z$D;16Zd7xl+Yr!S6FBNFaO^~zaHR6%_vn^sYE*5LD0*&Op5d?(cj`Q>*Bho+<P2J0
z+SdRBLCXh=^{pQ5tBy*!eRgWuA5WB0o6>JdLEZDgVqc4@U}aT&3=)eA^`uej64`j_
z?+9tN<wIp;U4*2n7|&h}sz!EyPOrw_>@yS5Nzd}xr(OElTW;#l3SDz-^kVhID-^<)
z5J7K@)eac{6_p>exmmiWA3O7PAH&ezpvANNi>4=*qXkO^m1t6ycjb|4tw~<Sb;R)G
z=0Bxs-6e$9RnWo{&$`E6{BxP;Q*vsJYN1<kK$e5m=ApK(H7`tM94dWSMmYhBN(U;<
zn4Toxrc3&k!`qwSH?<}eePTxocI(4->mXOX9uNQF@BE}3Ae^+@{767Nzh?UkE4D{3
z&r_GDpGObk!21|>zGemX%fLM~k?n~c(pjH^N>ueJ)vrwcS!$!#)Q@fyyW|SsH!Aqm
zN2eJ}+4Dx!oBir<>vX7@n?zvo=u|LkdV%&bZQI+noi>}&tQip@F^AivJ4459d&tKL
zqS=NdRC(vnE1$$Ql>OesHPlWF10_7asItwcP4n}w=Ltk}Qz5Lz;<jyDG@SK#3sK!e
z0h_PR8@+Wm`?h?|btw5hVV{~bi7Yy5ENjh>GpBoxXS9sapPTL_Ke7K&3Cu?DV)%&5
z*RN0>M>-BAK*xtM;ByapPCJjNyTR!peWpSCTu;9rUTB|CI1z-XCgFOgW)h|W-yWvC
zj!-juFl(-xr2f=DYW_aOxrZD}_N(t=e{%a`cO_1D`E}HoZS@f&{cdm-P8Fi3RJiQl
z-af|WpcN(>(ms~3L|MW96*mt%`!iMQXDaBh|K~_S%lB@h_ManaFH7!a(gREEL?71I
zK`NlMO24Ie2cZ#i)$93~E#Z5V%^VullJg0i-*og<{&)yWF&d&Ex#y?xTVjZJw&OeY
zErYhVEwM|6@nNmG4z)XPnga0$?<aWm`>QT{XU?gSon5-{@_75DW{WPZg<kHox8nl7
zt@D;k*C$A|D=ymo*omXU8DV5vPTM3kY_lK2EFHdyE)m-lkoc{CHXrfF;Mta@$ww?{
zU!;Im$j@Gq{HRW05dP;T^;B!FHnf){T~gD6=J|(!YO^a>t@42N=uI^3`Obh%*o3^E
ze?wxFXArt5j3vv!joS>zGgTyd5l69yu6HVFEoFP~qXp$WY_gwSC}2odUKQxTZCeHh
zh5ZxjO>6-vd8WA!_(gcMkY_qk$tTZB?;OcIn42Cdp3JMwid`(RmKS6qJxdf>FjDeE
zua2n$<Y;X&(yxg08cV4jDCwVuUbGd&tyA3vs!FGfo09nyVzP89Pc`5+&lQSfh`Y{r
z;pqWZN;v`DLbH4+<q*1EWETFR%F}(&^Yy8*FCIwX3;7pK@YtrMP@6JQg;oGH!?1ky
zZRRa8%swBlfW~&yZPSg;<Wcf5#4>UZ?6%FqtOTJ6(WXgDtSM8~v;n61DvCzM)dk~f
zkkZE$)83=Zph&0Z7xvZ+&gVs8<uGFTw1{Ne`FYuUrI4o<V$ch`p%;j~-ZV$udA0CN
zG#UD`+T45gv>(J&zQ|HFhf>)xdoEjFwU~cEa+G%h`-5ATQM*uJ<zOSo$oo}+V=SH=
z=2DY?Vkt7w*9<M&(NP%Rm)224Ue!u=&d4WT1bgZV@9F|A&cj-aeYwtcGj`&49Y0Ly
z0o}c3rdMU$l0yJ%(bJ+Jp$T2t?7c;i-H1}##bW>o>8oYjYz)>KXxD*eb961E(Wq*3
z#8CzJbcr^%u*#&1HAfuC6@BmTN^Sy%E7I-ESgIbdkZM2Hx+COj66lXs`Iag8*pdh~
z>6O&G{a;=YAWkTFq!P=z{AKD-bQ2Euh+9?efWn;3s7!$B<nOyqoa3U`#*WdgoxTKz
zF76B}WsZ_fXbZVOw|dMWK4ZCPicTkjZWmEz#5RN}9a&m9-dRKt;Y!OKzdfu$KB7`8
zkd&k7!orWyT`mwGFT6tTYr{cQM!Z8fV~;3sjWDWxifQJOE4lA7E_O8ci*F55KPq%A
zyI+xXBnuRcH*5d>g7(-j81(u%1ILbA@_67$%_WHTq(AndVdGh0<wf|!`PWlk#|z1c
z^Wam^=JR1k5c-YRuNT2b=Yb&7=hZW$mNw_CAUFv7@g?|${dQ`wpXix$V;%KH?<@%X
z=qvO%@^|V-koY6{BkEuNUqLv}1h?xE>#tv^Z|w(Os2{7K4Hd6?<<C+6;{Mh6+wGk!
zS9$Z7pHcLM@9eWw3#X^=Ay9wGFoF*OOC$TqtGe|WJ%KtG@dF`OTvWgsZVfQWQ4PY-
zOZfBFAw2XjtZzfciC{bYSlSTk`a8)v>PE5lyRjI*@;%tpKXPK4L9Kp%_gm1+uH9uz
zCE@HQ{Pl4Ie7%LSg|Rga&P{ss>sN>#%<0k2UhXy|XF>PC;Y7Kh(>p?F<Z9$)9?OGa
z%oMITdCG5=K{u4PVaVcXh=0`5M=D&`AYm$GUU6-*sIovNT=(#as3h6dC2;-r{$=0)
z^HLUl2sl2&Ij3NDT5Gu?pzIK4oNcqcrX0vD+>&Bd3$Mx3VBblrroFTGx@&&w&1)1c
zM@8IV4O3>JA0=hQJoR2S_47wR^(KsWr@C3<E`J?&9KkXo^ITM1{A!PkP(2rgntsp!
zq-Z<AP~3SuvDsK~?Tlo1__<=As)*j{jt!8jg^$1);T1@U>K>d39)uKTy9rfX`bL{d
zsljHit`6D&bwZS+mqCsN=dWj?+itZiKOw&9`pZQbtSvE9SfpH>6k13*vv>_UsrHBM
zki!?4+*?MAOTx6ExF%6~xehM?l{Cb|fx-2|Da}(o-V7jb^4FBo?Zksi(9Q9@;=jkO
zy|o(uUQIJwq!4nYxJ65dDKGUz5xcCywP8l7Q*FQQO5^_ds5`6Q=#IftgsP0*;RR_U
zzC-3I^6~;2xf5>pJ}K02C5)!h4l*&mrq~y5WSclr<c^u4S{4hY&t(x7$X!(GG4q%5
z*K<`E(xlk8ZcJa=@NTvvx}yJ3?~^o<!@^2lvO~0!5%>yvf?6Xi_0`elqD<E_&}p~k
z)wOSH(mk0F3m7H`dyBLdki2$j)kG#UbYF@&G+wGXbY99iv<lQSYSgM(=PKsX4rUKn
zu1P#v?`ykc15{0F#2V_g%m$t>v*9ksv7YJigwp)`)~m$};Of8nh`_YdB<&kD6XP2N
zkGs{wvxWPIbi*S0fR`Odm1#su<Hs~h<^%gW=>Q|aCv#TK^=xsZoywWLzMSBQu132a
zD4vn!IPOK>BUZ3YP&+hcdD9!zk$~{57y{90L6SqHi-deh&b5y1*s5e64oS8R;Wkq=
z9tQm?^(CS=MBBdmO8ZKKo>=SBPKCYB7Bi8E0rs(p79uAV(%Jl5ELV)fI0bw-l^27G
zZGk^gC#G30UrE;jQR(u{iA6t0hS-tGzk<0o%^HUr_1+5nK0hF0iGw_1QKWRv{L4({
z)wKm=LGgQVt784TPS<YXktNf_=N~urM37Y9A<Jes1Dvw$X|+w~h|LpUF4_Vd0Tz#0
z2Ip;RoQL)4zC6%3&-VbE4Z&0NF+2*sN6oHfCV)=6MTTWQC2XaN(y40`_xOM&%Y8lN
z=2S3Q@3>-`%UiDumFA}{JfHe5*JI5imiYOC1%8cVXAHrC_U+}1yxS9hwZ2%+y@-pF
zyYol7KvJsRy>pD)p-0z1-v0RYQRfY>v+lcqM~UapL9yav1%UH%?G*E5WzUrHZSJ=!
z9x9kBD#{Zoj>>t;t16-@R^`Fv=(FEuy=UoWd1lFH{k2xKZ4IprZ4E69o#B>nJGd>}
z0&XMpO$aFTRmf4ues`kEy2gNOd4dD9K>m4wZ-JYiho6t1yPd0@-wSZ_`GzkehZSlu
zfj=<|1wq{=G%h7C@h)92SuPDPeJ>d<buY0loi4>LB`!5C6)u+u+!SS_d1Vw_N;|at
znSZ4UF<)zvmh&js=Fc#cStz!r<}(LqLA1ilV^v8Cxah5PAw8+ykj>OGW>(Gl(pt5p
z+-6ZLFGyc%D6^bqd_}IJpanH^1skDK_>lE9n`+F+X8T;*Tsu!QPisp{ORIacJLsxZ
z-<rAoLu+hHEYj9bxiw6K@MDx~Beb2Zk*$rbwYIUgtrq0a;?U&Ke$;l<PTq!8b++Z!
ze63G1l&YkLH7<OIoz1_WtJEryh-2V2od0H4Viae}dp}QXY(dAqde^e8s<lM4K&)qh
zCm8gM_8_D@EXWvmE_LpvDYr>4+$qx~b0FWfk(&}c^Q9`}!-ycGMU&nUb*>v13af1b
zL}`a{4BewcD5iEei%}RKVfFoDjPl9sp6??4nMIY#*JNF0?U&GUci4iF?N@UWq}~3N
z?wQJeh*z>vQKChnaW&5a0*&My|J~Y%z@{QOt-};L%HR$wPh{W8&l+y6KIA()nv*0d
zOq2GZ4TybVkg=DFo=+_1E&YbcZ1{g+E47S$=^8w-_<w=?G^u7wI6)mIGu*z6X9sci
zb3ee>afRw#EQ;KJHYgU}cEtGyKmJhswI~uME)xFajv97?e2LSABI)&6(yP>G?<)Q*
z?RCVo*}lm!uCE7UU@v~3=BI~i)knyF-oHFm_|rhrfWY_9i9>4!hZwQ56~e#yDFogN
zkQ1Y*z7vzSsE{vE?2y9rYTJ;-^b&|`z`&e-Tjho9-IwS~RJw)?We!Y|eD!Y2QBYq+
zpjZryeM$G#qrI+|Jur!z>n5%8;?=AmEnL&`!|@hRO!MR){iE`L@|`8%gyW!_XlgZP
z?_|i$%Qogm(0{6Bi+Sk{QPhfU!Y9g~PekHs0*7G^9XIy<{KkYgtM3Eaaqpd0vdmX}
zNcEm#Yu>L&|LczXBidr~!{WzQu+^7&8s7naG66yXEaJDr!Q4N%gQsRPZH*H_5x<`N
z5(h=)Hz-TLV{3MxGOwVRz4_m`TY>Mm-`{;_NG$uZC24vhk?;K^Hg_FRdHC=*2aEg-
zIacf|Mic{+bsOZHvj6{6MAz>1T4Xo><_YGy``=IIn^DByxe|v~mm|B|alM>rPu65t
zdU5%WqmJ+l+1;kwm#pTwiM@=-yo|P-u)CuLPJ+k#3O%-JVXj;uvA<QT?kuSd6m^qZ
zEm794Pw68@U0kzE40&vJcqYeuIzQ=U*n@eu3|%NXPmG<NK6$D(ayPy|@~rsn)E-(6
zmra<RgMWLfv@hp4){7N(*;4JNGlMzrgfEYLXCysg`%TdRB3~^MS8O;bbP-qly&l|w
zTwfT@3smT<UWZ_|Cv2$ltQdp~=Xdq25i+;J6#w@_GyFg5-a4$Ur(GK@rMP?X7T40^
zCAdrR;@+Y~f(MrZrC4x>P>KW(Zo#Fv6o=qioZ`;O@7>>dzrC;X*ZFV1$y}4?d1ltE
zm6=)BteJJsbD#dM7om4Vy0B>I)&XqXc>X#&jNU=$NUY$GJ(XZQAcMP)#;3A3azOpa
z<x0|jb>tbdBq}OJcK$f6bL@g~N#)$&BxzK30i+)Nx8NJP)|d0Hf6Tw(DgR~WMI8$I
z5E%-5UP%zAq-m|FiOxRwN{%w0Erir6?&okEL%dJA?iS1c(Q&nsD7DUmStc>WXYMZE
z@u!Qw<hy%SCq8a@`>Ig<dqZsQz`5L?wv(!H|Cn)qqGlfHE2N6KM3H+(m3t>Oxr<@O
z9%m==fGbuc5pYO=R2~*q#zWA@0jO`A34&O7pV{I46IZ2ve!<>{sfGVf%dR?`;|f#u
z%g4DQjY9wTM~1{=cNxa)%=8wY2G_EfKz0u`{#Nq8-vPIhj2FT3d#Eu}7*xds{8~0H
zxZ&jQXn1iI><GT%hWuE;{Yux9PZ_);zuH9P<@8qmsuLNX|9Cxa`R!%KFya60<@3%Y
zNL?n8GICrdW?aU_=Bvw&o$&=<1%oq5Za7tLxReSdI=9u!+9V5GqV92qZ=L`17Wkk-
zY5hm48}~@>RTy@@MldNyoHUwNQ4r5_8XOu7Kbl5NVN_v~eyt+p*|B8^s3Mx_kOAwz
z{rx?ke9c+Lm}WY=sSCxt3I!^kakd^YY?s)tKoMucw|`~-siSo|s~)kz@4iVyS8R+&
zn&0R?ez6rT`1VU1I|e%3Xk@*}-MwUiwEi`l4B@~NE2=gmDB(Z<G5F=*qO#1tEdTFM
z*ZB{*Z*;ZDw~dCDf25*HE`G>O`;0Tl{FjO=W*eW2!OeUA>Q_p=V#KagGO}#DKT^rl
zJ{kqN81D=g)=IMf`u(52Tap6|-{D!*OPz~gxo5bVHfan2XLGFoR@nc1UUiFlEBqkk
z-|`6X|N7|b|MM|UTq&na{rA%k^=bMU=<ehN<?RRmlt%@zvay++KY<fFdx0}MyRm=H
zE~b&blwMQ;r@_DHTANchO`12@ymy2=g(QYHS9#ATJ;}CuH4PZ1;fS(dkt@>__g%~1
zaPzMoe!*s7OWKe}4;!_K)2g_7!;)>5>{{t^6iVbM@S6VXhuAy^HROf~)whFT61%ZK
zz5$rar40j5uX#rGw#Tw~41XfM`<}6aAJ#?Z11_7X@+7>JDjX!d?<sav?$ghb<q=yi
z7RaG24c#iI?2iY#CRxB;n^6#6o>_+MUDl1yW&(|h#AjuS9i7MYvkWQUW!ZK>`ehSA
zUaTB}uTsU<lXS)tHDkzW3}c9ooILu44LxNo=UZM|iL?G6X7TY-PxA`scRZggE1zZ+
zzLjx`@>)JnD4_T8SR<MJQYSuCZ}(a8T~4O&TkaXwHq^P@`uhO=nX<`h+7>=6Oy1aX
zcC}?EDt5JP%?|YG4S`rUsc~;ue)798{Io!coj+Y;vIfQ{J~`&EzY-U@a;4^d-@djR
zx)sE+>!!F~>k7{2r5-xKRXBWq=zWNGD95<{EB}ohy8TzJ3;hdK*7=%iwYamCTlshn
zL@1Y_Q1XPHl|j6l|Hh<%ZSh5+)lwL4q19Z@NB`r2;1G#I8VkJNm9K>fuW<*VHSrah
zFN&j`v~mW&=wENS#w4|iwJ4?}Vp-xBtCEjDg$$7LrbNHu>%Y%0?XAq!J7yhJ?-E}R
zNZKgxK-v7n8PSgVCMYX9MilYTSCO=XSF8}1k`EXGn%%aGmk$)?6FHi+CRCtLtdJC}
zsd2>QFn9zfB?@yN8k|3A@Fom1lN19v*z+D;&YM=%wY3;5iCIx|zJBme*p%T`&U}-s
z1u$1MNLAj1MxRfT|9;7hP&e}Wew#_joCs>O46yvdU^U1wNO|eM@?tQ@%6$B}Guztd
zvRig<_mx@2r8A8F<s@aZaNa_ED;-uX6uJwvL}Kw@<s5?E33KO@198HKj24|iiA1Jt
zR}6R}E7vj5)=#S5aiaQk3<SyH17xSp-l6wKU2S;uZ(`yCIAf9mSXJW!cvO>sZ`aLh
zcoe!kar?^rS=3gnb`e3tT4lXm`I~(7V`cpEYBPy50$MgJ?uBXK3~@##H|K4(gp~K}
zZrJhe?WUPUx61y^TotbAv8bG-?KWTZO?D)h@cBkK?>>8`>^-gOYuS!vU4OPA7rO5J
z`*x^7Cr}mBW-j^R^*f>@2OUb1(JR`|MY4__e4mO^KmL;72j5a8{UwMg=#;a%m)WrM
zQlboeN=xH6s3nVK*%)BbCr-1OBi5JFP4uv2oc{{DEp7WF)V8+6D?CG9T@)}!y`sz9
z2J_bYC>!e)<5hZ{b=~Ymb@`kw0TM4b;J69c#CJ7gmYL7xMNd0t4sEzVPeHkRhVdK&
zHT>DibSjbQ$MXVGvD+0kQ`D#Oj-4Rbeqe!DM($K%SOQ_@IUx?GSU0kucS(rKyHnZ@
z`~$rvo-<C$4qDvl=eJCg`CPRGCzFqj;^hU~Wg`gjD*wR)#y?9JulaX!{tTV77Twu(
zk@->`1%;~Q7#8x_04s`yxZX1#TvaE#o3?3N-_>bjO)BR6bP07xX#1Mx7&-Inm-SQT
zfY>7IBKwhq=o+^ldd>i+A9+q6MTV1llh9UM(nOLtyNuSi0$d8$Fwxg$Y=qch47vJj
zL|?ExLYt+<a@)owZQ1yVsc=+7t))S^spCd$B<Pq|I3b}HUCwI_U8r3lUB_WcU8HLk
z7R_%}Fmc>Mo4Q0T+6c+kyPjL*YOr&Wr(mjtS#>3LX?IO_@paX7xpj%G$*nQ39d}8D
zriKM#KM|V}nUa~3m{KegE|V@3FB6FqgK=0x6Q9@kc@TiI?xF$R{=LwX-InB3Z@}@k
zKR<<-wok#i8oLT*7B7E+v@@1dC!-fy&ML)oX$?%QS<G4NS*%$cAxt4`AuJ)B2FwO5
z5Y`p;6;^?CV6O2?He51}P@*n<i>$X&UW#d4AIJ)^_`)QxYr-V30?Fx!7^FXVef0X^
zWvtJ1FLzyfB4p82DXq_5My!itAG#BE(S>f2SE)3|<v>)AjR-yL!nc4{s?2d85M5#^
zgvExbhpLB-Vb)mWbX}+sg+1wy7A(uUC3h|LF4+Y9I<?~1SLJ%S<y8^8#cf<}HOo>s
zYuF~ztLr+f=7wU(b=MUvKCsdOQfY3^K30**Vahps{b<-m_i#b(0}}|uScyL#25tEM
z^}h+W%bxf(zQS{tdfA8bWXnbII1NANIZQ{&C8<yFt)K0MAM0_R49#v+J@30DGE!kT
zDmm_J^do0sf!RDrC|d(EC%eh@EN$Qp%-7^xPx<LKU}U9Z=%FA7e!|o3^E)Ttcg|gx
z1Y;nUHxX+2!z;5Wm>jE_$4ztS25bigb+GLadd1R)wGx_kv+d`W(ABVpAjDZo0jhjC
z0iA*pKDObkgiUQ8uOBnm-TU7ohk)b0D@MxuR{?}g9OZ6?HVpYOs?;hKYQAia<W+@X
zlXS1awSAMiMCuEBwG@g=wW*WhEO?XRN&wX(75d~yLdrPt_x|XV>Eb;8?36ieTn~1<
zfQPViAtk1V!}ErLy>rmS%ImSh_RPmO28oZRx4xTA=U0;}toD-<icdkJIgb{%;g%-1
z?UPTcrixE&4~*5~4;$yP15vv<`GL}c`GFaa%--w|rMNirDe>vK@g|g)(Z<z0j6B`y
z_*epA?yesi4f~mLFf+`<>%;|F>RLBplgxojJU4laDhv0uVWIiu>WB|t3jO0peOw{+
z3Dj&esP%>YhV%~OMhYE)0{6q#ZOpw|<#j9<b2Gs+R`Rjg*8X2j8*1O!*e-siVo%jd
z{5kJK-5N-3VZ&}YUX@2Qon|C`d-PG}NJYR#aA6`~Wv`0dFl5HQ+@pNfVBY}NFw?MX
z>u7VREaO{IB3DKD@`Wi*8BPnnK7p55rTB@wIlx>ma`-Vfi1GucNb2s_tDT2kuFo%~
zS6N?P9)=DnyF}I9sJ|NE?%1YK>9vYmahYs<D-;{$mb|Ftgw~K@)aSTa?~G_NSu{O*
z21*0`%HAA(`8g+M){FIc?V*-@f8z3Y8t_-cI$~0HJmh%fY6s(t@w)2%MF6%$NKW@y
z-*Su9y>b9vJ7lE?SiYPM3Y8emSsyd41dQ2Zr+vxX(>Wg7x83_DX17(CTNq#HQW#NK
zTxd|(R9Iw}YZqbHWS4ALZWm%#V@K`z=TM0DXEQk>7c}Z12u&}y?mc)59}#yOH|{fD
zS?ph&TAWy%SsYkgS{z!O6&*LWpmU@HLM$QH_?hzv%=ZN>R(QE}lIfO?Rt0Bj_D1#q
zEz3jmL&?Z;lQK~Jj|(Sz0xiVCqz`@ZXYRU7=8Lk2a#Tgs{f8N;{9KRk9+*w@BEz>v
z6LTViB9V*Mw4eQh_-n*%Y1Iw&S@l`tR`gj7S>ttQif7($;_r*@OHYg#+WE&P5sMdW
z>%5-g>-PIWq5te01t&PboapT{E_C!@<_^M2@=C!IDs$S^x{l_K{h*7WS=4=0;4{Hz
z%b3XhKUi~^UVN4BPRPwkR?9mII}kx5K@F&xs7B9>o*SVco+D5I&*0DC&*3P?&zJEI
zP!6zKDCTgy=qpL}(GO4$a1ID)p0&^m6C$VbFNAURQE2dKQ0}>%Nu6<>xlT}4LpuI;
zV0A=vga;)CX$KRaLQ$ZoHqUIH+n_vQ;-cE1?mXK;p+_0TkPp%{$9;(*j&1zR54Vv}
zAItcKG44H%Gu8>LqoAW5B^4#-*&7UTEMpWu>_*~ierK{1%GEEcH5~%T;m<yJ40RU8
z>{$gyTYubTGFm#6S7J;w`$ld%efY@|GIGy*X1uMJPH#y!djIxJal4%_);b``o9k?2
zcw_oXd_Xk*#%>)FP`doFT@_fkQXw>J^oRRmrLvWiVt9bXQruy9AWPl{Xmd2=$Lbci
z4Nu45T^SNhy9wCN9d=BISvrmR3Aib2+ouEg%*GazZ{#mpm(qdOM@oy6)PIEb@GdgX
z<!?uPK0lDR4hR+YjS6zSmCps{oarp73_lQGmDmK$S#7P|uVhJ3=iCT7)1T0;2CTw6
zP&=-IFoKU!2~ZkP%ut*#+OQW<{O}q{u0@<FPViQpRx>-qa4*n1sDtr>g;1zbfarqg
z%g-HL(FUVNSAywLVo@Z}=`aGGi=y0<dJ$h!b`N)Uyza>Du;{>Ebza3>1qL$)=ONoA
zF<ATM-v8_|aRyu}SxJfdQhZj+$@7e7bhp$4Em1$&YcS;aTHS&@dv&o(YB`%wjZoqM
zeEhXVuVzYkrt{xa-Eybam_T?vm$YbpeX@pQvp=E;ColJ@X+(wu9Z((s3a>F<)qF3A
z&*%XuH6PU0-8mkdU%jp;a#&J7g1L0O`(Sv;a}tX#9t6-IF$ak4W>a>g^OIX&Rpbm?
ze{U(rZK_?Rc2T>vuNG$)>pWNTi5;T}o!?B=hX=3pY=a|oba0-~?hne~H~C?|>{&+2
z3T(-_bxMm1>~@FgXll@*5gGXd89#S3Ook?C3<Ya2p-pwtBQP>MlyZH}-_nNM)&yXK
zkk9q2Y0Sdb7+{0oNvGKid+yql1z@eNp?!IbXZVb+J+y9C#Fn-WP^V^S1MfBMhJ1n9
zsn^)d!K!gCOAmE@3zw{Ie7!1$D>@0|+xG|5g|CzzD|VE2%~-x9q&WFbSr#6?nIbl#
z-?kilKKNr8*np7A8NK)9l;9T(PP54V6FR7?J1iVgt%1wT_s!*%8(~@p#F{)Nx<<8>
z3xC|qI=*n)^ZjK%aKLw~Vaxv%a2jx9a?>FP^?MWl#KDvN#KM!96PG%qKFGNV-Aq26
zJmt8d^sc)vYmpC7Gv$=vfhC&7%?=$8U~FA&$(%-=B7L{q$lPFZ1^6Xdo^5E~FdYOq
z#F<T8?EyFV1Hk;{^#Z3h2vOv_|C{>n++U*R>FT%%1vH`WJ;qy_|39G8NZ@yPuh_cj
zUq_c5FI`vVHv`;ciYUeUd)zVc))S{$j!A54eNs)XO3Xu}0~RyN-}>_|D9$f#B`$<8
zeWT*OCboUee=`%MZR>qlV08v*OHJD}Ne{85<{$9Iy9!!sOLe~J@%LPo65Lf998lzq
zPw`ITdR^L&ULAArI=mmt6|AyBIy!>ZbZe|#!9AP3KcwTlu{&%_mrcgZHPZgNT?(_j
zpn)w12{mQ5Hf)9}sv0`o{lQIt9MzKk!hV{m^eCqE*pP4!WWBj!zFAQ^Jyt($&)f`@
z7zkt=c#=wZa!z>aW_pTedTLL+S4h04XTFJLzL8KnrB^=<OxTo&-+ba92;?1jGDvuu
z@@|KGWVyZJwW#+IbI-B>jB@_*^JbvE+8GxqV;ZvMu3*fx6+2?MvsI;IgxZ=I3J1?v
zPeabW)ykJ%W~I83IV}Fb6_LZ-x))E#?8z0v1vRX-*){s&UX@2RUe>Q2@hyUILG5d8
z_Kg%STH>~i$J9r!yB|8738;_4zxnn!KRGrk;9W6xi&;0)Qy;l>KlC`OzdV9|^PO;(
z;9JzjnziL*S?bsOiEg`lRrqj8UL8`OjJk>G$ZaDGsi&Z}fpY&En=W)Ld^ej_pYg_6
zeZdLcjnQr>y=&yBqYX+!s8MJ6nxL~$Bkdv`a^MaHbY`!4i^p)dJ6z0<&2I0X9gL{-
z3y%<Af}DxBgmR?3*RYZXcGSgT2j(^!x;cO*)1|Vuk|P!tM6K+o!z3Q)+nTs_BM#ox
z-%w7<c9lTEMIPKMm2NScB=d|l>~FqxYe&sR+v4ht%HP($d^2)ryuiCc?{+kAEXQl8
zSzEShT*7O}S-TWkMEM37b%wsIh!5=TZ|7Zc&f#C&!2^Y_Q4Q<jZWq1lHnD6R!n>mE
zHUTzf;$7)<tJbm|T$NSxGCwJZa|W{KB(`gP?_zKHq&2J@`6>9YI72xj0Uzh1bOIiS
zQhYis#{;c@`{Ns{=$(CqlD*&CM!%?{`G8DJrS*tSjcPJzLSAE%ac}u1I~}vxUk<d&
z?M=PNq-PEy$xH?w&AP=yT!3AS^Q-faxUxZc1TTUFiKt<9<aAJ<*Im$^hs19y5wUah
zZf5*ScODK%;vV=)3ZMmN<2FbIV%c<~eP@$ki%kt=RgVkgQBR^zU>!)@Vn3zdEI#c%
z<@atDm4UF2O<Yw%xLv>m4poRB1L9-L_8rp12)&PLdu(Q%pEzI{A8Rsx8ctDt;c$Q!
zmQqs8sgqeq>1gWcXnRaoSQq2ZX^m)_3|xLh!faQzR8J+$V?E&aB`q=mG4obdrR`ee
zfRLOoEc@Tpml@in`<x-8b57dfrHoT6C5+RWd$u0YBD(&Pv{3OPuwEckO#|m+j$zU5
zG=sno@=~cfS-j%9sf9g(FSHkibrn9@hU%@R<?0)E&=#G?)E3nM=JzIb0$eTiI*8)K
zY5Xq=7ix7R4y~R#aAt&W?;Bp#_E`Tqxi89kRoafPiZi$WSgnU#6#uB#L#R;Mn|(1$
zFmgA<{ckW}5t6lC(R1_*^txc5yakO`CCB{bGC^ISW@b@CiRv_B%6jkci(6gTg4RRK
zg7QPFh^D_{cD|Y}v?x#mT0&4dIkmfo>rp78(n@h@<6BzrC4E8Ru=G;<uABJqVXwo|
zzIFj1^83&Scq#T$DOp+nM!7+SHbQoPNM&(B+>ySx)W5)Au3~amLQDO)1jIbMk9ra8
zewj2b`&9I8dY%I@>H1iE-oq29wNnzPyA!{e=;U?8fAjNp(ad^3a^A}x`I4Dm(@7_T
zqk(-S36Z?5j8jl>N?kB*Ri25b&5^V=h`H4;sA!eMYlx(2(V_bx=0&}QUr;`wW(RW*
z+A4Dy3>oy=0u8>{y86akt5%zO{L@{hITzM$w41w_XsKQCkv*imR)S4CIsEt2n1(e+
zO+s1Wh|VMKklVn_*7{)H;Pb6_R=KB*TE$#i<eY(;DQtmZBTZI=B!jN{5MPdg%f*_(
z44i|p)*=TDQ!PP`Ks`bBCk;VP9!{gAKn^2|<RdaG_$i0O<l%>EwFU+6{pUCy7)e)2
zA%k~FCsU|fm8ZF`vNsK`A8#-{m%yAkY^>%>hc!%hPEVSnUB3`MNKf}6w+YRf5AbHC
z2Mk(-scu8j)5nIAC#{BJSP^1Zzd^=db*Z?m;z(;n15^qu@ttazYTZNZiC@rqv_G~5
zC_YI_{Cq+pdFf{)CM2d}cj@>0F4WISZlSkI4}1?vkMD2(vO2<Eo3vq2zbU^1!sabA
zy(AiCV-l{vr%3CJ23}LHwQt`%Nkd9!hWNES5&$^{PG`?yaIfhRVVKwrR-|y}!@Xf=
zUFa<4sF?bJ$NTnWkH1Pg2k!xuV4`mppw*=gI*K7^6Qy;^q}dW_x@p|kk5N21%V<!?
zvk6Tj@?IXw!RK$ob6qK%spP=r9@%EvThi{!(?O%ybF*!SyDdL3vVAY0d?7@O`cBWY
zsfSm$ozHd;%-=Oc8!7Ez>^G?{>WawBjT~;^PrUDPIU)t6j1p^k2dDlK?d<ivd6vyS
zwLyKVdcEyO-Nv|5zChlu7(gQtpEEeNzH_P>@VY(JY!tRWdrEyha$nC`H)B;($+PMx
z5LDce(ZO$ye!}tNSqoJfRxJwi58RKzR2moy!Sj-=Z!!Kn-+q1;M2DPl;Nm`433_eL
zy(-Wl(qSJwi?WaM&-6m@#qx_5ygA&t=X1n!*mG2K<a79QbaN<kL|&|wB*@oGIF+20
z)F*Gu|5ZgDzCmIZz*YVeoK?!zz#yC8oglM!wIr`FHiKDyP^L-$)l)MAPg*#O;Hrgp
z?!FbKMTd5;y1&fA5BU!>25y~Oy{AQiGOoJ6$N~pV5;==JS5xTN#T5R}GHxOpBxUlQ
zvk1CcU&roCVOmt^=T&#yEO79Dm@(jA4T1sPSaqk#0*6exIE&z`^>ywF3)B8b8Shg^
zcR5|G=~dlCEC8}EGlJPAao&>Ylcb@4z%WH44bnAd(RiUONm=yF;|FaTn)|bw;P;Xg
z<9J*zZiD4Io>jioe~yb{j{-xPK{3TB!zd$YL75};BKc=+;J;P|f=7b6gSdm+QR<)9
zqt~M>qd4F=U^oyQJUhT_A(_L%wD0#!DsM$6WOh)%LTGkf;=WRz0~6Pq;mN*7XpVYP
z$0c9Fvf60=<9j~xwnc&(hFnFk)f75+*@S7)pn0qAq*>svlbX)|Sw`CnpGMmKHI;nK
zck>)|ypCjxT6?aRubNW0m{j^*tFb+~gv?IL57}K)`1FpcFI`baRdiiE`rr68pv=C2
zf<QkV^P;KyN1F?u`hE+0x+L1(r49A&Y7aN08I6_~=FV0%G}QMw#A<W<#2-@Dcgy-D
zDSDyC#|RNhwfJJLEp-ccU1@|Xn?`u#DqD9at-oD;u}Ww@)jvDgSn}*wFk=u-Q0#iK
zg}m`Q#t*}6QS*&=LaV~7W`BoXZro^XG*zyN<ADfk4zRDJE|W~Z+w`q2ds&N-+6@b8
zL1OsU=1C%^eyu+WZ(LD+157&G@C}v5J)6a%E^v+)f`2Uyb)0w=uP8I|!Z#Ei2g#34
z>YnKpKA=+3=O{1vTyM5+S|#!NQ<HGkJK2MQgK4c$=FjoF9S0?5b(xJu_y?$2m|18v
z>MqYdy)^H6`|LHw%XheMKfMfkiT>&v%6AK-S@N^FCvf6>PN<^EM9_BLdpjAC1gCt8
z{A?s9d}0)d2@f+>wXTn6A4RWrXQkd%o7vXN0<S<fu6D2eoB!Uq-`*uJj6AFWZ6+P~
zYyp{8Mjf8+N^TKM*(us~fX@K$kXsxPfX=PJgTTV*^7x7*AQP)%OcszC;VDRR=)kft
z|Dm=f{g1?)4jK|afP!3CBUQ)aTaTo)AbwMZp?wAHaOr4YM^Yu875s9u=r%zU`aNn*
z_3r~~v*n`s8RQ4u`5Q)h{%1up+S>4ukb@ohVmt*Wkuvf)Q%ltAF5t`gis8-X)~wdA
zAJtZwMn{|U54%dH0reo;hZg(0Q02Sg{#(1{disLOoOfyKFINdy9n49Ek;{G)3sz&)
zdR84TPq0?8k$s@Xi(GfkkrkH<4UB@1GKwxA+#TfdN@X`RegZ4s{W*KKq%v#Vzr|Gl
zNseE=3cYCS(tlmzFT+3Katr>_%2WJIPT!r~=e+aInv8ZOeum}3mIq{!SzdxMqh3Zj
zJ09?<yfJv{ho1UtFf<L%V_SjXg!EHjq)X~Lp?TK4b4ShC+WbzmO-}c}gp&iev@s#(
zH|G_Mm8>9+bh+)HkMkg*vd6^s-uKcuS^W;ulV(B*Zv4X>J~r&hGhekcBD@SmRhj-q
zUo*$|!kEB+4)U$m%~`o?cwBmT(ptTdXg<2!34fH*je{>Q|7oJ=Xa9m(iG+{uAYoQx
zl(}QC`E_~Oz|Z7^-iZnfE9T+4BvV=po=}(lo}@ZqiQ$te27qUt!xL?Zb{s$F@Wh%-
ziAmzGjcU4nO;Nt6usUzSucubUR*H#GgjMSYD!T|H&w`!5t734Xit!7%>_<@b0K&3g
zbq=R;>T%BdHuQ;G3Y+<x1TvE)ds2rG?LW}0YEtFs{}zZn_j%w$=C%CtRGcx1bV+~u
z*<(Hp=e<O)uG&CZ^nM1S`vFR5|CQ_b!4UkH*A5y|t4ycj!b}~p_3rw@?>p;n)QWo#
z$BWrk?Div_YY$i#%$F=+sq|#u6zz21H0<ff6penM=T>&QrOl>}EaPmYhR3{yp$Z9}
z|I&MqwO{&IEIiqN3FYu!SFquSF#a|F3DK$+)sgODz(xt~9DzPQ4S^r_9ELEuFwvTF
z-AWZF{EMI4h<hD+Wy8$3QC=TH!Mh@M?l`(cx>Sw=xrtA^JQKtZ9wjc^mNh!x#;3`v
z`GTA;_$zKH^=j7EabGnOXq89L_nd1#9Iju4mk4C`lrgB0Ct4k-_|LxqV8xqM=j8XJ
zyq7E!p65(FRI;*p(4ax3A>cy2M3oQvjK#XsA@pyQnEUdt^-s-Q9x5^8fk?guG6C;S
zx|I?j^Coe=+1Ey8TjOC*S0tu!!9NK$1mwFA%;p<Y!YXvAc5lckdB;7S*<4}Wm(e%D
zQV5vTv#K2wcAwUlB1$n?I^Xl3iTv=oCgG9*-s3vJAh*?gDp=6qs+OHsb!_`#!M((r
zB&)8gv)UEKF4tqC*}k>5Z9%eJnz}q@mc?%J56M|=qi!+xw61MwoyUT_V^qBfq5wJf
zwhgcQyr6U#t>zvD$(?kP1nto+!NSj*eNbDgmOlUs8fM{t#Lky}0{tt+rRi}Hi+tzr
zZ~gp(+w{!}VN<hz_AgX#b^XKJj8>rZQ?Y;gF0^kA06_IR9M6c_@xJ}Ub2}gX9BAK#
zvVU=#v{^Z9QfSZU{P6aTKP*5}qKtl0eb45g$EnI@&Q8w~v>@i$E@la{2bu#NfYv}O
zAn^FpvBk0DF_7MY-h$pf$2{j#jz!Mr9H5!GnS+_NnVs2ZGvJEl$`>R<i{pxogssFU
z2`33FiOgP`0&6S-trW4L<gF2G%jwaQ)akg|N+iWsC9ED+1FQvB0UM61kwjmW^!4;L
zIkh<h3<fD>(OgC;DO<y*mNzxh1|Bt3mI9++Ql>dd{dH5z=nPtGZf)>Jsp16$?WJdu
z$|w!os<&;p`wg?|xa_TFGRiItGOO#Y5BnFg>v;CfXX48?44~DcB3=q5GR}(l@b0Y>
zk>}tAun+hfm<7BI76gOAPGAU_cY?uQZ)Uj+)gZhEY?VDMvhfN(im}_m%@!Zpy>SAN
z1~-Gz!N0)PU|sMf_zjp2>DciR+zBQESAns>>|jdpd+-ey4crU10w;q7z!zXua5<P3
zyae_KhkzNu8(?j4&AgxIm-;wvD@2XS{PKaM=i!0RJYG$vrO=pD;?g^~k>}V!^}*>u
z?mS~npOyMBBttB!wx4A_<sjNYMAi~eBR2ndpy9c6fIc5nlWEm3=#;a>3|H_xK6soD
zsZp?u9f8D&G5gA2W*ywj<5W}F@C=!zx3c*9Ultye&jYGKHpfHaY5q)iUYErOHEPT0
zd!$(jlSl6FTStRx>T4i1xit|rO*Jt!c{Q0e(3)X`Bbq&$U7DS&KUsTOTUq<jA`~L2
z!l?kg_p=G)YVCZRW%~}R4hIg~4qFb#2kQrG2Zsm8GzT<mH2YbrS?gJASsPi$#;e8$
z#@oib#v8`Ri<^ski))LAi#wu!MAt=+M7KmUyLa-pG2d%}#rl#rMzA)gMvGG?-$Iqt
z&awpG)4DZpoe#4Qv5!$^@bTIhkM?90zpruK-j;PE-{u-HfYfl<IF5eH8hMX!_1r!f
zn9p(hUfXY%Gsz59P&>|gd>`T_zZpG}9>>RQBR`szb@Lv_m3)V5$RNFj#m0ZMFsuAM
zz}0i-VCa3C8`F;0XmM7}o8{y^V&jCNBiE*uilEZ^Qb=iTX+&vLX-sKeX(n>N>aflc
z)gIL@)lSBrjJ=GljQz-F^5&Gr6u55FOtWC4AiTcGv-z^|5{};lZdPklgO6@yxJ|m2
z=ZD#s*?+Z<L^8L6?c3~w?W^q5?F;N<>|2rCs-^bf_6_zq`#<)-?>Fuz?K`~5$;{x~
zRBpO7)~gT_iZcQ<m^yVYvNVmjAvQgS4^t3)4O|VPAlsw<MVBTLH|X~0V0I?;h)Eip
z3FLiLvRKzd?JBh6G_;fsX9Wcw<u2wmvAU}7K-@By?3_xCTmXws4P&(KNPbmTZdZz(
zH$x`ra2AmNQQ=~F6TlU;b2KED=F4>DbyU1q<FuT;N4}VVIPz?2Jqm)?!y)iocm%u&
z9s|#VXTqWIVUr`eJ-S`G9mpTZ9%Ku$4{oMtPHjwu>ov_b3pEPC8=64PSB+P2f~MGJ
z^+t90*jD=4#A%tgGK6s~duIq|dwQTWXO<0SXFAkU@11?xymP_8y$D!@FWoI-EGaDZ
zEkPG;&aPXgL|>~9*6cK$ws;4(EO=j>Qf&(i*h6MnV4qDJS|Hw5-do->XY$)ILz!tp
z0zlp6#TMJ;t`=tRp)=jB@)1N_!+W67@@R{g_uU!(7VQWi9wc&{)pwwDrY{!Rx8~yO
z2l)X7L))P7&|+u-v>ciUg+o)JFq<FHF1`i6Wh9qbOl?14e@(2Iu9MOGfG)LfAIs~D
z@18f6Pli{9?}C?zPqVj=&!FfQBo`77ae+iYiXjG&CP<M@u1$nZlTETsxlIU?`z+H2
zY7=YIz7w}ov=h2hyJOt;UV?ii1GWh`UAk$zHxJ0ZzrBe$&D?Gn24=3XxBCXb?%Qrq
z&p1yNc4EhJk|ek#vLtvUAZF?9{DE?hUnUq<GU@wa*=9WL76FO(+c%D<fNjvwak^QG
z8AO6V(DJeIKH^6E%w}tBBzBu;*es!4G*IVp;U4cM^Q>X(cz7kTUE)dO@%KH+4fJfx
zdt{j(HeKpPYuYfogXgpFweL&qo#|ubgYW@(!+m|d?|d+PI9u{sH(C>0CR;3yMS+V(
zyC!=kYbJ*#J4=6-)|ZZ!wwCtABn`a~UH~7sx3AAo%hq!4a{RK(a>R1+vcYoGauFyO
z6ai`iC4<UAA)p#iCI||O1+`zrT@_u0Ue#V12RFSc?=bv9DvZ5|*7nt0D*Nj#S`2mu
zc`cW%(RlF>Un$tvHZ)Wm4s3afXr8o>Z_8g9zlFUr)i9{6HJ9t$`|5#4jZ;tRz%!>)
z*{~|vx%Txl8Y|A|_4l#$p;z44^5oH+Y5H&L%yl~#zuI<oePu=)!qFuw<DS!~Y%(|M
z9Q`VWc87ycM#C+v>D;`UHFltKX5b$=w&r%{*Y*PjhPA=sVa2clSUD^a28X4>V89=+
zE};dXWuXC~5sJ%^vtIw?wt_aYw&^yHwwN~Vw!=1)w$?V(w(hpiZHaAsVfo`)X_~g2
zQ`p&I5a~dRqRKaRYes*J){Tygwv6@>tB3={HewgCfj9<i0`>rFfJ1<u?VAsrwd5RO
zU?g@6_EujXS{Y!G*HswCje{Wf<Tx;$E3E{sb#z5`{SMo}VI@=J#HASJjHb{ff5UC8
z+1TuCvi7TsI}CvXB0J(1)$nRO(O(<r;tN=BxaPYTY~KdmiUqVwY{K?|tH1-`HgF4g
zjKup$8In42E*dmKodef$yYj+VvDGOcXPFOn0i|Yt0ryVrWAx{<e`l|RPK7QS&KoX}
zXrZgC)2j=DbG>VYyS_Wt8|Y2<qxWND`$YRxdsq8H`)K>`_TKiT_M!IKz>dJVz~R7&
zz{2mO29dmx4swR^HT~L~JlJH@++Q@N8jB1xOMhO<nMC@KUcA{e<8QQ;{XO>+OHNx6
z=gID=iNQ_NFuqQa-IcT{%1^HIr-<A|6cw2O_ZNey`XX)3tDmNF{!!@UI;1ggsLc3_
zZ4EUWZA~>>imGkxen<YCmfMdMBzI(AFs&`M1^y2H*)7)>sYafS6&J)DM^uSc8^pJY
zb&Z-Uxg;4Pxgl92St@xanJO78c`W(VvD)#yW3D5#BdH_0Bdg=S<7>xyM|Fqt1j8!+
z_47{2Y{>`7JjqGPAxVTJRPss^Cb`nlAt`6>ZtiEUWp4P2CXM1d1_!DND(CZ3)cxnw
zs7B8bsPN~$s2I<~QTv{=qS{0%RTT*5rK#OUX7@rq1-cY9I=O_b|LPryG$L!@Inr9p
zYXrGGt#|e^M)r}bvq7{(^Sspl-mjzeMn$EP!MIGdTiU#||IVz__QIpC;>mltqY&gE
zjw92>(njFlj`hg(-@O}AtYqq(_!MKDU<y5Q9&TjaG<%u+{k6{Bi--b|9dnCo_%&YZ
z{~cK8lOnEt!S~gDozfj$Oe*j#X&JQxp#zNrxdWL4{Q>a-(E;rNJq-;F5e;<~VHR-~
zQ5H!Sy)mINjWM|~r7?*y{UYfi)gsX%?IMNfOHpD`I#DuFqpsBa1oF<v)jzA(tNE+7
z=EA}}F9~$fQ_=Na=wZyF386Q<XutrWU7-`aAi#)4Q%4_5iX&E0lE=!vPZ3rTWqwT1
zP+CerXO2<HNUr6uGn**LS5P`mcw`Pykxz=|PS@Zqu#_LjO1NRhQ6^92;xsU*F0}L?
zC`>441}J-`9&o<bcg^4Q8YoVvc`cqqMJ%n=Pv;uek}FvxXs1ccQ_N*xSpCz|W1u-9
zhS^BDKJ|cO-pKXGrt?5mLL#$`G?OKkRp_4=qMNwh(vKQ!ABCn~O$kqNO>s<#Pcct1
zP64JQ_=Wiy_yzf2^E2}^^0V?w)V`_}uH~xbt!1eduVt?lsAa4L)bhB$b!T!Hb?0!e
zCpY7)OVLm%v4U-tY?YH0>A-bc4e{&+il<w2GYx6&Js7#AjieDWaA{u|4C!#0K514N
zn=kQ(DTb7F4t2GLqlOT}N5fo04|{>4>1(9_yvuhktmkb{Z*kv7aSe@DAAr7Dy!=;4
z+u7M+74DG2XZX|$8MNbI`1fZ$sDJXR>bpJ>=O^GKzv_Pv|I!f%v%uCm*OSq!*37fi
zn}@3*0il&Z(@{HpQ1;c({OqM$7OY@-!ojYFri!K}tMc3sovS<L-B7;OFJ7QQb(z7-
zp%kmWYMb}=P3BDwP1a3zO`n^9-j?29ye+&P-&aPKYuUHejh9rGl#7)9{!-UmE@i*C
zVD4B|Zv-eenQ^ku@fa8RMBAViLB$Q@0+ut_*9(ks)DY_?>(~qEkLW_DfiZ^r<s&nK
z`$YTi_Oa|?9vvbMv^7W|N!i&9^L|Ehm6HLe%y*^+=}2{G#(pMq1~79sqc8)Vp_rMS
zLCu_FsoO$eJ7Q-p6xL8W>SiLyYkM8>>dB4ZNO!hY`}G&|=#Gr_E{G(@nR;`hddE3o
zM7^Wll&$uBtzgKAgWJM=eNp-HjDvj*Z53@zcICwax<hyUJ4C+YFF~MDb@}{DM2cfy
zy$!$~ZVq>VTf^<(pW#4XOW!ZP7QT*v%BVvv-?rBAiptVM5%_PXI{2ZK@8YsKu&Mz8
zI5fF*^3Cxd7ym@xpgwPNh;wO$WcjQCB0z_Cmu{C)NN>6OmqwTHpYpz~t@F#)$O)OX
zgvD_k!Cd&^=S!u#X#eFlOS2ljOYS?c|5(6GKxe>wz(~MkKwrShWB=pSW7p$Cz$zgi
zAMB@)E3>8naL3Q<-g5?g1vln({$95Qxr;Q@EP=)QethnEca-KjEJ98*1jfVIne#jl
zxuo5pp`g{HnWb%@0nrlB#L|w@@X!Kj!qp;*e!p9N=^6c=g_aNO-Iwrrq*J(_27r9@
zH|Rs_v+5J*Q|+Ve^Y3Hq)9%CRv+oPmK1dQd%MMcu(>|PfAEQ<}d59~rF^X;zRkJj|
zd*JE`xXTI|CE96p8+^ZybP)>>%F1#>H0>{fAa17arY@$SW!Gg7ac6N)akn=2HW#{P
zrV3-d;L`pAcRORBRHdmu#%{c$+&f^mG4C1gPVaf|5${RwKJS&A{+p?ruA2q#RbqI4
zg`Zxo%9<A3{Y~D`o-6!oMPq5_^!gW&M{~3BQib^J59DsHqYT%PW^&`93OtIP1<%9g
zOOqXA3KKo!S(651kO_fttjU-$j|tE?+$jPuYqI*rm2-)zVcF3Yv1AIG%XSxPGFqbj
zDL-p9D=@1%OFQd7%Q&k&i!*CK8*Frt(tNfQ<`iahIMWp4REjvnZ{9dU2Sve`mUfR^
zLGZi9kRzh2M&CiPeN$&1xX@yjFQRpS8I<E@=5FR<212rkdPq1+cuKgnySKa0`!GR_
z)q|n^dFQsGKCuIzue`)8)F&o4?JnHCkdtCxAJGTM>#-sm>8U>fYXOJiC*Q@i)Z3ur
zc_&3;BC)?eUo?tIsV`2h+WoEd6%jLmIH~8@jPtEiUVZSk7Q=xc9e0MGIrw^t-9g+S
zQ4mhZKEwzDhhRYZAU2Rxh!8{u)|0u<eM0V?Y#O6?EZ}`;3KKd|^~r20U&cSyJaz%b
zHmm?PX)n~gpsjApNuXX8Z=qJGY>a7`-r=-&jA`lYA)e31GCDA-VF|H&c<SkU*AlW!
zbleCU1nirfyzv!k$pRtZ`%71lGt+a^zou8qr^^@OC*qglXKm+gf9Y<S+KkPDVg1l^
zJ3pVC0h=pte+#pT*-iTkk8AKP_|C`gq3!ib5wJ_>F!QXyk5hcGVHdE4eDc}=9K$!^
zd+;?l_m}ftf4nwwGdOH=c5DCg;s)KHvCU;A2{_ZRYINy%Exb|>oNYJ;>>&9Z*WpL-
zE%?6gs_%jCw(qX*2H;%fzUlFKV7%Gx?Da)J;>yw0ZTDk-`@qWH@d^C}{ngd=-Gj`d
z=2K|kg2aycjoy7y;AG%n;6mW9z~#V!!0Ev5Kt$l!)A&=*)8f<Mli(|2f!n+LkVm4Y
z#=t>|eX|puJE8lmKt%ig%2m#p*}2(Yv#XWUl?#aziA#yI_Vf0?^yo~%i;_}5*nZ&J
zKEDlOHz)8yU6bS;C$+_Me}P=)!0>tg5S-g#YtHbNHVr5LIVTE7C8aQ#Fs(3&FnuFw
zBUK|&BW)vv*Gn&AFFG$WFKSY>nh<X(gE-8RuM0n<re5mfJG^M@@H7{yq!*@WeA!6c
zNY_Z#NbN=FMdL;8Md?K%jH~>$sq?G3rUvEIiwi03ak_K#?oP`}_BpBpOgcO|0;B`@
z5Sh;3tFq1_!W19S^uB&{=JVq467gd368B>F67XX50(kLUzrAL<7QN=U7G%P<3O|*u
zCM41dt9>ogPviRSKG(KLe2V4^i2yneI_w1u1BiBvPXB@)BL~e4edPs#OoE0}(W{T7
zTHp9z`}dPphqvT9vr&G*uKOk;tsv7UBbNI(u3^j1Pn3Z_5~h`#Oh~qXn~j}~pN*AG
zV1jLew}iQbzl0-(D~2UT(2CuP7u7Yt)>6s!Aymi0agI<hJli5rn5u$6C>+tH(AC$)
z+SR%ieB$i&Vd|w1xeuiei3qMrSJT>8XH9*|na~Rh?K!&3Z{2H_jqHn5N0{_@^aNL-
zcil2;zfWYnL_{gn!t}a6dhz*j_=)(j_=)?m`w93l`T_iS?%&=s-HYCH+zT>9S}L3}
zRAUlp%GDCd^w7A--^bhLi%-zlMbSjiL}h(Hmq%ylj<4#sv}EC>H;62gOY2W5dZ$II
zDbG*j-$PoZ&=T*=L}?dUD=)&Jz}Uwq7XR3<Vad-+lnx%2(~3{VB%6=Uip&CMMP$Vq
zM;ga0eqRJHMu|p?Mu^6?M7G34{+$2aQpBY!tE1^SMJS+<tr^HqRURv-fcUBKv+pPC
z&(`0;f1KU9L@2W(Mio+j+H0~jlPyIY$&JbL$nq$_<baV>d26=33#5)Qp0cs>u?k2E
zfZw@)Y~2||XtSdVe{yPaG*gO^iP4IYh|#x_wo<hcwbHgy_`mcg_NVhF^QR{1t^Vx&
z&LH}G@u!8f*Vf?opC9%4b?NQFb-myoaIadA&u7%CwK;tUUO|$~Snl4LPahmO>q!t%
z*)b;HO~58mOVLXaOR-{+Vll1XTfwy7sXmKUJ<e%3@Cy=Uf=7C_s*+!lA)>P*v%%RB
z*|8>(CNWFjm%vL=V$os|VzI4}tuayS^M6|!xzu`eTpSk(h5E8x0!67{u|j=_b%pi5
zb=LLPzrokeeq7>|IT2%hsq6MGENx^f5y!n_zj%6h`e41lU&lSiee}IKzs!2f`Ur^E
zL;2%#*gmik?}e&Oy;SejTmR_C7r+r962KB59>5+T5WpA!2;g~q`^fYt`pEGp_*&VL
z^^~~!MZ5-cEtX7ImNUzJgzZo9-&wXQG)gooS&HW@=)~O-RXs==r*}E}%4N)HJ-VM*
zt5StC8{-<Y8dDn68xtFIypp^!yyCsGg%u+cCoBW1-xe#DBsS;2vr}zO?6ee}k8>ar
zU>Rk7!(74Q#N@<!#7xHmVS=!lGB2~p4IEgSYNaqGl;jKADP|;&=1Wkj&ah@CIu0-n
zd>$YfSl*O$6@H(R^<k80CsAdfjwx|b`H1N%!6uO+AvJL}K`0TFaFrOFpq|K+087O1
zSQoJ~2{5t9{;6gHE#*U!R4jUQBIhVFCMqVrCN?H|CLj~DCG(~4MelByZbWZ5ZtB%O
zrkbScv6eFKee_rmk;!fvHQ0eg%}gUl*t%)jVt_8_XGMe452r?_GN)>%LZ>#TVyAL&
zF`@)fj3@;dfpU*rm+G1`JwSU$vtlK_hF3q2JeH(d8%+&!%*^y*MS8RQdodR?J|N_h
zyy=R@iq?whiouG`iph$eguaB9gsFs%gi*UjyK%eb*g*9SB9AM)U2HJ_{!sH0KhQU6
z>$E|^fDS3N4z18x-TY(zmo|pf?w^EmKIrx%C3<A8c?D#m{7HjCdRDvG>52`5cE9p9
zA}{)B#wxiCxuJ1z3Yo6^3z>ThDHLu2WACqu`rUaS5wZ4`_YL%!|3tHc*FXuuA!JnF
z?{I$@{{$v|glk_T7@t}>8(Si+oYG^FC0zr5Tn=3yL$+a+p9~ar`;cW`Aj_Qj=TcPv
z5r&aM&NeW%TKDmi?G6`t`E`FA6eyp#2Xd0@&XCu-gS@h`kbjCgR()(az(nTo4@RmY
z$O?#ly4>P9U77C+gyIDHZnn?Ld4Bj6D0G%;X@V^K@f$MR)8Go-77&^D9*8srbRf0x
zf6_pYmqmogGs&R``hNV5OlL@J7vo?;CdK!z(1oG>Z}~nQ>uY#b1fLkAt~H@|x#5NG
zP+^V<5JK!<iOx#?|4vxVIcq`>)n{Vqk+sf94`outichvCkI%Lie66aj+>*Erkafyv
z>VZz&lm2zeI3~Wa+a^J?BPTqD-iZH|%Ah9<vm+;_FT8oJnPg4$T3uU>ZQ>(guN^tb
zAb+x~QU<fET}DBuh^j!YlD5pp0t3016a0kJcDf|L_+w;MGX!KEGwMR$tMXYWO-j#A
z)Dm6tABJ+OQmm;>s(MYH6SwjE%f20XMWoCpD?1rYT*d!cmSN;Y{0BazdzFkQY5x3q
zN&dolMgD?$*?aqpCuM%<{0Bdg5p@!7yL!T>l<jt+a=Uus9HlcpS)&Zc9-GN~uHO)A
zz~3f*2?h83c_}|6<re3}aXEuge4;g&;Q^mBKk^(<=A{rH5Kh(<*}{KDx(m|(Tk%iI
zDcNzs4TRxAoD-XL_sZaJn{-OyhxmX7GI~rL?EfX-$Caudid++s%ZzHonLWVo<xjV>
z+CBJHDp}h(@*NV%uO3KLdSKtJK84M_QvAyBavjuj93ep%$aML=ozP}NBA%N=jW6Vy
z-YYvG`O&^r;eIFZ!7RPUfBpFMJb@v*Nb<4bUd%iA-oNR?WAMGqje@JRDVHA7_lcEj
zj4>xn@yQS6uf+E!rF)5<CzX4iby&~J_a`R&ElSraQ56Vd>Y&?}U7~F0A6oCW77bIT
z)FHA{;wI&alvL=`9OyemkJ0+8haHjuzAa+!`ups2SVaUCpCzU2Hx8Lhi~hGZ!hH9X
zzoT!Xx1;N$87cdC)hy4gaV>FeqOCqy4_gk~a9NdEy`?mw1W@`?+VH)xG#+hCapBug
z`}Gj5K&j4WYS}U>Oc>Rx<<i!uQASwWD^jKDKnCxXaxq?f<wVpF1?V+dcS7!S&=6&y
zqfn2q>BU*M`ui=71Q-SCy+eALi(2Pg-`{;=qVKP^YGR1zQon?-;f&pTVW{6-Cmk@R
zOP^Pi$?CHB(5oM_CG1*?5WOyqH;{ErSKTHoKKTIV6^+TG8CxsrAQ9&Hdl17R>XBzS
z!?901-M`XLAS-o~%b-HKk)tSmpB~77#fG+m;?^m8V)B;WkHC*UDL8C3d{yBU%AgdQ
z{_~O!Ee*Vs;H@9zQ^5j1u*%RzexTI`dyb<tOA7r#eK04)4fZe>o5K_g9$AHU>YnhK
zQ(qfY(%#d|p#;#0J`X@Sc+rkYhxSA(iXMP<u+AQc`bg%7^N1(<jG(jq?Bn+iTn$|7
zuf%UTRXcYBH{G$-psW9pk+SnGy+|uIRB!E^Bg-^wveem!Obynxt0VlMWh_}emvHwX
zQse2`l@o5ogi@@XGh~^DPDVNZhZ&LG>Cd@HmTCCpzOxUl8mxQQL%0<mI=l8CX8bz&
zG;T+%mgt-jI?0s9vc``ERT5V1`rmCL&3X)1({|4II!T&UxXO<PWfxZMw8Q@2ZTh&d
z>lttAF72LH#UvQPV?#IM$DKYjVU<1RG!_8iW7bi+TCoe*aXFfUMvB)ZrVhiOjx+)S
z9=Clvube2(TXP;BzYVj)A3Gxm@NrVb`Tf0`{@DKBkKLBNKejp>GbdZ4EECb(P@oWR
zzW-ep>lEO=lXpiicKc^nfk)iu;WtX>6U0+oQ;`i*AeS*ZG})O%ib0K^kXsh;Tgjbh
zNtXVdVl?4K59vD<F2bQ6^iCo~&zmasEXFs)df)eZxYytO4f6UR%4kXq{4UcZ3*qF6
zqZmkbRlOYpCLp#<z4akULIXxyw5NHe8>e*M?S6{l9AB6q#5~_;dxDL*QrE8}$Xx4;
zS%n76T^mH%Vuz?VxlcX4p)D%Q+{cLog9@7)r|dUneo}2*D{*e8jyDy4W&vsengMbF
zCIKn|dXJKi`i~zTc^_61Wx{0ROW8C?*^{tiq+v)35^NYlnIcC9X?Y}muV$}{T<lM?
zclj@MKCl&%xkV;@l9OT=l#7X!4wKH+{X;4rrn9E|g3LuO<fq*4ia#IS*_+AyBc*!3
ze=>eokfy`MmO@62tyWb&r*ptL%KnC<f~|tniT#L!j*X5J!fwj3%!VJu+}qTP)+^UL
z_(`>@ZSJE3(zS1RRAR4cZ+S0muR>HT#TDrl1p!$sxjLyj#TXehQZKT2ePms`7aBE2
zn#0rf(Xa0MTTzv;J`Il(n-jYe&k@%V$I+W3PC70+b~+vi2ZY;{&GgMO+je9_6e#K{
zYK+W`t4+(V^;-Au(mF<OY*Y?eJ6C|VUr`d9TQb@pLxEPY=3X*Ofyu7Uw`3)&#A==S
zT+tHIiUZ9{&hVtXL9DG>SG9Dl3O4qw!qX%qD^v7o%W1-C$?3P#`cueh?rFqn(`oW)
zd6DLP`GGb*heFcEAp2ICt5j3jqK50B<5q>MnYWs^rnj88iMNWk-i_pq{>_IQts8l7
zeFpXcZgw_y4$Tx><#Xmjq;us4CgTJyI}SVUUAFgzt}Xe{{C3MC%Ua8ymd%zGOghzC
z(#Z}fSsd?8Tnjh-1_}~NnT3>{QWrVB^-uFR{~zw&J1VN?=^s=P5D<_gQBcW}1SBVw
zBw2C}O3pcl5l|2ikStkp1|`QC5G3a)c>sw+7?>FtW`<$MXP<Y&AG`Z|_dI9!_k7Q}
zaBf#u_r29sx2A93>Q4m@RVBAPNqS<MR;CKjtI&H=Q~uqiz^2Wn=snLO|03U_fP|sf
z_ur~Rh-6cCe>LV*Y5qWiv-;l}Lj|gZ!}>Jkv3ja$N+pJwdVXn!GzRSY8kGk6(Ff%R
zt(D4ibqqT3l^l9Al@j`@O@)Pe*_FDLGnK-Xuu8Scs!GPn<;vj7=t|DY-AcpCmXgBh
z!|Bdx_<(IirJku1mq>=B+EvNaG-}#TyXYY2pzt8}p#32Ip!OjA;QK-5LCHb<!8bjf
zEK`%$CVG{;bEyYv8YSmC?vAa`jF<G5OqR5R8sPzsT8@DI*ZU6p3j03$W{#CUC8<wV
zd1ds2+TrT^m(yw`hHCDqYy4e?sBdtUeb}^NiTm7R-)2dzT<oAh)vQU=3s(cFxiDWn
z^Ex+!mWssk#0stQ;5od5H`><wThsO>0&452%$4j1X1?L=uWIz1XM>tlTn&Tg-uUXQ
z7Q5;DmnT*xRt3*q9Xvvm2fdW3$<r;H<#AH&s*o*_t&uH~tpgSVD}e>T8emyid01gs
zZCFW|DaVr${t+IvYu6%m{Zc;R)J$B?8En0Saj3DkvFTz`y|pdpaL@?BaMVcuFvp19
z@Xkp3@cb~HwzcsKW9`g(b=^_{;k3n(PTP%o8)IE#XJh5XsroHj8QUvcdD|jeD%%-b
zZ`+FcG@(kDhC{u@{d!^B-4XsYbG{C3zm7wT#ol^O+ldj2w63|2&la<!<JILI^cZUT
zzY03%Fn~BJD;AzPFFjL!Hh}wL*p+p2?3<msa7E_SsB`)=X9lH)lEtY*$8jfq2YzSV
zOkBi5!zg9;nWKrwgRG*gtt@5@klicc%FIc1=bdNVW3f@wE>4<`n$F`6<Ien!wN7ph
zZqCP!%uaa@dCnG&Yw2;r4I{AO82}ZZVVd&@>GqD7eH%#H#KLmTY|S977-Mu9bGCLC
zezt+jH!yUTd3JeLa@OQk8d4Qf7E*_Cx%_Z8vb`|uo{o!DvBZ{R953U}77F{%wzg%q
zueRm4i?*q@XSTh!E6&oqDnlADdYAiW!rQwe0%?|fAnmXYjKyW|8Rz!Ih-DgRF1B%T
zN!k_V{@WzYpi0DH%%p6-F5U^!G`1vqL~$f|MC4lM_gt#_!HlMpeIsm%{U|Ga%FWTg
zF?gwAiDYSH$$2SzNoonbq>KZvrCnNBiX`^@(D)cs`0b^3!F>^@-A3-C*z{>PCoM-U
z=Lv@iX934LCwB*T=MzU3r+kNeXG_O*gO5+@dCs2L&?tPUd};co{HdWh4~Awc78Sb_
z+Z@YEGw?)H4{mT*@2=q|eRYFTy-`D6{c8QEG^R9CG{H3XJp6iQwXFu84V#)juVR&P
zAJ;API%~xzV|;bYfwiy8CM$d;bG7Z~+I(M_n=L$asutJv1a9j5oQq|oY2i86m#z-b
zIqlrk|7n{0Dx+pZZI_`ycfV0Ga=hC60MlMxYq3!6Jo8}c!A$NX;()-Xw_OnT6ex++
znNHX2)2*hvDYukKRdsyrsO~83sKCW&)dd#^R|XdZ*GQF98>;facu06?(hgM3OTJH=
z?AP8k=;vX4V)|s6M~bK8Ne2)5387+qdvrTz`)<2odrMm3@ZoT$sxiBEMdhpk!;`VJ
zaa?++#(H3VTYb&htL^W@RB2slcxk<9)@dne!fCKHwKV56^=*S~&25YA#bJ`P44yju
zwdzjYK+u`?_RKJCS{)BL{B4(Bex1N958SCs(|y(y;THOuWkGE3PgtsEXvY63lJzPg
z%oy~@X?AztHt1#Dv@?RB%lKp#jnEG50vfNE$`#6$$`zc<k?%z#tZ_RHKZRL<iY;e^
zQG8bkVOjtKzzcveKm(u)PzG3Dzq;1DetB&Ic+Fm$Y_N@UrredY`t47w)0&3OX{uul
zMf95VnhbpneD!?|5&EPC@p|!w8v0`fe0qF_u6myO%laMqX#L$vegks~5d(=TjQ&(5
zs&c2Yxsp|Xpi)y0VL+-!Y8bDtVKAmQX2_>sqc5m$sxPG<tZ!e%uV-G{Zs6N+pgDI{
zsjRP6WuezqEBW*zsg69bVDjtJa#G32DJzjy(iie8lU5Fbjf|3{=233)`EMq1+a1Kz
z>Fr2KqHKGk!i8NJ{YcSK-cfN;JW-G+)2NOp!l;2L`>2dUrCz~aBKf*E-A`TUgw+}B
z?!uzjd$Ym?UFiMp21hkSkwlF|IY(tjNkyTfl%vX`XrmUQBAq;&8YMyP-%PY?YUlMC
zaaq=m53GDU+Y8!D+Pm5t+N;_-+UtV81r-N%22}<%2NeXh1r=pgt<|p8tkuaHhJHt>
zA`l0rbN*E<dUCa423Pec4Mc(V+fkAGba9_lwXG5Ah!BJh!bC*3OTSCE%P_PV^%Ajt
z;5;W*b)vUk7p8aBh*CsA4)BV8af$3OlEf1iEtLy1#2XYX(>?2tC+)v)-SK_qm+hhG
zIXz)KYrp4Ks^@&Gm6@m;oy1nN=R&Kyw0);T=i5%VPTNlB5UUWE5W5h^5Nqk`q}ku|
z)U(ucT+Yu#Pz<{9UHzt1wJNa;@xlEK{UrS({m%W_{Zjqte&znMe%k(p{zwMT_(l#;
z={F_qqS~oBI_GNK$6YIpP8^&~NoiMULuplMM`@kiH@jlHPP<CGX1fBrHoKyzs>RyH
zn#DQ^L+|f9s$+;OQxSh>=2_|5Km%C)j>cGl%G+TPnlG{Hsww@&VwpJT;00<?b`6bE
z1KsHT^8MC|fms2k>NZPQ`HtgQT-JgJA;)(Wr(rRgENYG>6?>tqYK|6ehuCZeb-q$R
z-Li_2S=R$$(kvzQty1opYR8^Nm!+qkrLHrzj_W?-K2ttFeO7%&d=}u{@L%vz_%yuV
z$B3t5tcI_guM(H)*$L59Y7$)2B5Iah?ON$tb5t&465QEb)(rA1_iOYk^lSI471i%}
z>{OjLzq4?E{)y9EQ@e?EP1C$NV|Dz3C=UL&dBJbqZ_aPwe2#2BVK!kwb8dW|f0lp2
zZPu%4xv8TG-L&f@FmF-OWf5F;?sgQpG|)8RWH}G4ka?yy+O~7cJIUB_{tLn`Wzp?C
zt9PfkZD_^m_$iABi`c~%^qBmPHtc=ilC-^Mrr~I6;7rJH$Wlmu$XbZXtV46w>dsdQ
zH@BxPUzW#mclf<q+9sqOm<1EF%SIb^@L~0Vy`z~eV;wu8FbS9<j0WZl<Aa&Q@L<+3
zVVD|>5muo1cBqNkD3(_>uD`J53$I_?0%bEBpGLZYTJ(1Lc5BJNv^#zMCle0dnRE%Y
z;rh1)yxHlx=`-oV>9BOQ^s02m^yT#6^yqZX^xZ-wwX%|tY1jRRyCzD!Tj|^*)wVtL
zE{oqh(p^VtZP&fVy{5c=daZhmcrBcDpZz);J)1u3_i{)x@~*+3e_S<P`Td}VqiXe_
zDXK;VmvDP->5Yt&jN8%obJOVRqIn`nqwjcDeXS8Uq!f{gXheKMbRv=wm53-rGa?UB
zfQUh~A<_^v8a5-%+l$lJM!Zgqn#T4uB)9;TsI&$*Q~w(Dy!U+EJkLC2-V~SAn{a+$
z-hMt~UTj`IyD#0D=Nrvps%X51yYS+nXdR!6+ESKFO*7fD_OhpGV$Hg!4P%qWuTod<
z=2X|8N{gbdWiDl|_Aa}w87_vdVlFMN7cS(kS}qf=buR8lkAs_KCi1Y#-W|iWO^k<j
z9W%$c1^am14hP^-&Qak}>{0ts`cdss_|f;H%%hT{_@hbw@4HJRhl+kB=GF_#8h#zC
z&g9D}xCGx-UA<wmVJmCaCoSZQ%12b^j_4d2Tg&gd=Nf2kv?H1x9f)Q}>!V3=xhQ1N
z@@OiwH<|}+8a<eFH0V9Z^j>~@Qt~cYL+?IRsxTo)xuIyxv(IzX^T!mAQ{#G*+&8&q
zxdu=p=sSxfTY{N#c+p^ij{{Rs^w1msfCq1sr>A~9`1*(^NG3=HF<m7*8Ys8^A$at~
zyO@cGZ20@W__p|w_?Gxd>+jZs){WMq*4==;fX#s8fb9SXwM0X1pk`)@M`eylS&yTi
zWNw)KtnrD9U$aD_c%p=scyKP>_?z7?-qR9WIsW`H47rr{wGG|Izx5<VG`nVgH%fJl
ze-qw!@oJWo!evJu$dwrn+x_f4E3uK|H!h(&PQ$sq;*;l<=ZA|d_P6k|@Lls*^IP+l
z^^x_I^#^(ZePhfPYo#+r6<hWAYev9A9Xb3Uo`Xt%k&Y!ZWgM&)r&(9+O<XqiQIY*D
z&#{hlGiUz(rfnPoecO0D|3?OMj*Qi9-w)<0hACBZa~qNelE(+0h>j?;qFSPbM(6P~
zubNh_g;HF6dL!f$q!W@1sf0v9njv|R0!R#`4Uz__G5tO6x7%jx_M^tjd6l4L@yG|g
zs_oy^vADV;yD7UPyK(GG-Wt7XeXMfvDR`~xw}rRxG2cZ(@I>f*Xiw;3=ve4X=s@WD
z)!>!h?B1~li!Y1+MJsw${#g6seejaZu4bFzN^0;-=y2##Xn*Kh=uqffXm99p=)~3J
zRo~Uh)$r9k>zPgPnY0l3hIU{hbL7CGXAmZ@ylide&=JOT$^^@S!h;B;d-DV*itYP_
zPmFP4=yVh5_5%&O5|B1<+hN;I+kV?t+ezT>z=Obzz#|E0Y?qEZu;umaUM5sMct@Ih
zA~yQWB}g++Gk82;JeWVQHpnf&E%-Q)IVdk6FW4e*El6?A#XZk(hrRPj-Mlk2t4p(P
zoe?n~oZaQR#=2&`Mzv;f^3MO4)J`sZJYcs=ZB0aAYxV3n;G)yMi?%bPYoSxD%fIuY
zE3s3nOQ5r^i%|Bv*1^aH4T@T}No!XaRV~{hz~uzbJIg!IJI%YWII}>kLD$aLV6t%8
zQ`rmP84wW@vIvyUA5})`$<|DOh0!^(Ac2Fb3la2Eh;qn42xmwa@aFnA_ffI^?9(xH
zdWf@Zf6Mmr>CxpliXX|3uDx_a9V3s?%$Ip63#0{_4D%K=n|~qz=fOCE#@*qjS8jkw
zmJ2bYDdq^P3CIAM&hB*_b?gT31#bo)2X6;MXfGSC0>d)%p;Z_YP>=h$)KwT@*7C&t
zyyY?xnRuy%48Fp{zPbJan3mhhzYw@wz<dIXfVS3Q`3Os><+&wn9ln0Lej#@zhX6rA
z=PbATZaO}cdrkNH_UujbZn|#-E8$iTnH}yl-d@7X4X=If|5e~A9Uajp!qQs};rQCt
zE=e&gHReEgNz0Wa#E1o$ozZ|ZsISBc5{;*{d|#VPhk@7|8Wvko8XR=1MHL9CHH
z4X^3ev=Z<T^?2kV;lbx2?7`_F2jzl3gFc4hV3DZ_OL{O?Z(dXA5&FKco@DSLjO+>c
z_UIR-3%MUbN5pCm5NzeaCeEBgJWfCxG13$NkamUanBXFES0Vm|{3MeP!BvmLH`!lI
zE+ouE%p`et&It%3dV9WuZ9F){S<HxQ@iV~&9-OVT(u|$=I+;4}chYxKb+Uv|hcJXt
zgglVG6C*$UI;{L@@tq3!_RoSgq;2v&ucc@2IT1BQOUj!U9KW`7c#4DdB-i+0Cr?ta
zJ*o7O#5LMa9$nyF5Lduc04Xpn=qMm87%1$2ZMyer&uCAfT<qCB2D11M9P+{imy<dU
ze0}emUrH5pO)gG;nB1OhnjD+VoxGYXnw*)8n}kfhFk(uNg7toQqiFPC{zLp5=U)%V
zqP8}oJk(lcR_Kq3{iD%8A~%wt0Rc~>87=MzM2r0}3y|t$TqDmXvAk<ZWJ$hGyiO{2
zM~+O61aucf#G=HOwDKyvTu}Oc-rb4!yS-`~O;4%Th)>>M{IKt({gKhT@I$QE|Hnmd
z;t#D}fgg3fgcP0%3`2?3O4Jm-3bcYs)fE10bTP^dkNJ|$U)dM)Oh4F<yQ`%1cq^%5
z(8cCaJ=5Yx58Q8pn~j_ozn7pFyO)d?kC)il!!z+S-ZP;y4llYi1@9vKslsxh%9w+q
z(sG#t8WE-D$5KgMgNuV72Db;B2FC_-2d@T;24@E21|fql^qA6=U_~Fa74;s>DaLC%
z&psek+M0@TP-~P~qCblDQ$`m?P9^OH_&kwhH2=u2ELLddBh}8hnwS@7@yQ~_B5^Ht
zEnfDcY=UeY@DnhGxu5O(iqVT|uF_AAZ&6>k?Ggj6H;jblsh#6}`*7RM;uwm=iu?;N
ziV_R8iUbPliU<Wg)fq+-Y5J)Jebs4&`>O^0dFkQ?7~b-IKR2?k=9zy0i6iY-db@?&
z$m!zpsF`W`qv!XdUv4gPe*Aude(ZiSems6+=MT@t&w0;<&N=+(GWxu?@J|a{g=%9U
zTcxcs$MMlyLjk&-B5M?K406mTF&6{Tn?<KFNS_c~{E5`ZxUK1cu+FEoAFH<7TLs<X
zJGOcPq}T4@ve^zuZJD1Q2UvzYm8E1!)cR?^MRK~0RLY5SAMoEopL(Cho${PQPEAic
zP6<y3PVG-KPQ^}p-?JrUbG@QwPbJcLng5jikjVXU&MS^A%9@yjzNx-b1+79k!Bjd8
zb+%F}?-;$e>@V0wsmdtJsO%NuiOhd|`NpvlWA!-C;Z-Bs5>;+Yt%84{fZ!K8l~0_d
zlnpT-`n=w<_OLfob;Mltwe|h%OY1}Q)%30QMfPp=HS~@2W%s?&Ngma>&lZ<FT+C6S
zm6d#6EJm-%k)km)j|-=AI18xfT+C-uP2k{6o*8PhdD50#oSZ$RJ2W#SJOmq38>$*&
z99kX<9*VAa!A`S|YzW8*aRc^~x_T{xY}zm-%IO2RlasRyW@Fhu<iAR=4Cc&FAow8h
zrCQ>lJgyn~Bd&A@carj_DgswfMXDvL|HL&d!SzwPBOp^RgsbM+#dXhz>t`QVT^)tv
zQ^!>sjNtg}aMcY^T<dro^$<th0poaSalCD~tBn4+ZWxY*<j<Y_x!S>>9`bM}47lp*
z7~DzLpSzjCwVWTuG3VnXsTakyK=b1IXu{nWF1iE98HwYRoxm|D<4T7lf7pj`CClG9
z_99&A`~>&U?~ioAJ{;W~SHi`1zz45!o&I*mT>=-|QKB5yjVnd}sq@E97u`F}V8+FE
z>}!9-)#GA2;9P9DswABF@Bb%>?U1v0o%+b>o}+?mA#0&^AyuKp)H?^GXB=77V;^@E
z)e1!@SeGb|KAtPsE7B@tC@v_7Df%m1C?+asDGDgmDH76e-gQ(8Q+lHm#H}3_q6g$x
zy*8e?9+n&12=>CFPX>OgXRQ+s^ss;zIDh+O$)z?pYHlJDp+UqLLGk$fYa)vYuzgtU
zLPNlnum>4NLYy3X%M7f7@$b~!ShuGD98w~AE|s!I0<N4r@XdbK)otu9%#7X(o^fBh
z9)L0Twe<P_B=1Z7IngKZ)4eY`GkJ7nG-9++-L{lNH{Wr%(LPAHH*;vTbaZ|+VYDc7
zKsZ<kEgUVREX*lXCcG=8o5_=@w_~?cF*=iJFEn9qG2EFI$O`k@=^BmB)Dp_K2M&ku
zP^i?i2U2Ff|6I;y67%A1x;T57ik^;uV|t@X!m9)o%~wI}c*$>uzS!spv1VrQs?4)}
zvQevNT};VIGy80oZkDo=x{|b#A)PFp*7><JoyjJqq1gD+_=9mQuWvg4$QRo&FMIrk
zO=D7HKI0?fTw`<NRoq%_q%o`U7H;{q!I;E&#F)|8Y~F9)Z9Z(itvb%wu)fxQb+|nn
z@etxU-%y=l>|RgSz`oeFh`*?~IP9X)EQ^cYpE$RRZb(_wz`eddSX6FEw7;;quqU@o
zw9~TDvY)Umt2eB#I2=3FT`X&uu*shQriO~3mClb2gBQsg@@?cM!qTopl~Yr4Q!-db
z9(n0WEHTL^NDO3dO~mZX?mpXX+-4e*NcVnRCT9Q8UfiD7UdW!qUe=!5o-cZ6ad>fP
zaYQ29`_Zn~cvDWcgumDEuJmwV7VPn^?|8T#Z<;Es<b%!!J-#`Wc%7<QK2p`KX#&T%
zM)M`^qhvodbaCV~#eS=gsw9v3XMQ!Y;v65-cAnLYycCO6izJJTwdA!l+0U}+vMIn+
zU=lNsHIVZnH^M)5`Z^Rj3y>jH;2c&3JpQ0~0Jk6XOv)X6Sg%;~K6Ub=<i{sJ1W+6l
zY`}*o!Bg8!P>klL3aR^VcWRcHwX^)X&ZK&#*Tg`)orpkihm|an+2{t4e7Kvu`z2KV
z+a1guw&xP%H{xEf|8Kz%4Bwb$BWS*oRo~RG;&UM2`%3dyM1<rE+C2i9ue9*+u%|Z&
zdhXE?K)QpVmfZy3C|qt`)3^}Gkv6}(CTNbxzq#B!5pe|G?Iwf5z!XptD^8>$lnZ$R
z7KEx<(IQ#Eo*~CB_b^mZKQYdasZ!q=KU9ARzHyWAj`;Hs;`c<i)gM~jx=D5C%k%Er
zw>a)S4S)APK+^wuvzj0t*U|q-Q>MQz_wf!LzO@yT`a6|-dH102-*MiSegr1EsdXpd
zWjEEW|2q;8I<#p?(9u)(P6lk)V*z!xVnO<TW5E!J-w2~(x(&i73tuOQ?m2nK3ij{O
zh6aP_kf9z-n497^vG;Or18!@E%Mq0I<m2|LY4sRG?ZHe)Zx3b+e(Mb^rFwWA80Q{5
z=rJO#w`wDt!IH>Rv`Pf^tH`^95ljJ;E4Kl7Zs8#OmY((SvhMXrDKJa7IW!UM2-N~J
zBkes{FeCv47<cLIpl_;u{!G^k7(*x@QVe<nqXoT(k<$8bXY|G?cR_dA`&;>x#38C&
zP+VbMfEro-8r<+Qe1aHXmgoPX@RN|mw36$#-0isT#P_0<OMBM=j2jYRU#UX~NAY3Z
z{yia3nQu4#MA)#r!^PNGQ6MQ^z4Ll~^M0i2x7&K*C0`kM@kFd7%JF%gKQO|}>Nc6Y
zYx11O0q^K5o=*h-Bx%rdfj=QPH||C}dU|(0903NsBei1vbsNj`>uwl>%gt+27koLq
z=J0&{<(`S~2jJZvRxoY1CNvJL4PEcC24{5hL*=@+kYy@oDWZ?3l-QO&DljHFuu{4z
z6vn@5q=@;~6IleXw%-^r#J}*uXb$l~1n1$Fgy<gkcX+tOi!Y$2;Co0{4>}B)_^mKn
zCVUWKLik_5Qtzn1<UJ}-WiU0;+JgZ@B#wur&cO!|jEBn+?)F%|BLNHaP`BRU4+q`K
z=&_9C0Y7OasEuR<51c%~pMHo}|Bx{6wph>lJ5#WGk1Nz4%niN3ZI~qVpvABTFkq-!
z39<Amgx9z7ZeIQw;NP78)Nubm|Ch$7mtHv(0U|_yz^q<yBgwvy?1Z00T!MqGZX#v5
z@Z@fg^pN*FhO&OXvHkTHFF~3WQTZ*k7a~RkPTgLwNetdeej|7m-t?8e@twgW!O{!D
zz1!wr8R73NCJ9kJH|TE5ThUeHL3#i;8M~Ff5n&9!(PN(dx`k!@MI1)pf+t7P9GQ<N
z)jbiZ+%51f7fjnz1O`P8bPI%=<KXxPPJ{PnaS|8Ab2U<Y5G|ZkqF(y=l2O}%mH1yz
zl(oQ&ScxHNz7b-c{2~b>J;Vc%oky<UAnbOJhy=HEKY}iUpCTW4+{W;W6NiyA;ep5#
zBIRyycC$pJfD^m9p#$J&NGcBk47WH5_HGUyfNVSxbc43rGJ@NK!t53RpFa{rVA!qi
zL25=Q_M8%f>?(OdVDo}Zn#e5zbhD*<Jz^Pr(ya?V>3IMp2lFG9q0f+<9^@F|R&p%9
zG~U^t0WR12r-u8zKh975rAGF~q)Dag+pY>l@eYj?@uG!OO3#))DltwuurmDXiO300
zRLXyrNdKjz|4+T+Ln0lVgM9km@{Tw|g5!L}KVw!uf<OMP#`}MJ$G4M8cb7iCU=(y<
zC2;Ng8c)|q5h?m_Ct^6oVJiPwBK@tTqD0zjp<kq7_=h(^#OD!~c<AoB$Sbf|_f2Rv
z_#u+d;|@kt{B9T_(@hXbLc}`WK=(=H7MQ%72pSD$L$Z4OdD$ez-p;uRARdp9!`to7
zkA#5*y78eIR>WqvGrBFqN5FMGG#)f&cndwGpKo)2CXfruH~x&L6_E{g@8*NHfJKo~
zP-<kb2O$Qpl>|#6O^PL2!MnbD90|BN@h;@gsPClwQx>$bD*v|{@3^uxPRYGs{O-Vd
z-?gtW-l&lxPW0`R67SMS#eY2!+mL-#{GTP#-%6Sqhy&0c5`b=<zq7;-?x_n81uyi3
zK^eg}kQyHMF!#l8hcPk{fbbIDt>Y{AoP=A0FM2$ogy7pqc@Ihqg*ZNzE{6bcYy6!Y
zzI{)AxHovBClE>tzJ*kKiq9XR2CnP2g)V@JTZwDKAz*@6f4%Y`PdmoKIeRpqV&MBo
zQx8VWg8*WTOe-Gt<_iAxojii;+sEMmf{Px|JNxIrKckLT`KK%h3M}|rjhCXhG~a-M
zfjXFs1ZezA&iXbQERMv(px)<L9z}bF)v0u1DJ-=9ywjb+<a!|Vm{G0Mp!;?IhZ(kX
z%yq&7HwMkSnP`3sz`o08(hvD-rX3baDhJ9dolJNsh0S+UCOaA|cp%Zp8twOcGJ$C+
zNnXm!;a^V#9DC&dhl%vJk}v_M0+Fj=!)|71m6ZTe<Qq9g@)vm+9@7mF5n06gt>|v|
z$X>92HwCl<%!QQkxQme$C&S*zxdFJN86kJ8teYir2CUUh4=n@pBLDZL!W#gh(r!f$
zA`DIIT`YsyO~W1$j|VF^R6gHw{Cv|Gx^;nJYbC-GtlR>SxJ82Sw8BAz{@rr#I>0PF
zGvNGg8R!I97D)@eJJ|BakYpW|vABF;U{k0&_$D$R{0QlvxBvgbzBV8Hmo*ZB>Nx)L
z;JFHn|E=T7{d`SEI`)a{g@yi{`KpSfdF~`p?!9{yf)5|!uuQoA!ZUgLj!fbCZ{EjI
zw<Tf*Rc<RN=qdEg645Ct`bfu%4|}|}xo2Yax##O62gX+pg#-g@{_Ey%r=JGf0sSr4
z5m>>FTC_z|J6YE}th%?3e*HnNOL0oPPkoZ6==6}1<l-wFqO1+;|CB^(%R1laf5)x<
zH-}XF@z%w(@|5z-z~sR6z|_DD=j2I|R`I%4z5?K#Y$o<$*Js%e777BTS|xG{`AYek
z`7iQS@)ZGJWV5k%LdmYQQD!J<R0!%8>Ltn=t_UC4kK0$<Q`^^?%$UkA7ATWbw0r@`
z0w!bcUKyjj;rj61{i=O|$%RSF;<^%$f<OW1WA{mocEy%`$R1>$aS!knqz?E1Ou|07
z5<x-W8gQ|_?0xs?^}>O_?1Su|G7&nSzwHhMSlk1-z(Mcg@75>15EU9!B3K-J$VhL)
z8tG#5`QJ{|4k;03`cD(;e^pb=r*$<JMHUSfc@{MmWfrac=b%K{q%gTq%B!0w8&o9x
zC5k$TqU(z+E<a)@L#SjZK`2M){i`=97ZfX80<OI8y${=i?UU@0>?cmqPO+2;lnN9G
zl*qlXR01RebFkE*_*af7Rg^H?et%-ha4Ns7t`zj#QXY^5Ovh4oy|102Iu+Z$zgk*X
zR9EKy^*S840fh#ogsOrs?BRf6r`Er^mx5FPam@CAEJ^&IGN!kw|7D@qwnf+VQ`fgd
zg@%+k76;iFGi_K?Tx^o#)$5Z~{`JIDktLsB|7k+~r6zWvFo96&&}X4{LwQ4)LZw4*
zUCE*pP*-pjIN@H(KKV4szV4nP{4GikB@cIm@5AZgnQ&ux^nSyB;^gimOUXpZMA1Z<
zz*m7{IVDR4Ko0N=@I5dUdpnf=N(JSG(uLE&%l3KpCnobt<diKH0eQeI?5$AJD@BwE
zN)1lgt|_(`!)xS|4NL&$0mHF`s1dl~9^-!9v}F-Ub6o)t3CzTDT=50v{IR6{Z~u@n
zeLQ{iw}oOe;;|!2*Cf9NA2S-;u*SLAB*pXACn<{74=UYX{I?T-8rqM%`A-w-FEynO
zBD>()@F}<;{5#weehMdoqxY!xFJ?HWSiWkN%DoaO)+(T#ird%SC!Z>tDx0yNw4b)0
zVkw;{m3x^l4@i~GkWG}$2fhP-#?pmSTzR72q9{>1C@Q!uoO6F<Uu(*6GQYI0SWX_0
zj%5m^xe7!%p-A8&aN2$6eSs;pJ;~Lt*>DAZ7nCF_2t|Nm*%O$tEO0LdsRH7$lA%;r
zq$oR7HoRre^N%H^_x@AHq!jhHg(56PQ38xt0#>ZqE;cFgF7-(oqV+>cqKktZjEgq^
zb|ST9hHLbHnoxhK>HqghF2pC&ZJICWG3)>1B=?Uck^NJ~L`U^s7J7Yx)Z+ra#cc>+
z-}rzz)jBZ0>2JGA8k!-&9bk{qR7|iO>MT1C?THRpzqc`5O*~$`(0JZ73WAx0LvM2u
zv%^k|BO`hv+~<L;Xqm(Bl@7Tg>a$g1vdE9G>j}2TwR_$m+(xA-bLh>`rhFax&?Eo^
zINxf~!AXLApwSRT3@CqgYSXn4S#$~%`#`y3;%?;eY%M3G$@i#gH_#F?c~AQ!<Yc5X
zx=R{;C~?swdmY*Y!n@LIh_WS}U`X=Snjg$jgT`099B-F{^aRvK=mxY@_FHq??lp~*
zK6*{OL3OJyj-F3xBa-)#%A!uf=Mpn+mff+EWsf!GAmUvfwoy&T61eoZp&A`}nsJ&a
zCqMPchsXLV+Bx~@m7ds0IMujwv9S2HF$#ZI(3moocZC0Gv#EjSagwfQ9tYYZkKb9G
ze2`vzA~jNcA{ny9l+8Nsy-grKks{C+NOk!*M=VXCClI*8w9EJVzBot^NWIIqoi6Uq
z-tr^R`O-K?j#DlgrhoS257cxbY;IWNrA`o+7>VNkek~{4Q$Z97KagT~bybY$=W1`L
z*m!iC@>a+vbXbm-msU?;QZU&#i?3WPtnHZG1NgHGf0reQLi^s%&zI+-YV<tCsh-?h
z?~{dOSMTef+Tp%0RV?#?IG$3#Cs++O>gAc(8LI)71ta*#@uht8GYOBR&$l%2{O_<&
z3QUskUg2GN%07I0V;4knx9{?6_rn}=G7R&s{4IG8*=J9wck#mqJb+x^?(8Pow+oi(
zO_n7GYRw<La<&|ml5pm-`;zJ_*8eF-q!Ua3Xzsc#?5?oM`_DlhPMihrC8H&`q&3S`
z_i86!<qSyZ6Lsaz+~w(Er+Y)0sXyeH1p5pFBr#rBY416Xx91q1UOG$Ay^(O=?ppx0
zc!zZd=D4M;ymou_s!gJ;&B&4AnFDkF={Q~LPZq&gO)pH&&R|7MB0YEi)aH)3%GMns
z4;LFxz29Ea&o*9l8|k|#X>J)a60mGA-(=ZWLZ5cnQ45O`$u7#!TkP@scx@oW&c&4Y
zvyi9E09`o)c7QNIH~`3U0&js@`&^o$1Zy!hS2Y{17+0_%^83MM9o&)#Gz_4@I9<;{
zoiPjDQfLbKYhNq`ynwEYUI&A2hNZArPh1CIpKSDA^=@1szbm0m5bGo?yEvFUaQ=<_
zz5F}*hsw@ZAHo{vaUp&Y6VQow6K4|<6Q|bCP`j7AJ+#R09BA50+8$aoZErqQ?j~UR
znhnD(w^N6MW}boCV<x)uVRD3kwZyhVK+p9pjN)}1Gy@~h<11%C4B8jlXlBVo)Lqm?
zU-w)SB9*R{kj~fza5g3zoPCwO;eNRu0XhOOV)L$Lkc45Q6xY#M@(q?txd?ZJ`v-TJ
zd*li9<Q-u1`ZjO`L;_p}F#-obgun$5E%SNw2KoxUL3l;D5q%ZCK>@fO_9GE7V7XuS
zKL0E~BL6&pXE5<P*OKMB(*2?EyLG!5(1EEy1M@f)U`|X*m~j_znGwQhv$N6p=-SOa
zWt2l)3$wZwCoIq(D2zp{8DMz2T!oi6Q+SXUfy?&I1A&_-FpJzpirpB{#Ii(#Fs`5c
z7LqW+QVBr*#m;CRu6gL1sj&OcKaA%?oey?HFAaU7t;b8>aJ<bW+Yo!_@c}AqRJ^%h
z%`hJNC?EQMT0Sht`4Q=E_-lf3Vfjq)I@;m>z^m7Hb|ng;#NDZ#-or><#(Rdn*?XBI
z)>HS|aIf&S?AoIAEb(rQe9h^lZNZ4=n&|BPUBmZF8<^qO!8w*R2k&52@`hWT)_V*&
z{y&~<^q@Q*jCZ`R9SB^QBo#loe-H&@lwb7>(=8_)cPAtLacNb}#$5eqW~zw(>v-y<
z`eZ(X$<1N!=sf)OHu+Of>@L~Q>+3SF=*?@9Rw?RTA@)Y*#%(g!TlQ`8?r&+lyth3g
zi^DhsujGrjF+V`G)jOrchHfTqS<v4oFUW@UM-gS;`3ybBFJ*Pm6`B3xH-+1)Dg9da
zV9~T%44eilxNRXReaFF^tHK6M489ZJR0`j&tfp|jl1<_?Tdg};Hfro_TKL*u*!!TX
zL*)J{>f*x%#pC-_Zin3xk1fr(ml|q6QYZ0bN$pk?hC6KJlx>)2Nbbr`y>9$nNn1C<
zHLdu3(A>SF=(~fD@_H>&*1~fmi-Z4OO|D5uojaR}gb4n`v-=sjp^0ol<9Qt(HnAj%
zjEyhaFa7skOkUOo6~=hqr>2c@DOg!4(;}a0JaKKo0g0m!T_xXJ=K~{6ZDL9{y~@TG
zH{VXpw-v^s3Nu@OR0Mu=HG8}ilO3%UVpRyge-(;ShChI>!k=E<>+(62N#S_4?U`XZ
z6O3EXqMh-dx|k-PPMjRsqX?q8Qbq}Q8k)iNf~+vOQF^inKZaAl7jg4U^1a~wZFv6H
z@n%CU5Wejbhvg5&J<3}H?Z8sQDL_JpX$j$88=M1vAKna4fY-wF;6QTe$(<(`Rsn<;
z?<-uFTD&L1E%z<%xSv=MgND0qt@U&fhcyNBVS-xlPY%N9!y<#JI<wKP$oOM&@an2*
zS#w)uJemr*eJlfQKE8tTtVC}dtyuQf`2ZlJ@z;F<eMp!1qy>VaBEJ3?QVG{p3WT0b
zdt9{?xeDQ}rgy1&f8Oy-q~kuu*G;%@-Df1I`H7aQFZAu>waq$M`fq#e?gHan8#cd1
zi}GTo#5+W%#@muFV;r*h<$JDRRV|fyAEL0T^@R_WSnTm8$CNyry5*zArooiyN)*ku
z-&BV4i_K%$DnhQ~;2LDsMY_;sL_<9uLesDm*K`OtU&MDvWZ^No!K2GzkoV9a)usBu
zqw35yBSzRaGSMIA@q&d}Rw7QZBBk{6$syHW`8KPzuOr1UpyL$N72ab?5UqUQ>sjiu
z^Sbd(Q2#WRu*48fb@lVcsg&UByOfbXbCJA?E1r2;?4J%>$&1L#62Gp?v#5YFWMgHs
zWTSA=m<h6Zvf*JYUFX$b*v4PU4O?L54{+FrC&>dtGrtv)ADUj^ut5~~Q>tk6hYTd2
z$fP}9xP2jd5$4|}sbgM_-E_<p;<0rc&Pt8vW+^_@lt}gx(k~X(I7*V_LDbB;R-k8Q
z8xI@p9FJz&%Sc}_W*U4E6?0WIX%YZCAO1CwJ7nB4g#?dX6x59x=GK<lmx-yJB(HIX
zDxvH!c?UZzx4aUNfcX#;ch`z$rC_PaN0Y2i`Jr#3<cheg!}^y-D>7*iOS2GTcaJW5
z#Qg<R^ONnMlZ9pd6OXP~E4y!@9v&V_9<CnF&}CkL!E*IYW7Y=Zh8??_L7{q4d)F~y
z`!rkJcId^$#j*Njd;baM&oV+CPlMggV_jH-z0c<lJ^YOQd_$YU{I2W}%L^wKfah09
z2olId4X6;P4e-9ILG&U<4h*AbU;C9Cmxq=IJ3M!=DS!HmmfGgMXmoSbkAnKwz6n_=
zxih?Fp_&&tHzioTiM@Arss{zVM0Z`rh;~!A^&-9My|cHQCyw%@9{St3y*XZ4p=nb(
z-oYh6*;uJxIUsO~JR}%nXmp?K>Ul@N%1ABxW!Xv*uc&8-z?AVlW2#8`xGt<7mbKk9
z0m&14=x$^22A6JxCQxZ@r?Vz-qqDyAAj+xtFlvmU+5K17#=9t1#`~f<%N~mIMH@R&
zri@XH>7Mu5u-iAQOe39UyKJ%^+7(fkWs+cGroT~cOHnz=;Kh3C&(>TJ&DE>}L2g~w
z&Fu*8-h=tF<66^v12&z`rUNz3x%OJ(Az7mq;6DGXuK0q`;@kbPwU{#*l6*B#*S<iT
z3gW_fu3+NK=$en=bRtM%`&n5?&9RiM)Q@%&h?(eoy<H3sz#Nk5E@8{2eeC$7L;lx9
z?N5d^#s<Kh9r$f+F1wFyZ@(KoG9Z!f<Q0v(_-XK6?fuU;+8j@E%5nj&%QFkyoRZrF
zWh+Tsa)!Cn`@OqGIbPm{D-g5w<vDJ9iEXszrCQ;Ne~qr>!bKM(RU}4erH4B%XL{fD
zR~uH*xs0jDLaZljjux`=wAvu0PfyU4mwKeH;cbl(rv(n&jr=FscV#B(l1)=>b|*Gt
z)ij|Jvx=D6mrgvssqLyV>}9)_7?V8pRCMkgCc3RuO*QgnpW!*pHaTr<O}s9@&#)Hd
z_M=^_d|a-Ve<5bN?RvyE=FH<n;nF`}S8{@7|97eY=Wtz?__kizN;a2T?nRp92~Uk?
zs`81KYT1>gnAh;4rg0V*Xn!YFg%y)M=Bo@JQdk{GT0}_~CHU({;RNwbn>l#GnXj)&
zttqj!lPb)wN$N4IsCk*B%dDC@HR`>qI~yp9D$t#W<{?k2N*@CKzIM1-Wrh6;RJP*W
zk|}G*oxaRFXx0pTs*Qchs*T+nO=QV+!OZq@7sb@~XQtUR<hqaNd9Go-D|IEit_Qf*
zLgT-1?0i&w+h)YB+DGtRrISaNGXG=O=4Ye{?%NiIw~Z~II`yo$R7b5McUI+q1CfkU
z@mFCj_MEnH%zCD5!p4_jpu&!eBu~Np79_!A8Vx1cLirSn%i#@&$)R4a$5XQ3TDnE&
zwq+ky%U*l*p9pA@zhyKY{vyCzqCjrTo}{vvMi=dcv7Fj0$r`La43yFi8lkdvdR*^i
z;$Nmd8nSrtqEOv3iR&sxebD6X%22p;nffPF3Dz7gVJe<aX709ycRBjIazxm)?W#00
zzp!{+MJUh@`waJCK3yLLrnj+D*+$N5URoE9s#WWG^-9FlYd_XJ!+%jGox{Z_weJ1q
z?fXFuN|*t#{5#Hv`?giUFh4ax{F>FRUc#JY8RAEyTE4@sG4+=#3X4Bt)=M<6`F(3!
z%(A#lN!3$pvc+wS$2-#mmW}M!h7I-RYFfP6=U@ki;a(lhO|=7%D#(1@-G!PK0V#XC
zVZ+e9)EE){<H^01U`Zd(;lANVmPcDMZui3O;9!rI#PeHxhqX2Lf5Q&?P@MkiGS}V@
z0DQTf{$|^$<Km!xQ!%oI#){=SXM%ityOCT<NXE({{ZVf2)UUSV18)C>&uo;w_xhT`
zO%}EguWKLy*rgQ{UwVY13L?@MvTBNZ{JE&PxtoH#m)|5kR%_i__~O&;KF*A^-T#!g
zOo^@x=@1@4bIj{pCJ@EcgM?9paP?G>x6(y-pDG7Avu<=MbSO6lp#XHYT1{W|eR?@w
zFn*V=9prYGSdx8?bN)!Thd8M)k8=h;J4fhy)QG<nE9Cf6vn|>ts9Dk9aA9mtW`QGK
zGeopqqcCTgT^sn?2tqG*;1KLo<KG$PS|eEtTC6?Z3kqh0G!;TM^A#@L%#%~sYb4fN
z(G9RXIjO4g{9I3@Ha1X64tQNe8gnL4MYTQd8gn+&8zUs$;RZ;sxn}I>2;u$CGqTM}
zx$Vh0z0R+dx-Q}D$o3-T>_Q{g%doK8L&$eJ=0!=vy#A1HVdSD=lZ1BO0jJKi)6dgc
zv-xX9sRvG<i!>XVUVhe+a#m^*_NrW98)nIw!uIl(`OF{Yzt<)67}j|FQ@2V)1m_az
zU2<bBen)7Verzr*^8UFPKQ7L9xwxo--8gguiFasKFUkeWyL{5+P-=V3e*Q>NJJ%~!
zm$_2-jM{LbIH|0aLu&hNEyeYPQU8f*YDccn_fno?m$Ji+RNY*!3S9=xOeA|jIV+B?
z$(7gUyS%^XGtOKPkaGeTU*9JchsgWsWK$V>=hkQZaZvubLNA`E#!^L7mu+*;D8#B!
zGKZbG|Nhe2Jk3o-{k0gCduD=rdVJW&Vw9F{G(T-JIB(Cps!49Oj?k_3QstB-6W|7>
zYfAj$&b^PM^nRt1ky|gHOJ7}__-edir%y3^kjL29FZ`CEsyeme+w?C2>9J{V<G=MO
zou(t7yHIJ)Hr*=o5vr8%oTY4#CwiYV9i!j9Z*28J*UfjhQXzB0Mx?h*?$5FRraxM9
z-$rVtP44d_5U?{37(%Psz3t~gyw`2^7`~|~vCJ(dRU)hup}8J0?oY@mvCR;++XmAm
zl5`*RGO=9WO(m+;f2m3B9irl#n=H($ExKkD{X8}9OhOJa`mt0~Dl46BI4*dhuq7Zg
zQ0J<t7?oEXq`w-}V5QR)suTJU;=43E>ZmKsnK-s4Hz5;)&}!=&>Se#&UGt8if~e)J
znAc;ZFI;?7?P*5+bAz?QsBjh#j`;ywX;|T2_a8p<K5;y*t{z*K-2Mz(*{c3Awjg1P
zl)eyW{rX|1_I}qySJ?;QW>aZMsww1Y-1O#hJ7UCizJQ=)y}ljM(*>D7$ue)jqV;_t
z^2%&;7qd0wRpq9jGHacy?RG?PkuRhuYOW^H&7?)v@6{>_ndS?*II55m<3PNs1Q@ko
zpD(me$U)s!gEq<~Lu%DC&ErHU)+@Gig6$#XzE!6AQ^jQ4Psroi5sS9Iki_?p`CS){
z%7s}}SmW+gNd2)~U5i>J?c8N(fwUxN1(2%(C|v=pyl-D1D<)8}##bTBQ2~5b0hFi+
zD|ZXc%h8+As=Uyw)Y7b!GmY!qM3AQ(tj~7=!t8Xq<aN3pR>+D~03THV%iJ(K*SI;v
z^BNJ0O~h<*`-!F5wH9Oza22|lKWDx>PwQ7{3UD!7-KDKjt;}GX6T=;xb8-*8b3?BS
zAK-3umt&5QZO)K=j@5S^)T;4U_s%+9hB~3o&D%}PKI^TUTwvMxQVx!i4|0<aR+A4@
z)^Q*`I#;#rkmY0wU&u)I?AS$Y((b(TRh`K0JW0xdck;nV%7Jsr0b|Mm3vQ&@=G0OS
zaKo-OqJns?)1|G`WvkPr`{x>0wZ*8`VpL->s<0SUS&WJ*Ms=tlw2}{^lMj-LgEUrA
zs_r^6QWa~@D%M0R*4Qi7q$={L6Vt4d4|G!wPS*`8z7Sm^MIOZ|3liFsJZecof6VlX
z!F(_(lCF~$IB)0Zu%Je-<X6Gi*%1k|9VK$5<7z3zuE2LEN|yxdxxhIuPt-@a;92m#
z@C@w`%cU*IaBT~>oDmuF+__LBiQK8C(co;oainqNxBSxf()L-#63tTD*_)b_d1I_9
zq|!Gn(P_2O?QFrszor8dKQ9k?l;J4Tly@dr(=u<$zkqTG{k>&^OWTR5nb(4F0?J4y
z2?i-#zly%bS}<0Vrt>s*G<N)^TDs@@F+_)FlK8i(>lab=+G!;R*5A5IuUw0n=9C<Z
ze$On?xqdRMiJ$2ol5?PHBsxo6!tG|nq=>3yvn@EJG!326*SzLQ1<c1bKE7mG(sQlE
z#EEKTa||@nFWpsiXlOK!EgqY<<Ea-_&Mx9wGIOonoZfMU(X=$bHZ3n-(p}PxRSq@@
zHaT^|p=xn)FFkQhORlV$H{fwxVsMS$oSAoWPV=cz;L*lp70}0)8fTT<ZX{hIV3!Xz
z4mKW|6?I}v3&MeSIjg?L<;c;gZyZ~)V>b;}3s$SB>#FIhdEe;Y<e$cL6nYfOZis%4
zHgf!WH0j4pOHll-_!$Y;O~p1gFj;FF<{c+kJBv`~7Po5LbCZV}ZO=Y4zcMr-Xna@N
zNNjUkD0MzOC_HG`HoW?I`ZULDx!0C$(x0gYwU-DOZZmKh-j*c}DQ+ZjA$8HOy^Bk_
zuDe9&ciWH45MP!kq|oQiA@QM3E!iR2p@Ag9`R#MAh1=%@=TCBPZ9F&HXZpqRtImv3
zoKC#lj8>dlyx50`iHymhmYj)*NxPju6|ZENG`tSal4tdnZMe{O|MS4FX8X)YQD}{q
z?nBCtTr#(4!il$cx`(<|O6;R}dP`Q43+&2O>+ZTo8McYAim>YM=WdKZxm#>;nc7rY
ze7L@@<RxV$RlvvY*xgQ(5~>%jPYa_j`1E;Nj#Z4+kp6R0Mp7Auzern&)z+&2Cp|4s
zq!9m5s{(z_lyuPtFMGGh75?Fq52-*wtmW^De8O!QbD($@{_?Ekl9cjVU;=*+k$vKj
z_|B$LthI1r-Gszh1dZ|Ij#-JvO$i4`ZO}qs;!T8MuFMZaA|~j4yW~JQj7isXbeONo
zH%FbRGuh`icKTt!`QVsyOc7tA?5@;HU0Bp_4L3T!1o@_fdgK&Wz*><?k%fI?Qha}|
zjDh$-C5+iQ&`8tx;@6h=amT~HqQyGp&3%$3vq?mRBdrS%{2O27l=bo`{^w;v-!fyF
zsM{{nDnM#;eY(|fh4Cl`QaCqepDU9tVi|aDw9CZk>Ea6fu1Jy4mZ1ssc>{}w4)Jx>
zU}|6iJ}zAZ13M%A8((HQKx0j>!?N8n&;r+zVU0uXJT0z~MfS^Ku7sA4JbpK4M_Ma(
zh#01GB%Ie)HCxEkT0;`hQW`%6%V3|!oh3nlqr{jk$xF#~-!^lO%`a27rVC19aPar4
zZ1B|g<vustaZk#ogw<g;7mB*oUz`1!Vty|r>e0=|b7JxBwu^itK_A@A<2VB^NINz!
zex9_~aD}bAdZSn7?A7xNWlLIUp+*70Dww_HE_V>n8l|bU*mYvU<i0v}kr3|ha=d^y
z@E-fXWBmtK2~c!mf-FVSC$yjevw(?r;nH?@je575Zn8YDBmE_4b@J{(D|YI{1mo6w
zV!`-}bl_V!r|0@zv#qojGK7b8jgFIOe-Z3eY{6x(TC{SMVdA<}!Oz>yKN2iQh~%`8
zm%zo8MD^ONX=~MWZnd&b(d|`k)3QUp<hTgMqqufz1TTZpvw8=Usg=TQMd!E<YH}X_
zC)jTR{+`^W>dO^zr3~b4%ueXZR>!eYM3!jqlIe_}dYrmpSz@-^sK;19aDPGO!Dzqm
z@_487&ihOr`}FbQY<+R(?dlf$P$3>^$UyXVbhfPY*+v>UKx$c}W9l%xVPMokBpAlJ
znUs*I9&7_)5-dB)iSgbU5A+}JQHHTRxZI0UcHZ&(BK5`soL_BnCc&ed>uYa;UQa;A
z3e|yISih%ZQWjgD1dh+;a>slRTSM$Fh?LK3`_p8KU9_+QWk*f1%SlG`n^lf}2>gO5
zTcf1x)nB({RI2+=DS6zl^o<-rWCk`F1hDbiJmrY7m*&}ZTdKT-Agn8mZ{f4>iIAfe
zkw-?JqCv=Kz$dUZyHf~eCFbE8&z7m!7B<#O7|2In!=t$PX}}$=fG)mz<5=@xqeZ6R
z@!GNXdH4bD@8<XcOF|tc29bvYVhG|M2Vs5rTzFf78`3~Yc7v~d#2JIE3qKj`TvzKL
zTZ^CGra3o03A=WucLP#FOff<JA;4zOjvbzf2c$-L*;k?l<1PL37P=GWTDkgCeV(aC
zFEXy${rVStLU8y37PE$;Cd-aa0M<IKx1827=2hAPhx(ysQGM4u;`Y0qeyNk?owA@K
z*_czh_4NQiKJr0;<QFlvFm|j;h(O#rJ?K6I%_!P8N0cEN;tGrETMw7&XFtX^Js1jh
z>eN_~1FXIPEXzlKOB)KdTa*a4qp~k!8Zu7~?Lk;*N-g!Td!c`HrpFt6b@i>MNPK%X
zdL^<MLr<UR`nK<x<wC1eedJ32*0h7Go3S+P^i(_e_OtvsqxVWz?F&K+<AEX4eXwLY
z%lMxqDW*6yiC=Rj)SjG`zJ2~pI3Nv~)9bCC(8hVs;|Hg!P3Iej_4bM0`QT#|%Yzlb
z_0iUXIV%6bP*N-l=y>(|5bTC^XJPvUfW1l}Yb&1jbi)ktG$kNkY1yFUq{c&GAh%VJ
zKiekLZkp9kQW@0BT#fZNdKJO}+%ufNGRdkbR(*8fP20xlNlIAmsFagRneQcVkSe}8
zu~N^gse9V-;w9ha`U^LwDUFqHaneFi-j=>ZdOU*j^=DRAImSlW8=o~cLkL=TkC2?6
zQ899~0$YUiWsHt@F3t`<wTj(u4OYs@KZ{zim;_K6R|Rk0Fx*I4CfUsSx%2~@y~&g0
zO-ktCdN+m_t0$MY@h}7Nk;)7+E*^i?Z{H%&`JHNON{~4we3jC(wSX`<@|<I7(VuUf
z$z4${Olm#*8P&v){gL*hq<}V6eQLtGbItpE4}SU<erRP@X7r3}l{Xu|9tIZCu_?uB
zzD+e^3yS^uHn&x)lW$G=2#-nY<AcY%=`mNEjHeOe9FCjhI(QY~chusG4K_(CGJJSs
zyEG0s6VxJ0I{Jtl%b)4#srak?FT8yPTpV4VE$;5F!Ce!q2_7W4yK8WFcPBt_cPGK!
zNr0e@Lql+P*Vp;x+nw3>c6N8>&3iu%w@;m0&|O`1Z~d>-J=6mXR$1I4PZUD*)i^xU
z-`){PS32lYR1ZyQel2#L4xNUdwwRW1B5tjA30;xzlCfrUPZp3N-L~02EV9`m-m+7+
zXl-B7Ym+~rT%&SLv`?{5Y5UPU>i*&F2=rE<GWxyzz5G6&XPKbt0Zn|uX`)@qDfq|k
zv(zYd5#ZuYt0EBv{*TKdfo<4}&1p@~$PUpA`r72&#HcN-do`<yr?#hhZiAO-lGL2f
zx1&<U*G{cq`-2i6Q2;|HwZ;$O52rtbe^?X=k8((S(81MGDzc4|lK$dGpOM7ytcJ)a
zVwIazy(MF`Em|CT^|rX&ss5_iDRNr(p?zA}iYA5e3&R&_1Ew!bw#D|zZZh8cY12xr
zk`L<pRk}<P$*eN?<)Zr)E-CW#tI2lL(%?lkdCQgeOHq;wMhwkbu0C_h6UNu(6v-v7
zj&Pf0WR;95ntunFg<dpd)pS&KFx!mKntdiw1gV0Oxsrt${ZqM8^hWTV#EMn#<-5eo
z)r~K<S(``M3^tM4F1CsFvh}jJdux8wcwS`Jgx0*>depUV1%1hN_C0uz(?49=e2|>e
z+pbA_l5(#QP<yFd-o5$Zy#nc8^3?k1d<)5U1lR&l`R@Y`0E}PSMpw)(l-ye%Tb>#p
z1#YEV$H0G?M13-ILcVpnD%|Ryq|i3eGVwj-#J|k0Rpz?P?>>e|5jv{Cyh1BV7PUMU
zrxv`-WN1OTMui6BM_?r|GdUW#41AFhxV}C3v`yq1$FI?<qn8ILiBbGgCY$U%O9wO?
zp}%IhW-yC+XlRomtgKO*r@yUaD`#W)tg1Jg0uQ`CI2<u`{q|79srUT(A)ixfwZcwq
zr*e6Abp-0#*){hf<RP@pK&ysK6`hd@*nhB=QaWpL&^*FrUHtIvqC?8VbnwPQFg67>
z$2`YvL|s8j!NM%JG`cj}smD2Zmv%d^w6wJO!X4bByqr=i^ep(CY%d5c*sU@m7%U`~
z;xyqffl&P0Mp~P1pYV`DnNdhZh$}hGB6Zj3%P80UWt!|Y^Ldraz2Jmbj;oosx~F>U
zfw#K1zC)-Wo2QI!YtD6!yRK)Buy<3tw&%-1xl`k%xDdxYgguu%*E~CTg|bkamgdG=
z&iN1a0`>y)^ry3+xSA=DJZQY89z+JpsW}JfgY;`6K_Jkw?ydLf*^Rr<I_Vba7ULD#
zE$A>~qjSQ$+a|-k!o9+##J$bE%_h}7)xGHuZ0>vtHBWMC0+Oil1kr$KYG6TTAhViK
z5H4s}H{SDO?Y386JE$FWU36=9I$E<0VmxJ-R{_m{W@<`1g}wY;s^u^lk`B{xG@?eY
zb))D8H?>oOUU$6!60(Rb>ZL&0A5PWMKcs&+b|z0#&`hW$P16@Aj(+H*cC8zgWBI`1
z(3!+f<r-pRa!>}Gs?ksxE{SvP%;5*P2HB__3;-i*ewK%pgRfVW(h_;s&J=zY*OJ5d
z@=N8nEg;!v3fIg-%Y!bUSj~rnUqE}^DPZojlb&#?UUCy~mEKlsDf&dhDsu+pUMus+
zTs>0#DA<+Y-F~XP7JJft5BDJ1TIp-zi>(%KpJe|v<Amu7w;Xa!bxpM~$3Ej!iDxhK
zRHusfg5{b;jqQfzl0_r)Uj1&a?5D4dug$Dm7uFiwwagk**T;j#uD8CYWvf1?_aGJf
zo97?5bd9C<(e{~M(WlsJWY=h5_b7eWI<}+bTF}10-eWuez-`KD5r3ci$ZaA2qQ>T<
zR`$Uojb7Qz%(jbGcFKv2#%%bE%Jj@E-+tiLCsz?KdZ8lLj}sp!RB}In*V<Oq%K<TW
zrh_NBk6oo7R9uD6kgMe?<mSG#wDCSiUeT#BJ(pkM9z0xGOy?@SCcNlAI3JAePn33-
zfv3DHx0TynjQVvyNcop^ceTx~^{gpA54;9<OFqk$O~cpgja1j8%J?T1qTpn3GPuck
z8gLKmUy6L9vwrl%Q+gPVLqvS}obW4`3ECt#n!6sL&H{*1lZD-&+P9lBAPRG8`92&s
z^?`_q=-2qN<F2Ba?x*&IvmE;n<Xh{OX3UdW2Ybdf{9e5j0#z|_)|%$N>--i!Lhx(*
z(uUr>$C9b{w8IV2((;FNyyXJ9_|AYE{d|(x&N3esZHBdorV$QZ0kY*<AL3VggzULg
zB>ZvK9xdtyb0N@GD?L_5i!w}J+=i$lDmT<=H#`xd5XPgjoMa_g2vR-+cx|^BArI>#
zlXDDiRIuw`02wBqG1?V9H+}~E&v3l=$oa#05|iW-0Jm+QbLw&bKw~N?tOS^AOwyv|
z{H{q-MPbW^mXAw}2Zh68DUb!9ol4Ib#PS`DgE+B;d^L581gVHx^&@<bw4pl@jxqUa
zCcsOr0q9YDA&<k+-oxj2i-hN~NyG_YET00f9v7ao9a^d1y^`@0K5Du~GtKVM*J9vT
z94o~|A8QPYVdp*O!J8OVgkl&MQt>hx7s`iX5MSd?iL4@YB0f{_duT^I<jCgdQw^&?
zpa!3W(~1mEGVd87a9l8l<^<>m=;PeyT+?@lGv<9(q)~-^hM)`s{hCDBBij>E5|)TS
zV-QiwHED+0<WI2}PP`_Uz>_>ii&-Kiu*ElOSPh!uB`&mOmt0niX#x<~3OU@u6R_!}
zKoT%@M_2c^?8iHDk=v(Lb&z|j^F=w{#C}j4G4@xE3+~<6JR&$@#3r<`7{r(=pL-17
zct&4;em;LWbi8HXT_yijKJIZ#)ZyKE*#+n`IAkgJ7*+Eah3P2922KA+$JWSC89pl!
zI4hw$O9goJ=Pt~=^~CEF0QLXIMR9(8^LdWE$Ao3aE?$QPJ7`9ah;%vF-8D&l2-NfW
zblo@I!+=Bk1_G2Gor=3@JDNPLNuzz6s2rE>N@8-NV=+`RpHW|ZHrF(M6hE=x>v17F
z)}doEVe(W$qn>v6`coJnOp${bKS1?=UKDW)g!R}DFb_COu)c7|VJ}F>fq?KE(Z{^!
z$uIQ=14etNlbCx<WjOpq%Pd`CU4a$G1`#Utwc<GZsA^)u?}dkMB6HbGZSuG#CnkmS
z3?@@GnW+#zY*c8Lpu}aXo<ylJi7Da@ROopdW6tkR>RXcIgmnenh{5LtPp;*OO@2}I
zJc>Ddcg1o=iWArcKB?G~(q&i`LGmI>2)2&TP=o9iTqf;8dd3!lZ$*Xjb@D*<wSv!z
zH{o!b580Cm3&T12^%12IL~yZ#jgLz5LA0AbNUAWng#grT=45m+XGZ|KD4C$FBCEtb
z%+;ImFJcNJOnIf}FZgHo+F4)LeT2phdhZ1=oVG;b1ivT3^Ibf#+(hqUgphb9P@_9-
z@dfev!KR3QPu%r5LY`=zbl;POc>pv`s6b}-v@2|^rYPd#40e9cE+xu+4d8d$B1MZ0
zI1%YGeZoSbQsEKBj5dKEKhd`XzC<ih0ZUAhPc;D8=dXBn96Ne%W5(De%?YTvViF05
zzN46!hH-HA6QmpcMRq42`XCUT=mtl9j3T*27}LN-U}eD`MMc0d`|r5xQaJaON?tRe
zT|q^S_ANw-_YGFU9x6jL0ful`_Yv?I#bmHcek3TQjrkk-yD1N+R;-*lb+nNwN6eTS
zwT+P}OUx%VYL(gVssvhy)Wk;O&nN|ca7x0#Ww|2235p6#ah{+Eb?SoI2uq#<0!f@o
z%t7|wul-r|xk%{7i;!GegP=#j8&JxKon!umMq;^Pvyo3c-}!UYxn981Y}snS9p2!g
zD9QkU@V~;_#y<V@=uS?2=NtB&Bcrj!{<Lof#^X6dSwgXV-bBtf+&f2BN2NqNN04KS
z&}rY`*)7lw$EnsdZQ&z)#%4}A6sXfm*GzIGlZ^_BIZ24<B;P&m!7fMzF9`hiNQ;JN
z$4570CF{`@jA?Zzaz0_-Suq-Gg<jYU`i-?eFdvl01Yg$-Ti*;GNg?TZ!5g>}jyd-y
z*nDLldNqo9W#f4121~K${zQ+tVb2QvcftW2{sbm3+(S>0M}Z<o{(r*M+VJS{u1t!Y
zqgli%y58${7{o*2Mo{_S+yWrK_kh+wjk#|cA<HsRXMC)SA9TKhJ$b=$KOUCpe8&sj
zXe{UrF)<`e`s*k-cVkiA!wo;@kX3cXYJGga<r|Ls3#oe?rP-j=IDgl^ylyw{y!$UN
zpBR_HOuSzQ(H<%Q&=n>Km~<=kAzEsGcHxz~Zr#w5gqy4lJp*AC{bLZV81kSQmDodo
zvo9{Fi}~ev?1*TObV_~^DkaD{KI+6!0`<`yqbjX1xlj=8>jPe{FFa@esZ+x_X(H;^
zvB=XS55KIv5Z_PiEr;?`QiP&#{j9O6+l6NLmRbPq)cF6668PT535a|WQ$)kXzB9#8
zfII(B6CFWMp`1_AbhW#miE@BvMPYP2g5|%YQ5CE`l>2{6S#<V}IWb%#+20ow$0|Ky
z)@T`k6xziR4&+DM&0@a!0(pK^urObsf@C3kiv!k`mBDkr%8@b02e?cye(7(Wd&G6&
zc^5w|D3$X8q1tf3%aaCai+vHX%^S^cn#5HU*pn#}a=`^cwh<j5=s~*%@r%ui&Wq^f
z9p=|eqAI@KlPnW(!3ILN5gs6}LR|;hg?foKi%bm36z}G#O<M24TB2T2HQ;$6G6uSQ
z50LvF^vRO6fouul84~QN3%i5>cH)KWM6(S7MP!SL%M`QJvlXM~3yYD9kc;V@-y0Yk
zSrIpoE<qlL03a27kdA`@{T-w+i2`qKS`RlD80OXY*d}=`1sb525PhM1qgD;^ue6wt
z#v@YNg6j)UnCXct&_naG7L;5OujHy!B~XB~^%2$s^5wLqBD@V~OCb}lF&ET(CRwL(
zp|cZ?!YvZjairJWF)3a|BKYrP^N~$T1wZCR=aozjDsml>d;xpTG-rshIII;<ZY$~l
zYkL}P>XuzZ7vH*#Fb&6f;eLm0rNq5>uTKvv6FN;no{V-+iHh`|P?1&@9cf6WQ%jLo
zl^jWgPmvV}F%mrK$F_7T@z`nEeJfgq=z<BvX(O-><86d}s|%?Yn_Wxof(kf<at*f&
z3fp)L%O{Dnx!veenzXb;xuO7Zkb*r%Ld<`GXzre9R_r(Ym~M*aC4EU%Lnq{i<4Qi%
zPvczi6zel*1^E@34pK41a)d>_AuN;#)J-5(rbOQgRnAkTN0kYOsy9)FOGcax4pPKR
zMx6~8RYXgU#+;+S>2!ev60~7hL+QcrgtCTZi2Ocy8}PyB$>ygjGL`YT5CY-aNUV|d
zARB{gLYBldL`d^0^W!FY6zR&iTv%L4fv{1v7JB)_d3KYritc-~W$-RsK<qZy1K3rh
z>oB|Ehk-cRKd(?l|0{clD*;OiZiI}uuCV}f(QkR-`HPd(lO%gemaN?98R)+>!W+2N
zsf8d}f^$Mr|8hgix2QJ<z*h&Ui?O}8$-~cYoRn2WEE0n=6~!|ZTR<(oo`l;&pB$ZJ
znv~pA+vC}DwZy)HoV#F|44=%+kI#$G?|#1w9+g0|q`Q)?f~x!gtDcBdMTM(byla%w
zh5q;+P5niF0p6+Z!M(5IITV>G=fB0__QGwAMqcb><)jUG30~Sg)IFBH_{rr-fywqs
z@5#r>+&uKWe|vw0&>e92LCftP_Q4fCbS)d!Ozb)zBboZ?pkU$lU{f<Rb=?PcTw^G%
zd?G>>m#@cKJ-?=x=SpJM5!F_G${g2Ly<VoWb|9{jn6g1b!n=M%tt`{=HS_K$zU75C
z<fg*1Hp;ESl1{xF>6)#@0>0*0{26;s#S;IDutCT2VE4}MsZZq`SpjwP8=EnYCIb^N
z*pk?9wtV>P$o*aXI!R1*Q2i`6hF@!0N=r8qKdeOlj3Up&jo4AkF!>{>Py~`58fnm4
z@XxE6C`wg<dJn3M1BjyPftZZW6V5tpVXLGM+1NkgjqCEUs&7WxQeW$?6KN}GB>~Bk
zf-M=USkx*3T_*e~0S-0~g&w;C9#*2_E%Hd%ffyw{{75L#dryp|eF=e1%ToN~D}4l>
zK-QoPQG78?i;gd%EcH}PLE4)gsOsat=gq1IrnK}eqwOB&SLUIerw~5xAzb&}S1X<_
zaGctD*eO;G3E<cg|1LtUe-xn*gEoDKVs|8N(lr6-48)&(&&X%KX_uPiOdU*$H3RKA
zfjOZ$!EzlFL7#LD;H!r%lvdn{CUPQYiy{`zaioh%JnEgO!x+lxxz0R=@{M?EKlIil
zE0gE`u5E4^S{3!54Bl*hTQ(|(O-m`>`YN3L?1KjI4|xs3vZ#{zmFhhJN8dd3Y9>=O
z^r{v;uRUUGZ001eSFylx&z~%0?7f|7LO$C3zIn)P^W&okju}PNS72a$yb8S7r2~Lm
z8-gW-EErEDUMxDFW>R?%(US1$O#_J+k~X9eYIVq8KD)Zegji)hejX2aF=*{QnzA?Q
zJMG-+v^Wh7+GG(1{pU9Z!8cM<FJ&tnP2|V%BX9F`F&<^~2_BIS)lI6jVjXvf%iRZV
zN^gSU-n)zRn-~<w1rCW|=S5DMTIw@LbxBM$(?8%ztQG9(;P^%t*ehMJ{F5SgwZ&0o
zgHE3QWVNFG9&Z`Ci}w-Jl~5FkKJFtF;Sw8He7*afJtltM>EYDr^+k5Q`xfS;ho#6T
z0pmKM7aJH~gZQpmskQk+aQ^M_-lN-<ufRhWsqb1`m%Rc@ROe@H6d@R}?>mt<{P9wp
zo2^uPQ=#7SRL!yFyjz2fz*3{0ZafMO6?CYj4k4#v#LcWBjG8fwT0u7aRFZN-k?Q{I
zD7t0s&Qpff_8-5*zx-lqWWZ>s!2u5j9Lh|!DgT9<BPFJbnwDUsGl>6-sCXU@CcOlV
z3}&G6-%!&M#gzbh910}Z?}HW*qL3Ho=__Je1-HSIk0RgIZJxY*r|waGL%-GP?;KTr
z;p>h@PN<ytcVNVdL<~`gn_v`hAWRX2SfYq>BVoisi5Egl(ZBy!(ZBugaFj&Bf4*tq
zdk=Oz#;MJny>pZ+4}Pz#P%=<B8Hm9Nqfi4gR|7M1HR7k;fQT5%#_Qu0|JAG7U*Z4u
zp_}-5E%xP9^3}cYwS6jX)pFRb!Q|~yJ@N5EtlN>KfLkGHJBNlO^|b4JJL8m07ipmj
z#a!Ez=I)STEZC(cn0Dai+<?_j@36$=XBy$-yW@OKttD<te(v8jKoD7&xmf&r=RB$W
zR*bnJ?y6WTP2!n4-V!5Qx&EcJutpA48xx{GGw^5XSWArb<oesv!dy8}4~>cD2Dz)E
zUvTJgW%@Jd&JDUZY~zjN$a_eH1Ni(P9A(8;rr&u-8N;)?qZ^)(^{fa5w0c9>#upqb
zH3&sDNlo3*FOf+s7g~Db{9lW;TF@rp7{|{MX95=URUYwZkxhF_h&BGfhdkdUdA=&e
zep1~81-CS#o*ajyCq?D#n3NP1G~W|Q#ShQ>nU)a|R!FkRPL5(-eTC^{7Wo&`fs{RI
z4yQ{7r^|9dZBuID+yeMpLpX7E=(qy9_(D3*J!#~tH|RoEfjP{Q3cOVAxqpiSjln%N
z4llJBecZx-F-;qW=8G4|!}p$y{y6?hM!bt8R+QhpJhgVbcj$J-gzP)gmjZrl^muQ=
z?aD&n;T!4mBCG1X$W{vmwTH}6iy*v$aNP5+^1JT(&6(USzItoQUVn_Aj>G6qm;k1o
z-P|9}5>bNa3c=gkxKtFi1G^Igelj)?+ajp>l9RBCCVSurkQ=HE+`+Yq92+DlW|CJw
z`OZ?18}i>8Cu9M%V(6ll21_^ywlZRw(<MWG#{PbyvZGu3_1Jr(9G;$4qJBij<je|v
zZ8s2C6aW@cw&?uydZ7z&FOnrM*qAPPcL?<5%X(LFJ=->2p4sH*$&m%#D|?-cm`1t(
z7!_WK>?e><=RqVxnu%WLQ6&Evmq2feq8g_}7||GOMiQt~h5b7%ag8~aZihR7aSa2H
zLj<?Ip9lLJ{D-iQ8|t~`zdN?jNt`kS#;}s1CPaM6agB%#O!4!U4k|Y|6D#>6otV$$
z;^d~3QOx2tu|>WMj*NAis_St`;(Uz547MIsPy%wWZfQtI?6?a?jCK906c0+`!clut
zn9uYD<Pukf5q>yR@l^kSIOWe5<Xu48{Jt|!Cm%Fvt4O}*W(fmwMCZn8!zY4`4I6rI
zlJ5w<4MDk(b7QuVi+;jbr7s|sa4C$i!<mYuYEu$_8?`4Hia+%%AnCy)=^>sI$RQ{N
zgL$kh-i|X>gM*E^$r5pn7jwnA(u!QqDpobRRi0KplNd?p;beaFM)E~E=IJxRJ>5AT
zuIECe;E_0){P*a3W7b&GL6mn<gbp}d>-0O*`c<gQiG{x3rvO`)bWRP}d`poe$Kr8r
zR8j(og)HBv@U|?Gof=^ImV!uZMdF$$q;wMgVOfdLNi~clg;L7w`(J4qB^`&Dym468
z0196up%WI@)*JKh(qjpq|8B<jbNMX~I;Re7K2Rjdsd$__)v!R~X7=}Uz?KKOQwKU9
zD4gU}Ebf+a_%UJA_aBf4EKS*iP$Uz2=`Wtqz7k06piw&0CA7+z)?lSqitlXP*Tz4+
zVlGBgcw^pk_}skX?0j>>$$2OAS9o9%3Whpf@O{;cV@{=x#x&&!VwOx8MEFV|f=B(`
z7)C3G;{Qsl5Km=HES51X$I|+5X%vMlrYS=ZvqVBM!dD!TRI2aFFj|aKsUwNSPNwA~
z{|udi)2fh6t>7cxML^Xm6UURML@rGTv^J%9Y2U{w@J5;v3f;>Qby1*fE5%r~7H=k+
zs+M%A#Qf*!E>3|n(iC6lUY4kfJSBfAMz%`CIKvbalNhRc7*SQ9fr+p}3b_~?p5s&A
z^*aN|>VazuW1cj}{~QsnsK$E1n)4KMJpT-hP>Q(59C$#`CJ~9=Je=nk3o=QA9cD+4
z1NT{t2hb2~%hnSC{%BRcKLgK^=Y6@i6b|ws5dp+ekV_@RQ-2@E+}cFAaD=&k_YcYl
zk{G=RR0JY0)Dea-m@yPVnBwdJ;y5E-lKxNc!WJD+zWpLF@8=i`Gf6`oX8(H`FR_b?
zVJIn-VrJhJ2{~2&ak{dp5Fpcybv#j{KU%*LK!f>+VEp<z5ykm8_nYs04+J9Q;GPf|
z-<Z63%qxx{faK&b!UKVHbbKg$zNjTq$a&Zw5<xSD(1Y!`IQwRyru`;YCy|Zyb$14}
z;jJk94N1&qD?x4iFCR=zD?~rvT8#99w^SN|-_;UEO2xPw=1G!~>rU80&f3wPxw-^2
zHp+L3mP;MFIMqWDG>lwwd-ec<Q@&7zk1&$Ah%qPF5k9a~27%u-C@ygSc`CVv7}JGK
z;7iB;Aa8h;-LoeUIOPsicnZU*5;~?z$))yP4)>p-PmLGQRE?KMr>QdeXYQze($umR
z;{F4?F$-ad-PqsP5RZyW9j`Gs6T|LOsk^pyUsEY$N9zj&VU@KJgM4Y-NE}(DbVo7g
zodz1gR3Y{h)rmQ#B@A<(eS=6+w?D#$z!8<Y#%O@&9}qcQp-c{7hJc7M<=6x&bnGSa
zhH}|GY5ajLU#L&EBfR-G^yB`Pl1r_`Q=bfD-fl)bIu1O)+wdcC6pm~8AIn)Bal_97
z19wu14Bdf=9W*!fPn1L3xh9{ty9e}>6b8{=$PdP008v!FulDW}F7C8KgmDfb#3C@b
zDgDUe;(CkM0QE0}-ks_at7>QOF>zHDx0KOfF=3PtqidpM6fs0#;wdrWL<p%Mxx}IJ
z`TDF5UXMotL<XVVpO5`7Jlni0Dl042ybjBEkJHQ3mS?edSQ{6jDyS+OmkdcO_3M`^
zYj6A&?m5dXo+XU;PnqzibUyFJTE*0%pTD$PE_hxINUfVlE<t(isKjkrP8DBmao&vf
zdX<}{vPawQwmH?TLAt4AmWhr+vKrbI-6YS3T{Y#AzSFmD;;(1~@l*iYMOd!vV9$cx
z;k~PV8KI&B&Q2`Wq^fVpV0=Y{r{NNBa0pN$+&fC8z2Rau2u{z3l!xA^opj3F*9Okd
z!kw<IqfUdio>6XAK7UbIGOmNETK9$W`Eky8hI`LjA!^UGkdIWjXzkm8SB6RyOq<8I
z-&__t70y?pH#Mv#eZ|m7$qyxnOk1EiF0bQ?>e~QcS<_P?U6nCVv1UB0rpXhkreQeC
zqUj2&t{2Gj*662ll~xpuY`rN%D)V5JKwUvRu5Z<zNiQdJ3mkGyPY_exIuUaV6mm(O
zArf*;Z&3NEmIErDoN@1)-w6($ZZPb;;a@gzHEU50Q;dYj5AQW=P@?ZO$A*mosTcLh
z@x>!`stl=&gUZF46*#gf#^uV)YEi{9^<Ysuu?a}ToHC&N=bkdf<$MyWpX4=E>VZB!
z4s3WCVQO=km9yD*i(=-H88H@XpX^jTJ>1-%n60!JjTWtAw#y-xX1>kVtDCeA^6Lu4
z&F9*Y7S{AzlW*MbZa8yQtIUd5Mz;Z;#TnCI)Gt`(ep>Su8kTqfyR!VW<&SffmiZs3
z<ZUIA^<^S;7;O29?_=`gV)9v&B-%$?tr0bjH!2K$l4n3oy4fG%d#)R7sE@7RBaSlU
zr(vZ^tFG<qCeI8XxYk$><Jy$j<7(hKNO`w7p=$8R8>FmPh+0KRr8v&g3R*GcG~lu=
z1>oEEN6VCX3+Sr`;is(Q(s)Q9k|_mAed?!f`h~iD7RK3;k77^XkKMF^sB<1t?a{|8
zXvjoXhl@_1KP<CX&*^2uMAEIFq4OYot?18j+cE3&g?9`B87Tiu3bOO)>9oe)##iy<
z*v9vsxbVwb66YJl+NjWLc#^Eq#Jghd;E?bY&Bae@ivhMox?4R~hp~OFUoEyK+-Ci3
z2jov%LFY(~YTa<PJ{3FmZE=E6U5KM;Qt3mwR58AMcg;LVHM+nCkC-AGIdh&zW6l7=
zfLuJ#kLH^-mTyc`sWz|3oh2cWCvV>JWtt@Noz3w(9dpEQjGcRm1cO5(#?{?uRWGL1
zn7L#0G2GPq6^5RtYI3+ecN1XEo=Oly1IKj|Re$4F)k$h&e;elTVl|xuS?D25Bsl77
z!eB%4=x@|&Wms~s`_tr=@Q!4lSLO`%gHuhyGm&D^gM@@H0czz+87j$S@-0gbi#5Iw
zds@AQoV{IqT#=My;M6+bS;vT(WKN+_eMAlbd9FObmC-O8$?F+K(gT*dBM4K!*Rm!7
z?kYU~Shn7mqls;&!cxs{1LS+Mx(iO)(;iuOx`Mq~cJ!lfFGu1XkZiB5EF9J1*r|XE
z$mkx)pozlU$EnBXvD^JAEkm?I*Bl_PFcf(|W$s3)><9Ea>fWlBq`gPvGa60UB*R9p
z6=qWdn7IxA!v%j-Wy4OvnC1>6zy5PLMHxckMSCbSU_1C2?ICq$I~|lEW3q$lRboJy
z&~}`+2~GGum8luHN4SMc5VQy$Od-vod`+`99;OORD)A3pF%Pv>X<kDWa23Hs6gsZG
zI_;a)tLJkkW92H<Ue+CIxz4EXO<Jd|M_$+`<+8)+a>MC_EgRRLG4qNK!lc~4#ckbL
zPHO9+yuArg1C-8}OxmdIH8OZShMt+`xI%f#!_bw#t^T~|4naEm<`Cy5yQkcmy|AF&
zm1tNGC>9e#{A-5i%<Amt5lG$L%2W^5PCYuvVhi-sI?^5aF5Hwu<|_f^GXbTRhcsJ9
z5x)NPsCU|Bd;p{&g$EQ$(h^9;kexvE1+yp?=8rQk%V**NZbTy=5ZXhfA<&kWgJi7*
zzb(A6M>=)xRXt;yja8bBO}E7&dk2f26~vl0a>V<?TefrmBfR}*dpIkuSx=BRNjJKA
zA|U?ojKv;u+fQ_<be(G&0PmQfpcUPVrTG2@ck5$7O4cKkkMsj$Lea`>ML^<m?4mPP
zVY5Ktt)M-N)m>gVy4N6t@YP%}R^wPdy3o@k6YO1{1{^PR?js0lgb!4n>eb$37uOAY
zmlZzIizHNdr-#!Wt!-_^Jpho)KqXnf06^bFK=`m9l$%Y_f8TfqSCObs3WVU1o=|5n
zzr*43Vbl)4I7p&{2SQ(qKu;!g#PY4da2Ln*e+V`*D$JScvPPut(719eCoQfmymC$M
ziUT0R1(pJn_hzgGsr`}UW>HHH;8a|LVM}_{R|`z&cRfcu13BrGU*3SaVQ7QDs0mlU
zc|nuyKxASTm&WNsIPHfq;M{=c{Ca9^y31)@%4xmJzGi1K(A6KIH(aLMYne4n?~|?6
z5~6fVCpm{2QxqAKMn}kD&uKizE|X)L>@z~27J3^m{W`R7+wp4qoPLvSo%n>>l_4if
z%VomCZeS9ZQv(QXrtQ<gwo>cKIql1FHkxQ1)2%JpJ>we-JhVFIH?QRz(|2C4)v&sk
zI#cCfiHGMRsFv@2d$^wI+Tg?ElU=mE?cjzrE?;8N^5s{M1{hY`ZrYwwXH2N(wXmQ@
z%N1fEiFqC0m?3gn@6ORYg8Su*J`YDVE-e>;?l*#2&LRXlq<TLaCS)L2PK3_xS|6Wr
z@8<rcT9G9*VQ?pTOg~V2dQp3NQuAp`yMOb;CuzVwI$b5{&f3xI#tXOG=Qj+Phvw&g
z*&LoVy56aCbg9J{RQK1;?JrjI$$WJR%M4cdXdb51Gsc1c>Vf-8KO{US&1N2XKZbRA
z9=>?jC#%^OvuFh9a)A7#50MGa{DP_e(Rh|d(-jeL4mYM3VRmVB0L7dcZ+3Z(YQW`U
z+la%fk3`HiD7Caf-EO#;Qg<}cpg$U}Wzko~Wi*$5H%7JK!ol1Iv7?JbJsys^YjVw5
zr61NfYS?qnzV1Wd06=+14wn^gHfq>;UkCC@vjfC5LEz~iMpuUn;`JDF8P%t=FF+A|
z;y`I4XwpW}sSe3j?~`XTDov@Ikz25$J>tf8(?(&c4oOk(li@NdPOqDiS+Ios)Q}AN
z5w3+~m<r{^kV`fau7_mwMU<cjqlrF%1<IU0fDp+r49d$IQK&H_M;nR>rw;=53Wx<3
zsJjDlMl7}_EC&8}m^Mt9Hq`zb{=(r4eGm&f0+jT7=-CXD@iE|Qr3m3O+B%n5hPg(X
zI0|Zv#A6MA!&gpN!5DayXFxYo`+0x<M@%Ztb6cd}&te7V{TW@!0ba>o-UnkWUyevj
z4Ek+pk0;&^9~gZA6dSpSfn48c^RMkdWwO98@jaRDhPAp!$<c35d(>MOtg)MxLNrc$
z^fS-4NEa+PZ_;CYX-#rJdR(G)c*65$#KeNPbUWOMK>|<{tGz-BJ7l{R!)FV}E4?-y
z%QDN&m5z7jq6dx^W*s^|vT>a(LRYjn+^-P@6E?;Hzs3Rit|Bfsh}DlFb17483YKbw
zER2N`p$%mTc(~IUoZ2dqHb_<<DXZ^8)RU*8M6KjL>bUAE%i9X{*r{$b@0m^=43;)Q
zStFZQRs-?w<RBYui<=D9m!epjln>QE)u&`MD__c3>r4M+svlIhUXwZ2DfgvmtS!2M
z`n|yviK$*$zj9A?;)Tic2-HOR(uuHH6X2-PV>Qv=k{k80=ECJ^tJJ?9xO71Kvxufp
zaFAXhu`q$;@J3>Oi+M|ar1kT=LcuznEP+U8d`HRmQJ4uEb{i|wSpp2Z;LK>JKO|$A
zA_7PT$@d2V-<#1qiISSwpzMYmopFaVRYV%1-<F>3;DECFGF95_yNk>OT-U-pn<a!*
z7Gd4`-?*LGyiuJ+EUUntJU~3jSGC>JWzg-$JXt|-uL%~I@6CpMYZrq5wlDaQ-nQ{3
zv$*Yztj^>Yykw4SF0Q>*)Z`SYxSx;5L18_##C5}PNA-dH7t?F?9r6000AF6iFQ``+
zaG$;ff>z%XUs(3LEU{<v%9WPBB{BT`&|wd8vslD%pLy8@`?&k#H3<BaB_o{ssVwPI
zGo{c(b-~BVphVfsD9h*hhRO&x+^IOKB_(m<s4{P8SNpt^Jdhf&J<3Z%X^rtfM?y~m
zhz+cl$xwM1UGXJz2YeeL!5Db(1U5)J`-%Ij?Cv*|R!@)I$lr1Nj9odGv-VBbHYl0<
z;-8EUP4-EqD*#%j4*l-P^TIE8g46P+K!ahU-;&|s+8{{uXLOmT(u2F`WiiXKe1bD;
zCmx+OL&-C8-Snrb<nWZBrdQ&4H0EnOU(&LmkD7-pRo8g8-vX5B6t&4Z38b{(xXyJn
z&se-T&n}wJE^zd73Zyny)}T6s28C!_hGA~g@-#N-2aIuyIjq^!@-ORL$Wq7q4^^(5
zvh?Fjt_7=dhCA7MF6<poky}n-I!Q|5FNy%_6T=7hE0>}tc`=VK0qXFn6QzThmgltE
z&4@O;CdWS7t&w<keIxgpeB?~KCfhz$S@9{C^$q|Y+rGYg&9~%-J0`0>RhbiaOEqC8
znKTQ9Fz6<dhJvJ{S-u@h40zi6&d)B#9*x==7k2G_){7`{HfT#_EMuEGX~WG4g;{()
z&`}l4&&iI^muGN0zgWilb*2>v-|m&haQ*5Wp^Mc?^KNFpwJX0Uazws7!Bd@5-&sYa
zFRUI5)=7g0=h!BqBoCo!bK;r(I;3kkp7pXu^-DZM61t1>vpy`4@L|g2ZJwKepFh~e
z9d^DhzJR~0O$?zosb<~OY^3uz8Cjk7-(sUWC8|pJNlIGlX6Ze)Vfh)j@%<I_dFZ3M
zd-AE8HL80@qyR{D`^S1oupr@zDo@ZCS|E-fDkws4-e}%+&6}ztN1NApCKgziNW`n|
z>C~S1$L4|yDevlCXK6EW{r=Fig8k>M`>0z9cB2%!uf`7Z%SElYvqCReM0QMnfvs02
zZ)a?=Ti)i#q@&pus37;+b;k$)nW=kU(~n<p1%?c*OCeh{IwgN_#BzSwvWAmegD|5K
z<)>QM5Tlq$%2ZDCl!lpQWp%^8t&2P%e<@0~O4twscKBR}$j{{~?4dmPcE!tLYqZ9n
ziRM{)!K>;sLuw6<xO~BM2Wy7iSVtN`&oXsu8VmMPXIV(ZHA7(nb-&O)X$GOn*8Q^n
z)B;UhQ&L^|oBkmgA@b_RqH37*V|~&T&D1dJCv9-Y<z?;-qgkjEw>D`Mtx}JeMXFcD
zlBKb_Wn9YcQ4ZC76Dg6TNgc`aw+U4w4N|=*7So$Ql47#k)*Nr$389+#xp%2a%k0$6
zu*W^pF<<6?mHP)bzso^0uejb@Wm%EU@{V+7bG$mnJE0!;9cYceUg`Hbp&S<)Xbo?9
zLA5xu-6SDoneT^r8$jHvcYwQJ9X9g34mk-gh%i_2#gz1p=o94xE04Haun>5qe|1z2
z?Fy(u+;><cuyJtJy&UVB4kVV)OF?dVLSR#A2yo~e_*n#g5;F^mKTt))!hvWHN*>-K
zfUB3hM=Ou%j`|M!9dQ=)IP7lVWiRZyxs|C;9v+c1P;gU>9e)g(JTSf&st&^k3ZQl=
z%2t-2e{KkMmv!q{hu~0~kCX>YaNyzL(-rH)8CQq>rJcuH27M4ja+X3w#7Z+ES*L~C
zs1u0&9-U{g3l(f?4bcf?x><#2Ulvmh%&y&8+^*=c%HQFW3P{bvwM1SDRC(`yo#f2d
zB7^EE87RHZ1geFU2mm<C0GY<$=EXQKdl=M&wUjVAu=G5ggax8b*0Mg#n!UKCcdyE=
z2hx9s;^@gb;Vf+*+qe7Z@HJ!C4MM}&hx##mp?mBFw@we&R8d{>BacE&GLeVw#{^XC
zz@<E}L0tn(bx-0ty#v}i{4Dr!c>Dn5UWs*M2gDYXCtPsgxY4R|zEbXSf<672ARoVl
zcm?_dwsV%d!;=Ukh-#k`_ErH|D1RfLu9u>x3;`8RtVfX@1qEIq*aCu@mK&?1$91z8
zh9_1(mq<T<!$?x&9U@Y%MiKrug+S$Tdzeh=NA*El;=IaZ6bwjL5wv$C4G;^xLueku
z-0eb-*bDBaYq+|IHBcJCHsCK2cOpG%S8mX`WP?v(oljw5rS|9ZhRDo{0Mzn#cJ5h+
zGj0#K7zk=eFIlM0Ya|a`Imp}qg<gwwXAJo0_W(_l)BvbD9A;?5I`xm?*d_glGrvNh
zD0dQV1G?~iG$MT0BNxvGK6x1P3UUzVq>*aZB8k$h6W2i|Lm8J$(gvWR=8K8#jbfOE
z(Q}EX=dZVc&;F;OWfyo>2ZBd5lU1WCff(m-$CD>QU8J_pyG{-%8OJLlk2!hxE$}PI
zWDxOz!;qUldnM6$o$3;UV+j<#W#ca@7{3xdrb7t4Tj=dYLvu5%`e^Z2;Ihvlk(~Va
zl|$hCjnH|9^r*Kb)0Tvq68M2&p$D=C=5@a?QT#nE!i$a(j%gs;v^Iax;VglV4+;PP
zM@}9bA3r=iyt%n~etv#;=h3QQy}tW=e))3e>HpLr><4<)sG^xwzv$8CNg^Ya{@q}A
z1~;Ow_L#j~@PzoI$+Bq#iupVF)AUK@YSBtG;Abj>{cG0-Gl!+)7A3Vaj~CtH{8dfH
zgv%3m_|~b)Z9r8eY0YI)V>%+}*9aNMZih}h5UXzOt~`%9;+&mnrI$43EUBL=A(%~4
z^;l!88m*fe<8BRPWh*sn4<^SR!k*zGL%n1Q71<o#{{F&FpgVj2EcFiut_=_U_|Lzh
zU%K5$Svq{#K>z}Ka+LX)sqP=O`I3Dc&;7(ja8I0YeuU87SLmmSl1;E@EbVY*h#7(E
z72UpX9(nV!8^Tl`mg$^U#9{-5hkD3O*5f(Oh6(OWP@Xu*UI^?rW!>xp*p6ST{R0^v
zdQZXbdK<a5<{Z<KoWB8gY7lO-Mx@)jq*M5zR@c9hrO>KQKlqU80$fBPa!t0jIGvmb
z`MweGeanhfUR{J4`Q9CSc}Grd=};#>?|=06L2dq_;zH+f-Tf-j&e}BOG3rVwUi<-S
z=wpZ@w$X|>!CTBfs3#K2?=sZ$EEyJD+RJ4KLxA|ZA4ThogaCRdXt(!WfG-ueM4eHA
z8|KpTJI~5*FaM|+AA-Vr`qwch(XZg+gNA!H4Iu~+av&6fMAjMD2~Z%#djG9-^wP5v
z2{O5M7QUfl5<4)LcwYjPU|}`JshX`!W1eQp<>ovM{ApaLg~A)%YtFI243{}*_>JHb
zUhtn{K133Iz#AlrNT?45|0hMf<O#md$cIs;55$q72*vvFpHNuYn-CiBz9gaTQ*rIL
z!8$$FdGIa2t4D;cO0*Zm6BzgMN55nx@5-7wD~*K)rcX<_yvInHl7=$~pNIlKQrB6*
z@W%F(U@mY&{UKi3as1a9TSnQj9eO(CdVLt{23*!o{5{$~*Kc@eRCmoTU9PN!F4ObY
z5SkvAxR+KD-0496Ny)zFh|BPXko^%Q%@=MA0IhxsUwIom``CN%Y<TTw`2dpv2rN;^
z+sFR@K!-w;Omtyb;l2b22k)w8rPGhg;aJc{abXXpM{bOXJDL}~<5K#EWqIaADQ1pL
zO=I5rfltPfivwUMc$$ldzd_8z8)F}|4Z}q7v_a!BW34e`j?W(9>CEO>Gwhi^4SCyh
z7LUAyGWBX?ejfJzv{s$f`q}ZZ_GCIG{TR=@sb=g`FQas=mV5b^>hv+=Z*Q!BD#hzW
z0}scXILuoSzUfA3u^Lw^N{qR*?l(pg?YpveQ~Cynq;DJlu>-+3-54#_A!dA&)M$>;
z!L+~1C^Xrk(xr;i49PA?e~%)?D*IV-d*BJe4+Ye(d$OZ-<h5}+yP54A$*iPE{efX-
zA|t$5_Grm83F@%|O!Fy(Z<Zli+<ku|@5zy8?-z3Ux|GC^UrnV0_-CXn9{z(Uwyb7V
zMsfrp(92p!d<5wYX%dv)O3vjhY`&8-Hs)x)V>IB8xX}%BZV+_GCi3)!;zbsN=1nA4
zk~ktmLC6~}kNGqHZES`&kvK_XTSDnSyu++i(s(%v-OVK9F?rtf<929_G{X|~z@!eO
z?VE_>NK-|<!IVgfp!zXJZn6`Psr4q3Imr$Bf*0oJ2Z5|x76@J0<V0~o7YV|Fqs@0~
zVZH)ZlE6f9N*4*rfe67QaWZMD_&14CN#CiZw-UwquKpbjzm$l{8h<H0vQA=ODc|PP
zo-EhWt}AXV!pKm?B}FW6zA^5m<-0jtXNg-gdc}P7NeLf`SiYihwC_Vx-}+RxK_B-n
ziaKs10vmZ3^EW1F@p59JBC*jYXvxN%`DH@V-o>}{(6OFHBKvGW<+kJzq;LlRAt*8R
zD>C(GF{ze2)3nH3Qv=Sj$w;_LvX*;E*U8s&lRfFyyCO)VB1wIW;d2*yrGAMkzQZ&|
z$R+4=&!Kqz>}4iKK8sD6a~4VGvw@iF(I*9aEe0#0DDpFc$tPJ+I9V}dp^vWVERw~?
z7&-S3s`Q~>@!yc;n*7W|59iPcJztmsde74tXr1vJ+6Up<L}A*0AyF8IbP?Cs0}qJC
z&oK3VL7KuMRk;*%3jd{CR`afcDefSuux;aiMo*fGKOXn|V4OIHs3|!*^zavIfn52p
z^zrBw%?_?PKtL5K6i+IDP|4Eqma>LW^kH<%SK_Ce!L|p|LJbxn6(4<z2i$F{lFGIj
zFzLe<mKp{nYm6>jTlt}q+q_iG`klTSQ7ifi`VB*8IG-PmAS(xs0m>l0*!iHM&%cBo
zy(*p$qAB_`n%41;w#c**&j;9S>u=gSRXb+uTI#aRXZk14{LI|OIaGE{pZ%z3x?L`4
zliCJiRED+e|74S`zv&v(s6SYZWn69_(ac-sWW^lJG$&i5O?L_8mpKL7wcm)!oQm%2
zO*8#Sg}0GVkwt41FDu4wbSX~FpYuMzKJ;amm8e2rm{78*MrZJ?@d{j`Q@kWQw9$Kn
z1p-o+sDXg&CFFs|jjivcAH^@`u$J`m@U&&6b;e^_f=I}0ACsGWWyWpN1U9#F-k(5j
z)kvJ^IvETJ@@F!UZAJM_b88wT&Ba;p3TG@nnqLZ<Uu4cwT;8m=XHNsOD!tOlD-n0B
z_bu({$bL!+lUIV8KqfcYG{cVY$Yl)i9^A$(Q}vcvTKtmx-Ytc-Y31-m76%{rX=5EM
zy43pg_EX^0($Db`%YR_O@j3(`bH0Cb=gNEb9vtlvB>M79iVPN0@0G&I_@B{xpa`PD
z1q7}mp1mP}fvZF}4fB${0P2KAzSO@*2nhuDh6jN|>~spG3dkMlLU3fXjs?xi@iz$?
z^a=a=e@wIksCz;ydRh>4Q3#gdOqTbc!NaM&V(Ug{2z&4k!BSwOZ%1|r6gA{nBg1zd
zM1s(g0f~mm+LmOca2dzomKJ8`TgAbjbbIMq2gY8-IKoWB!}_IkGEDP6TfUxy;d5vy
zw#QW;wA&exs#bATs)TS6ZR`h84s}wj)DmhKWyF3(p^G(*pz-1UNYGKj7%5A`ic)<e
znvTmQnlpkTAw5B5puociL|#EXfxHcRd~fd{>;Z8Fi5}DiVM{E!95&fR*<g$CKc)Hm
z>w0P!8ITt}a%W^7<YQ3Zdf^Sx?l6A)sblf5t3sp(nHlnFLSh-x+(G#uss|Pk5r7J5
zm+^Z1kLyOjkDt_ngH37?;z=|;2dYPriXJjV$;+I_27`^X$NE<C%-_i)&$K?geZbpZ
z0YkWbPeWP{^hvkOrsZ6RCx*M2%?S|_W~k9#q{hjYAZLa;$U8&i1*E3HW5aMphp+EZ
zRH0`@^cp9BKwiK1orGwRD$PQ8DTm{C{~h=l5_mw$DcbY39=VqVo?uq=2u1Oo5Znyc
z3zO^ioEyxF-tvzdpxZ&*6$)frS@b#^qI`$-2KJ#S!4l3ca&>VMXb_G~5spnH9`>++
zgE7)4=qs3*TZB!aK96{I5cMDQ0z8Bs7LXrs^Y<dt9wEu0V8nF^c1$^CXs!wM^D*b1
z)^)+2PIG+-Rv7%i$JvlE`1j;z6nn^IQ0T!@?}aDH1(C?0<AeVgh!Xrgw$fwB4ub;Q
z4>r#uWQU4@DeSR4tIAj>Erv5UD?`-6Oem-QfN<kax}%^qnl`G=9v_<kI@|rTnc&u2
z+}=x8hwp=|(WnYI|EBPCgf09yF!BGK_Ieo(`J}utX92fx{t7hT$ahyX8{=;rEs|Qe
ztmKs?#w<Ul|Cr0%wk~WHvjuj4$`D&=jaZ~Nph@qg#qQt6`V%Qw{b0bJt7P3V$UouG
znO{Vv`xw*arv3Pn7U^!}>24(J8Yk%*N9g{(>rrZo0O`=^Y0&6h<5Z=0={t!m>#!{I
zwm0{V-YxOR;l&jOZtfY7KOYwQ`(D+?zg$ms10Lq3ULXDoQA2jBvUpF8JeH_xGF?3U
z!E#dBr8FLNHI-RRxX2he<bxP{kCnk0St94<tD1OAu~!*YuxM@a=M;%`qiMPW`?u99
zpVQ~3($sSrzL}4>&V917^QE}1JGGb#S02q^lG1eKgV)I|+<c&!4qX74v!paFbaHz{
z#f~#jxmGtwvSk(K8o_s4(2Iai=%}6SM`s|)#l)m**LW-ZU_n=E5iSfL%}k3T)zBY3
z7I$1NT1!}+5)q)F?<}Ipcp{Ec1eDQ5n1!1-owS^nl(uDZRs)~XsTyg%nX!H|3!DoU
z-voBx(Wp}CU2zRk*y}7|JPC&wYwNc9ebravpA_%irS*DlwX+64eX~5)8_q8sW7A$v
z)1f1Aayu17UUuBUw4sMy^Z5RFV-<@}R5Y3FcP-7-`-(wF1ex9gt&|`U`$fjJvi)J9
z4e6>Uifh(MhOwyVNm0Ry_yG0<?l!=?*EjEN3%MY~Ljb&pft4)tT54J+3x~Ik@m15n
zo^9lhWi0<@nj1UWj*mJnI+v3!T=lb$*0DU9N>_o}(y?4h&6zE?IZikLrR;Bh>&PqK
zO+fbFk8^9HDfqJ;!&M5jGHO@@7&Xfm5AywIuFGBDKDZS%e3c9oR1;Mo4@>f-cKJ#|
zct8<uQawr&&GfZwSJUeoozPj=lK98mgNy=TT_DlM94^qG2I-3EX8!A`G|Rm;E>SCv
zZ->U?gcG8(n)uOrcYT6DcoyH*7-gwK+_AFGTwj4D{e7F$H9&83_2?I(mk`P(ExkQ)
zReLtmQ{LEn%y64BC*!+6u;pa@?^ts>=t%ZHmShmxZ+)i$TMVlpcSxeRi<|6^+VT-a
z@0N-=SK-0<Kqn|0`7Fzf{&G9%KKkIN+`Nvs6~~D&It`wZF$2v*vSn#*SLpRqqJ-Vr
zLCJDr5vlZ{{Oa&e%X$-7rneeR#aT>TR-<G!XjC``afyvi1y#@n!Fto8fA%J7D_-#M
zYqteCx)tkM>-E2A-!x<XSdsqWUfDVaeYN#L&=-dqZ#FnK<FHGs05sXiqQ*qvyeQ7+
zeV*8K_hA{sESxbQ3GWw?Q^5?WE?P|z-Z(uwqR-$XPaeXgd}&OB?a`=}4jc<psYJEa
zN1GEKfmMOAnwWsRc#U<gz|x;3&)@3hqE;3)=>~BZb*EBS2pgQKQx|1)e3#m|>MFY!
zYo0#?`o3gxxQ(9gnya&=)qOZnJ#c;EkvN6vo?%pSzV^RBd|;NYL10+68t%f~m|lyk
zKk1V?F?y;UCYPz}&eop+4DvV-yDOr|s46>cd1*UAw_vUmzXpr&9Y@ZjzH9yFdeR6i
zD||Pe(i8E}%5-T=XN6N!qWnv_PO12aY@OFZpauF0%3Z}y{o$1ghRKnZfzN7nko0;(
zK6<aY@qqZmMPoa=g0#U4y^$GM?@qe3I|InQxqp<Bc9&^GT9H`xnqrgCZB1>0cXTmp
zAY571=zV=(;0rjuw8~X@^!dH}8X7>wibee7_eZ<hdHzfN{^3Uo_<>nml9UwvaDZVJ
zs{@d}N|2OkqMz;ZY*giJ^jj6foed_7&S>ZU9J@mC-nVPUNQImTg&cx|BCLG;B3Dbn
zG>Yo}*{!NGjU(AbaOY!j<0|9b5%yKWx1;5r<8?HQhKY~2O6y#|8YV(q4RCGZ&#q^}
zb(e(rvYF_znZn&3w?0)a<6U*zUYB_+E|rf&TqjXVrC^TIh_Nu?P41B48YF7V%XpR*
z^Jge~t5(&G?3WAac793fQj^H9Tf&Vh6QaCA;EVpgC}|)N`wdYUE4fL}fVkPMAG^14
zZ38vRhI3$Q-fO^6>qw_UQaLyaxy%e*sa#=Hrg~lHmv@<K?b6Sb=+>`U+P4_74-GBc
zA&dpddJTqeX;@0$Ea}vT<s68R=xB|&$t;R7;EH6ruBK?%?;Z&0>g6x%FNW0tcSgt>
z^1m+y{&f4g7W%CCV_!f)bB(iv2{@nJ5Z#0m`sqi01C<ODx*7YZhIYu~ml#D=-;Y1q
zEoW4EtF)BFBLh*D)nT3E3QvV`qnuWhBgfA(P7+u7HO&4OTVEO0R?w|mZz%<eJG4k~
zC=wuOiv_1>AXt&$8r<7Lad!#s5;VBAxKkv!6blZ;g2UxI=iGb#+-J|)Gqd*WHImFc
zBWvxq!gNdT^C<i8rsZ9(Q>muRhAZ<c&?f3uVkvVQuNb3y{kg@^+OOq8+{VrO<{f6r
z+;?&$mUw_fKqE|TSDrxwZ*nvBh2C<s$)r^g_a^RI15gm|#3AS=mBlJq%aSW*o>nO?
zQu&!V&8_QAw$OTU;pkOUnM|Glx`Cy4*u_qq8Dx{*Twd<dJmQ#K4sD*y(l;7O477?<
zdpVgPgXEGKQ5&$4x@IQjL;Dbp2s{spS%QlM#ZCQKqc5TlQ&U3%8af@AgXVTa5;z$f
zgru+ih2I3FI+g=BSu1cA0CR6wb|S8nch&4fVW?hD9NCI8aS1HS+UK}y-cIAVo8H*t
z{!NY80~Ot~b5>48$_^FoaJ#2Iv)?=^W2b^eBIK+kG77%q^ySV=WRR=_pA=wUu@vk>
zz||AC$RJnKiAeT2{E0fz@biR+IKSycU|ALzdDgLAT1Wlo>Terc#Y|m0s!H+<OJ-j!
zvTc(z9MeN^Tif<qbC@ju<q_UUs@jS827SC%SiIyZVL2x6%KnU4zL<Jp%&*6AD@3k|
z7O&s@lv>&kvHWFIdD6zC+qj_;5Kj05HK*OoX7=0a4ADyLWRw|)2n`jjgw%d%Fy>yE
zq2Pc0+samgoVey|?N#<rXyeC;{%nhG8tn*f?J9z>$xb>|b^;s}Li?Mv)z2MGqKOi;
zHe-P1&=>k+zz0LZW4?!0t{}fmjXQKWu6?(R@2>PB1`<xT%g%PeCE-+CGAgsdFQJLV
z$(YZ@z)t;m26)S3BYOa_L`Q^(<xRw`iyraKa`xaPXv*-5<l?0E?eY=iR;oP8x!mX8
z(Q@z3t>Vzn+)PB`8GDKcYKfl2j{QC+34(Z?4>-vx>K6C(jiM+kI0Ba+Y%HR7UH~+e
zHj894IV6TdA#o$RcmAdRH7pw^=ZlSdwCk)-Z~f}>pZ;nuZBhB+iO34{Z=<tv`y*7F
zu=bZyNk8Okz^siS*6uki@vW>+7>ZRhM{J`));3VrZ?_Z|8ad5ap_y;B(l)2Ljc3J)
z(qhw;EAvB4_8KF8Bo>YyTsDSIy4K3ss_vquuj8y@o8&UR!j{5{>w%E--04^a{N_K)
zj0D<<7{0g(R^8E*4J+W18W|OJ-hrc)jYCoisi0wcIgM77lSae+O<;-JWvli1*Im@4
zD9ER4@%mIl(8p}!95#}a=}~MOi{S%k*!yV8Y+G`b8K?MM)|*suSQSEK+G@@gUAvCA
zwMy(K1#A??J>2g8?(o=XQC-M->cuOFwsOs6=4$wk?Ft`G9@-&bHyJnM)7;A_*(hRJ
zZI0^{h(G>?($#Rx_#M-UvexKxUxJH26@JAP{=!|&TDO0PQZrj!dAACq3VhpNK6SlH
zDV_cyGAwK8EpY6&ja{)+UjJMi#)AoypLx<2E9qH`H-5bx<gkC@DJ<S_fB&zva}@e&
zkLt8^?s<~kRYLwfQd8ww(vHxSh8^4exVfK=t4+6|$sI&fNh9veRdr)oMQ;%es^FZO
zkFcU#sNMgnw4wLQYPpEZ-;qpDy?-UaiN;1i#V1EhYzw7nrV03x+R?Y!|D3A5ME!Mg
z;S#;4=nP5|%>jUWyaV06^TUyeR=$j_`gkbpDyF^o`%NhAb8vkU<#~Q7`3^OD#{YQS
zO)t~8yVB5Y{BXj28GKlRH(BPq6d~TwG%ysIZ|q6)+AP7zWkAGgRNdnx;`&`v7TuR;
znI-KdVUviRapxu4k0}(v`lLmpnk$b*Oa?T^RbDvqX$L-A#!oC>?dS6VK?W347;QJ6
z-YG{nR#V;Uu^0{lV|m_eo9X!<HxIV-wP<^$CZ#0}E~3xSIIt*>Fpsna^AAG-r`+v)
z;6Z=0m_{uc?&-AM{PxR;#?Lf>!J*;f1|7SD=<jG6rzjCiRt3{&C}c}=u!;v-L|pcc
zyQ8V2NlgYatvx-k^=Cf2exvbEY;-L53dIUV^`8tol_ZtD^L?G;;@kXId9nHgglUXZ
z;DqLJdQJKXG{q^~DaL!{X7;kC494knM<-X<>{Lr6G!2{{oE{k-8IFb7xf~>%Dcf&;
zW^to|(IkqFn2f|7BY3;W&9p}*Ml3pAGn_JbMa;{1r-Fsn;H2T~<~h9mMd)=Q-Ux~j
zJ@f3bA)P%N?nvi4;DF$C?Ly_)u*+hwW8-e4PLHOYOMQVOLU#~hqIWpuL`f#l7_so7
zhr^Ed++mIXT%*3`2=83z{KcB`xue^+u|c14pYev?bhI+>LBs=u5C1`!$lGn}(~%Z&
zr=p{;=$s*r9$o`LMfp*=04mLD=xE9_EdtN~{<r=5%X|N2ZJHZAUlZs*@rww}-}iq7
zV*hh%dwut^{mA7%%<;c||0pT{liUXPfmua=aevh_^7nq1viZk-g}sI;)D)VkrG+RH
zDoC&8wXRS3zRW)1YhuyPeUui%e5ra&b!8T=NVmawN0q{^-j$%&GB9NTUDG_23v7w9
zmqyx4|3m!D^P^K>j8jW;+=t!exX-iZT;vgP_e`yNC^0aK<(gspDM3s3qB~8Q{Dw`F
zyxE5HpR|{i-&TLeC@5U#7v7F{a(T%DPWW3UCYE%b9xBS)IswEWgtQ#7LTHFcZ5w9N
zb54ENLIsg83IKUoDXFK(TS1=jbSW1=t2Y>H|3QLGn)G)d<n9i2n7^Lx|A=7?E{whl
zPsG~-*Q}4wBy(w$e~0C`B}yd?!^l~2^Sf{nc($=aUvw<e_}<v!B@mV#yxM1k+>^B1
zm*2L9V6I=x9a37f+h^UjJ@)krG!-@%GM6tndAW&402?u82q4EYkAp=z;j(NBZHBJF
zH{nd>PGa=yA7%P}>UrU>F-S(mDfaY330&?vEc%U+dYnpdHaHt2T5m&-aX7t{TpV?F
zQC!{|_4}eRq103G{@ti}y0Bd1V57o=#?eF=<iPcyVBL$%BqhA+x^d_6=Hu~eL7%?+
zce$J;p!DBGUT~48@b8n?&*(q)yrPmA_+ris#&HUa*|aogV9AB6B2AIJsYEgbQa@r?
ze)m!JYH|s3MT?E4$O7Zwa_d7bFu9Z+#kIL<_;h9G?uf3oSrf0nD;nrAV_Lu)r#0*%
zmQ#C@{xiOD<~LJ16nAN>%%Lp{$(1f)x#zu6*8O1@em1GO>P@edj-$+yxUgjtYo?r{
zE)$WK&VlqutBHWmr|-i#+y>;9SN5_Ph12!p+vjJM`n}+y@h#J{Y=Ct8bo=7gj^e+N
z4d(tg?ot%bL^?=ljIg6Be}ZN@=xtW;>;Apcbr0YWp?e{6EI9x8;1Tyz{+KVnJ{Ui<
zp`)=mel#x@)27Dpm#FG*{KhJ@yiZY<&k2eqDJJ<Brv12GR{sKum^_{G*kzc%p1X$R
z7*v7TYg^-!R`)#ZTPKg?TL_8|eb#K(-Q(&*ZlDI_9{gTu{WYlhfg^tV=5_ZC1E7bi
zyKsNa{QU5&=#oMIDXR#hOU@g=V)Boq^I!P7_^E31U)&JKK*okFK6tcPXzX-C0doD3
zQ;G0zV|o1HT2Z#Q7Eh1)LirQ-EaEH(<t->g!`IBl%+~E`Y)81gK|<c3fs--E_<IRw
z5wKFQa@Kmtm|Xm&+9|Y{_+ysEi+HQYPvrsHJBF4os0K1?GarMTL|z=!@SXoOYAdEv
ziF2DBi540DM(c3%zQw#B<dFINoWq|jY4CL<;SDhLntj-3Huc)d@?h}K0$A6{kb2n1
z1#rG$aWKedETbrr+dP(Ti}$pE_u%7!>HNf2KL%?JtKpFDgpM1)+w^hm%;u?CxP_TB
zfL8`UImM?i{59e5+v8H}7iC7i*1l{ysn^C@eXr$Qv`04tjivKaQHwjAXNW<>V1Bk)
z>x<Mg3LUTxIL5cu1+e}2DgU20GksTSF6oo=qu*Gn{<hh!{_^x<lswUoL^nf5EJrNE
zM<>!Jy2o44zbrN@aT<ok^+=}lw0awVHGYf#Hpsq7ut`wo=gP@w{>!+QFAQoyGWfl_
z+{osB_>yvd7rxu);qUZxJ`J8W^CBE=Au}k;3sEU#Vrl(~tVHwlHjXx`@Ivg5Uxq)3
z_W_o#SA*cbR1Yx=nHs)asGvXmv))-eZ*u&%MXF)D6iZjigEyoKPVihHC#WWELj<ov
z$I^iEFnrVf2k&Q_P3cW(*b7B-%Ywn;4(CKOp_c`NYl2?|dOb!{I*;_2GHrj^;qGCc
z_dc$GS{sz+dvHjeKx~JtUHB?csFuWB4~~i1hcBF#d|R}#bS=%D<zO1N^D^RAsL?L4
zZV1#)@Fr>$fMqtsT+^S|>=SO&$H*GaFcEkN9)DzslA$36^TwnAMNV|M0fm#N{2d>-
zN6-JN55MCcrUtA;Qd1qCy2_E1ss5J5)y{=XhC*VW8wwJjyjAs2q?M9$Ui3azpA4P~
znR>7C3m=e+lZzu~{{}SqjXqUP;uk&&0P5lcX-rV5Qb)RH@E8WS{n8}NCF~c+axE&K
z{Y_NkQvcV|EN!vyl!@-L=Em<rO;<zpk<T9O#k!ea2JGxiMJ!iDd-gZsEb42vZ@s4>
z<ZbJ-F&u7avF{R*h!RT<=4r-P8W9@BOvBivW#)TxE|*4%(sNy3)dM<Wyqs3UE2{mh
zjd&V&DiQO=`!XABRl^wh7gHK+n9Zy5^Kq5(+F}1?JN{VhXx+ku!Nbc?jRV{wz=y&e
zWJTNZwbcY(rrU~WX6a9>-s}tXXuF25XFLCXe_APgzNzA@iCBC*(+U+8m4Dy0JDpV4
zQ>yA|SblsIF8wvtQ-(wC{Q3^F%M^Bb@#lvm#bLhMhI;V8s8R`>I*-4TKHoB|91o(l
zvFfu_c}qH3qwae;5xIPo!_;nl%WqSQ^-Lwgl`49d@-owJ-w&;MJm|eq&oi!)sQ<4N
zHVU3ViJW=<Ql|oo&9cji=d#acmR<<kT@yq7$VJ)}ot6cz2;b4Zz!D=)(b5q++^oJA
zeAN3=WK^S(;Gg>ZY4a29`bUX7>`JK60hK3{5aQ|U-`5%cZtK7(m3mfjQMLQI`#TSp
zFp8pb)f!-%vER;iNl<FGdFr9gZLfByaG!e3(UHVuRNHCcvyE#AEmBIiWv6Td?88&u
zcF{jh(sw_L%`fkFSK#?zk|T1qb+>lQOGbnLuUp7$iVHWp?i;s%+n>6zyGx}xWgAT{
z{is}Vyt_NabPhy2SS#z17O%PVkJ$0Kuiz{Ay%YcabKBcUmQwH6by1XTXRoL-$6cuZ
zdU&?v`+jUsqS@J$54tMR$k$w=)wtETeO4pCqj<^HiV>Z-m*%<!Mo~oHDOSPp^{Koi
ziVVPw37JGRAKR}jxx92+k4n=RcSN0k3vaJIcR=2W2#{rd$IIdl9nUO|w>DGCLrF7+
z$+Ux~Y=%WA0HdSjH*chTV4ouGH{Ke4HvP9)xNnKp%K=){i3MT<>_>`Ee+;NFuz^5V
zL$s4ASBuv>GVC7M?oy)NcS`9(hu`Lwx^_fS-9djwgePadH8<V^sPsq1I;CEjpoq}F
zvUlhJBEe*`IL3j~lU)Pcxpw2E=7-lJ0DY~;xzrn69A}Qu_yjG(--Vu6*Yw~0s5;y}
zA*c85O`Bny%Ct<3)Ysmmz5U<k%KFdS&;Kp^X`-Tko5QS3KJMPH6E9Dkw~y|A8wH#(
z?OLs=uyNaNEDOlTm0-I3p6uV|&)rQNeMcutT5SFn_q!v8-jrih*EIY9+KY&&uwWUc
zQu7IOd6Zh~@+(678|6l7HIBkk$Ky1E)7fbUg^jpm7pumrvH`a~Wci0xoxHk(`@3J+
zsMrgf>2e&T!1e2Y<X0l1lv{_C&zAScLhrvW&tBacRAK<E+TW|oeckX559!p#Vw}D{
zt_8K`1{UKEy>}G!zR5m=Qy|=i*9BU}Z-oSIIjOs~#IT}S$0qIlZbJ`UsLKL|=YBlK
zOUeQ#-S=H`{U|yVr!KvjBONFS(9-D1UH)6BnfZEK=Y{xPI6fxiCbP}L+zxeE{!77W
z!*3_w?hE+Y8}cq*o0lhdE@zEm${_EH-@-c*0NEcGyQPvRRm;t^|04B|#c$?%udF)p
z+QqNf9xNuso+_{nsG-ZMmof0eFPYTOGF5Im;1%2Ul=jif7%SHHi7?=ufXJ?T=X(3Y
zn}=2t_S={D>kF=bgkr7E4{wK7r`so+h0HDx7(t1<Lc{j6B%C3>pnsMTzKJdO+evqk
z|JtgEffvjZ6pbm)q?>Q8*hPt^a6Rvv-8pXA|0Vf&Elez{-rYZ}^O#AWkN(43DPhz!
zPyFjfHKe|ApRV%$o|5Zyw=OfYYH~@Ex$*Cpw(N=ozy8OEm|31Rrt;S!f}jVG1HVo1
z+lT{k&N0VdshMW)Zbfd~eC^b06WWX6088&ve|5xoJ7Zt@akIan`Z3*JorNLC@0gyp
zWr@Agirn(;Zx{`a^9#59eC|e=;Rf*yI$Nm{?2)iMeUY#aA99JC=)IB^zb^MSYqjvh
zp7X9qkK2egloAemC~Sh}p$PLzP-Yv|sf(-%#a8~RWJ3vq=+c?_-PK8!&vIe#O&8af
zAJ=^`oIyNGnn$CekMG7x+hlW()g%6HV?N0FH60OxHN`lFfetst0gwv6{aJa6%IVAq
zo@)zKcI$S<F|E(@%m+{#(v#Aq9SXqbi1AEZKLImNFxSp)2CeVmD#-W!R%yh2dg0|2
z<@<z8O~yZh&!q~nPS5TPd$v?;elT4Y77w0Yt4yY^H%W8+ja*W_mldBD`OC{88nuu$
zA|5bxnl*_%{!qtzJNNk1a<MP;lPIeUOfc1LKPJ`(KcR_3Hm=iOC1_HA2RB_Sau^%s
zegJLq)Nf6_d$#$_T-(!*EGI)Oz*Sl8<Xn6>t>Qyvdh8UvHHvb_avUR?J`jCKcQ60K
zhV%ZUVtI{_d|xx+LA#ly{n~n2;LvwNlTmF0OL6Ynw++6N6$sCdO3U3%>o@v+%Uk{9
zzSkiZ84wlvDReB!cpZ+d(xoAsF7D)K>ocjd-8rC=vAKUQTBv@xpXA);hBuCp@1cCY
zyh{!`(<CkS`vKbch*C9|J88aq?#krS)Fh|hKX(1tV%Z%a%`v&$T3m(*K}NG<uIe}3
zy~}TQlF-Z3=k0@Q871D4F?X&?y76WvSa(k2ZObvEC9#FB-6R{uypuximUT`3JTj%f
z7r+^wB_*1s%ZH7$#p^+avm@94k_MJv1p%8R7t1on#p3@gUxaJHd=q44?~hxK(;mZQ
zmyaZ7?L-1fZ%$`W_~mzdW~DP%8hcFW^S_}~z@K*l8}xfr-nsey&WZFXC(V71Gxr31
zQ_y2lwdTQy^_yl9IzJx8+(bQlJ|4(mYfod32hXpDUl%nZM$Q7|@!37YJ;TT0W1S89
zGGwjcOr}WgJ~GCM@Xhc|hEX!>@Pw2eK@)h3d5e`|%y|T`hc3mI#=I`3VRlL6^YJjQ
z*-Ms>!fENyVvj(N0(Rbe(+qmHA>rZXb?g&^6EPhqE+8`zg=TPyB}(B+n=nOO)?G&0
zd^AtyHO;-u04ngOoD4;E36Q2@LrX6k$&+l&+8VV7hM&}Ya!nl^-l!ftE-TurE71X%
zRwUR$!>X-x&)!s}LW0PRN*hrN4rTOZT7lNJRdW<6Q&>}2GLt)BUHGcYl&6Yi0K0s<
ze7S)x1ug}u6FYYLcBZ-y^JdCg|78O*7fDgcD9SSlm4E`u-hd^nVV<TSF+2{QJCeu%
z`W_r3u03*rz|x<klmb6%I)OdID?k3puSNbV`3LS<T&Z2D?YUi9b*MV}<nGhZwMDq}
zcFE=x#~#a`n+C@o?~t1Y+s`^EqR^&yghyr$wP)2M*c_-o=>EIhT7c)noYKB)57D*z
zwfmaSwN!H{_h8$vwn=SMLrZaE_WJAjC~~j;@0hs2>Yy1(#R(cSJOK``0MU*&^SOIf
z1-4Q3OsN^SvA3~0!y~oJe5LdD^M@&Cd$X7zGj*>v(PfbZ1B=Zxj=d+sMl>dVMt(+h
z_2BuR=p)yGrLP$l*BFBnA`sQYP41eY(vTCJMA_@)MWO#h{~q}bMQ6)2K!2iTv{t`&
zZ{Msb1^v`+2w{eCtXZ_FsnDGs=B9;FHsK6|777lG%*5+|&UbiE+HTWWilJ%NXsmIa
z=NoK?m=-a1UQW?o)$_l-2SmH~O>rHY8}x^a4rmu^hF1<64;s<0&b`l{IOTbTcohTZ
zZcDGhPT^j;UU9&w*3R2P;K=?qhL5SCb#VzDW=C5e1swC~^XY=G<2t`g<!bg{_>5*d
zc<WYlSt7hZZHI26U*tw>oI}rvPjCdLhXKp5`Uc(M?E_c0=F7<DiABq{wD;tJKzjOk
zd>(T%LGs8;gBM&Ux8d3{04FV(;cy80B{`5BXQ+`pf`=l77Q`9iEI=w%9-?Q02GK+*
z0!Tq(!R#O1q!OjIbO>~)FXv$N%{;q0D4u(`M>>lCf-%U&6Fr|&Q&uC|8>W-w4)XA;
zEdR%OerLD1wzzZK={eavv1=*1y|}+<jf3&@YDE|=JzdJ3a(GYxnW5OlISYgkwyrGk
zPBGZ$2`qWedX0IFd3L6)Z$RulD?IFVcw60CQl_X5eGYxB+XUv*Y<>2Ik4Ut!TSi+L
zwc6?@b*&Kp61}k4R(w{7A%>pTEp*mONPA>OE&r9nsj9WU^QTjmQU)RRE2Jg~H9oba
zZHO49&(vHZ)U0s|!_LJvIG3hL&o-~7b5=tUI8;WhBP_9!+!Y?pQNaB&aNtLXv6|8w
z^wf?qck|Ty+VaUD56Zrky!yYRG4$)qjvE$a4~t?Up7V6N^kj9FpNk^Hb{S^%%zLin
z;M<?=WK?d9P(#LP$L=%Bw&pm`gVl<-(|E7^f`wkgy3@p$`H81LajZK7GbXunWD+M)
z?YM*7CBLK2{`S(#T3RCGr)1dHWXGd;B3Cag+-oAy!zO=+v1bfkd1butGWdLz;ILJd
zDj9{M@}#1=dbI5m-kTr6{fq2V%2Oj0m9|ST5)ep1pO?-}5GX3cyT_es6gBo{o+8jE
zVU6XVjkP<59ypO~Ka@lm5f!1b!LY`gd~Q12@?mH`WB=%11>#ab;iRJYKX-ea;r2qS
zJ5k7qz1ML2*~&6FKL*$hr^6Z2J24#Zg1?{_K!q=8@WM>UE=B7OI|p$9Tmlm<3y%!$
z;I>q*c5j3?YxLiM1SY8#zc`&5IUq@ImW`9I9EK-B76o>X)u$7*v?3GeL6EaD&vD>a
z+ejl@ODt>J-*x$@(9*wlK-Rx@<qu=p*ZHxXzFB20rn*8%VeCs9bL^-%f}4>8=Ud@s
z-c$Qs<>_{Wu;hJ4IW~L=EEGWVT9oraJy|0s+bBB*=53*2fz-egrKDhD3NU!36b;EH
zmAsD?%C^kjRwKpufg*8QDN`A3e*ixzzeYa_dFJ$J-fG1PCg0%M&_qQz^bE$%`&+H5
zW3Xc|&(Yn(y-})@t%Hq$NI3v3pG<B{%+l`=8;@E+tp;Fs{#*@gf9=Nz@K2HC@lWv=
z+3nnAB;mwLk_DinaEt>KIw^~-)f*H`f&_vD6cAr!vdi~Z_SJ;-XgHJNI)yugEl?x>
zlp)n@En#bmD~nWzScfsVEB2ksYOtTS@-Fk$lH<Q|=Z(0NgQ&ju*n)ZX-w4yG3Qvp>
z4PtCmtmajPS()Z_TuD5VOBs6fG~=vm_91$@(<ATwM4Q_*Y95fgSQ=v%gRRr%lxAtn
zXl1a5_Z~Kl>;#zZS6mg2>#KF;IId-{AO3dLQL)iJNFSuTtMxV6fcTVHqIFbFR4$U=
zmGT%_I}fuJZcdl_;StlMj8tK`WoUj16rQ7ISs}XS!<yIM6OTS&zh-ybD|ZFYd4Ko8
zKX<9}Vc9UWG?d(*p7YC1+})#O+5B*=wQX@;c^Iv}=Qkr-T$SWg?_7OYwSsdk)?9Bo
ze?EUcG52!sWn)qsMl$}S^7bR6i1EXr<L&-k{C&|avpH=IZLT-ktRD+)W;whdqBu9x
zxxWI_`zWbEZMLNfr?!nsY{Jy=n=I3qM8(AIRbjOEM3!hqU4Pu>P+6-WnPM|_-~_OJ
zy*hPUk%<g5m4^+>z3C0U>t#$k%O%dW(ny=_1HRkg%whChc{*q$1>?02xAprq3&aGC
z^Cw@+8Cq~LY%*b(sQj$_<TFP1q}TiFPb}rW>whXuoEx;*gn2bi)_`Z&^3u~Q3H5$z
zy}P&a0^}3V{aja>Wf{=1_mjNC!Mr%W#<(8G&u?gd4Qlnr>><zP(?6;7Ic|k8_v$FS
zSguVvSjk7m?N7$kDeD)0M><gmDXo)D_Ta-}C&n!q&4oZhp#G4Nv5~Pnq-$hCT>2V(
zjX67FA`otyUbk+!iCnYsDiqzOhT~3-k8R72sKeD|57(V@68{S1$z(y+XFk<dO8<YH
z?Bb_dS>-IqOb#T^APXWWQ`;x^-6}@tyVZN~lAk6T*ygGnHmV%s{9ic6aZxb(OM94o
zY}^>9o9yIm(6!2O*4GA-=aNFN1L1g$c&a0v2c1;nt6~yDR)L9GW_{va)O5BB*#}?B
zB_{eDEmC9h!eK|8Zb;$4wWP(Q;$7l%Vj%AqV4jU*{g)0cH#UzyLgPXYOQ$$|kqbeN
z&c2U%%31ERpN}dx7!j%>Ls8@?o)S4-XB8zN3%xMCZscH5f~tbD%+n3ov~W-IvpfTt
z+wdzYfj)~*z#=+Jf7T|cYC6Bj8=bwr{1^pb8#|1=*Y5$ebImU1K#l&7Vx9<13WM2t
zexF99sxnnByw4v-H(IVJIi$#2lL4pLVzM;6RG9fB9zwpwRQKSLypj~29=<+&ZMmnv
zt<S=J$a=_Xxvsyj&k^J??LIB5eh4{)RJF8w2sn7>x;?bju^rv$a%+3srq-cWq?dcW
z9Pgp)q3iL&%B{bMo2MHL!&y<tCl$9SdDXhqnwL8?BlcJHS6$S3*5vt>C!QSPq0u2e
z40Cc7Q`3IV48Z-D!2pdGNRCytpX6Df9Kl!~k{^ek%8a4MmMjK5ro1B8xR=O|qt1F@
zH!bHP(8!Y>N6hoX=awrG=RFF8pHBMmE!yN@dFQd`vCfzeUKKEr?lg%EJ+7ph3Xh5^
zpT+BXs*To_*59)Nt@VP}k>};eV>5S;yrEOG*dJ=9VQQwrz1Lq-y_{M-)-U_gxPrWB
zy=dc{zSn<)h@Ftc#2#{FD>^f5aGfXC=&vyLo%}p!GzWW>GBa%>&<%gs;`z4*0r6Vv
z#ByPupz@L$XnHmAIj%XwR2kX`V@9IQM?hAgkD-Vh{~Z53)zjiF^}IJ>xJmT6Dxl27
zk?#bI&ly=k&*e3&p2=$reF~|T4hhxDQKSEo17lC!vOq|U{*j-Yq(G`UYFP~ru@3OC
z`fYHP05)im1$z)_^*cH10UHF1wWX4duJu5Zrk3cdT}?cj)}7DV6`pUED=rAiJl{?|
zK)jrlyu|+>?*BwH49?z_fkpqFmb^4--T9s3iSn;`2%{dzZ?cpIjsS}af+{>6$_>u4
za47@`yU77LkVSNs-DMmGvX=3!r}Ytlyl4hHTp^-8mZoSXE`l<Ga>M=9nyb!@vNhlT
z=n(|tj@)~+9UMyCcNEtXw~mM0JF=Kn9mgUT)>4*kZ|in#;?@_Uw5O~AQf^HvAbmxZ
zcBeTZ?HQ52qRJAG_CO>o!g7N`qH$c3d0Jdf>4fUkTB(&&aw8O=<EbCW{t(1@phT_u
zO-mQA9N-^s31x0j+UUSf$Qu8jPz>`4-~?a^Z41k>EvVgFfeg|Z`C9pg!f-Tf)SW^a
z15TmL(*>T0pewXIZ%85sANK5vT`{U+@NY}Ya^Ch2jL?Fa7uG9$le?d(%<T9C9I47)
zk1d=Ib5OmsmPCF$Pxb=hY6V-EY9-54?6}aSY6n7LRAnS%3$JyJBK-mMsapVg+!`K)
zqMGp*dJ4i_KNi}Ut~Io&dxm(C_p+(67WHP)I~?_7aRKsR#*Lsy&;!Nh=wc-#>*MMy
zwg`b@{X%k)b;>ew^;7a!g1bcV&eo+hsFdTUjEfNKtuSO@oA&>BrJKBehUv$KbN>vW
zYPHG{wXn#k0j7W@8Me%Dtqdk=N!p)caU&3Jx8mwpY3&NrmF)!fk_Q?=Q8blK{VCkh
z<QN&3zhXe7Q6rKcTrPx77{WG<TY+66`I0n9J@467L*i7ge(BcQ9E5fn#~$0>gp&C$
zFY<|N$$xqLwv^BJEcSOT_I1J53%tlCmy)fyCdgn$wq{wbrj0Gac=S_a9eU3#_3RBo
zi+3O6>IKXAn)zwuQ%y!T$||4V1xe$Ad~xePm8D;5@kiVeClvv(;6Qw~w#I>gt%sX1
z@4Vg)oUvT9SXR`c<sgQxm7qC#IlNP-D1u9+ws&@I-5J3?KhKrJE^Gl!$xVQQysAZ|
zg>tzHV+bq;u#u^I7VXgXZq4rnHWh%4=N1EQjjk^SctC7}gvjbWi_zLm)eaB_w0=Kx
zmwfZRdT4Cm_!)v-*a|w^ZD7om9q`F8qvQ<gh2Rpl@|l&}9h|6bD>G->XE1*XZB$WD
zoJ*6#ir>J3=w#$2Y&>`UssEn(p?_uppddadb>vgPtXyfodV0ag%D9g804GG<AP2Bv
z3Hh8+LcGoh`RqFOnx_{y28^-IdZ#k|x;kuPc3Uy!w<lYMfjwi{wC>UAe+TuT`$aWp
zo@_>~OY$>~GmXh}{+i$pPZY6AMH4L1z$HJ`z-2?Pbw{51e@MHciD0U<{Gszdh;qq?
zBxr&~T6aQA!TLw1C2TGa^w9G|3&HwWU>z66vj1j3u;c;%D`0h76TGAGzmGR}{wvP}
zhX-K~c_#!LxO7kacOIKs|C{Xp3f}#HCHzlG;Kg8lph88Hno>p6F{pKCVD>?R(?dD_
zBXwu%za>75LTu&_?~Nd;cjO<cpay!V#)lW5x^ph@lGJP44)<tQXx>w+UUKC7d&PUj
z!~fFk*Ck?@?@VOHM?^Uh*YnM`i>|OHt^55&!iBh*7u=sn>vQL0V9HJ^CSHm23H!8*
zPR#py=OV}O!wi)nhsQ^sK<8WshO&68-<1zg2Pova{lRjdVI%*8t&Q`0iH4sLR{8+H
zCO5SX{R4eH)Zjj2VdHtjdGvVizQVP?;0gmZ<@#1_+1&1{Y=7Yy>LLDMLgi^kiI;8x
z*y3A)*{zXpg_^h;xT1N+(q;EQBmYQ)u#*}pn$#OugUN-O?qT=R8Pf~XvoDS$&E3+P
zBM5$6tT4DmHG_n<FIJvVi^EISf^f<00@?OmZXDEP80b43<1ex$WzNEP*70(JIfX(6
zl|cA~=942uO5v(Zxtu_!U`FLXs#3}_ap51vQ<zuptIiLOR8gS&i^hGknpqqE^LaC;
z<p*!r$EiKKAULMLGL%p4*$}Bo9?Q5aeRrQfK8sR}aUP$vJd2WLo~((KR47r5aVU{`
zs#<tVfk-ePolGcM;^EM>jj_}f+vx83=E=V6lJH2%sQ1B13eXEyMCct2y!bNm5%h0*
zG=J!~;c}M!yMBpViR>@SdG>TRQv!sXV_ffT#_Hd4PH@q$3+#~{1ya*5RjvgI>|Lzj
z2+On>^#;F@`W)$42yOs}NAChAcG)Ddr|ByAjq0wIzQSGl;w>4lUc*8d)(JuaucH+f
z>@9L+lTLyxOmXGnf!<*kB%SpvKkNa>*Z`+M?N0hYknFK&XD-pOQ^wmUk@r|05_B6_
z)^f)_10)1791LW>78mcgoid_L-RJ&DgEO;5-hV$1pp65J5U$2BNzqFNO9w_9U!<&<
z2Z#&Yz@vEs6ir_N0u5CIqm{`excW1B_Xx(L-{;XwI=qwY%X_m@&#=wg@{WP>3g<TO
zGIoVA_CdDQjEaXu=*qX1NBW|Q<PsDxf5r6|fIyQ#fvufyD}wz%Ne8keo)+m;IHf7Y
zot2={al5MB->ikdw$=O(>7Vfg@O1_o1?+5yynpH;QL=LQBDD732)*!9t{Jc1M?D6t
z_Iu`mk7f;0BJIyvaP2>bcIZa$xnrvlE&VY4?KMgFW*TQ2>oP*twG-#5w6Qyv+MDNn
zL?J8tvLr3)98V5qU!Omy1q5#jFm|sf$+@=Z45MvNG4Fxx0G5&Y<@rp8n*#>6rF7FH
z+#}rF(wi5I!b@31K?2M=M=$cp?63Z4`bMcyE#(sZJZJ897w`~Jz3U`b6@f}cVVMmC
zTZp=guiOSie<B|fighAc|8%D=c{w`K<>q1k&~VRzEdpNlA2ODEiGt3#f3Eo`y0%31
zhn{nH7u#FsQgy$xDM<DNbblt;z)I@Ed;a-GyM<166>y~f8Q)$uCo6$3R_kA0-uydv
zxexu|e~C}>--V8J<~jTZhsGGQ2-VAlNMxO=Zx>2b>T&p`&>>idlL9^ts|`#3&^akV
zYyLLQi+XDr&a=cKMQ%<>89=cn5D|sF{80>glU_OCKIyLNz9eYYB0(O-;Qh0j?+!XI
z>ygR?)pLnYL1AMDG&AE}xBYo{^J$AnOFi%`@y}<S@#c88Tm4CFKYX0{jfJ;9U7u9*
z*n4H{GI%Jtwc%`cv}5c`T&}^cju8#2Wh4S2;`!d2&ySRjD36_vos8MK>z46pwdN8u
zSKSf-1Lxhu1L_0n#=_l=;v}@Wg6Es7R-q1VVJd0?*Rc)Cm+8mCj-t{H6=5nXZoeal
zR@xZFB=HY|FHAPz#~CvS?=0_kcKL$mhO483BgFOAH-NiUE`YtIo-v+uy5njV|L3%K
zk?KS#tiFm>+3Gj(hen|SNa8tpxiKxv!@OUooVNa^lS`%g3@Nn{bNOmS-GOZRMEh}b
z$}He!gLw{O%S_ZkwAnGWM6p)0!gb)O=Dy>;<Mup}6ONohtvS*>4}_$j!?%3itxlSE
z=*Yk*T5u~X%<1xlVIy|x%fDR?QE5l@tkW`3C8+GwDKw!ve~|`CGd%t|DoBK1mQ*wY
z;|@VHXX#=J)P0inM(so6{Y4E<XV}t2F&-_fx)%&d2<Je&ejS=Z(UE=+XS;iajL+tK
zG>yvVG3Lmd@+0-N!caMP(A$nte0_!{MdyS*##d(09bLZN?fJZcq0drgIb?K{s;sIc
zF>yulMWGfXsvKifIUZ7B!Ku&s7oHFdA>Q@3{IDQCvJMss;U}>DFei`nFG{kAYCdR{
zdKrwXaxKQc->%YNn@%Sr>72NAgFNKUam=wk;5nuKJSZ%oAhj#f5yfn}qZ?ZJtt(iN
zPWWhBohJbn{8}?(CxLEY@z_cL)leL1!8zugBa>rRf1tL7jXxNoMS%DKQ9#n{tGP61
zF-bWS+S2d5pOc;hAxHI>Kd(l;#d({~KtV_Gfx^YG{cnK+L$d_m`(Tm~SpgI&?2Xi8
zDI+OWDXkn+x*(y0M3EfhbGHrTq1<iC4#lr?1GmO9%V~2$6d~X($2*83a=perLwt}Y
zr_OSDUy6F7Z5rP;`6`h;ZDD^Y2QyrqZoxEma6c<hff)6fxT-rX-T&15;VfxU>N*6s
zvHiSxddr+aCo=X%a4btmAaO#9exl8CRELwbZDp`yzGMDjZ)p0lz#{>CJFI2p23~Ig
zBfksZ4#^b|R#eb~)>!ex3jNAv2UnmWZac*R51U!*tSK%}+IMdCmSMPjAGl^n*{Qg3
zKx9x)q3D=(gnN{ii$@?u_Zvdsh;69!)pW8jmO!cip&j7x-MU&US`^)iev0lyo1h8N
z>S*2o^Wjab-l4Ss_I8rb&Fmd-S4i<CEJA|ADnWUmbtxj5c#y_Z>u)XrPV{I(ei=SO
z&IoPg1|DO;%3SbSfWAhFu(7U`N>_PsTd)uQOZrHuH*Yh-$wJ8@$rxMSI<l<FcLhjS
zZ@r30eAH1H%$CR;MtuD7Yjw9#e+`i?D+ez}4ab@K%vYUHeaGE)dd50tmNm!;&7MdW
z-*o8Hl@Eg?9s7yt0nHq@>J7`VKG-B|fyV-9OI`)9(L?Ih=`osGb7~S4OYLAOg|mme
z3FQOzNX^ly4<mjhvSe)N#EkTf_m%YN#MA~1jfTKU8-p(j`V#x5`iNsnzgZVtjPykW
zq|w(C90cz%E)X^*{rj|T^so1o%9mO77<0N&nT#l^Fsi5r8!9Qw+&7t$?L}`T6g2eW
zMOj5znMyvEh?G!h^L9^54>Q7PQDi8pT0W~wqVjNvQUkx0j|N!7ZIb^ho&%|o;iOoH
zzbfd}%N%6_TxlG_NE!WypCT!zTuMnwVXVo*#QBr6wzCEjAOxKIoJ^|!#<Y#c^TT_?
zbZULt#kbs4t?xX!vj<8W7(8{Hb)CJOUpg!*-2`qa1?c9~6CQ*wDb3KfW=1Pehl)}7
zh<JXyaz2$kZQKeQOTwy<Y0eq#X6E)>m7_5U#R}!_?dqB_R>P_>hI8k0YjW2ZTbZD{
zhMsah;m5D*LK2h*>qs|zD2Q_~88YiYa0|a`)UY4QNN(kRX^h)T6$Zq2Vnx4MnN2?7
zHu-gwY+WT$#y|CT7eq#29fFb|C>&S>?^kVC0jqviZB(JE097vPf$?*}OtXQ-O_
zTs`&%W>CLs)o-q5I6DqzYy(8AnqOTTpX1Yni%JN-_2O}5b`^Bx!$|Dq&#+YyI;z1r
zU4J0D$roe4HB`!(%IRsq0i3`Qe2`Nw8CaydriI7OY{BLLtmjik;;pAAx$tC_w3j19
zmt>k`8h0;wb-LU3-2zelPY16B<&H(i+kopeTzr}cVdXyP%QfZRh_3XoW->S6ffbz1
zAf?M)^bZj&ksAPQ(~=@{q3x~M!XX9_!`_0gDy)^R+Kz$N%%$;qrh7(HIy{cTUZt(-
zuIjFVyDFZPr>qLE2@u#tF3UI2w<S5K+!%B`Jqp5VoUFPaJStor?aGW0rxhm=r|}zR
z)vncgnoaxhnMGBP&U3w5-3bJ6N}>by?gTYOVV&+$?$UPot#)kgjh-iA`$AK!L#+$P
zil;THQN7E<S#~u>+fC=X?7HkF0#x>NDsJk1htV$c%JW^u4z?+*-A_N_vudUo$-Y0v
zGQv{DnhIEd29hw4;I1SPjQf-NF|AT8`@6&E4&x3+tig9G$`%S1DqHV-^*aIsl(2LO
z>X`NvXVU+uG>EUfT^S2l!}7-}!~zkFFzPYf!8$a@-DcyT1u5C{;*ZAi%jiaXqRi^L
zXKd;;bQ5bw(8vU3qXb)$_x-lDb-+50I%&JM{wZVYT0|w{p?x}(=VdyE>kt9LHmw0(
zHeOhGGq{8_HR+Y<)#+8~wdqX4CUuVUwNl?d0#vOjRrnaL7zGI=2{?WUN+co~=LjbV
zod~cA2kj*i!Aw&OQ;Z`@@XQ%9^|Tpy1D~VE>Oj|n@ofd8o{BfvSm2!5k+RY}v_gIX
zicr{7SOB?yJbJbAX;rQxyUPfIhYHE<QrFS7UH#dm5L4I17DDLSUtU95`0){$Sri>|
zE^Z&!E2A}e`dcf3pcBD<&Hh;c4(2(g8^ef!s?V6&GwoGY)Yw<rzqYTjud=T{d}F^k
z^Q&!s$$r`1z*O8+T;6>_tSI9zX2KhH4z#zqN6KM~8N`$(@{5J+l`}BPjTWlKvQz_D
zm|2<n;Y4w!VXTVsN&}&+>$kD%imXZ{q4patX?$$O{FafIpT=AAqyv=XICdx$tTrx{
zATdbRkWC~@@x;`?S~QZ|(rH|aCN7V9N~pF_u2s(K)%geNO5A@Tan6F<+T$TboR}NA
z!q^dp^awizp-es*!3<}mv(f%1UX7-<)$eDyTs>g2)r_vd>y-5dQ!kj%HGCc30Ns;|
z#f}?{D_yhg2lTrf@t57ytvB|cm^j5!#-+t2ec)0tNNExBusy!&D_JjJx2s|C(1k@c
zvU-4FhR0&#Kv^MB?8{h{4|t4tpqV&O9GCXbb%lO#ER$LuQTnA+C^zG~V{dtFd5us2
zBd|LrHc1VxM$QfA;f1=&`^ZZU{D|*nQBY$Jl(ST@RN0o*NveJiRUb%<-)9j<xzj`4
z<oyQj;w4!?>XGz0$#Fc%Fd-<zhTed5#?Sac7BDJKv^$|h3Q)MCt`zXO7(JP+p=)Jj
zrB%XP%U8?lqGe^f1E2IL4pU20(^b<|2j`W`>&ML%_aN~%iYe(|qh{nH)YJqD?UWX|
z$ps29sVaE~a*LGQL)P?X-=JO(VBt@Td(~9(GUP?$Jo(SOceHl|QLqTWL;xQGYL@zb
zn2Up9IF<y|BFZ89Kun0}N)g0d3p3&aBGSQ*qC3tq!jed(fI~^w&Qd`)r7qRMcFuFK
z8(EID>#(&HjX_v8k6*ny&!<)tCRj=0e`_QwoWdW^59d#HeJ}J4^lo2mE&++<V%tlr
zkTmX+Sm$iw`ANgbQ`=Lc2_OnwjLAqc7{WL6ggzjA&u*V><7{KQ8|HB-8^*S=FLYOV
zdQw)3w$l5gQ+zM9e`NQ>?y=n_WZbPJxlOor+54T3-_`q*kkj1lUivrN{`hmJ6WjFL
zn+rG6f1yi;+u#X(kyt7`bLLN?y{+U0;aP8-0<pZ`{7H;Sje+(LI+(?)i72W%%4qhK
zg+l-@Mv|YxU+NJRoAT*!nmy>16O?~lF9MhlJ1EJR_s9U$hG*ba025FiN3MVg-ur&J
zYJs(H6t!klFKC`-{MFBNeC;mN9bQAeNk3{HE}bz<HrjxGOIHCz#;oD`caGu{K;5*d
zh<*y~MV=N(fFg6FjTKT!LBPs6)wLo81KVbFvNghK$c;}Zm0E#%keW@dI+ekinr|(V
z6I5@KmfKr3IJP;nDVY3mOK_FU0q*<;7)YJV(Ehh!y<s)EFP_IGMdo<t-%`rs6r&W?
zl&PWht_@6!BFHRb2a7k1myOrlY-FTt)TU1_x>3+c4qZJ|H-s6&jeJaS%riYUo0q}!
zZ+?e7z45)1`VG05EpNT4-R1<plR5ez;4=o2a$858a?N|qi}x^@7s&u7dk7hsqh-;J
zLod$s>VUjlkX;@wbAt_Sx(VXt)O^$JOT|&16g<=C&=e+>`Lbko%1lF@;<~A_GIl08
z`I?ef=1`P!29b_aH5$q>U^QU%z71e4JylW$&`H;!Y;@B}tEn^F|00U0Whxc0#+#i@
zllJA=b(pFuBh)FZ9x+WHe$ywE2}lHFxNzw9O_@<v-&RXjbIdx5*v-1u#ieId3JWtC
znY$XfdQ386R%THL7C|4IUuX*uqt;DFpO3ucf0EXSGpq1@um)^aQFrig`rbMv6y2JU
z8?#sbOn<y*?_kfCHFNRlLbv&6S6Z*dy|z6ckq#<-Q`%=VD}C>a0bcK}P1V>=W+i{M
z?XB#org2<LU>HN0nalgyVnt)<i&dq@WqPQnO)#8kyg^#8^l>U9HUl=KikW=X*i0e;
zOu*jkjANh&up5{V0tE6pnGwdq8P0$>J1m(sj~d7t0!EAB(D2#jU-cWvP3J$eN=)uO
zXt)cIa*rT$4VVV2TeqnfhPk5m>V(TkVOQJE2C+4nBgPabaLHc}IK03n_!`hZWY9@@
zGkhi=?gS)7JhdW9bpmc$DcVM|f%{RLsW5-oa3gnP-NNKTnVz|wrJd$M*}~icu<?X0
z(1~<||8wC_XNVJ63J+aApdUA%(#-AVbTG9*-Pqdb1v^L6^ohc~*w3Ho2qt)aIJY^t
zT&P+&TCnzz7}Cz*AC2BjB8@fg4;!r6%<ttK9qeZtVjC?TDGd?H1Sbgy*texpuLID4
zUaONtG{>lJ%Czi}pWf0=ORdN5Nz-xDrN;1l;&g7$ibwPD)wk<ccxdW=%0A%~fp`J9
zK&spOL$#%ZmJn|i!zBA5ygt0asDXMk)28t8$>bY8Gi6^#MMUa$5m4F}dN*`4Yn7N}
zn7RC^;hmr35LxEgrGl~7anc4?NX4-Ip#A7!pJ9>!y#2kO`cnQ@*q?>ic2Pg`yMvp%
zn_H_4VpO^xa|zqM#hqg)<J`&1-1%db%_ymQ)z(d8s}nA?VMdwgy;WP-+&A|AV!^X`
z?rc%zINsntd*P014!e0R<0%`?LJH}cBRc4(B2Pvjn^c=30Id+Qb-i_)Q2hfN$GV>R
z2ZNbXxHUX|Bw}RPN^EOkXJKW}<-qa4h32ndug8qXkjD?0)j(N#;Wu-*dHN>GdluM}
zoDDkgejMvq-t7@l^(i>>0b7-Z{UgzZbSB#?mdY<93YYeu^}e^hTO8hegbg%cWd?&{
zYo>o#eZ{FS$twS9_xt9D(7%XZ=pXsd2Thz_Ymt-{>?Ocve$+nS#crAmug#)tz?mT=
z{Zh&1nv+%Wb(sMcnS%UL_4n)Vm>-V;73_jKA2mKwZ8DQ_G<=eU#p<y(<e-zEyZn;*
z$_sLQP8j}^;0xG-{Y}<T%yDl=Wk-<&8#FRrn&bni(CZW9p4Va6Y*^+bBL#1&>MF%N
zqc`&_A2+=FP~_ma659d&X<Iedf$4~BDE+znTA*wGwE(eQ$PVj*K?83aYD~Rh9s-^*
zY*?O3eb=4IboXUtY$)YtFZN4p71Btej2aY)0ecJlt)_eJAE?;J5NY}HMp;8s*4K1=
zPfcFgN*7D(NRQ-<=al5={7ho;1SxNBvCw52@)cSbjOFAM<Rs=y<q%7khEAF8%=q!l
zS%nFO@srqc&ZYiQMdlVg%#|g)#+IIe#=hrtO815;6Q#2XsXNzgd5>w2xsTNvXKU-)
zRL+ux-Oi|x1T{FZeXYt*R^BmgM&t{&3Klk0HncP}H54?IyW1VztoE#;SM$3E!@wjJ
zA8a@cbX(dQN*kKpDJu)z!H$MU4~wt>Q0U9?$hR4a!X0f$_agTOcjSe{QT{4hHzA{1
zNO_kw!50E80!?EMIZnq)QjUH$7S3Y!6dj)CJTW^RIm!MXvE7Uc@`=)O@(<U(+SF2P
z<idEY3nQgGe=!r0Nk55~<Wx)SJ|-|Wov|6!$I;rB*KX?9pB<aa*sJhDK{+X0J24(!
zgG|t4Z`6a;c4?LnK@)Zql=464qsNou*YfMeC&$aw%q=Y~HMh&g=f;8gC-S5T{7Us&
zb82%BA8v5a+)f=I8IQ<MQ>afoVBY6gRBx(3{j|L@Zj#R=uac0#BC6}z=3M67atcZL
zQoz9*f0^(zUT0u+U=O+t1wwxYY(P;^0MrHQG>A@m81R!gICN?J3T&XWJJq$&-NB}T
zrop;|v-o|OiQ#Npwf~NloCTM#8vhs9YMUaP1{>s_#B6>w8<cQEt+9MTo8}9R7LBGI
zhYF|L`XRfnVFq|g-$2hmN36!%)x*a_^76-V_lCkiQbPUgNK$>0TYLrE9@p|$YmQ}&
zwufce<;d~k#_h&6ed#Mad>RgM12JviChxo(z02<7LGG6W6^YHP@vnV;7Sk1V=;5my
zmC7ReN*uJ}wKTectY(^%T0_Oj;3{VB!kprq{B<j7>+aA{O=4?Sp@~Qho3a^2TS*RL
zT{c&ZQ?0$?8C}PBcQ)NCp(azOp@dT%q3XoutRr(n#G7nAHpRqi#M3s#3GszsD>j@2
z-+=cCz9ATS1*l$rE03t>pQSG;>N?sw20HpW>N;RxJ<Jzs0(IILAJ|A>V*@9pm+2|w
zN@+J53}3M|vo^EUYhpAGO7_;a@?o?fmV}pVQQFt6i^7p6ZxrG^3s(ysbo<)Ce+tSs
z2jUVW6FR-yz>zRq1CP)8aXX9e7j%mdEgByAFo}pRGg)5efFAP4Q#6`6OJEieB0pOh
zvcpJnRjVoSP9b`aK>xMOJgv{pK9Vf&;H8#yr%x(gW<D1S^DwHtdAZ8_zW<9A8DRf!
z621`M=r^uM%g@BHZm5|P6q9%AE;VQL`oY=DSu<pS+A@zdutrjrC4IboRuAPU{&BmD
zO3@|m3QfFcB0~SA-z~AW!Sl<fe|a@ELRF_F|CYW7d)WUY{u}m-i$VAhmR1pE@qYlS
zKvloyp#8<@qpF_-oo}H1*|52gucB==@<)uCXztOCUqYS;Ttk=+oeb_5;WqTB4ZMmW
zz^5Qr%kDxg`KaZ7j8X+gaxq$kHbW;vz5#g(_;=AlFX&W5{vg`Zi}s_G=G)+Xz?VQX
z6@6@g=G(CRHfr}l?WA-4O`fmoZ)zTcyaIC7P7dreav#B`gLf!SU=A!p0?dRw7ju-W
zc>uLLp~HNpya}a_Kyw)^W2}^|;E#h}2Yx?VJH#z<m7-KJ<Qt%q4V!A&)r4ul4EH$1
z0cQa7QECy|b3gDUL6n*`oq{O;gxf4N-)Lg=h#>qeqf){szYIyUhXjelymo?lM&bv-
z4?-s%I`QD|LD_qlcjXelQbQ|5o2!}6JnAZDiF}MDQZXctYiMMYd`%1Usst^05NJS4
z9@k!H9qo6SXUkG6+fnX=omP};h5kY42cwqfaWxoMgVC>bz<;Vb+!y(u=ut5Dh4?{e
z#zQ9_^6P8|^#-F}8J2$p%Q7qvX*N^6J({J=L$Vt!`3Y*-jq#a)wITFk0@j9Lt%K)6
zc@}fgfwCPa`zXr(j7LWEG^6x0zAE~%zKFRKeN_o-icdrTFz^vbd@*aM8AV_8@lTAz
za~}^gk`A}(Sw@mm+e8=8msgkQixw`z>^zG$EJBT&xeZb@w?S}0vI6y<13J*7Nc6~o
z9y!>W<bX8+Ywr$R6>wF+jMSm5pgBwY3yj2bDFLNy%*&5rEj@s>^eD=1(|n)mdX+tu
zv`v+;9Ze{#ZR5TZ&*QKScKS3wA^q3c<4Jwc?}L6D^!uRS2K_!BD@_~5t&hiw_(ABz
zLnj_`vY`1dE$p~nqgK7iE%cDk!Z%?*8mnalt0mek;ngB*f>4TWMq|eBL>sb!(cD^b
zlv^u*js3hhig6yr%x=WhPqF?@Y+3viS3ku_UVzT0ZXNO%${mbSH|FKH82N6rq#N}<
zhY>KM-foP55hKuz5inu|x-kMqj6gTm^K%%1Zr<s{6Ke8R31+PuqkRu*`~_;fhijC#
zvcw}?10E8LzsGm9KW1K)aE&BcPNlM7AqW<-(B=TFp9x3;R0(<!0{kv|5dcs1U99%^
zF#f$5rS~vO??KZOqx2qjcQ5v1tnvo&^BJXBSdP_xoiLSA-UrNqBvxAhNdb5}csqDK
zcs=;L!QT!3DU^MRd5p~K3au8+4;ZD_QJ0x{c_k!fNNN@KNG~u-wW<VdxQI4nf&V`E
zT5U3RO%L%=u<wAiVOVppj^bn#{{;D$7{xzfH2wrTDZoxu2R-U!Bwi0*5B_fOcZ25|
zzr;0)f5J*bkK{~PR(sT_{Dta`Vw4(H30h)7n_)+J6ywv$)|5xl{$jMhhG#*E!Ccg!
zYz@i=q3nE37V%@sZsySo9czkffI3xzzO04*R^Z)`=rC(17>Vau!`u<iv-V5$REJh=
zKu>ktHgO!NL)&su`yHq~7j?};z2_K(f2tDHxC1C*UHuMyk#O}iM(h<x{))1%K>iB!
z$I;GL;0eFSD87P|G!AQKJH|N<W3mvVlnFZvRS8CE8|*CPJ`&IUU5J)Hh#3jPj64Ya
z2ciEs@El4#h*IZJ>OmeE;_cw|;Pv3|27fpBdg4E1lpfT~BmQ5E(u1xO)Xoxatu_U1
z{xbUL0{<k|iF$Upcs%77Iew;6gE)hDHU2lo!G*DU5pDh_qxd39y$BsUbRKb!CtGd;
z&R54!*-8AXj8Z+uDiLE<kG|KV*EZmj=zBf-{v`TdkG?;NzSpDgPonSj=(`Plujd_2
z{8Qk09Nxq@)MK>6P-6&c41;Hz!MwH->tTi};d-?PHE$7r7kYFz*GQ5b#AAiXz3S>h
zuQ5mR@6qNs^bxZ|Jnz|Rb@xGM53atBeOiru`ib%_%*eNxhqX_%0!dnde_<3q(Tp<B
zNc>UoN5TIF{BOWdfS-VcY*@%<9;-Bz?Q1JgS187LmWF0cewHI@X%_0esw^Q%6{C1n
zm7oo)(1z2%G2m6rN!HX*E++25sA@4*f7kquc`mDYMjJ_dyygmxLlL7Ck9uXaVGW}s
z!+t-b63j?Z+)?HkiT@4w-+-S0KLP$E_!{Q1#ujLf5r3FbOh(K9p->JYA7K>#;bKqn
z57dGh#ecvWY!c6XIfB0YgWD-@Q(KGi*~;T1dgJ^`$JO(QC)2qW;Zw~kbhVQ+6yZ}<
z0{dssm+t|)fQNYQNT2)F&PY7>>j_5UxnGYl3WyMdPnF|rnNbqC78zqMiRg<F^={*O
zMWZT#{+Ke8dDOTSEqNckSb<)=kCAy_^Ls{&+xuLK_QFiGfp_uad{y|=V=jARMv_y0
zCl_m6bkzsDqm1WHGlqFA!<@#0KY%%n$2e!A4e{J-C6iH#$2yt7$e)GgyC`c#*+EFG
zsst7k;C--Tg`N9g$BGqlA4bxO6>=X&(hAG>VI-|sb)A?;t1?FXLyVHu^+&4fo7f9~
zM7`fckN&K-oJW${JWl!oXFc*?u`8Q#byVfCV$DFbQ{05B$8mKNMtBpheic_6(d#_y
z&An(_9(0<({}wAST9ZKh!wTipBF+mjTH8wcU5ui7Mm(j-#yH=LRxu7>d{R_YM;IfM
zf{}^G$fRIo;xRHQs4*U%VSrJ2g2zW3g|)qm(x;4?S5+Q!f%UA-(ySmI4f>^F`y^ri
za|&fwGK#0%`;H|q0sGLlK=+R0wgsZpGYVz>(iKMW8I*bkmhXb*Gg#+Wu)B}(j;59W
z4#^#^D1mcij$;?N*q=9h91u9GrCgqJK$ZkU@=sO5(K7MKvsf;rGE(-$ntdv=gfbD<
z@8j{&wqTUHakU#)jeJ#mKjZ<ZJpfk&kb{30F?j%M67Ph+t%nDG5Z?GbfwP8s___z-
zwcdjV8wC%az;emLNPE8?s}u-*h4nQHl>Jzr^_am2F`F!JXE}}SD8_aaUhYBgTuUtU
zW3_J~%DqeAn2_7{CrCO~31a3Sy5p|5(2}<hQ*qgcfe*5TqLI6p*BGeYw;Aa?#i@#`
zPx4jG8J3IZPzz!eIsps7zXhHx^m5jt@k8#Dk349T%45BK8CmTdO#t(dglc|CEgWT(
z-qX&avSnJ%b30M?EtLHTHoF<+a4x0HU|xh=ep%&V?PqL9`G}EDv0oAI%P5|L=3!`t
zVaE-ju0hmw5AuCIqZojUJ5uGbdb1$88<H${X3f2Lj#2Jp)Lv3~cXr&xtBz4lbmzan
z;_Q`C&gQmhi_z<B=>HJCD@9L#2uUfd{Q>osx{gr2@1p&0qy4I1O~v>;k5Z|SyaYR|
zAbCm6G&z&i7?FMV!<tEr;*g#F0@>L+$Y%qPDSN=CKP-5#ruG`2jGoB#JVGGp;a#ko
z3%{`ukw64S?*`|F${#U15AYt>EadY`$!D*teTQ{CUS%Ea&ta#Abv&wAN2`Np{u}b>
zy`1f8b8%m2FRV@Abgn}F_^f)zfJapmihC)4hFq)Wl{fAqn+op~-KX3m4+V8?R7SYX
z$`+n?SXj+F-NP68>_b>5pD;>hR}9afM-BW&4ZKhqwd6V@@u33Wa|?z4NrV4M10M=L
z6uyWhTNsIF&0hoiSVA__z=wioc{EFuJ0XvT{W~G=hQ1N<Zs;3f|6{C#Uuc7v$M}q(
zM^B*_So6|Tt~l-sR%xBqOqy3*Ioy8a-9JIz-G_T(uY(W3eZ}vp_Z78CR976M)a*JZ
z@I64zyxwJ$9*4w&`&6GozK2o#l;z^9I0t`%Q|}S=4(IjLgvB0-BtNG81@rJK#V(FZ
zThWI5(1upXTUGh>W8l5u`59$cI1CFzXzc`A+W`yD!a@hUcL(fr;9kTC?xJ+Kz6$ih
z>A=<;7_r&Vbf887ynt2r0xSz|IqA!|E2uq*yCsiujoJseM)^^c+J-i~iZ*OhB`CX%
z%PNc1J4+b(5$KdKFMSo7Uu8{k6j#5-SH)3y*HMobu%a@U*XhA`V9dEL6Ety}5PloT
z{pxmA0hzxC_mn(ve%*tSxrg=Tt!%*~9PQtV`+Hl_l4@8ELJPAndcVNv1)y!XcPhT;
z!8uM3qxc?be-AzVGGeMP0q<p$(!dAc-f|jNf>Ze`NxrUmmP(Cd-KIb@8qv$wasC#u
zL^}tiirkUsJ8Y9t3UkFHzWo<`KA~6&3kz9aEQM#gtj*^<Maw(oGHS_0*?8>h-!rdS
z3CZtO`)r4z!G{p1aSZkvqqy+;r;L16`T#nQAy$7F(fIQm+sLaGj&`1h4?M^I&|@>B
z<{Dy7f!jv04f!`|AD7b9vB%TSVu>aMc0NG#`!u4XP>$ua6&l`mU%t*~{p+~u>A}4)
zdmwUVzeh0x=YzjPDK%?*#$_TzL@hn5wt+pK$7ZziBu96YKYqYDqZ`#ci}`*xA~#`P
zS_8B)Qe7(Yj&6o#3M28n(<9ZG6FRDVkjF&+E=Fe1mB&}n{!Fz0LCuHAB0psQI?tUC
z^GYEk$UelMvZtcfo<w|g5-nkVkdb1c-yr_stZIx$m@*p1eptiIQl7%|yAqOz-LuJa
zQN!7*<~Zj{GVX54cOg@#L#A*SX5=bz{|}M-UxiQGg!Vjxd}<rAum`c~7Ng!zu5(P4
z>f-wtv#=Mm*iBlMhaU^We)LxT7`)H|k80vSVN{R>OOL{4JZEP#VqfN6$w=!~MK45;
zT=sp8q$hUY`&<iUb9@K*2}S|lKrX}S+=QsU3}^8e$J=t58ew8Q4<G`MXMN>ftffCA
zM{dTLkAnXue9I<Cjzh8u^={Js2pNzM_;K*O2cxxHdCYO*JO<5$u<$VY9uMynj$Vu+
zrVT(|^C?>RD%zv^v{Pu|O4N7?_d~{jFF|L_z2@tIZ2zm;|DvnGjFi!2BY$}w(Q-Cc
z3-c8o>;ZnO<rv@*O)ANE;SLq<Ye_~(3L!B<5~%qS+5AW;VP4IB_*Y%|+sf~lht8v#
znS26j)-eysU9j_I*!eN|tGFBXF{Ai8OXMb8y<byFSHGtmWFGe4V2QkoCE^>9^g{mu
zlvRI`ImI<<DpBK7cRTqMUe5PLMKkV>Myfn4tmLcGI3)X^FG0VAC2}?M+6Po#y_1Qn
z+hFHy_3kCwd5&8p`!cV&uJX{o2Yoz+9{J&p;zE@5L)7{T+W!RFe-WBd(6pdz3-3+k
zqVhcR>b*ft9_JcLAK_fI`5iT0#ofhh;8xsiTaQtF3YJF@<CXHAH=PxC_7+2O7!ur(
z)8h9*<)_?2%@1*h@Bv8v#lH$^K0>65Uyd~IV@yu5js{V*b~R$xZy{1ue>vTSdwscl
zXHxS6+^feOX{il&2p?7NKZ7q)@9x5HKMu_<^$y_;j)Y6O{W>e|)(&x8r`v-VH3xSr
zH{c#-9W2l0U(A)4m6x%DW{{ob?%zZf3jBKq<8R!*BP>Mr$G^=TcHetv{t4iNjMNfB
z(FM)_hP)o~Cn0|gvzE;$zJ^hH7<Ju?Hf%u~?sfkrn~DsJHD8A$7I!}9<2Qu|@%us;
z?t<bDHf4zTjYe}9$872^K8Po4`MC&Xk;a#Kc->bt<o6T@OT<?o`7u^q4R%Kf#w7Oo
zc|tR4T!|XZ@NZ`LUI*mEkUJo+g6H`M@K1>A9>CQ`wCz!}tp;t5fxHH#YH+9bVce0f
zag_ksf(||{3OaUpp;zFMUcoGX4Zmo-;+At=xNoeD!+q2^u0^w*Ymw7nVIk_xM7;}D
z33~A$V#pBno;-T=By`eY`9+pU|HKHth}vJ&(z!2xU(5GiUi4@Me;KXfvP~#k4?kRw
z_Rj}~A(#Ii?!bp3N}R#^+Df$WF0@C2g;!uf!k84|7o2mD_d@e4>e@z2UdPGuFuXy9
zIu5v7{wi<=-@Vr!)Oy3hQ&=0`SU=yvdj1Zdt%&`+fhjoCt>70hQVhm-vsWl{i9f6i
z6aSjZyDsC5<4EHM;)-;{Z~s6nC&PjT2y5aCh#8(zc|-+ILh=>V7!J*Pm4`2~BL)}*
z+Og)-G*7_ivxN(MuT_b~)eDHqE-4R?BwKltd3Q{E96dUYGm+v|F&nXs8sXrcfS3&n
z**EwOp$B;6<Ko}I{|M270TIZLAU_UC1SH2Hku)C@t_Di@jX=k7vhs*>ku(o+Y$lhn
zHSK+j6dU9Nxkp+2>!)%Deglm|-|@?rT#5MkJjSOIeR&I#!^$_9hhzYe|67RR2hh7W
z(9@UE@@Dr*$E|%Ccn9QvMSRr^%VtJljB{8q))h-Q8*O+WBRm_mtO5TqqRoAbN;qQ9
zO|WA_T>1mVw6DR!J&?Qv$$6FtuOX)G0s25^17g}@NDLe?Qv6RRzVsVL@oBVtA!6D&
zn8672YmRzyp$!KZr6^pj!qq608pR0z782a~*SrNuA0qkF(AQ!dPDB5Ki`(!F=4d7Q
z^^D8FnHPGYK7aBETI)n>Usa<8?1EK{VlS6f-p0MJYYJsIia$SXB_cPWRs9G_W@Fau
z$|-7(M$=9FCiTt|+Eaq|`~tDxW~|IwjLG}>eS9Ay#h*M!ThNzBWj^t@z`|DSh*9jg
zbk5o|*}N0Af98BdLB^#0BluBnr^bq_9W2pUZ_uuhpFwQ!ca9BY+(V}G2stT6;7>eX
z@&~M=c?3Ei@UB-L=Bt|bG|QQX&cj%ZFCfBy7<Rq_$veo5zT&<E$@fVX<Ng?aI}`tf
zdo0&*x9wl<yKP+i0=7)iKCNoS&&~6C@W%-JnD@Tqk6I#m)--FeJ|iIs<rS;F6D!#d
z^0%>C{7~cD${CUjF^X@a#th{TRErm*lmVUHDD@E5!){3a$@Nmq&v#{Wu)1n6YdN_3
zA?7g>k`E#I9@;qrGo{`kJdJj~ftH+h=jmMP>#*j8qz*oC53d&akU}T5G(*|L(G)-9
zC*c=WsZ!x5Qo7~8G7rf{=)40R+$WU3i4ph<cJ3MU<rMmI1~JBcs)v^YnP;TlvCfCk
zQGeh66p}w-uf;;X6Ox~(JnF4L`{C213P^I54w9^6ls;tC3M!AQcW7Rqt6LeRJ6s%n
zDX>rr3%GwMW2b8$#^^=3BhsTdHMrhg%Iol2uQQLUo6wg_=;<~1w0Yn=P^uQC@YET3
zFt+)wI@;*hY|O<;c!?iDeiH4x7gytP^<IovEd1vhM6D^jgTx~m_5k>eLtKwt_BX72
z%(b!)zhu1(9>34h3gN3e!9Rtbu7Cs?u{ePiKF+^h$$|XqmHY~R)A@s%4Ji+E_Nx4i
zdHByR-0`+Eie2s%$QjLH^!G#T$FFNMsa4P5&f#<Dmmk*W3h>`nxNWo0>u*ES1W73*
zO_0n|e~)(mF3i3z8T<@*hGXcv7VQ~@{1o(eXm~eWheyhWe2{&hbd^^%#Q=}s+-LrI
z{66~{bYA1<Lgg=^{g4O-!9utMZ~FBRFNq(E*Tfr=$(U~};(y0N+Rp!$g0x$DUV4S!
zGAq3){YiRD8kB~lccgdu-LcXK{9agDlx0~XYh?q!-Id?xD%<$qJCF<IV!4#^_g@=+
zhJP2RnP@4|ayPA<;;lj>U0q7tN@2CIR#-1|3Ejdrp-0#y^a=ZfgTfJEKsYH33B$su
za6z~vToEQjNz{o(F+dCxqeQEiEIPzIlJZlo>XX`D?x(O-Tqf`@a{Rl;N9u1ZxFh%z
zc*>u6@b7i_WrHFtmZWRnr_ss)pMZGqm$*6$zbC|UUZrNh;_HZ}=O8zoqy3uT&N4;h
zUgG<ZsQgD7&UGsJD*0(H`-%Ewfr|Jo)Cu0HxgofJZKkyeghc&~cRSWKN{KG@*I-7P
zPd}2-h!8J&HWRK86v3CIA%dC4I6+7j(gdeaC=?5o!VKXK;p@WP!dzjVut-=eJR~d=
zzALl|j|%@q<NuWK4Bqv;L-;k#!Aru+!Yjh>g~P%z;S|lnUxl}YzYG5@ToyhOt_q(B
zE}9EjR78!a6+J|~=q>t)CXxRIl1Q4HXfal_iL?1%XA<X$-xTMI3&ck8ez95nmiQg9
zRs5c~QhZcw7atQ>i5=n^@k#Of;yQ7?xLJHb>=$1Y_lo<(gW{{=5%G2L58@l*fcDoq
zEC0!j&aO+<W#}BbES*zVtSjU9Q|jjH?$s^ir{n4WD`+6JqCxZ%L#QorqFqcEbHqZz
za<N*h5$lNNQhOSyEp~CKxSU$DT3kzYcZuENHnB(CCHA5ABZLFuNpXm-4T;0zsCa>P
z%oTA$k|dpElmb5Y36r8EtCTD`rapO6u~aF|oc5V5)k_W10%<Yne)d@+EhB7`+NBO@
zowQ-<vq{=Q`*9~eyUAWZ$)cqF#2u235_g>T<xKiMEsaR$q;~4OL*ieG*J}7~Se9}>
z`%>lSgvXedPAHsB>|vBIEBvI;AZrTe7{$dXRn4e5z^G_}sS4kPtA@2&*y-UjT`q>5
z3D(ipp=_;MFQarCSgC}ukCNf3<RQA+2)-5aIgE0P%s#)7dEq3Zn2f8Z88rdWSq<!!
ze?Ta~LZu?2FD!2Z!kVT_tr0j3YzOX<Tlg1JM%m6NZ3G{s;U`H(nHR_TiFayeFUbuo
z5su0fn+azarTr`yj<UX{3T1<US+KlSwZ=M<PUbrdesVuY!tyrA*}@oKr8clm4{!`}
zEAT2><pj2KDQS+owS4zaVN`|~<yv4b+GY@f1W6L4R6!C%V~24)`PTpU7Q+86Zz1#&
zMAI@sFtri26Lk>L$!^*}-<ycG5N#*gNwVFFuW5~`)3otF5bJC<Z8hyM^_upW_L>gd
zL@YaOI%YaSbjoxFbk=m<H1;2eb;eECd<9>vuVEVTfBX4{_*#hKeC@vJzB#^y|AAPi
z+_&1d#<$LQF4277Mo_cwQs3o7D}7gkU+cTxx68NNcbjjI?=Igy-+j}F|NEft5#Isd
zlfFa$frfoYVdH}DCD0Y$2|vkC=Vx>i^8tQgeo@ni|J&-9?B^h|x+%}E*st<7i1lXr
z&GxJJYw%le6D{^z;<wDN&9D6?>hN3Vw_zG>^4oG-wB2u~-)_Htzx{rPZb?V|j)MmM
zPJ>4L&fOMW^t<eL)z9_s$Y1f-`<wiOZi~$RG5$9HR8W?`6IAM71)Akwi|;x9^ZXb2
zH~F{txB9Q}U-boA<KOAO(SP%Qq^<rt{CoZP`0w>U06Oe{%>RV{sn5|F|Fd79^ZsL>
zqjCRhw@U#+fHuGo;P(Xz39tmj1=w$<o5wmJJs{_{s4$>BpgN!?pe|tUEs3wq4`>W%
z4p<6)dBDosqSXOwZ?$${V?9w<KzG2lfS%i;T>*Uo`vMM5(UE|GDdOuViG~7(!H))9
z2)Gn*C14^@LR~jepf1pe?|{It|431R*1+UI$LGrD1r~pfDg$SJfo2ER2Q~yQ2wWVv
zByd?^8@}5EJ8spUe@B7q0yhM13f%Gq+8($waCcz;7ifRrq0iCLz~fWCeVQ+x@|A8M
z7dRMrdeR34js%{Y?nkE9$n<%2&&kvnT@1WD)#j^#uIX)JUlOE{KcV#)q*vEv(B%H5
zeH9c$WDbhq^&Vs+N)5`IT+cyH`lfn<N`tC`W(Cy-%?X+pv?!=4s3oYC&zGPTL91BK
zed9ACXiZQjpCv&XgEj|k4cZaZ8?+~AZ_t6D!$HS_P6VBTZ>K&7oe4S{bUtW|{d3TG
z(6wM8SQ~5z_G4enKAp!RI3(D@zB4#37<PlxgL8rlgUf@fgKL88g69U$4{i)@4qh6(
zJa{FKFUFL{lE*N3wP|bc+Titkjs<to`Qskv;O=01@V4L{wt;KAg8PE^1s~*dXX>1t
zK1XhwuseCCxX%J^7oUy6M}h}}PX-SK4+oD<&NK9B?s)ElF9cr-z7jkUB8BKej3EIm
z3kjn$e21I(ygqyromJ1}kSIEr`7Gu$c=9ava}%u}^zG&|wppbRt8Whz&d14f)lDJE
zzL%J$&Pb-ovvK-aIsJ^BJSW{0;-GVo&q6-?=sXO`^IO7%b<5{mhe{#EA(gx?LuQ7|
z4yg}m0KXt)ambR8WmvQ1KSJ6<+Cw@**5TTQkWKjB60$vHXUJ~ew;}x@`*}a1Uxz}D
zh8zzW3^^S#f_>rM2UC8Ld}+wJkc;f+LM{gkOzx48t06A-TU>t12j0B5Zr)dJ|1!C^
zV1xW-s1no~st+}B8z;*{pY~g5P^dXHCe#+18k!aA3@r_<3Z2F6hEJkCgw}@637r?Z
z2<85h4|2CFv`O{jQ}XrGblh#`zJ9?UPx@~5!;|#yeBHnCr=czG?^g1ki$9|;_{r(M
zlKtbPkDTTYSr>L#hpzD$gsuo&5V|UK4bO3CXXr-mXXxh8t)V+Ydqekx?qxaqtk46Y
zheMBro<RIU>yC9pPlcXAj6rcn=-JToh$qOWg^q=ev(98p5PB_42-Aic`1}v^3kzXi
z7iI~IW4mGYuyiKgqhUE=g<<7k)nPSZb?k@3=7!A=YYb~<AIknRY-!kXlwBFNdMaMx
zn8zKXz?RzvUkh6swmz&Ytee|471z0A1OI707&IBfxML5t1smJKdct;v^`V@*JnJLg
z;Qyxa!WeMh_JtjUjN`^hnv4^t({03pXxn5=H$ASKB#!4M>E@VjGDf>aY!-GzrT-M0
zA@-Uce{sy^j=Me=XK`DpEOgvsGP$?H2EtC_dnjx;Y&7fw)+@(6?tK+@DeOwvM7YEh
zt_wGY2ZV=(M}=F%lfxb1dEv#N%J7-tv%~ABulMkV@CBg7;Y)abO?&J0hVV_{TW+=A
zI6nyAjyGWQ`>*-!*T*OKTlir3=_#Jyf<5^rY$D!!lW)Yvx5*qdxd+W=a}3^yon>}T
z?LXRA{1$9(55F6meHOoWkI$Y-;+WF?R_s>pGv0~4#@xxii~R?`7n{$NNqxK_d)m9P
zc|E${kIiq#=67RX<G6s|jLmj<{M>KIwy;0u`JZ}Ew)<V#Jmx%h5!Dej5p{S|Hoqr(
zDf{k-<q<2PzZ!4K?&7y(a}3CD%AWMi{Ko9bbIJYY?30|2@Vm1)r-&Gx{`PE(k;l;z
zU<u=VgwJlgLz`^ydjff$`3>5<ucqFj&2P{C?2XwSe7@t_I?D#$bIfzQ@z!j9XZCJO
zKev7IZP`5MlW)xCe!1V8?cz6Ovrm}vx#TA!O_4!-R!+V%o8OPk{%-Oe*}Qgnyzsv4
zIg#^tJ@Z<KT%^7)o5zuFvEFdvO(YqN+ItxJO%f#8jjJJ$`~i}W!QT)5X<U6y5S71b
zw==r<7u3IcH1qRrEYW5`vI19EfG-4JsPe3-@nVU_izON_NFpGKV2S+S%*+3+@_be9
zg`^kyq0kIfd6YFkVt~W|Nd+VoERkZEmts_&uPT2)d;S2)4qV-#^0+!5SLdVl1*ms{
z%A+OURuPg`Tx~_aR-)8O=Cv-2gA47MftJird9*DWl4wZo2Y<iH<LXjKmcnK^Y?kBd
z_aOfs<c~rAn98F)N70g_Xw^|ju0V1Hk}I&B4-5IQmXDsk3_CBg#G{mXk5ZM#)y25F
z7`52I+f*L*--7+OVE--Xe+fEYg8d(&t{*}_5Ar-{zJXG2K>ifuPl3lQD3}EqWo49=
z=YXFBoo?uKgMStLtC%$tX3zxrw;=x(<QQ8CW2<N&*FZi2`2_5H!@f6otRfk!NC|{~
zAZD`~vsn%K>yW<={u%JkfIkiXH26{QqbQq-vZ=6t9rmw7XBaxe;N!u^LkI1b(SG?6
z@Q*+T>tDh8SF*up!~R;>UkkYcxq`BPMA<)r{|Nj?(9eW^CiL%s{vFV{8#;GGegyI(
z;C}%A2jD%xdteOLU<}u&b};+*;_AID5&y-!_%B?QA(v4KyI#Vsm;Ztq|Dx)%1?eGN
zeF&On@MdVjvJA`GRcQYzSiT0!*TCNi{!Z|7!Ow;M0q7rq%^}zvg3S!r%z%Ci^jo0g
z3msqZ7zYXCAe~1G&x1b&`6<|eCz0VvG}v((b;msi`E%fpfj<Tw>p@o61J<F8b*QzV
zofh!H;DcckYg>c0twC80$|_&N9{eF%Wy1KM#vcDZbiS{y8Az}~G;7sW0SWe$M%`2J
zHj3(PegytU;IU2=b)EbT_Wy=9z%y%9&-@|U{~_cL!7}Df*@v?GFjkEit48qfCz9$<
z7C~nbybb2s19PoyLf@NU6Jw&mn8<IUt~bFS0)Gg08epdZ{C(i>gU<WVc^`5k<VNOo
z!`x0C_MHy?PzQggO+>wksP{qC`yko|J07s(F&q4B=x3q7D5XIuWj<!)eb|2umS01u
z0F(-V&N;N?9BPS0*;vTY5(O=hFQVlaA+LhG3i8Jxe;jf><a)@lBV=_)tWeKNoW(B8
zTDj`yReuiLfU+B)|4s1Ugq?oa>4zMrr-IW{y96V%1T%<pN5Z)y!^_F=a+)X5mnR^1
zLhgkAKcW9m*u*R=m}QUeVobgZxdgd{y6RC^J><(EU#9vB^y^o!{3~@$;%cOdsB1gw
z+K#K(SqgTRgq0&<<!FBj`#%N$Ecj=kgA-p;Pkfw8@>8mpL%kW;Wk-O%7(?uI1v_0y
z0-ppP>p@Z11MDlXuel53a~I?%AwP+_x=>da>ROIAEJxecqiyTKBYM#ydXd|p-v%Dh
zm#ju#@51K0kbeUCC*ZO7W$b+&{ICvwScel<hZ9!wTeR)Bs0(AI#aMY@w|c0%btmla
zgg$nh20KoRvRaf?wnAqs_}_#7J$Nm6E!qRGBEzf5-@-`F!qr)jEX37?;BmglIA1hz
zs4)(5_y-yOLBXgh>Zs;|&&5c74I}wA$mc;m5ByB<Ght^Cb_T(ZfFD8G2T=9_@X(i3
z{RHSFfJZzdBc73P=1Mqom0!dDufcyA{Fl*w#3~xZDw<z{|0VcM;5WezW>dm!N*GBA
zBPm}%T^E=a$Cww#paah!!81r$X%beN@;vH&9z4z<1!s^_2EGh7`(U#V{GY-98T>Br
zyU?~2v@Helk0JjUcIsfK4*Wgf?|}{?d>IkG7WTEUuSLwGMa<*z4Xmhdz&=*B2CG_w
z_G{37E#hr0;%#Ld_Q%2F99M9T%O9Yw4<N_9D3}+`!?5!(bP(Cfh-?+uRMZ$AJ6*<3
zm*D3m_<8v(<YysATp=N@(7XVfFThR@?DT-g&QjF4>q+oWLLYIm263|d5^TN%9{x(k
z87gCa%If;;K-mtI{X5G39db{|JuxN)7?T2&g*TSrjb-da89PzNSjp;GeFtT~1Do)Q
z8r3Vl1Nl49$Nb8eUk}7x9yq%-wa~AH{(k81hd$168RxiM1ilD7Vka4~llC`g=Wj5E
z%^1UG@bJ14ysm<ARxr*A_Mn12s9^0WSbGx2SyIOt`%zK%Bk~Ig`GpqIqZZMljJjmh
zr65L9)c6X0k=4HJg?uk~_z*?)A&B=BHQqxuC#l&S@+n2lrw~)gh^f>kwS;lu8b7J!
zy_4`;|KUlkS;C#dU7vei>wck0Xuj>Iw%!m1gyWxkcI&+Gp78$Xp5RiZp4y6<dS2_B
zUwBUIu`fKI_0rVSSp&*i<@?Gr$|hy6@{;nJazr_=yr+DuT;XhAI7huaCtRdDuTp)A
zsHfV3M6(z}XcJS#EcGK?1Ubc0vC93KCDw{_#ChT(u}N&9maGt0iEG48aU->1tGGk#
z759jH#RKk73+S+TOg!QKoD$E7XT|g4m^dz8lLSdC86-dALL`e6C)tThmvW>+sa&d_
z`Up~uR42`q=1Yz4PqVaCT26W^(N1a?^yms|rFy8BZ_2X3e?!cFf3roS5%{U10K!dp
z#!6y|^d97$ELXIwNhu{s#LbX5FltURDyfiM##5!^u+sv09G8;MGp}6=okn0a?2p0P
z_-D^mNo)Cyp0a_Tu9CJu^0@oiDE{jxJW(ZljOVRpe)i0iaBbRCSG~YS`7)kA<iE&2
z0m(L1{@L?ZvIGlbK=s+K9=Q|qFQ5&bc&3S;tE$8ER!8vkQx^Cv`9-z>{TnP7{oPMs
z@$**i;(03vEL>%jYf-imPe?ggBKj-cJPs%oglDX5(Aff<13T*OYZLe>IZ;aDXXR-3
z`O(fxpk3#{uH!v7xzn122WWRaMLTN;?W*Uot9VaM?xgpG3$%Mov~Ol($IQo$X~B+}
z+$S%Jdoc#hWdE}#UBCFOYv1Rdcm3iMuhM5vy`ubTF$!oElL`5s1b6U95M3=d_>Drd
zZ}8K``)}~mesg#Rq!Y}OHuH0FwG#X*;D?~Of_c#e3szkHJxX1J&X1uJ2l+1`&jD}8
zRW11c1O5qUI$`av(7b@F%fX)l@29p6lC!RDkZ{>_-~z~9tm%HfbwZLbZz=!p*|z^R
z&$iLd(b*MWo&5`+bX|_FP*<+2c7JN<zv}Rr`-RVZU8Anq{aLD8PM?+hFVx@kS*=^k
z|HeH3+wyLk-N0@9@5#GAyGZAYpFZ6_Dt}OS#Qhm?e@+62h=y<R8P#3TU7GrI>8?zD
zChc~8;WObWdFnikQ=b6OF!v|w3m>a)pJ%fB<M7O*PcgOgrjKW(=S<Jpp7ov$^jUz<
zV$UUn%RGyxK5d@uH-Bhca;S6%wPBt6v%&q@<hg}Di;0Z4_-yyw>A8FA)8N@Z`O#Io
zZSVIybkpak=W!}IIQ2R0IfBp5TlD&z=S9!UQy<n^=Xv#}kIVC_UeT-nGtnnVmFvy=
z7($!dI(_u1`YgTk7N1gmm424K7VBlbehzv}AN@T2BF_$elfFgYs$cP$ooN<Vd2aY@
zJ?YozJM|mgpUv*iR$kxw9ay=I`d<AWUJLrYyk_(Vczx&(dmhpsLvOF@Pv}pfMW<l>
z4B6}Cm7+h(*LC~!=k;Ses`_yref>2aX)nP`>t*or^9u2@=nB2!JV(6jx?!($uN+;o
zSD{zASGBIotA^UQ)~n8IuGf68Mz3bCrC!UuR(h@WqPBRg_v-TM_S)vv<F(7H&ugF8
zL27X$wQ|_&2=-W)*MQeauOY8tuO6~E>UDu^@t#GGpt%<NgnHz4Nw?hVir0ie(%B6<
zl3yXca@tD+1|xBWh5$ntVU)pYNH#bOd4^)_<>l(fP-&RSy*11>)EgQM3k-{CxALdQ
zu*9&;(1tZmH5uB;UI*_+!#bi3hE0YohV6!(hTXaghJM{8!+z{8+IfaUhNJG4I%qg<
z7&M$VjOa~<bGl~3MNdgz<+;Uh*>IIcd9%Ugt$6FbO|)LG>Ybh=-a+1G?-<X^dXu+}
zKB;=WcNSLQe)?dpSWoZd6~lAo&1FixtGs7<?)R>xE1lkRyytl@@^12O@f`GSHAvno
zyjOXz@icmOdT&ID&E8wRchIL7YkY*(0896H@AW=FwI239=6!-br@YVTZTz8YXT8sR
zkI`DK(yjL%_rB)2#VGJPHEN9pqn|OvXfeha?Z$M^4aOW@kFk)}Bd^HK#&Tn|u}0rQ
zE40&dzp;+i$raszzJ+#Nm~k$xL#O8w<9uVIXR@)GcKia*2IErl6Ya+3UggG>w8o6O
zE5_C2N0#uuHm)_U_v|-z8M}?!ymskJjXgBh`>@v~c&7&AF8Zux4bNoVC1W3XDw+><
z1-mub!_cf4*Lvm|_j&F#9@KRikC42d^o-PkEye-jbjFj$A!_5WanyLhc*%IhH~}x1
z=OeKP^wIekJsW%ij6*(Q_(YMPTc-LtLzs^h>xEXZaoBT%PcnNm!Y$Br_~iK%`&8;K
z7*D!A7yGVu{aO84(%wQ6YKeE1&rF}$^r`o0@LAwF;<MOi34InDTn3lVGM_f~NxE{M
zcCR6y4!XL|XM^FK&nC~SK3jaY`|R}Dt+)B~`|PJHhkTBbt>Zp}KBsxd`i%IT^SP*7
zZ@B7n+2^W{%cPj}J{L_UQ;^AQiZR(tsrn#O7Ln6bYN|5LGS!;qc&#<fGcD2`G^Ki1
z>4r^BCX>%@&nUx1Txl`2npWtVO{+|6yiHzOei}`;cKQ?Fo>8U)^iiMjK4m)Nxd6|J
z*}Te4WBk;e>8$R8`zdZbE9SZ6v*)%=Hs5mHfM<g~hM&$RtfRGRB3eN+e?;HuJC}T8
zzwXLsPm+06dv5Vv>Dlf(->}Sg_4FsU^;N#zrd96ewi~BCtIbbiPd$b0O&OT0mZMf>
z7DtTAEY~k71DLDEy#l|9>?-)vz<c?sbcE%y53-YFmWVOnTVNqo;I~~Mrd1*t#Tl$4
z+rcZ)JO+Nf>!*~BDFX5{$bahUCkY~LF$59`IE>nLkneTzUv%t(O#`mhqE$7_Q^qGu
zM&R<Gi*grbHzYmi%O3FQESEMy(xdj&h3p5VdMV$aEDd}=YMjZfqPqC6#LgkEK7*@`
zDBB91d5FW;q78EeWU;Q7F@}8A2>mwjh~dTUY*QRiGd$+iTtgYc)p1o0J3&A@_fa`3
zaF(17o!8N-2DNvtA5G;H3%FjYku%yDb-wuh&caC-|D{khELZbYVJAw3Ft6!C?SahG
zXz*Xuw4*P}QI{w8PBgln#(gj1g+7#Bk8um<R;d|>cnFxmGb?UZd+oyC@VIB3?Q~$Q
znjvvuF08JDXf3}lX%F+#e(+YH4w%kJZP*X~Agn!$zwqS0MGwI{{o8@f>ievLIcVW(
zo;zs^MsL5s?=AWSV>PC(AIL|6M=-xzQK}a$908UxYOy9Yiy(2azC3(`|60*}gWsy~
z5o|WAwWz&DK6urg6>6q3#I-;VMqL({^1v!m)&R?SrnEVHRr42aiDveVYghx%1ACG2
zaoKRSJ<QYS@z{QR<2`|Y?b(P-5Vd1G%~)?8XkjHJtr)Ad7~3B3PFFFHlB*FqjkvlR
zeOb-+uYUl^d5kSvFaRrAA|>K|A9)z(F-VTM+At&hH@X)vUn9`h0pnfo5^C_4lWwf!
z0N2k^R}0oK|H}teXsv)2M!5K|OB-)|$`;Va-RQL^uSszx_DCZ}V1(-x_o}Orb+lNM
z)USiM1InWp2ak7F^=#OuYf*NbuWEO(eQ}T_<PTerYx79@p=>&Ks~^ji`MBzI;jiPk
zZSq}M+jDrPglpV)8jW6z|DDj}zSOw>0(=)W+Of{r&LgfLqAZX0QXUP$=TLSSWzS>%
z^DYSE(V#VtzvaW#Z@4}N&wq)hV6+cGXBYIhtB5h#jD7J8u09P5`RLJ;s4HK6BOzOm
zF~8y-=)Va23(;ns+b^;IbYj08U>zANS+f)V!~vZ){LOYN##X(LVa965{S%MV?(>3o
zmeK8p`_Zps@ZLO<8&Uf><TKsgTV1Pz=r7|u=p1xy7Wln3Em)sCo?nH98tC+(4T~YM
zLVv)GEtvfljMyOjNeg^PKYY<Pw4eWy@atH6J&fXdtcL-imfCNEk5%sor9<A%C>(_s
z^>cN?XFkmy1}9f3{J<gD*$(~`Z~*#aT%%?y(18^jhLdhS>(d(Jm9IrDr`_Z8OU(F2
zoQ%JOH{+JffluyWiGY9aL^uQNLr-_X&s(wYI-$Q`ErnVZp*<HcgT-#|U5N4FT3*3O
zu2*{jJ35xr>Cf|i4PL8?>(y=$?AXz-QJY^A$hXK7sAUx1tOffk4)%MwUfR*0Vpsa`
zZiOdl1#ZN;9l(A!Vs|L;z4M@d1wOnJEjf*|do}-kKDC+oO?1Zcxy+*xf*mTceYpYS
zzZa#(get^8x$xNhMh_<}cSC0!<M05=u6DN{Ye4lX?lYJF&5w5J4e&INnxhz>9Q1C`
z^(IcMV_0b~qwo9{vpPo2CHxyU{jjhRd$}2sVvO4wwnkp-d5jg$?|EP+*3t^dP4F=7
zSP5;+3;#m2a2%2qSOb%P>FURS>FRyR`!(VJ{iW;wp1Xk*b(`i0qG=v|FQV@z#g}uO
z+oC3-7NXXFLo3|0%1vu-lRAku-hwu}X)Do=+oWEiJ#O0TrUPy|?EXGRbb{y<(V1J&
zS)%i|L1S(k<8HcUTI4I-MA}=B;U@C?A5aL9<rWl2WWNQa-$XgLNrgn^MAiR>YTQ)k
zrn$FC^NAY&Kd6~#>21<-qLpr1?WVPETJQeuBI+jEM$~f)+C|iN8?=w;Akh&w4G^8Y
ziH2@L!#C0B|9~zKUAhHbA)2@a-89yI(ruEC$Ve3MZ-}pj5k<Lq>upl9>6U8;Hkcel
zdACW$M3qc_Gx0rp8cpidyT2QV77#6-R@Zb|;{INC8`MVBepC65n`qrFXamtEqAf(*
z-QPR^O?&<w?I!BK1??v~bPGCq6CI!CyQllxNnh#qV}66CDgWYk+Vna9F||gf&+FuP
zPma;Zv^Jmne4D2H$@H~3xqsbz%kSc6Yu@kj=hrmqxk}_RE%H~0^h750eDM!b<>(Wg
z5&mZNEb)&avJs^cWf3`vO5MJl`s-gsG|L44>|aYXhls|AeKGrV9tZzLCiqMLCe^M#
zoqPUt#`)9v=FfFgo&H?cM)&x-$CJzQIqARIeTMD*Y@A_ht7?O<`BNGHUU$20o~N7U
zXzDz1&lB6?v(cZ<Ie)6d|G>2J=heC6|MsUd&!5gae>(5{Pq}qkrqPO9(9P%a=3CH?
zY3J+oGj@_rO{1I7SND1O|LdF#F@63lj5B?922MNg{LiTC(x1+B|MPC1=GcGSy<W+G
z_|v%^AgKQxpml#!eF1*zz6}Ub_Y?Okfa(gMdIBc*#^gSj^o!(61Jd1oZuVz;<o~kw
zK5$Z1b^rLe|7MnDcIM8^y|XhL5*ZN^@*of*ArcZ15+NcY5^hL{h%2s0gosE)#zTaN
z$YX>ANQ6X0M7Sa%5g{2F5fKmZAYU@#Aw)t#VrPEu&->h2W|u`U)F=Eo_x1jq&;6YL
z=bnFa&;6X^p$$mCCH`yrz`AX#ZoA6&FG1U47*SpSy-qrfHU3BI_U2*C_7J{@vDw48
z><!fEW}k#Sco=`ZVS&GM^*?p`@p|3l(_CMFoX7A2oGq?%^{4adpl&}|*jKJ~Pxq09
z{b4llyE?FwGC&{gjnvQBtJL}QFt6}1r|>3gx%62c<`SOFDav)d6StnsEo6=%?qrU!
zME7Ujf}m~&a{>=?Pv#jI|GibZpYy7MaMx={8}%@+@G!6N;7|HtPyFr)`cH{3=p#Lu
z7v$$llTY`f3@Zpj>^#gByyHQ->h{BR`rw*5Og@hFK^W+ReKYWr_rEIWpWEy5Vi_Qv
zeo-LnT7cg5;C$wSmG0>|UE#bgj|By&JEzOf(Jo|ecF?Uo|2poTo_7_FWy1o$M^2YX
zzHRwI{q!-1^2^-QbDp4G`It}n%>tl}`LOfRUVO}T{B8ky0)1-NcfWstLArhUnCtjx
zTR!GB{^<JKoAix7<}yC!GCtavKkamT^Jf<Da{|oMkhbSz{^BnU%oV5GppSOsqn-I1
z3fdode{+zYt-8<hx9hPd51CW?sNeqHAkUaH_=j}gCH;qgRF5fn_ddpdALD!q<A17H
z*T)q4z!b*+6vpP%rFveFYOceP@=IatPhsqr{#c%W3Uh!|mjK;$nM>KFFb_y!4v@ke
zAT?O`-Kn90dyKIujFBmf`!WYiVQkFz%_+<Q^5aqpV`U0srTiaBVZ4<86e*06DU9_g
zjFYKlx*Ss&tL6WQjNPd<I*imh{hU)9b-PNTA4p-WP9fhZj9n>=Td4zje5c)E-R8(k
zx-pKWFn*OPo%T|UU!@WK%u6wTm8NyRN-^$~q7Ia{(0xKppNr>L8jO{tcvhttS4z9;
z{;m}9l=jwjSISHH(tbgGMqMaH{Vy%o<*1C@aXD*U6$=GFggmI$QB{gx3sXBa&`ag_
z>VXz2HBSSbQ|j3T8m3ySl)5llhg9p0YK>8?B^v05-b2dohqWH4)&LE3KefK6*7Vf+
zR@Cd%8l75~Gtl4E8f01<h+nX4t;|3Zli!wWy-TfYskJP%ex=r|40I})!a$Fb+FpU~
zBsCGVzNFTa)H;${J5uXK1{#sfyVio#`j3I;qt<!U+K$u!(i)Chw=vLaq&{Py$w(c>
zKzosTi&|q*>na9Xiqucknu%H`QEMXxdWc#Bk-CRk>riVNY8^wZU8wa6mEs#%ei<I<
z5>n?#>kn$p!9ZtFYYS3OP-_Tk-9W7ssPzE@O+c*!cz~38e_G>D>-q&+ep<gzmjlZ%
z(B`8aU!cLKb@#M(p4Q0I&qdb<t$C+QfSLkY&rWODIn0aJstfe#bbX)>oz|YydUIN1
zF3^>umRz78N6k2`6Q{M|iuk0o2AtM?(^_wVz8f{&w04`;Wz$-0T7OMzu4$b$t*xf@
z)U<}0)=kq|X@Ra8wam1Bnbs`RI%Qg$OzV+p4Kl4ernSbjzL?e&(>h{WJ51|^X<aa_
z|D`p*w9c2-_6qd8v|fyEr@CEey)CV=rFFHm?uphUqGp!X$<o?bfgTpyexQ4$b>69O
z6=+)VX$IO=TI*SBMKL8>i%RQHY0W9EGZkn{X+0@wNNL?Dtq&DwLb0}M?I*4G6lgqA
z*GX$R1^P|YR0?#OsLd4UF=@HhU1Bex^_2omCF&>z+DTe3i5f|PE)r9y^^dgXQJ{0A
z_1d(ak=8JxZc(6Br1goY&7pOOwDwS-H$;sgtt%9039;YMnn8h1kk-r7Iy+heh%HoW
z{b+q3t?8q6e6)6t*6Yz4JzAGXYw>9Poj`L(_dL|r(Rw<8hK|<F(d9{f9Ic6?b#S!y
zO`vz9HEwjOsAZ$|YqVyK)~V6jG+K{FYtRI`Gg@ngeT&wV33OywR|CBmtr5f0(^@cE
z|3z!QXq^|W?V|Nuw1!Kd+oEfT?zQwtq{kHYIVz$S%bK5+Ri?@qM~v6eRlZ>ySEg~&
z_@}asoQXlwbj*+{G8>u^RcyLuTt!UZOsS|@W`0Py=B4IGRl;m;UZy<ryXJRQ%IaZ#
zPL(>9&b=xVZ4$jgeJI*C+D%;^y)8OiT@xJ{y+?f}Iy(AQbzO8q^g(rfbaM3T>W1he
z(P!0-(dVM;)WqoK=>Muo(ZkW>NZ-G2%6_Dj-56*Jv;bNI?SW1OX4k;%0rUp?0Rw?@
zU>GnGs079W6S&ugvZn$wfZ4!YU_pQ-z;a*}Pz9_9HUTdI+k&`u0(*e{1?Itm`y;?{
z;FMAhiqI)4Fr$D6lxg>3I!%CPKue$v(4oNW40Ho}0)2q~f%`$g5MVe^0gML50TY2K
zz%*bcFb9|iECQBthY{th2G#-_fX%>GV7tzjvkTZ8n6DO?dH08OnbO=D_#0MWe-t<Y
zWKnf&pcrsZn^HcZ6ws)^ycB3&V73C<oi-)Sp^iWopgYj(?V0k-YMH1fp}snPrYG+{
zRR;rr!GSp-c=iPd4FyK%@(zsx#uS+2fl2B|))wn!YlpSl+Giag##o1~W7bJq*&#b(
zC+xJ{*cxFswOiP&?e=yjyQ|#;S8uzYJ<u+<huI_TN_(t5!JceSwPz5s?YX>PU@x(k
z+pCBwd%eBMehDFNLufngJ@$U$pnb$XZl7{Yr^tyqo>OK|cA7ZNoR&@-r-Rek>E`rw
z`Z)caLCz3oxV_4$a7H`hoQcj9XPPt9nd8iJ7CB3u6~JoxS?g?YHalCL?anS|uk)&N
z$T>=!aIzs=5GoG2L@LyXxHQx})C%+ScEQ!Lh7-PHs7r8l$JNW}5b6tgqu?448Vn2w
z4aGGA*Qn5#(0JHSA|95LdxKr;2Rb8a_O34`-;R7c@@<3N?0XAE3ki0%&$e+Mui5Lq
z4P9Pge}epV^wkoyRS?<@3~hqg()}R2xlpGscjg%f-V+V4tmoVZx{_|56u;HvtDj>y
zlPJGarz%KWXNG()`5u&OzJ&a><gX@w8^U=-QdqrL&dWk-J2OYx{U_+=7N+)-4D&Yf
zSCPMiDZiGv8&1E%Ut#4axt#nf451-ydr*ECLuMM})I{(x^4HK!E5<&EvBVh5HRP`)
zuidw&`(dE1$+sroM*b~=wr2>GkN~<sMZdPC{7RP6mCl`vr6b)4-`1K#Uz_N1G(%oM
zem?oF<foBeD{07fq5IC1%%trn8JhMr8T3C$+w$49wLe3872OYI8tx!{MrxX~Q)*i1
z4XJ75i^*R>{tEK#Lc1uLPsw)j-;gwfmXY61zM8i3eA|R2J*_BdhyGbY_&wd&tX+Q)
z8ag3$EG*%8AxWVZo-K7uPLIz%8D1iFO!(^OgwIY2Jt1{0{F>w<TuOREXz0%pzUJjD
zMDTA?&iWJn0r{@vhf7U!eknCg=P|Tj+!rN;4;RzrDW<k9!}${3l+l(oC)|PbP3C$!
zZP$`NL3uMuwvzr`Bt;)#n4K8AZXMgnn{@LvhWule(sssZGWKth{~7&CJ!!3}q#tFt
zSL8)e@~lOHybaS(PW~$Lw=)FR|DqVvL(25D(dh}zVtO`6ePFJy407F;A%BT(ZlU{c
zlJ7tormt(rvlWL~lS9mJ_zTR1#L`YNC9Jn?Lk?{RkhdAj-&iK!prkEr@pQ8PLE1KK
zk?NZNXVTx%WsdSInC2>`xtKFjv^BNfr~v(h)7|;3^Fp+7v`zFg(eBaDMSDiCi}s3s
zKH4XGeY9`%hG@U&jnV$mo1z1vH%A9XZ;1|y-Wn~BeknR6dPj6b^v-By^xo*W=>5_0
z(FdZFqF;-yjXobe^e%?{3HewsKm<qxNC#+KzzZ;QG+G3_xN9Bo?E`cQfDzrm%)r15
z(!dPT7#O%M58R7vSi$|sz^n`~wjj<4!Tn^Ub~mnl>VP_|j*0fVp?K9kVWUOODI5BX
zjmAblV<5P4bqsFhq>ajglQza0GvvAE&|;O9dy)JPrIwJk$$g*vWuy;FdkAcQK+3)^
zH;%lfY0^h1*M66iU(V2$k^YI2KappDM|oSGOKVjhCVwSqf3dBWKDtfyZ^-|T(CiS>
zfs`B&m({BzZGrqgQjR@YpW*oA?<c*IzN+Z!|B?SC<!ouyPcp7&DF2o4S(72K?+DUx
zly3IW7uuehsvM<M7b9w{!L=UOW@Cpr)7oPlvO`W6>yUNG>4CXX4`(R;%Z$S{Db&q6
zg!xI|(7@0@r;F1?e2M8)YPYZ*2>*M;uf8CaFytEQjH~hAw<eTIq@;^=qcy;~*}BEL
z)vB}}cl)`wxkKII?nw78x5B-f`X*m-$GTs2$GH!<6WoW~N$%I&$?n(PZ@3S;-*l(C
z|LK0qo$k(XXS$ENkGZqm@4EBcC*Aq(58S2h)9y0&hwgIsNA3#uC+;fuXYMm@mHVu_
z)_u-h=RWVQcQ>d;?$F%U+*Wr)?svK0xp$I|%KbF=Q}-*meYt(^*j!bv%6%aBc<yoc
zLCPnRPRgywt#H3aI-PE2Fq}te`y~1Kq~B+l%PId6=?c=HF#I*-s~FC+q-#l^BV9+j
zLBdytPKB7NIWE&3&JY$0RUfu)%$4WL-P>|6=3aEa%$SFf-a&d7X$9#$q?M#&NWV%t
zj`ShY$)sN=eS~xt>0_j`Nx#du=8=Ank_DtcAYDrOH0esxRiw|5K2N${sJhY}lKWQf
zTS&X)cBtg8Rt|=%kE)Lb`52LVJ@-1ElhDFE-F-&R?j;>vkjt-}k=Of4$DbwNGnf*c
z`<Z7cgYPiqb4kC;^v@%Gl78ot7M9Io=H>fL|C!~qjP!@3KQ1V_pA?kePf1swr7TVB
zMio;r>+#%9^i{U?c}W54M%P?dtCID!A8SuL*fds+VFO>*0MeToPCuqF{}hhrj^il^
z9Zty|<nJP_AibM;xrclu>AjSUCLKe`SXHcwQS!o%BfX!t<4GT)WHRa3NvG3&zWhZp
zlP+hGe~ffCY3*_r$pX^Fl>C7FQqreMmoc0llKz-<CFQF~e@e+}(q|}no^(Cw21%8?
zvy&$bvog0aw^3QRACVh@yT!T1D7`Cj;VH1y_fr{ai`~dF7oYd$?o~}-;z^*?=jP_3
z)P+{&4&@HPy{9~sy2L+>^p2pW3#|xBT4-fZx<bE7IxZ+np_56!PWnhtazY;?olW{Z
z(gi_H6uOl3>7Z1Et_n&*=<}rOg(82IL0xGqXTl*rf0FSr$gdgdB_m8|UQw~~RZ_j1
zKZj#ktzYiV+?#JZoCGfMi>JUm)bpd=`TWrSYWRk@#4k#%(7*KAxj*OrOkP^5sz2Si
zM=&=D(j#?-7y4Vtx3uXRI~fDS{NLRF)_9gWS6@CPZq(;mvO98jsPp~dnX|76!mkxp
z8(ekVo{^Ti=|Y`nI6*noq-jTPM-7kGl#eU-m)u{-2YIgV_g2q}b@hCH(%S3#mEYmq
z;hKA-rEYk+Q@K+${K?!&nrP$da$Hh&zs7~0L!Kk^BWF9_hztEL%T)#SC10*V`J9oK
zx5|G|UT^i|tU}Bn&RTYumDG((dcC&_m%SqLkoTW|PG`82`djyxuP1poQWvhnRrgn4
zov!0oeHvF`Skhya;Hobz&*z?3Z}lr|%i><1eH~ei-TBt5B2`3F>epGGZLM(Yv{nA<
z^LLhX)f;BeJ{Y#t%eQb-uU(zCdRBKqnMhbQ*NNN-%A~%W>u0JG{6n}!DQmEGtFqm4
z_jVO>?{M!>QT$7&R5ABHcf3mBzrla1#`rHVTeWoOxC>N!cai&)`ZWFrtWeit_P<_T
z=Wf6VeltSsB>y>7#2RP~MCi95^e93f4E|Qc5k(wd!dN!M9ilA!AGuA1@t<TU;{LKb
zOclAeBLzvOAc+)=#CVPWDzLrVy<0WFKbBFLx!i-4C6TiGK*zXaApeT{6{K}6W<sX?
zn^BH?KhoV0>7Jkx?t|_`g#3{E5W>Mf9OcS?92Iw`xKj`U{_7wX{M$j!{}cK2kk4;{
zPRBgSbieI>8>yXv*^=!(;y!|KX1X&G<D>4QNXaaB7D9N;eGIm<Q95yy&J%F|9d|Br
zhkr}R9sV!D_IoI`B9>YbrS>!=`1gcxmZJoVQG!1~`d7KDkn*3ptC8}bxj#e7*SKro
z>lybMxUX{8A?5gAg;=DlO<bK>*2OIAhAis{%eo=UI&wx?hYHF%jDLc|5r>p@*d5{C
zi4;hQ$64ZGmUt0Mya7u*?B45+hD1s{%n~mtDDf~$yoe?4vcwy(#KSD{C`&wyf0Yj-
zd?{;(WgTZ($InvMVU~3f%en!|dNw3=%QsX|zF~JUW~K@E`|kIVmnH5Jge+wpW?2`p
ztQ)vLc7F_hrMnVxDfbeVdzj^3#Bz68?hRP(VU~N8<sJ^oJ-=sJJ0;&I8Lqskk2wuc
zlJ}rij>UiJ>B!3r<U#&7&ys)6{F0>^dXQ$SCC2a$+)1#r>Z$su{%VjKqK2yqH9G&j
zi}_{IFAR1FD;Jv6yK{Aidm~q^v|ix7$}l#QryjW}bHPA6*?f)sexX)dp-A(k%2rd<
zdgQ=zuXWM;yS?4(k<VM*ThV`;%5@qz4InLd%UNr_jAwGYI|5}q(!C3{^ltYa)Tw*j
zd)Y6173Flld%yCL-v`l0JmgMN89e97>O*K*597bT^cNp?pKuqc%kX4gKzT*c<*Zd^
z0p#AO1Cd(=5LqAdVRO1U%Y4F|Z!R{MnJdjT<~nnuxy5|h++prE_n8OG!{#ybq@{TF
zal%Sljjg6u3#+x&-s)s^wR%{+t$t`J<<>B3q*YmCKh~OHO}3_5GpyOxTx)@~#9D5x
zvZ}20)+XyEYn!#x+GFjv4q8X7<JKwLwD#LYcGULlGP{Z0%x-D7u{+qE?QV8YyN})9
z9%K)(huanQXnUMJ(VA*cv8UNH?K$>5dy&1=UIEvu?X~s>+;6tG+S~12_Fnr{`;fWA
zK5Cz^vyOdMGl<72c3dZAMVv;?rA~9FmDA4YXg9H5a=JL(onB5~XMi)<8S0F1Mmb}g
z@y;aYVP`sg%yOP^<~xh+6V5VcrL)FaS5tm<%dt**=1r%gv(edN9?O@n^RlzUv7O!d
za&-1N2b{ysvHbJN+dC&iO3F8HhC-o8C=p86ly{wS4>b-o4Ydfht})x&(?Xp>UF(*6
zs7I)Gs9$Jcs5~?*G%{3KQ|@Oe@6g!LgwSMjSxvbIW?o)nP7Tcn%|=NF&m}ZBw7_Z~
zT2j+Cxle=fC@J?TQPkEosBv!GNXc(WsV%K{sxW*?9wALo5+^^6l)I1QzDfB%Nx5f(
z;;tT;Ux`Fh?rfnBklsQ1eNyg{lB33OPVbDuT~gFTl>C*HJ&DO&828imAEbI8j;*Ah
zqvRK)+#^A;Cs8990(V%+GGycPl(YX))KJgSm%(00QS+O#C?m(x2zFTc8s#}s?gC<P
zXA7f(66*1*JL&5I#x+`KH6^F+qV1Py`wHn0hHNo}3A8;)%G?=0Am#2aYCh>lDES8Y
zXBh%_ZON{p{70nROGYgw{WvL~c#hAyTIYf#rkHYdH*Jql{%6u(l0L_@ac>WUajEAi
zxt<d4&SG%K6!jwIEGy&Nqzy^=WcB_xicePY$(q~?$M|2;+l5+8r^$U~45r+;gc9b|
z<UTjX|05mDa9CH>EwsIc@+wlMR(+jvt$m)M{4r9!hYf3>`4>vK<AS-A^kbBKkCgSz
z;9e$*W0U$4C48oe`=c1m$uDH-@#z?Rn(9xapP`&P2dH(VSCMkR4RtkbKgnlzCH;PZ
za_;?uF;Zv=<s2&&_q<W}QKD<YA%?&*$?B)}bJEVVWof8SF<&=RzMYgIn@qXElpDIO
zac>^Op)V<I)=1TgZC(0}du9A}o4S{|t=vz#?cFQg4(?TMNB3&?2KSa)<8kj`JT4Bx
zXboGBy8|iC56&J6Vn!&Rt>v%7+wdndnVuKqyGPB;Xp9<9Nw4>0Rw1cef~T(cY(2eS
ztL)bL67FQj)}87I_~Ysn%$;hd-nSKYdt~p{;A&ztgJfsme!byIct%TAWwgOv2gp{T
zek?G$!B=Ovlxx4yQynz=pk{DSSP5Hg%ZCkj{RN1_Lzuw`67<-=AzgmDXHcUH+Dq<q
zja9D{)JgVNxqHd$zL%{}_w(v;QjSOJ_oR>N&~mwaKcm>sE4JmFZdvT}4fe*t$i*F%
zaw~JEKz~+KpA+m0B^UPvPgiJptvb^_us1O$Z|Zi%bHBm80nh6e_lv5DJI$S@K3b38
zHZW7TI{Zt%+hJat=GF0E^4|jPTL*1yOwby81+B4|t+8P}zC5@rLrH00h4w-h738b~
za@M&f^z%zuVHj^6)53QkriEub;lg;H2yA=sDfO2BCg+Udd`q!s@a*~o?f9JuRo;-7
z@#-7Y$af}OT~9k)(9_hlwIk5wf<uvTE+mxpK{<5-y1oP9NJtkFP6riIjd*nix?Mm>
z7xJVQz9Ua+;XCrA7QRDIYT-Ndq!zwoPikR3<Hq@h@I<}i#@qE>ciecp{^!H}gkaqG
z3ix<1(~&uj!8wk@IZgx4aT;=t6XhHy#yO71IgZacPMUL^GR|>6#CKzjYi2qNIn#Ms
zwRL}p`OZ~{FXlFLKkhbnTezQa|HHk)ZRdW<?d)FTc6A52UqotkT6HSd!JMe(qLkk2
zbiQ?IzMVX*$CH|bYhExqU7We-&Dz>8sI6Z)58vlIE{$YOZl@|$|C;i-kW`;<ycI!j
z(jIfy0q<$d?b&N|I`5J^v-S4l(`cgxz9Z>AGyMKR@6t{UdY5A8z#McAdf&HK3bjYe
z{z3hbH_`8GT5HEMpr*daSsw3ZOc!1@3*V!%S@@on&BB5aVJ^mmi+@Cz2VBe}g6wfA
z=f=zj$}Zx3$oSI^PvZY({Amxo*W=HqVE)?y81oK|A?F*nj9hKddf(lVOP=SuHFBNq
z>&npEy?b%!@Q1!bb)#;7dV3JlK-LAR3FT_oJN{H^$2CZW`9)4gKvs<hy{obH58Cy6
zGcU+Lt#>n~fd%choZ2eyUR>{X=`DQEN^jwNSb7qdehbNU(qQ(McXOkXHHOY;1xt(&
z_)_;{1>v_u46PAI8@Dav>BN{mjks>C>0|Sw>tJ`V#EDo<j<gm>+Av4jh8$^2IMTWt
zY2zGeQyghaIntJKq;15J_7aY<O}Hx2f~yjrRHaJENrCks6qt5kT7X$#U+B*{OBmPN
zW9;$vB;a9i)9qQn6Tp0Mi|u9hN_!2k4%|k2i~X{_1K162pMAhSY##$o+6Nrvgq(<z
z0Mg(ZJ58MyPHUh&xK2)2r-#!U=m!jR%AH}(NT3qjSZ9JW*_jH=05{v2>nw1V0L#Ix
zs^hQ9S?_EDUIMqx+3D<Y_5%l<o%TuRh;!UI6*5Cbp=ii+CWOjDO@L++W~gPTO{fFV
z8C<v8VTO8!`h@xegTM_54G&d>Mg!x(O@!+yp=rQO@fVsCnipCGECshBv^umlv;o)*
zZcu0|upQVH+Uo2H?G3#eIs_aAcOsN^j)!faIFt>$PAHsmHUTfOl;(!|hZ_NxN^V15
zs4UzZXch9p?VKLrj^QpqcW}MV|1R7&pXzYm@PP2(@X+uGU=+A9h<$u`67Vo%pAeoN
zo&`L?lHVDgA6^VB3(E6gcxA{8uhHchUKid7Y@y3g_~q~pV7G*Vw5|*90}e>4?PcM^
z;bXwbGwVx{Dhd@vibD48qC`<zYEMyPpsCcJ;KaAq_Q|47_N>}<iKoEzF6!a5kkj9s
z2}R|hCIFu;Pm8K78tJqz8tX)gCh(NE$wf1O*+p}Cw%c;2DNk@)ADURSDKrtT))&3x
z%q`khv=i7PC12ZLoqAU1j_11VFFJB&9V|L7=eHG|at_KFZnbNqoa7c>Ca1RXw6<Dz
zp_X!X8_<pQ?5%3#9G>RZvq67d2YII3pa#RG4mPN0FuK9G2BSlp8%%64rEVQ;FfF_T
z*qyI~4Q2v!@^!GmJYW%9oZKx1R>)n0)%p4<r?$~<Gq5#pr~Qdt$g{^c*beNHTF_uG
z&uM!#+^WG*)Z`;_CR@lXwxuLge(h49X`@f$=^)h7>;C-eOzE?9xC&`-KYN3xpy;(u
z{Vjy0zb>ex?f=l0YoNw=Y0K{!%zl*U)yc1t?@Bq>G=p<s__d7wE=7O4V)3*GljoKg
z{BlOGrJDTy&E}e>rN0W`*Bbik8oko0zur;$%MGsPD}LW%@EZe@X*P74zeroI$(lDY
z<Teahe+j^^bo5%SNx9AMD=dBPkp4b_-{BZM;m0bY%P=J@RlUNizx}ZI)r3BMD9e&G
z`K5=&uN3sDN9HGJdz5~;+H3OM9-Ad*{RidxE5Yk1=Sdfq{%V3J0x5mw48N%`dHRsS
zm10A$M{{M_<f%<IzizS^vcYeeg42*#GUlyx{}lNKls`$H-#8gRrR_81`IU~PPk-Xq
z7kcH|<abSmUb)s^Rq^B>tCY6<`Y8B*gKli*!r~V`!M8VGp<IX0Z&Yl4pQFz*3clIk
z6F2plLi~!x)ZcOGT>p_gYm~{aF6|#P1bz===o-!vvsotAXDOjyN1t=WFI7yIr~NIu
zVNJ7HS1r~Vlh4cHS5LP74u>_<<~LXRi%sV{l<?dheWFotR@JYB=2-q{HAf)lIaFvz
z;DeKz^!F++&?VD@79=kDO)1(G_}oUyw^Gh8VbGc+1b$a$UQ5Yk<lBne)?X{_6<+DD
z)cDPS$@J@QnM{7Ur0zFdwk)_b_16eFEioc+$(E@2b(YC?WUyA~FOh71Z)33>j0efH
z-kR)fax4?H4oP$Vi-;rnFPCyFjVN5+Mql~_E%qn5pGdsw7eY<eVViZ;;`1`~31j*z
zHTF5COE>!5Fn*^OeBX7F<)CZJGmMvCMwx77rY;lKVMo`0o*xq8H*bz^-9KYF{EX@O
z18ry0mN~WA3iL@Jir<N$ElZ5rFH>$_K{vY2NSRxh(@x?ll>RDB!F+GNy0I|#?&N-2
z6}|}?qw?Q8ef2#`g(;~BVxNUL#|A5M?@jz~{okiBZL?vH!<G8COr1QlvLI!78+oq%
z>-i$=tLGJNq3`@UZO4Dnf4ZPnL0;0jPU_q93mLDLi}TOBtQE+=+SI@3zi#TTIA`jv
zxWLq%uYW^L0VXITh<)69x=MZeIrd^&q_w7y0(p0(Q<HadK5srR)PMdv%6u<*|9jLw
z8E#v|Zn5RdGhFhX#&4=H>Pfz2E_3^$wzP0>bZ=BG-GQhxm$R&{V9jY$lUiGi$CYNy
zUV0IvSDx)ymH%q{-#e|kCXBntYQp%7s3uJKKWgRq5lcVe<rl>h&Zjy5oL5{F&pDs!
ze7m3UUO#QlKx+3r?|mAsDCkor2BXWkAQj`^<9gqVb!Y{9io#K2{J(V_l2kkR2U&)v
zH-YotWfx7lLuwUfg%f!-Qh7~+iy`Hv5n^54&-yB9e&9Vy^S|F0nih3Mq{X}njQ{_2
zX~=B8FKUp~kfu^5hUmDz`aUg{cjoIGOTAiCR>lV<^%f;%s{`tQ(M)=I!w&uxe^6Fu
zt5v5<%0#(+P*!hMuMVn%Mspd1F|L`ooA^O#y~TLf%xL*R&3ap-p)IYkrqn*@xz4A|
z9Nj97RzbToK4_KaRnrQ~?1R4SeCygFbx8JEmiN*|5kfztCVfzD=bq)`A8eYlR#R1}
zdGBF~y))lpTWYmh%eMv-;C`c;e-Y(CKZDb2Bion{`F47O+KF7fm$moZ{$^hCl+T~}
zzRR7>H$dC@4rnfX>{9FAXHV~R?u388<xgw2?%<l{Jls!GyVd&l*%RE3r*`@Y?t9-n
z!P>p3&6>KarX{{#^XUXNc6U%`O|}1hQ)BBs(ZYO6+kC&~RO=zij!Cl5%zQ{Dt5?;A
z_hnwqU>^aQcP>&(|E*?i_308_OzB<7{(in%Tr)40J-PlJQ(Ral@+Ez7rhFmm$l8J#
z{06o8qG`GH)p*In+L{^r#hx2ILtj@jFW9KIT;xyZbZ&&d*z==j;Oh%UdD%bkV$RX~
zr#D#mzUmDYzR!Ath3~W8VB!0&H_%UL9iGbRCnS5LUTpcPZ?<N$=54HLNgw3v-#uTG
zxHs?VmbF!Fe_!Ox<ZdRS>0!Yf5bSC4z&j9Q;jHU}R(vt#%L&GjO*L=H-Y>QN{oIb{
z247JdYJvLqe9!U(`+|9DQSeSkzFGeFeoOHLOSX#Xoda(CMf47}Zn=-I$%k>#=ECOJ
z?)iUI#zpj&x9-y@{9icXqRmI$e}wWM>SBE&Yw;9LKanjL@u-k*DW`K}T=e;If|{0}
zZ5bEgKij%bsP^n};zggMGv|#mzq*+7Bs;dXM7T59exk0NC3E>1r^$42^;tOY$tiTk
zc)|$Gw?d(tK1L6tx6#iSXp|enjFCpAG1i!1Og5$(GmP2BTw{T;#8_^uGOBpL-q>Wk
zWNb5b8hecW#zEtVaojj%nr4w1H9fP;Y+^PuTbgam4rXVwo7vOsWA--(8Jo-@=5VvZ
z9Bqy>Cz?~tX|*7JW}0)%dFCQ>sky>jZLT#pn48V5=5}+Jxz~KvJY*g<PcVJ?H0IL@
zm|3I)>9uUDSkh>@R?2E*UCMh&FJLvdS~1;0+O2k0M}e8Oy5!Stb+>w1eXRjZJJW3q
zmULS~tr1K+AUrY38Y6kJ##{QUNR{6~%F=rp>3vps`jf$ZajcHy^*%J0lj^g}xJ#3%
zcR#v;`fh)tOMPk<cXQDvYneQ$$>LdI`eZ6gpPBP2dA(~C_mVMZk*D^ic@JrSy5ZS7
z!Jbt-w<@Q1gyKFiMr+!RC*}S$)?CWD=a4>+%V5a1-n)orL+M?ha@--t<bGGd&Nti#
z%hY>oQHR~)8B==aB%9}w=^dCXea4qAho6vg?;o3c##q`t&u7y+0NLDECfGA(J$Y(o
zT8!P~DOfho?6S6z=gwOuce}Cm9!T7a$l|V4CeL}(XWZ#Ma`ZWP`a~>~dj(nC@yKAV
zExlWhPUjCP;chnuPl~g7?vUR1Nbibdaj!3vPt(>r@o)z$i~DBjGs?L8k=_|YMrFP4
z#sqcx94eFjh<4GW#>Io6j@!fioZHjA&b_scyT&!{<a=k^?dE>Q?e6xjaivesl#_x6
zsQORq%Da^PkJ<qp3n2Gh>YyV{6aOU|*R%<JE+BUf%5oR2tUfO=f_QDXmc4aKYI@K5
z`p){!^(;}Mhc2)Jopg;=G)?kV{5NA!UtO>sedG)^8zbrhnEG6;`pvw3)j7=dfw}1n
z^QFLDeuueYwh=ySp1_?yMUbsK%Q~FZJCN~A#VqSa_Oqwko!OW?Pr$Re8=OA*5apOg
zetU3-UR!Dl>O)WPDYw4U&8`h<!Dnk~O>g%Wl&I`NHj*#`q_`LANL5LctFfq$lhst@
za3oA!ic2V$ayuW$8D{yf4<vUilWMlaEZbT&cbls=C}9s-&3(?YY@yXWxvqM)&{Kap
zT|U+9IkVjJteRz;<?e3PlY;VTuH-C7sb_C>;@jEnA_zyGQ{Mo>%Z_7%gL~OGZA2iK
z5nv2_$QihOK;<0VKHSr|XW?16x(@K1Ya_><*z`GR`n1U$dklSYW;IW{&GNLvEO*q)
zvgTBCtjY51$1G2h%wEqvM0PdOJLBlxaUMEHzVrLoyj@>Q|0Q2fE4{Zs2l`d?HA$W8
zEWXR#F7$mZ|BX#jb877hFiE{vdvZxS&el^Jm{(p%-acE8@2{P=?;aQA`*RoMyXOV@
zzV3p2-&&9F$>;66+Xeal%mw-GenGx_(|058Lf{qnKA$=&t`jOhH~6}6b^ia<-f8;u
zzn}=)!63ExZTLAqcZr(5Q}%k0cB7Q+5h*9`%8XOa8<ssX7Y8!oWmgNC!O1SIGOv=I
zAGaW+DQcRUi9TW;IQg=01vOe$@EeP*{FZrd{*=_*q@e7C=g6Wsqt0;#u6r1RJ9Gx8
z8S|9a98bZ`9Sz18;d$1s(&rd+|IRFDfLZR?Q_Y<_v)mW6nzQR_?lF0aJ1JH(oU9)8
z7+RL+SY{Ii{l6ajnA+-}2mQSCxpLZB59VNsdi%Rq=o3!wVQA8$c0(8`)$<(*Pu?d>
z9hd#Kdc7kdmNBn(aMD}v3l3ABoyTySvgO?5%83fH%cYFAQNm!m(e-0)P!II%GGtwE
z-DC~0?y~N&#!+rKH^a0tKgz7g{8-i9MeiFDHd}2x{_Xe-r4nCG+^NjOU5T-(LDEll
zRerKtvY)y(*+1D|_49t=ZC5vXJG?)uFZ+G`zUn@|pMSF&>)-C*t|s_*_;;!Y{fGP?
zs7dLn^sm&@nV)2SqMpla&b+ABWp-tD@kIRQO8%j>;$D50s`JZrz%@5FH%OO;ob(&=
zO1xIe@UQZ(Qf4Ywiu9*<r*|tOb8`kc%v5A5#GNJQQ7UVi?WqQ`FZ{dvlayu;1y^TW
zqj3EV7k;^tTuJuL?3=kpxklLoxa7AU*P!g6>J!x`aw~An%FW6i!?hjPQC!or({mGY
z6AHu5c{#5pY;hxD7vVzqg<<E@#IV1H>+am$3|rz9f2*^r^I_Mdzg4c)8F}iT>tA?Z
zlkUm5T4Y<)vO~J_CZC%4ufjDqxLjOKapmu;f@?9Z;7QZOC3&osju0-f7jtKBXTD76
zS1vcW78hK3dokzZl5m&dT992(XfI_ZWl>Yx^5uP8U-Tz_{G5Nb^3Fd?G3$Gl`Fz);
zTLqWIBVk{byX;(HGw(szVlVggh0XFu*x7ctBu#s8ZNT*su0P{i6kH+;o@Mo>>P@+C
z;hLJ8nw^1b3og_Vsb{PwrYcUhMGv6Z1Gww~KEfX0QuY9C(9&n9uKrAaf$E#yfcAbH
zTl!sW>32)74gVOMlb=j}QiYQ3lb-_LDS0*c&dF=QcS&{u|LNqX!FNSWVZ_u8^fQRh
zWPB#$a~Pk)_$<UX6ZBEU>LAt)=m&nD-lU4szeEabq+qiOWnM%&Or}HnwrS`Uua`F;
z7Wz{3jdv*{J}5p2^p5xl(7WOyxjQ}z^nv&U(24Phpwc56=n=oHoW!ui2=t316C;(4
z-mwDwR}<e-;l#HSkAlul%m$s4m;*XLF(35Ti9M<$@jr<psv-K(QsnAG$q#{El57Gh
z<?1GHN{$5owd8cr?<5z1KAl{tqRF2mtHA#%xkp8ke^34cJ@JX;DHZX;UPOi255~Nk
zyaC{E@xG)QctgD5;J@Nc0R4vdZAfN#Gr-UEW`RELAywYf-ZE9}E%#P{uJl%dKI=UX
zD&-sZ{^B7P?@jMbxUBZ7LDB7~u>T4F6RH9GT+i?1cY>s|-x;)v-vzX*k7wq0^YP65
z?tXXBo_<fz&-<STz23iGnSNjYM(_ju!79N~BIMtRQNr}^^6x^(6@CS5@9{^2F2uM|
z<S+G~R<6IyU!x-aGyXai^Pl&B4*5p^Metkv-z(qW;U8B;sZXV@QQ=hA6w;9DmO>g*
zy;8kEzmWO@==G@^K>Md|0=+qPGw2snUj)51bt~xH)LMifqe!gu<E0&yU;2g8A)sF=
zoecV&(z(hieX{gNs;Kmp(pOZ&($`D>jv7{#eoiG&+kOuEi}Wu*H>Wp)Zb@T?mwq|@
zvTB&#mfi+_dwM(Qj`R-Do#~yRGFBzie@g#JrPBM;`&EPVtLaxE|7-fMpnpsMO(imJ
zCZXb)-kIJioavM41KKy!7qnldpNeGqXZouKnE@F*caC|n%<Y-m!QYX&1GaZ&?u6}K
znY$p7u`rfdn^_0`h0F_}(kk4{mdvl<a%*NQT>d8W8}QpQ+ra-W^E<fNk=X(Mzcc?0
z`R>dfRh0Ql<^bfcWnNcBWtp-v%o$80E#s@v%UG*Id;|Bkez|?P(3j_W@g0*QFV`Vl
zqjRJ4vijVrfw;P>?&4NVH58Y~#I5w@(hr`>o}$|}stx52=N{(0xD`M7aLaS$?6<e#
z8iA`US0-mY)uaJ(nvyO_1IEc3w-|G1SLoJMMVvV)&YZ$%@oiL+?dA&1ldeZ!DRsXc
zXGou9P456d3HB`(`j%nnPi{{PM{jcn`<XitmJ#$bcPH+Kn^B2T;O|LPLVj;zH2C`x
zW59m}@tKUzW_%9gGZ>%A_zcD;d%%?aYyBWoS;QXAWDjMr4{{h^m@V99d=1#59JZ)p
zwy0vZsA9Gpn{6P(y6a@VocXdUW=(Z6<1*tgqczRFs9UCa-0F?G<*EPEA8VP)y`Fo$
zhO%A;v`XHZ)}oj(1ioT{n{s&<s%weVInc**kL&Ro5y%e7dA_-7{x8I<C8y)fOM<$~
z&~&`o7W0UFT!s93#XB=MvnEG%^Q&s*mo4tB`DHkof5+lITYd}5_RRd&^Tgj~Ijc^%
z6yK=U4oAnO<%MqWZwGDVW~I;?UO?|E|BYNoqmcGRTfM=*0d1-uT9e`T_isX*8UWW8
zTvuU^^KANAWv17r*Mffzt;tNUORt0N^Xcc&veu{9gMR_x+6-4(`;RZ6wI?{cDNamJ
zOjivt$C-it=8?oB;AbXgf`1gV9y>8BF$<E%F!wPNk0%}nFEb!B@n4B2z<($49q@A#
zbHRT%@m=uq67%5e$;6Y8$SlcDd@u1m@Cy<Pz)SxU;*3f9&yT7i&X0;YKPu+@sF=M^
z1I~|%*#|{94=U!|rx>%InacJa^&Z8%aTex2w)dF#m}=<F_GW{B+<P4IIhYOE-jBT>
zLoRclsCU9U0sc+zB;^0}PQgvJmsJgY<ttFbH}E7(-vV#@4)~Cdk<SnNMc~`|?Sg*S
z<@~6a^P^(UkBT`zD(3vCnDe7z&X0;YKPvVIV@?!fznSC=sMsIxk4MOQ9`p|%sq)|S
z-$czg>7N2$?N@`(`jR&MF~PrJl~T%187WgWOj#+UEfq>3ZK-f748AB;1inG40r=un
zL%5HmN+5}*qL9Q=F8FvV0X~^Zg7;FT;IB$`1pld2CuOCsPF)SYbE-4=YcSh#Qe9GA
zAo(=rTvqDZ)V1Jc=4GWmlj;usv#HO5?~&>O{&T6%f$y2>318Qxu7gBoXHM$#sn3J&
zow^=;-&9|?xdAgZC)F?25AqvRH-hh<>JRx%n7cWt0jU9y-<%o<{+84r$iJ8x3`u#a
z9P~@6FF`&ebsPAhDa_MT!&1Y*-<}!){`u7NaR2kv&q05Y`UU8w)F#MZO#KS<*QsBF
z{wDPs(3exch3)nf{%fTEklG2lEA=N(8P7^Mp2azy#W|kEIR}h!4jAJcFvdAxjB~&+
z=YTQJ0b`s4#yAIzar}#L4jAVgFvdAxjB~&k=YTQJ{)##KE9UI4nB!%Hb3Hv?MmV!8
z&OD!4kJc{pyM~;>*_l6N{(yfy|C8AZ{*}xt;QyR?731q)GJk=a1DMS@nZIWKs;tb>
z%-_Ku%N*m{h2lHk_DZju$U9C$MPxpLc?f14GSiS*1!fZ?WIll&Xaec4<?W0i=LEPa
z&Cbt2D{q##66OQwM}{$sJJ6SmOWcpX1pNqF`PRg5(8~8FUO_A8KSZ?i0m&iB+tAV{
zC%>7TincyC`DAiFTKh7z^;P&M^n3gdI)VQ`AHqMLA!zOQ<A2T!{HOVm{EI<5-sBzd
z4tak=D@NNzd+dwe6g??g*PUovJN*Ck|AE@yQR+4RAKWZ;2>$_ooO&*`4bS-Fc(&ic
zeE<8U>q|G6zJk8?=Xkci#?#z}r?>-8Zx^23pVE8r)Lu>h4bP|#o=rc@$OmKwWd>);
z@pSIM4E(OlJ(+tm_sM%WrfG-w2mDW+#ZoF`88=e;&F(ipD5;>Nijqx}AFESZrb-!2
zK^v=PwaUv&-26egy+yfMYPw1r@;&G*HMgeZOqEQ862<s$5=q3AlZYo0ssYN<$H-fn
zC{rbgOA;SZ@x(_HO;rkI+f1bsmnW`JnMB*fCspIbm5C1OBZ*HXI;oE)Iw!7CA4_~T
z(L;Saab2R9x-8K<@dfpXMBl^^b$RAQ=9KE3$(A|lTInAW-Um<XEo*t&XaU+(wNys%
zZOS)m%FRe*J}AAnD80Hp>eLTPD=4jKP2N6}?2hz2<WEX(K&TrL?xuQs*Qp=$u5Ysp
z>+5N!e$dli6t(}%UU%vTz3#tIl6qy{Rh69i>o=goQ1^!iD<z}Q0xA>uUz-?{7^_P7
zUeZNwMydo-I*(rnhR?aev_N&`+LD~M-qgR`Z{=U%w<&$JbXMtOrL)torC(3~J^e=d
zAL%#K|4dh>vl$~}W}HkoQ<N#rG|ZG_Vwq&d&y;4;nGa<eWj>twNaoT^)8Ic(f^USS
z2K?v0l>T=zMW!KNS=h!1<ERSBtB3RdRa@B}**)3q)xE2`We+GNr;S!G$&SnQ$~~T|
z$~Dh*<@>7%XY-%kbEeDcZq>W8bF$;IX7yBrv@tg#w-KR_${vunak&-1Xt?YuF0*EK
zOLhTVuFWpU9m>tk9jYFgofEA3ip#lxggG*BIjs8SGhHeVv1pfux}0^dG?`A8B`-;S
zIQbEo0VJCxKc2iS*)rKG*}A56^!IO)_hkM;|0)0brLUJBE&Y4xvC=n6kC&b*tuD=$
z=F(MY3v1KQrPrmOPp?nEz;#JkkuwlF>L6mkOaif70?CJy9|rwM@*|KmO*RAn@#M$B
zUzWTKv}F=~24Zgo+B(^qt6TYZb{5~+Ir^O)QnL`YPx()Qe&7GTGLf?5%0QZOe53aQ
z-_U(XYL7Cc{=n|h(%CA4`tut8S-+lsU4>DPWYy`7^c$)e_30m~0qWG7%0#{TC)`x0
ztCf?^rn4#}bxawkWe)!5qo(2ie{rT5|MMGW8meN{xe}E`y^E;?>RwWnp#J%glx9km
zi+Y$=ajA=td^q!A<w=cHu}o9c$|&1;8_u-)1#LyXpDJO`DE;CHw3NFN75??oPjThU
zRL+^L8ZCLIx|A(hzSi>c?S<{Z&BQZ_`dUTiV+HZ|2;%?NIpeq3hbZ<TE?0`1yv;cE
z8<Db_HzLz(zDH>gj0htVcLp)vE;Cd-w_5GJRv1kg#<x#@(}Mp0Hc$M8(?`-L)2Gt8
zjFqu7p_(tKP%HR_uu?N5bcsh+dQg*}LoI%x<{gZgehtso3clyLG$^4*<P8K$NPOMR
z6(U2~LCVscy|f8V2+j9@Ges9EZKT1cZ%;pf&>u`cs?ud%S*g05@ytj+!cb19AW_iI
z<$Jl}f^toxM4JZR6E<Rg@^M{QcxR^m(Q~H$f%JoQVk<0<x+#40oPJE>h<u%HhRnq(
zrrh)CrGqbEeiv|msQG?lUtnLQ*BkQd4r10H&KY!OJ@z9C_%dLfeAk0(Zf>Xk!l$;c
zS|L=OJ^fs75pJuDGP3fL+ebP#aP_hdmwEs}99%is%5kHdzVuqklYyI^r&CI9V?O<|
z-kSHX*Li|f*}E}PY{Xp^a41N{);g(O%GH{=HKn__jy=D7%H2#?Wp(UUP`Xt=8(E!}
zJ|(^;zFw*LhWHlMAk#L}QC7oM8Ki5J5q~EBj56a@@hZ4`HvX)#<7?w<l@ot1{+tTM
z*TvVVaQylB^QtJm9-%ZqC>!AG=kcGz*T(op`1(cs7x1+yzDX6we;NO!Y8c-f->f3>
z7vnF&*OnmGw#v-3%d|t!{>jWI(aX2bv`24#W#&rs`yDbJR5){0<|-A<bVT~(i@{6&
z#q_-pe*x)ut5h~*DkDr~NntAEzl#3~V@~~PjWVr~g0#kTS~H)@e2QN+M$q?Js-0CK
z;|Tsub-|46vx%YVQ)x5ZN!^_8oW4cP%A6=ms+CHA7m4R2=j0O@Bdp#u4Xa;pe;TGW
z@SJ?1%(TkSkk@uUtcI8P&csOARTlUiTgU%|ded?~={%Ra`tqbP8JJpdKcm2$T?Y~t
zMpV&-W4ZQz7s`0x1(tE$G}JBQB^OB<FF#8;tU5~^RcDc(%U|yr-Uz-*moe`o>1<N&
z`uC>ZbK^&(KPMeZ`JkFvU>oh;_yTB5_}uH_9&|S6F|(;nB=j%Ai4Bv;YhO`Hb}PfY
z-SLEGBSLdc*$Z?>`yX!MpBQFb`FASK&?8)q9-#?)gm&l=LaJ}ND1E8ADSa7whf4Mi
zQ`kE!lKvxJ5wAd>eNX%zS=W{?hvma>^ADM|nLnC475ek&?f~fNqXz=BHjL=ubMl2U
zBYNx{;ha3p$JA*zu~2Pyu}Hmfo=<wt<*vT8>o^lYy5PR?X*1TeHYBWA3!rsSb_d?!
zay)$g<yb2Zb<45+MN*EP>d$Yi>sjLHQNR3L{!Tw1^LV6Jq;F(EWN>6?WJF|CWK3jy
zWD+nY@-Q%+_p>5Tz?=^(29`xuM%Do9A{&8~kuAW>yx#$LD<ivseZYap;mEPb$r2Sg
z3I1eB2#5$@l878DNtZMx-?XHKHi6b~dl+VW*taj~RMHiEkCNWB?@`h(a=2t*NqNbz
zl945qz(8OuFoFDJ$fuUfAV0fgF3knN61Xjgxg7S(OIDRsfnQ&;iS{p*Y=hm-l07B+
zaeoll2^;~AlRs6mKWavcgpWp}9?deK3Eb|1*$np0qAjCsz;}ptrhT_)&yqdSKGFWs
zLD3=6;Xogt0vJtx9OM(DQ-m*RADu?oOkfV&_J=tS_Vc2PqD#TAh_0snis)L{ZHR6r
zwgTIMUBSIzZvnqG`fBu0!M)&UV2b=iG#fn;vtz}83#4K;?i&G@#+s9F1+;^Gt5`?g
zcLBNsy<&ZNKOi<ZnvD&OjR5S}C}0dQ9vB*%1Uwv@PJR~99rm+gPw;*|uozetTgm%1
zv2_SzV{8lYGOz>K9o!4{74R>|4$#fU0vs;zdn|U+RX`|qGIq?300}n)q<P=iZ3??Q
zS^%xx_K<f1y1G5w-fll&Akf1t2Zp&LflA(wbtk}_9AGLi!<`NJTwsB_#9i*L0;+)Z
zz!G;8@Di|%=1$1=0Q-T1v|sKX0geNw<UVf3i`?b$XxxjJ0Zo8rKs4SGXajVh*%`8K
zKu@3#?Y($^U=T2b_ro#TdGXQlap#SR@hS0Xz|8m@@bkb6=EN64wiH+atOnKs8!*$~
z3T%h{2DsZw%!%)UY%lOCa0oaGoQP-78)r#d!cG(?T)<AG5{<}T3cfkztpa&F@|2%7
zoQ{buiS9tJ!0ekCkQfXM4a~lY5im#KegyC9x*wGolNb+73e1Or>A);N?4E$X`M_eD
z%MvSLt^w8oPb4-bwj^Fo>;QJt+?O~2^DuA>*pfJzRLM{>0we-64KxOt0%F%9+4{WD
zKG`YR73h)d4Ze4>AMXby%V`b+Mncv*S(zN0oB&KtP6a<TIfM7JlXGb<0G2>DHMu;w
z>by{uT%X(oyaa3ms**dCdxEs=2Mz*z5bu#7-s8Y2;7D?+XL?0m6!3sD!1S7U&AgUg
z8=wQw%<JrRquJBz<Mjsy1!f_J)FT@XRFEH??BtCDCIX|qDc&@iGXrx9?Q6T4!~1yw
z7K!OC1y*>g!LLn>@WufXfwkTSZyL?bfw_V9wcTvx{k#B+#PqfUyS&xl_j<2-hk&EN
zUhjmL71Ou<V&4T)fmr}=$eA*~5pXH_=6)-`o!`;#0tnyT?^OqVYxn{FV1Fnu0vH7h
z@W)Ul81D}*nG16g@G$SEi;S4%KT!vLYxw#8Vt*MR=1O3Vzs}zXtns(_FT>p7@Amfr
zJNyIwVVKAKlPTq&^pB-NsR;N)Dh)JFHHF!NeCt$unw?TzVfIL+F^-P}%4v=zKb7M?
z#`je3l98!?B_pFPi9KS<n2vGU<T#G;I)%AIsvH=W5>%$f!kj>Ua%w8g8L8PY=K>2-
zOH#{$RjI1fdYGG%V^c2y+fqAIdtmNQ9VCvVj;Btg4wjmwMWxYFk7gOnCZ)|vTLuum
z4bTC0oq=wts?wf-xb0KgzjP2V1Q;Ihf(l?XFfQOH0#kr#z)WCH;BH>&qSB?MD@s=b
zYk>^`FW3xh1-1jbfW1H;;8oxda5QjtqBNVf)5U2wok}+XE(MwcHqk2GF5tzkW4a5_
zJ>3g@U&;rh2gA*!=~g8J(?c=08i{#U73N)4n1fYuzBaI=Dm_A*w3B%oo?Chp<YVMM
zJw81Nrp(iJrXR*!YGkxC=2!cHgEG(J9IH)wx;AMi^E5oy$au(S$$k2X^nBRiIj0w=
zm!(&x*QD108-XprV&diWj(}fBa~ZK4{J!9RCEOeUB)^9tJC;6~Q9vjY$s{uAOk?nZ
zrX^LG7C`H0n@oG46YK<CGd(iBGyO6HBZo5sOPXfNBPTP%O3H!RnUR^w%-E7WnX%C*
z`3cefnaL&XGv(1CnW^sb%#66lKD{gY%?UwYEPbr>@#w#$&y@Bd^<V0@)ZfhPbgRr<
zq+<cnuq6F*{r~CD{5Stj{*PC0ShCLYM)m;cm3+T&rSL}25Mnn5tE(Xy8~zOVB>COW
zF3?x9Ull$iJC-dCe^hL<|3k?M(nX|CkshVrHVo%hN{Z-yGWjD6;c7|_Qt~wEGG&;1
z?Vl>c`g*p7@XiSEy>s6YK14~#B8`ii>OY8Wb~_~>rsQ|zO@`2xlIIxC{giYBy(im%
zlCP4=JC)tG?9{tE+ns5U9oly1zD0f=X*ua~x(U%XPRUOwDI!0ce1ue<*Y4`$ln<k%
zKj{#b<nPHpNdA8rdn-!rpyUzy>Oo$YOb6O#81E&N@QGwUM7|0650id_v;qAtAkXKO
z{W>Ll3R&jYxsT<12g@YQa=3}*{B@RIijp<tLoCB*S<V|MX-M0{l)u0bK0^L!%7;_Z
zT*|q+nv&0wP5_PCi$OnC-B);LGwBJTp(&(yp*|c5Y*$f&8fy-)SICZJ+1G^1b1?@v
z|1C81A=3M4n<Kr2l78gBNcttZ{|@=<NXHAU-b<I4Q!;~YwlJ=>jHQ^8ztT-}()%bc
zqx&(G3?V<3E`LCN80q5-|DSa8DN3HEo1H9y!z_V&naADCqeJ>r(&;FHW7;;<4E!*8
z-)1bxEfrq!1&T5>{+K;P`UOh5h@0$Z$Rqv6C`yKfW{JG|P1;^B?yKKG$T0_X&)AvU
z2>$YrltwIEL`gzu_BN4(Q1{F$L&Js7-b<HR(u1UwhyI(k%}F05MW0}P(e8zC)?~j8
zzQ}n|XvihMO61kA(RPgVHq{SPzDRN%svt!hG_uZo@`HssM;OA7=u4h&vyjxKYph>V
z@(G4;3F%PTFU%=sEHBYE$yj=ct$l)_{hag>x>uw>q2vmN9Hp;Mf^Wo>+ZK97vob3!
zVwODs^jEBbv-s3zIX8+VJC5|jl>CYG4Z7)0{ucUug*3_#SYw@6N!ydIBi%t?A1B|5
z?l&+Ek4YM&HCd*O{@fas8zwya#!*?3n4v!8D@jXfJDl>~%CIvw`Wfr$+<4)oJnc+K
za`7wsAChaGBj*%j|1XrlYa%h4O9-Z2Ej6ckNYgc>SCcL$m73Yp-odfsD$;u;gzRkc
z%}MVd{W9g~*^Gzm&q+Dw9v9x(Dm2u9CI59wo+HhX{*&@{ptJ4UnVu2CI}3%%SO9)5
z=?PNF#SiSivNszd<BN<+#zV|e(wRppsd^~;l<?t(<a^TPKgj=-v;$Msi0S+mQ<7xL
zzsvN@qV06@SCJn_ei7-%nTATHL0aXnoj<b{Nge*R{oj-v7b<PsDyp8v*dHfd!c?Ug
zra_t@olIX>Fq|@mGnA69q^O71vg&TIons#onv*{2OQ9=B{}c2#**N(I<gbyE6u(H}
ztsE2M?6F@a-=8$bcpEcSS*B_jbC)LHnEV5zA-eo4<=>&?YowBkWKk(?%lP!uqz{mW
zNWVtP5y##qG&e{}FLVhhQf`&X2y6a8>I3-pOnGOf{AQ-Ji1hQM2-9p~|3P+2l-h12
zZOl)s@9U>;qiq_u+Fhjw&K_q!+>K+XlwmR$@gF0VuSj->2Z&tC3KEXdp>I=uGv$35
zS}TSotz)5$8JhW^%x8>+;vQ7mNV$!tV{By_%AFU4&;CsK&_vocr|q4zokQFEXnO-f
zi`%Ukri?^!_7V?D8!_Xd+xXmNjQ&(E%DkLntyo3*A*QMa>sU|P9uYnqrDOne(S<qM
zO!`~WYZ<~O`VG@pYmr#<C_hO_CBq*;zBxl{LCI*TT@IeI70OMLI%fYx+9P}EU*|9?
zS!K>|*^aJ}CoX+2W<GKz$WvL&J<L+4TIBXm*!rXo>1o?Svn^p;;ye$&xqVE+l#;am
z#GdeJacR4b><#{UNZgOg%^)wco!4!d&8`aF%)Vj<(|HYPf@%0GYw2Xh%Q`9H7_YG}
zdX3NGwa{ltn^3Zcd^hs1kx!C(tO*&Znc3TE`vZpTFyyN#nJhi6vx#}RiN3;=?<J+g
zVOww>Bi%;&dxm^9LzdBhjm_Gay^FKBR%|=6xARlB%;cYPK1%xkKr2|sdfGGSYYcsL
zW@&$gZU&IvOv!4{M;tv1<=j%z2HJ=8dd_BtlW#^hoftdk!!i?t?SGPAA?Y#y20FNU
zjf81SzxrDB3W>#flj$rXMO#*z#f{O^{0AkYN$(@gFr3#|f9_(BcdPLB{Zbm{Dwc*w
zzG|Ifd(pN}GKDvj4rF@vk)kw=7j5=q79_^ZoYcdf@~_9}nUlG}Ug?cN_5A<i^o4ny
zQK|a`XDMyjJ1N=GD;xR(XAUy<^^;i~d{xrr8+_vOy_a4WooG$Epmos($zLb8E9Kwr
zk5EPaJ^l|=#9vu@Qhg?UYx-7mI{vrbW_~;K<;+;~sm!>{{pK^7U73HF&vLzVcz_CE
zbYRwo5gm6<zEEaFC!QmmDFytr0yi`3xSLaNoad9CbGfT8?HcodMFsau3(OUDAYq|Z
zMArsoH~Jke$8m3?94p?U95-Af<+%AQ`Q3V!IJTcfelCAC&&T{@!<`NHye0NGJlOC^
z!{ZH4H9Q_Mfucw>;sHgGvPct}%_1#<qDULui`gO4InpiC6X+A^9~l%G5*ZFuL`Fx(
z0TUxrBGZ7Gz#L#=WFD{xSPHC&tcGkYumRXi`zevFz;<94@ApPtg?T7)G;#vSMvj))
z0S}ZE11^vX0MtM$zxYPLr9g9_70@nl*RiAv(7mJ=(6OX1%mFY514Bzjl#D7F1B@sc
z4@?3cE}4$|S-=w|^MS>IxvXSm$r@l?$;Of`B`=rkDA`@IFH%%;AkwGgaLKWflO@NZ
zDlkLQNHhVYqm4`E1B(N5S+r@%8em<tMaju%i)ib>3`N^VI{{szJ)*sVe$j!^a+t$_
zkw9g1Eaej*pAelKoeF*iF&py9gm$m(=0+F590-i%y~YBX{pe2QOL)ILx(X)zMNF7g
zl&uFg!T(Dzw*fnWJ@6y){gCg6`-9+*0LPJr^|%*k_uB3h;yVbp2jLI*F%z<blu6id
z7b^n4gmzJ+;h^|K8V({22V-8W3}_N-7HbK!4bTDT9P37TPsn@5`o#K!9|R1E4TroB
zq1|h{ir8qF&46ya9|!cOOu`m-6Twg6{j}IjnBs2^Fb`N1TN+ytTOC^)+Ys9ftN^wG
z+sW^Od~fVk@`qwaX`TSGaJxFT!nI>-UE3`#Sq$Dqc(8X<Zll<0w>Y)|pef<O+$&*-
zTlZ4jH>cZHaJwNk5B}Ezn<X5P!%aJF(oWJLemg?mg>iLvdx4j*0-4*_9pDZ|xI=-y
zzzATJ@a`CQushzJME+rSI?Y+Y6Yfy>>Fdsi{d{+^yA1qFcMa{=xf@}(82sYE96^3O
z!w|PyaQ`yh?r=B4Tm#u)V5o#c`7(ERV6I`<W9WAu_yfE@>>h(DVFj|-ifC`3pL;S|
z4s#eV5~z%ArhGzdZFGWL9Gwb&Mr=h~xs9T|aWA0zz;14A9?Z4CX5MSequGz)Lhg3q
z{c^V#c=&TW*2vZan~;W=U~U6;0(;;`<oglsez-pf{s?d!X;_bY0o@07rx4#kxIGAe
zxR05T9i$9l(_P2tLBuC^QKaFZ_{+;seq}%tJkORe+W;Ma&Um&W?+JNNJd^(52LVG+
z{$;oqX!qK#0?)EP-1dh*xgQ7gr%b{Ycl*E};QciB7)<dO$V!gIL-7cZ0MhZs@uu+*
zWGw=-vDg>7DLEF~#rxI)+Q-p9#ybIB<2`WS8|ViNBwrpMMss9fmeanrn@Zk~4S?|C
z6XKJBsR(aIv~gred^RvQG9=nKz97DY=JLQ?Aog|KtfH)`M!ZVQ_<CSd{3YCPi|>r@
z0rmsi;s@hLXdVyDgS4;h=9Jtg%m77VCZY+^Q!Pt0iMEJ`63u{?D2EpD#)&pGTLflf
zv9IkWwu|>2G$g+;I{_@eL}#EI(35<5q7TiHfmu%b+HNX&Upu_Xz*L6UKQRax5}1V;
zUXQE-7)^d$Vj?glFbgrf9@#WtCiyvud5J~9(f}(Gs}pO14Z!Ba>e$4@R$zN#S7I;l
zYP3h<5O6d)FmZzBWSEl^S@3mnR1hlyzeLL-Cd{ftHs&R5pg7hn>B3CK`oQdyYy|#N
zpizKg+D!yMC6LVl<^d}bhhi&|&0}kmt-v33i<7O~VuZUQ*$(IkSylsX#J*!9>vqwy
zJn!~R788S$F3gm>80O++Bk-33jRF+YZXfsqfh^#YU6S2_UO-=905BLB3XDjON{#`#
z1HFL0zyM${Fci@C<CBw;4=1Msvyx9F=O-5@mjNr2Ym)1d8-Xp!my<h^yOaBp2a<=A
z$C4*K<%PV6m+;aw1&zI?UJI|a*WT;ob@h69y}f?kK(E{z=8g0!y|LZ|+)oBS)tlkX
z_U3vEyd~apZ&i)F%3JSkg1eWzZQf3AkGJ1D=pFHnd#8NUFY=?l=a>0S{APYjzm4C)
z@9cNOeNXUx{QmwRe~3Taukc6v<7(s+{VD!5xWk-N=63Eri~;+i!~8ku!}p;t-WS~l
z{-8fERtB{37sdMfOJl2nL$PN53XaJ~OBVa9-2uSE{yfMq#zjnbnZGpJ8yFTl8l4Jr
zJ+KY@L4P&ES{-W>F=Mi-^`5U?7QWrZ|L*OoW{r|>DIemRV}3<a-Vn~U!}6vm_ki%u
z7x>m_0qAJwHlew@h05D1YqYE+f;Q#53xn@2b_uoC^DPSUYyMZ3Z(VG8Ypvf5zb0>$
z&ELoy3@eoTn!KfSrpntM>!*ARbOY#bx%%*$tWfB8U&fm1S7_Uu{AltW81n0&zjR(E
zMY$P&w&ktDpPgl(|LwHlyQ7c_)+rF$1_?iS<8&kAx|$Nc*OE6*;N|_&Z~4aQw|wLD
zTfS@hE#H9smT#PX%QsHH<r}AVTy?rL`)5*l6Vi^WPM2imjrW~gQEJC`o_A)s3M?g{
zX6rZVTm>E~s}<@xS$$KRvmaCWH|_c@H{U9&r>cLbg0)d2S-oEc?~v6~vVsZ88#QmD
zRJE)YmCJK9TFQH^;LV|ukj=x{Z-NexwO6F%HF@_{EpNIWss0{gX)81&XQ}k4o=rL5
z_sU95u<ra6-(@|e-G^k&^h&yXN?Zo3!&h>h_sZ&pD!)ctk^2v(?K09!Nx62+Rby5C
zsLHSZs_JhtwT)DM&G*Xcd8%eDm~YtBsYgz~VdML&3a&?2aK*VI7bags8X+CZoE|6N
zpL7W6gQQoJavhoP@hbEiJgzlYaILvQuPJlIxgw`S{t)ShNx7QLmFS9sHRTGfDOYe!
zx#IL{GI;$~@K*A7lHaBBZwM<+zacDqFNgGeT?KD|!T*!>LBEBQUF7qt@Gp^8kUmZ~
zg{$x{P@-4i`2|8ftMIo_!X6`7d6&15yTc<%U3L1+Cw<AvBPdtQgEyb;n8F{?CF7NL
zRI^@iB`LoXsOB5>+(#*yO34=Td}mv|l_C5G`85pZbxJ-$dO0P_$n$-yv~Hx3-vESu
zL0|jHe?ir}tCUqX$SIMx=#X%?gsk)-dR^nGFrRN&yOB4mNm+}5#3KIyeN|DyGRd;!
zWnBi6!)z~qV>mV?@?N(mLwJh4Zcnc1^wiHK^epAiQt~a*6yLQn%rNVcq(rYJfwxqx
zwIoRNDqGDelG<H#iG<+Dnu1=POiD^X`G#4qNiijbt4m2~-NBkv!Ag^nl+g6Lr>Y43
z5%kKid`EGmj3!9AoH6v2tQ3Q1?WJu+==WTEa?Z7C1~<{OuTRzUPMhzpja$vxHE*_W
zwSJ{!<>d`hsl&6YzfH<F`TUlqrAR=>Q2s^G2S|5krRNz+{^TjC=O?vX-gO%dG+%u?
zDfv^c(Du`k-&4P#JSpWPZ{w}+O53znXGekdmC^(MG0Ib<<Rv9={}A1D<_IEv^&cfA
z7(3)?{;^tCwT?-QX3UZPd}mHp;$k5gVRwqHIe@maZ24~FR{_6=bx&5i9ukT1kiC;5
zrtrsXS^0gEDZEy`8nQk4QV9GV<k7cOkC7Gp>V%{g{A0p%C4IHbB5Xru5#TGq_mZ_*
zYqG4*S_fpU7QB2xbfEh0;!@UC;a=8N*K+0byIhAlVE;yFAn#21&Gg%qv=!Z~lJGgZ
zSS_n*b}tFj>MN@`i0dWc&9#hc1;cR|&aLF5a$cU~&bdT#2mTK7$em+KE}Y9H7vPZ#
zXRPGHxm<GLbeCL!Z!5gS=yaD{INc?+b}z|={i5UoZhpgXw7fIr$c4R6asi55IG*If
zSt_}3JjsQ#lqIu5a)G#>6<%`Tcv2q_j>B+nB_GYNnAEJ5kazSbFW;*Kt1a>khKi`h
z%2dsitj~rMCHOZPOSp+lqHWrT#N>YOa++218i*!-;k}$h(nwtz=;rI$sjR;bwpI(3
znWQnplC}F8{31@T*NnEtT+n)r?6EvpssE3??}4+a+8$qf?{n_G#^5^l+<VVG<X=qE
zBu$c}Nj1rnG))qcB>9&lsXR%N<awSXO`bPNnk0FWBu$beUrF*j$=8!7NuDIhlf=Eh
zwbnWJ&NcrB(|dh?&Hn5)>+Zj6uf6u(YwxrF1aAx81~vE&iJDeHBn^znsK~SMaAaxZ
zEqI=9=zf8|(WD%4Z4{uo=KL>WMfH?&@nknq-CuS()k8^m-NG={8x;xHw8T6sLQi?&
zN}}D#6YH>g%cS3J3jbGcccSIAP*<ql$>Cj`f2WO)DHZ4A31ukC$DCgYAG?)O-d?5T
z(YIvxa^n@&&x@jy=qh@PL1MTVEhdPmB2O$3%fx!IP3)H-Q=}>D$)++xww3K=w(KGM
z${})u94jZuTsce5lZ)kYxkhf3+vIL}Kps_^s;Mm1NTsV*s-5bnx~N`ifEuPosqt!x
znxXR50<~1FRO{4cwL|Syhg4MaX@*u;OVe6tZL}<{v(`=PqYc*X*T!fQwQ1T+ZLYRR
zTc)knHfUS5UD|%_h%WV1J)}3#o9Qj}Oud7iqxaPN=|lCA`Z#^EK3$)!&)1jeEA+Mc
zCVjiUM?a_^^LRXdkL_vfY3^z5xx&-Q)78`4GsrXCGuku3Gu4ylnd4dLDe$cFtoLm3
z?DXvO9QJ}Y#cO)&d7FAOyluVhz1iL#-oD-;-Vxrh-bvnE?=0^;?_%$A?;7t$?=Fzu
zy52?@wmD*k*YY;=HbyMXn~t$tCwyCi^c?cG@V4@{MQktnxAtZr7WKCDwn06Ze4CL!
zXcW(z>CN(X#GJc&dxCP(a@^3La;fKS?7hNGPkB?(tp&R^Lw}@&Q*DQ|ck<?-3;*|a
z^Y+4W4Dt@e+{Sw*d8T^%A~wpi$g|Yj1F>PA5uBg&4DihK<YP?f>E-F`?d-w6+0)9Q
z2TPRW$@aGK^g*mM<?p?Md_99HK4LXJ9Vut@y~5Lt;v<%cvD2x%ajFpOfU&z!zLY1W
zjTlkr#3euGmBRxs<<<*%iS#4Z4|z4%I}EWQm~J1YsxR`n8>ieG{o}sFy(7J25F3Sc
zH^Dm@v5DR(-qGH1h)wcNMgQrDP4mvcTAhQ~Z0}r*PrmtB%L~0r5L@J3iu^;aVXYT<
zS9oV5w#>VdY6P+6-c`hJ#8!A$d)Ik8AhyQ4-fN@oD!psH8@!v@cO%B#;!Q<t6UN@k
zzMC=a4c-vP-RNEI*^k(IjJ?dWi{no7ZtxsIY+aJ?Cf9cZ`Y%Eq&hee=+2HtkW_#wc
z?`F?*&rHsDi+4NA=??F1&p4bJN$*bYQqM@w7>>K$GnDEVDZ<ivmoZh_ygS(!<9YXb
zx-rdLy*oUe5ko)k9xu_d*L%Qwm{UIJ-R(W%C0Y)7kD@=(a@c#!C%vl?i~2P5#gu*E
z^LY1r7dgI|Hc@)S8^yGV(xVuAgLhgY?!-jgF%;K(6k{W$KI!xMYT|53`ciy;Ux;MG
zXZSq6R4-EMtLZZ_E>enqDHt~ku~hW8yloIOIc^K`_0Gez)5sU={;0PuaJoLzYjE6<
zuP)Brq|frzLurp9X8Rg=TX+s3R@c|a*VMBYvBth;-nyP0h^6_`eHot3h&5;5b=Vdb
zdX{*Wc~&B}9D5jSXNax#6!=1(1w^xFE44GC*|Xm>%`<~a<T>D(=$V3;$8*HH-!q=d
zi#^gV&nV&s_D)+p!<bi^4?F`9JBF=)HO`xflPH&-E?f(Kl#Pyv9q@WkHrgS!&s)>e
z!qW<|JzmX|=1E6v7xsR2J&i~<uqQM;7T0eI)_zT{eM66WG?oopKcpXJ*{G}U)eo>-
z)zf$AyAf;PP185)+YnoYea{?yqth1jnHsg<mE0OOIWmc<uSIN&BUy;;M!Hb4n5z90
z!j-GV+{*T$WTAXec}aGBsZJd^ajEvn->F|mCeg2lBkk-v#yj5iT}v{_vSE9P_f)$q
z?Oeau{<(flYX697C{<2e1Eu4B?<h|Bu+yucRPDn)X8_d^$(*+rQ^kE2$EBQWy7}hB
zWs>^4xLo;=<Gy;n#?(tA)&Ns(#xj|LR5f6kw2&KzeDxfu^DOl&ccjj<0O!aY*K>qr
z63c_Ka|kpiT~X85RM?_{NJAH<1dicvpQtIEmtKG2HDlEeC5~Rq<~1tb-xrPHj0zsd
zR)MoL^3^=-`#$YGmubARm_}i=<}qHc;(e5T$VIgBhIzh7?i+bm=0tM$^`rF|-@|lQ
zrDqE5Cd1SbSD$$Ap}7(79UGucMffz~I4g=^__gXy5Y>89YMw6IqaeID#Qu)HXVZ$Z
z_Ib=t)DkYwp<ML#wA&YXjk9*oS=#gHvYf)GZ#_8k)4IlJefj}fs}|$QU8WuT8<&gr
zil!Y;V|+QyHMzWt`9=>PrL4x$oJ{rOnb}6(+dkNJU(W6bwF{W4t9j3OSUtrnG&sN4
zXK7eR`uptOMmal$bJ$&H_Xm;MQQFPK6WYD5UCrs-!Qszw)A<93zlu}HWS2~Gp;Zuh
znd{Pk)1f(TUrIrr#H&HysIPd}D$T#A5l^()w5w4JP)*o9m3E1$*D!qb7_GtN)2>5#
z$?+rTKAhd}CU?ELHWAb37dSDNWS6bv!u6i7nz4Hm<~)Y?yc&C#a5bCp2RY@fobrCG
zN1rwb;f1m3j9<-oKMu12@i3hQ@l2tV5ns(XmPOk{^JdRkZjJ^~NPN@B#?Gd70;(6S
zEAdLyR9?itrMbIUs%R~014%M$lpk@eeNIvreTmi*7;nsypRb4;jp<v2b_equXcn&R
zqmYP`dr$37#Ltd?iLkZ$k!$cydi`F{M*JJ5^K06Xtv|`T`193d=FA_sq#q*v!)R4T
zJ4So1J%8j~y2tc~C>`3>tB;^vy-4SKM1!^tW8Kg7n6GGk?hCB|X}&*7_t(r3v?Dl|
zaQPj{iF(X+N2ykIG+L|f#P}arqN<ax_P@01qkZm%{0HJc(!5`fkc*zp{JfFY<g|rE
zt#&rYTBy<4ow>AsT#e(n!zr#@#A`Wqn1)_Dt@RFK_xJcb({T<tfnCPX%ByO?>)(UK
z{{WpM`JCNpXY|G7E^nY!OgWR!dF*#7q>wX-^UACLz_2f;e-p=Y(*KIwH9FaLC%dd7
z7x@GAGb)EtR`=1DCB)HJZKpF&YKfaZ#l2VyQeSlJ5XO3tSF?7q?;uX+F>*mpBDb}t
zNS^hkv~Hx0W}bA@=mgb7MW^dJ(mK6-fp@v~rtq>GpAtC4CGAEfmFI97Cvq7la#=p5
zav>!A1@!~xOL70HXixM<wD(_KODDb55}i(E_19LB<j{8>Pd>?#7*F*pUM4v?HcDaN
za_kVb#ONk!?*P=^k699X+Sqz((XfVE^f5~uqLB0*4}jc7I=REE)Y8QiYUz+mZCr3m
z6f3D+%Wl-JF|{<#g}y8uBA%f8gPi6+I88dswT#-h{1>%x#II(Y&VhBN){WG@!T4&*
zo!Ygyid<srNdn;uYSGcRsYS=~sO|i`m~w<`s6`|F=o_m~EjsoF`9?SKH!Gla8vT~=
z*rU{<V~-M7A%oY_GRPOMA(z-2)QX`mwc?+56CWU#+A?y0+#}SMk)A(sT-uR+l-e?u
z`UNgEe^sN_Ay)GDnZA5};vdwO;a>VOiD9TuzKZwh2Y8?UWmI3X8;1vK*Qz$9@0(6v
zW~$LGg4i>##D3{@UeKizHkv?91f+!%N&xFji`MJ}468k)_C2)Hmvp!D-NsOU=j2}Z
zmgiB%QsXV7z<Ara={cYRT0rL;Y3UYP_eNyC@p(kx_k82?(}7&R@%g2|T)y%7{lKcg
zM}c*Lj|2Y-><xSq_#tp8@NZL^%G6A+d8K)i*~7fq9BMvbK59O0&Ng2$-{f1MSHy3*
zckhD!E?6g6KiDAHD0nfyz|ucBz<GrwI5>D$aA@$J;C;c7!3XJXX1W(YI6wTC@Us@s
zDyG;|svRaah|OY~*eUji{o;@~Dv41Zw5hH&TwB!5LR$}QV;3*_yP0drv~X=Jv~68`
zg=;&Y?VR+#OF6bj5gVs3PFHW2j`;t$?T2=-`+r!H9pT#1t{vxEN^c_CDQI)i=AoU9
zcCPDAc`ZP@IO%^u5xb&@O)Y`1aoShAcAaZCx|Y(};_|11TbAwae>W|xL(&wTd)h9F
z^#=DvXt*eP4BYp=#UXOXHcFbuv?!m&WA~06avST!+c@qvcJC5v&9FDaRs4O8@Xik8
zF!wRs$8ZX}PjPTcUj&?V7(U`a4)X~6{*m)q!!7})a~r##PcJ@;^P_Y+W~D=0jK5B@
z`&pdMSsbe)hwm8WFQ-glfZfNqzLY{2PMLcF$b_E7dI1T#v!YISL_-a$z*-Hptaa9Y
zsLQM9mr?tX?Mk(m!#J1-Q*b_z2eV-=EP%zZ99F{y*aACY5A26Sa1=Wmk4P1UutYu4
zSTqwYL@Uu&Tp>D$&Z3LxA$p5`Vz3w{Mu^d3oR}!4h+L5;W{bIEfmkdG#0s%mtP>l>
z7O`FI5_`n~aabIa5~s{HCEY-qFXkbf$#9-nm~fdSrXn0KaPBRpis`P4CZ=Op3ZcX_
zF+<Ekm+|N`6GJF57TqSJ%Ty;6#_1+-<|lFl&hSJhk%O?Mz?rsaC)y)yDq6A&&hSKC
z(Ue`9BlL^92>Xgb2nUIw3A~-?i?9u+*^BYyFhdz1%I<?W%plIUFX!7=bmCa;8Mb5E
z+AwrzXr7?68;9>k;bA(5??mBY5{GZk;oEWec1&{{8X?ecAH&@Ycd$E`6gDwjPr2ZH
zlJaWG_%en|5H^Q}$hGE>1s%~v6OEw_YCFy1?Gk4!B+DcCJ#&6_pKgX^m)`8sl;(Fl
zesLR8pE$EQl6{R{J;iw(`*M5I&UVfTv2S%w=L`OB#wm-MB>OtwVJvk1D(JLzjlQyK
zey3G2PVbiD9E4Nmw&nFP{uSr4f+@-2@M}2yx9qZkeH$~}!jNy|)>|_^hvB<!E||OL
zb#^%h5bv3^I|x>@oiZYHZeFGvwkNuwrct{!Y8$2zHY_7zq**mAzZI}dD`?SPm~%=R
zwG$(AeB}Ls$69BkrBRkf*dpU=ut)IbV9($!!Cu_r1$eNBIMZruHL=pHvs}ukj#j#q
z(T<G9hG7H^+h{@Wau_!m-Hh%=594N|r*VtX%ed9(ZQN$`v1(eit&o*&Wm=b6ovrJv
zZ0mX}$GXAlV%=zUwQjPyS#+B0yb|>f(mqi0sFD&n_hyrRy(6hiWpVr0Twdz`n}P>2
zade{F!TVd2u>XI;nhI&wH0v#B#<zoK)6LFw-VK1xyFrM~yFoL$>t6M(GOH>SZV=j`
zXzxcm3M8HRQ*=7@#BiFLP==jcj{oVf(?G}nI^#1E?nTR!j(T1fHa$>F>*wNwQ5zfK
z;-k@ybMc92r?_}-5j@YuXQQ3#;tS9&cJTtVD_ndv+I23z5$zV#q6puGcCYJx0PSIU
zjBq6#H|2A~6J8UoiPm<1H&AIR-NiFhYn91ZmTG{oBjeesE5e?I`Kmr{cuHr08WPV-
z4Ob%>AA@$h8)lN4s;0a6OqH+Zx%fh~OI&;z+LbQ82JLzm--LFni|;_YTkT`~Alf6Y
zdsKGOG{;>_aojY&6Q1!9+PY{Pxxbrg&9#;;-bQPuwP&o8mV>Yx<Gr-L2nQABs||I-
zQ#$u+qvCmKW3>s4PnKP{2bz!b$wBZiLJw+HBKCV2g0MNSAs$lBPT=VbY2RQ5@51F3
zUNv8hON=Z27_GJlTDwH|9ClgAF0=}KltPLJD6U9XcQPK~eHx#zZmh>=kDfmg4W4&!
zoD$v}Xl&Mx(mI8<lUMQnO{+ipxx4};Xg{qcVq3_a?%eSDXb!ACiQ#Nk{Ya}GY7ecw
zqVG2JZRq;aYHU7H==qKyhS@^yM3rX8>NEVFTxhne*|aW+a68Sh<)@g=U|Ls&S7i-M
zp`C2OzDSQ}2JMjad`D1!pZ1t}eo_Y+U(C55<lMK=Y7}upH;H2y`U`f+VV8vjiDSNN
zi5sYwTuzX<;oHQTN;BeyX901;SBJRa*-W|X?TH(DdrIH?7;(e*8kJZ3nYf|1<=sK&
zQrXdW8@unM**oRyTg$nh%bdKG_@M75J|LttZzVqHyNM479X_O?4)F@{K_5XO;Z;!$
z(`iZE&`nxZ@l7T^_|_7{9FYUQFNp)ly?Im?!jXn8Jj%D{_cmI&BVw-mdP!FRezByn
zwG!tBts-k8AHpS(t&y#8DbFURS&MNrc@xJG+F>apT_OW{gdK|`EbWUOmXzKp++TeP
zl(dF!KzkfJRI+6Kt;v|)6dWg;mXW>&!%<hW0P7CM{bFUU2yM>1Plq%yg2TjL1$m3-
zeS+WK0UF<>iPo+%D=HMO0opXQ>1Z=R%GPX?!zkA}zcWFTS!LLc<@lctn~k=si}y^p
z`@q0j$wbZ$f-xuy^O4&J(L~{((9ovPFG25}Z-Z@ECEI9r%s9@FaVF)%`7@a<Xty)A
zi&I$0W-A=w|GR0f1~bs?K|3Gqe*U!-UB{u>j&=dYBz!NdK-aA}qL3Mbb|qtz&~+`g
z4l-kL&QAZA)64@$qTC9PN^43Pn;<blanGif&>D+O<FgMdW9!j{`#tQ1Y3*e(t$N4y
z@u`q0?91Q7AeY?LCcY;si{h#kghMWUC&2KXctxAOt3Acv)pBWdn>Ai9WQYl_#yb@y
zf133=q+4&G{C8rF_j+yx^bQlijVMvm%e1l_|FW#AP`H_B^U=;jyRh8wLM|!QYGwGH
z4y&W}Bz`YTxEG}{1^eBW*fS1=$tX!{VGl|=z3<jl^hDc73=l)aa4}Mh5#te?<gU?-
z;nkRIgxP4Eb(m~gui=%Q=@@IK$UvBZCZA(xaEz(W`VNLL5t?WypFa4X^NFVnhsAg}
zjIg!H6j}JcBc|RJedCmjge{!fUTlGJBON~|5M!VKA?4%4|I_Igr`!j9^F$xWL+HfL
z!<6t>BJOC6I~w66%#Hr{B#6E}DQD=76!u1#fuZPsCc$#sV7%R7E7Mxjmv8Nk*w?(H
znD9qQyK^<eH?Z#!GF{O<KMVMrQAg;3ttJ$s`_uYR3R2OFbDo;~y>=VDL8EU|SE75a
z+`+4wbR$zb=|6IRjPA_oOkdx{ceKwOWBq}{H{tLb&}BS*5%kO;dOQQ@i#57@z%Jjj
z3$3SgWje2Cnr+$ztrakQo~i9f)OswY=L@Fi3zwb+T#9B$e=1ReVgA6rPVO_=w>GUM
zF%8c#4R;X@=$p?j-?Ph54%yP}F*InNm?OX8j;Gf}nnuos9PTklQy11c>?Hxm)T*+g
zLg7ZEMSVj|L_4Jd;ZY|Md1cty<@lctI~NrHUy$Us7;Qmu9`LJxJ+KAzgTbgnj=+{O
zt^%!LP3iL_9AzB5FMX$`udDhu4BOLg5PhtmdpeceA8#=-jlV}5y!xIBjd(nnPOBuW
zLjlXh4J;QovVQfkwI5y6B54@5JAl5X%B-wVxb<i^q1}ph2PmA4kd6CmMZ)WJr<s1R
z411&;|I=Zk;KBc71>H6lclTi1_xOvI@l4d|`=MOSM*U_x?|^EJeg1Iln-_}pVxLTr
zO=Wx8SB{ml<Z`)99#xiVrMjqLYKmH*)~UUkPfOFXKxzZDA=+?lB%3kXcx{q4mGSA?
zNc44Fda{{{ZZoxf#^-50(YFuB&SW#yjZgR_Efam|cY}m+QYLJO*1+|Z3FG(@HeHiW
zzG_$8XdTIyu?)4#iK|w}jT4u#>1wqbcW&HhH8oS~%J^Y57k#m`YGT}A%Gu~kSWh((
zeS2zs)Zn<m(q(8v7%xzR(YLFXr8>tAr<~1LPt_THv$T$?MZ)B&JoF`Ov}%FAt+h;L
z#En){6<}I~HBbinrfV7UP~4~%6q>Os<RSD;)6(VUxZ#vD7@I3Mqpz(F%cXLu)_|a@
z$Ds-HNYscmQ*Dtm<P6OwsA$t%O~T|JIRm8Hu1Pscj?#Pt<xZsQ0AXsPq}9ePYM1OK
zdtv$r<tlYRZRFpBWiN`WM$2{>q8*!2YMjbrY_e>JzUx$P*$BfoV$)0Y!_b5cm5tE1
zK&_CPTJ2VUJCw_HjO9p;UaeBI#cov~c9X$Wx~K(=wG_MQ9Wpgntce@hT((4C!a@T3
z2jULuORiC~We$cW{0My)Q&Ug}Nf<c+<K{BH6}2O&Mx(ZrFj$_67@n|PF@$}y3ytg~
zLuwr3sH36pVAjf9Bb$pOsx9NFqoMB=td+S&`o&h&fpOH)(6<$7WpSfYQ7$aT>LHX#
zx)>U<Nz6od!qP}PV=XLU#1b(^&SK0*+8JwM2_yH2K5{JMdr3QEEv(S&!hT~FW9#?}
zK?UYOvBeb~cT`W>fulW4=i{~Q+AHy~Mz2p=H1dQ_y65w4oy&MXNiEjhQhBASckFtE
z^LUkLIK((S-Br1g?vhlW@G4-0QyY$2n$SmUjj`9foKIz$@<9$sH#!fNi`aJp`ZlFC
z8uWdWeQ#plBb+a4j-GpYWor`8+g9@ZrW1)y&x>j#!o|FHXv#k9o65d)9ydbTmbV(s
z<h+*<$Gp{OeG&0m2piGqdCzkG@@2}wd@^q$yPwT*X*KanI)jL`J;Z5tqc3rMLhcpb
z?bD6cy_B=V>R~zoi5#O7@GJRjTw@;7S8>Sw6j%L=_TFe8@(ePcI3T9TxwOxXZphX~
z6K$Bz!?d5x4TB}so?-VU`cZ_}@=9tG-Whl;X$X3C-kaB(*8j9)Jd15Wd7(R<#ydt~
zv=4ay<kh4<$Yt!?iPudJ^FAn(c2Z&4$-O!6$l6bQ&^r-T!c>yE`Wm@Y`pD~hnM-sh
z@g9zqN3x{n(F&y|d1comclT>ghM0E3-1jX=KS7hFx$k$8CRh)s&3Xq^nUxg^Hw5i)
zv?I}u0p%UfHtw$#2`{{p%CJ+*@jo4QI_UUcXMARoJI*b<^NN-4BAfwFgnU?zebqsc
zD$+zd(F66A$zrZpDYl8j(l49IEF4uv$f<I^TrGE?u41a@s)OpIMqzKhP_4z0KdM<c
z7I)J6;pjd?Tdb|u_UKZttGCj#^+EbLeWt!t--vpg)VJ%qX#YN%!}>A)&jx+====3U
z`ermoJ;49jpwB-2puWsCM-tdF^r5t7yXHUw!x@9VP2Z_caLt|sHUWJ$>09+7u34YJ
za0Jm;>+AF`u34PGP$KpD`XarJYi1;{Hs~``&(|BcW?lkA4NA||C+Z&8<Rvf<`b^L#
zYx^9dPm5z3ac7LSSKH_qePkTdHloj9eVDe?G5Ux&rlAI*_tgiX-p5Ao700xh=+jlp
z)5dAz^qy$@5at;4>8y>_25E!zE@(Rt<{0#8q#Z<^D_d`hwmD&rK_6S&qP5am=?&1D
zggFL%QZ>I;SEsXdb#;rNW6(!ahc&6Euo@99)F)BzIjk*Kd$5PvgK!r?$Dq$1ZH8K}
z?N{p&t|jOg^x2Bq-eT7rNMJZm(^hNi)C|XHjpLX?4N6<8#>9=bybwp9d8qTaM$0e6
z(I;1RiW_ZWA�rhBj7ZI7XWg#}sK0R-r+SHGzYa(L$rOEyU4hBY*4MC3k7<<N^Bc
z7}7UU*UOM=<yx&Z>X~cf2IK6IyX8XH>`Pz^(PuBFk?Wen2@Ge~*nb~l{gKSJ1UAY|
zt&eN=C9po|vkTMf;F<#otONRN!<kES*KAH;&CzF#TrW-6Y)W9LLCF<zwK(b+SrEs>
zQRG_})ckgc9jb@eA(s>881!i`wu{wbwdy2R%Y4EdgFX#pXE9&QS7~CtoJg2s(8oX>
zbgG!DEHPCMCCo8M!2mH>j8K{wAx6mI1RaAuy+w}bB@c*R2zwB8442d|vgA&Yg|Hn#
z$Dq%8aac5yn?y5&X#^dEKCQ%B;df1^1m;JdMzU#KhZJLyG)jpa+7>s`F2vEt11sZ3
zLLm-P9E7=XgIae2$I)}L*bb8&BX-3xG!ljv8nGzp*C~DFP1YjC`=mL_*J($R+(2I<
z-4%=1#Z`ze6m+ZmISSKJKHjxtE6f*X0Ccx_ds!FpWu%Fy$H*7%5HDkx9NN9E)nS(p
zc}M>-MK=z7NiO0^Np}!j!CxhV<f2bi|4SMfr~eY^bXrf2`!mOViM6?(1--8jC2Cb0
zH?IfK<tL4Fq8WTLW;45wCK^-?(n;laT&^y(^BU)sdpH)oRB?bbBjsZq?Pb!-<U6z)
zh}6>SAa6QvMUW09qa4>uzN)r9ka4<ieTVuM@orr9!F=P!g>)|!a%=(Of7R|LU0c7L
zcK4GGh^4*|@i3i^Qa2DkwNA{*4a7;glyjNO^mJj`26M^{Ip6b`lFhVdT;0j5mjB{c
z1nwkC_-$_ww5B!#dhs1Otf^(Qrj|pR8sBaJ&=mlAR#jG2D4dP90opXQ={WXeuoXqZ
zX?p82Y-TzBr^9A}j{kMWJ0`hjqb<(IM$jI5!$_D03ve#C6OM_HXdya^zGAePE*6P(
zIPV5&%a*dU93aQaJh?<}kb9M;>Z#T$2Wx)3nuR^%GPM%T8XQSCsjZB!R67*S*EjO&
z%NDgA^|-x^A8^)U)J`=S%^tO19a2XL*Ff_q>`5@4;b_*YgX##TLildAPYp+(U8)D0
zy=Yf6b^vprceuByc5HT{9n07rOq13kHmNi=ThZ=dj8aSE6^>Lk+tH3-jA%?npUv_h
z8MO`Ve8v{3rSc%rhNCJPwH|F2V+++1xrJ6W<Z?1<1=?netyXz*Ir=P;`DD}_w0_3s
ztFba4eP+_!QBG9(2oEzhPf2V+Qsv5_WH5!HI8qQcTXmL0(Py&kN=8jX>t}3+sw=yq
z&v@CEjGBaSE@M-bE!)!Sg&IfeFKQyfZH!Hkdw4Bo6jI`oJ~b5KaK`S(QQL<;9n}!A
zU+h=I#eO-Lv5|7I*pEIPR6nsvY{F4>lbp<0Z#hHIUfBXspmNYQ5(PL8(ywlEj3~f3
zSz?yzh}I`&;W#)8u}s-dpzMh8V!UdFwyhYC;~@S*3OkAM7^kTiteT^3DF)*>I2hqd
znIQ(#7>%PU8XTi@#B#>cab(OPO-ZySqv|2dXRNUdiPq@j7xfZmB0&`r$3#8!k+hx1
zF-RZ5n#vTk76q_3ZbVmt$|Kg`e~GfNA#Oxlf^rS^rW?>_9W03((TJejh;z~<=(8$m
zHD(sWIdVR)#f(id`w61Xbrk51{{cy66G52=J7B<R996H<Mkhwnx`c~f^kqQ2OkW0$
zO`+9=V~6OQz_A51r;ol(^KZzY(Jl5ht?0l*6y~R%v~qKNt8<2lPVmIu;MsXEn#YSq
zw2C9rY5fL6zD%c!oU>MZ6Jo&erS%(FL+dwU3a#H9zlB1=7c@SiOE%rLL_42kT^@Zd
zBl<Bl%rTlu<BoHtN_L}l8hH<`)1Z4d&V^2cEu*y=`6=;AeoE^ch||4V-S}q1e-H<v
zvnjm1%vqJ;JE3~fdd%_n_yiU3J$FZGCFA&9DsOZXt;fXH(|XKtgY}Syn1=xh6V0Sp
zvDSPFDnc|P$DZPHJ;3L#*6^t^I+c~-`aVo$B;VNA<Q~f-E*;;>={)M3=;CiR*YN7d
zt9<6HFW-)L4ZG*EON8IO$mRM<Wy*6Yedm-ImXTZ@qScq<KRD;Nh?1XrQrR)Qb54tS
zNb4@K)*SvQ*ZWagcR{KeknAB;=teR?d#LhQj-H`Ak`lXsYJqOlHVmj{m_`t)8)3tS
z8pat$L#S<>X*9-=X+|1Y#<|A%5HT(=E`)l<MMi6AXk22ng)@yz<1%PMyN}^4;~JwA
zoNaVAu7h)o9HS4MiyFj3kZC=P8pMr}Bave;FcP(O7{VIF{ruH(G{f~wC+!}~<{O;0
zBq%L?ztSVtBamY~W<3Tsuy)dgwUd#NBbdXe|JE`JYV~apTM3rPPLxtFt(07vod25A
zNC^KzbWrVPa_wHmwcCzsw;$6qfN8p`7;mX}vJjgk>Wa{RnXF3){4#WK-kF^Dl`e;z
zop|wY!)XbQNyrDf^N@Ho^S`ohD2;LjbI>f|`WEgD5Wg1M1>`f&CCvLT<vPL$K^d7H
znagsr8|c<k>W3`Y`hTx)KC!f-m!R(zZ4qAuw#fOdmp(ncbP+Doxj+Fn;<HiPw|?ud
z%j&OB;2rgT%YJ>m-w9>Vc)fBtEM*yRbktv4DV+OC6{G{*TJ5z4S;MUduuVLQErM?C
zr4_Wht$VD;tqDM@YniUi!jfj9r8C}Hm`5h)INxiHCNl}PrZcMuv!QEzHi^*T6V*M4
zZy~XtS<o!!QNAy!FMThM4HERuV+OzdmkI_#x)qg5Mf>cP^|bY@mCx~OVhL*E{J@6z
zd^8ek&+tzSoiVGoJ7#4;C=o7b_>F)OGU^z0jYdWjBg1HATx_&4E;ZU2zcV@-*BaTz
z^~UW+-w54KoysQ*2N{EnyNn@bAM<vzuX%^r-yA^SgPpSl<_G3(K3nh+wCA%0**yAO
z0ljzz<Luo2b0u@e)G_BlC{crrA)tae!S3MUQwBBNoU=IRPr=}v&%~V9z`5McsI*SW
zf9brj)U?+$QR*3$=J&0}6UG$dNn@(<l#y#pH)in}&Tybk;EX`MK>a|2z^8%Df&UHs
zBXA_}Q{ZUeXS0r3*F3|lZ#Fc~G#i^u%rvv9dA8ZiJjZOFTwmsc<|uQtImMi6K4m^*
zPB-5+mznRF%guMqpUmTCEObezZRpZaX6Ule6``z9r_gnw>q9xAuA!Sk-9xv8ZVko4
z5Efw-*2CVgFI+905>5@*2-ghP3LBC4BA-P59{D=5hjug;=MQtH7hI9VnZH!NPD<rF
zwvXV&oX4OO^2n=n9v-8=(I4ym9^)PmoS)?UOwO+f=SR1}>*fRI2=n*mNb6%))_W)A
z`)s9ay@s*F_`=v}d}-`9_8R*GuLl+f-Uz%ISQ>b%e2F`uoy|P0vaSMGaSPv!E!>EF
zh;94K5?k0Wk!#Vm_1yoLZL4I?bUQ)rXH~j3N=mn|Rh^jn^QS5GvfI$?)7*wi=A582
z2hbjzl{SDE==+%Qv9TR-><yCJUGS0MY&er!-&NfDuHzGQv>Ft&QmtB+VTCQrs%JH{
znp+vxg;p!;Vymsy&br*nvaYr|SUs$p?dqJT>E`L|GS9DYPDoqemB1qAQ04L@?siJz
z?u(VKLt)%)j9{+RF(w<6vE@!Po<`SajAuX@e>P@di_SBi!yfc`;{`}DUN+`ojm$UZ
zLoH*0u^9Zu65~w>n@^fgLd2YA=7Md`FlWFS=CkH=P|rMK9)X7DQS%ryGNWb`ngk(O
z4bp<ugEgQ<uvV}ZTo9}sj6loa1;JKuY4FETYq&h}Ze#^K8d({6A0CT*7TE%iN47<F
z!5<QRROh5V>i>S3CG0t&rOv5ziGK~{#CkCYns)<mE$_wp%}T1}|NCVYZXFBOE&*Pu
zbWhm~OFYB)i!sxfZM<N-YAiHfH{QgO<YEb)Lz;g!kC{=VR|K`79`pu%NOfwk22x!+
zXas}7P|ylSknWbj3xlnY=9Nq<&bk6BfU*~OKd=_(F3FU3W=iK)no`Yp+L(vjeYVWh
z`*7+nS332Ye0R!#`0R%7PZ?$mH|{qcFzD1!HS0U;C+lY`8W9ma;*IzsDcs81@tGoe
zm41%X7gs9R87F8Vvy6P>MPrWfk}=nK#dyOV!*(0{jf2Jy#v$WK00Mmiw+99U1_lNN
z?hM=&7!tTQFg$Qy;QqjKfmwm)11|*f126Ju_jX{JtHJy;up{uLtHm4-L<2F@Wa1jk
z+2(oXMP_UBVzZ5TDQhwPQMLw|Lr{x(m~|M^VE%0W#hhh6Z@y|SBpoK060CWG7USqJ
zaSdj0=&sO^(A}Y-p?gCQg~o)&h8_=12u%!4M$IO!(bNbB!ga!R!)Ju+g&T&?3ZEBl
z5k5bh5xy{dN%+ceR`{xL`|$6=*M)BicMEq9_Xyt-zCC<rcyRcx@R0C5$aOD{kyl{-
zX9c=|KhPCN^M*KHZo>Ap+58GJc+|XtM@>2bEFxzl%ZM1sGBWSC+WJLmi`vcs>!@|i
zibWuzBA!UK6YGOci=I?{q_{f!8K|$*%|>Z~^Z>0$dfc{poZ4z)?Zb3)Jeizo1kVjN
z51t>)D4`d?`3ufjZU6}07`zE&ushCQbe_L>xQ7UFpG0deS-*Jhf^Yt!k~^>I(76yF
zt;NwTQ<mSVO*cuQn>5b1Xzr}VZ`kCxw4PMcU7ymB+M7|wq_uQuzG<$&5a9HDtT#KW
zTPK7vF19Y@b;7#5az(t)Kzi#!8xBuz2#VSyA0DKrJI3=PHBQVl<08&yV36*$k|>J-
zrpV$Pozb0M{u2hR=y~WKPiv#~cWaaNse7+jW2UPxq;m3b<Iov}jTjb+rTS_jgifg<
zU+V`O@EOd%fo5&C{(;iG!}=O(m5|S?CFG+xCU8uhV^%Mg=fXrugt@1f?`ws=!8&fP
z4Y+n3|3%ElA&F3$c^<acOTxFaPDF1h(MsRcBBB3dtK-FJ)UdP`@~{O<sYB)K3E3#*
zXIv_L+^bS=`iH>8z!QNfrKGXAj5K<p*5mZ$FSxz<Ke_+@p89U?ovCk5?wLR1p81O+
zJ@a|k3lDUA-#=rI`?~oC&+?<x>!OadIrt4~bEzRKbZ)4P+Y4XE{cf+&oo?SdhI`v5
zLV2OrLfb<>kgQ`LdkOZZw}+n#zZ6~=elz?<_+R0l!bh!Ji%G{D37*zA`W3xDH+V7K
zT8rc0`_?M!18X(MCW);J@mcN?=1Ryi_<tQM%(ZhI$BbJ-latywzmf@Wa%-)Pb$yFf
z!^*Vy+`2KWSh%Gng$oWS7VfPQ(;LckHgjog%pnU(35l*)OP}J%d4yJJN{IP(DKyi1
zHpu|iKiA$*!4$3$tPf75dAX@5(insE9-l^BH&>gVam@5`V@iri{}XX4LbDU&19Ni;
zF_x8DN?$U65<TgOvEM0`yIzd_&%jR9Nsgn$LkV%0mzuMVF$?2K4DayNk=%F7<Y-Nl
z<;Ez-D8=qwgclc);}h$rtkj&_SXM)vie^bvtSFV!I<}=IftD`6DPDR~y!T43Ri@p!
z$C~4oQ0|o_Qi`*UAmy5gJrngxC-z9x<Mrb{@1A(ChrJW^P1G}O<(_F5_DoUki>M!>
zK8SjtMZv{IdZA0*-e*Xn*Lf$jk$N8PU5b`-Wr^h+%Cwf%eu|d*{W43f#rxb6YG_rd
z@};3ve;N2WAzkU^#FB1q3U%6g;T|RA^+Bn5dASvBp;m-#=(<Y9)vz64E8vz_l+F)I
z<}b%9ozB&8GJRUnRQ{*bR$sKwxUN#My~#a>Tk6)_PUCUcln}Rgp7Ak5LaTCP7tPa&
zOJ7cDv~0(>sA(97V$c~?PYGJ{$JP#<JM6S}f^F@x_COufD^Mjn!8SlWwgYsAF2(K;
zDSBIV0roAcVI6FQEwCMS!Cp83hv69JO*d~z^j(pFeAf@gS&VQ2nqLaeMkC#GM-_$c
z4rlje9)5vGO`{tOHNU!#UuC(EP9AG*7-sV;E87{4OuVMzqt`z?Uunx2PUCafpL1L~
zN0UQ0b7|jd&&J<Hab848ehWq0La%Xa9q2s@y)~bxp2O$1-=)_xJg;jH6w@_6EVaij
z8ggwZV?y!P`%xLajAlF$Sca|erwYe&dQ}<t(kyADDk+X5;~s1+DX2BpL!Gflg>!Sp
zDiH`(G%p?%RjDK5x-xhnj435(4(m$oL4=WC!WdFg_`)$nVef%`M};YK`dEoQ&d(K&
z6X#iz5_q<*RGvBEi|U0X=P<y{;erbDD_M_}m`8F?`Ef~kaES~1))RUBahW`pI7*i^
zMt=;YjYp-AVIP;luTTl4FFAZarYcw>zsksgzh)NIA=j5JUo^6sQ%b1G^<_%_izSr(
zlM3*wXf7MdlE@OvvjNJ|utngiO6F21Whcta-^%2h&Kk*!Nj+h+a^gC5<Z*Op)c@oC
zO~whbT~f?sot?PSzrs0^94U%jqR#%e3b%^N#QNV7=c^^t$Gu|E`Q~tt-^ZiZ2IzZa
zlV51J9o;UQY5A<`a3#`J6RxK9L-?H)utIQ+6|v5M>#X`#1L$HkvKm2G>ul>>xXC)t
zIv;vk7g#OfR_h|GHQZ*ku`Yqz=_Y%)!@9z{68c+LS?yt<^*gIO+{vp&qasl|1s<_e
z?Es&9))F_&K7=#5hpnf;;yr$}VrfOXL~e|9jocLJ9=SQvGjdC$PvrK<9g%*KfssLx
zJ0pW5Ln1>X_e6$89*B(Ko9Ag&><}ChesES%e&eB!c}F}WUO7AhSHeglH~xRXA(D#m
z;M`8@NCkZxt>7wsMfYDsj@#ACtc&8iRW+7xlx1%D17Jj=<yRejWzmo<7k{rZ8fe~j
z2!z;7FTg_DX_mdqjVn?1NCKO&1g5hDHfITJ!4h~mOJIAJz>X||omc`pvjpa_1m46F
z*qtS?2TS0sEP;Jk0{gNA_G1Ygz!Er!C2%lH;1HI;hgky0u>?N(|3Mr3Gfr!!xpoHH
zS?>SSW#_p6=O?)>O2U_(=KSJzIoef8zt<-H-%!NH%RQ@#c`&0C9&G*(mb;>M+ey$;
z$j4kUN{mG_K};6YoOigy9CVw3cD`67mWt(K6=E~QT6EvQew)$Vd8=<}{Ix!@RC;8p
zG|>Mj`Yw`I++g@ovYu>=u$gQjTgkR!g1ka@ke%^2y}d%G?<sa~*$-)$j4p#Q1;Xeh
zmeJ@p4)KYEi8=i8%0!tf^U!y;oGUiV1#%d=FO~)9YRM@WHdp2%9di&a!qiqEg|pBu
z!ZIF3dJf6eavjnTzmI4y{leet#2&d$9uV`<{jfZyr1BxXNS|z>Y9cmFmG-7{rQUG{
ze!Cg?y=J~`oZvEseCMqoT^#6+WW<NDdpCwYb~(g2e-jq@nDQ3#Md+kcm+?i6-_MZu
z4@v%(&S#|gq%`7^-8T?zPHJ>s9phfczI?|o-3o{}pS_?PXINIr{RPJPBtN}YjBqkR
zdQlXipTigo`HZ?l58WMukY8C5Qz$R7mveN=(vIN*hASEF<+x*rX1CORh+5(g#$s+r
z=e1Klp`ltb<kM^FS@!*u&-~MxafZ5$Pq2T$DgT3gFC$+`I|ef3U)h&ABl~lh*LhSO
zgm5MASvt3jkvq${%4mN|<9F5Q1?OTpQj1ul1h>js3vIpAkWO-XjnOt^+YCm+7_{TD
zMNLIG9;U-gwD~X(-526-y31lFEQ6KU{#L?z*aTZ)2fxIy4-R6?BN#4<?rUI;&|s!W
zac`YSyuF_MmimdWsMCuF2wO8Gd2UKC$3ZQ}g>RPtz9|X#1-+*1-qdyH^GVJNy!>W5
z#0D`O&LO*UI;+@)Z@7r@{u)jnVm62A#E?%WMGrDe1?T+`1?_m}j|X*`^Nov9*ErX@
z5P$o5e@e)G2d$TJJMU95+&9l|w0Z!QVicB}&Y_M?!Y80+I-Ge;oF2nwDsqbOnaFL&
zWgc>TiHkcNAHy7vhbPXDVct6~2a)^n@KGr2DIMNpe;NJK*#YD9ZKNBc%cOW;7+per
zL-a>F+aCRrPq=fh6J0_r72V1AV$$oQJ?TsX#)Wvlf_QekcZ~iB2jYDvx-X9RdC_C?
zU!0CbDWH4t9U@d8!Z0DeQ=occe?ZaQ0Sf63ov>eI(|>TMNJS_vx(5e)$Rc}i1cZz4
zj7Yq2cX9k(-y&a^skgV>G<hwl_9L{Lr}o#iV>mOqDsnAEB5y|CghmkG#c#V7;IneV
zOAKcw)z6l4)2H#EF7KVH%Q619+#Kq<afBOVYdJ9#r|raXsQO2_R5gXdeJI;X35RLe
zRxyr#&S~Gman{$~jd9vWvM|n)$Pzd0<j~tWbngm={wIgNt&Gqo*4B=4X*n_c7v)lO
zV)&iq&{I?zzAT5HqTzRyLr>B0UzN+BqSCgzTn-hD@pZX8DjH)?xm+qL(f=x!Peo(w
zEtgY8V|-H%RmEG)zH+E49^>0`s45;~f4MbC-@NHub3HZ`=eu(2uy~vU<<?^HINz6B
zkM-PGG7;xsxiwil&JX3*W$`$N%B{_MiCFPnt^Y2!K8wdWTyBjPkMm<Wv}rDnomh?>
z94UvklH&YS4s9jHIa(%dQX5D6B(!b%W{eSlivDF3b%=cx`zOLr%8nL2<M_j<llCb$
z)LabpRN0|oAH_aky|+?-s8LrS4s^Y9bf?XhHXL-4j&0kvlTOFBZQJVDwryJ-+qP|+
zzc0@@b7t1ex8DD%YO{9Ly4PK`cJ0ezj3XxcG1}eWwN5ZqQRgCmg?P~a(b;;{_b}wo
zoLM+6wT=jtAg6g%jTi;oYC91j)zJPP=MZ0ncQQ_gR(d^kJp87s#>I8K0UdgBHqh8I
zQ({dUImb~l)<=whtFV@uh6V?DzPtRKF4zHe%><5V?&ax`noDUkO9kEI^|P>#sQ{<1
zmQc~Sr3#V`o3?hIK2ay~m&6J150-}WmB-6q7vguRj=IeOnTGkxBbQ)rKkvBBH5<d0
zCi*7&hMLBPizgR|jsowf&C#x<D=S@7UEAXo_7(QE&C85Sou?`n+m0CT5Z)O)t9iQD
z2F6XU(*C8E^MHW|Z2vwUEWhB_Oh~SyMGT%)UE~MphWVa|*Wv*9dmFe#1^|qhAQs)9
zGqGXe*zm?ik!>~?>{36LCSkWSZ_0(=Yjgn`V%teOqF4>NY;&u4FojK^#gPvNl`<~m
zKM59>{lgMng9#LTao==ob>RtVgyG({^tOTYX(ppm4P869)zr!}2>nUV!Pt_oRA9E(
zuV9^P6TM@<xG%VK>5^RtiuqUYU`$tpYB%`ORm-p!qtx!0FPIr*c(I4w->u%QXxy1Q
zFoy~qs5*i+LB?fCAJ%9ulT)FRYOzwr#t+4J@040<>TCM$6w54DcrUZnjx;YcYbSoE
z<(QXS$JC1E($SwE&xg+CIv3z1`rq%MzeZSBE1evo!mXi;`c2kttl&fnyXabZTXE{M
zd@)Q!0FHD~Oq59#bM_0PP4J&mv0s+S>sW2VeQD!82F+uJ*T9r-LcG*s8f(Hz@Tfz-
zQg5(*G#p;Q-7|)9rur8E<jr%V<jJvRD}gH^bVIy0ge7C*?w{hZhAMO%4#j`UXhS<w
z?8YND(|e%f>&6!4FYZ@9exHHOg5EkAxDX92Am4{g*659$%lfm!=0O1rbd@<Mnu={>
zudCtGD<g(<LKHs?vn=rM+$62o*J$hhp17XW2fb#;x(?K-hFTBc8A@J&-HC46yVA7$
z;=Blljp0p*eRjnyqpRFTW}y__(ha0~kGQO`o6#B(4)bDpD#X6$<%sgF3{zdzon1)K
zIE*N2PNSwy>SwPj6YpH%m*X?7&*XTUHL<9uo5sZv@<LiyS63I_x-S1YZHP@hpC11F
zBgk6`1UuF475q~6LE`VcWJ<<c?wu*#;NC^GQ>3;s>zncueRH!yo;VVe8aT9?30p^J
zCoyvl$r=C)2ZF(9@GQp=hKlTV6L|$3UHs&zZg2y>Q8;wp>f+Ktk>2p4G&5Mm0LtC?
z5o{EPqYi9vNQL5&iIhpbAZ$}PUAE2L%dxLUdxhN#c{t$(|5+EZdqnr*YsImyWE`gM
z3q`?~-^Dczm}v*)%YfrLnw6S)plqg#aS65jBIa$M2_O^2>`OoF%bPi;d*M=A&wuc)
zsGR<`Zw$`C+T{zZ{DS_T&oh;&(8)$yQkA`@TPcf5rbEqEc!ngJ=3Wb>sEc!s<=G82
zudD2A-d}VG#z7ipHT5Y4r8J7aboQgPzIz2!F3ES&-HIxSxn!ezI;8yF5>FFKS+(Li
zg_*61zv#d=x)W0QdHJt|=Z<3qlk>qlTWMdnnnqez3CZ;evQiOWLn{?0^1J73TEDqW
z_e9)v;(OXexg;*>9oY-mm)LUjXB85)Ns_F$bW-t`&0?WUfn{Y&#J%ftpY!Q_vM6e_
zVq^Qc!FxH~W%<kgV?I2zDzmKPnPz#s&z|!IzB1Xhu4>j_^26_6c*||Y48`PU*K%*W
zH1lI+^|=B`jTjzlU*B?#uFMTAm!i2Et|`gd3;CyhpeN#|g51@ZRbQYQ-ccVUh0Bsl
z{s4WzU^b+_XYwb{LY;0cdN1aaK?l%OQ_5;ZUeRY>Cmvk`z{D3^byf4SYG!oH#x}(A
z8|mBT#LCyw7kYUe;xZuC5Wgj+AJ$n37q@+(OuhtsLy26A9A@*3rE(sjeVMaiDs84f
zW}ZuW*QBtFdyWMv@H6%kLCmv}7c23TL7|K=Ddvw&Ow+Lcun!956VYId-!z_WOo+wP
z{?mS}fov_gfb%=NTD%g?C`qY4VDt-lp^<z&Auste@bkyZCFK)JsWpGtAxmwhtWeKX
zlVfjVPF;>)F7IYG9O3)4+80AIfPSQahZ~;gso|+XZ=E@g*g2NCA-DRI=k5^ZU>sU*
zdaC6<uj@1alZd7Ec*QX{?=$`riKYH{&2d-i-T2+u%xb#fSP=Og^&M5L;duRim*&0Z
zNjI;ovquNWbiHP+<`=VPUMIp-oo<7!(6;c%t<%Aa!NCjm6ZXu8jsd;j{RR7FQR<QA
zljckxUC*0X|C<{4@%r`3wLoy^h7KJ1%Jtf{0c=&RYERIU=ac8mn2vc(V8q4q<#S$B
z=a>!{`a1p!z5uo->(U{qS_=LzP0y-MG`c4K`epq${B?Yx;?AwA{cb^S&w@@wx)y*9
z0Jpl9eKli8;$87waipGoJwqOZPl(fO+QE)>To58LK>LRKo%)^n#Ozumtu@#<A9;MB
zi3T}Ko{XinIyyQ&ZZh7US5gE{atM|NQ(KM6=J%-C?uCi`rV@K1Ogz${LVjK12@NTp
zXCyB;X@Jq-aJ|ALo@tEGD1my}RDJx|oqT_`ne6Y;mx52xZvj;PaZ&4J_<%!VJ$_^U
zpm@f~?BIAo1%-^FLXua4(b~)7i{tQ-VJlCzF$i&S@8mz=TIaBJXxqPEbFsJ*+E!ED
zmj}K!zHls^N;;8um!Fm?AUrR4DM$hJfFOmt&QD&6QNniwiP4y+7z%vR3t~H)tVAwK
zFI!=%Yara|7CA~l(w8OBN7iRnUOGSpP$l3x`Sxhx!RmB*c@5jQJ?sl1=IaX}xOsti
zzxGD~Y<_tXEc(^}bV?7qrvaWf@Awb=KLr6oUm=7Cz61PdL|^t__Hx7gTl~OhZ-9g8
zptmo~FE5UD{$T)KW8m3J(~RYNP_j=1kxDzDVKDo}UHZ7Oxbeiu<U_02lPY1#=qdU0
zK=1gY2#1_}jFM^DdAdL`#Q`{{MN5#JGGR&{FEl5k@HsrG3agYQsha6KExoK>Ni?ad
zy*#@-1}itXbl0K~r*f$D){KmiPgz=(S-C4+lwR!~dTTH*LE}UF8u!D2t#b@_k%d<H
z-jXn>cySRc>{COrs*R(tX<^OmvhhiSoOYPj)}bt6d`j-T_;K!y%WDSQT&U?iOTn_B
zv2N{0h;4O8KSc1Fk##y-|DiaNX`}iYj&&C_y18W2;b`Wpin(PI?3#)7cOA|{DaLFw
z&&JO+!W3p0Ty%82MZqOUj$+RTrL1YKy&O5Ol5Vfa+)&1@pxwobJG}jQOpnz=#34&Y
zzH|Z{{gm#yap2&9l|$~}&Xu5f6nZ8n8~e107n|Ugdgz?#c==%0y7%SC8bde8j=#M#
z?jgD0y{SW8%e9`s{mB<|fwzk=n)c$n7e4qM9F5-7wd@^MhYNT_7)95?doNiRT_L;D
znZzmbkkPD(o6k&NNJ7ODQu?jo{oRx1cbY_ZH88J*ej~=Ze5%NXG9tKZSEk!F9O%&%
z*~S!@I>Y+O%vO_hULs-+QK31Qrf`x+wR&(Bgco<5LUch~Q!gOF(J*$G<3cc5H@XZH
zM@~x)spqT4Z2Rso703(e4e#(5Oey-Q+Sx`Y3wo+Drl9W*(RVg3uju>ck^GafZG<&?
znVbZ4h9h$$^!;HgK{!Wj!4sH_k@g{=G@b_N{l1Qs-Z<lNbfVdswbwkwA?`%#GDh4k
z`W__n#N>7(_?TP$-#Ha&If!0-3I@79kMwh%ik!y{lXSOe1I|Iu1W=S-`Na%Dv{<1m
zadb?-E#oNbe~T`s5@|Z2@(SZK3c&caeOC<_WhX(iOQ#;dP@^5{=VF9J+W~0TN=hBN
z9>9m5nwdD9y&B*ZUln#DC{F)wm80p^N*?q?i#k`}v<@y3e8q@19J!R3G8#cDOC3K0
zJz{MkO&Y9)5W31hX<;u(;$kX~X37K$Qz^-OCTex2OlJP{9`c=5a@HHEui$X4;uqo@
zEV7R&Zl#}THJw$1Ydl`{hUm}1STbGdl;c8ev2ZSxyF+;v#cCm%gam|A3oQV);0sPZ
zLb~Vai3F9X9o0R)I-;m~>%akEnN($2RXfSeVC!pKUCs|cdzzVSAwKJEo1Ea9`0ZBq
z{WU%I@bk#0as*5_s+LZgG)(%<BYkRVUb>XUv|N2URynIzS;eVrR*@x9yY2CVJW_m)
z!<is>-aE*_8x{Q>FzzUz$?7{xpgd2&E!cXiKkzaPo|(FW37^AvMoyVw+<yniV)7jp
zqD2sX#NIx_v~}KnnF4q3qcH^A+kEyoV``#s2j5H<dRR|w6nhAx11{BKKx@&i@3*gg
zm-y!aAWOqq{M$eMC=2tY1DqPoWBoWf!P0}+h<iiWGNGS|yzYM8P{JY_X8jOh_z1}0
z?p)?XA|t5&kp8g#OaTzZ2L<3S(Wv{eX*wZf38T*nJ)nIK=rKw~A`}dAFv?3Iwh_rr
zpg9hL)TyC_qP}E&s6;p$6s+`Jtq;<<Y*WL9_U~Z;vZ+Zmaw;jM&Bwu+q>CMSq=ZaH
zmY5U|vh^B_MAK+H955u9IlY|<IPBkyWK)JXvTixdjPW@I;NtoZ#W;iS`?kXv=r$ex
zCNyV~l*Ai*>^F8eMer1M{@l#ma^htE${81Q($@$}&lz`}nnZO1?IVx$?Rx<kLTC7*
z+wV5@;@I!U-0ppW``#mNk+<&{-O0D~7y$oUkRfOc{LvR8^kM}`A{@fkYW-){$Z5mB
z^!qUkUqAQhnY<!)nJ>Oz_7yR5`d&&ReaBuDBl!ovb--(j(Vb)JPP>KP=0JusUfdDv
z_q=ScJR1*TGfYNkiP72CUuX2S$rGt>_cq_@7GKNpYxz%shR8G9M@}#L>}kl#G6H#S
z5vqms*Wu%ZZD7)qg_TvVOBr~R<G=5?mtNP(^q0{iQx9TEdGem~R11c!A8g?EzWtp3
ziG!<9yG4h?o9rp(E~w8>g9E!X%fq}<gfC=@*XxM6nxIW*oXJWcDx18xlGTLQ%Uf$_
zB4x_>1+>48;cDWTf%#-SvRjm3Vj2vAc_$?S=R(QflZdZ3hB!v8{RU6s;hfB~YxWZD
z^HnR!ALN_4X=}6+nzvn)<~8jo=}JJTN&B*iCE7fO1tCU;)j;b?gFuZ@pG~1-dNM&)
zeW1XBQvo)}8VUUc%@Wy%J-M7zI9_06+Fop;RV}X~`>USQS+ss$uAUi*w%8d}+-3RK
zsEg@^GWj++<!WRK*{UKn;p*tyBv^@1cUhv;e7T|MlC8z-{D<jl##_eg^li>D|MvEr
zZy5i)ZyEr~R~A6~C2p)BQs&HUuIUrzW-MAOL#Aem3Q$xdO6wyn-%qA+M``c%y|3|H
zl6JI7Y&}qacFS~@?L*^7eMBv(l5sWNWS%{6JiD)595UUMY=uzsH^DrrXPQ;XQjT@S
z;HuxNJhw7!4bvuLa#GRFbdFnI334`abv|I&-$rR>Y!?FB<TpXrY5A@_wpQg>Gb=V^
zOIAu};6^57Djn_YINDZ${nJ8gcubxCfE8o#ax9J9^6y^J*Fe`46+umucy{M_MQU~m
z;q0<l_IYb3d<{rx^Y>@p^^;6IDUM{2H>W)_ui<F)E>De5iQT1abf%14M^v5%r1kT`
zAeaVuN+Pl$8QIb3_N}j7bt8t$vUw_;B_{?w-dJWodqushphE<aZzR@HHOC$UuVBF^
z7#FkthZ$GDDCUxht4@qODCZ|RMpqxp{aKM#U)Pjd-+q$CP^_o!VIbg(UA#P!gp=BQ
z%zS%4Enq4<XI_@Wa{h1q&Vy{Ys#Vq^vuOOnAWYjJH?`GSj(GgQXTlz<_oGuh$!C#V
zd?wbSCYr>bArJqf5w7FvI+J|+n4;VC&^=|;!OrNR&t$egc@0a?=J6A0LDv0oBqi{Q
z0EzfQRZhB;Uygm-*AhsZFRWp@9}<u3PdS&iSKTw)W4>|SO#lO5Y(P<Ws?)4CW(Jk9
zFYjj>F~kS%C@yK%HTd7P3I~j1R10_LjvI9FK@D7v{jB@R!rWSboVFTNjq$T3)S=XE
zD_OB%zHJ2O`6gi8d3sy6@ZLH^bqA$pqV0TtD%^dJs;vX=>Opggi^H=0imG{jeRImZ
zo{n^TZzJoPfhU^!m>Q?1s$wXpN|JN88<>I(n|pb?8poW+o-H|;0oS>MW$7L(w|JQ`
zFX1LU_rT{H7egZR+IFL)eH#^b^15RF7v$_L79gQ3E!xS5+^DCl;DMye-qO{>sVQFn
zk9H=#YF0%uGnQof&~_6G9w%!Tq|UyNoTCThvFDB~9Vtse>Xhp?rZCGp3;?WhvxQf%
z8$jv-`v%u`-MFGVnW@J4eP1f=(A{3o(`GnJ`i<f^A&Tm|uku&q(#OzQ1oTR9L+2X-
zMYKlQ8{=+S`S67HqiX(j>dI@}<&Et0#QbAW(LOp{RCusKr-j{q&Z#R23=_`vzrGOg
zBpM^67fijBU{y~e{0-c`rw*!aIz<dvzPNHSF{fq{$&$21E^(Uepo1zJ)nAtts<$;d
z@@u37%2X#eI!=X#2HLYIiH1~2!4q$QSj>kEeZ@Er3Jp^LZDY>W+cb4A3S@-$@5?pW
zg(1G7*8W!HLi-d(ka948KWYMu5hy1=YEW%Z?YxLrzcxr47WNF?UfkY`Zx9Fc3#1D;
zV*k&8Pkkply&D-fju){TV+>1FHT+)cxMkv+e(pHdICy<`BTFOdZq!vEv+5PJw>e4L
z*bmo4TMH@HH*C;I?kLYl{UPt6&(!Y{3wH!kn*Jdl0=d^&Kd<x9hbdrwLIuTA^yp0I
zr_9TR0IkUv_0p(?x)F2m`gX)U6)-@G_Bef4Gc_o8?U%;^MCVVFd_{>A4%Y>)PR8m`
z*lpb=fAGVO+r{1M@N9&Cbc3=K<S-&Q?LQ9%sO^moq1<5MW9JZ<ewlj#v!2kI-ONhQ
zAV6)PoPZ;G=%Qcr6!_UA6hAxn=DXhH!F5VNJA>BzI0`6S?hypzgYpVweK+4x6odRg
zcmcj8_9Kop@Q|ioU^!29&P{f2aA#g%dr$T5VZdj=|MTZH_mv>^X#Z#*f#npIv*tDY
z6)ID|%c3j%#`@m6)TYa_E8+&!k#&LjIn^_lubW?Y`(yM2vLBzlU<XzQ=P!mOCAk|h
zi(cAn!1wF9(_T;i=RcSmI2)1rU64KjH^VzIJFrE;3W&{+-*<-ECtQJ>LYs(NNM}I|
z^ob!i-$$6A+mM|Bc7|reeQFfoO?{?8(;&Vt?Kj`pVMt%lC%eae(|+t93NNIA)P2+l
z)sQuUFTxmY7M<3eu&|ZSRnNW6e6@T)<8K&;rFl)gYk#`1tD;W2M%MzbGO8x!me&ld
zfsL)3nhjE|m)J^;y=}bVd@MtnK($@eJ9-*jG&^=-&Na_9%`i@JPGPdeTu88q;xfhH
z0>9r^YUgScS{73G*~Hn%G0!p2AzO%g2zv-J%yG|QpNYPSz8O~f#ra_zO^tl-i13Xd
z!t1b&0K)62jR?Z)hz*Fx3X!!SFl+gET=Q#xGTf-3rMRa<lH(!_sH7>{H+FM?^qOpU
zBfYWtHhDcFI5qM7uyUiilj6hl@G)Kvwl)ZYW~dFmF!w<EaPhE6!Ds|+WK(ei`EWLO
z7Z(?chdv9m&{3{uiQ3lf*RZSb@{q=N$#;xuMJMDezpxTa-0-f!xxnT+TAOqvFN()c
zyFy&OomNX2w&45=c;;ZCaC`pfc2+l%`+~nP;GmWcWNL-Ij*@w*&+mSHsVv}d120hf
z@FE{{hClaQv0d*wYK0K-hYa^SQ>*)&>;qZwdKQwnWxf+L6zv-aS~DS<hPZki114v$
zKlH%c`B0~Vl)kf^xGzAuTDl-=9s?dhUn+ey0l_HeqUWNeCZ9&1Kjz+6-!S`eTA~AN
zgsUi)aze!r5P9>39z)spKxyNV#DP)E@XFvQ<FMke5JDHi7eI)SLVx6nkYGUOOL8EA
z`woPwsm(hRInNgP6!N9U1;>fVQO|MAVOS6)t!kYM**%r})wpdEr99ulCUIxoTi0#X
zL7Fwsv`KaaM1J0O@6+dkFM>Ouw1xfs&6nRi%kM_+5OhXWMC3J$0Vn%TEJLehXSHVz
zdsMK)L`~Na`9cit)^-psS>1Yom7;YVPfgbrB1zYFz%)lP_v0@rg|8#cu3fS|A2({2
zG}73iNtg(rtZoR$;iabjBl;;7d@{l!#^BG+v&E~9>*1O2hX&0Y=g(6o3KZiaKQCMb
z8rU$y{!4<1FS2f~2(9H8Z%T9TkfOfku<p@AES7_6b$JV5M2nWw6T_LR$m&-Z9pU-s
zANQC-z~IfbzJ}v(kec5p=Fyi!_+_|xE=a$>7RY5t?kvZ-oE&`ouRDuUlzEbux&HG&
zAIJ4b#@-e2otJ~2j1IhZt8vReIJ(0PZd0gxCc@_--l+JomKF88il7qs9W|BEi?X-}
zYs6MmXYlqjq{@SK@rZrN#_U8w*dRTuGM~z4Lil4zLMW*WRq{bgEY)=XYPVM9%4AY>
z&>Z4BayPQ_shgec1#GzLtm@wvYliTYae8rOI=ow>6Y-?0s0515QHkUMp9>=k&lCEE
zDV!_%!k3RZ71siY?%E`4?dxLk8c*}otw}XzPCAHlNB*6O-#8vwszq}fDDO<9VcYr3
zxA-zIpLe&<NZn<Ruo6#$vrn^y3!{fe`E;e2CZt6KS&RdvhC#jVvQh$gGvhwO+f!2m
zoU;i-&_g(x@Rtl-3|;JSSo||M6f^X8s(NBOc<G>E**~RvIj7hCjKA|#r$ID9xj}S)
zxPbXU{kCVjXPDB`Dd7~aHK|pxlec4>;_ZU`3cZJ=cA}eNrz^q~Ihp!SlslL~=9qSa
zJx0eC`p#ogYXPbHBTGMP($@;e4eK^!`$hc{<x4)zA6K2xeS3ZI3SpV*yFgq?<>z{k
zt?JMHh~Rn?5lH&_K({EGc(T8sgVh)izjZDOi}9$lXIOw#)#sjc+Vz+u`9AdE{<EP}
zdsN%w{r6i`E^XpNJpf3iLnkb`G`b|CsDxzB0w#^LFz6m8We%KF<J4zeqS!HouS^RL
zhBX)rA`=Hf$pQ&NhSZzM=56iQRfE{@m4X9r1YI3%(F;!xy+ZOqL-b=6l9y3SYPW(y
zK!dAgk??zHsgydYM%H;>A6GHwH{$Q(OA}RuDh-SW1ZaOD*&?72AW-f6*nH)--aPO`
z*@l{O(A8?>y2K*^1#la^dZ;!I+YL!nBY&5tQb6&>e(nBBZy!jjsIASmdtwJZ|B6{s
zv?H5-nL9PcZJTJKo~^bA<j{3&eRflhT3aG@?Xw&;VPAF?ZbKw|;Zqvy8*3{L9_pw|
zv=sn)9aLwiE=kNN4-BDwcwNKZ9q2kUI)Zg4NLw~PG;VD;{28cN;)p(o0*kB70x?#L
z^V`fQ*Fs(LdDDwOIw&(_h(w)`I|J|UUd+AYGPjSubh1Zpus!hAKX7+FAWU0z;Ec3P
zKWIH<)qSL9U|$*gBRHD68?N^+@)Mv-{$^`;k%iKMV){(PYA?*=JZt;Bzq`+Q@_eY&
zw@3GXB<$J;^D}G=c48)Zv=Z><T5Qd`s8nx(gtA0sMioF^Msm93AC99(D{n#J&p<Db
zqqZzONHwyp7u)e)&tgI&-vEpn=k>rR{5cu$(Rvjc$MsPwgJ5ehi}c7ZdgJurar_HP
z9o&CY`RcRTS#eUGg$?DWnf2Z&e0i=l8JH48{<bB_+)aa#M)%F^*BaK(K46fo=iaZo
z!kOy@jJ$MnPIPmAbgv#VyAWc8&0-PTMI(5o?SlR&uw~SVy0yg6nTj<q#yR%pntkS+
z(Eh$B`x{g+{hK)^0WCGvTa-B_O5&{w@Gx<UDYs_XRq8CvPq&C}h_CHAS2r&Ge!Op7
zm<6?!GaqeBOZ+3rdij>J=&#}E7k@P6u&+Gk*Ka^N)ooGzGHpgZvE=yewq`S+j_&ZK
zBs1ODNt*MESoRxs07rw&yL0?DM<dvGaq*&Nw#A|-?&}Bk8@wqGL|DrFlw0xO3Ul_I
zk|kSL{|mn5&zelur%3w~77-|WpGUMso;Oa`q()~m`wa3!9QbkqL;Cn%8O}lx=bDA&
zZ3|i2wo=+(KnrNq0ep7!8?XVpa2U~S2~rWk;$h}Tp(lm<Ef2ouM<46WJk52g)7Q_c
zws%jJbxTpSLl)O97!^8cMTN0U0_0LD8rH`?#duyL?u;hp5m=BGLD5dUJx1l&tg-@I
zZvC%*XicXf^sx@}*3WPl9EE_Jj*#!OfP4Z@C$Q}luJ?7jr`Y!Wc~hw*9i`t+6R0h|
z%X6peGxpZbSVstKr{{`wKZHSKFzs1FH<TKnrj<D+#N&MbWdegcj&^x!#OA}~Vyw$l
zw_YW=u2|6U0?9CpMA9V;k#N;fxjC>hiNu^#vR;@X{O%)I)7`@(+cSs%>O39&$aCsr
zinH6XYy0`wYx+9oRo?bA%sHvChg;wKRf=^HINSSyf>Qu7R&;cnYGh>1uegs6IkfU!
zQ$z%QCjQJkZC8Y>_=rMZ4-h@NUv+wVz8k(jUq5p+-^`#Azx>NmQevDsmy{I<*L}eU
zsLoMTtNSl8w5rx0@*z|L0Wg<ohD4lSB7c|!dK|DYfT4m8P`7Xy+!x%s-<UQ|XqD}~
zM<OobdoRG32cIa`QD!6XL8x#(9N`PN8aIzKaIu#x5d1NTE>1+v#)uiM-J6f$S@1G_
z1a5<l-cB{aKbs3G$rs;&RjC~|X|mVRRT7S&NQ>nR{4~bjvm+h6C`mQ=8??o|C%M!d
z=Ec1!8woOx)4Ud|%Jq09h+Q<zNsIT}GC8eI$56X?i&C~LsFj<Zj*d}H5^BOjo^H{Q
zFTqSNH%@MzH}n<cO|e%Lc}OO0eb?mp26z-V_^enNe%ZRhSfUvexgSirwPqD<O$wq%
zSr#<$NlDLv{W#SZh}KCWmBPkqcGEs;hw!UyQov`OemzBrgo!K||3SgZL3{wj&QY}C
zxnpIQoVXO5%D9=C=-D6@J=Pc2XevJxXpO%o(z6QO{1Yv3;!V*JS2rE3De6xY*X^0h
zDi?T9`~$E~E219I3Hk||*|3Gj&TW^3f&#_{B+1h{7a=2`8l^71tU_5L{nYRve!z3W
zTUTVE@`ldu8S1zlQ6Ow6Dh7tpQOZ2IRzka<Gw&v#wJQO>P6!wnFBNcF_J9Ioo*pTz
zYab3=f%__Prt%z+_{am&pD>7Nlwue5our9uTqiK%)Pw6JxXT{9$?PU>+EnZN>O^u{
z9kLffAU1QZG$++-PKOT!{g~{Cd0*^XKc5JWLG@8cEl*F5`nY3e^;b$#yDp|Y#EeS@
z%b(iijk}8X9XT&hPyTXFmq&WFZlurAY}~^52XRTsc~Uc{Z8aD0`BKO?qU_N>9)`==
zJQy1Ff8|c0ZDt%;-vT$Q>l4SzN{o?5wC=-Zd;N|M3}Uc5w!TAzwh;CEFsb|%CYjJ%
zIW%-|zgSc|0we!S9s31Z@;e#tZ@+6Nf?UuNr8v+l6ghl(>3t*O%LP7%tj>*S@H6*W
z#La7%8&r1jcp;LY2*?j8iqN_=ZH)8OFkSdCmaNsaA+_Nv^#U+Pw6B()Uq2AmAU(D=
zAL**S(6X<#^eRYVZ}WgrEHX^){(wLQf%l|Lz)kw30)5$HZsR{10gAq4%~4#Rg7vtK
z6=Z%hoEOLLlhMiS-Jcy!w8CTsk9))2DoD(UWhdrN>l^?5VdgD{FN&;QGo@wvv<9B(
z$r)@S*^|+FQN2Mq!AIKn4xC*aotD!&=wai>Df*P;UsE*g_X=fgA<$h#3OQ1I4t=72
zFKG(xl{%BUB#heM(xXWA{&kSW$TP5Wu@jNlwwqfMmP3uRpO|5Lr^030>>{#Eq6()P
z#$Ue?>+N!FbcUT>^_rmLT~Y>eV;E`TA#_c+=@FblX<TA;+8wBU;bX{-c(2b9;`jWK
zG<xD~-QW4TF;h+NK{`=3m-gXt^2qHU6uX8Nu|;7k|2`rNb{(2D<ZiOoX3G)|WJ+QM
z!Tv7Z`dU2^tTb~SC(#V8>fJvz3y*_p+OlztgLz>?V{2wQ1u`MN=($S}5$*(hnUf>}
zE|4JQU}E3M0+c(mhXE!qq`tH$t{^h2E}{TVTSZVtKpT?mBp)l>#+f%;&t#M8E0mkv
zGM-5JO5C^TeRl`)xH6~XtM=wAx<e0nxPRUvEjXhszz^Pu;iMN2;EMec1G$U;)5ivq
z<wAJF0Cc6|LMZnx%l#tK3z!AN%O!@*#Dv=P?*|%@-IWsgBS?s1^>@1JI@N_(3To0n
zo2JsYZTaKn>0LHc1sZKLyZs=B`|W6$z2R~m_lYWWgKXIZZyYk((t+A{ivxl?(o9a|
zN0}k@^0v^$T>Z4eqhbmCft@+9@t~D<i_;~4=s3v%`RYguwxcrS1Jf2ZAw%*goidaY
zIiyaQ6b9;1y3>BNs-TT}0%nuDC~EF;^|E-H25wQQKJW5ml=)3T1_m6W0mAqUouFu$
zQK{NF1kqmi5`#-tR=xr2IZBJrDmC6T1#S5K7{aalwmj#0WoOOyDo6cRywJ0k3gc6A
z%gv^<{?-*(7t>n$^Rv0*+)&K1y9nZ8w%%*k5YLuHcO0eYr*c{mZA8(9ixq$<uj->V
zm&~(MM@sIZr=*u>aXY(yK$iT-^XHH|4#jym16q3V9{Ye-o15RFSo_x4?7?VW2Gns&
zEWIU8I7_F8Ki&e12dQutM?eRc=HEC#yrG)?d=W&&FIH4EWyM*iSCx|hn2LOa3_ddL
zW5KV%$pBo6HC9U06a#mBQN=~@Dx(CDwZLS%j2P`J)68t$v9lAt<>P|)H#R2gydy)_
zKUw_Mx?Bl}Gn-P2w~sv`68!Gr8Wj-Tu&h2}=e+$*IQBRecig6hx|_tFz{;f9PqVGA
zSGaGa3iMCp6!_SwDYFv0HWGQz1f?`Ckzz=@wf7!5Xu5rPv8et;0+8W7d(l5<IO^O-
ztQvC8k7+CW*<{R16@&KZX(U?(d<}^~I}snTYp=JV%DTC!PlETjH&8x$r5*9{5wdg7
zJ=)z3GH<HA&c58>@iWQ!Qh&G#;Kc$L%A2X13m^t^V>MYzfRfzjtP24!x9`KqEktt8
zi^7B434J{`dH812tb-Y<S^@E!YO%YU{qZ5esBV93uW=3y$DLF@S!ALX#wv;b%rJ*8
zug@I4x=92#@!nJxz4&bLnfEfgk5^o2A!X#v+ix_?52b`z|BTogm|lY~g@{&$RkG}X
z=GW%5@BIuLfyRwETk)er#4WsOQcLJRa!N2l!X8dY0KR6XZWh=&zS*5<Z}~{uJr9_m
zR)R%SyFXtWef5YHYPazW65f<xCdZfmjYsu?qFt|=5|kc`-)YBjLd_Dgo=64W_w$5?
z<?pW(78fy%Bh}j<Wd$Jbj-v3twF$U-&)QBc*_ItF^Pa(AXj=H<TDEr!K8Kzi>_jAh
zg0BY%Ax3(9JKVm;H%TG4H(<VX`qlvvgFWJ>_dt;*3H%wU#AOpD1C0wqr17jq#96Ei
zWG;DPwhiwrt`lp?q9HN}&-`+ECSd?qtwn@KMN!3gTdh=JBGv|;$CaOf5WuCHp^=MG
z{ycx*yI$m|6-63r0qb>0Avgi%`m;nQDEH#~G*I|Hvtj;7e-+Z(W-`IE?h_~_d38AP
z7~XUI955M~%PRIE?n#5|`1+YVQ;0o6Sls8Rc8tAL%V)@EGJlamXtBQ(rOd{uRnwMN
zw~Q5#j0}DRFR&feLNXicN`4kauU^~5LMfY-DZ}%{k$)+@#uTIkvnmyyn)~N^Xn1lo
z*NWs5>#)@pxx;?TogPc;4K{yI*mYE<fwy5wRB5#y=|yRnl5-~KO+ExfZfuWZ?Mhwu
zunGg~XqKBr<~SvLV};!`)2>}n<zwY=sjXPC5i3s!jpNHzz}7JK9MSWH4=b5BU|Ox7
z59jZxi6S{A>n9~y^Y+A<b++wVm}Pjd5PpDWO??PQ1RdH@_?X-e2aacodp&nZ$wqCY
zD0r6hV!p|o@*E1P!SOAIE1obtB&b|oGoP!%tY|VxMQ!b-I8WEEA(h_@z5}ExJ(pGB
z^Ni6~k{}<T>CAh~Q57DaNJ7LXKZOVxc?BUl)GG$5YwGVklDyK1gKkkgx4~{&j*!*@
zX?<%rt8rvu?AouSjk@MMlwHF{kH^&?!q#dEOg4`Zcx@)#H%wEt^v2?qo5k75UQ5m@
zJQ<e*XhuU8;)<8&$|C~C&Y_q-IJ1kh^`FpVf2An6qp#$wZ)?<IY>xBu3>(fR+{^e{
z!JeHV%X*ftH@rtZTZtceC!Q>2%e)g4i)0SOO)I1*#f7Z?^+=`n1^$^x2;{f%nt^g5
zzV(_dU!ODoXQZ_oY|sp71yXFb8!48b2?T`#8_G;T#a@)<pjjG4fC+FL83gn$d-*4>
z5ft140>kl8GRHnrYa|@;y5ffjahm3M_xjDTrCqrD<Vu=Or(j+W@N&0vdsg&u(cfk5
zV#GDlAnsL^#m(@TJQ|89(c6b!I@7*+957iW?YVA_eS0fAmgW3pk^Ii@|9m&&pU#U3
zFzY&^aCew3e_G5O3CYS%9jN9ZoHbxYMY&>)z7FxIy;o3+h<`ULXK5Nj(JlYgHVUXl
z(Ze9YFVj}baT68?yolM=b)B$yO9DIUNv7ZJ4F$I164%5fiRu5ei4-pr1gwno`I|^A
z%+IXNs7;knu^vZvMX`q+sgX&n%8=p5Rwg!|TFJeJ`zVPPYbk0bl_T(_q7&Zsu22Q(
zy7+eFw~U)dXrg0M`3U`fuG%7skk)ck!(y=IO>rqcW#jkh2JINR{_G=ydT&61ALad7
zAzpRxD>1QclKU3Vmo`7=7=gVDa6;?@ih3XIVW})wUlc<4q!5FM+$D-R;RJHNL|Bti
z-TM=6+O}bd)e#PtEmehtX@cM(W5w1i$XvF$Y5&)d-MoK671wH3gllVMjwtCA_9-ao
z;j!rP<$VR4u1ZH#i?K*B9Sl8&)OkcQLxdJ3=ONzhQKe(7P?gdH@_B@)2B`4wEqc9m
z;dqkxg@bRn&0(`aS2=7KI8;lC-TCFe%K<M|B&ji6#mA+oVxs&N(d*A=@wXNt&IvNT
zVU@jgyRDAfO^(0|Q)#**+wiv^#yWTF&(Lamc3gN^p<n~}doZ(srGSp=uMmpsDL1=#
z2?nM5BWW~;{pAKy?b47?H_RRz(G4-tQZg_RFz~uJz;YfuMvLBpfA1SFr9Ds~?#zjG
z8h5kg(FCw!k6X%w`3Gy-JO1Uq--y@T&g)KGnt%}&LfV~oeC#)nI7;qY6*oqr^xO0t
z4LW`#zME;b8o3t3&@%j~-!O>9HufK2CLS|Bn^3|5)IB(R|I9xe0$we$NxXy@Vhm=l
zf;W1cr-7KzUmgM1v0fY95(674h7k=zGy$BkF(NltAZ?A9p1Ot#4XjKuu;BBgEp1!`
zq)JQc_V9J`x|&Mca}RiCi?kho_g-=4sR%SP-4|H7UX}c#Pj?a97itCJK&z7iupo~>
z7j^%VDN)4bx7j9gMueQTfzG20n`(J9CI<XMpq?nHCfP4QQhg89<1%oaVq!x}ikm;A
zbMtx<C`J!03wK{VF?1{A?YyjKA}dg_C9gUO?Ox+yn4#%7>FjnWmvGbHIULI_w~Cvf
zDc~Jz99O#S|9ffnbXz1d`u>zseNH{MQPk$xlJ8Ldbn3Xo!EB8U_8_hwJ<nRvcV0u1
z_`=g*VZG1$*INSX=F;K-MK#xei0X&32{HTHy0Zwr4tdtmojz}oHWEV-*^x)vXK9<G
z6*s#G9ka{B>ew3-HlygvW9Qz4pQ|Y28S+yi`gEz>4+WmW(%WNWb9;w!T@U*d<SnN1
zttQcfO={J$*NK<`Voc&#{d}2*O9>OkCO<qwmmk+azZ)CKTGW)eV@02?^z`+8#6o*a
zJDs-fV6}e_gh-xO>A-@g?K^%6;@mgft$v@_HT#`^!UNcqbJ&rO%!o~R;gzgGpzZqa
z3ktr}q{8p|d8iE&mVR0S8_eji_>SarNk^TDnETGovKeSqKZ;Wu@?NfE@wNd!u^@Wr
z==$HUr`N6Q^B(z3JP;N?%l&X;75JkYAebj$^u|xC)y)U@acfsdP#^Fkhd(nl9Y(n2
zeH5A_93PF=0=~8*8CBq;6(JgAHhJ;-DDAMQvyLngP_6J<>4#PsfN8ht42e4iRZD{q
zf#8Q>4S@y+!#LNE&CZbdLXfPN8|OcTOXCW%?JnRS_6yM;z*<im;O)I(FVltB>&0)*
zoCy?Ei@JQUpH~t9P1X*QbuWv`>|@Niy-2aPso_**so^o=-GwMkzU0%8pCXYBZ7+K0
zwKlnq#2$T?gnqSnsWd~Ed?&G^W?uIF7CPy%7K+Ng6h?TKFe`Hh1tmOpk2)e*FfIvF
zZ9DX`QnoKsJgdR?l}5xeXo-oJRPNW?5wW6j{wi3XM8r!3+5>cg@WwT71YDob6VmY5
zQBy+-`YIe&`TZNj>!{DgUptP6D@}UqNK!$cr3pE6@v-o6ADyF@#_=%O-TW66Lheke
zFNakl^mGOvDLRoap|ke+Q%hE1+W9NL7+c&cEm?=M2k$l6eoP1iR(x%Kf-%mt&V}Pv
zm7~`nu|Hvd){%ShEr0tF^{Dmccdl2vf8k3G_<j~zr^w=gt+;lOT*i<G%hldrvmQ_c
zUj`U*CemODztz3N$0+elpj%{$<TR;LI0;tqY$%=wfxOC6B9E%7L1<qsv9XL9X;Z=C
zI9-E9N1y%(hTq^{TtQJ;+l0x@TbU<YX&b2UdpJ>e?$yshO~fjOFQInns!Zut^kc6J
zALSONeT#Y&mfrDyT!D=!gnxTP!heVNW~z)EnPr8E_AJxXT)2O~voQTTLlM5TE+HRL
z1<U`9NkD5_&E|gCz&^}!<=4boY1-qzd8UEbrjn1uGJjN<j&BWUSW$zqT;weNTZ-T~
z?lKi=zgVWXU86CF-4+yKSLN6BmzbU*$_d%0Z%+%{g5%wt*$1|Q&oRe@#y)VbZscM{
zq+22aTiI`AuT`xu%E#v_P%OG@A`1hg)AfbNj-m{v`G_M9;uSsUz)Jzj*v81w$-!9P
z`k$7qfdv#JBLM@!KMfupDEeRej>aOkHckZeLgK&wX;6zWLec*=b~OCv*0*u`XULI2
zli>f&`z@#F?&xG}EpB6C`!7CO2P0z#a~o3vmTyA}Q1lAMrsm%+xD&AcyRYbMXJ=(>
zZTxMO0g8_g>L1fewxZ&{rS<Iy=*5k`3Fc1jQ1t)U{>Kvsb2}$nhkvOS{KqdR0!~(@
zZz+8{F=KO6GbaKz=KuEDiGY@gjpJL^O5fCxfbHK(e*Lm_BVhZt@qd(xm|Gb$5pev^
zfQ-Ji@&As1xRbt>xuKwqsg?1!lk|$;^HU*U|F?vayWKbU|Mu=*^H6j)aQYYRzhe0h
z<F}*#!w*HTO2GLqC477Y+EDbuHiouF|3vD)XH6^iZR|g4{t^5(u4JohWB$!(Ou)$S
ze?9oe?tj*m>6`e^x>Ecngp~hHV*U?F@Oujw|Ihe8LHW;C_>PK`vBUSotn{6Xe;fZ}
z5Q<*P*v8b!jDU%eg^`8zKV3!wR!&ZK_V4KaduodR-e2FY{MSx%%e?4>^io<}<@cHD
zY`FF`5ocmfn;_ATmtw0=fLT@j_0#XiPZA@2YyvC)pP{9t_BEPyOGQm<XqG}iVUpS!
zjTVb*$rg(iMa>qA_U4Q20(ZVsyw65{e>C0!f3M$P4+F1xra7N89k0E!k9m$ckGC)p
zM1HRB2>EkSYgkk;Z_Pau6fvRZwF)H}qu$$!^WU-$++qbjTq`HDCU)Pab4A{S8U7r-
ztDvT;i01p;I~T+HLb&s-%3fcnH~snpE?yBs_*DnCNLyu$->%GzXu9S1(ikO8n^$=a
zU}6tP@WGy1TkUMF0K{GMc0%N_;uDiNyW}*iI{E@~Oo$%(jYjwvmb(outCwGR0@*MS
z=D<~*tj|PmM<9;*p)O&miH@JVOMOlGfAN1|{~CT*eR6s9T5`K0c)<7DZ==o=cyCa1
z=;9{KX?3_fvUWyawm{soK+tfWPTz_;hqL8E5`3BUL{PX6tGvE?+f2S@BjjPgPp4N~
zZ>r+g#vTcJlKtg5y|y)}&3@hXi8GMK7w{o`-oEs-^)^U8j^INEninbkdCqQ)=bYDR
z=Y8On{T0>ud4viH7wCf8f4YroL`%){)pix=n%4D#d>}^<kLTq&%pBOI*3oo2PA_w%
z(pB=uk%)8;L3&0eSOkHuy!~^WzN=OHHG5`0@Srs$vDGA(I~Lelh^LVy7oq(Jp(0&o
zN<hJ1lF%AKg~HgY1QVf@+r+!+f=(O-0vY;44w*j3`0l)iSyA~t_dZks3#(f<IgC7d
z(g&=A76)MXzJdb`-{0lLuHiJ_`CN-T+y0!Jz#eb>@f?ut$K9JH7lQzw91`(0vgdIC
zjB)|MI1GSMd5ujL_G7ab0A7`Kr$)c>IPm2vJC#Fu>o|)W&r9K;;k!PxzW+S6g^t6X
zy>zYE2>blDU~SCAaowbdpYVb5m}eXNGCcggTTn8R2e~M-T8uj=!*!f=(p=-+l`uk0
zE$Cj7#2?`B3f-+y^MOB$^Z=Vc0&%&YQXs5|n@}SfVN?UczzgThO`dfvxp3<|)oU%_
zvpP9a^Fn+l`2-5!jiVR&s+reunOd%3FN;E&lJ|Mz6w{4AaZBUDe0?o2J1V=B?NqI^
z!r#AzKG~~j2QO`~EqC||Nq9@EkFJEc%y8?PuO{`i$jYkw3hZhvA%7nCl)qQ9E_{}u
zJH8U$68G*3`x{T2FkZ~Vz7Urlr>X=0^f{-xOzynnQ6s9$e7h|QIk!9SJYp+M`C&}~
z>>V($89>$AUGS4#G?#UQp?oMN@AnlMOTars_>Rp2=|TtOOA!T;I*{`=ik$dboZ*Y&
zh-og<2l!na+s5F?r0*YvHf@Tu^@xoVfZq?7s2fK!F6oj}maMO7QZ>U#Jsxsl_D}Zr
zBSVCvFNZgt9&3NjA2-hLyG!{I!0WQq@C6Y->)qvBs-#{h+EdfNQwjj2;tsqTL!aQU
zFV8a$0u6<zq&M^+lfoS@ge=HrEpoCU7C_G+Y#=H?Jb!e0umsrkvgK-Us&=Y>!+n7?
z25twgy?V<1(G6>VAvVL+jrjGUuOxdW2*ZeON1BUXizD|_4fq6v28>14-FsB`{f()(
zoiB9U;>Hv~2qxd-%G8YQ8S2i_)i3G;jP|HnSbf9Z!y6gd=chBsT9>ru)jI{guRl|p
zdueKgu(=j)y`Az*F{ZKID}|q?*#2>i_H~aLZ@SF9IoD?l>8Rnh)wN;yfH#x7?fydG
z^)FRvuH&^)_q>?vyr2ymrJ&+@r+@MOD_;NUeDY^?SwxA?EvuVCdG~4{|1aYI=>Tp6
zpYy(B{U6!?L;hzKR7tDx(}3K8_z8eQAxJ=RfY5vHs-|Z{B!DD=rHST%C;vbRuo8G3
zEfw&Ke7pVs*YN+=T|5t<H-7;B$2?#?3>{GtKu+n!eeh@B_BWCjB1+({EY-pS5xj%|
zB?bPZNK+|dQ?7C;epZByD8CTI>?a2^9jlFrmY`Od=qaNc70+k3b+#n0>TAxc0uvWk
zUI<Ad)e{4}a~`W%!A$>5BCplc#e)_k@AtJ>j1SWrcz2K!%Ui`PyC`7NM!zw`GqYw-
za%RGnKF@cykUhEkwuSwvs}4Pno$hO#CXnodU;VXI?cgZ4trWS6ufppDpx+QJ7Pvi_
zGu?8B{mRDI*F7xy`uqz20{<HG;(G_!;}?mTQJB!@Wz!>%9v*e0(+T9Z`%yEjdBf>O
z-UXxUSJTVB-~S^2f#CxJ(CCvSd2tR?B1#w`g$h&1k1r*~3PXdi=c*ohZN(eCDd~IV
z=Y0gc`ty)~)#%}HdFIm!4u7m%56ycbwlZ%|mx((_@R7`g*CECBsMGDUti}SethKme
zxrO;od_DK3ebnNmC})qBuTh?*V|WNZr=xjLbQ+)cCNtP<PIS9%tc@nml&Mu89-nA*
zn;Q*B_k=I4tL`<ASf{Pi=U3!(RW%j0mDS~S*toScm?~OJYYF)2T}>!>X<0dUWFJUd
zFVPAFYm_Szq1vRVb~z&zsJ)f5vU>%Nb4hk8%EXD?b<t6rq$y5t9t7kU54ZxdW%ANZ
z9VQtTF1U+KQkP(276-s(8L4C>AC=yC0;W}7c>3Ms9kFjzRbJM31LXZ|QQX7@M$8EJ
zAAdp17I_;7nIgD)P(f5osdLJ$ssn%G%2kYcA9j{EDme)hfvdo7=+)PJXQt5gg7lNB
zqT%ht{*sj89(kwk@Blw%Yf)Bd{k!Fo2a^Qt4LddlarjF&TlpY;_Anc?ECx=C(Mn*P
zJ0KlTS9UqRS+ENl3-%@n6f^|}D<FWfE4(-H(zl_X_8G4Djfx5)fbXQzXKMxWCU?R1
z#vPnb(C)VD#4|y%eE=zK`v#JTrfrasvDbcxxRtH-S1W%_iq`mHzkVYQQ$R<?y4hAh
za!0Tn2Z|N`0oQ1p=qjQmHD`SWE~e$y={=INvP(E%O5GfPqjMu68EOvw>vb0&=NabC
zZ|ZQ98uIcC_eNPsu5Hp58%7lf`3mW}=}ti8=b5W>pL8XWftd|9%<CHjZ5NXUFci;k
zhzgChKr({{LCIHwvkNp$*kCH^5odQQ2rlXqu=p;oN$cl=i`ixP12-**26;FO@?}Od
zYKWpAR1j+(Z{V9*)p)hje6kti+!!_xw@vSB9_wMrUctSI%eziGyOF=BTU!(@8paN$
z4t;`3q8x88e{0I^l=;K!sx#s+{AmxQnKe_dD}n7mr~o%bv_!B`;E&z?JY+pUkWEis
zZvA_ylRo7jPIsGL_$4?P*aaiU;3ECNWBQjxBST9ryrjOxpbt#uOo>V-cV&HHc@$AS
zlsp&>Dt`*gCG@#}B!~&F9Wgu<?J`@CWqJPS{ITi1C%DgXeWVjn9r~@x_I8n--U7Li
zR%7%-oYR9R=LkFw9j*aJ6^=~})rqkQ>eYgfKe>wY(2kb-f_RygVa5^Y*2iG18dOcM
z@GzwXo(*i>J77G3kG^fHaRC&n@OJ8&CZtXS>}pDN@i4%=+#=V~&FT5h4|MlNz}NVA
z>=y<)XxCacu&$(Lon-5ayEV7=`e>VUDc<rleLyvbl1onry)_@gP)ak6MaTA^*yFiZ
zYayJYG4Am-c#^)l=67BO;Gab}l%zo<`-GTt^E@LIfp69C{XZ|!q9p=B2)B77<K&9<
zj4_<y9UCVEWKj@gP=a5oJk@^11gcv@CQ_QM+GudAS62NY26s3B{(%gM1UKgdga{m>
zJXcFp31i7Y3qeFGEF^aaw4iL@Bp1-M;tcebNsa=)zX_43zx?@2_I@C}Bae)7omT~1
zRi<3}<mZ&A?O*2)I1ThB+y#OY-IqWtV-i2qHC2DuUN42yQ^Kc~0`Efs)9)+I5%6Xx
zzzxAuQm){XDu^o0JWRP)r*VLVE+!>C>0wc$mdMzl-s?)R;Of9BoYPwmVt=T)5S`R8
zmTdb2Oic8Y?LFUlc(bQI4J|N@1-25nzC*&>d9DttAUTRE{MFSJ(XyY$x|n8LcXJ2s
z5a~HW`2rkO9z@X!=t3#dTI?-&RD17IyB7%b;0~8d3w$%gsQ9`{6ZHNfL#TyUP(VG<
zr6LvqIaCvTs+YR|y<c7Ro$jwtq-xlv##tnEqg|s*B{2tBE%z39IA>Rn(x}EBwc>=J
zF=0uM-eXCSP7o!!TLPk%!S_Xt#at#_u0Y>F)e__!;>Ypz_0vJ<Hpu}fJDdJotZE7d
z!9)YlSU8+=(q#|;ou4GBGCuJp3w(ilm-P<Us4z6|H*8YwlI}WK1GaTdFp@5x<^M<9
zImT!bhHJWQ+qP}nw!6Q!ZA}|r+qOAvO?%q5&1u^`XR^CF+5NG}ImvEvC-wZOAC*eg
zlX~B}pZlsMQBq-ic1ca27|*j4x!yyIkiL1&yU0uI_e%Un86|ezRt7tM{-F*Jg$=!^
zhFOtr8-DNuG~DwKl!g)96%HmGZxDADW-wYP`sK8`Y`L8AHmIYLN}*06xQ9@tD335G
z1fKu`aYIE#-cpEsKK*MGyVf8&U6PI7nSZ~^u&d6Lss$24eP*s9Z+abBu*qD35&)(H
z^T2LEORF1-+$5_OZa&JYA8?ELJ{CFGkzI(M%E86Z|2gnytZ;q%%0?e)1c^|~14#oh
z5v8?T9wW!Qe86Ks)^M<+-$Y;zwKH#E+f6X<Dqjgk(Zwxi^&(^*W@!=HrMe+j0n+XK
zYs!!!jLr~zco<cJ?y6ptS3x1b@Rtzt6iMhXxaxU|U24=2R3{XaKX~Y1M_tIoTmVRf
zAtUK+gYenKA4*bp;^;!Z@HS27&JcGQr+PVJ;IR=6mN{$)_-cEuzdLdw$gdK1m}C~D
zOeg_J@VyXzljlT;E^PNf4M|Iigu*{e*heBTtrV+Bg!3_S!c{VnAf4H*1K@<Nf4!q`
zodOcIv|xS>rcK-7=T26`97eO?hlCm^2oX?lC!8|c0s>>GBke?cOdIL2ZLV;SPTHgY
zpl+-tmot^KY#_*m@k$UF1DX+YBGWrW%B>h8$A1)T4+@S8g31eUzt|=9#@u&isM5cn
z&0+uemMvul`68bKi2Mb4d=UwPenc%q2LFPbi&UXcc5Wyn==TQ^9(e+}h9Cf!na4YW
zCFg7z9UJ^Y(**Ga$pKvjFI9Ol<?*C`j7o~^K1*DPzYr<HX0t>FFqup_j^xf}8UokH
zGYNsb39OsAZcKnSR!e%ojOi5Ch`r?$)rh@`f-qo(-I5Tn!bUZi$qCe*&eR0zj%Q*5
z&jAX|0AHNN>C9u`xtRhrAf45c7Qlzo9L5@p+Z@Gu1+)Q7iH$IrD9{5=*vrFNA8;0@
zGCP4bW>W+s9Bk!3Sf7AZ00l;XEspwhCf$ezTX_iUF_0E8Wj_*zt3Hv5HZo<VzzT@L
zQ6I|$8#!X9N?`2-W{qbOjF_`i#j<7r$4wNXSkHm700lZg2rz3P6Jvyeohq6YbmSE`
zWekTHfQEBu0gPmI92sV(if8=^bYUGC$AJc10;5fVajaS+IyeAJU^J`L2o6q(6)>Jv
zZ^Rm>#1a_8DmOxdLv95GvZ{^9;0&=x01zw@&~ODNGEqlz&8J{T{KqqyaUOU9LV&40
z+y`2Kkm=MY@C_UAJ)W6>^FRs^GMV}SMzfs=j`U1sdf_}EkMvAuw&Ofd0lsH4`&ds9
zM?TY7M{ytc0N;a|t2hsIfbXeHZJY--fRWi$0nP&%z{q5Z7}pKR8e}qcgZscgA~2h|
z%XY#$A~2b0h4X+vA~2m<f%8BC2%OHO#(CfY#Iv1f1K%hCM1ZLhpidYpGW!WO&?kx&
zne7C0WNS9lbcDckDgekkl_?J79m^ygAuyRD0R+xu`r$sXk8BNPegWTT0fB>=#Ox=I
zBU`^SiCIsSMm`f+g-xaift`7*?W`wSBmM=f?JOsLz|Jhz51a?Xk*(oOd|WqhK)uzJ
z2k;FEP;W8C3GB>f)n+}B8!;HjoWy1C&z!_@qXjUTP8p3DOyOWXoBa2+7Y8)GL$>_?
zDpO?3|EYN-%m0g*gk>^KuZxRb(YS}F#P767{H(7-ieAM?x^1rg<vbC8+XY{ib`qxM
zN{@TW%@D@qAewKg81N?6rRIu{WBJ;%PdgNwlQV9yU}!^?79>BV)|P0lsG${^PpjBd
zCN8Je7MoL2($k#d$JBu=$h!%qx~n(kCNs(L(dtT#t8LVWo}~Z73@1ybwx};ijf=@)
zsVvBi`^)LkWJ$}iQ@YXG6q_Sa#-(zos42^CC)QxeFj8`g*YlAqr)nT}{`sMS)QK0Y
zp`xZFiz~>L(+01uCbyZU!WNrsrq>*mEVj`Toa`@mPcvR-PIbi)nQXryk42f4YCbn3
zmRh>#X_H#2hE{40MM;}Vp`I+!jiho=5kRGOP(ty;^QvrEe6y1_x`HA;Sx3$wl_xUS
zEtrSqCo*qN@UV(mNw}6AL(7~(bTk^dpk<+iGQ3BsHSPQyz*bHpmFAoklG0VqTs*#0
zq*OfKk_1i8TW@Thpd11gB0-IfOk;rB<{E<1SnVEC@R@fyKx({?_AND8IpXr+hrfWi
z6X-p2_6Id3vFbgk;4|p-FJ;-(<d?IbUbH@uSl^+^?X*6z$=o(+eT!SW*4K#HAM})?
zv_5%6AMlh7^Ml&7Z|sx}D)(%4_h{2!(aG46W>{c8rZkqIiNb2GK&<Z{$-C<J{Brpf
znt}4;ZY{UEa`{C^+^GVJH3E|3DJ{3FsRE+ohp7Z*N7^kX%r@7oaztfEsJ@q`a)F}o
z#KlLVazy_I?&KnDrpY<Hh$$m!c_qdNNcCwGi%2)kNT6wOOOH-dx8%oXX*wg5zfwQl
z$DqFP{)Ro@1LUsDN3V;Iq*J$K$B}8@Kq<XcT=^;6=Vu(te)$(9>!1C+QFUdf{GfSb
za&ShU-j*3hOf^tWFqHOtL!w+=0IaIGa#Cumx>8bV&t+#UZh=r{sJhZpW~elIjs43h
zKOntuCBas8-A`;q9wU-t!f9#)TNgBkv;xi&H=Tg3OO7jT_(MB*5m9bN)(VQulufs*
zHl-!I(X5M&Tgq|G*K;qN;M1HFH+h2VD)Z}0+trs*h>hdPX{k5GwCT%^!}(eSwD>Sn
z3bt5sQ%=&J7ni0aTck3Sac_$@*uzrBo+~mJ8@4Z^x2iTJ8eN0=7He%x{;x;*A(0Zn
z{5ml_x5#EpY|3vY@mP!`PCT811hGX<kkUgOD+=D3ae7%rO%c8(f}uND14)+&RE^b~
zmssX4(Skd%iBugkaXmGR_Fp`#`543lf4-#KZ}AaN63J8yB;05l43%VI^IE86ZgYF^
zWPWo42y-gIbaC0|L{>~0thy{-a|-TsR&xpfyM!#CL%!5(qMU4^Cs$}P#)d8%rEDq$
z%^fmsbSfI{-MkRGb%D`FR^;<RIYoY3Yzaj=8aAbp9D#TQ63H{^kQxcAc!Y(BeX0)a
zPZhKBVF`R38*p&OCH3MG3Hj)V6^+GgI=#wL3DM|WG~7DcGET~t#EP&I2=$P`lJ{fB
z5Y&M7kJ8@J0I*kPP-76G$fnuC%iUmQ&;k&li2ESWZ`e_xkk80qWRM&1VwG>AJwu*n
zq@%x}-uSmzdy3m|FS{P}+d<$xps)0MJgL8s9+`tzK^nxqXGM%bdl0-~Z>g{FUSc;C
zUf@OkR>pNC*nnRPg9IXf-n59mJOuB8<%b^5imkJ6v|jIm{N=b+2K`&=+4`}%p?OW+
zLcg70r`?etwrMOH)CVB|1(P5ISC9Zg1obJ_Jn)rhS@Iz|P4xnvJ$?NFIuuN<5=gwq
zLck9(iX^s<vIk;<a_jcgdF{8nxh<@I<Gfq4bH3BCbNo%aM;%NIehsw+`I^Kx9Y8%t
z3>FCDa1G+y?Hl*OwdVx+{SmAm{Fms_gZ;4;`Td<KbsM4s)fs%xx8Ec9ACA(lsLxKr
zZA-f*drP}YtD`~VYb+rAkK@blp4|Y{f}38H)9#m+YsX(Ef3H^_^u5}yH~N}2f1%fS
zb$PDb2soX7=QUg+<d|0z)@|y~Zub3p+FGfr+kAF%2ngPceeZ}J`dxQ=xw}BOZnoa!
z1ON99t0xG)el3K(%>>DT)&9<YpEF0FyUlT<?<b~1Znw+J$Ut0j@jzUI)6tw%Egn(8
z<DQhZKjz$Re4L*6a>UA0-Pgxzd;Nv}W)~ilv*vfqO4^5Z%k%L|%k%Y(&DD(Y&PLkq
zdKW`qiO2bO{0ik;tRD7_@zO^A?n)QRALg-w-HooGKs)(Bw~L;y={m(XH@#C4A3$J$
z-O%^@O4n!h%ElLG-SV4eU7GU)%?ipz^fBTQ*var<8VNSjq;t4oL${E-Y@*%VQ)Mjo
zd7dM6MzPo4Jr%Uk4bQGiYv}4`klpFvbLtXZz?2i<8|^_9I7|>PE88H(6*>(#tUKDV
zk9(+r(9;vOIZ@a*+U7DYlymy+TeCT#8EEp`4>ds$huj`ykiKw+)ZRn;uCM>-Nr-mv
z6^}z$N4Qqx;SV&X8#eNRJoFdi5&Kq;wTkCCiLGHv#}&wkb}Rf11%lp~Jf+z80eypn
zi^Wr@3!{Vh=T-Y?TI(wEHI+XP!)-~Jv`U#^hx=l>;y~LigSr3qYf)0WklAb9kHw3h
zM#9yngT5W!zh>$V$3`pTkuTUDsvq^*)5(cT^medT#9%x7D5kgGG<{q3|6xk2bCwKr
z4E2mKwJIz$@;nQm#{(AFp}CpE6UuV9pu>X_?MC%wxMbwU`xJ9XmA~6yd@uy;ikE{K
zHX&@->9+_zh4Y-9`2r>-c8{_ICk(@UJK#b6K(IkP!DpZ^!7d>#L2{wjka(~g5gRd`
zkxbxC*iFz)zzc~Ri5ig_u~0y3L2IFE!D=CDK^{SUK?Q>y`&~t_3(*@98ZqWTb-;8G
zbRevuTR^eEut4-cA3zy{eS$6f4MfmQkP1=fKq{e^Ky5)egKb4H3(-_SX`oX<Ex`wa
z)kI)TunKWhAZQ>kK<+_(f(`l=M36}E6CuYS%t6G0-9_+7Fi{|;KuST9L1lwM`jKTI
zUO`|%nESz<!4E)Pf^~x7_aJycJVg-tp&G#$K-l{sSilfK1Vy0dz&JoSMIcqcFhF=k
zpc26-nx*$spq)VwL@J@hafv{4A#y?dVPC;+dH2}+`#=l8gh2ffUa|KIf)hZ9!Gu71
zkfXqMz<c1mp>L7<H-p<joWQ=3Uh(%3`;9?IK^wro!MqV~>Go!WwLzG{jle!(Z^`x`
z`-wqEL4rU&iEjD(|3`-c7l8MMy2bBb46XoC1`9;=2D|0iquJ9AHU=XC7l8AIxMkVH
z4vqvt1|tI5LdJn20NsM-LEwSlfx!VI06_o?MC!o4W$zaZ{t7Mt3j}**-E-_W3?>G>
zhWJFe1@9*e-UMw2b%gXMc81^c3(f)k0NI7y`rld(NIj$hcn6*{=AK+XX7D5^c<>}h
z1{f3QC8Pn+*YakB<(m~4gm6ea^g8-qD|=8ugg`=(`}e?EUO^E4pO*i56#)nU;-R%s
zmS<Mr|5*z2<n=1rA}dumrOcHpqJyy~Urvr;=N`3_aky@m-c(OX*3472;D0|C)6aXH
zp+3Ut#WO)T5_b`9hX;m0%>&M8AIaYTLBib1?2;mcL(Ip3b7$Bk^GV$xLu%V$$rmJ6
z>E0vqQivrt1!~XVV;&_DNv2t_Rbg#<*DosX%>J&A@R_cp!rAioTa^75;aJ4uPK0l7
zW7`#Dg}97jvGZt4KloI!w}O!MqP2dQuN1=Q#je11dN|ud`ag?0;x2)`klh}(u9O7!
zOSRxSh@SQv3*Y7p6Y#c)jyZ|y?>pi1VLM2l77<!kymo5Rtb<Co!M`~K8=m>kO+i{G
z^s~yzGf7|<#fsWx6w1$ASWO#pjUX0I&i}Kh*UT+j9W~^pc0+yFOYVaDbr5X_J4)<A
zcE1vJ9j7kjgx%-N*PU@S;<{c!(R3>Ajm<~Sp`WpIVSf>9Q;#*_mr79%9xYIhCHiyQ
zLvQVeqt|CnI9+76cn<tZ@xw>CamP=+$(lPLP>nA=30FyZ7JCx$UH6HhsQ=+t`1wjW
zzlAvXm5`y7I<YR7CE%Dvl63>iJD8{EOZ6@F7=ZJ`tDicFZa)x2;MfuUHTt+ce)*T-
z*k6?G=s<|B4*flxGD<JdAntco;8j8K*BQ|({wcL<>P~DRm9--Zp@{ey2_Hmu4>F<X
zkl5RLyrO2H3Ij17eJ8PCFcAd24~`&Q{z=B|s9YeZMM6}WbU0h~U&?pPBU#35Kd>)6
zfu+SW?las+{YRdod~~6Lu&sx)mowxu$y&&3uQTFXA2dPcFZ_j~^~TR2kRyM1J>NE`
zpui6b4>J0$fXC+fx{`uB&PwFjNRWG?xdl>p$lA5lxYc3D(&SG}-MON9<u^)^6y;t9
zL*Dz)dE~JdT4}DkK4|7qa$Y)-IBTRXo7)4EO>r4`)fhy~gQ3VeOw1ULw;_}t&ST)L
zKrmASq7`|bE7XeSB`@>xOSv5#e&8Zf+C)RxS<mB<9d!YGo<E~49gL*Q+45lnA-Dfy
z?oX1`fX}tNDFp4cgC(M9k;SZD@}#Vu%Ly1K2Fk0U2^pKr6l2^UN|$A#r)~qMVgsik
zbBZkF&4l>Bq(HF<sWbG=d&ArvE!9Z4`T1+Ya<b5GDbIL{7^t}$!e(b;PQBsjY4>G_
z9{PlTMmh1(9(umXVVlbz=K02IQ5~CImA9Dn6<Pf3;}KMvnY8H9AXT2Bm#<9Fpz2}Z
z9?^Ahp$Z?wuxcK`J*GBJ`qTSbq48qTNpXMt)KhCMYeV+eFfAly%zWt1a}-GCbOrWn
zokTSUQ7T8wk<B)lK0SBKE{-x_Sg)?7AtjDPY4;2}*-#B$P6YJPitOb>_26tXk^^dM
z4<9S5|Mo00a;d)(w*-vpk|K9kM5uMJLh2QP8X(M@TRjpN-5dND5T^%Fj(VtSS)-aK
zi4z_A+Ioq)X&2h5xU*4kc~GcZ(9+P;v!$bf3FqSjvO-Fk#H~kIr?c|2gG2KVuM6Y2
zhaVQn$NfDV8y2E|23Qfsd7y_GiTDKOC{kH7M8Dkg?PQ?99G#d}m*aFMyvViDG!EQ&
zeoV`azo$6WpJ-Yd+vgf5V0z0Gdr<uLv*hteez-NhWwu&3;DcperE!@bQ<tk#BU|pY
zPbO_u8hC*F^*)huN(#Kj{Q_(MVP01mJN6`Fqo6)D3-E?e6SVG+6A>1u#IDjREFfBf
zdAtfG;d=yOP}3|)Ao_VAm1dexLPh{bge{SjHNVeCgE9D(oCEN*#6X;m*~GwV7|J(M
zrK#J&iCisqrsHs}(x_LJF|s81C8vubWz6dP!@y!~PItk0(1xAOOpH{sYx^35d6m|v
zUcJYl!n;%H&NXi+7d17dYQFLk%JsMJJt(FoU1eF5I3{K%Imf&8ny4c)YrC#P!hFPK
z);XJ(Yjby6mS`0$M+V}HuR@RRT!AT&9cv2C!V10nEZ9`Qg82DPi7I*|GJ0bGq;Zyq
ziJ8rJ0L+=|C#0x*Q{mu&=dkxQoFhe!w*Dc*ig#=_e$@zE?5OEW=5bYhT0T&s8_g;0
z;FoO$|DH~bR~F|Xn$g|ylWSUT#+W7>PVvXc#7%Zmr3+QJ62s9=Ou@bi{j`e~PG})`
zG@g56EZrP41miINLYxmAiaJpeAYZiPH=>V3y^lnq&yc}$QYwqNx?G$DaX+r)7tVib
z`~v0Yd4y?gM}shMXg^bTNGD)zlYl%X?{y;H8WbtI*m5C~6@ti(Mo=M}C|*RI*~Z6M
z!d|YFk!LIfc2MbH(P!73*00%~^{ywaW5!!(#J+hyS452jq&4a#wbCMe*t_DNkKDes
zJZ*}3qm;vsaM)hmtdZBPtvPTpm%?~G8BAG8ugRiWiPg2qtiFWfV}n@RJ)=|f7A{)C
zW^QjPH@vJjg*guPbBCfmb@hZ<$5_ZuQoTqLn;}1i_g>13AjoB?8mH5~bU>d2TT1lF
zI`t;qSCvtzT*#TLLr9RPdA*p&D%K3EQmQaS#|qi4YTra_&3*v!-$<Z$Pwg;6+@#V*
zSJYcK0@OXIqJe}*J#>cx8x&GkSkm{IXrv5d>P`jspq@d>H;Iy%k4!kYY3qDS<insX
zq9aRko-5}5J<vx=|BhvaApa`4yk#xIWdigZOaqUym)Vx$n;GYlMFLTk4M-Aqo=jjO
zH0(jboF~u+#L*n$ai$=9%oghsL_>W~OOB5un`2jqD7`3L<IF;+a;3DlEpapHQka^o
zExsQwwQe1re7(M}^Kzdu>T9HtVgwC1Z#s3XoV=k?p2}{w-JbASm#nGJBQ{vmu}_!f
zF)B~55yvD9?{ss^)n%+%t#ce7vBNT6&a-%+So?C!L^y^W?|tp*T=#K{VQZE@ak91*
z3KGrU+2^W>^K7PFsRcg${%w)^=5~r<Wie~JE)tkF#PSaLms=Kuve>-k$Jtw>AeAio
z9FiMPEfChb(11_{(M{469Pahdk|Ln|hfmpRi&|ImjB*i;0__@V6EQzh2n!|;VuM=5
zFb0%$k?cDI+fKxcWDyBRHU}uB&v6PhNi+-S9rL7*c>l$dKE~%@(yc)BL@o~g>7ol<
zk6iIj>fikSo+)|*H%Ec-+8CQAYzG#27LSHyQUmfHKefJHT9sx1FoYa2+vIfjb~s-B
zqsXR)xCtRN#7{|nLMUT_iHAveoxGc(HJW*RQ_~?In*1r>*;%wNeKu#~-x9qcnaL=E
zKg4-F2{I2O4s|(PCluc8AZ+nIoum*1?=O|fRB|#$GtogN6JL8^L0#5DrOQI|XF=@>
zhqeV~?uCKV_4Zf!g7@_DX2p=y%$uzw%ek2s@LX6F{w9hw4BzAXA?xESWZFjZzlR#8
zYscb;)_LLSn$ZwkjJ}ne48$Z~E=ywuIr7Y;eDHhMwKMJUeTLJt1k{Kb<l7UrY~a%q
zjeB(X-${dtD8Q#B?4mFtE@^Bs>0xU)+L*;%%3KT#23fcUOfC+E9?UJxU9+l&yiY*i
z=%OeSJS4)Ao#RI1LlCZGn*(s8+2Ig1PyxnNFS-=!N`H_g3qi*YtP_LZ#mB>5m0c$a
zQJ~^bsEsO}PnJB7BqL@Ts&@id(DZb)k2D4!NwuNn_y;v}vem`m+g4`uc<6QM)n(pp
zMtt&ibljdSl&?DXvTFVy{4}bVwR6S8ydHk-!Q}R2==({{zk|)pK7!Uwt>p|>+aI=7
z88)(FSr2mHN^J#8pY}ZKAy_|Krg3^i6^^1?(i}uI|0H8rAYED<vR?V3I9KN%LZ!Tf
zB;a$L5rP*7o?xiMnz`jGd$eKq{@hmKdQG3d&YxpjdtWT=Io)k0xgY()?&n0-MY>uM
zdLb|A@NZ05lrz0i@|@LgO6L62i-g3@zx+z}U4hFngXfXKMY32k8+;~6x-fg?PFG@+
zJXDn?$0XI>jBlAL!03>c!63qbk^c>=6MBY1dy+CSBf<Ru)0H#&DtI^Y2I_{Q3dCme
z{A&!6DP_D!8z?}|%`+_(DJpbN-Z?<JwSI=Z73pjx#G&26UX`?!MXOckS)`Nk=vKli
zbzfFN9r22N*Cr-ynn$*izC-gR0Olc(%uFuE=y$$GXsQ#W(DkiOrGG8{EAYr*i+M3I
zXKqZYUbP=+8;Og#^w4QE+n0QX%UjCAGet#h@Zk^nOBeEQ3-^qCy&&7W(BEDP_;6L>
z&gam(J70dEAvDU1$j;A3+wvRqNQ`ebjU&vIK_PfxBsgx31S0D894a^wn}nm()olP8
zDjr5MRwP+?0B-5D3Izaj5i`qR<TM?2h=O~Thbw;Xq*f|cL8*k7tL62j%(YCSV7;-;
zbU;K~$>_ym`rJ_VhL!NZf-7O*ERR1(bmC3fP<7LNTKzQ5$$q-I@|AvyDU@u6Si9#v
z;`x}nKGUZ8z*~h_wMt+{aKRxuB`4R?V+d2(UifdPU3RTw`#R&F^dMBr6cjy*vy}?c
zhN2OQ>hX*`l_}tk!~scag(4|MlVH9ir@ymQ169&{(qcv2`22+gWGt&tDr<U>sww1^
zFT;J3H>n(?;1F2<^{o!ZYlCa-==H50CM#gU+pIM4?o)X5vIjq?;O>C%z_&x3UanLX
zHH2Rs*Eie`bUPUz#ns9nY^m8!HJLux4!0ZZ+n8-)eC!4ncV9ui6x$8dow<V&7n_9*
z))@A5R$Bi2Ex_QksD(p6@Ofy9LFZ>RFMJaz<|^R|nZB!2$Og`)9YKow4-)GkY28tA
z^KUc-XEREdGM>AMlv@ljtktMNiU?K(fHvKfkhHxSP>ZkWf<w0<<J^I$n|+`*j6{mp
zm3xOyeayR?K#G(B2Q&BX2s&m_f`tuT7_m%%Hm%A->S?STwM?u+GkPb<54O}qnpXqP
z(#+V^ff<2l8#H<kZ2%u`WA0f_=3GTWY`ehOiEaKaP8ZSNl^OSu+)@7E)g#5alMQu5
z=r2NdEjspC98)#44YT)8|CVfnfg%k%z2pF#gorfQjYK*|Mp9`>SE*E%X6otklS42;
z7kb2EvN1Veb`Na2BZ+gPe@SCG%!P8@jFw|X{pN7Tx%~xKj^+kEx1SjSQA#d;r@?`I
z+emim=a`U^<2?_7V~T)DLWlaVMr-+`J%+fU9JI|-8G`oFI%=i`Yws+zksBVDb)EAD
zbOG}LPqs)uw!jGWD_IlIH&W|T7)}`ST{|*nvQas<h&!i#41k;8GP_w+--)&Yhos9?
z<T84Ka+4TtmR^c8N#ap6iejE;d!v2KxYFrp+IUdr-qsNkj?|8lqugNTkSm~enn?QE
zGjiU7l};+8j+P*Tg8lc%+99y12_j*0vg*RgQKqt{L7wOBcGyqz>?$H@_=Nw2vb~K-
zW~2b-g6@?>Rbuz-BN;9ed5Q*hIq@S9Lbrnqr~dA?N(`x%c;V$O;^%j;`*NwuLGTV}
zStQxJ5G^mlMYLwhVKgkhxfl;CDNnM-l+fRztIdR5ZG*OtqAPu*8yIAti?-I*JpG%8
zCGhQ?z2k$I&*u$Z%nX5FUaQTkQ&npp!^;k<k}*RU4R%KUha1IB-}o{R5P15CSOm~6
zw*+{QlSB|VreU$nP-(a+LP>I*-^z7@*|6$&tXPkK%4AtQWI46|R-hJ5l=@^!NT@S-
z9HXzcfBwn6uJLQIx+XIj)iVySaCYI@H_?seH2;{XlWfgGy1rrb!-|xu&#OesGDs1u
zXs@^IRHY--y_l(yKKR-Kdr3iTc0+!Gqnq)iSw!JDNo0<OhzS!BC&uUK)z!dIzoq@j
z#Yd#85hM^h`~=Ai6F-l^z}AcVBRfAtncQr<3j0}Bo#Aqn>@yQ5$3ZN0cDK0k9bjlw
z6JuPcJe8T(9I`DOMlv%Ki)}SLZ9nE-_Vz2nGwoB*PAcFvqDJn-oOj9<C!$BK;`<aB
zljv4zqd?SmHv(C$HAQvTCwesvL;ZK?e9!0s6Pl3xg-`5=JHS?Y_f#o3ZKWi((qMvT
zabHA<L>gPV7d_OSMW)r%LUjDp<#@q_n1|^wfXFQ(i#=3&5w4sb;*%shWwhA+4qP?b
zWE4_N-=UO5=iW!c+L7uCS!zmcArtpmwM#>YZ=l!0*eh)+kLFKzHKm{KkV2@zgbPYS
z)nav5%p%_X)<Cr+VQjV45yQGFJHW`NT#2VXm0sO)dQu6lVne+Ko6%4sFDB&=7k62<
z!B42x0o%r5-Bg!e9(_4g5(}*{Ve;-KJ5O&-!<d1SxgoiAlL*dG_8FTet5Hb#g_PuG
zx^y&TZ1`tQu;*jZ@Ih-)G?t1`u3y6-&6A?q3351;x;*ZWC8OiliNlge1TiquV|!zG
zu_~kBnRl;<U{`3r9FIB{jy!m_v3`%aU>UhNp&LFly#Ato2HFH<48owcP0~;=q8e;F
zh?(OB|0F1{!9})$5;i|%h}8UHB;H`R1)Ii3?Vd@H*hTeTun_%i<?o9jI154i@m=fD
z&SdO4`7Xv{+`VY0^-7n4iNR2JOE*R2m%GU@%I(x^qZ#OVgLvxpWq&W=Bd_fw30AAL
z+3^G@LXt8{ye!z?Kv((Ih$P8s!beP?6m?f=R*Pa3sre_f!zf1s*rdSX0rP?A-YmLi
z!^7se#iT(plyYSc1=iV#e)5~)-#YkoMOK3q)N2r-TZ-*oFiWD~%;kf@mB`A41)Gi$
z*2TrBPJ&3ey}<+T+a*Vy-rlL8Bh<KfA$c1z1F>Gv=@CAQp#B$59{r^noj4sL-OSjW
zIpQJmP_>yN(D35rjRSTlm(jk(?%vnx(eicaa~K4N>g6ZDYuMOM^tOnP`VUzIcqIob
zD@5uo+M7e=ZY#Go-K|+{Ue}joZc05XSAVg&`V-^R1X+$}^LFYp2-Q#7ctud<o>hiZ
z;gg+1Oe!Y>`w-cgporZ)OiMCMLTdCfvpHwu+*I4g3K<!Xg9`sxJ$bp-3G@$I=J`%D
z5xvgB^9vEZb!+(61qmi%URAcp!D<F+&vf+f#CU(*>3USIJfO@WECh$mFVML4ZM%G&
zF+Q<%(h5QZkw(y4X)yweLeZ;XDD<J|J7^-=`#WkP^kK{tZYs(t<HA!#T1T(`^5k#B
zy6<iYhdbWwajJi~66u{e8O8D54u~4L_hchCg<>}GT%5VdC32@!o+~|CWKyslTy%EV
zqL52Tn=8*xy6?C~aY)nSu`4BNBRS71bG{0TQV?@-&jT)4ewXDX`O*GCwHlY?n>or2
z)U57QJg){r%Rgy9O;O$}_Y#i2$6;{zIk>>6B(5uP!&qPl<lMx7;7~VXq;UqsGEp!3
zY02nYqbwl)KVbv&G~%3aa36TRu~#L$)<~je`)BEw*rFwF8V9zz%{eAA?v>%)ZYl<O
zZqFvSEQ;8S>VV_(*3JN=_19_A&0oAwO{lr-z`ukmMWqyigLo32kE%r-2?jFHNv&j>
z>U8!3*hp?Mjlci7M<!U0oFx-ZOj1MLTo<fnaYk4q@|F8xVUs(&7A`EmbQftvNnMOf
zLoZb#__!D_+iJ$RZszwEkeZ4}?EehC>TT@9*)6m3P@mkvoHL7_&0&ecu2KCET0Go|
zE?u>;{NfdRZ;c#QOtp~b9}}{qSraAK#AU6>Vy_B^brkd~$LWryL>us#IG?g4m-p^n
zLb-75@{nBR(sr^{qF?_!)a19%a)Yz<Shlpqz$=rurqiFxSoApm?9bEIdQ9!yJe@HT
zo~)lAGsl}QUZ4xo+`WwW<_prC*~((dT*iQk+(A8k{GFw)?=>xqm-3I3yR4=K%C`Z{
z_g>--p8dnJ=p!u8=$4Ppss2@kLVIg@7PCz0K4i%)^3KXMgVQ=hP84|w28|JFJSBr<
zUf(%WJv?o!dLr*UO@@>paR<B7O%oRnE?AJn0i&EiMFQC9Kxf~aAm2OW5!MEu7-4D=
z#+8=b#zM=vAPZYcsLo<)Dc6)QB&o_gYG%<nZ;3uwCv53uyog#`S1qTOX`m%vD+@(W
zrn8fUG5*BKIX=m3oax`dX(hU*j#jTwy{2lkkbc_l<lu8#Oa~}rvB(R##-J^IW4IK4
zdr9>#Fr5hx)u(%ToMM}%nZ#RPZEEcJ5MYC62E+Axt(a4IEJYz7hMQ$QOPOB%O`YvT
zOqTGTJZu#ud%#Xtc!SPK5q$vtj%1U_F;z9Rk%)9b;M6%p=Mcy5g5wrB<?-2_bp($j
z=YY7Lo<^v`l}y8kgDK=(87lWqlhoYkaqiiJSwxsAi!4oc(xvdd4Re0PaxNk3iyK3O
zZ_`0_xf0VI)&yIF8Z~3i!IPr6QTybq)>+cg%edqLxS3kVe{O}&p|{*fW1A^m{+B+7
z<tVs|e@(-rqk^}TSP?AD!Uxog6rRBly4g#QC0;i&ccxnNu<WKCzfycA>h#(VcNiEh
zR5pz-QA_(pwjI${2pFv2jIo%m8Nc~$e#BX_X8QRyP+Dq{4t;kj1DaIFcWHnHtZ!gq
zw5K~_!y802Fcmiy_c-6w735rYjx}8_mcp2%<~YM6kZ|<RGbuC=iAuLzJe43MJdlgC
zPd5MMdAa679+1DUOAM4+(Y}D+4kxf>;c&(?I{Q`ecm?y=C&TlDip>*hhZF{LhIEbf
zUt}Xkju0!@&AjNU-x9mB!3NxYS^_o%m>CO0mfq)ztX$LYVEp1g2X)B~%i62Vd<{aP
zuy%pnn`8;&l`{;y4QizJ2$`6+1%WGr{@P~Qh4giOg`FZxns(<1qS_M8l27oE(-Gv_
z(?83z0Ss9I+zoP7Q;Ku<olmXJ?@SkbZ&u;iK$O;yMQ)}#8GAcHA71*T&-}x!PEOjg
zI9$Gx#mu94Wp{PL4+uhiM5L6F{RGU~{bFN#`ou}Vr1~V+%xvn!GG84}lX>I-R9kTd
zB)$#{^_G%-KOxK}m+%y2kx?lqd}EOildEwb;`d1<(NQ)j#0*4=^X$2%{OS^4iF}Q`
zdbU~zu-F+jLoHP;HRrpny$s4A_tM#+<frHc2?I3s2B>PbHT>XC*M3RuDk8eVAoF9-
z5^fwr-AYA=I**1q4Olmduaj&LKiJpmzfOsbI!nSpMy(IZJC6Ij)f@h2wEdhUbAaWL
zI9<PoDPy)iCC<P-<{Mq?@O{^HfO}5ZF)fDx))N{+jPGj<-20alrGW3ru^#33Y1Fd@
z{+JWu7d4mjfu?`FT+NYBr(V@hd?_NFJN&vOrqTqN)e^%;#XNEAi)yNT94SSk6r^<2
zg2?6d=BAuIry9z}C?56Al?5NghYn!AGctFBmC<ZdxYP1grLL4zy(<9FCRm-L32r3m
z%2W4Kpt=&R&7q&9i7Gq1F<RNUYMhH;mQBFrvSYtewGp}^FyD_T(icI{1VZdDKUOd1
z4|aPDrJ}fgUd#0oR33ReUc@OMo4A;JYX~LEOOPKH=8A2|2jnA56S{T9O5^#V4k5TQ
z!*v5;{YPtucAH2UR?Vf%JBtfVZbr9?Xnr_|PA8hbDMs`#)xv=p7iK9<2Fu&~uXVmD
z5>;tV9;Inz6d7gw2kfb8Go|zI52LxzZja~{kSzIBc8S7A)iCLG1sVChdm$@jt|g1P
zXSmV3jS5w2avq-Q{vld5=^q!|jHAZhXr_!z4fIBtr!mvj*-5*(W$e6E*+_Y04CvJ8
zEP4L8>&Sn?I$yEQ^)N&r&qztBJTkCMTWf+PiXo2>bHVP3#6Y7>;bdggMaoga#N5k~
zqS4)Datp=H-0{$;&ro3fNX{D6uqiqzx^O8>ey)n@(DPQ>VSLJH!1&6oZ<3o`ikIX!
z#&EWzq(_oH^AXzk(U5UaZ9<C8vD>VAnVG|q2l%rJosdIJpWL;N#r?#(x72^?{k^Tt
zpfIBsc-2%6Kja#lBOx@=J>jL5DwYfGGHZWR>#Ug^8qTYakIiA^ZSr;k&0Jm2aJuBm
z=wl&4FRTlTI&)9BA0zk+<u27K#GPNH>x1L~xtQQFo@5)hXlr5Xsk0|*ILZ<^YRdk(
zJh@#!E!tf@dQClijhHNM7FiqO2EkPn<&P<v_=(Igh%DKNsF)F>3f`xDRL`%SCF7fP
z1M+>Mw7pYG9kOV|FJ2X^pbGWXhC}xWFEjk#b#$cHyNyYZpSlfDHX;(m9{Y+vokJ*|
zR+HSqguse~#kZ=O`_M)CLgN=7x^#~DlXUQ4lSquCp7}@eS@K;VM1^Rz=fZP$Gmdz8
zF^rdY39hRUZH{blXMfyG7&emjd|$_f|HgN`F$xg3+A#d=)VE@!mEGfE8rSc05bavF
zNxLARs?%*y<-a^hz8c!(-VGA9_+5U}n)PB(urrq<Z7Kfu-v*RXCSvS-*<gJ1v<R32
zX`_3zOHb_Y8z$C%ujq&iGU57U)*)emcmFkWmIJ6hx@`R`1POLq0mKMAQ?MzrJLOyJ
zXK9XzDXN6mp%DX34lqu3u=yw*?aYZLIb}Z~-g(J5!6uv+`NwmLc5N_6Nyj*4mp3<o
zt_lp>vZd0X7<-a+Q!~C@6Oy~<x8CelkKQJUrl^%1fV*0mp3STylYx@pXtdWl#E^bf
z_nD6GcnC(F5x^6bc`ve~2!&!fwykJr5P=mC!O1F7JOZ|y9C#laHmzkRN}PqeR9Rdq
z(pnT0EzuQGE5%^w0bhMk;<0=lJ|B~v8!?P0K6DZtizljL@8HIvABEkVU^PF=djxue
zx}l#jm&Y#lUK5)jRX7?mXdU)MyDi|;N*?uSA4`;VnIp?51q7dIlu5=62_=awoiGoN
z=0PekC{CqqW@iJ)os{F>RHzSpRnS?E4E`dV`MgZUAxt=yN=PA)ud1n1)DvoCc_YHt
z)tJsU%+lyBDK2FUs+LSUa><82=5;+e&Qs0FBlOc(r*Q2wC{wY~Fm44yf2><06U5G%
zyE+pW-CZ^A`}Qn89pX=Ctg*YH+VXvPUntCmfS%w}-u8Xn{1MT)*64S#v(4|=&`Iel
zsTuSVf3}nDhNs2ZvZ}$ATCFK68xdbw)u;-0Bm>3Jsb3s#JAfjgtjtIjE95tYMJ`1u
zLW3f7E{||f5;S|oslA03m&ks#jT)EhTQ8Q!!id3TnYb9fjOr>TEzbc~fl(`wOI+D$
zK7X41it+n^6`aQ+%l>PG>sYYFXI>j;bP&GgQ?~qFq_Z*KGcZeD;WuQt*`jQibb<-(
zct~0QJ->eAuZcetommWXkelj1uGagX6_A6~6LFr9SvK*bb8W+;Iqj;|Cu`|$k?HCN
z|Hyi-U>*W0bf7ZkmR;_^Y^5g_FRkA)E$Gg*GSu!NTBow6eYPv~PtLVA<a}4@Dfir`
z@_BAm0>0oSg&BP?YJb9CVcP%f;wz#|dfj!8i_0wV3k;zh2!m@{#GIF0X5>_yU!W^s
z#9*wHwTW_=gPGCcpgl-Ruq39WN@En@!n~sKOd`W0b&$^~MqTJ4!H5I4wkK>#)8_PL
z7Wby5|2q7gEFHbKP4cR%tg3yt#I3RV6i9=Zu1{KiR0gG78v=7HjOD-TomB~*g<u)n
zdWIzmy}s^q#Q9?unK34TnOe!j+Ch&f@dK}B(r+3GJbIyy{vutIQc}PAVWK3Cvl(x}
zmf&E+dFwRAV!wI)F^N<)T6S)f^vtYmE|Oi0&qg*zst{jCPJ+taoH_68gu3plT<7cW
z=(W+7PU3ha7K7{N+J>>pM9`n(nudBO;f8?=p2?WM!X8)d?4nCKWC(y$sICjQvjzF?
zh8xnI?!L0JQWw&!fo`X>8Pp!{=<-th@Apvi2DX`B0d9YvIRCAMw4WF*6C4|Kx98^P
zbkGkOtZ%u^gKgt^E`XZLs<du9=G~tP^&jq|gh2t**LMHz+S~KDwYlqy(t@zJohy`$
z2L~D9!^(jy)$1R1!v}3A@UK<>mJIxVa29Q2!`0rBof?*TL^VHO2dQx%OcRu&-$A4l
zGLs)#j&Huv0d(A-oLq_h#5JkAE5s>hd+^^vjkN5xWlpz*l@iFV7m0A41IR60eo>sd
zZtQ9~c6cSfm-Cmb>y5JY(XE|fLjSHcN6<7U9qKj&x?jG!4U^eVbN-I|H~KQG7$@~;
zx)K7s2h3Q7DjZhytPTVr{#M*@YE5qceEmpmD}C)K#Yv;1qGb{qFXzaUgkP?qv#*L~
zN>dp8K?nR7^JPIw?ZrniI}9a*{9{e0PrS<gwQouwN8tRjN~L-Us(T)tUVCgnxcgG0
zcp(8I`dUPMkSC9y+W|l6uxKfM2_{VQ;zqq}(D+AA#|EMNLYPm3zt%t--Y*TkUfvDE
zU!~=YdirT6v{C7+=G-i%3DbUiIt3PFR^86Cu!qTATaCzFaN@?>IVGqI`VRUWV(;|K
zQBotmxg6+X;-}5V`qWmc3Fa}pckX$z!fGQ5OS-^9c2kYG+P7-fBTI3b-=qp@nuQA-
z#FZKoRV}V5<a^Z&U}=1PZE~|51}zne#p>1ux04HpECuz_Ua;@=l`v^b0zhHuhom%k
z5?ncmSpq%uWMsFb4<PAl&JF&_NjQK|e)Hs1+OOK~L^@+-%7&&YYo0`YX_(vERu$8)
zn!oLpz-=%D{+s6FH7u%vS{Uz#WBN>jl+w+Z&<?tOmQtWa(sj6A#hUFG@`-M577g(7
z#|ApVGX(xR_%GrYI}Nzz#>MK4ID@IB3EHDSz%1OhhI|Jrs_5oAcW_$4yARrDp)_^J
zroaaq?OYpxDZ*})QL%D9^9fmGgHc<pwIXYllU;~tj<F6awq#7bABwv_s#=Qfs%L#2
z%(tzE#IHb(hN2U)R`)_r?KJ+bpT3IIG1mH;E|pY#4du0_mZ5zkJXm6Jh*t}0tU$a1
z7t!UEQ-k+x+vK$;DK8E&J|}(DxWwzzWeM^WB@ywOpGii(>2*(kz4`Kd*OW6Slv%kX
zYX@`p2)Ln5k3xB^#g+(qpZ)*j3*;^E`dcO|&NlNB%u;XOnZ#(NDM6Qa7?tGv@_!5K
z?JKyVn#fel9INZmwX%FG-Qv2<%MDm{Z1>V(W+9*O`I`$hVwgw%shOHzuq8J9<gqQa
zN5jc+N{I6Tu?x_w!qwtm7HV5V{j)h5@<;aWF$hoS!7DH}iGFxI-U$~ecITOyg{!@I
z^Xx;Ckr9`)U7vC6%GruWqen|;$lfqr6arTplW7Mg<g&&{tC?p*C2gNRUTgV?OCj;>
zbq^n%-mpK|Iqm@XXI*C*8jR`}2SdD+jIieK`LVG4%M|H#Zq(Nxq59Gw)6mF@(9w5B
zXk;1&A2E>2SLXP5S}uaK>J#vB!NI^I53x_&dUAOz#fI5PS6@F)O^5X;Z@nB*_DBJO
zCMG+CRr6I0tc``@pUWOH=&j3RVUh3>(S>yjYJB=3L<wk|*=yJqNDSzF&i`J4D8*PQ
z8DcI)4zfoxY)qMMSfxOKHQcho*4|U#_Nc1&lMQ~?vfag}<{cjI>?DR-c=+XCOTWig
zDM%kNMEC@5Oug`bpD*<7BPR*16Gh1qHc`s3>(zdPF8=ShZT?lS)Ym9|B#}jQs<ubW
zQOa2wgqO7H1|gyqsc#qD)BElk^iAz1sfMBXsGsVx(QZiV)WW$f=Fwcm<ny)7<388n
z=26pg^~-$w%;)~8xC(sjRBFvO>XybWt-eZ%iX07p#4?y@vvm(08aWKW;CM)^nETD+
zBAd(H(|Gq`56&m2Bz~T*^je2K=0T(9&G}iXafp3nq@W{69s!)j|DD->xk;Vugfp#F
zcIZ^@yRI)6il3^vj2<tn?=JuRltOo4s-onJ5Zs_#ONIX}#P}1rOu;c49Vs{<vEee2
zXslVbYW%j`gcz$4Im`S`B0N8!b|z;*2aD;d!`w7Ri5g2Byr|=2ic6wbp3m)w@0;yg
zRwLx3&|;0s+q#CfE?YpoR?B*C2*7d}@#k`3e|~mMJX7t?hHP&2hCEX4Sg}8%)fe5-
z+Ew-u*T2m`DL()=jG8MUqP4%&V$zVw$1^)j;28Eaaa6$J2*ZI0oWm|>AGzko`xCCK
zP~WwM;^d~5ot4nvgoA9{{HBci3#`5)8??R<ExI0f?0_FaO)!?i@<cbo!I;TTEciup
zxArLCkn52szOY}me~jX-Ygf|S$x9#1zKKy60s`0NlRo)o4>HJ{;qKt=${x#jhR^}X
zEd3%n!-O))1NUQC<bgMNb-(V%9<H_oo>Momz$dA4(Q*7#<NXD>5>rbLe-i{{=?48^
z=Bfd_<n}mb&{}$4cOQQ}EV!*~wVGb_9#=s*l~c2)9(z%rFmx7@mTkl#N*#{LI7v%+
z(3E?*SSr$#Tj)Lr3($HVOP(&hq<6ed3wa$3&gD8VR=IGg`}Q#Bsk`jxUP)4Z)n$D<
z`^C3Y2ygCN%j7NN-g>2SIu;a^Yj{fw=`{_e80T#5oX*tncD6L8s`D(UCD%1i9<s@W
zS<RUcx8Ew4=%TzCkO@>x#uUi+z%HDtVEPnSDaMOG+}kzFos7u)H;*?+S1d1s^IqCD
z_R*KwmMCKb*VlR6KP&gh!?+P!(Dllb$|K2aJcJhh**{+KN}s*R)l_L8bwM9lgp`#7
zzXDH6nUP#s*=IlPd6`|MDVn<}SBv*}qk;Bt%k|YTUTHpRf2wOz)(%fn|4jVBc;+~7
zfu8wp{oqqyrmE3$YP259?^`$ZocZH$rbsKZ#BKEYaGXQb(YSHOET>yj$~-_X{mm#4
z!c@1lsBSMuJ4@kqE)+%Ql;J3%d-f5s$}~N|K6Rk3#P0WLgGC&a{rj}ol5KZnxMmz4
z#P(i6PcdJqCLDUv)>R>V@Q7OazzRlxKziX1TFnSokSWA|;%g}RBc;^7&G!IqJcsG5
zHZE?BQmE>p_CJS5*W2i>kj;yOG-Mw7wCnSV*%N1L>`d<y-<_spTh2sLtaM-h^a4r~
z8FN?8_j63cc>B)i=5V`%Lve0ck8WWIdQ&vfBo*AsGf6w>Z!-F{a!q>+%mlrxwK|fC
z4~=V<77AgVpfS@*O!HSU4jQ2p?A=I|{1Ia3M7c=v7Obf2=)F|qe2$dcL~l4})Q%&K
z^-T3xxKIed!aj4dy6%{Z)IKm345Srbr%;e%pFj7tS)A?;Y~73JH+<GRe{Myd?;!4g
zjt|jPy6zcL;~aszN+v!>Stk!Ax>bZ?2dkU+qmQUY)<F$&)=`>roJhDfF&ptwvI^Kj
z6xwnWR4uAx{XdaPU9^;yk&@Zl_OwB?a&&UF+1igYGBhWIbVeWyvVYaCW?k|dm_7|}
zc>a7}{f474Jh<l{$>_k&qazeBCha9JUrP2GUa_e#N{!FCUV@h`=TEG}<V^Sqne*Mp
z4lDouO=6i~tuyC>xp?==45j&H6+_gg<*T`HIxsu?`z|EkkP7@xbhsG;;b>Gg`SR$W
zTckdFFJXiL6W7YpB{%Cgb`Yd6Cb1JZmyl5Gw^`!trs&`-6zp|OZDGO`WnUv(JB93}
z=itW>asGYaPm;n?=sT-D7DOE`4dV=&o+PgB`cgW^KCZd})&ad?W_ma+HInaZM2Yf)
zn^Kep>QBdx3lTvV|46bYkLK_l_oVS{RyVZ1O>Zu3Z>n8u%)U+%yxd2hKV;Kz^0tz`
z162DqSi0yNYLkobTnRo3_s2^5xuQGH9u9$ik`bhJoxOZ6`@F5!F1zRSJiop2jo5_p
z+uOK!#hX*u=`Aw{s<;~8pj-08BOvQ8s#eA$c`);;bzPwNmchp0pYLq%x$yFmWbCD>
zX-pkM4yA`>Wiu@_Y&_TrqFWUVDXQ^v(uQrKZN@x;l@$Jrg>kvZKGHw2>V8_~XOBPx
zs2^%8D5iwLid|B$qx)EWb0(6#Azi755CG)Wott1Qa9l)U!SM)G_JRp!_gvs24}Y)T
zA4nFB#LloA`8zQfVb}`5)*pz|)ixzM(dk6VFdj{Fz`qfNhL0`ZgH(|9@w-bT;C+bZ
zA>H?RoL%@2WuouilHSb6nprR}p(oH%y;B<b(-b$58y_5x?Cibq{W}`dZ#_20T?Dl-
zwVNyo<^-Q?U(o4pLlmX1YIb#1S$c#+{|(sw^1GPyB;0^$K{|`y5S)Z}O~10K-CWd6
zY<5RZ+UZTYcoPnJ9Bb!8YIO4OcGE1btCG-HXBDnQJ1#*RB%%Kji@aS%+JDJ9^Wrc6
zl#;G1ItT8a@qA$O6&`B`6anCx`5&<PdYd^q%{+NrLcVlsnHK*_Z~66)yJ)-}8s=G+
z`&oAR`MS=ST2WtKPTB8dP3vwL9;a#jLmEk$GV+c!QNlypBk=5r2pp`N04C+0&4x^o
zK!sTjW=!zo*`W!%`UkE+rCD(7p0$^^+4;NS(r>)}&IW03<X=}QHB=h~?AB=SR>Z``
zD^jRj&M%fr*@#L9mA;(h&v+<$-V$^B-#vrw6d<PZ)9dAYCcw1_7_8#5$L+Wry!Re%
zZb(KkP7)jaYzx?AbVVK|&RF3bzr%-iC7GfnJI0W8#hiDInc}6;1J}Zsw?;@~k1z+W
z7Y&O`D*E$GW%Y=ct175AFEkPu_a{>ys)?4js4P@l&rzy+R!_pljS!F8#OXP>Kq|Jm
z*K;<uR77;?=^OAF&y`Wair8~@L&iy!a8XI;FbTN182|eBA7LMcbIAHJ>dnL~5a};c
z>Nv`tg+dA*Es%kjm&?^Gthxy5BSj3B>S=+g1wqO{43|nZ{Kx9Q?H6JNGbnL6<sxYD
zqL|A608l`$zt=jR2Y-?%@)!hfv_%Q>z}+ysUO{_8i))iVYGQsZj0>BE0|Ft_fc-P#
z>KZoxQf{nO0x*UCYZ{`@TKcaVBw7qLC4W>Bm|vGLffu|2p(hjyuz!~LzlJIEFDuQs
zO8$jnME@uJU-)+#H@<6GdQD&2%#euRD_&ULT-Td%M2h39CW?{R<dMnXU~9~zA|MiC
zXpKKVl&UMnOwr=xsujfu(D#*KE3w#&L62zXRSvJi5XgtZ*{H`K?_AxU+cH$IHJErU
zXXX(HkJ)Ax18HX@7xnt<+E-$7ZBl!w{n&%p?`8giX7D<;9oqn9-h~|iKRFYOiAU~4
zey>)}#_jFe-X(IJ*tMM;JC2PV8T8Cu-`~7pcmK$*C&wo@Pac>gl9S2FHI3g4?;c+B
z%l@%DxjEb5J;)EHku_><7(I`i5iOD<`jvAA*$ZKiL*@8?K|}-cV$ST5!RtM9CHY2^
zBd}&B`AP32tQqNEyBoh*f_Lj*^UD&vpN*R<*#<TDNS-l`qK_BH)5irFkJK)1x@6Qm
zzO=qfSFGQfwHKFhjZu4XQl<4oB~PaN2xp+wI`z%AWOppulePz3Y62}@_veOdEBVSz
zBr(3H(-t?FE$I!nubjMPW!=x!It^KIo+{2U!7Q*WS8<QkM%6d;$BM&Fulo|MqxH&d
zt946Xn5M0R;qLtti$eJq9As!^_iymM<WpEHc8{b#W0(*~C^{jb=!%4*D-z1co>25^
zLUN2-bcwmZpi4Jr8EjZ^r_P;6inCFPs6T&BTH*#TJy(KdEk%oNu4EZhHPpIC<97ah
zVG;k>Mefhb)Ed55&3j`>OaHc_>!@63w^q!7U!d6_DD9>JOVDXlQyOZqD^iyA6`Y8Y
zjL5%IH(}ebhotd)va2hztr5MvZJ9Hi!7_gMt6RHl+u+8HbYpng+}gn=<k@Ei$LdF&
zgXTGUKpBvcj~Tgsp=8b}p5^mOq@d(d=9EjUT{c%*J1Ad8SCTJ7o99aOKxK4Bu4Hs2
zq|+8VffaYqW#)CRyd0$>WTG`NxOd3kgJQa+DS&ud^6-9B_WOUUGF+A8HDbMd9T3kg
zgnUabT?2cW0P)%h0H1K#N<!>QuvUoQP$@hNK8s<P3J>9bgGigD<FCUO-6hXto=SD`
z$g+&P-Ej_SNiC6!cMbCKxwhP(5iJG@jcMe?Am^d(11Twl1-bB~8qvX`x%gbEt(Y4O
z8Kw0fQh90phZH#^#V?pm{}U;H)@`mV@+zmUQj!k)TaUhTc`2><W%37b=y*(#iymcf
zjW1g(#rx>Gbx!z;<>D)`WrJOVZEfDc^dLUCRv(|s4H{5K4UKK6>ENg>pPQDaO3tBa
zt?F7UMRYd#GT0zLh_l3CZmk{(5{l8Fh*7m+QTInpnn$ZSE;Tn|zGywir6jsQEhbz_
zPmnLG1$maL;4XL72plI=oI84Hk%KQ+=0&6xR|fqr@&nabuk|h;uV)mg*HngJ6m&Y>
z<*EaK3e{_Q{?htJwHfN0_ha9YYHI7D9#m5sk4KPWy8HTW-j1p)9DY}LqB|Eho5Q*8
z2@2b_@yNa-`*tyNcMlvNJT%x7v2UE)g;vy(r`AG?0gz|g$Exc`<oe6V9#dFzNF&MP
zd(CuLr6%pth3{tOO4Up6+BjF*HMn*_s>-!v?dbZ?mXsUF>nG##bXP&4$h(>qD3|U!
zSKXm%s=qojrrJzW8d_zN=BPYebq$NbC(nA-*VLv;@I@}sI@G-HZQBNT1<jU)y8ODg
zUj=iSPJ5Moxwi30YE_yNQ#2yILehw5WQ|DS6^%%D!JfZc_Hmx_bS{?^;qJ_C{qE`M
z-Fm{Y3`Hn(Hy|I}sgPp@8h0$)#s)__2O9?Cac^_F8E;;WIp#uxBvJt;1u7~EpdgR+
zNOMYUNNPN&<(%9mUCLcrxE9vTH$!#M99oWr9CM}6pox^UfT@B67j!^%#`~Su{#7Vs
zu)Vg51yAhlsu=HaS)}LTAX*LT=g-Bjz2K!2tczKOpI|UBw@gcNclK5iPo8>8F
z0UJS9Sp->S5k$Qmk^GJkUUD#kzdS43w;lz_c@!iEw||x_V)Ow)IZwqz_9%9rM~d1O
z6GIV}vJC}i0kyDbQl^GeOtM#M9FC5nMma$rlorP<ER|fsSy){uxrD(e-?Xr1@}nw)
z%Vcp0^w=Yk+p03TY)K8KJCF3Kj2;w=ps9MZZd|pjedj$}aeu`uzVL_Tn|eZPSK-&!
zdi?$KZxTnK6zhRb;b)xxbJ2pFzaBOE8}b0R{J{;(iZo2h*0|sjmbQi}Px<_Bi%p2+
zTmWGKM0gOTfIkWkbofEg4}9oj!3Tmq;FXSgLC^~#9Js*;d}x`UMlcQfywF~Td%rAd
zAjtNi^_gf7)t3)lUkgw4MTdN>eTW^c(91}&$KunH*DEgn1IYI!*UmIbL*O`z`2bHz
zH)7$9s@ITtXyUNDDau(@C7Z9AX{<2rxN+hLzzMv3Ug9QlM{Rnt{2h`4YSCkH1w;*5
zCW*h|jOcS%+=7buIH_T@s<%FexQIx#o*~v~4H^QrdmR4JT(E1k_|Fl)4z6ZVz2xTK
zr0#(A(gzykdKs91vDg8H(2S<(W6humZ9_>A_JOb$ggqea24NS7I6;&IF#@!<fworA
zmH_SbfcKif7_Ur_p>2_Y&7b$eEAX6h7;TGM<PJiIxvn9p91?qhU(WC6kMSg5G?)kZ
z#-Y$q>;3hh9(`AjJR7`d9^6@fV?Evnk6K10{P-%8`SiI$;XIVNTr(-zXMv&m09CJ~
zR3$}M*AT~hcyudLE8nLm-DtcX5YkNy@FwB<d_9iCrb^1Ufi?CjT5ulUgzg0K=f-I{
zNSdxzU4=JECYicKE!KRb?jWi18-&ghb$jY;TH;GMeuB{1V{T6b?v?)nbsNN|PCo>m
z|Agb;z%>Tg=R5{A{(T(0hHFHh-ReR$tuk^8^^Ctyqq%T!q1HL0O2fiRSLtA-Yc#OZ
zQQ!zveHW~iJzUMe77&9ya|E`46!sap1vEe@2xuiY(rihj)7p~23j4ydh^5F1EQ<Cr
zR}Pth2KAIWG_QotX~#fw0OVP~dXeiM)icXBq+>$?R&WgoRrh>LK`;P$;W37)3UwU0
z@4%X3Yl|<UsxnrnsxC=XRYOzNqZT6`cfiDwKlnb$n*2^zNB|mOEx(}#V#MnT7#Z^X
zKaz~#akxSTTvPr_y<XH(1mbksUj7K8lcThv9y|vg*NZxmpcz&9Bv?+PYz?fDD{n-4
zt^5#i3zS|^W{Lj-=75sOA)Vv^F$b_pQ(aaN*5~zjL<8)|P1kA%wq_(&8}JO-7;%Uh
zA(vw#$`n%pDwVjbPLNtb6g9Pll!+rG3Lha$qDc%RCeUn^&P|luE@q<&Z@h_a$k@FC
zPT!*8iSn1#e9-Oo8#NRF#Gh%w?{x+Rx_p)wD6LTsT1W#!Y%p2%6rtvH7n1mEB1@q$
z5qZ>m@vq@U%7G=YR_whJqEVSzXTj<-7>d!G1?!3~F7&Y1>o7gwO@ef?n8cGw#_@1;
zrs)IBA>yF2@*k}~pA#g`%-W!hkT>*j37(uZJy61ueDb$RLQBB&qmGA5(HW-c110Gi
z3ITw^F}1*M?Y}I))Pn1&mR<@kI@~^cXu7q2B=3oilzLX`JdNQ{d%~^O8T4)2I(nyD
z>~~E@+roxSeSIN_|4gf8b?H#dTwkb5_9e^#N1an=FbM&tXmnd$`LWb(TC>+2i3B51
zRwXE_kI^C)#+tAVlB^g{`US8CP3D026a`H5F#7su{4=(_`h$%psY8{igO(PBN>maG
zD&?<#rX-i68c&vB$;w1Q%aTRV^d%!FRLcC7NuDOaKZaN+oS9_8>hSYsJw@|&qtVV&
znRSiDsb>58b)HNx)SrqD!~z))PrT7TGahHm0c*Qfhk{xNCxy5q;h*w16QR`j?%q&u
z&Kt{rDVgwOdtiS+t;9;%urxNQaOa0+;Tv;|=~0*egWL@9q59}YRfiBA0itB866F`o
zF4LnW7w7+AiJPe>K2)k#ML$|n9a=<@FJ%j;)@Y5}n3k(mdSl#*lPdpI+g<O8kL>C+
z#-m{iOB1N`s+efOH!wOf9PbLVDiyRpvpR#0vHBi)-|~YaL7Ei=MsLuwMgv3oEStA%
zUhfKM1hkrG5WdyTv;cc~PG;~vrLpB+0Ba%8Pk?)hyx`eu(-6^T%rlvfXlvSfi_9rm
zsZCVK9DSx_p3!DLQqtBo=$695D%7hZw1AEHW}8nib98D;d-wVlySHmop<yzr;-ng-
z?~V>cgV6TUx-;S6P!j()xdyvZ4XNeVw)Y=g9uJ2>l2Vfd95JZ!ie%E8?Fj_?bG~>E
z_4fhz&ii104`E5{7AYn-32laVpK%C+BRmV%6fKxTd`Pd?Bp>i1x(I9RLGO&_Ve6p^
z@BU0RrB*fgw&>A|50&6KWD<6B5;zEWo;UVj$vb1!JY2FKsuJ;|{$0ynU*(oCn-(>K
z1!f6+pIt0JV2E`$gbNuT!>INCctex-;fEu`dwTn!necA1uQ!klia3ecZIO;TGs|g3
zyVIuEYN!Vv?w?s!7wzAe7y3sm(X1O`qagkgc%F7*d2F@hr8O8Zy?GX_EedsEzxt8%
zKL4ZUN9*=G59;?z*8Q9ua{Rl@IXP6-m{vbhO7E-lKU%6Y!~b$g$xN@E46S+&&6kS6
z&o4xwg6DCPCg`{Y*+SQA^*Z)OTJJELU}Z03p?+FsX&BB}8cZ4rr@p5*Ft|?ZsB<-2
zoi1y+0IQxv^$)&cbvdp1rpcULtx@ZY7=hJ+H}LJS&$eTu*m~^e@_fex=*6O#0Zd|X
z2o6^~*AR!lAxFn7SaC{)jUi>`z*d6Q#b}6psAYe2;-R8x+=QD3AK;QIA`b_Bt=3z7
zAV1?>1J*oH^a3xUWmB_*-W#w&e0pw1ZX?iioqKJ1u0<ghd*yY+A0-n?{Z!&_EH<=|
z50&5zOcM{4FcS}Nq16sPP?GNQ6X`Db;sYggAK0Y4Ku6Tv$ST2Xg{K7GD$aj>I^I%U
z@qOj!%lt*bm+-&p;^0e~R`&4iI?aed@9SKh^E4Y6UD*49<Y?9z7}`HFxTDKmA8~pE
zcC*djxu(&XGCj+(Uutb~#2mWTtTXP=C3C5F2dpE#@zwxG{<F<2#;wW0j9sT?EWE*r
z)3_<z?2q<jUFLAk8|`xIQuaWb#oQ844K_Mx%KGtili-RN(^=jXEbn%^ancbn2fUos
zD`jZFU&4>V5lPX@C!+>bgHDWv&6&fTLe!!^8K3d*wH%}lRzmt(YH6)uiMak`samEI
z$Jer$88>|8I6nNSigy@AIN&rj2L@x5Jo?a;Q7Ac;Zk@=O@qeqf*5<*1RHFQFWxsa(
zsfz|XSF}J)wFUN5ocgO2!&j7BuNnLhz8nT$5iMc0pRw@=r1$!l1*UNnT4#T@WGhNv
z!Pl{W2ek|FqGxZa39kDi#o0}jCpOtRO6N}}eg0(HxA4rkl~&U@4*xt?=XS^HJZ?q)
zTcG^2*gEutT`blB?nQYC;3Jx`05}VA6$55bb^;W2cEGt;sMLf~5psS4iN&?HL`_^;
z6$}uUsDP%0xHOe$Hsf1V2B+EV6g1R#m)61=k}=q&&;gD9GcU2~n(9cDzjukM@c$Fd
z&;)v8wbAfQ`PT+ceq-$S@QrJt3D=xq_`T9wRiX*^%5QK<x&MCYb1gi_!o8KYP5cUu
zRQ=dKscq*2aCkbEY!}c7?Zo=wSY>4NC%b06CtGIP^Rdi<*g;E;bd{K{)K6RBKO|sF
z7i{TWGcDeerNt*KiQ2kCyI;DG8jl<@WUj8G`W1XJ5xrnG=k1BooLw|II8`R+@2++X
zTOeS`Y-|`>Wpy;BQr6aG4aUoNj-~s!RSSQ*8<R~bXV}IDJ0_czmUsk8t6pKZ4+;yK
zK#w`~&qQW|7Vm+IfaEADqz5F?=p*`PN;M^FVy3{=ygkwZM^J@|@Ky88fq`g62)2OF
zmf76cHrcSK{|}*8dg!88l3oV({XU3NJ_+AOgg8aXS7ZeDpiBc0muVQ=Biu~jgEGFZ
z$ydbL9)U2E3Vg5vsNX&`DUW|Lw*0!m<p+lRk<sgy4euKYy^jlZB<nh&MzmeFig=^v
zz+@sax_6*w|3rOkWbaUPAm?^w2kPtkv#yQkX-nYG_{ZSWBD-L#>=jNkNc<+rE-+#y
zWE3#zl!v4o2l(r&rU435pQ|+u%(7juP_))MK&9hX2qUW2#l_Y^VPl8AzAkF1G(bvk
z=Kc1@E$s`|!C)fV9}PAl>tJAJd0Zp9jO7ayV&SJD@|Z*26IM|}I<<U{WF5q_UrHop
z>j1Vr@Umn>_DgJ)emlk?D5<qG=OQzH&g4E|I=B!4^t*F1m!vMjoGUGSe-&{*a)Xl-
zrh%8CK|rZl&LnVf1UA?9Eo)skAnJW)6-2P#6|8y{MN_Ob>MDPBaf=)9L@jDkP3sX`
zcQ^huFbChFAhV2p0c!y(&wA^<^;+93SXFdk+PVjR((u~`ydnRft%VBBFb}*a{G)&i
z<_D=mwK)T(7bguUh8pS~D9I_sLiq<v(zycjfE02A^@Tv0A5`jCreBj%2TWf&!X^(*
zVDjRHN{Hu>1arZ{x}3Ky>Cw^zr6L(uG#^TI)^!dQV&0aCjJq*nXDRp%MVo^uPX@x(
z;X)m8W4t?IWjRi3G3i7t#Tz((#ObqGqQzXKJ#N-$bqxGQ&{8^H7qhzqR&z+orxt+n
zIzfFB%g8wTG#2ngP_6SK$9nch9<{NLiu>aqQpvsaytDxG-0!~js$>_MJp0ASqa~YI
z6xl~h;(k^9LyB1_g)USWBqWnyDPmrPs*!<+j)4<2V|M$v%`2C&EUO)(6?^GkxX0e>
zt+R(|lBRHiH(OaXO>Wo-!U!?nN~tN5gnw?8@brH*WH^#FNNxISILeBfRPuId0<vM~
zLi$t)Xo%PW%K`5*RkN^4oGKI8D+RRPXKD<>>VQsP&TVgA<h93-+5!fPj!JKDY@28>
z(-31BZ9Lu7;v0-rlx@`j%t*=;jM8$KrOW?kU?`OUrOG~hClCH@Xb~8(h?050;Dcc4
z?lYoK?So_MRFPGAeLkK2fbJl6KprH3EoHYNORt)Fp!&T$L@0y<5Pnqrq|lmO>?XxM
zMhB-R$ma>h=yy5;CWd%{qBOkIXm%QC;z69a8&~rV$_SB$meZB>YP42T&8oqFYXz+u
z)){)6O`-@ssZ!Gfe2;qk+r(Gld-Py8Nm21$UxPW7GA7{56j`6q&}LMtIy#I6<h>G9
z#{7X)hmmkZ4>%51-b_wOR82x4B_60`A*f_?<d&XSo119qOGhsM{xu(oqp(S;2=X(8
zTJ+f+K9dID2k`BL#)$Te4Dl(FPziRU#VM%p!#I8eQ1LdC$)=}?+i?6kpcZ5?v7Ej}
zOxv~E@<$egrsvtJ(6n0cNx1>2>GCwI?4jNpg?M2Vlwk@xD37mxa0attK{#G%l2-VO
zSy=5Xc<&iAn_`(+@Eo)!ya6_LAiz?t140!>NMih2O(Ut=c@n0rEnnmA1!iRkizs<8
zvrS?otccB`fLfIbAEyBCwOiey8o%jQLIbg_-OJNYeVPWG*KTtOYU0pALd`i$b`OWs
zAIE>K(W*!scITH~f@)5RcLmzAS_co(D(XvrM<Tz7N~ifN>J897-T@`xlYKu3$v%5p
zt!6B<;GVNSvsYs_&VqZ3TE^@=VA600G}jR~D9~wfLJnEWGc~2GRcEe}xT>j%Sny@n
z<Xl)r#Oo|B4v=H7tAO5Zw?gDjK7`+e(}K%tb#s8iIUP%?b<9cJ%o(*LuF|sQ>v8Zt
z6$85zEAj|`V8nCMY9|)cV$n*TwwW`uhCrNZ|8ic2<!3ZRQQ}Cm|I7IW|Ej#W2uxHK
z6O~Vp=ascX<&)^zq!)}(cP_s6jncKZExGo#%UpY;zNNV?-qIW|pQS=g@mNzcy!JU*
z19jzp0SB?4U=GYB=_A(S#Q0axD$LVt5q^d}(tci<=u|1m{+h&UCiR1G+!pSkbfQfZ
zEDRv;WUWEFEofoy^JJ3=+jo$N(9{SJZ*zE&z2SxTe02T|un*po#bR<^8ye-@)q*kj
zMx$5(zEAus=m9iE0!>gT_pf=KeW}j&B>KO1AeHQc|50xO<zEmC^>+~PS){A-6eb0s
zp$}FmT*IO~zOs-=^;uG9beU{E14-l4q)v33Y+eIN{Z7ZJNtI62(MNQg20pz};sf{0
zXYteItMB0YFA^-gzSS#`1o$m%C{B1UfuNp1$y{hOnlG2qx@Zkrbp1YX22bK080_OR
zue6GtBQYt*CaPVMohzYC5LLgOEDb4*T+$$vHyYp%_>@|wp}=1vZcjMurUm=_JjC(6
z@Ve)56>%LLJMV{gy0iQ^_&s$m7Qiy{`e6c1MG+|UnUIoP6DALPCssf~G}45h;}qJr
z7NnRL8p3virJB|xNl2?{<yQv3*)+XrJq7eGo53z>iTq@<)6+892;fj-wm5m5+WO7%
zy4Sv6o_a|uuoP6I)Q*>b@S~ZT*Z=9eJ4u=*Xog3!xEVg-FW?jUupYU+8|3+FgA&P!
zwrA0k8l-g1tQ74oKXE*xJTf|<JThv#l^LzPA(zFgdd_SBzi>8B<O!{4H`rY|KyBE#
zaU+TIPK(JYsPUcG<F=U}{ov&tl$ypVR?vP6JpTRHz~kT4@X#)&Y4Ut|Iegwb<~i_n
z@(h${TK1Cg;1d{)+2LQP8F1nh6exy*l79EvPo-R6C*i)_Xe#nFUQ(W4866%SB6V)7
z!6vdqeRslaO?KBoKyEidokf!G|8)7YCr*~1{98s~D5PIke*VPi4bx|yd2%I0p9IAq
zu7R83(>*UeT}GCs2i$tf#9=Ss2F!p_aEG%q(&NF0<K^dr2dt^L5uTd>&s*xd>v7fq
ztJ|#u<nYkoC`oWG3mjwBcwKkW3Vyob^oh^Ihk@dQ&-fXz`s4|)_R|_YLlMw+So!2L
zXJ8w>bDo4P@|QSG9L1*L{>^az7t;PQY#P47y~GaCLR}C0o<q`76h8p<1kw>yksqk&
zh^m=MRP0RPS8-N@!KPPP7?aOpg`+(n?y4-v0RJE@3Dn4$_25154@>umVIe6lmU4s#
z(2WY`k)!Te%2AZ|kwfcz=F<0De8g<RZ>M>S!C>WR3u8nNVAO!}yB8fxhnGGP`c!UM
ze2kYynN9O^WR7fHoc*s~%Kq0cW&bmu;x<4WX+BA9x;Xov`Amu1fEEs!PnF>JSDpPY
z*M8)Mqwjj|h9<N<K6^vcso>~ME5;5kj|N9?TrqZNc@!7-e&d5vlOOoT^(C}@@Egb0
zJbIwmzURR;YaW?_+YcaHW&TZ^CZn)Vw@dod!p`FM)0m)TXF>OA=Xz=*l=Ox3QjSJc
zv)ZB)eRHNHeTBe#bs&-<yNae|2Xa$L@%!L3WAa+eUK9H!idaKwgFqdr6=3i27*sY5
z!e=U$A=W*_qCO?q1TFn#oWcR2Vx(NFTVZd#2g<h-J0$lMGk)!}jUo7pwansooMFA*
z7RM}TDQcPpGeIXe@GY~T^&~xwp>+nx<1VzIZlq*IMtU2bk(5qhOO<nIbkeC3Jj;q!
z3Lx(}JS|<#kE{?Bz_(hG%!gJYzTikKrEj~3VmQr(7M)qICN-Q6m<FaAMQg)IW9PQv
zG)uFvaZ_rcZOwJvtL|8zviBZb`)j;G%`w!V!C}y-1h>`XwTYTvwQnBp^F@kDyEo#c
zp{CZGc^x10TO*_U`?FiGy`lfh8kyO2qFg2pL-|Z$_sQ~U#D|Ky@m10B?&$b<w3|Tr
z{jPlu(~BKqhqZYYSc}Zas^q-iPmOG_&H~#>YKy!)CN<Z>%ZoB3LtPHDgYXr}>{;pT
z5$SYYX_Y@YUy?3>^849f)7_%1g-OMg)i9Ui7?6@6R%fm&M=m8#lbaw8w_W$d{=S22
znzazNB72U_PVVpPzNXh-zvA%d&00<ajZ}_3(0%Pt#GV_^wQU{FFti5ZT2gIlTeY_^
zb@x=l+qu5Aux~}`=)}Fd+RYvht24RHqK%_{VXwb)bz^>Q!LQ=&CJ`Eufx^0cY$)#u
z!~zuWFmq->Zwv)2$(7glcU(K!ti`F!<UZKz{qqc&A;VZ5w1hWH`Y-9@XL0&Wge0-V
zEKWUVj`P0tNe8t3Eob>@W-~dBDYQ$7J^(gH6wQcw)pK$|9+iByq!hI(yh;jn0JQ0=
zQ#HA2Ypkrk77zdn03VqV4c|to_^durbzzn@=xC^|G~mya(U<T98r=GCbLR3cyqo~9
z4){Z_p_E1xw2)qd4a{QnIGsGvr9tpV&1v3xZ-5BBRhCx=VN#CJPOK!iuqN>Rv(Zd6
zqjk*U1E(;pcNSo$TU)98ENDAbKV@EMRMmW;3%Md&QR%ZKSiByUKU1ooqRh38Xi;YJ
zi`UsyBOMk}Y@%$6vK2w>?z{D=oh>^iaz=(i3uQvx+lLE#mM8opH?8)hB0<q<^|)}i
zM$b}4vE1$(4DSEbwT)-@e0qN~XR;b2KHkP_tWJx!_u8Stbf=r3NP7t9y<WBG6ob+7
z!z7X4ayQcZN9X5=A5vZ{gY{!OCG8pOn8ka~Xzg}w<1F6y9HvdqH#bv3_`0XWb=|YT
zR2cylgi@I))-=No1q-9BOxT%{xQ;^Q7lwq|l&Z2w$i^j<JgOy2B`Zrzf0*0%_{`)j
z(}l1grj{RmY+q!wD<!A_t<^B$mSv3_?^+!v?A^=OrguNMKJtvUd8#`!I#96tikpgE
zn>*d$6RSRU(@=D{^q$XbT=B%;+`F?~qc;dH2+er4p4X4v_Sp@b+sd_Uzjt%TrtW~w
z;xXLz^zKB%_;xwsjv<c1w&THi<+j7)yH3-zMVQ5hPh%EJm<8>p?NjV#C2eNaa6CoX
z(RXJ`(w7UFGb;gvQY4hz6Xa$<93?1d+c(g9Yrx?P^MD4wyzsDw(@;hO{u{lCrHR)J
zF1ua-*Yikis8Ep8Fe5q*kq~WgA|9V>V2ys4^1*RDhxK85Wcxpf+b|;*#cf5#%>~>>
z_{-#9z<c2UU&MQ%8Qj=L#V^>_^<1b{ZcV13nrws|ENF{gDB0FgJr`;!wq?n1-z1~W
zsv3k^P?}*tL%$`T7h(NY7;y5$cRQ|oZ1*)EpXrE=?d@-$F8Ug_e`v?n`=*n=u8nO2
z2S%blJh*$$K}XA)j_v#6fxex6h0O)eyYD=97Z_c2`&1$}antgS9jizDp1$!7`JNl6
z8dDQ{JM)`X4tfH^t2W_VR&Lq4D$>)@;%>a{!Y7j>#ZI5MqkE`+%kJGMP6W#98%vQ-
zpM-q+B;;d}k&oq)$j4GaK9+Zce28x}l%6_z{Bzr4>Ag=Kz3p?`W6xMSuALa()#b9b
zOItT?C@IKi@7EFX`9DY3KDxiqy88obl`U+SPs0lTI2nW5dqQrPG2C9{1h>G#U(6~R
z0_$V2{TVAb;ztk!RhCmpi55je5f-6QnFZKj|IzuSkfG6c2~Z@h93ehVGdk6U4Js{5
z(@^aK{UU^9uo|ph1N|$tUPJYwwRdoc5)F1iga2BBN*2K?u=I-+sPxt?8o`cw9JDBj
zkHT7MmFHX#UfT0)Dgb}6+$?_h3~Nr&Q2Z^Y>o)MY8l<E&+!~k!3)Z2MXG^dsom&Ku
zYWd0+qoeRenGP4g(MKuRA1~zeCQd~#oEBJzryBSz*K}MnlF?DDhGNWxse^@ecdo0q
z^&Xm<!?SQ~UkZ#0TgLl?V^iL!Pc1k_yU!d9*rFq)?xyX#6;K4Qoe&c}2xYLgf{7aN
z;i7KYitw^xc-gXWk<i1DYd6G1Z9<!1&P$kRXhr?J*Gmm;Fkdw$lFlB=%a~||w|>4P
zU10HWb~#Lx{~to42Rjcvv8QWhZ7Zjy3B68}Td}{ldt0wRzT)uM5hyQ|Ctouo0ix_g
zu64_3hC#8N1f|lqt~}T?b@zG*h^E?l_Kzp-SbP7@CX?IE>5VQ^(BTPt{GF>B^XnGi
zkiWRDDK?n*_#qtP9A?2{(CULh#{wKuWheHa(a;O^{J$!AXyXDNvM6{6{1M_I#<xD=
zNTQxkB9sF)e&Z$KkW`LG1<#h`l2H9OzGE~*{HxLMpjz}v*^VxJn}vo2T3HL`NTWC5
z@ufZ7gS@%?2~chaUt5BP+!mwTZq*T^Dy<Y@tbXgBDjM1j(a<9j8oGHg8bUaG@GQjH
zqBZ{lXv6BURtR(;O0J(;0<(G9B&k6~XW&T^96D9<w?YW;TuD0bVsu?=m0Sv1`{~O<
zqeuF0J6UQkt<3Rg!bi=jn7V;$2YU`oBqI~ItnOGFmY`7wvPF!BvMVr@-v8MCmQ%Yv
zxxdw5v+8t$T`)KVwasnwbnhDO+*I&r7egZo&uw`RYzuqfxbP*2jI!7u_H|iC!}Bi|
zEgU|!c^Jg6FMu5d&{F`}0tgmBVHWQx8nsTR_U0VeodY8|(3%7B9Dv%Y=h*`oK<-Ht
zPS44NKF`6+U}-JT&d$GCWZ;grbv~V@!ZOV2y$EK-r(cQ3r>B1^#l=gAOZt>SfyWSd
zrCaAq@N_X;0badV0les|0bXCqmL8j#xMf2}h&Lpc-}u<R&}gw<4^0!GVl`|yKh}u2
zUI}~G*y@IB?_U>w+LDLRYq$?WufoPcabu?oe0tT#4=;vZoPpJGqFw@Df`0V2&ne*R
zp3SYBx`POO9e?`TM0#R76xubgPo9u+`!B*?CWyUup2kd+0bwueC9#*)AYm`-6|q;<
z*-4y`pjVROEJ3?JEZ{Ww)rAj;A_QLleHq{t4TdGyMPQS#wLCAOt|n{%C{g)&v{Xny
zX=mXF<W$VfDo1jaBiYK4Y~@HJ@<a+?tWohu4k14zYIH*&T`7~UEJCV1A`xw+XCcP3
z8KaW7H7YG}Qa*d(x6xVLTC^hs2*r)4W6&Rj1)HTZ&1l_=$pyxmr4yBd=)~sd@g5AD
zf8{i4whPVp#nVP*%PU)%x9UYHeOEVHVZfkkbf@7(yDJafU3utk<)OP#=MfkbXV2t1
zs00L}eT#sovU2Jbd8tkf+l92@Yj|5wf576(4}`1ma<+s7SNq;6T&<=Uya=y8-#+u$
zo^5}#uQfWdudjUr#H-gxc(on{Y7gumiTuFTydqcH4-sqo_EMd{Z)a~|Q-|lyJ8ruj
zjIO+WDp@yq)0l!-CpP4JZ(Iuz>%Kzc#+5@}39)Xf>rLAbW^HfrWRG6>RC1)N!{_Og
zFzX(un|8w1_WDxH+9YAtCJD3ZPjNdSDAg-z@)u)PJ;ba#5N6d^bLC$ZW_`Wox+nJU
z{d6hUdf<rzX!~?@U~6md_8xy^U~3!N;@0Eexqr0lj+fqh{5$uJ7Vr4>Lx(=LIoi7W
zkqvMgYuo(@q9&Su6TD7FFdx=h_11}}eUi7X>$FqOi+|zks3W6+^pqAk>$=XAoJvOg
z_}4GvtE)uIf!7(M*J|;Y)c?ktv=l)y>c6m}#bK~|1eH~qN<{<W=Hm>mb6Et7pd~+|
z(#Vsl@cA}C<QXS3SUa}Af;_h@c<SC&@ziCXZ8X!#9mq|WJ4x@9-E=LNchhBynv#45
za?<4>2HmMR=~^!Bq-(melg<nuQms>8xLa@1(G+9QeYbaQqtTM+Nj9!5#5HKa3r?zq
z{IV^%)wfQ@>|KY}KMr0u2>pWHprIiOGP!LQ-OIiEr$&ALwtB0>Z%3IHbw)wQyIrRG
zk!>y6Z3pjJ^Qj1w$vW8HLJ|_ay@EuWFG8ZlqPYS^{{ms?&k%~-Vg8HU0<Vlgi#7#>
z{sjThpGg382W9?CrFkw!pWy!)eTG^~AKucmaj1cV1DTd(>$;~qTGzF^y}j4=Ux!Q;
zlF_M4*);{fSl69uT-%pG<ReI+d=nJtvKuF2?%ZgieRFpZ)D7M+ncyvUMA=~U+90s7
zr@EtceMuXww;2sKJ!Mb##k@^1tKDy>^fr+*@jA}!GzNOMc4k)fBp8CK>s|+Yb$I?Q
z;!ZLMAy-=Q#-)ASESNtNp(rdh3qDum%n?WW4Km^5dB(S$kyGbG^Bf`2Mewu8L+qJ;
zqf}GWS}6-5XeE~V%J|cbO91pv1NSkN(PKtye9QIF;GvME2JWGap19kebn89_yAxgh
zI9~oB*bUlz{-2^`si@3PDc)r@IIR{vKEdi4c`4hCD&B^VU-$_^p<CvELs;S1-YsXa
zK~Y(cRZ(cGj6$1d0bkVCcm6wU6!qJzHSOs#08~1GFL^uvy(FDNSr@e<rL%!cV$bl!
zZaLH^l~i+tweR4ESEpC^By=<>=?f;(GTzv|x#)TCUG`|e!&{7YJNQpTTSIEJn(~a!
zVs{xf+<#3DtX^~Hh7>Cp8CI~1yhX1P%!0Rhd1CVvK@nCD_=3}+mP}(&Q~pmt01#h(
z0Je#J^Z!Ncg4!s9^~!$Bld-m0+*t9?8H*yO&Hp@^6e*9V7<@zAQT&sl@)ZjFB`!Kk
zGXL|EQd|taQ4)7h#XnU?0p*;lcG86xLB(B}Ywp`HG_#^LzzgyIYwz3S?rM$mYMf@&
zjIW`)ZrT2U0B&mP8IG(yHW_(h%T8BETh`=mn#g9CWvpQ3=pCDye1)k4cMT7`|6K=G
zq*W}(+pH)kiqSHyTaNZ>%>t8}JT$&xr$#XAueo!=?{8a%+EHr$O+vpIBX%hmu>)a5
z0czaS)@|&rOJGFw9mI&}%S&Oz>|%_lM<g%h>q)&iVDm);3jFPbHw3}J<M*R!XX1wj
zr_G{$>nT>6e&<=@+Hf$4eDKIKHv;SOT3D9|BaUF#%bvM3j!T|7yv8%v`~q%*gLyY@
zhN!5yyCav5(p3Ca+m3-(mCBX)>Mr4)GgeC5;;)u$JE(zIt984WrS1woI(fve1wBgr
zUYp<b!L3^#+?w_jH+4aPV@qtfchl4zYvR`Iinb!`1TSsgmKjc4jOpcVTi1APO;g?7
zs~Vskxw@lgUCsp9uHD1YP~YbE<oICGV{0jn)Hh!<91nGGXpRqew>h2d{ma3B6~;`V
ztjC?HueT-Em-%pWL)z|Y%4VJ3=BUM4FRgPLhmu?lC5dKKl?Y-po`)jy;-;cT>v%)h
z5&H8I=u^}RjyFoe4l4BLOQ0U|vZ!Zy-G+yD_w8HR5f)<WAKJ6)fvMP2_WVS?FrG3v
zauZF3iKKuVj(qF><<Q_c{DIZCeDnV0!}oscJqJH=O|rA}@EW*Hbd(;3t@M4c5!6HE
zlf;%+ymf}>+=75vSrJ+)#b*QCW5OR5EP>`L&q)d$O<9V?04h;rO0Wzq{IQB2YNjr$
zzPiTC`s(T_4NG5mo?=lN0+#ym&jgc}MEw(}DQJxutZoDSWflCk%V6VFD$Zsw*mxEG
zr*~-p=dlQ8j-@_LkOW#Np?d2eROIvX*mn3<Sy&e|@sAqBt+5qig(SoZH1V<q)m1C(
zo285Am_Ws+@)>DVOTIzIuWnRJ!ci^$|1he_UX_x_9oL9Hi`65l$_183>#sC4xP>;j
z>pi}dTYp?<D$nBO$H96~=kvX+lCx>5UZyyw)#$RCwfI(6kk$N!YrXi$g;$Zs4vuGu
z+VQLnj%Rh*x-1&cn&t7VRT|Hdoj>#YspK~6AKz{~OSa16nZNUACFvB(`p2st&n`93
zBn@baHzm=w_rqJ-H}%)CXlW(NR_bqG-_<(Z9dvi^81yv60%%CHqIAz1iF>-d!QLC)
zc>ks}Sh@Pn^(np4sL={`BWKpBj8Ii)Cz@0JX&XrrW-pk9LmC|H1cyOW{x2Mlj~_to
zVT;mt(TFCkvppGyBN}lA`A*=7h7~zX+x+jzBo+Q69L;`SQFs@PWMZ=U-{D9`iQzv=
zqu9?EG~HErI~K>%SNnQm<9(Zl4@@@uI6l&|>;5gFzNWC2rT}alDwQ`kP`_;7fS0Jd
zYxVjgqu$RL6T|twgLRJlM6PLBgBh$uWTt__`kC8@dfs#Ub*mcHT8?FOqE@tXG^=A<
zw%#^qt4pmqG@cyFIwQ8NcTEOE?PF*J+X#C}*WwwbqB6tOsmw6tPTMazg4yK}%zniY
ztY(I(3%(3hK1k`{5ay5YH2BPg-=Q?df*yZVCot7P>`7LuQU)<bbQt7ejKC&f{f)u;
z3t$acS7j8d1M`>x3&PrCoH~!w0Dsk)7jOcq<aV4W3hGRIQ>rdV6OmUfI|{E6Z!?Nj
zN?RhYmMlAn!fPdB$tXr&auB1hJkK=t^)Ih`@8*oBbGkD>o^!<4+_hoqw#mruy`38i
zo^MQToL+BAj^tOb_BxtZx8+6~th@K`*$qthKkDn=){~wX=x|tDx<>2Ut{JQg_io6o
zzBBD??_CCdSr{8Dx*Jn*OL%M96llq$?Uq!g%|9|RUWu%sd}xrzhGl7)@Dvn`2Tz^C
z82c<>PH`xcE_0Gvt&CXbek#v0bLd-Wt*=1yuMD)-S6|jzH(eZDQ#ksiTW>jgLvzQ`
zFCM!UZco)MKQz4dreR-f{NTu%n?`*2@rVEL`Aw@o_r@nb_{ND%tDkt|6WaT~b-Zot
zo-fTP+e&l|Wr6m3quermxKPws1XjyBC#hAiJ)&8q^U^r=td=cG2T>%`kN#JJYP1@%
z{~?ypx-AANs0N~CfXE{&F*Q)Ko!F6zrM`Z_QorpvR%mXKjrF8ttgk@Edh{f{vesB%
zI$!jhd=fI*lZwf{LNeK-&}3h^$Yj6N<dJw4p*3jssJRka^XA%Xn*=Asz^$7HQw)4(
z3a2$f>*{@-8{apbG!NXd_dK3L6G+1br>If!ZnM#CvFHG^;lZ1>#^YnHet*QL7F;I1
zMbPu1pgp(Y=DyBb?tgmbHH|^xxFrrlDb>s(WiPVbr)p-ASZNmN_s9lcVTQX(v%K0_
zBvzh9`n_btuRya%Y_;M3Z`<*QTV|e|={m5cMNm_OPS0k?_w`r8Y7SRsk@i=^YPJkF
z>J&R(%&pnqwf>%kuo|#?;ypXtjBc-9XLOqb4$so48cyXeu5Ch5HU5|nEkMy(44lCi
zbfi`u8tAxoqJ_n&%t|?`=1r2Mj1uD6v4D7V6~yz`(`IP~2?|<4GLy`z%YvTM@+=Zt
zWJ@)rFNJ$*c)TtfTSFQR-%=Z;*(CLapI2jRzC{^*Nq3;ZqyLsDqS%`C;Bjy~>M8%Y
zlHeZrXx?QJJx+&!{}CFva(K-@`S8~+j3}*aH>HQj=Z1<Uf3AvrGF3~yzNkrd{vN@Y
z3G3pfbs6v@ouh@|=l2r$nLu+%i`&yX#y|9eJuk)C6m~C9=}|~4)GAE0XZyevB5eeZ
zH)KVzHsI5HKE1z%w^&%M=rr;+UTtw&{XM&fJ2!TCNGaTg^LaG}X-?@890wq`^=^oc
zm3SMRCSJr8E+^tBlv~ZXze*YRb7<U$s6TPqKEbZK#JG>XgX2E>@_!|=ggj?(Ic)mB
zen-orFmg1(p%I;8IE<z^;Ik`{CGgq*9>Xe;6Hv2=SRAlYyti!$)qSW!b)P^qO(8Uk
zkpML$_9!ES5iznE(IkV>iax!7Cy*g06X<%CNf57+Ny4kpvcc^yQCxozaTMT*qK5He
zX{?A5h#bDCfoG(c<qVEVjA5LVWI~#_cu|^b!x)T7)H~#nH&iq7B5osTRsm5O@jsoe
z%|akeE!6PkJ1RqS=<SAPI5LwpBQr^SBenOL<2OIPBc3ijbK4QPeMawyw~wV)?d~wU
zyS5KDuj+_eHTZiT{?o}VYd-hJCmwo3+J1h^hi_QbWE+3)7fTPkbX#k%XXABuVwETm
zI6^0ZR;q<y&<%nv5Ojio0|f0LXak7O$O2+g?HCZlQ(DT$g(@TsFeH2|rf?R=6p_ai
zCcKy;@|Z#)6`O_Qzus*{Cs|qamlc#5A-I)hhy-OusOI>K=n@k7n+Bfo2>}Sm<Sm>I
zOvd<GpsEbY$m&%H+0Mt$#T%srFY&J_(>e>xVAB<oxNx=vFF~VgER4^WGK&A#16YV3
zJj}=eEIfiGBnhB>NdNUd6u_dyuSnSBTT-3qVtEjEgP03(u@z@46UjwjM!mr-&9s@l
z5<?fBsDc=|Mp~Z7k72AVLKZQvu_&j;Rf8KeVW!}l$^@CjvG)Hx)L9ZJ^Vc=kwiukb
z@odMIp$09osBubdZCkgeO@=ym?LUt<UK#2{{c3~T#F=@$DHyOyQ0K^fC$5vAj%0t&
z5f37)0|sPmIt2yoM1r0I4QeRL2BdZxBxyGwX*WPMTVxOzT4oi&SP^jwhGCH~BCxCC
zBQ;;)@0ZSWpfepxcYxq2aaN*GL(}?akap24&0eqcBt5Eb5muhQ4W%_|LsWXBsWu>W
z3#EI=^Q7+pf=R?{5_jG!)frI<k)h-^hL(ldP_%Tu4Y0&J1!xOghyTAs`rx!$Y+bd#
zSR3gBu3LBCjwX}KqnAQ`oZb+`Xsa?!Yl}4)ZCz6oMLtKRP#+G0ViC5K<jU(6jHb$s
zqZ!mR9CyDbV>BSG$tboW!o&oK)PrCI1j8WY1YrjVNa{0W1tALvn?cwF!bSiGPuNI;
z6bO<a?f{Z5HORU&VYb2#W-qT~9h0+-{p2~6jm()$^0V`A6<x3dkGegN+7ypyNqIB~
z@@TOX{{k*x5sZ{IDG3KK)a^-$m=S(WlIhfy!K1>@7greN;~4>EMugjip1<Vhe-~mB
z-$MaQMw#~f!mqTv4q7yf3VfFm-Suu?gPVU)FqJ<kL(BudaQU|tT2jE%yxS_Gc}c>c
z)}jb*o#w5t2k`&6&??6)%@L14tkj9UCF|5k6Nu!clsbf@Q=gSpYLlWjn^2qq3%ga*
z^H8QySV>WMG>ZCQRKGm4KXWWYWL&5sT&N;kQs;J|&h2_0Z^STo6$Le%m9mkEvnat1
z%EKpG^AawtZ~cSU4^WWP5;!|8<JmaiUsHPLx#?Hrjw)9Js)uU4RDDq>`CI=`!u+tG
zN>{rG=1OTf-VW)$ebiK*dnZv-;1jz(wZB!cS@l}MZV*t|l*{hz-B}HrT7bAp*c3#G
zO57AgiQkeC?lrKdosbajf6F>qfI5~Dd|*`IWsLAkMF~o9Lr{oZ;r7o`i$5e0#qzV2
zvv^)6DwWRSm9wO;S;R$qJ&(F4t<cc=Dy_l?YQj{0Acd!x6jV}^?@ziW-2UV&JV%-~
zS_HmjSR&P6T;Ywa(8nr%xVOdQGB4GY!i^|KuaN_e7VtQyQSf*a8YH4d!Q)EI5tQ_|
zF|<F3pTmDh{Q_5!6ht2%fky)POW=Cy-{28iIWmI3jPI1nsFWjJ@T_&x5w&t8gujHJ
zrG5;LXp|#;u*^#8hwuoa99a*Kd{{b*RgPrfS(~LY+UmW|;UARB=#(Ry@nLWceE=RY
zC`Z=9BO9b6B03^j6*2sW_^1@yQe}rZEwRI#LhLYK<qikFO5Ji1JIq&0++iy4)e`*5
zx->)EW#)G9A4Vo`UA^kacsM$Nw#y?Qu%~+KGktZUBi$R%^u`Te-0;xumfX&VH%&df
zyEVV_;q5E-_qZa1ySm`k86Mmvab?V>!S(o1W&PO~FdumOjN~Aj1>$MvP1F%({h90}
zQ`Vn}XG+pn)%9o8m10`1R~sCN@<R2n-oT)_3f1!j3vrOqrXy!n8VZh=8WnzMT!k}e
zv5$_S_5%_JXeA_k!jbtrz7xtcFMA-r044f|vk70qhc(XP-9<)Y`9busHv3iLW;uwu
z;t`W%tBYEGP=a3**{_yh0U2RS&r2_fR=I4@v>D&2)tBp7G)1b`F(1lw_?co`s4d}D
zlNy?!4RvjU(ZZ%qk1n}pXg64<<?eI2Nv&Dn&7#0Ql3rHKTT|^uvytX3yxC!}ne^V~
zWr;xFs$IR?CEmX-*lO0nH(XYUP)UIA7IpnY!T#o8e}Ax<(A#Fg?~8U!KU`Nd+Xw4T
z{G<CPZrtsr(qHL1Z2o(tK}o7R-g1cu700l<?nDW5^KRTsz|*?YUnzARrp$j|ZE%W~
zZn;!^bbcvl%GbmiR1p)(98KWs;>!>Ar$(E+$Wz5=X>X<{Hacl-7)%eU8RU#%RDCPf
zws!;z4L)e3-~^?uZyOAEPItJLjYa#iPE+&RcCS_tR4ivPn4Jcr(B9-qd3jn7akEiN
zcef?;qD8d2bOxP9YccAb*@5`rHXbKj4Mo@kL-T3;EZ)0h#tuAL@n5|Q&DdF!Us15a
zP0W!i&DdG_<X1{HMVG*etBZps8u7DQ-3@A9>I8K8DYP0Lr&Kg>!I}-)oKc(h23BAG
zIsWEb7Q6F96<(ANk?{REo5{$4=V%o?rh+Or>IEMuOO|sVY&9$K0z?!WDpAnKEAc1b
z<syga{eOp6gnd78qxCBbO=JlLkl5<~JG2rkk^g=vaU*5@N^O&fzr#3Zh2;rfnOJeK
zKhTv6Ye|wotZ6D+tdNRyC9THzKw~&-H*lgE9E8Y<)a%OsEGDh}yZZbM#jQO7wO(Kt
zXmr65L&X{NoIfA+ragMK!3@SMMz!9ecX`j?z|*!0d2!Z58GIP_oFrD1y_F{;O|#&c
zGmO>Bq-Md1q6K5HET6@Hn+4gY>*^@~i^AddFV{$8dS=PYTwV6*5-ceAUn~iSsrD~l
zMjrSjV@obMGlzdTI9wWBxv%KZy0gm<j95~2UacDGJhd&Db~P_=v;yx`TmPnZ`+a(E
zHk=r9i@~N)B<JUnO`8UyP1oE#p5DG?Rab~oYqe&RVA4@)wJOxLrore67T0z7a{<w6
z?3>D4%+T@%SO)fi&9G&7WOl+YU_AJ5Iidvo0p$}U4Bxlk$R1hhl`CopyW#sK>8mS6
zlPDMf-%Jo{viuVQQA9Ys908K$_vy3*&CuXC5C>2=sW%x6?1e|w8X78nof<#naYD7P
zrgRo5q9lfY5Z0XstH;{0WAbPj22Wu;<^@j`89VE;^YB-lcmbS*LueB?S#+x783GIN
z0sOZC5cs_5FxTp7#phc=>*onnr_(d&|7F*I!IMpa&zDSxiPq1Th+Ap{YD1M-x%`qz
zIkUNTQf|?l9R9(NzrTCWNOaxWP*d3G@7>wkdriSTI<#u~iOxc?lk;Ulhiqb`BO1#2
z`Ju7VA+TpJqD&pQCMLvE&A$4PoZH^eS6A2)jBNou$@+B69PqmN=JJ<pk$_(my}^hj
z+mJ%NeRKH)xCVc<!d8H|6pl(<3b!FH1@Po)lZU+nE1X*(Q#geVSPSQ5t{22MTA{XC
zOs258t+l<G1gzD>nK%s|$OQyLFzW+qokcL%v;_X#4R5~d_P-uRmJUu*WarW2xA*qm
zar{^Tha)${<M8R$!l&CHJzciKrEpZ@Qh?QoxD;+X&Dk0G@erAUgnLe*Bl7cw7T6TB
zO?foD)UqjTFa&abLc^K$W-CjywY0S1xYjBPW<3r3xuE#>y|*7f+6kWwM~2wVf4Spb
zZ{C2CY{0<<FC0652h<bI^S{Hl<Bu%hvZBF=xf$LDY$v#59@v&nQ16262R0w555Drs
zR}@@!qQo7e0w+rF%d3qv#<%<X_Y4m0>h}10_Y5uHQ?$RA_vJ%@tdAGrdqf*OIxsMH
zbX_L7=GO6{Tc)!4^*0YSuW5BTn^!dVuFsj=Z7ZNe8|L2xx8n~&T-IE{WhaV^1kB!Y
z9;1#gLS;n;!LqkX(id0c1gK)N+tq@@Bsv5MlaT-pH!qMHoryQuIE=k@P#sMWFN(Xn
zyCeaEySr;}IUFRo2PXt~2o~If`@!wt?#{tE5Zr=8(8qW0t#{w8diCmU%^x$pJKZzg
zJyW~2J-=3x;Bgl)mwvwHA}ruUyAY5*hZleW!P2NKVWrekj&a9VR{`twa%Iz5gCs}|
zc6q^w`f4)qM<N=Rxin7F^^*#H)fqK1ho>^AM0EAcN+1=&oUlz)p@x(6D_%n^Tz}AM
zPC=|un)>56T;WF455aTtZYHoF3?gvI?N$+teNCopLk?ATRgl!aeWS^$YLVpvN5X^y
zd9LI_mJ*NR{-KFlM7g5oFap=Mw>#8;*xEBIN57q1SOu2JC@3(R@gl?iF8(H--*@8_
z!<<vU@iwQqGr%4u6{V^;NFPRtRsS@pEQS5?hZE9k<pe2P6jQj~k)pWf)qt2$g>ev<
zn1OBZ6=Eu@6kRQJdyJik$^@S?;(E51GUru_Z(x=zZq)z+Ahx-130JW8Z;4JkLg_#X
zZ(yr&n2=4znS%{B5B`_y@*b8cjlt7iNXdCkjMs0FCdYok*U{gD>btp*pRZFUjq#Q}
zk`xyu5lt+p#d2(*R%s<8X&vJgYMha-th!pLrIPLXstSe=$O~O<X3KBx_*8bLKMVXR
zAflM?T}skIKI0F1kK=w)ov!*XyD<Qx8@_!4c~F8;L@K4`hftlp09pL#K<(K##X~mO
zN^WxtIg*Wlovnxcstv&qD{I`G6%5oSd}qE3jAhjd%gnJWTJ%Gf0ODl1gRO14SEnk2
zDdT&@Dp(3(@+#~ld&&mTR|8JAWA1qA^r`;4OZQXVc+&K|vI=GdL#tGvfY;q69xJu7
zs7dsOQbu0caV1O5A8htumwj0jwb(dgqpA}np#r>o8$%1!7ABDukdMoU6?0sHSrpxR
zq3Y&mV$Q)9b+3P>Q#CfXHts@0=CTBuhH91H7TUNBc&!mUH9_shKmA}q#mJna0sn+W
zVEqWl?ioq5F?i`Br_v`es!o{;Fh~{>sbb_lZlZ(Zr3p7MGR3_<l4`pe@x17xrXGOf
z>2o%o+r~#=-k~Y$ky^s+&5ZiCI?Fq~zD10Sx?lTRh@8&-9`&+37&yfg^`N_8Rd!e5
zGdx#q@@vn|7T$Irq<qxFXF)4?cqk~S6K-kN_>@ZMy;;Vn^Jz8b44phScilz0Ms}C0
z|6@!qx!!xqGYSV>ble`O9~!`~x@=H|z!@gIw7R9fY_xx<3#CC*w|}1Ts6#eAt_<X~
z$Yt&-P*bu=qmNs?y61|gvF8jDqC}rkIx^5bj13O@XrK7V%xlP--qNwI8_X-&NEGam
z8srg9SL*v|;=2bFYa$Y{m-53agn9VQ3IL=2d*tKAzu!TMJeuDTWL}p%C*~2`sVd8R
z#%XxGgW0ZH7}q!}PU<qr91OIA(%w&RoqB5?I#W%1ceLDkI)C(4-QEurKI0cy<-2pQ
zc5cRQzOR0;sqbu}g*agddI#O}KeB1Y=et_{-e{Yaf8tX62G&1NfrR-?;VZU3hc%9q
zIb&L;wTUDLVk`{8<%Y&_u2AebM>%zv)HVr;AoV)V4j&xUSv@m-7vAgBDZ=G@^y;U_
zd~kIU{u&~$GM4E1ywPg%$wK!h1JnTQKJc4@b7%PSJ?K7OKZTxDU#<wqn9R4QKt`pg
zV7-z;|HGSzImPvZyc9@9?$aL`c@7S7t~a5&_%X8*v>}`W(_chwQDdJ3G~=F!MM%CV
zH#*S}rX?LLBy{Kqf+WHOXVj14)CyO6@$7c6l$_ntRj}9!bnSUQNyXV1^V+2{Y5UTn
z2fboBL>sGr?$;)XFvw@b>DAK5*L_bqytho|fZvS27QYcm315h3wZ`97*;v2ueV*;C
zMFyLqLVR}v%+{(ZDo{Z=7~N^fo;O9-P;7+dNPaeH<tN`l*<M`aR<i;0z%upfuP1MJ
z7F!MAY49`sk>_t$=vQdw*5t#xxvJ>J<)P?*6<+wnS97kyB&_GW?sbEt<2|e!K%$(Z
zo<sc0JxYlP!tw@th|w=B2+#Yt|F&{X*bl-w{d<GU_=0nBP#>2OSx=Z!ExV%IrN_2{
z?0nrh2KE+j+<i=W!mTZO2TqkfoF<RMjKh??DPR8;B(BcO$HTLeeE1hpSSWA{z~;Ao
z<j$9j8XWG>4Er74-(WNFwJS(TJX8!f-f{-IIivsj!@{CJejCf1;D>%(jVHn@tm#;h
z8!^&$X~g^y>$whEiq1tp`>gHTFIDU03;0tuwP%r6v|DO{YB9EdrCafN$hx*~F=Mad
zIO1}~4#&jBFT4-R4`%OQY_E{wjF2DC_TDVF<W=hXk#BI?k@nL_<iVIiPpsZvnh{5>
zay7GaZuJ{#gI1RvYDNUdXLdi`1-eERg%23YSPA2svROYeXBV^Tz@6K{-BkGFrN)ZL
zyq+@=U;`{AtqnD((6m1oH#yLfIaHIcZZ3(PEs*nshBet6s56||kvE2tQ}*^Y1IzqA
z{T*QpVJ+mdXRE5?PMkKNBeiyE<(0{HGJtHm(g=|?%+Qx<iwrk@J;QA=VF~?4|L@d$
zvwUABoRi$|mf&P8?9414^G6zWxVJ<i@BXmV70QG0g>g^uBAIc+Lry8Cj+~x=*2L(N
z+J&*LBCLIJsAZv!4+(wOAQ@U$Ioj{`zZ!uaM%8M$OdaFm&clnr^LDqOKsbz=pzy>M
zHjale%B|kFq61!meC?Z~<j9i*4RoPr`A?Wpe;A|#TA#5&B`K+}O*T0qpUi=1793RF
z*F{ObFrqiapOAM?;d@$no?t+8U}>IKT*|UF8X<48H&i+n8Gy^PdW!noOHpb>)9CAD
zGOEpwDp5iOZkrH9Hw^~sWTI3T`B~=s-Y_s$qyY(E1%`N9V(tg8@}!v7&`NcKJshma
zrlJEbM+bVT$vNeB>o)fMmacuohQajw$$!EN^?=a^FNO*fY?yZs+W$Fn#@qTrs>0XL
zL2t+VFb!SnrGCgAL^oxaVW3t_zPQ$_95!vpf-;7pzr~$kc>XMD4903EFP@fUY1Ffl
z6VG7<zJDT!mRd{&2MVNCPg!nLFu};!oD=?_d)CcI=$-SKidj`<{1cc&k3pA&e(<2T
zKZS}nTF>&4U@C<uuaXwJvN`pwIPALGO&4!hG%t!>DH`_4=q$T|fvq9w0+Gy=DCRw)
zkQgJK0qjGPS&X!~H#6HGJE(KuAeWJ%;;FU=&2=AcT>ysYpztEcQkCjJY74r~<83yY
zgA`3e()t5f6VblJKKfV-(WJiBd}<45CPT@;JMgtgloBe_5e~M!|6&EtgG;U->@Dju
zn9ywakoX(KAf!0l?qM6cgh>;uo{Y?}71fAD9&qFyRS3rpWjAAt?dy&q+(9wxuC}mT
z73SdP?5dsqbCj1sv9)y|XkPKR!ub^K+y0|dE9TMVb(UCtcVXMjtUX_VWq{vxZv6R*
zi-X7v=rR2Dc6cZRv(i~+dKKZyo7<poJ$)~BYKKPupCrnWBv-lI4TBDyeq*+RQpG$&
zabLoz5ZGWi^@&t%TI?k|!@7~Z{ERQ}AFeKPO&w_*UkB<ISlRwYU!|guV332@Q1zmQ
zb|yGJfnVzTj^HHz56z_DJcWf#5kmRX59nT|yX_KBDZf6{pTJSi9*y%!E|7~SpTwi~
z(+B+w4;(6*v;SQUKU*`27+>dF@#YWJMgCww$rLXPd{|pQ4&sv^j~ulci`1<iv)p-R
zD}2Z2DHj#J?<vKArxud|L|~eom6ENV6i1xiu5CAeNEPTF&bxBH`g{N7hxp=@=8zI$
z7po$cM~F8%7j1<jiBDWbvIMB$lavWwZUs1_4UaDb`^EHb6OpFE?u^{juU53-U}%#&
z5G7K8>=PQ@CJy^Y8k!Guv;giupATJ7k-!wZR~qF885t=V8N*|rhbO8g#y}X86Yp2m
zds&!Jnf&!n{A9%*Xw|4z`WO86*Kdnh_hrfVuKhLlz+l=i3-*+=#8aka`!eTi^3>K$
zxw>8a$A9y7Lp_xVf|Y(sc^vkoKTO&gZlgHT<9eFcdK#U$ts`Wx&(`hTjr}+UUWY<a
zx&tLva7dQuX#{9kT)nL%Y+NKXAg?)6e(q=(XsB1%j^qfX8u?tjwI`q-xJa7E%gkZ_
z>{@4}Dd<y@ILw)G*~1^R&SKkVCD)KMCfyRi87t+b!~Ag28aEU2*T4T<3sEO?rD_W)
z2RUgCw$Iig_;}NGLNqV9-H$d4jdVw>&66bt@~P}sPUa2Yep1po^jY(XSGw)h&&>P^
z3>Y>B#q<|vDNxUyh2@?BDcJ>m?-o3MN)@^<HC<}|P=8H5E`AWep7iS~@1Nax&J_d8
zPsQSL+WHF}V%9rwg%4t!2o{4!R(xEL1MJBIw(k-WN+x^Z*Gkh$y@;L|2unTrSSpIp
zu^JG|`EJ9>x#h@Tq(diq_&R<48KZM*sIi4Gf?mY1?)(VasB|}*h-<+1dO6kbHR~nh
z(9Y{ly&C_3&nV6$j{%o$BdsUlX>k)D)lup~??)?0IK6+ZsPkpsO6EMtV&vdZE76Z7
zX*p5hXgQv6eX#4<Jqe~UydfbwV#gxU;NY?Yj&@o+sjz1zEDW0REidOW@{yW5r;B|k
z`*skDDlLS4OhvHi*+~D9RmAf{gPd?dM>_ppzmZ&49M24PnS(omTfmGlfc;ON%>C>5
zCrR_4vkN!54)HeRcHzYPHznT}e?Oq6!8vG6&!`3IDLD{57erWZ!_9t9cqwtnpHa-l
zc(j+NQ#73u?IkfkUF8+ZY`>NF>#&e(*n5JKJ6&%v{oT64ZU>y;M}9sJfMr$727h1a
zLq<bq{&^zcU}vZFI&=4jiHLZU+g#f!vwHk?)(csEgfdUi^D2}=v!*OZ$YZyW$|NSK
zP=3hEW=ojYP2crCoo;)mOFCiz(d#b-Zo<rs)N`3rPQ#<AIBV2dG3~C8z~54{^%m)M
zb)M~dolBb8I_fD2VgZRp=a{!~=vLE4epUqIh5!eT`;6+SB0nZZ&M`GEq|MJ5S^O>X
zHK%Y#C|$ODwng=P<J*p-h1|6Dzvn2@`J_Jjc{C)eU-cq+FD0ZabYqPu<^dhVtd9IK
zc@8&`Z`2JR_y~3a4gzrBzBUvbi4_i-8($@K=Q#jMoynIs1Ag{?FN&KK$MKx3{WI~}
z8}#~!r^rQ8<8WjB%AE<OZ7%-G5bnNF6zwSdXy4#TfbGN+J)22$#VB)Yb^rr@eQvYJ
zchs17m*rg}lEXeMG8Sh5t6Tbos5++#4`LmYq%E=!knx%Wt6ltOS~jW+3e1lCsQQub
z(T;sOtK+J(*k;P^TMSkQnPl8m6!JLo(exgxNMuTr&5EXnLTA*V?(D)+(jKD7o?FqC
z6p=_6mgEwPj#fmc_+iTDq`Xk|(AQRb`5({x{sZ|_AOA@UVIGs#@E>Xmvf2R;Cdip~
z8Oe3TznC8*bc1aCB3?B$Y+-yMgIMSK`XY8VcdC7{>4~mqlNGAWYpb5kNczb;NQ@Pd
zK}%-v!R?_2FKZ8#lCQ8x{(+MsKiuaKWO-Cz-ePIlqh4%bhaNw(E;YQ|Mhh=E<BHRA
zH4M*)|Gb0Eo$ZQW7XMJ{Xw$)`nwLSi;xY^TOSZzvd?>no6EEeM7KW5O3evztN7W0J
zjVAq!YY{4_di!v1Fv@LClcQp;I8AIW#c4h?a7fo~OBNs4WL$k|FY_#p@z9xZg5;^j
z*4lNFe_n8*^n0Y&WT(SwQ-G;fIuEFGsTXGExXP1*8jG3BYt-8Ewk)|VCyu^|*w|!5
zFb;|>h^k+egCYLA<R7CS{nq#S^x`L|zatTrVLxn2)MX<__+;S@;MbW40d#*_kLjj9
z@9fH1t$WEQk0{zCfiMZo`g}R%2vOuC@qpdd+<uW8Xe8`&J{70oZdN_dZ_Fh<dl4R%
zbw7t_5~ki!eDjw%ZC%|)_4-xZla**^UpXcx$mL_s{)V;fdgNcDj()42xhyWwYGi5^
zv29tn9Hd4Y#NbWel(E&5vX*JmD?HP{@%QHyrKNPTGBw$z4kt=;i3e1w&#+SJ2`Ox)
z=6glDLo^9BA&I5Mr6}y39`TGJN)+%;je~3r;ALXT(A3^!g;=eL*I%gBuvCL~#m2dL
zLY}^f+cgee(fKyCyAHuR6@-TW=)I4l<o@#*S|E*73PC7|S5u}C;}X^RkdrO$beeE!
zf=8JXF%*jAMZH|kS~srWOSRGB?A{`I*QF|cL*Z)@F_7!O^Yq7Yi&t6*{iFqF4V~zc
zw+@%c4woDSeb@1kGhn`<#p=j@(dLv(tflO4A1`gQM#bvdN+i^<w8N<WcnXhO6EKt2
zYYlKYM14ef!wB+Ej>!E2J!$DQGiz^f>|1R)TO{^%O8iS`v1ckFh;)bT4XPA6TQ0Gv
z(D(bA_^iwc_6L_U_FkGMZ9X?Bg3qRzGm99@w*pwJ-#Uv<3jGQgj}UXmY7;%jle6ZZ
zSV?8_b|KlR5|1E8Qf9LI7KSf>w-j0QxxDsl^_1&FFL?fB9$ARXe`_yNxlpyc-%^dJ
z_G)HWlX^pjTSBNp1xqSBRzVch5kyz-^e>WWuch<s`R|SiQvdmt`@dZzVF~4`t?)N2
zxCWG3oV#zloD<Aq&R^>lTd<X1Z=_>27k#GosJ>N6bo{~WXkBhplG=W6uc#R&k^|AY
zX+FI7{}La?$tfy-LvfI0jy&|^NA<$V(dKmPm%JM>quQLu{hJri7W4=E@NK+b^IPHN
z{zDcGB?*uUWR>p<Jnx~0kH;Y6J8bBsM{;f#dw67%M#40B37|bAb!+2oDtW8m;lcW{
znWu7(xv`Y3hAA3Q{fk3nyKdiI$n`_Xc2r>i|3>P=YychOt<vKYDA3F=DLGkOVN`u3
zI}_3N<-)U{T9rKQ4)C~(dxyJ7pGW#nC7jkmYG_sy+wxOJeB8O{<6YHxg4486vd1No
zo3vvy?bGWizQr*O<>*o3JcsAfa^CQU;Q6NOR;)1Z`N9J+)3c-bdQl?3XV>M9CD*^a
zWYgeAkE@@fe#`+v{|<Mlnewu}?=ks*({e`ZI!evj%$&0xE9JM|1oPhyt>5~5oU}FA
ztb0DWCMJ$V%tGrR7BgBXJ-pj-Q80<Ih(RV`CX8pD`q)+8+S&>?7ru0}C9K+cRjU;>
z#r*Gbp+vBW-KXwdElUfThF|O-w{n$UYL)1{AM+Vizcv3as-0?eIqwU$!nM&C`~Ok@
zpO4Q6d^pRj$r3Yrl$39^X#SH`KU44X#&yODNm2i_^#xa7Q_~eRr!AOMDx04B|LFIB
zGU-m_YbjZ}>E_=yZNfp}oTd+Uky4M8)Kg?I3$y13hMeF)u^`Mczb&HB1cLNoDviYx
z6)mGr$hj0zyeN^fPlRBWp+Z=#ledgetnislnGzh-RrR3Nzc4LrKM>ZpA5&F=TtB1y
z#yJu~CJ7@6A&D2DaAnv*gM92kf)EF;8C%1WUyfoyXeGmNe;~w4#Y)D?Q~VUbbB#I?
zfuf~rhPmqdkee5t;P+5!G^5cqHo~P*hq;hk^8g9VG0a7FTm}*&S&X}3>Sz008(m1w
zSb8XH^1>8I&S>%%Z*hTTC!#$rkf*@Jn&d#uNY2R1$bMXTI;*y3_$d#6jMjl$Od$Lv
z{JPvtpm3yOWRZo*H7s+h6`XF{CL%bcC)#!MLpDF!L0q3tq09gOY6EanI#3s+M>OGw
z#zDc8!DyKX)6)iQVx3vmlOlT1GLk@6BxWkOW&ZyxlpKE#0(BvP9u0`v`y6z8+G-#$
zX%foFu`W~>j1bpeSo<HEWxYQ3E}LZ8El3B||1VV{`LaP=JJ(P{ih}=_YTLy#9Fz|t
z+am{BHTHgu;UMOD&H&+b`qKK|O5GfX9WJ8JRucc#W0$D~L;^Z-UR-D&xBusj7)fzt
znChCsz=9f!z-{2lAkbbn_v8`J1@+K{b6E(+g`5+f%ZNQZ#S&J{<rb+5Zc87oQV8+?
z@BptsOyCJ)Yc3-w_b;p$Of4ZO*BQ1tvS7vyvFgCDrwtm!lK&Udhn8-iH3P#I4_BXx
zIdjDT6nIB?07*vv-=30KXCKI^4*MDQg$IQtP!ryz5ynY+y%$Gd|6Q~yOqHAe2Zs=!
zZurJN<2B&seBgFuA_%>?7mQ(n^9MJA{-?}DU#i2VBL_Q6Z6HZI=D`NiH5tqbcuk{a
z4G6e^Nx!!!z}<hrm^ofWCOKZkCOKb46d?9AppW&$azUJ!L&^QFWfKZ;MitJ7=mqLt
zoKeo4AOHny9FVJ)5dQak&57<ZV>*}BR)P#ygDN-vE4d(eT_Y@kUS4$2*e&j<S=92O
zJ_s_5v&U#&fZxN91t&*4L^DK>B~KBRE*lJ^*Lnxf*9t&b-}j|-L1yV6xtB6dFs{{V
zt`#qIFy+ROpK$Y6Tj{cTcj}KGGuNujFzl^KFzoG?J*HWoVE}f)cQ^cLR2OdZErEK*
z(y&?j<ch<-ioQ$ANtaPUw@I;8X_n@l4BRJ-2Kwxy*sI!g_^=#koJgEht^zv>14sjM
z5Zd>(mF!M+!8?1sFnhxXm3?2tEH(5uA`|FeN%B(Yv$_g60_JVsY1BuE-cuZNyrF>5
z15=n>FB6#ONe|qM`V$H$A%x0TbFS_HWaa%iW98f7c&>cA)=}+@7y0|Gh#S5C`hESK
z=2D}4gEtHRx^D*uhVuk7kgnj9VCG8r-7(<tT#z@4V|i2Mz9FrOA$#L4zsLm)UO9up
zw}3inuqy)Hy%qV4HY9dI9~*yR==0U3g4ArH{=6Zr2Na~0!@K{;0MNieWuZSv<(%N2
zC->mMJ3^A|%D%ejg_3NsNKG7M3w;7rd~=I&fFO_0up)nj(7c0;-{puLpv5BjmZtTb
z)X;3PfL22S^&$yDqqm}+aQ5K<4)mK~gM8u%xK0N8lQ5w+IF<-NQrInAEwGa=>s2ue
z_(BJj1;I7Ky*d0=Mab<DxIoZFQD+eUj(2qY;V7LMCYV`4Xdg8Yikg&bU^>TrqRiDG
zK%-BA!-|DMlxAt=DuM4e^*`zu6Jtq11_oSQ<8W|aBtVgtmZ^w5b<8T)Nl^y)I8~@9
zO9;<|<3Lpj5EIRbz4;QtLW7}|sswzhY87Jx6Ak(N1S<*(5ds1_TreVRZ*WqE0gi@M
z(?oC}lkPa{2ZQuQm|nX;Ag=_7j7A?b!L^Q~5;pihT2hz+rpB}{XC*9|KD!mK#1N#f
z3dzQ-GkuXk-0GtQh=4|4>B=G%t`WpMp{2zzkox!C1KnWR+xuVwJmTQM3peyo=Nf{Z
zan&t&fGZ&!U)$;XQ$&Y|?ZE&Jrkmhf3HC^~8T2LiPMT&3_H=aLUf)x1<iE6@=5N}t
zEYZ5(r7o>%@?|bfzv>iWf>jhl8&lF4<N1W}SSk0ub`F2bSWrsyUXf@&*}tq$T;BT!
zcEHo)Z{bgNy&?lNC!Al&0`9)tAl(ZQa>1=$bpK=~38wQgpmAH%2M|S37!QyCLO|Xc
z9Z!-cr>sK|9~$?KKj0!IcxGiMSIElG1v@Y-LI1q7tj}D_Qq;cid1uK-OX;(sUP9{%
zu1c7i2@j?wGjn~ts3}b06}A7WI&Ek$-=Lc+vTEbIH1^IcGq<U}#Jalb$biNEo$|k$
zr=<vM$QSh`2c=OtH%xU!#8DA*AGDOv6bQ>{7B2!gUHcl$G%Dy)B7H832$c31knHfH
z;FEGJ`y0xO5RNM}KLvwP3?XntQp(~<NX6g1wPdU$VrDrEabpvut;|N%xPZF`98Q>1
zhk<k2#!-~7wSjyM`L%vne%F~6iqv;{k(tG>3}gq>A-JCkswwv;LwuG=5G{qAh2e_u
zyvOY9f&Pn=-`$`-AKhG@&wZmcu|1Oz+{6|@r9Ned&OcWL2(!y6t;>T};dW1!&M^*+
z!qn~Zb!hD-v8I(TRz4(Q*_*F^9Q?6Y29aFuMlm8t<VsJrZNr(J(%W^iA3j*Lnb*>f
zS@UHR(eHeR+(Hwrltk}OQ2ogD(Q!W!`7KQn+cAtRPb9m4%FzUkzFzY>pOW03NP#<l
zS4LPHzWe(JVHZ`MGW4Mq0+&yaUwjq#g0|mM=?meEZ3U;a;yjh)-x28W_v3lXdhIA$
zBG-Ns2->!n$<>yHYhJf@bH(Uf9lXPD04b1<OOtBrDRO^pSFNTmmX)Uxf=F2sW19Kb
z+ZUJ4C2GxbHTp!;sw*&7_j{k!evQp8Idw0&mrVX%sms2ukl5I_7*8ei<1#nQihAK$
znwR|9+j(L;StDRb`jZ3wR-@mmytHd$Q*TN%;}UYJ6}Abzo26^yy<Q));#(yvz2aM>
zncOcF4hpj>ShZr=D~JbCYU~e=Q~IC*8GQr-VDrS03dgk@2`k%#0GQzDTY+;yr|I|*
zO<(EV2Y+?1o$Ro~D2LReNj{sE487se^7UGlEF<peMOFaTS<H;r>s!?O8(!qo7SoPZ
z&%0+aoYy;nH`T%m^|Ya5*$Mh!G6i3$Pcj?zxnK2s)G_Ycay4?p#CQlhBi}*rMJ7X<
z?1enzE8>oNctL~&f9#qBO5;4(sH^3~Yh}(eiPm4zb(nW342v?tGM9M%I5anRGzotu
zxLBU_^x-)UY^vM^Y?GF<Xx8qDh}jepxC+J(@6yG7C?3%;G7+okcl>G^Bj|%Y8BkH<
ztF=Bs`=~Apcc%S8CP(PsQQ?`o<L2SM&v#NAO?RZ@a+v%1CU?FNZnnXk{T|Wcv*${W
z=|>x8WroJT`+L0*DifoA)5Yq8*BLc0Vez~in>M)GZ*ysq<K>4PHIh_fJ?S>ajcdWe
zy1KkuB50SVY{LRc_Z=#{TjSSPpV+9hT^96h_sG`S4ZnXH_*V66n8=Z0X)b8??cQHI
zW@m4mi><K3OQC$Y`ZvNKlaCPYnByNL>@fn!_n7_FU!7}z%8l=uwI#Iv)$4Md@?w^G
z90;R}o#(!g(~MrS)}0KoR+0Wv5Y|z{Onq&Yx4aVfcQe&y){Weyc7IDS=XKW>h<!~;
z-!B^8>EFPw9%7xDvkoZSP@{Mzu)RDN7usG2{Cg^;XfW2jo+`g<jj_2~0_R6g7t5Zy
zIo;dr8V{;d-*-xN5UcKadOp?d>!mz*6;5gd-Jgr>9^L&CnR6R^8ftihGvcxTfZfL3
znR2CXI&yCZ+ijor$53>7LJJ(HSLl4j``YDLATsonjco6AJ)=o$>mz-!jve4DGIyo>
z$I1WfkmwA5W4-<UY_hRr@QeE9xrdI=#tjb^8*}1XcvV$rPF)K}i}CI@ZOX&zo<so4
zrGQzJ&cPqU=m$lec?acb{ogAf<`!?>b3FNLvh}CcwX|2TuBf_qT=9Y8pR;+k%=92%
z)~6Ux_dF!t2hVcbk`W8Uut<j~qE3|%B19_dh->VfI--B*i9t^T<cEZVO>6pWskI&_
zpNF~o{Kvez@=_kNhjKXwJM?&m&?a^NW#2bVuY<ShY;?Gv>~7}VC`{I5^}7GP>R`L%
zIomQI+RG<vCk*x5X2hw_ZD&yaw&7cdh5tyJ%haD-Gh>cX`!_n3EdD@)tdTs%I-5_9
z56Cov&pA|#Cp@M?hI+<r#=68GrqUy*1#IM8<{}@aLR9CbQQtn(k2kxpWF4szp(xDf
zGiAD&+oYZQm+=lrf}FdSMe1AoiPGA=)`37_h2sZVt!il9ysJp_559m;soYtRj4{2;
zNFj6j2F{4yXf6$N^<k-8#IqsjbJU1|kt36vLYQxyGFnaGBt?Il-C6pNp-VC=`sOYS
z1-2?YO=R2FOrjUe5E1nEY!uX3O;!B%$w9gchD>GwLy2{h66IkjR^?_R;kGG9G^AsN
z(6{Z$_Hns|rKB^?%$D;Z3x8#nI8(Y|v$D3?54KAr;aXU$(Tj55jI8Lfw+x00nM;6`
zGL|AGE7DrCeoc!VonNvn8i$n{|D`*MLU!)#o~Tc89SOW%^qr0>Z~Gc^BZbUP$mT_^
z|HfhXUEBKoT?Sm<X%-{u5H1o9sy%_CE5@QLM67LPePTstw?WovYHY5$YYj0KF%@<(
zXco_N(N~qxR?G5wL@5Uo6|D8vyOR}VuB()UUzE{L5eZWoD)h01$pxF^JJH7<<<}an
zDN-2k8o^h=(ZNR-?lQ89ZKBmBpv=kSFIt9<Ufw^y7;Aog54!RCMYJn;`d!ZE3vBXg
zC5v4JTJ)(y8~0U3^eOLNn5>ScwPK>bw(n2T!p8hEaJx-HXM5QQKs(h`TVG$>#>+<i
zEKGJ0QKvX1mTF2<e|Lh#Lwguw{M)bhMOQC)b^4W%gJvRG4}e*yokFx0b3LX+*>K9O
zl*4#;ocX=9a0H+Od!3r99wsaK#aff}hLs%wQ9FfLM`w6>KId-dw}`c>j%HJ51&aPJ
zA+w*s$2NW*22_VlG_`nRRmui&{RW1p(y5SNggTPr$8^kC8jiJ96)^Uo#lAx<`9Tan
z)DIAVp>BpAv@tDpEk^|c;yQ$*7&ohlHuw8+q)nlpHDbUskD8-gN<6qMI9aoJR}a22
zxC<uZC~tNu>2lL>)1h)H|5R;7#x};%0MV|u1rC&76t%na@p$RN6d1~VoW?@>Fu!j;
z^+h8|4-uWEB6{?5rs1EFO1rztp!0HMu7E>+EbRdm9OC(o__X639iK4SuRc2Sq}V*R
z4c2OiaeDQ`h=dZ|;Kni`ros{$uG)5T{aG<^#qU0Y9d}(_?9-J7(C>Vql8Fs&B%vGk
zsfwy}!xTLOu1afw*aN9O8XF}qqR-+W;a<Lr%_5h9hw9hjLIR42#ldA}-G#s*s}=j6
zu<Qwg6^oKcIF9Ou532xuLlac2D$>UK3IaRyd_~+{AK=jMih8Y5{P6L-u&VWQlnS`+
z@-jE#=oO4vy>H0kAF4jO$Z>mBg>}tV#rwg5rel-lg7M;0CIc0f$I&Txp-*g;wI7hx
zqgc;M9MR+VIr^xpb=PE}C%}6<YaQF5{e*MW8SD)UOesv6)IL@av;K#2bKz2uxm;Tz
zUG0pKpHF5*PeUM9dOV?Bb_xz6S`3NmQc2N>=25j~q%yR_@S9bF);cp|@xNj<qP%A}
z;OHQsLko!Un~wb2^>u|=HR0Z5VxMEE!a2I^9w)a_X__t(Ve0;%wzlfoXi@IWl@-;O
z_8^~GHWzG=Sq&vZEg|^sl8CfwP+nzn{!<|S7tB*eWCT9#7O!;6iW{_FKYkcY2rRbx
z1oD^Vqxc3{gjk^!o(<~Y+$<9X#R(7!a8riV^!%RL03>4f)?|NV#D;HLn|>8RZ_WoF
zA4dnziR@E@rfDowgs&UD4Ub_aW$JM|msf``6kas>jWucIq$jZ;4iT=YqIWJWHs?+b
zx94{9A0Nv3_{l4kgv)_Q>oT!sJTZI4gRJaQVcJVD1;=>nAP)B*m}}t0Q`&nx;4*%s
z9&sIxiKan??825wMf0|qlH<IK>K{6*U)sN3VC9=J?JCC1IAsMS%n%1OjK>>)!<DY}
z8a|U`cY_G{Hzg(qX=4|Od?;G?2-TXuHUa@-Ep_`J!4>VHImrKH0mA&#AvT0rU8|^5
z+GtF6Vm_}5unzBuc9(}^)h0>v(sRt!sV%0*s6;=D3No&2^15P-m=vD<ng2E?7e84i
z9dkM`ksWn6TYfh%5p|b%lrcJc_Y2iv<)g*Wvb^=$y!_X%MWsCrHxp*07RmG65o^i$
zru#Mmka;uazI?&LGY2U#ZQn5xzU8uCr)IV^OiabrMF%Re&7~y=mi3%p%w}Z#bj>~0
z9zk`aQ7d;<bt?vi!$mzeqZ|%azE*a86G>d37`c&uuB&)ksgoiH`>Pn5%OR<y2oUM!
z#hsAz3E7)_K3+6Z_^lqs?h<&X|AKqRbsAHcErHYO=fazpmt9N7muJLM?*$Z^{c>;^
z(&HCnL!|Eg9(Az=%D$P+h#dmWW(cm($ia`FX7AVhnIA5aS;KFbALa-vvWgGi&JZdX
zwxK|H{90mD$f2{=$qJ{MF5;=8G;Wym1&<q8#aY#0{fDG`DIU>KoQS5H8vVKZqAn2i
z&H2R!+I=7opLuI2PG$4roqzi$Xel1~d!f&XJi;b5Zfn#0Bd6raFhVso{<HW!C+w-}
znHMICD`K+nNK+Srjag{8W8|qDZc5}c^Gy^E>OaYy7xq7<FN}(bL@_it)qnEr{vJe}
zVZW~2RgA69V+J&LE{?4#qrW=%WyLi?_TK5Rurq+)-FSE8=y=U(&^P^o-26LBJS8Sc
zV3yP)8l576b`q`rs0{5d0<`U2qM1_)+89;>ro_EI)m`e~5C@!3Bji$;D~t<C@nLPd
zk)VWU8dfIaFh)2+U6kmHB%Dt?C^=z{QdKh_7|?`6F@$u}6_`<c7HCz9b^0)b)YFxn
z35n+S`si;Yx2bQ6E?7kw9ZE{Wybk00#C+u*l3p3Ii>$*;kEVa;=HkO2BF?I@M{gX~
znmdC=X`BH&Gxit9s9+@cT6bs)JoqX|kM!b^{GuJ+n++Zi4_|u_1Uc!kC%zCu0e2w*
zN`oM^eddzbV22(S3~vv3fPWA~1Db*ec0vF!_Eh3|FT&Ld2SUuDO?cj-$Y4I$T1XJ2
zqvr(X;*rcd2Ns}rXfTTaUWKbgfi9wZW5NMWsRyagCY9TVL-dTGi=^I|NC5gk2m(|G
z1zZsXsqQ(Uf;Pc<i(-QL;A<&+PAs4v7~U_e3vg*|!QCJY6l8#CAOr@Q0tX&~sm%(4
zxI=ldz1iRZ*zmQyJtwx%Te6E)B(NA9U<;;pzUKr^l=1k`7Bn7jF7GRMsu+M*iwvL-
zg2+I53B4C#YK?**Qc#a>e)hIP<XRjkAu1RzNRQ~Eozz<u84v&u@PeyF4uXgWLSlMO
z*q}|=-juKa>rk>Fm|7U<V$h2d*9930SSv`6?_vxQfCc5n_ufDRQy~D<;r>(Oc#l2v
z#VS0w3l4A)2qE;v`+oLo8Od7~rdF(n1=V{42J9B3hj@{R3_eHtZvxDL5cExO?30Lh
z6Ffk(hlS8P4jwSrQ%UB%2w(dY2qA;sid@*i0Q`a=dOatx8nh@q<J8_Bi0?Mhqq}H_
z^;U%i%m+anpdQQ@hDhLCBmg^ntsL|g_Cg2-+yxI1pEHtGN(+e>MS0q1IL-R9^R7oM
zFcVy@7L*s=n+@T=F}&Nmvgd>ndP{rpxSo}^=YtJ63(~{5AVUQ!1wvT=W9>`gEs6*R
zAOha)UfOfw2lXJW%7<YWzBtAN&jmrep*jd)yC6N$3qv&U5=<>-k3I6mBisc8B@5XR
z!UbmpiBjc&zL0t>{JSOeK3`-afwOx~JfTe#|FM0ydVCPX73vX`TZrTv6h0Hv$o-OX
z7rgvk6#Wf}^tHi|o<8|tBF`BIAw+w)8w05q==*fW3_aP7z!d7G$uj@}dovi(iAWfF
z^QTR;(ts_WM;A{JI=>HbeCrL)ST3vi$!p{y$Byc2!bo0*mq)ITZxedPLTp@BnPr<0
zDH*LQklfRip9m2DHk!2FK89%hpg`_f|9Q0n#gs6sqsD3UIDD}(&AVF98Rw=XZOa73
zR3Kt0Lmk=Ffz;Q)h@!D17$Ef9BQ)ih<%G<<THZ2hB&j)H|8&$)T>Cc!x6`RNxQeyI
z#F@eOPjEY;hsE~tUj)U<kjyH?@Kh^QRBZ-0RfRHmVj`Oy1Nm5?kY2l{hW2)$puPh4
z0fzSj{3Bg>cp8?7cRG6VL6l)=N{As&x5tYdV99vx1Pqk6%CplGy4s-2Gt^0`;@+OD
z!6B=!Y;878zhR=q=Z*360+;4OV_HS5P#vlGbcz}9;8krD6cRp=oJ5LlN9rno_@9GL
zNDxDOj5eCvc@t74&C#B|e70ObmE!<MU?1^P_n}EQ;MYa3Gg|A1$;3isAXjwvK!^){
zAp=QoTq`vxV(&8eApnw?p66_H;mY8C7HaR8^olK_xV5AB7%-eXLC4|Zhv$tm=A<|G
zeRRZswCo=qN#S6cgv}*mmFrUylZz=_!T)UH7=Djh<atWs!+uOsV_>=|MxbP5Du*Sb
z*k)9aqvs^UWWd3jm!oSVblh_!FI40(B!iw@h7RMWnj2z_mJ!E>$K2lD5)-qQ)yjA1
zeFi2X6EUA4WVoiI9`hd|Cc}oWfGJm<wk9fWs?0Wmm8y~$M%zd#h=jj((vVv%K}>5Z
zvn-M#6(OhQs54rr2OLr!Gr$r^I)`9QT8BZ7B6E5=`e)$JX3HQ&92GXpW6MGsBLG8(
zYk&>v!Jc#*M5A`HFVA^v!dEGHq7!S}A#K;NT7KDSrcIA51|AqdGqBKOjP_lL4|gRy
zJ0W|f^Cu&D9d0$*r-pi>bdk(pOj?9UylXm592x!2yxjELq}{!c;3DB2dBo(Y^X*X2
z?|o>i#M+AaF#8c6Net;X%Fr0{m<~Fnb;2`ZAIhm;Gjs(88KZm9k&(tm#57E#s`>TV
z9(mY+1qwVPz|d`9aMr=Mjv|9OV=X$X4cznt4E8<4_;e^Ex^eyBM`y$qnFimrSxX|7
zADC^JZJ-9-E$i;-E)*?MhGf?C*a`Mt&XbdaLVk{b@uuI_c6TZJfj$$yy%XS(dET$*
znflBoYy6WAb<nKIsgKedBKw>kI4K9-*e54BRyjbc%_C3s2AXtHo0rn(WX+7Ij?0NR
z)i>=j;N6A#e%eFXpk!Nwoe&H*Z(+m^62yk?OO6fKa+d!u$j<k>(DBI~6%a8tR_~-!
z^bUo7rTiHb!HH7U!E+&W-^cYlgNu<UN*(>40KN5ty~mJ=)!LQ=omFz!gT*n*$Aa@E
zArkR|&%KalEAiecJ_LS*+MmXhZ48czWNQH}<WBq({OMnNF#y5=UHeVfvr$${{Ty{j
z%?=>|4x1n7o(&_xgJnL;-yc@HG8V@!M^81~M3$m2csWuQORxsIE=MQ43UrZ`<DFeM
z5z<#?b~>*Q9x%iLx|%Q7UyZD1(TPGL;2}l`y*s1zQ$Qk&u}aLiR?3Z0n0b;7>EAec
z6VaoW`>A9%7T{7B@tQvoq-&infF8gSGlTI05mkJl4LqD;D=8_kb$3KT;N#=~(5&I7
z0!bp&)0zTp+Uvr)!TKAhyjGfpt8V1?p{MQntk4E-3L4S=EE_F<@6Tz_uBYvdZOmFJ
z8`rfhPo3QA<eEe5q@np@SEfd;0d{zDx>3sr6!KeNeBJ?O1&@RzG28eroavD7WSwl4
zb^ZPd+aG>cw4MT=S4+&Ewim-}ql<Zd;TB!1DMwEH7z0`~uuA<xWsRPRQ-3v%r@?Mh
z<Zsz6=;c>UgqT}}<wOv7$h{o3JB9n{#B!(K(+*|KRx{YKjs!90h|8A2*}{&Ys!DO~
zc;*O+n4gCtgS6!Ew!@n2Yp+fAd>Lfg-eLXAi8ao%ibHt+@RpV7Fm{74{0WTdU`SnV
zA0)qAU)&>M7Ul(+n4gc2muDCIZXUk4x2>&>_}jm<u*I!a6w_~H`;zfKU0=X2&3PXl
z6frSFd9JUM5yk0Qc+SPV_a}NcI>>#<<Jk*kIVvLJzmu;WrY!raOiCB>w33VuhOkk2
zyvyWV_VKxh^po+N&1}mlAFB6e5*EK<li6|oAjUdlMJ#kjq#>an9YTOKTGkUVfr8lk
zh5FO?vcKWI*1_LGzHMjol5KweOhqBm+WO!)-t>ed9nC28DN-oCw&15Mk%@GODpPb7
z#E3N&3We%Fn5SR{GaTMnS51U8BCiq?SX|PkJ`h(zcu&-knYd1^O!Ki~j0Bxt^i?jo
zv5~IXiN(_AQSQPK5r+4hMP{&<`sarP4;|1@nI(IEqkm*7huYN$iJGArO<SyH^&2%H
zZ-er~$K%+z+kx()r4Vq5xv~BwPym*|WDkh}j$Ce*+ANlAs&%~QDsuQ<VdXw@P)h!v
zHsELZ(%2t;!MacE;;Xs(I=WPj)O?j=xQ^5SZBEKMG*AV~*eNqX;TfsV)Kx$&Z%vPk
zs^bBUKh+I`$yI(SjxmgASkRY(CYLe<!<cAz!x;ZwsFt01b51Nt3g@g^wgp%6ndRcL
zLyw%4@#og}bh0Sz$tR-<&m84RtaR9k@}opoSpO2ft98+rj>f~`x-YL%e|9rth{m8L
zwZ!;H*OJgN(r-!VgDJNr-$k?4|CEy3!jp8zkcq)qsDSnA(qmp9EFuSB79Nq`RlW+L
zLE~y}#Kk9RMpmTBxF8yS#Twq&#jVdgWq2CJb;Ijxgk3|#;XaZuhdv5quES(nQHyR$
z>n074lJA;aasG?WhV$ax@k-J6L%%sxP8#v%%2-J7*#%s&3QB)QV=`wnpF8CAOyXb?
zj`HUjF>HaIe1!ExKvrh@GQz_ZvXJ;Rg1?(*iSLsPmKUQnO>Wpt0&btJY;B`5c+SOR
z(DNs1X`$<_F<P?u`~)jBCz<TR2rB)c>qfKM1cZXf5s0C$3}NdkCCM4PeD%LX6ql0I
z6yR4>v63uyt*^46kcoWE0vSffQ4a<x3NhjU6iczTJQ3MkX7*&qUH_|(|H8BB(-0Be
zKNQ6y3nN>oN694Q7R6R=YgsQ}?d?)?h^tPIDbdr{%g5IzKWCpNdV=`u=ZOpr3cQHt
zVlZg>M-h_bt&+Qwg-5ySe>%|ACbW!DxkXYicPFp}NBhSXv5+dvjmRXazsent!Uq%P
zA>&i(^CEc4Ider8B`ZE?o>9078%U%kmyV)aa%baFCrppD?26dpIebU-y~xy<i@Tu>
z8AWlU|H$xdl+u#cCqYD-FG+9Ivp$W2iFpKZ2k$wI9L-mcc!U{eng(ELLlcQ4!(#3t
zncHs*qF0lsk~WTLO)Jop(#EOltiw0wF{dz>k_31px+0hp?FbBvM*fRrjNFTy3J$JU
z`r|M#7&(rsM=uugAhh#&AS7}acbbz&mS&%3pI(=4ipBkx8ZVoaad<15E9H*d00ehS
zYCWnI*)_n-M>gXKX9suSPb4$$G#x<3!Q3VlM|H4x&&P_z9LJo*oOxhmrveQ3?LFwk
z9M2r-U9|ClZKT?OPw`%{+BMvOA5I!=jfAm@p~*Ifc+>+0tH?AM_mV_f8ONM#$3e!y
zqL(jqGSUdQMR?49jI{&jo{maFB-WeY5@E-7;9F!G1tB7qcyO6~Bh4c{68$P}2h9-8
zoh(IUx`wW{{&8A#dQf_Z04gUjQ~4E(oI8y!?UYP*gnoQ0iYw~Q723$NE?te}yQ-*M
z@pp*+`&&P-L8ue9_u~l%o9>6^XfCz%Gu0)=j?ch21|jZjU>OY(T{zu;Qsn6GYCgFL
zq<9Y~4ZNRx#8KA{;#}Yuuo>u$B#lhQrHs^B1VI)uB0VC#Xf{JyF<cRMGLPr3%snV~
zd<Rq`jo!PE<9gAbSAJ$G)5fNwk`;;a&Miox$;5%LthDem=*OkU>7XB?8=}RMRFR#K
zp@<MbtRn%nG*Qe(36R%eU1I%bGaNm-8rkny?}I-H^sidO^`bqO6$$hvx%{wmA8C!t
z&e<3h$s`ld)77joa2^SdD^H^)l^w1hrT_i|##L<RUHvdmE2*?Kvg@I(l&<2y>@yM|
z_>AG{==&OD_$z{Dyp80IJcb;Gd~8`wdDY$DpCmCP5dtKfsGOLb_?)G_avo7{4Da@A
zz$K=waS2v`6c1^Iz5M#WJw$wmc7Xofoz&@aWx)c%d^NQJ_`q%$RF2O*2+QI<Xe87)
z2m&-T7#y7W_&_ZQ1}G?yq-Qs<EAS&MJnR>EJgecmcuWPvQ^Ew;Wnmg}ka`b7PZ#VL
zm?uO6xFJLp_)}^PR1#_pbO9P57SO!sdrwgyVqibqIjjnnK2ka!2#$jncze41upGz?
z>xU?Uyetf)2j&G%2KvJ{!`-1TW04Sp&_Mw`fS!jy_&|6#EO;g)3Pcq&0a$@|Tvni4
zk6_QQK;^*lAWP5Fz-0+hV66l?@UKKbk62LeJCA<YCqy}zAw*B)Q)&`)5^54;0U8$$
zpg9l^s0Ad0f_hYXc6%s#e)TB6vuJCuz_);pc^`++vMRZgTTlQkc9`&hWowpd(39@x
zR~#eQ*AE7quTaB}>z5_{ITaWIIMsOP^*SzV-Z+o{{BFM8yR>+<ywutdKX;sTF4;9T
zX#rQT&UfFe8DY=e-mu18s8vI<Hc-6nM*_*k$d&!v&gK@+JY2RG>bfIQoeAE45+M8~
z5QVbkGr!()-4QQ5_F;-(IW1ngI8&nBPxfAX=0?~Q#)GPEZ#lmm=+PAvrF>ksrw-;X
z5I4nx=2RjI8;AV}Ky`kAFS_^%4EIWX`>q(s4;JsMvT{IoR^*0GS`&edo-sF3_WS%+
zsxNXq$ia|j%1s(4<k~L$O+2DLqeJ+z(zlPI2<Gw_Z<IH0%ITp37@VY>h=1}%-nwcI
z8BrrQL=tGMELiRe<D5pxRRd5R15npY!!iOQm%0Pr$fpoRNtK5ZFE6OXaW}i)roRTs
z@X}wG{`}wpR&o=k2TcD8K>uh9?<)Mjp0;YPNW)SSMRz1q^Mu|eq5BFO%@FMVir&`a
zwb7)>V4?u&PB<AgvE*#aVx_%LEPjJE==tmRN@^+km-gO#`s;g}AwF?2G^exwa`@4H
zgg&6R5CQMXc{?C8OhWFBwjux(9S0pZ1}6r$lrEJfl}=4M`{$tqt2C>8l|+>c7_knm
zj%+qcKjeM2!Mif;yyG%Q21sXz2oSqc?Nq<-3@x-%^3THNqC02*Z4yzfFs`&abORkY
z#PpkS-q<^xk;*uKrHzj@mu}u*cH9P#ajB&irmWb6Y;udwj^uImXvM-?4G%wAMYWk1
z>ob4G)r%n?Kyt11mJyLgZPF5sD@Nss*`HG~luw&kbcc7$_dCM%mE%&p)T+~F*`Q@h
z%l!pNB`b!Xb3Fp9)uPXN%nlxDdHiv|eLT3SJ@GohK2bkrA14x2`I(A5PI_gzLOac=
zO}bB>O7<<TAuc9Xm1&T`Df)dU_?lUgKBlUyidiCE@^>;xaE8L{++L0EART>D?OUf$
zichCc<-h!Yq5pml0#TcP8DSYtJsLdsJ?}hgy_Edh_|r1x+_FVFShV}e{#V?X(U{p@
zk)6)`!uKX6lNzz|E(gqdtj2x)@oK*+Q+@TdBuBw!sjPWjXCo^k=QX>vKh(#0XQl_;
zD*>f%l5hC0#PArfy|B{=4yY3-*%bQZ-ty24z7oCy$MzP|<&ug?ZpY@9m92gKtZ$N9
z8bA#hjjjCM{OtTb8fy*znfm-D$*kaJ<TGp`BKMl=1wN3Y%vzUY^4fkQo5P8N(Uzyd
zT9YGx)5fM}z?y~QG@^2EP%mz;e@Jr3w_x;;oZj2s@n8s&GukE<So}f%q7COG0|x_L
zk+XuEf|`O^BzKXRrNPK*f-3Er^j!o6x*+kVFr;v~&^t_3tVvWh43F@oh|lOI<n15b
z{SIGeED8=*70=+-WE)S`KDU{ub@X{odETC-HW{rsed#zmyK50%IyX)yAR-~cUE*gI
zWM!`6m>|`qZf13GTrL5fnLYLY49l@+Z^Cw<p6zme+PxDzLthhKgS40~{cwCzJ!@&%
z+IrQ0`nIj*4fI9;3v+aH;ea!mgiq<I?-SV{M-D_SQFj}t>T?tBIJ%&;rjSE6`Kp`q
zt(9%jANQS`ZrW}44|<~>VrP(Nbf3Hy3d$pT$SXNlRrmd;zmH<$oqLke@ea2M+g)5E
zTcu*~UvZrpUdj4<g`1uqQT6G!4+OVec6R1zjj^R0nncWsQ<-zSbWhAWeE@yeIwJR%
z!IlBesiSJnf^19jHCN|(&8tRKbpu9Jf@|`*f9Uh>5~m+Vto?VtZMq>Db<fmy#WGO)
zAdHEvj*jg9!^?F(_^0WxLAAL!5A}D0TMt);u4kfJkHba2VfU&A`Rg`i@Fe6|vI{Ew
zOu&E0pvJ`r)<GdU{hp1)M!h$4HKCFFckyZ#y-{TR9r>>58R_#DN7Mm$19P}Z#Aw@x
zb6VZzU%Egp@zwY8)B}d=@1)bycK`k_0Ej?$zt}9E@7MBixja9q<>Oat`Gj#=K9PIq
zM85t>i@mLIqmR~a9O5I7@R7@X<cB<D82_eN@A{jHedJni+2J$4<CwQxKE+3__mE-z
z<%>}cCUIm4NrgARaquow47ZnBxMAD@w}9nvQnOD|UnW~gBiTa^kT1w_a#~w$Ik#5%
z7g}CXr{$FqJm00|w}?ES!1E1SUd63m)t%>j&sMGD`S)60&8<*9kmr1!>P9Vha_?|*
zt2wz9oxFbypQnbew`R7t)@$DK)>6$8lmki3pVW&s3TIn8g6C_rd`2gp&*u3hEuYEb
z+01=fK8tH%)-zf@n`>?Me4ZcD^1pEwf7__#b9ls?vq;P5a<+5xd9Lkkk9a#Tmgg(I
zdCxnGvYCXzJ5)63O9qo<l0kCd9l4P39X*flq+1VadEHhmzpYlw=g07z@7%xh_*>6y
zb33=y?Obbj%!4_NEgpGijE~&cM~?H6CwO!4lHv4OQ0d)%fi@q-pD_s2*06y4(}MLp
zKZ|XAV&_6`pM_li3%Pw4p7ho4BCdl)lfC_H(Fz>bv*l4Ozsu?!SMG}Uk$tpu*H#~S
zySIFgkCyH|>LY*QA%oWLTSR2hi^F|;w0!9#kCsfH<|E(X+jA+`%l+}*bKJkvyXUe{
zAGyw3Tg%?Ukqz7iEqhU`<uPa3c`bi{`_*#2mOn^%9?Wy@^A8=sSxh99bRykJZ!(Z1
zkr5=DOd@>0tl($KBYYi?JgMa?6SVx%DlK2dqtz<D6CUIHb2V?bdV#OCSM#{E`kZgg
z<J`v{pYN@cHOqaqyN2^#JIA}_lYv+J^^*s*{Hb~^UpM&bHtYC4eVXg<=@B?%^SDn>
zyVhQKnxB`?T-5Ssc})AK{^}Y2d0ETXXYl+gy{zBF^Rs_s@#nb(pXX=%2CnB9_#I#)
z-*p>#9DI?V^)Fe7Oj*g_!{%7?@@Ag%UHA%*(64Ydo6l+a7Q45uw`BRq4qrxF_`T*e
zhj+`@E?upk*SU4xka)fcJyeH3HN^h#3Fp0)pPpMezc=|^=uLiCdUKs`9D0-Ud-J0A
z?r+d;8D6Vs;L)vt$MJ^U-f?wXocC_twhnD&Y+hr0^W72qZ#$ypZ}GGI?U`D>J)Y-W
zx9{+qT;p?EzN1phcfwnX<g><|{5|1ar<U)s`|5qyTRcDSTk{^@)$curHNU&=_YQ0M
zZXP#w^L6ju!gC&P-sh+8`*-l1&-{Lqx5f8F`pB86*WdB+Jvlt*`|AT9OZRe*-FrsM
zKU}Qk`;xT$qnX~b?BD7mAM=(!7JcMmZ|i=%-uE5t;94#JbQ=40hnAj)g1w{mp;Yt>
z8LifGi_q%$&FBz6`#<BJf0)-F=DznipYsbl?%b<(!k7GQ<4Yc~k63ulBlTBJ*NRzR
z^ZXlb*>Ab!P88ybubSlqKLNkv=l%EmWci-oXnyG8p)<H?{P2vo{Bw72`P@<>W0}jB
zJ>NiKyeqT4cWF~6)U0xib7~r?BD2YS!XrTwzgso&n_?4x>v8dj;+o8J?S{%eG1KxT
zJlFQ1Ae8W2d)pDj5j@xSra)u8Rw&SAe{zKa-N|!p*9(%K=e0c7bS>xx^IVJZf?nkL
zB%W($tRN@xT#K`UA)M!Hh^%k%M!~4}iHU-dw={a6pMr74zql6&#<e`x-YNu>mFIOl
z*P^XpF6OxwNd(Jmo@)_N@LT4)CWUK53HH{n5>8~<gN-uSr#=T|U(Xd3Za1Z#=M6k>
z(sFgkwfm`+Jb#Ag+TB2~M)17QE2@HRtShzL_MF#gA=tdXyCL|SJibT9<VGKPzfb#p
zKJuP_A@BB)cM;F;K?!Xdz219;pimz<$Vc}6?urnk_{b4nZy7>Rw2!>XTW%ZSZMk-v
zyydV!@AhF%Z@K+4uUI04Z}PaM!Fs}X`_v!xmOG?*w1?DTx%d1X9`cI+LWgDE`slFI
zr~gAfvTyq(-m-nEk9@>?e)~}$`3rBkW0=Q$z^7vupZe}Ta$j%$ol<?|Io@(ackl5#
zKjb}L*L~h{<YXWDxVPNR|7zJ&U)}ETmb)k8N!KDD^X}jMw2$n4qZ4}Az2z9mM?T^0
zPd#`0$cKF7vp({9Z#g#F+n%uled^=9^%?8%mixqd%l*!I%ki7N<w0}sHrOl=N${2v
zC2x7yPH+3BF7}aEdCO@z-g3I$N6z(;8@=U`KK_)k+DAU%Esx6bmNR|)bM#~%d8v=Q
z+(%yPt^d*Myya|%w>&o1yZ`ue-tq(=eN8ywEl<3Mcz$<WnE0f(yrtaZmIyuC#d-OQ
z*v{eQ|6;omAGz3TKcMX4&tkjPUj8Ar+v+Wc&-a!)rh3Z}CU3dR9<TL_-IjXkOT6=<
zx4h8cEid(s-{K>7Z+Wfv`5^u?-dlb-*;{@y%Uf>9^_JiDwx_snrnmfAy|;X9iMM=e
zrN=!9o}6Fjb-sz`pY+!E`HepH>wV-cKC<`Qqj<sYBm3~Vu*u`515YkAc+Y>~EgyL+
zVZZewkpkfXQY@^*QS*gmI;+kGHU30zNmm*zY07q`LBTgO;goPjI4k_3Br3yD?!(3r
z{YCcsNqQVrpniZsFbBK;u|GfO{;n^~E6So-w2Eyksg~h5CWZQJ!oJ(s^1b0XaO0Jl
zKQ)n>zfVlbTJj8G|2p`3vWaYgd^6cfwnP3F*-7?TZXlv1&5{k6ZW#kOLODUGXob~(
zhk2v&J>+db{sHqw<p2>uItbXP90J^_93d3ewO#oN^G4+;<ZpreHRg@VF<$=-uRqS~
zzt!q3BXJEGxQ0<|4VFxNG8&&`;i`7wth;g6Jvi%Le6kOp>}OBdzdp`xhq{xvp9pyz
z?C~q;Vm^qfppsjKP@z4k6C#C3QZGyrCX?F*hfqcq2o*vFStQ&dILTeYB4H7^S9nNx
zm@E-~5`H2}h4aFBa=-AK@Ecjie(;VwAnHXuSuR>c3wcnqi8k_(7$gRfhsAbcJF-H&
zPP~phB6btIk(FYsm_;5Honj5yD$WpRkOpzKIGbz}=Zf>lTVlOfPqvG9ig%KC#AV_#
z(kMPCK1g<mYsF8<PU=S$a+&s}eMu8dqRGTX(`mXO(nsl|0+pQ7<AS6s&=m;1bw#=&
zp^t8=ZmQ5%SE?%&`su25)k2)EMpq;B*Uiw)5aM+o=@$qCOk+%W!jGmq&4SQmv075Z
zS(Y0utHkI13jL;uKl|P4w^+QSh>C$4l#WVAsw&qh*HNp|S?Nq|N>`;T^;fzn-DrRk
zr9{y{rH9gkwo!U2J!z2AOX)@1Dt(o{G+2pK;%JBxuf)?(WuP*Uwo?WxgK3yDL>WTc
zD+x*h4OfzsB-%kqR+6b*NmJ5jM`emKg?3U3l|p)*Qmhoy2&F_Rp`Dd7rHpn_DwGP^
zRk=mEg+?khN)7F%%ur^~?#e7>7L8JFRc@ux%5BPRw1;xLayyMt7AOm7Pi2v^h{h^+
zD|gdg%Du|Hw70TUSxWmT%amobud-ZOPWvejDG$*&WrebW_E%OaD`~v4N?An*D65s#
zbfB_ESwjaYYn8Qhu=1qxB)wi)r>vtxlxLJ@=uqW3<vE(5tXJ04MCAqL1)8M1sJuvr
zDK9B6(PZTn<rSKuysErPQ<c}0*XVF%tFo1*Dch87G+lXHd7F+<-cjD6Bb6P>4w|97
ztGr7`Deo!o(M;ui<$XF@`9S%AW+@*kAJQ9?kCcySw(_y^F&(3PqI^PgluwmU=~(46
z<uf`?`BM3kj#o}8r|1ObjB<ufRL&}A=_KWxa*p1poL4T;$!aIH6P=>=P<zmu)t+ik
znydCwd(k|#kJ^vstAo|+X_1<wCef*CvYJdw)KoQ<ma1uL8l9$&P)E?|YNnb=9cq@E
zMa$G|HJg^JIcg5AP{*m`Xr($qoj`9<C#jQYl{#6SOsmx?>J;i!bJbj0qvosmv{o%t
z3+W8CSS_YA)e^OY&QhnT)97r~p*rZ_)N-|)&QUAXN;+4qQmg1Z)u}q^t!k}WOY78`
z>P&i@I$NDh=c{wnIrQ)9JarzeSL@U|db>Jboloyj>(zRCr+SBa2VI~-q6^hU>LR*G
zeL#JH-laaMK1dg<533K;yVaHIN_vmFN?k?oRadL4=@NB~x`y7Tu2t94rRtOFlk|Rd
zow|-LQ=e0xqYtR-)%A3_x<TDQA5=H08|g#pCUp~iSbbT2nXXVbtDET~>K1hiU8%mV
zzD^%ix2jv|Dz!m<hd!q6Quoj&tb$db&seFI(r2x3V9@8RvQ?)4v>L5Oy54HGn(6aa
zKdT?zU{$RueZgw8+UQ1WfHi==Xl-L{LpNF5THDf>tRdDA`m(j1wH<xMy4|{+ZnidB
z8|kaooz|Uni*=WE7k$mT+q#>+Zrx+uL*KCOweF=`t^2I|=$qF4*8Q}>dcb;sZnGY=
z9;9zs4_Ob<x2=b*hv|0f7uGN6JJuuCBec<a)OwWeupYA>qdTp~t;gxR))UqfbeHve
z>-Y3M>q+ZLy4!l%dYZm(J!3sX_t+$xL_e_UZF;)bX0RFPhc=VVMEBV&HVgg8rq~p^
z9|&3L$2NbPKRsXzv<1>nY(cglde9bZ3#OmiLT#b+kS)v>MnAKK+rsH#TW4Em`nj#E
ztt<V)*3H(Pei_;>G=Y8v@jVYt)n9~5f=kqC=c5=Zb`m3Lnl4{gs4Lc$=&E#1U9DnQ
zIw=uK7bQ~Zu0$&_O03dH>8JEp1}KA+>y@GGR91#7Hz@^5kup_rDCJ6};#6vtnaVt+
zPN`S!R2C|Wm3x%?l>3zjln0fEl}D6EmB*CFm47HtC{HO*E6*zbR5mCZl}*aa%4TJY
z@&-Gl;cRMzQ)-v8TiK)RRrV?Sl>^E_<&g4)a#HzG`APX%`Gx-sH~Wr;9ZxLwJy)G@
zlTakRqQ7Do@&_!_|68&QMV9|y_aC8D|JnZ#e(WdEb-*nLZe2SCc0~}3)kgLcm0?0B
zp}Wvq7$_tOBZO?YbL0!tgeqaSFdyz2ONAA}8sQmXqp(GIOV}ms6AlSSg%iSQ;T-gA
z5OxZCg@eKocydO#2*VmcKf$71jD%Z7yqF-SiCN+VF;^@RE5(^&op^`1SX@fN#3^F2
zST5Fz^We!n;&O47_@uaAd|BKoHi~=11L7Craq+ZxUTmUzs?Z=BP9tb{8VfxyQ;Aw=
zAPs{j(Qxw^Op|E_&7qTNA$3qEokQ#CV!Dj3q-*JObQ67@zD0M^JtT~-plj$ebR*pY
zPj=CL^bkEtzo%#EB}tS_lD`xxb&|SEy`_Otk~BifmL^HLQnBPP&Lk9c<uuO1yv8^i
z^IGHIFrQ(Z3%L_Y^DuWBZ^gXESciG7@ixq782=7=4YaGr+-bZW^BUtFnAaNb#C(Qv
zA>_5tZV~2A<6W577#Cw+YrGrt8OD1dp8@TbVD2>Dhk1>0Ddx4t`!SzkoI^yYoex-J
zTmV>Wya#ZG@c~?awQ)J;_aNu@5a;(W=eL6MdxY~^$$34>c|FE?t>(NQ=e*W%UjN{{
zp5VNm<h-8Zyw-7EPjg<+a$e7IUjO90)^lFZb6(4UMYVAi@>+|$o<UwOa9$fZuNOJ5
zO`O+DoYyOy*Jf_FS2@2eoZoAl-|L*;8=T)(&g)IiYa8eF7U%Ug=e3>ldWZAc!FlcE
zyx!%!c5z<sab6pc*UM<N2ISR<yx!-$_HbSwa9(>kuMat|k2tUWoY%*k*8$G!6VB^X
z&g&58^%=L@Vb1S!&hHD(?@P|_2<P_|=k+z`b&T`+hVwekd40=y?M7bvkk>)9+EL{7
z9q08u=k){Ub&~Ts#d-b6d7a_Be&W2&a$Y}kUcYc&=Q*znoYzIp>sQX}H_q!a=XHhi
zYT|ZtY5dq<^=AA`g2vAzYWz%;^E-jOP9v{#$m<fb8pPNMq?@o$d<^2#Xj)9C(rI)$
zt)?|}2AxIcQn>fgMf5I+R(Heu(oy;~Jx0Hw$LY891pN*o(+~6{Jw;E`AL$wT6U3>X
z={fp~ANxGNo3K}0MMu(1h<Qb{gqG4Oh<vqlCPcq^^j2C&Z=>_+-{~U|>t2Hh_y*ld
z-=qz68$`ah>2~@KZKOLOD!vPG@IAVlzVFu$-}8I3a{*@kg%EsG4JPj2_#$L2eh<LG
zT1eqiSKfl1n32526HrGX20I9m0;TrQE>emlW{)0hj!2I=*l(k#5P1V6ourp!$sida
z5}PH9<R>YTDp@7={R)Y3g6UWvQMz6lLM&3Elt>h)izgxUNxBXq{qxu2buA5syaxSb
z`UHIf#(auC1*>_MK1)Qpo<f8HjlB&s9;H7JC1gv;7SMr6;z%&Ge+t^Izotg7VLRxh
zhm}1EbF8E5V2<bLb1=vA6rvZb^nI9v@xh-faUDdR97Ub9=x7VH0v+kf#Z6cJcAxfp
zGVb5?SW50E%g6&{Ie8F&&vONNgsdcwl2!OyERVyT?H^#jC&-iJDYA|{O`ajolIO@j
z$$IiU*+5<(8_A1g6M2ceOkN?I$*W`wd5yeI-XL4ao1}qkBX5zn$#(J%X(T(yPVz3<
zMcyO3$@^pv`GD*tACi6KBeI`-Ob(Dw$U*WcIYd4qhso#U3-Tp7LcStL$=Bo<`Gy=P
z-;xvLJMumGft)0#*x&deXUI?FEcuz7BfpUI<N~=!ekGU4Z{#w$LYjyRoK6sL5VOTG
zVvaag94C&4`@}?Xl6a#yS-c7E5jVr_B2Ua03&cXP2yPWq;jU3CP7|k#4zUdG7!`2y
zxJ6to9uz+n4~d_NhsDp~cJZZnMEpuTDt;{<6TgAG#<$`L@jLN*@dxoFHHoLh)6^{f
zD4r3263>c1i|52&;4X4OyeR%EUJ`#3FN;^iCeZ}}K%gR}a3j&dJw>JlYNR*NY&r(-
zBRA1pnn%m%EpQ{bo!&w3r1#T@;a;+VzCd4uo5^PSD&0drpnK_ua2xrE?x!Eq1N0Mm
zkbVkxlh5d3`Z@iAeo2qeucSfJU}>N9k+fg>SUMnmA{~@Il@3XtNr$D+r7xr}r6bZ;
z(oyMa>6rA5bX@vYIw5^0eJ}kWos>>Vr==gIGty7eS?Oo#ob-!yUb-M%lzx>iNxw;#
zr7KdC<kI=+{N+SBNggIA%PDfIJX}tb)8!HJNI63uC1=W`<t+IIIa?kh=g4E_aq@V1
zf;>^4B;P1cmT!`$$T!Qma-N(o7eFe4G!;^*JWZZ1JLEFCT&|ES<y+(`xmtG0HFB*y
zL!K$ml4nDjBhQuR$+yaN@@?{b`R{VQe7k&ye5brXUMMe;?~)hGcgy$4_sUD;`{bqa
z{qi#T0eQLnp!|^hu)IQkL|!RBDzB0slUK`+%WLF+$ZO?i<>%yo%IoFl<qh%+@<#bZ
zd6WE-{IdLtyjgx#-Xgyyzb?NaZ<XJa8{}>BTk_lTcKIE-QQjf%l;4$i$?wU#<@e=1
z@(1!>`9pc1{E@t0{#ZUBe<B~0Ka~&3pUH>i&*d-VFXbchSMpK$Yx$V`jeK1GRz4wr
zCx0*hAfJ>^$*1KX<ume6@>%(!{HuIP{!P9tUy+++mw^}r`3d<+`6+pw{IvXx{Ih&c
z{zX17Uog!y&HDe?`wloMistR^*`3|JoxNpt(#{-+fJo+u9#KR@L_~7V9N~_f4<w1m
zi=YUIfJl~bAR;1?B`P8&^fe$VVnR%anIz$>es=D-BPbFCzW>YosOo!my1Tl%r>i<l
zPjGN>NN{LySa5jo{@{q<1HqBO2ZN)6{|Sy(hA2aoVajmjer1I6fHG2fP#L9+RvuEu
zC}Wj}l}D6u%A?A7Wr8wMnXb%GW-7Ck*~%PcuJV*JPnoYQP!=lb$|7a4^0cx<c}96w
zS*ARvELWaaRwyqhE0tBsW@U@ARe4EyS=pw%qHI@QSKd(GQg$kDEAJ@(Ro+$JQ{GoT
zP<AQ1l`oX9l&_U<l<$-ul%JGel;4!!l|Ph2%3<Y*a#T5{{HYvQPAaEDEW|@n$P@C0
z<d84)RcK%6>(KttH=%Ds--W&p{SZ13`Z07c^i$~P&@Z81L%)T75B(836gnI_5;__>
z7Wy-EJai&-GIT1Q#q)S6-V^VQm*ai${`f$ATzoKIi4Voc$A{x{#H;a<cr9L!H{#8B
zD?S=;$2;)}@j2sj#orL0JO0M_Jn?zs^Tpp3pFjTQ_yX}W;%COsik}@nCw^}HQ}OfS
z=f^LIUl^YrzbJk&^}Bgvv$2>Jy<eImQ4fl_&Zj)JJom5<JokF)un#>gJT2Kro;IGg
z>=RhLPd&Xoz1d!}R1dJvJd-?=*jJuuo@s0!+29%MYgn88ur}Yo+I$OZ^POk4XAS!v
zJ^ul31#d;pFlQ>sK{?1v%BrmLQkWGj?fb&FpMUEw=`YI<Vutj$;6uR~k`!DR+$=?d
zuLX}tr7=&Mj2Y5&SnoKNNH#r*Rb|y#6L;qcXK@&tRg!8*cT07Hj|bNT#l9)A%cusG
zy(T{7B6gHCVFB`B+OUoktG7FUFW$xTut97%*&`4AJ%((MhiuU#Hcj~tlfthlOF>^H
z`k}Ie=ts(HL_bm91pXn>t;$EBpAdaR`IP8e%4bC1R(=%sgiR4QY>BwxDB_*~9!K<*
zaFFP$VFgGIAS#du5F3aCBtal#KbJ`FULpIL-Fp82Z9D%R>nZHxh1$d`X%97jM}KF3
zs(%Ps7hx6eBzssJma0Bko$;`N&B*=<%NMhIoi5Pg4gDKicebT_l5E^*>z37WTx*st
z(~^<Rn?|-dtHryWJPYAh#JmdOQ`94`;;8FW{7D`~bMhu;!=IQ#-o!C#wN0p{wiWF%
z!!AlavfIRv8j6IpkRCEZX2=RfLw3jsC4_Q@a)oXP<qq8#$`i^P$``sRls|NHs6eP-
zs8FbIsK_}j>3_~`OT%&DU|6{zi@Nk|n;Om$R>P6AEbFVv4&^o2*Ei2;VLv1r`;qdA
z@~QG!hOG@-;VA6wkLR_xC(gFHVLR-E6E4c~X0yAY6PLsCsxSYI?XAltZqg7affr&1
zug4p)o3I92h_~ULSW%wBQ&<_^g?C|Pc{kpJ-NJkE!K^$V%BQgEd^(@S+VEBUZI&$c
zmHM+`Qkpc3jgan_9$;gn2c?JDBhpyuQ8rPUAWdRZu$uX#G*zPhUYae<X0tsZkH+SB
z43ELmJ(i~kTjVL`DZw^)N_ncYEwJbB!=8VDvDq%~Jn!4=dpROUxGf)&4{=96A|K%i
z@-g`s&*>wD@m#*KzDM~Dz6rj^c|PA1-!xv(H{Caj7xm5YE#W16OMNSOCEse_c3$1L
z!}ktv?Aztr#oPEk@_oYF`abo2#*@kNpWvN*r^xb;^e6c%@wNV2{kQQ=fx>|zd~2Xs
zpag$8P%2Q0zZysiB=H@A3V{mzwLq0X75;jlYM?5ABTy|+jlUVF5val63fvvIo9_(N
z4%Fsv2O0$$@pl4E15NpV11$nA_`89&fe!q=K$k!lzB`Tv<NTvwa<BvcIM^we%J&4j
z2K)2RgK5Du{sZ|9Gx!1W9X9hnf<Fh3@RN$9w3PfxYh|$1J~SuvrF4J%J@NNQFULO`
zKV8~}eUTE4IG15&y*2ObBCE3?Vm`sg^3nKL?EH3jM)RUPk(cLp@q73*x_=?&85UA3
z55mjv*GBiRjr7;2bV+1u+sg@ZPC1u+gPdEwQO+ahmGj9r$@%4*<pOd+xsY5~E+Q9|
zi^;|1M7e}qQZ6Nzmdo(>`1||=zKegzck_?<$NUq%hkwfV^3V9^{0sgi|BCP9U-SL^
z8~!c-j(^X8;0L@Ouh(<PbJ%mlbJTOp^QY&y=Y;2^=hUTOUgqUqvA?%H`D78&i_LQ3
zl#ODn1gl88se(_`-NTyVq!i($rQ)OtaW>HX^c>~jDm_QJc_Dg^T99_T@b2`q4B%;e
z7$3_Y;p6y3dSX`bEqp8A&R^wkV&>=q=Zh|Mwo1&_cyG^~DVpfc6bbM2R;iSfBvqGc
zk$=*ZypL|dF~PCHhlAsSj|RsFCj=)3(}RnGPY0I-p9wAv?h1Yw{3!Tw@RQ)4;Ag?l
zgI@%{41VSI;-~v?(MM<W(4t4p=ubsIdV0k2Blfmbl3HcTwaJxh5z$7Fs{%<@50bSY
z+4}sYY|Dbr1(yd`1YZcQ46X{U&L-<O!Eb}#1%C)02>uv682srkC5~B?to9^p8Djl?
zmfjwvxLfM#u3c4h%fguGNqyww_hC$o6j(Jenq>9GjtbUL84|ja?If#q1Amh4OQh14
zqR~#0l*Bldx&ozHS*pxDRQ~GBOSMyr$)t&Tlwt#^0rQhanz8_Cr3H;6T1%~2ko41u
zDdaPDV<GYu`>^<6^I&rprV;FLmV-tqlb9Nu9Gt;&(O6|Q%O6}D+{}__#PSoX68t52
zgmof&{1EFwmUki>OqO;j8%cI_6`MkK^CLEkYVT9FmTK@bwvMdf7i>M%<yY)Qs?V?4
z2CCC<*hZ??@7N})+aK6wvXDQrEo3EsVq3{l{=!}&Yk7jbOt#U-c9Oqfvt8sP<Yjxw
zFDSzHlP(l?kSukC{X+IKfxPLAc2Uu77yr}frE64ZvKr~fa93CtV^^8yf115y&1UGd
zT4rngpJp##n=O>tuRbl-H!v?0(`a7kvZO$RGlL5V-4fiv;(|vN5#!9&k$)On#44HP
zd3idsR{u#V8SzVIO7YKAk*FU`xEQ}k?54OFPlV!yNJfiIV<HU?#hjjlv8wE2_9gos
zr{POH$Tdp!!uKxh;5(@VACt8E`2qebCy!O~N<m4LEGd`R&mkpBWu=NzRjGzln_77@
zsg2Z8>MHf7QN&Pbq%=kv&k9Q#_I?zRO4FUy;JdVtlIgC#(qOvhVQG>yU79B?kyc1+
zrA^W{>2>KHX_vG|`cnE<Iw<`v9rG}cPmD7>c5F`rJ#Tw>5tK0pFAm;<mj`dnD}cA*
z6~Wu`O5p8yW$^a=R`6tA1-t{l4ZI_-3f_s|4&Iqp2k*jbfOqHjfcN5cW4e{2f_qoX
zHuxIZ5j^~7KoMNl10lhE3j*=r8v|kRO@SQXCju(?$v_1BR6rA)Mj$%)Z8>6f*p(M%
zqBRsHT8I}T+JYy-^DjZP4X5@;Wh_Os9WPC^JugEvnU^Knf!{*3BTpjQiI*eVnO74#
zbod=ayYV}TcIS5y?Zs;n?al8d+K1O7+LzZRI-TE3bSAGubcSp&iOOpdT_cN`#y<lR
zlc=QhWKcQ1L^lRxqMHIfq9+1=q9+3ZqNf6JOro;U*d=fqU&6%qf(!9yz+3aB;BEM`
z;BEOb@OJz;@MOLmyaRt8yggq5-jTlm-ifaS?;N;6aFQpt;3UzF;2Q&Zz&8c*f}aTF
z13wwK3H($bzu+X@&EU83+0gYIXn8KQ{1mi24_clN{Vsrh7eeFd(DEW^c`>y7w9s9^
zfObr1$AWgE(2fo5IM7Z4w38Fs$tARtgQ2$(JJH2^g9Vs)i`q-Qfl1O#q$gbTO=4GB
zZg+QCK5n5^L{XbIYRv&nMO{x7Va73T)bQT3l+ZGv6W(RbNGn%DA3|Fv^d(w5p&!u(
z2?K~WO6V_eO2KAhd1Ky`H|NcG6P_AuMwY5YY{f+yAPuJ{eTrwg=V{N1@bU18@X7Eg
z>Jw)LX9wp5=LVk&&I`^DE};H#Yw)Gu%fW5ISAyGvuLgI74~M0&C+rQ&VPDuE4g`+|
zj|Kk>9uJ-fo(!H+n8KCElu63t%4B7VGF5p(nWj9ctX9@2Yn64%dgVoBgR)WCq<pOG
zQT8gID_<)6l>N%L%J<3v<)HGj@@vQ+3WVZ9!H^OPh2lfuP>xX1P_a<)P-3V=sAQ;A
zsC1}IsBGw#P*SK|sC=kGsA8y6sB-AmP?gYap{k+VL)AiegsO+`42Qz;;c!?B>tQ2&
zBz!b{ESxi(D|`cKv;byY7-m^y8d=;!*1oIMoh*ERsXtluVbU-bkDcIQ%$?-GjEIU=
zjfm%Y&+|<4J?C4_bl)1^8fN+q`wlZp%oDJvm?vO)f_sBsv%+GwfR$3lke#onJWCe-
z4&@`V@U@jsluy{bu=90b=j+1G*Mps}4?EugcD^C(d?VQT#<25EVCS2{&Nov|l7(*`
zQpu_(!>SL1RUZ*H$*Mm{<y_BNTu6;xTn%24ddjGwAhgM#%{b^$gC282kNHvZ;wX6%
zN?so&Zv=m)X>7hl4$9&^4vE!buMw@ra%XM-XSU+=x5rr95zj8Qlv>g~u~h@A;mpx_
za9{B2GiNbR&tOt*SYmYtGAVL6Q>KjfO}y0VhEZ#q?A{ZSb7Ya*W^t#V;f&{0tZh*n
zu1}soL*7WVMQVwM>F$!uywFtz^=0wKO>FOln7^WaCH7v8kdUk5L@ckml}T#vbK;)(
zvh+*Ld#j%5If^%iqiTM&u$rjeq9&>3)beTtwW4~fdWTwFy;H5B-lf)5?^bK6_o#K$
zhH6W-Em9rirj&#-7@28>&Y2d)L#*1_;^v{a30dNDwdw`kRs4**BsLf`bz*d3;l5`G
zQ{^~0jxn{J(14n(b|THBs9l*)?XLD<LA96KhotSN_G3BJ0qT8BRfniUn5hm^?`M|!
zfI5;n>L_&-%c+i5$FN-Lqv}+4qdHw(zzVDBq|dTquMU;AHsw)AtwU%7wIM5_HdY(6
zVrmPuH7l;RC2f^b$Eo93X-HcPRMdip4W&z*rzOf{Uq@1l)8wufsU^Cvai;WMHk_^%
zOq>WJPDV($&g2&-!-^ARx%)H-$s?}hLS_z`Wyl-{nH9(!hRiu2vjLe+$ZSLA1jw9I
zeMEhP<<69RJ|usJl~JE1`72~;2et9UjbP&JpJmyexPMEQi*3QRp~G6}|0Gr~i{uxZ
zUaWuhpw}0F)nMY(c>A)Y8}mPD>_h%(NtWMD_slyRWcKr<bx4zdb7^W)xCLv+8eJB7
z&dlYsZ23vL+~<+)+){~M9Ca>}mQKraEj%6fUgkD-Z<e-@KTBIUpT6%sZ!Mj>1>Jj|
z7IZy6-}hejC-L4aPj~{Jql{<j^0eN2uke$5{@N91C=F)+uD^6zu4bSk;ZclXBiVQ+
zPD%fFJ&M!PG&oD9*zU1wOD5rYt!CGczj#{q48KeGjn{|Yb*A)dN%~FKk@RP_9+{r_
z5#;x-WLw-`J=b+u3a{IWuK$`4XGvVYH6i9faGr-M-px5Z(;!Y7_NtFEZ+uyjSolD(
zwUPw*AfDKK0?=3tRjo@UY^c@)tuN?b#u4YX85Bp%WQbTXUO&dON<vyJ!%|sK)}L&g
zuyxo4%x1f%d8}p|V&`|T_u0qnbGDxyV85~>>?HT{AXmA?#ha&vcp@*$EApzm2CvN<
z@MgRX@5sCI-aL&D<s<nRKAulj^OMy1)tialtQH_zKrKkLpjwD%A+<2k!fFwsMbx51
zi;_MiwU}C*XmK@>XrfwzXbH6>(UNK@qNUW*L`$n>h?Y^Q&eXD`XGzSc5KU6c5iO^d
zCt6-5UrEfc5Ur?IB3enUOti9kE74okDnzTOw-LQftxB}2dOOkE)oMhmsdo^)LnSX&
z=$NR`vn1wwh~A~vBwACwo9NwClaiSKA$kwB9Z9WCZAYRO)BxkthN!*9L>sFuh_+B$
z5^brrBHD`Dl%%$%HYHKZ8b@?omiL)sR!ls}v30+H);3SKJMli7kDiP+Op^a2Xgpa`
z9%2tt4Nc{<c{*RlSMyDLJKxE7@x6RMKgbX9lafygOO}*dDj+3FNm3Q5hEzvtauM(U
z7Vso`k~~#BH9U1ZO+0NpojpB0X`bPp(Vp?1sh-)Mbk8!+YR@LmcF#`FF3(=ie$PSA
zA<s##&l~ny-rU{--b8Pbw~Duhw~n`ow~e>6x2HGFJKQ_kJKj6hJKLM?UFKcw-Q?Zw
z-Ra%s-Rs@&J?K5;Jt_O-ux!b><pOe|oFrF~YshuvCUP6Ov)ofolZVTr<?-@Vc{XXs
zbbA(|Uk?2ifqsiZzr~^7MAC0NRvP_IS@b*Q(eG47zf%SM&h6-Ts-fSx3;j+_^gH*U
z-?<n4P93VDsjNQwomS{~$mjIhRL=aw^LYz-6Nwk|miCq>p5(3Utwy{mm7d1u-df&z
z-X_EwiFcfdxAAuLb|s!lI_XcmuXm7lIPsz0k=`-HM|;P4ClQ}Wnwm*`x_7QOo%jOp
z67O>2%e*VS>xr)={cR)ul6Qx9C-FDE?|OF=-{sxo{gU|Sq}2n&zxV#^Jw*I>?=hJX
zKPh|VAoIup(zQWclWjRS@mz8~xe)OJaxu9y@sd;nm5EoBtI9QqSC?za)I(8?G?H5o
zZ$|afk$AG4D)%JbUG6InBAzA>mB}v1BdE6M*^nQWC(2WaPnM_4bBWKE7syM9FP4|d
zD~Yd=*UFoSZ;)S-cM#t$zbU^<{2h6hyodP5^5^n?;``+9<)4Wklz*3x5kDfI^m&=b
zC;0-tF!7L2^U<i#XZdpZ@)6JDE8r_eyoj%)FNt_rUqxS4;#GXreYJ?!^wse-BHqB)
z%-4o^D_^oNm3U`gcVA!Py?trEp~MIKM)*b(ALV=4H<9>w-(=r(;?sPyeG7=s^DXu*
zBfiwP!nc<AYTpLmOT@SMw)@^B{<`lS-!9_s`#$!4PJFL#pYMC(-}(;vekcB`?}+at
z@#B8UA7CE8&mZz@#8toL&qX}JpT}Q-cz%Boe@Wtr{<8jx#LN4u_^T7I=CA3mL%g=X
zfxj8?CjM6bWa91oo&DX3clG!7rxEY(AM77Ne7Jv<|6$@|{Nw$TiBIxR^Uo$e(?8F@
zn0UH>sec9W<^I+F4aC>`xA?ac-{yba{|@n;{`dVK6W{IM>)%KGOaHh2gTxPrx37pF
z@*fXK%oAV%pIFNd1OsZoB5ni{#ENPlcOZYD2=PLJ#6Vf%r32*yRfty(R1453F;F8=
zJJ5i5y+D&dE8;Bz?E;;NcMNn5^d{aj&_6Jk_@Kb>z$oG)17iZ?iH{3R3QQwDH83+U
zkNDg`dSEH>C4uFE)x=i@)(5r_-xSyuc%Ar;z|O$?#NQ3<4(uhqC-7z9TjKiz2Litm
z|2c3daGdzDI2Pw)o;Yt@Fis^Njx*vCh}&_w<LLR1%NJKDj-LOxVsWM8%2S_2J+`3n
zWkJgbdrEzHeu03N5w?|(n}OU6qyUftKnegU2&5p8f<OuZDFmbtkitL;11Suo2#_K`
ziU27Jq$rT0K#Bn=2Ba8};y{W6DGnqNNFtC#ASHm508#=-NgySGlmt==NGTwtfRqMO
z8c1m%Wq_0cQU*v_AZ3A+1#%0JTY%gGBne0okR%}GfRqDL4oG<*<$;t3QUOQ>AQgaA
z1X2-5MIe=cR02{7NM#_Efm8-^E09}(+zO-$kSai`0J#mwZ9r}VQWZ#5AXS0f4&-(q
zw*#pLq#BTFK<)r?2ar2}R0mQWNOd500=W~&oj_^;sR5)0kh_4~1>`OuHG$LwQWMDC
zK<)-|H;`IDY5}PQ<Q^dR0J#T9Z6LLQ)CN)qNF5+`fHVNo07wHM4S_TS(hx{vAdP`E
z2GRmZ3m`3kv;@);NJ}8CfV2YA3P@`pt%0-#(iTWtAZ>xP1JVviJ0QtGl7S=x=>Vhy
zkPbjP0_g~(Balu&IsxefBn3zckQ5-PKvIFE0_g&z3y>~Ax&rA6q$`l_K)M6z4x|T=
z9zc2k=>?=0kX}G~1L+N<H;_I+`T*$zq#uxeK>7h00Av7=0YK7#qyb3-G7!i>AOnF6
z0x}55ARzYvxev&FK!yMr0%Qn~VL*lf83trHkl{dv1Gyi_{Xp&q@&J$rfII+XB#@Cn
zMgkcHWE7B5Kt=-@4P-Qshk!f;<RKtqfQ$h$2FN%d<A96<@+go;fjkOiJdp7~#sirE
zWCD;0Kqdm22xKCV$ACNr<S`(VfJ_213CQC>9tZL`kjX$M1DOnD3Xmy4rU01=WGaxU
zK&Atk4rDrz89-(LnE_-bkeNVc0+|J57LZv$W&@cGWHyjFK;{6M17t3cxj^Ouc?!r=
zK%N3J56C<q^MK3;G9So%APayj0I~o`I*@cA=|C0%Sp;Meki|e216d5@X&_Gnc^b$P
zAWMKO0rCuxXMj8dWGRrPK$Ze|7Ra+eo&~ZD$TA?yfIJ7}IUvsgSq@}5kmW$02l70S
z=YgyMvI58oATI!U0mutLRsvZGWF?SQKvn@+1!Ogl)j(DQSp#GZkTpQo0$B@WEs%9U
z)&W@uWId4eK-L3!5y*=`UIelM$Oa%AfNTV^5y(a$n}BQrvI)p$Ae(_~2C@an79d-I
zYz49vh@j&9(>yGmm1JdEc~%*3P}gL&Sv}T>HDj$<JF!cIM)q}RyeCG?V&+85EQ`}w
z#5X*|+Zf`sesMmU*l!_D<d3~!E!G`kYge@|X?EaVqW8LU1Q_{Kilv#wl38cgo%O{#
z+9TO$_Ancdd6}7PE?dABv!!eWTg}$HU*@vZb~G04pmtO{(P%VP?J7p2G#2emBhfT<
zpn4yTLWisOi}9x_R{qE`Aaw~jNXSLP+u*U4L9yZ?zPKX3Y(PC1<t@IpApTEf;@hX<
zo2TMirxNCgIR1;bfym3ptP!;iG509?3mQAm0G)|hk68%MMtBawa}j<D;duzpM>rjH
z5$Iyjr$Lv3K8rh-A^be(3eXooSAwnrU5z`}AiNfI9q4+{jm)DqB~If+wHfivK(~lE
zEMteFn0t{(a}<MGh!(>{Tc()QektBYgg1$Bw%L{x%<?S|H7#ZWPn}{JYj5JzoKaa;
zV4wY$S72+SOuf}*t}OFVn<Lycu4n(%6-=+1pL|rNHYES;MztmRT6r*Yb<;T|T|jM4
ztU8T!=ftjMS<~rh^-?{HE8&`#wmhRz8+xA%Nj=oBWy~@L(L*XM`+kC~@taV8=%HGv
zhdwlx!ucimr>Qriep~E7PGAktKVR<j#V!k(<-*knz5nITA+|FwpPO>_8W4X?&#VV=
zf|mu0^LH|wKb4A93!*k`Sgngsr!r|fruPKczKc&OAC*ZW?G`yh16egC{#x)4@1O79
zU)3#fMcC#GmGgYLU!K%5WUH2`#mev+E>*hAm0pH?)v48GwEimC6>_N(UcMAFWXyv;
z)X35rik-6`t4A6U&(G=Bdhz>CvZi}>{<mMD{LfBTJO_o4YCiWJFz7~(!<~14-UTXr
ziqjrQ4|lz134GLNgy)IWYB8Z>aVlPCx3_+d{nd`-SYLOKTZTADEWW`S=k9zyz3(};
z=eYyX9PmhmKiXYbFtT5>)H&*WvQdlGwd93)U~R<HB`i*z3y|Wk^YfF>OIA~TT3w<(
zLq1@voFm<Gwz~r5{JRng$!59bY~hx(<|UN#%o3hX|LT`B<+9di$~9Y`^RIAy&c8;=
z+5NKCXZLHiJ{Mo%`doaClr!xLmox1eDd&nST+S8ONI6q4>+_j<%|4&$SGYdYv13%D
zOME@II%Dv!{`q@e;q%0(<x1oeGf3)->IQYAm~CR>oqpj<)^Po~<yR!v*bJ7?o7in6
zzL6??!+;23zfmi9kC9EIiFes_y558|&$Fw)6XxRHwyTPk(ZOw11JpEXQ?uPRwc`J~
z(iXpf(pt=eS+i-^P+2qHU#x%K%3u6Cmp`Wey4Sh>>t5&juXmm6|N52xPSA$et^C!m
zbNOprfc#>;&11K-+uP#%<eo^^$gqf5sU)w)?qCalO^S4h^uXMDP#}>t&dSIjvyVBz
zSZAy;?-L%7xFd33WK85?W1#V%vBp?uRucZ0Uz|Y6Bmap!3N7Vg3VE63aUx?aR*yAd
zomp3$mrXvc7SU|Rv;-|D3upzj0`RNE3EL9h&y?^6n(&c3V@6GUUqh^~`rQ@WQS4zh
z5o@R8n2gob>1-}br@Q82-85YzUrdW?ZHXpmO%ZO7a5IEE63wYKN4O2}76`XPxFy0J
zaF2+qA(oE&4cuws9!qOQv;gvoXvv7%2KTfD(hhgFM+)Ls8);g|T}Rv~%eE$}HFNXU
zL9JMQdFqR=C5Za+)be!q#NNhEWT(GDBI-5v-3%7#8yP}1G>YoLaEdsk@g{>5c_6`t
zhn$43wi_21k4GL5brtz0a*8qMPUl|cIBT3WEFV1l@>o|9Ps63Bmc2YL{7p)pNb5+u
zNPCp1Vzv@pXiOo;&d7d}qq0+-<XG*jc1u;6uB@fH)D*qc{>4=mUh?HhGrP7{{%!5I
ziL`~TN@AadaY6CUowsPCT$9|?8e~ar)!(EhXZwx%4)?dHv(j0K6N;orvL<KgVe{Y;
zX|KKjon(wc^10WA#S^PiH$>J()<xDwUW{yrY>aG*Y>sS+Y>m7Wc{#Ez@=9cT<kiTI
z$ZL_;BX2lmoU+a>PLfm3DeqKpDms;rswfddX@e+{;ilR*(l63KG9Z!`85kKv{pH}u
z5W4F>k<pQdsQhCi4@Vw}jEg)<af&*{oZ?QRQ^G0flybycr9?8lL9&*iJd9W`U~D!v
z8shCUkMXSWlJPQ=_%`;L)=TTH_0jrj{j~nt04+@$s14HAYU{N1+Kbu-ZKJkH+pKNT
zwrVeFFKgShSG4WgtJ)6jHSKln4ed?cqkDB(_vwB;pvUP!UC~2&ydKtb=&BykHC@*Y
zJ->dlUO+FX7t#ysMf9S2F}=8+sF%=7>ZSD3`ki_W{Vu(xez#srzelgF->cWr>+1FN
z`g#Msq25SutT)jI>G$b_^&$FDeV9I6zh57rKcJ7)r|47lC-iChllpXhk-k`eT3@2S
ztZ&m_(YNcb>O1t;^w;(8^zZc_^aJ{j`a%6C{b&6b{Z~UWJcieh4WDs`QQf%HsA1e?
z)HLokY8m$!wT*j?I!0Zio>AXuU^Fxu8I6r5Mhm02(Z}d(^fUS!1B^7XS)+{q7^97O
z#(ZOevCv3278#3;r;R0K%hr;eTW@SJwi?^${}yAH@u9KX_{jL!_{7*_d}{19J~KWy
zzA(NtzB2Y1UmN?)1T&|Z%e=wNZQf|+G4q=F%$v;o=FMgSv!GeXENm7ri<u?Nl4d!x
zyz`2)-Fek{&3ViDuk(TP5!LLCS|_b1S;G4?YCqar+Fo{}Zt6F&QhFJ^I;*NT)!VZM
z`h)ry)>@yT&t@I;XY>^;MSnwopY_sz(+{)z48M`Uh8s<drfibY(rC{fC%ZhDO*bAg
zCa~GYGsZHu$avA%z@DKtw3)?P&obi`;{&$b_{KQQwwguFqU>F>xS7b_GfSDJ*$2)B
zXA}F-+2QP9A3Lu*ud`2_oz70S$9dOzmwoE&a(1!3)B-EA>Dqj4fwoXf*A{7uwWqZu
z+B4cx?OAP^_MEm{dtO_iy`ZhsR%xrXHQF!Qui9_g@7f>QA?>hsL_4Y-)Be<sYbUgm
z+9{psT$l77dQZKV-dpdZ_tpF9{q+HQnm$mUpik5v(<kYV>y!2Q`T~8Sp02;BZ_qdD
zoAk~47JaM!lKz?gx&DRzrT&$^PybrquYaR|tDn$M>Zc55aHE7#(kNw=Hp&=fja!T)
zqnuIRs9;nyDjAiHTa7BlZAMk&cB7in+~{I-HM$wyjUGl%qnB~NF~WGj7->9dOgCm2
zGmTlsY-5fw*Lcc!!B}amGFF>$X3$j3kQr}=%^ap`Moi7rO~W)z%Z!?~>6o{eNzO~o
z%g#3EP3IlweMfxP%0!Jb)VPUSE{Iw#jan{`TCR**u8vx+gIaEgT24VNr=pg7p_coh
zmWQG?N1z5DLk&KTx|@o+djfSg4R!aV@Yg(e`^|X4t;g}&1Z|@Bm^Mj!T$`*-(WYuo
zXw$SOwdvXnZKgI$o2|{!=4wxA^R&;j&$TbKFSW0<ecIRBe(f9WTkSjTd+i79fcB$y
zQ2R;ySx?qG=pFS=dS^XFPu08VUG;8ycYUn>u>OcXPJdJ%ug}rv>QCwO^cVD%`YL_3
zzD8fGuhZA-ALzUE5B1&pNBYP5C;A@!Q+=;~L_ew@)Bn_u8##?!#tlYp<3=Nok=Mv)
z++^f8ZZ--S1&u;RVWWsq)F@^YHxi9zMzYbt=xB5@IvXiQsxibEY78@m8xxJkj7i4h
z#$;oPG1Yj&m}Wd@EH{T5D~uz?QRA5Lr*YgkVVpEhnat#-WO_`mDVsjiZwAaVW?5&m
zv&Gr!yy3j<yytv)P1IwSQ~#*UUC0K;&ipF?Ybef)FKad+yWPudNVK;}KDO2;dYnno
zS!NU9O@TK9enQ~xy8AfnTT~I&HJ=uwa)z`VOeWt}V{zo?noJ=-HG#!zH)wfTM7v4L
z&n)=!wpLs##T>1Sb_>g`mD9?zyjmr#GP_BuqTR-B*6z}3vVz(@T5VQXtE1IrMYRUx
zBNum$ILBEP=VXG+um-R7%`8_;COgybS#yrxV{bIaP8Sn<COO&1L5L?&Ye;2`p6y=D
z2Olb579VPzxP$KPLnZ8|4Z`nUk*e9#?1jH3vDog-*lvaOS4|_5mWncGl}_wpn2fPd
z#+e$|l6)B_U5XZ2EZZ-lHid7Po8@N`PV$k&NijA_ul2QGWRlt4-h}XGgf}3(5#cQe
zZxvydai(x@w>HI>40DiOrJ5&O+JqTo*VnKnWZBoTreq1XvSwu6_p`QS_e!&oWSJ|l
zht107UF=b_j@g_&X{J!B3(fiFGwhk@<I(ACrM=#MgKe;Xa&Bfj(Q7{Aw#VA8Pc8D@
zKvbOFCq`^dJ<afqyTRi70g+ZTX6{O(=3bHBV#FO85m^{Xw_Dk*F)r$Z6rVfm?c|N_
zujD;v)@1<-7uTw?JX9YYSy|@@>Ais)Ga<9>Z$eE(G^DR}%G6MTtD&=h7po@|(Z)0G
zxO&fgC()znmL8@0OVD#NNxwnQ%e;D7J&DEXmGmksq*v9eF;%ZlK9WuzXia92=UI<M
z$?I&ya+1&4gykj==M{FN@v5<d<uTqc-edX5o7=^T3V)6jBX4dWOC%5HHC7HIKZ~wO
zc#8gSY9M<H+MKP0^g62ro&CGeU@pvwP0Dglto>dsJ&N9EEc_bb)d-(v8hJCqmzhg`
zjPP59*D8G0XUSU?zUnG%O%@*^<{_N+{bHV9hM#bXJOtq#2;U&X2UN-X6P};&`^aAq
zzMr|<++*%FKQq5HzcTlk`^|67@67MbAI+c5U(Dak-_1YFL*`NQgn5dZpvUrBvgNnp
zte~Y>VJl*3mSLHeWksz7E4P)$%4_AfZng?og{&f0QLC6$!YXZ*v2L-Fta4U)*FTAQ
zo9~gY`JuDh+2efb>~%hKK6k!wzI48F_F-N^^u4+9-ofPm)z>v&U$M7D#Jdt>@V%I;
zXWtFXT8eqka>N7h<7rGro_Pt^50l7moaB0rS5H!}*3wq(dUk{JNXc=^mN?gC^i|d8
z`SlokXDGu*-Ex&=l-LcfFEx`!GzLjIkF3lBJ)I@!i}fY!1|#06M)u`yqXqd`$>d+B
zlK+&-(yUX_No<fU**+e!1Gd5=cDx<tCe=!WM{V7<xMMr^4g3cCMmrDBXVb;=+lB4o
z{ARm^U5Xd6%h+Xkal4#do|mvI+Ld@IyNZ1qFJo7;@8GxCciJ_0Is0zAIj@l5O9=8>
z384gCoZg@5M~%74n$tz;855;vvM4=^6QyU0C_Rf8rDqXQdS;2zGh39NIimC|w<tZ!
zD@xC95~XK1i_)`#qV%k=C_O7GO3#Xm(z7a}^pvY;H?7>hqN>|^Oik5v&C+sexwL%R
z&01+KNvoh$)Na+PYIke3w0pIBT79j9*3l8)PYRI_-$m=Hb=P`mJu}DAG>R5;ym}e(
zEEstf`&oYbCGv`Ez|_5kQ=HAWE*c=XLx2DQf;)uZ9^BnML4!L44;I{Ahv4pR6WrZx
zfZ*<f4Ks)D`|WejzW4qEXIHK2UcI`fW~Sd>Z?!zVp5W3j-wI3X8Uxt3Zaiz<==_ZH
z8O&?{(P>=)ph)=OEan~KliMP$*-`b=*waa64abyjFH+LGu$5p-c(1F90SJlD+6OzV
zZ!m6(PX~4P`6`leb)u*7WPc~lK6qe(dKc|tS{e(QCk$5F&el6)a+W5?)>b1ts2r`*
zniX!qU{()2m1gE;f*&#+^+p+<^%bivH<KRj9Rey%7xlK+Y#!(xv={rG`<;V6d=z{X
zm${QNlS7?4L5X>nB6_PP3sJLgH<Z*5K3dDECvvin=;#kiscR9=#<S3b#Z!p|f^6H(
z;%$gBD3<yS>=JdS#;E*GF)PwO3k!2dORM}mSaZ6tOFZK2R^-CAEPS?kF}oR@PfOu+
z;6DF!&T(vJSw+8Zik!~RVUT%oyI#7|Z)d|(Fhe9~hUGq29po%GGCnV%XGxltm;(^=
zFdT1}I^-pGopCR<U>R1V1}~QVY8tSV<;ag2I$gxSB+TWFeNV5HYLOe}`-UTE%x>?Z
z0kX>(5OXuunp^29!vw-8lOi|tjZ>~%(AuwaUTa1l4{HD)WD6Um@N0N`=W?0-;^KK`
z+!rys$uVhj&8Cg6&v4CbX>Ujuj(HA^{rr+g6rGY@6*5>qu9i4u=HAe5AY7TN&0f*6
zFm!Bt*YIS}SBbkQYn#ly>OD+i7SlxDJZOMlIaE1RHM025w)`%Hdn41C+&<?wb>(h2
zA<3H7W8_1QG>_L^Z~H@cEI_?fTE*X;q@(nG$F7vkW4yk#(9}X{%Sx<ps4<5|%t~Fu
zP}LgjpvyQIbh1)#0$Z4C;vXH(83+QRu?t9@6yMDtg?kAc&kbt$sR5<+eZ_r(y!xNs
zY;bC1_4%%9tojnZ>w3Sip>EGO_M3H1`?FT%OZ*VS6H1ud!}|`c!+0&q7bU9}^p`rD
zOZxLd<7*TJN?~%VvO&2WniFY1%MT~Y`q5U_^R|0m@71REYI_O?XzC$hRoADKY69R)
z1~MOn?qP#`-&1?0Z4t1^Qex>cY5m)65@Np_;tJB&d5)WbXQ|1kl(2@#3td;Iv08w_
zW*M*mSOF{n#<@qtZE#2INISgFMWz_S3Bo1^KQS5DX^Gu}>zbXe*DFvgMO_(=cQFqn
z=(OEt3;;7$XmSIBRt+^`8MJgsOIjg9fu@!mgt+RQm@cHdsD2@LK9l<v)(V2vJ)eI}
zH5+^vT`)R37`wIWZ_%Q8D8hi2e6esP67IRZ74VsChut-t6OlYmL*lu>36H2=^ngqg
zRr>&Ya#QEO{O0_6gG4f)XMafS25Jp14C+gaA1Wm8P!5(FU08T+JdgFl6G~vz-3u^y
zt5&rwirZ34lW;++9C?2s>x>c#Vkoqq_+AQ@s`w;6RpA%br0dj<K>~Bj;w=mYsv@;%
zE9$kDY#f@JS6iVyC`-uc*20eVji4s5K2YjFl1M5|W=XO|(o+&fx^Xtz6u7JI^@jSy
zFhK;ju3kL%w{G3clLjzB+P_f6prT9856UiZ$GXd&YDs%X{v_*>B@zgE8QeW#`F1w4
z<Q3sg>3G1rC<D`nWfmQ69*WinKB+vZ*tIU>{yAS#d7mx(MMM>!Co{L`+>ZEB#M%z=
zQM6zsD*Yv3W!couY;AbVZqhgy_LR#1=R-fJnRmrt#b=UvvO-ZP>TzmQnsaSsv+;9d
zE%wwEm*Z&VS_^c_X3yJ^>}I=&UDzxDL65KAa+&lCxySha!9!Hen+{mL`zb`Uf*{WJ
z#-^P!%sKg*<X9r<E^vH)=r~DF?YJ)2bdNzeOpAa+&o8nghMT5l-)}JllDY9voF-Wy
zcDy$5UihZtw*@CRglBQyv;ospTa5ESV=5CT2X|xKTL7R6dwSR`zM4cV>iMRlOX!nJ
zL3{I_ACu%N{bXFJGXAmskw>BPV+ESYM~z=F_3STpF{IqYg_(+GMQUMMYL46!n&mC4
zYQp+IH=?|419I0@6m&U@eW*dQZWkj~4xA=tp_LkHF|?~br@~w$g5LmNJ^9q=N6Q5#
za`sP^OG@VOH@jPLHopvu&fj5ziuiCnV-wz5AbG)~YHso#@_vpI3hEr6ahyrg4KmgP
zrtI~O>Nr&T?k$kcgmX|xNAqT2mUcc)gzk%Lj~kk^nGO^Hr30wFmNd!~dh64GAua=h
znWor(nps>-a=Zpw#~04BWDR<w+EB@Fji$wjDh=-=pyEXo(J3e27+yjYnEdQ8=)v#p
zV4`}^=#m1G+}Jn5j_*F77ne-_nM;`h*<M)4y<Tg4$9ym?stvL}YBVRv1}QsgU%>;S
zNc4R7@7b6r5-+2>R8~A1GX%$%#_uPv^I1j<a!WtNL?IPi%{Xz%XvRqA>(7U0&M+`;
z{rZ0X9rV5XP-zA-lU0D2f0ut(fLRbzFj2soUsYhAZ(nehe^xLu6FZ|kll(pHd))V_
z?||={-+|v@hd;ls9vy_LjH~BX%o#@}!l+J%(anjX4k->d>m#3V>jT_tjc3N+n?{@G
zjF9?A-f`t}YS-cp;?}bld>U2c4a?|T!E+65OJ(J5NjF$Q7Z0;bdF*yititu)HA$os
z_NB1a*f&9sxqd0shzVeB9KlW$DS%kbmh}bTdhY=fEzvJGLzN#nW^E+=v$@vN0XVCB
z^m4!vJp9ZQ-@>(bj9;G4s0L8U6vSp-GT%`FpIzmm$YaQpND>^Ilx)NcGI@)%C)Xwg
z)k!%<(^ey#Ym*h54{PVI@>kVUOLA47OjwOuniwWm8T*wl76U}rSeRn4&PvW`dkq4s
z%rgkRUG`s0OUxou#oa+lC(`8B6jj(UjL6>+(!&PNc`RM=(=lw%=FpE3Gfdbki7er|
z3XKy7zWMWpKW@C$J;{IXP895^xngI|W7;%fY02qP^Z1h=un<UafxrwRs!)8H<hU@P
zkHWs{wk7cHWs+p9$@W$zR1uLRC#0*Gj(=Jmv^1Mtjy_bh?B$UxYb4d{6-^KD-^sq2
z`pY#otH(upQ5_gA{J5N;BBJ|>&v(;y0~32Y%21zUPi*YVq{BgeNpB*L2k)z-BR~i^
ze}+v^zs`E!Tf*SEKF77V=rZlY+{U3Rsb;jg{2Vtr>C$Hr+Hw`|_MxMZ8KNX*Q}vbx
zu9dWl>L+?6O*OUJ`W2N6izK#Hclk|$(pOoP6N`i=m?x~Z^f8B<4I;H3dKCH{RdJQV
zizQsWu<@t$r(S`tWR3py{tf;uSbAYq)Qf5->Fz<f*}B+jsbmG@`O}Ced48!~gBne3
zx8usa*~e--Z&%I{HJ^_(@1rJ4*xMkcSUcJkk?vVq6Xo^`O~(dGmBs0Et@DW{HWec=
zGyO-4V`X<91Dnpbk`YY_L8k5@w{`KkL8n({DpusYVB`!=sfy?Yk2Tk5)`1O7rwg`G
z#`h;OGa7_q6neyd=A^D^TDi0ufX0k2DsSp$liM$+Z}v5?O-1gkqNDo5lceG#<IH2_
z`caLTNK@?R7bT)sKN*h&U+I5~USgs$wuoMJ7$~h`lD2OF#76MZ{oR$$#?zeI(_`$n
z{>c}ETM}_YJ3=$)6S%C4dD2S)sm#8tjTA$Vc;A=u&bBEz^0Hap>b$13?=#rZ|4{z2
zm{|;0Ruu_PGwdz5Y><u~8qFabs<(KMaT-kr@{Yl;t185^e$X|ZdPL1-Oqg58MrKx6
zW|nlOuqhG)c3q-wkPX|Y{O|oIwF!HRq_TaGnTqO!-*B<ogkMkYEA1uixZtPgN2Qj@
zlRwm!@#to%<1%kK@Z3M)b>-;qd218hpeR*2EMhE1=2j$~svY<od^FgHY=0PBb0T71
zx?2a=FP+PzZMStk;61?Tic71IN~?+;F0_6|H0A5UZaCDi9|I<uQdv%7>8`NCe*k1U
z?>NK&hl4E1wEOfcrrwf@2H6}NOgHw)(RWwNg7msXQ_GB@yfXdrKTcy3mc4(RDkUsu
zwss^%LVBM$=3YKD4Qd5&Zu*@NbAp5$CcG|a1)U;&tAl3bXWD15GF&%JB!T!M*&B<j
z1-huid#TRYZl<fIaqvt1I%70u`C7aUL{mSQZ#Awu9=zY(SflFeoe@^WENVyj`EgT@
zl{z^p4tbo~kMnq#wfD)i(W+H1=u%BCP1g1UC{+;V-?GN)(%NSam#W~*%OZ6FBG~&a
zRA_h5onb6F(McJ!J2ITu;7r0l9lfUZ5|vdnwWhnA9EE0q#r4si{H?jL=*HHoeA$_Y
zMLzka)FhjOZ?a6?5(Y85EJ3-$W7kQiZ5*EN`ioIYMujse7UT7P%8kRJ=Ot~^If9cB
zZ}%#*IlI54kxr$_C@hG6)Eg)(dz7^zFHgJHw8XZq<FPew4)0R<Ryl%UKZa4I;KVR5
z1<52{O(oX1YVI%JAxU#|ZR4Y40*fSkcTUXekPq0SH~x98A}>3v$V<t&5i;&(&~eo4
zF=u~P%&hM`_{^#Cdx3p<VU1Wo%D_~S$1+0X=7V2LI-sYUM*D;C57gVOqUqo?X>4OU
z124-0Ars@K>$i=>t3vi|&4WM2)0M&7MG7oS`YndoCJQd8FcOQOw<Lu?)Y*fuTf~ok
zl*2~4LUP_R!crGS_X`vY6jR!wH`OjLZ<_$_awb)dvz{kDckFkLcRNVHKaYQ+KX-<F
z_H|zvjnA7{H2zdf;%Zvqs|RlFUv!^b-GtxVy%sV_QU&{+9-qzR7FD(O*V~PO75)6~
zEGOCPF$xi_qHeDFpTcTtlAvO<f+v2HGu7SQk!Qz(XH)2>$RV9tpI_=;E~_KoYq5O<
zFRX>;8tprNbmb^GcBi>%iEnFle&%Lz1#hfw{x)I_baeezF+$~l+5bXbF>=!sdP~ES
zf0c*4BZjckL;8tavHyKN&0xI6r(Y~SaxeMAK$~K~OP{E3@qnTxavgQnU^>ExqcCR|
z0#O2}@9BrUW4=hnh~6!}pvu0C$G*=l%y0<#_s-R-<m?rVJ^7LD_}=^Uu{JnY{)luS
zW5i?D=hy5x?wT>g*B|djp34Rref`^+GbX@)j@FZ6HMIC0^WD^Cm8li?)^1Fc><-bP
zM^SgKTZdRc#3M|NgdkzC=G{=37KL;HgnArj$JcU}55Or?nOSRSx<KQxIxU)f!8>oq
zR`=O1nX8=Rg=+S}=x{{X0^aHuq=3uR5ew4OAMQ3F8cFPPj{Unt-#&6~y>sO+7Dw18
z%(~l#Yr$wpuGNZFG;MaZhj-KAuvSC-I!={Ry~e3~H0^s-wM86eEL%B*-U{|qDRFGM
z<pgh&5r>gg0hv-yL(c^v{J7NWq9hh^2dp;IwjzFm4w;&Kj{}o<k2quc)tn0(PZz>7
z@(!ETyZ2E8M=C^x+h$7<znsA$DlWo@6&2qi_GZcF$O{ZZD-E9wpR<JkCQT-FxvyAX
zZ|pAQq`SH&-Fi~|Thv|j@tK3#pCTpz6_GLYCv=ulU@36;-Ak!|a_DW+lN_PrE|*Jv
zty(WbkIVas=zT@*#2EA9h)339Qi*6v^QsHpbF1R34|mzA=^B<;lbj<KSlnTW^h=8l
zV-6wb*IztM&-BF&^4bsFtFPLD<V~4=!nZ2<^{L9&;E(+DUqh>Yfx;n3b<$Y~A^`72
z$g}fIuT+NK2jyR5E^HqjD~UaMT`ve7mG)_sijsc$PYg$JaR9h3sZt;`+7zXQ8O%6S
z#A7iBW)+S3hMMKyH1pG&CY2Tiuu~*|O=y3sqR#MIbiNT{9Hb>mD)GUJ8)~{V4YM-N
z&SX+nFdEfvU_EsQi#(_MDN~Oj>{^q3qi;(?ZX0FIjXK!*FOVoxCrM3@?F~{Vs-yD}
zNjPB$66jmU@ET|UT+43VPb;+hURYKnB@IeZ5P8MHp7!HsSeqE74jbCu{-YPJaiVvT
zX(!jrY^Tu7b++^%jlFyRf){Ik(+}bNyC3-ZN<WzMtA2c*G0&CfO1Y<5O}eLF1z^(&
zq{n>}2#TW<$c&>Fh*jxjW0)N2zAOt-+-ZoI+($ojyaKFZnb-lPs;;H8AdU?oFNw<%
zc0l>Yx)-`fEA-QxhdV3C6IL(qBg7;mK<dGwe>G6|0v?9>z_V2Y7l8e6@y7%XDsXup
z2!rz#yyX2E@CJf&X@o){{U8w%_py_7y8tC1<dP#qRQf?BL{#j7uh$1hB=FKWM1>Mk
zfFg+2i;Rm!3E}Vku+5GO{@98Ajd;5T7fjhn@lCXMlkx-3H+mHPH~jtxPr`?A)9g+q
zA-X1%rxPx)lDti{$O8r67<UfkiPaFR(|N5E&n})8e!KHegJ;iYLm4st)vbrXQ&jNV
zC;R%^A!W*vPs}Jlamd7_CtUKNxOM+z{y;ug_KQ-xj@jVf^&;HaA@HJvopPMe*f*6X
zKyAs&+}R5FgHN^al>earqW`2n$k@83&bgaZd3SW#2;k+73mQ&6O^JPvJ|}E-&UetO
z0%`HcMwbImYq)sB9*SAi4Re|a|4dr{%9-P@b#2EOoqaD@VqoTJXmy%>9;A*jq8>T-
z{HMimX%DA9Dhbh4P#5aZskAr;vIV$gk2iB|uy&;xF$-2VjHbV?vy&P37Rsq_Iy*cD
z{5LF@&t|cn-JeaTUa$FdD)#wrWGvSRl0Lf=Wp-31*(EG<jBWPB>R}36VxFce{fS*M
zT;|9k6|}thI%L;vr_bM&#Sanf%AV2hkM@MqVg4-Wqw>kB{3Yon>Lu$X%x_u524)SY
zRS{TE_^@&%2uFX&kTEs*Fz&{%7hu16DWn~i`yf%t3pOk^%InWR{aZoW*N`kswDN0`
z#`E+;wnJT#Q)x}zu>LL$bAka-Z3=%agAt6cQ9XYl6DI?Ete!?siMJD|$(HH`f=r&b
zHUT2yJ8{fi_pL!%GvziL4jbRN8%Yc%DtWX8nOBa#x;MT?QL19oUSjSReC)j?UF-4v
z$(8NYL*j5nB$y6^tu*-ds0eKy*i6dYW{tOma)QubFzBVCT=NG|XGE=mTjp8OuJ)}U
zwTq&F(tvNf9Fe3JF>5n618pQzR;M;16^KJQ&cBof%Sa?9s`kg0zKos!(r|m)xy`P#
z0%W=t8TdEqHi|de+#1)TxfZBM9Y`I>5J?hA&lN=FM-`~Zq)7rI*kVLTjR^hN+J&Bc
z-K1_q4@VEn504Ks4_6P{51$UBW-w=BW|U?omQ~2DV0IJ@aY;>IV~4H;MCh?N1N#QN
z%jVe>Hh@l+8&+jw=rw(?h0V=*H0xJ*##C(n0lf!UBQ*&y>2o}{d32Po68f}uy+Wkg
zd($Xj<7x`M%^BCGuVc6yj7y5+(8`i0UpKU8(?+{jcl4ALourahrcTh?Ehwp{+BL$o
zDk=r$4m<o7@xfETd*NZ05x!T`?s+}8`f5slX<vzV*S(;tbsT8huvSJ?Jyx!!VhGrv
z^fuGZdD_{pM7kTPS~2<&+(`FmETdNuus)PqlN?%0^xG%ZiaFky5c~1<{DeG-&ylr*
z3~wj?T??Xlo!mhS<3Y;DwWFl<scMkJ1n#Qk4sK<RMH-{ig8Aphnbm?-=G823*RB*1
zU5aASLea8|`OPKlL*Q{3CV*ow{ld=4m|tO^&*RR6GIqh^eH=+tjKttK4#)G;{DiZN
zYs8wr4y7Ec6;>k!hFu;dE%RXlq&a818=aHg$u<g@g_i21jC%4Z-tsR+zh`Bwqq&ST
zS(MWD<)VuAX7#O;8kM|_ymeMt&r-m0oASs-n?+{iBlwpg!oTQyl7=*flMdysHLo=9
z=db5)xNaJ+XnfRPuew|3{?1Lv<@gt%o{`)3FGO8_%6p3N6{Mb(doN7k1NH`cb>Bmd
z`Tz2tr*y*A9CLS~f`ned>ZYJs&^3q&WCO|s34o+Qgdh*lBq$feb>VdJ{o=<3%>~zm
z-NnD??hBg>qzl3ekBcmjXIDp;PuFuNawpIyZp@gUrlOwqAn|4-bXT&i($Kh?>L0-N
z-7AEhnP2am=|1^+OkywLy6>9Ct6fOPn1ww>XZU1~^_9Sb%&VnS2lP+42NsINxW{zg
z;e(q{-^?lS9(eDb;3@^Ib*pu^aJc~HzU01Xx~9cfy1To*yT=5_T*iQ7Zj^qp&6;{&
zPTWrXgQUKzx~#ghzqY^WI`<iBS-Wq$FxZ^xrtVJiuMyqCe#Q(45{(1?1f~Nkf%U+4
zU^6fQnDX!DXHCE-Yfn1sbCi+pWzk;IUpY|Yupe0?{hs`hhnq)XdU_I{@s`O3$)xcY
z(Kh!E?QeNzm%sR?nel;nghMV|6#ErtH1^eRyqc*5J_$rr4e$zp;&Q@**xh|kJNHh_
z0erB5B^MDVkGiQ(akq#`*#cnmX-!oUd_i{{62w(RH=dht!Bee=3c*9eX|cSUFMwX7
zjrH68R%cV8fn3B}y=mOMsjakct-xvp4YAO7?zpd?!q${kTT01iD=bB4JQj~^kN-zK
zkyj&XTXHY@S5cpTZAvL+q!TIafws4f@_Qs?Zj(*qjT_tH$7#kqSEr>n>kIGeNU3Q|
zc|FW{rB4ULH~uMlnDslH4myZi94O<5sDDA8t_k_ORQ%AyD9)JokCGxdfnsfW4@ZU}
zK*U9$+3)D!iI}6{$t&|6{yW8VV4mxjp&${-GW?<r(@x-+Rhw_~7_z!ID}yw8;XHg>
z%a?Q3cpvm#5MEo0<T)#D=9^Vyw~vP(rt9*k?o%DkSvS@V+S^*(Tpf@0mC0k1>_lH1
zXnyY?F#m2L3NH|QZmaYgtF;E<{N(4e{#w)*3OF*EM$DrnY6h+~q+tdky-;9#TYwVW
zg#~PAkLs*Bd}A?YgYdsq#0@x{3_4iVz>y&d;JyBSA>1>ZOn8A0Zf_6mrrYxH#V8Pr
zWEeH{hs(%ZlC#0XzlB}C$9-6(4*N$HuY3L#9Q(!yr5(kM>d-8YDh%v^b+++A;CHp)
zt59;mHDVurndZ+k6O%IXbUA5HGFZx4Z$IB%bf=$h+I5p&%}MaE3ZeT6hKt$YKz3s(
zmF;NA^04APn{-&s*=Q7`wm*)*!w_l;DsWWzBsH~_?{3t{Htm5rqnpt)Kni%gw4ctk
z!yyeM6XjfiZ%(c<CtX(19Ru}&8vrY~%EnYWZ4<6H@IndnSLK~_HGNr^Je`~uF*$I5
zvy?Cn6q)&~1c>(Zr!o}U78*Km@9|0&_o!Tr3Jp?K2OWitKm&UPMj|77)MRS;PqBv_
zCmO3NYLF*c!C&L<2@ZPV#K1c@FQT+Kk4KucI2ty7%y<n1!GS#uLvm)B;BgnOpSOu~
zI04*l7mkOZ&FL=SxBVAPXBZ5U2YVDto5GG<IevHhi}4Us<KJPgc}v7tjhqONO@r7a
zj#lZ7CKUhf$H#w7q=3KP|Iz-bwEd@M2|>=?nyECNits;!KjBzD0gX|eQi`ciHuPOt
zJk>%9RjN;UPLG*-p?IXG>_3%8jO~Atj)LM3U)o!96^WL|*@mmoT~2~TfatSlf4x5&
z;dU^KQ+ep{dg%0@M=t+UH1(7^t#&wdxO8i$OonF?%5kWsm?r~z$S@#kLRL5Kg1vEO
z5f<~1g%ZezE07yk5UzZBgKk3*k0PeuPK)Frh#mZlMI<0BEU^{yZvQ{oNyKgb`>uF(
z_FWKq+r9XCSG<qoE{L@4Ui!Z|P2{>yN87!J>&4kVXl<gaC9C5VN#7YB=)uC$xPkon
zHZWig*<aNJ4YSuT*lF|Q`V!G%7yJ1Mx@akdP=<ds{T%jxALd@4Ukp`>MNRKL&F+yu
zk4kB8*EpP;X#6p&d+w-1{-Z$rhTY;#XENOM-#0?I2>)LfATS<%v!p=0<;`e4Oo_=~
zNEybp8~^LWEKcMG??0|0J}vdHs}S%Pw*4a*(ni?-$bbJk?c}G6cVAnokvrUlm#a>C
zswueMT4Rf?O5ptC^jsc8|2q8{rNgSkdSh6tHMa8{`QIlo#_FM@zurQOmp{~vxE7=|
z0<oN4@)`psu;o2p@@^GH8D5{lEa(4Gjs9c#uPoy-n6S-%I$u%rd%_7a>*#GTp~aI}
zl;MAhE-!gf)fA1xcfpdj)<3gDD3Z^g#Ez;dl5>xci#q({<BKSvHvbvCzkLGw#-B<5
zLQkIuO$DpOmv+1BP6hk>bv|7SO5}W-bUN_23c2~oIqNk|yayQ~J`>uFb{-VK7L4QD
z$(G5vntW@Of0NER;<cV}s_0xSpu#toO`mf#iD6aTu&8%1E`IE|ip+QiuMFpr)KO3@
zyB|y9xF|fa+|n`0pNJD$%qPde?7EqHJb5=@^(-}hb1xlPXVQ1DL0^@9aS~ogOkw*K
z`P8>E!)UpB{AoptVP7KNlCsf7a+pTBCSUt9gcHGijb#jC_E29EVA<wkxb2c4J;kII
zJC^;FVWD30!wA!roUcOj*g^$1?jlv~)E0Cr8Jl0?WVlFwS?MBO{lniX)u5wy58NR<
z`~KM8QlMdysm=q@RiL5riGa;E{Apb`PB7JbO=hMe-%+??{s|a=(Byz04Qxc+*Q!I^
zCul)k)T%{YBxpvRsW8RQ*IB1qUJ6mFg}G;K8Cqm*L85plw=?TdQDN%2ddk^5{8A?+
zGsn7rMV>XD3+G0TPBDrTY7Z;ADsf}PPCi|Ur1zLweacl4Vbtg@j;~?gCB?M=Tj6)k
zX#cm9*dd$~uI({6OMy*0e9++0FvI0#V56>Ojk6FKIM7`>q4y;lfu)=C^<2ZTk$25t
zBe|lEMjM|VG_VWnsHuv&^|vTdNh0n2JUNA5wnxo~ZjlWga)s?}_|NKF&AOv6rnxQW
zSakLc&mgf&#qrfm2_IDR9+DiEv}HMpq{@EYHzSbKzJI6hUyyaPIkdFm!V~#QD!wB0
zw3#M6{;NUEjw&l-uV#SnpbBEaq;iS@occW^DCSeksdDXu<3_&wu1XD0aJAoLQCjC%
ztdhr8V(&~I#;mTi_*LuZ=s10^26XGANa|JpeaB^&+){YOa28DSv<bkpoLl~m7GqZS
zj$G`X)|g!BC|-^N{R!UuI8jPuKELk8j`57$h%revpK6{eY8qb+Q^f<<yH`QIwYVaq
zvxM6<qU~s2U0Wjy_o6Z;AKZY!`kj1Lm4!xsVb4w`XOi0eT58xhxR70ewV0);+>!<J
ztdv<_orPvqTiSLst%%!5gxJ)iFuW^bN~xb$Fne2Ua~DddR`cEp%<-K0G7jB;!#VNc
zJJ#n5v%h`^frB4+M9gZh@;F8x;y6|-cZ(@IFAVE$lv)qFOijWG9&Pjfa%limWErIh
zrDu)C7`<m{c<-~M0*?8&9)s&-H-~WuqoX5)#xY95H8Q1gQYPiI(MGA!#pXCSXUY=w
z4v3O|J+ybV_UnBiU>6|B@ZMjh?XEC*%%8(8X|Ob0AoiRR=}J$2&z1GtY!Kb>E80<M
zm9_)gUc=#o>0D{L(hyOW{2r&9Z{3k5zrqkqh?Y`G**h|<KEVzH6bm@-rT_+2S!6Bq
zfCWIBQ$G|o{Md8CT7M9_BnB)KU!V_wh#$pUZXw>pFUl`cF9<Ivpum7(T{Ao0lZ?BG
zK}#KG^Da^X$1Cq_TE$s`;Nl<;xHHUEqDG2CqRG#6N2v|T-~A8t@-1+>@o%N3v9qnh
z$#Lgp3F|NlErn?QlGyeO4|<4Ac*FCa1oIFAGmWH{(E_`fzc+r|U=(7cxPy}_6|I(S
z(o_(-c}0vm{>=#}iJ6O&hekDwd&NFDa#YiIbjn1}8I5J{nKnhX^4T+Z3|6KKr;QgE
zF9(14+Dq*hILlB*Jc+iyz|uiJd2#pqz-}sFKj6{~l1!rzStwte{BbV{&C6zV#6_m9
z;q~ri%JZ1@w$QfkHe?%qTYQ^p+jP6%X~Zexl6Bi<8*N*D+n}!{)De3Vx0`ugV4ZTE
zF&pok{G9ll?3_Xw9UBcBI}RldP4pc(DLD~2g+B}A#}E03h|8pH;%&Wc{_T?9n?Cfu
zs9u#Y0IDddF}X3WF|je3F{v>H=sgI}pRtp*Q@E2F;{7mjIe96#?b&w`<{9c4CW>`|
zNr3`;2c?A=JYdr)Gp2c2>0!f;1c_T?<Y{jfJCi(PE+q5hE#+uI1NW%V)sIjxO3k$A
zaeO-R)jpU|(uc?gbfjFCIL|a@;;CT72);P2)l_enVp0Ku#B^UH3(rg1ur(zL$Qu=b
zdMtas-9GczZ0)SD%hNt<K~I@m>7J$9a-Z9GqAQR_QeVn_zyuKfXDJK*siNo+f3=JT
zlZh#J#wkmntinnSPpdL)<0_gtw7UAB%^Pr{u51YuKPFCd9ZX?=-b-btV^_~xRY{hY
zEBbzzNJGoPrWMbmYFo;pWl3Jvu9@Riq_56Or*K#3Jx<RZPx1*kuW2(1uZ~`Z7?t!-
z$Q#vT8h6vkd8Ok)adnC^>?mv=Y#yuat;;Q^RO$y+Cp?W;njTKw>aE@_n^e(Op4JRn
zL=$vqfBD-0RPt{*$&{lKm0_Q?Glr3v=TeI73hNd128tQ7QsS0b_B8f1nzbJlAET=@
zx>dWso}|3Sn_G?=T^e1o3%-uI##}4)E%6=VVH9N$t(_Q+8;!Gzx=y;rUn_^?Lwb$X
z{WX+p(^51jDb|Q1L+qNFlW|7Jz`q>O2woX_oWF&VVH}{yEVF+T%>H?^EExyds;pSi
z)5&UJJ5Kv2uFZRN2h{Vg&OHTa-P9^7a<ut-VkdY6Diq4ZI>?mS2;ZEU+Eu_7PriCj
zf=w;$<7XE^$F8@Y_U>(YY;+KQwjtcRa!*`;BK(rQu+oDnd8nnm?B*}XSoN+ant@bT
zai$4tC0%(-shkaeQ>VUIRVk>PN7F$46mnG*PKfjpaN6Z(NP6UTFPO;D6JjBDXkmE^
zg|da<h@()3-~|1YK=~FS5iU`7q8e6Iz2jcGL)%|8?`*_gj1YICKO2HG<Zk$vFQhg0
zq`g|fXo(ifIpPH8FJJ7A>JVlBZ!F5)aY*Gx?NKh6U-;nW_EAVC;Id0*R+f7IDVFPg
zy`_2#G4-cN?YrAxi?44g-)tgu1E>MpY(xjJ7(<mjOzO#vb$)MlPpDx0sAcMN>P5al
z4HOpasgAh_d+Na3#R0POF@1eY|F&`~d8=}(b1P`8ek*h9*H-FR<xlLb>_2FJQ2k)i
zCBW-d{1&T9LlesMTkQKz{^3q+TzIYWGK1ZAY!KGA^0yYJxLTcM`VTndg#W}qrsv4A
z7w2Q_Way;ICItDKiLB*2$+c1$`po(A%+U?eP0_(fIal?0o6HDxri#0=z>de8T&+jL
z#oJ0lytF(qjsguw>&0bCX*@<7ZhmtZ`;8lGxAB4++XszRR_5mBR=XCmobQO+F%*6=
z_hsP@qgeHSZnosIvKw2@t)n*689a~nBS!v=W%*&0FSEz|Qs;^`tHo&%$M79r(lyCV
ztFeKxE64}M2c+P|jyu`e+=-1--HE;Lj+5It*||y8=|wTRCiQUBeq&4*<ONK+?~r7;
zp!TAmEWb7$c^0Nhysztw!)@|<1-@jLjy+3)#PTT}KRW*WVFmgMqRi*GkOeVZop<7U
z?MV87$~u9RB9bV)j$S=6d^cP{bki96UzoomoaG_71+mrQxCKk)A+sQLeMLP)P!JQ<
zMMC=H@(D%zCuJ=jMzGe`x0Of*Uoqb!*!Boql6@6ke&c{h+GBYsyruA!^ufQD4D#kd
ztQO()Z2<l{9F*{ZvKAd;??kkW*^L3kY9)mjT~co`Z;4zMd}V*|*&6zz(<5@Zvqk?W
zc<T)x3Y78(iV!@M<HtK+%n$H!fqh$mpBQ}bu|f2IL=jYioIk<Qi4j8H@gez>d_YzS
z1R$ye2VmvGi6ZAB!r-&th+^j=0N>;y15uQNOyEoYum=<U0lsAqGJ#_c3_vtSf{}E>
zLorp(8)mbCi7>~<sq27LU?%Ja(gZQttvP^whCM&VT?fPi(_uA_aW?_!FdCT5qk`l5
z{SIUg0uTbmmH#%?WYv=C3N9}pDXp3pe8g?!z59-I4dYuVP%CP_uY!a^91k|fV9L-J
z$i=?sFw7X*2g!ic>~D_3^r3dpr5ncsm@Cu}$_r|}P=*3`H~su62nv}>akS(@%b1wN
zwKQg6PCmYOB(BE>hoTo8UH+RlxpOzqphMAb#))EIpW|Sn37=pFTksF|m*fv*mm&{F
zmv9flmy~=6{sf(f{+QW_Kr9dvj5r$s2nT|LA$E=>p#>3qMX7w-_m$v1Tt&}eKp*t4
zH*gEPhkh&W5AEg9*5?QOOU4I{+((~3aX)=}bpH5l$@Cas-v4=deL@mj^gVq-jHKU@
z$@1{s0z>miS>PW(XiwSx76L*W8DR*IWRJieVd>p~pF716tXSf8VMl?Ezt1Z*03$i$
zzt2;N_g9KJQf*E}_nQE@myXWKL~?)Q!nZe?{N264&!X6II~0L3t<M~u>OsV%A0FL5
zX{5bcd}C=6m&J9V8y=6|`atTxCq4m^^J6C5Np4B-ms-$`#DLg6gsmZG>}teISL!yO
zUw_QjD=sspMOe0d!o}5ypks;<8{Lo4^}!pttAocIxpR?k(2IQDM|8u-Ki72K7Y~q3
z^WsY@-TjJ;92yc?%C?B{kGx44=7epb<8+&oRwz3+!3l_k>B;fxiB#6=%1pAf0P5)Z
z1npVrRXOA%8gw~cz5ah&U9I#ytbg^j{3OEu{t>G_*Y0CW;sp)qh-ZS*ZpVn_wXiw*
zBi@R9ciOsicid#*rnJ?J!J(Z%n1A48kxAjrp|8H=jVl$@XMd#)bp&Q-PoW7;fJ|v)
z<ojO<C9Z?)#b|D%D83{=R8+vDTESVVLIZL~0u2OVqEpYkUHWVZfxg^hpG9olkZdsZ
z(bq|1w#kNJM(KZQCJtKVv}$}`cn{a9`y@|e6fr$%H<QN|x@q;|eGObxuE|DTOe%JM
zNMG}h=#7}j($N6YvXgwpT#T=!MhbTo5*bI*Xo+Y77~2>gBX<*bYiQDF16bRr9;<f)
zcYPAW5`hW6CfBmp2qRQ3Um#8rgy8_$Tq^v2t&vUjoB0-1N24$Opka}#l6?GpQT&{D
z15&7J>bHzDx^Q}5oMB}_&nE7OPw)X^d0PN9OEd?9aYEm&Esq{vwDWiCtm*6z+CAbu
znYy%#;qIml%ak6Go{=U56g%JpS(~_gC@Q$(YhUgj^Y6<?W)Uj>FE8Bgp-(cAHPHYW
zJ84#WqV2wg#ff!j<^g!Zv&_ph$sCIt$}6|8arUD5ym7#K2k{pv=t?}K@eY6K|JX8x
z-%o5B*(yJd;~5dw|GAEBm{1l`AW#7Zr~mCl&{>dCkY7-+;nd;VC1&qj1qf-PBhFi*
zB1abyKZR>Ds^GN_=6*s4AghzG`MI;d!t$!+2+&TqyW`tq7HKN5>6_QLzUvlVmd&+V
zNDk)MKbceC^*t|(=xQw_7;`L&G!^FFcfEr-Cc0h=G4H#M<6&X9*M(mF+S_}zt<*x?
z`mR-YS!y6Q8LPD_r6y<iB0d#?&$-(N-!FEa#)8-Hp$tTQ8vSpH2FCiih=%x01EY5F
zO+%wBia(}B?VmI>N*GF-0E#xKmxlrzosg<<-X1{Ue{XC}^QxcaXg;%-fgQ?U_G{X}
zRhk{~HozR4i=x$w!c`Mj_3Mud{_G1PicOm;O>ydH*y?Ad<u6N`&wLBePYWV)O``Hm
z3T5D-G7tU*D9wV1Qj@4s6Z6#Cd|iEn{ENvH^`Ensob>}RrfI66_Bnpk`b<3&j>}M#
z>=##=Xr-;~*o^SJTtS=Fw>j(14KlR=K^H9aUu|YqicZo_#!hNZT22z5m|K}!*>&Hs
zplgSUf8+5KA2RW4MiuV;8BfvTRB}u}MU8HQ2_4cx+B7tCG7IeiCQe?z7D`!uNO>56
zxmU<clMWAWV2Zc;<z(_r0Oh8gGBD?qf%CER6`*((P_$}NxOz8FKCax<Rt6r>6uh@h
zcy2kU;-X(jEL+U5K`3h$T0qh`>rg*?RzE{lKLcw%Z)>jQ*qA6cy_A8S%9UPVv-2=^
z;S3vKybX+LVX}BNd1W@4zuvt3#jad9%?6llQ&YHlQU<my13%)1dL`BzkR?J4>**dt
z&5f=V7%2&4LuZv{F^(*)>FROq6D$=rW3wgONbB(;itt1@aqsMp$?wP}-}k{@co#@F
zd0-=+nB7+0SCE{pgb^7^EqN{VCQa%Ed3W`$`H$T4O6r`~&&!1#We9ryXuP|Rj0sN<
zhNAO+#~t$soefJ39!lXN>;m*pL5H1(QTcK+$%kWq@&C5+Q7X$f7nb{95r;~Wx}aU%
z0UuUPbjpBIckIY&A0I<@^LFoP5fVk?G324DF0$8hBi}|S<YHx^x-Od6ndY)Cik}rX
z_C!~5b!@~u9B?PiVUZL|UnW2JYb#@Kr$F)exkBre>M>R<^@>mJ>sid_d^=bUl!&>}
z<25vxl15~SX$ve|GT>LZ7d}r6Vq_)SCIXWb6`<tA0*-RsbQvkWIaBi^CNBhIk4z`)
z86y_GRBe=xO!s7LyWVz9^>L%#7C`zn_UH7|pQl=SfYY6N{}p<3WD6iWX?%tSVTP7v
z(uxIEhQ@v(!RUHDRfdc<%gv~~xrkobI6HF^V(Zeg%!ty6sGKE@$wsTuN=N)ngC3Y%
zFY1(5ui~_;-hLSR=&$!Yh>@2bETs+{fK5g$Q~3wh7zBBi??4LzKC-;Bv{N07cu|Q%
zgCK}%O3odD;p!I!AenhpVNL8Md|a28X&1dV7KV!WQ1g`f+DduC1g)|BdJ;WFZRU!k
zE(vXR+j#qwE{#QoXM~l!Q*4Vcb3ig#>Py0D_-UMlj781JFY_VuzWPl`>Diom?2&eJ
zAnO|Kb8RJQn_PfQvyYj-`t{m7v6*>gD3K;ClnFdFB?*%p9F{hRM8}&f^!Y=FVew>X
zFJ-51>*`V?R4=0+R!CEf9#3U_7i+>B^+{3|WzAj>_;PN^X1%S0-70Q#W(QlwJ?|pj
z0JjCR#zz-&_X?tP!XN##R_R~(?omNBel3l9Pvq87x3s(J$7%lJ-l|W}vv5Zgg)V0H
zJ0g2)g%@efI}Om_S*#;RyW!7ZN^7EetCxh^@Y}enM^PGKIx<ka%t`C5N<x&KSvQCF
z6XR?2`ngwvTdTs7LO@DxDzxo3`qp(=oQLwI^Y(*Ff}gVlPdzZ%*jGck9++U90<F5u
zyuB!#n+2vBr$K{nf8A0P@g|g<R?HgA)=(O(oMAqWp34Iti?c26i#Ah4;{8>gRG<8g
zsE@D<qh<qAL{gzR8QrOcqN!}un@cLZ=8&g0H%vWX^)OW0LkrweZ(9#cQW}HiK07=k
zuVAi-jyjA&<#?!{%TEdKjd+=#+fSQcBgwheI}V=@L!~@)z)CBfrv~+iD=ilHr59@0
zWfvMz^FZ~uGMRboG743dQVKPN`M5HRWBPfG<C1x_JI8+5v;HViL^BMT2lBiOJ4o0_
zr#%C9%4qof4O=(<@gfSV(Fs(BO~C>l046|VX}p@HW5WIWaK*1jH74!~TDzcDB$@d`
z=t5Hvp13Stsojfj@o-JG=ZiP1t-mnIZE<d&tKjRDd}nEsqHHH)vro8uXBa?aH>jQC
z*ww|mpg|Z(5w-gvphqJSz1&M)^bI+|m1~v?9wxB8n90fYrTXI%^Hu=GTJIgYKx?-S
z?-J)B!7VCMYj;olS52qH6S8bVMHIR=Xb(Y8;}+eLL@Tu}j?mT<ib4=U56P0kFy21e
zfT5@uH5V$Gp-K-s25LdC_qU{4t!1b*IQpg6e>?9o+)4L`VLDDM`V`6(YDq|1h)(EI
zC@0Klsa-My;y5Vfh|utd^(#+0Lid~fAoifgJd}6Ac&bQ=9}#Es@H7K$R1s{%gulO0
z`hTXUQDW@6@To!mwI48oUY9MEh$nxLoS2tUy3y^BHW8YCvIkae`SjRtJ^$gkeEBN)
z0O#~i4<SG>Yw>~80Z32`L&N~A>cEpNcCXpD3~xfW=sqE=k8_;e8t_m2u|`tnbjl2z
z!^pPW;zB4P=KH_fWL>g3d&HL=+xI^*`LTM`;wFGvlH~M1GRg3GV$HGK=0Y#g<D2NU
zCRA>4$_$-j$^O6Ev;y16fnJpU9kjpU4gyg2aw4o_SO)2B5q=`|6?}kCN8b;8{0hf_
zM4R`n@C!+DFq$fAxfo_CLRB7SV=&e<Dq)aAEy_O|2#klw2w(Z%!!!4w=wdGZ<oMtF
z1)HcmK^O2@e>{UHwtW5&UeeYQ__DWRN<zPqJg54Th6^j2Vb3l1xnccBV-H%M;sSHB
z!asK9csy18PaVpyK3J0DuTX;TBmnn6GjTM;E^!uyMDtDRSkZS3Gd5EE)rYIgVxSz1
z;Oyr&Ma!V50Uo85GxukH+==n(qYISyN>%*U*fh3-mmxeq_lD<u`4I1Pzk<Rw;AP!*
z92LuXXvi6EtZINghcFx8a4Xj@gQAPTPyd$qoaLz@pZ$hYu^&Ly|2|OF^lfiw9Ww7A
zc_asTYY+6uXh<Y5VD+;5fX4U6|E*#nw1$0qQ6wJGr-$QGL-!<Q-j-HlO0F0@fO7tV
zUP}S_K<>re1PxO^;V1(ud=E&Q3XKHg>z<5lRkU7w1UTZay_d81daKp@$ert0g?)ct
zLQWyyG^Bop0;qU*@ume}btf4Gi%I>vcw?8#CaxF~&ajWtf}0~rG!v|d`;yKL7HT;-
z;n+V=fLMz0ioLsi=bOx1n3ptlIf~mBfd1h66}lL<`5myih5+T^L%|A0=I@Ty`N4mO
z#=eumUShnxH_zPpY9Ow;{A|2!(b+q;&U~q7R*y=$P3J2a|15eOL6@KMo!(<>gPe_T
zv}^4*{IBKljVBs_Qu+?cu;YDF*_nT$(Bu`j5R`;G05cAl>J8yOzk*e-tiw*?8Vd3$
z&-q9RW3D*c`-f2L9x`a61ScOdI@ykE7`rDgm&$5fhgNt?9k=)dk(T1N`2>IMoW753
zFyoty{iiU64gLRht`~?Zi+c%*xQy+O71x=m50fanOV<<(1wT4_u()TF^*MWB46SgS
z^F@_3<Eq$aJo6Bd^^r`qEQUQlYs6s}t(ukb#O_1~Ah+fSOvV=d=gVI77uR`VzY+i`
zZ5+*xceVlZ0HSGlObVmjkf-LuHACNS>L-qShXD0I0m|r7_q9alS4ghD1P~NHc)CA2
zUkG>e$7%rW3y5^D)Bp!PaF^_LZ1t{DsTvTR2c`#Hr?-kfYksl}J6iKM6<OF>6C3Cc
zrl!{Ym+GH;^jsyakG>qFLJ&<5P2^kr^I3>R_HVe-wZYDCmrGBH^VC1`DD?M%tSs!(
z72x71VrdeG0ORM-b4qy5Zq;;3`9bP=67?g7{aSD6(ZUzr7q<o~1u}}IfYTE}fM0w;
zTYQnX*{J#Yza>wUf|~2W?Q9@>ox1;%^M|X00MEXmfE`C?!ZvQ?N0!m`f~9cxbAF9=
zVXHRJtcdn5$)1KFtB}^OO<P1Eg<EN+aAH?Yo~Vc>K4~yo<({brj59>hzFC0tMQq1J
z6Qt_3PfihczT(+-1vM>Row~DJO&O~Q`;biyreMT&ef^+lTBW1DcGzp{UX(i*I`m)w
z&jw$Nxyk9%)(nV(516{4{;RW67|<lT-wGDF!nqfsOKt1A9;~$Ry=Hn?`EJ_6C;rZ<
zWfyY5I20Ge(n_@3%${m?#Qh1?9}gno58b$dtbD&OUj0$7RHzTtLaz($o&St}j`+y>
z&h$U6c3V`_SH-{Cpof;RzAJ84eGr;^Hkka(_t9T#o&KCCKz!WKHBxjiYbXKk@gg>E
zC-)z5y|;sKV|hkLOl?2A^eG}=B^So+(7=>fya?i6snbpV&~KSPt=f23i~qj`J|VZ_
z66jGK6goU~7qRqwm*Z&u`*Go7W$3|JO{_96RFHX}nF1KT>AHIbJpZ%eg}K?X^*X>&
zA)J>i_njoyp6V^_f3Smvx5O@^wj6_Nf`Wg5!iF~w9B1n19jhN*n?Ba3a65NJV+CFK
z+2O`Th_XVXACey${?7dsB?A10W(e+(9QafSIal*c>P+-hy}q=<G+Lym^KGzJRh+CW
ze5K_`J)z)}B?@Dp<xQtf4_-+GDm3j0Pd}duB|_Sinn&RS9&$pMzV0I=TeF*e{7UQc
z<1(WE`{-c5kT3az>Z0jy^qf$HkX&APpiK|1detwg$14H7oB0;uyIK1W-B1HmIm%{}
z@Fk{Q<ESYiJ6iA7hUbuJ`s|fP*E#ROL(8T8qw%v0W=FwHi_!MZBKNVR)1H<JkVwj0
z`pso%x1sfUe^eb2(KUGQU?1>Tgkm4fyFcS^NI!i>!g+G_n6w<!lPha@sg=_aenIZ-
zu!0>O$*}#dhYNCB)Vk6+HFiAmh{Ud%LkvERLN3)Sr`!nouEjNpS8%7)WWvp^-!<-I
zh_8IL`r8z_J=OK0H%0jv$uTY(B22PUr2^#%HosR(v25rUl+J#8mx-7+ljlp9CC$Hg
z&&<rDD~p;Zu*qzfn^5;GMLdRUl4Vt6o+n`~Y&bO3SL9MfE|Zv7i~Oyu%Hkd=ppa9-
zrkYk}JCAux$SpIWasRqJ!#`$hlE-(W%aL%UkZO$NndVtldOrL}_WR^ex;@mPK=3ff
zjkhc8yy*E5?&*`TWZW$M5yumku$am$(Gl}4mtRtD(Zw|SErNG~alXzWcbjT1?NmzC
zUZWv3?+BSo+&VipF6OP?laOCvx1vdb<8;d*zjto8ifI08P@^L)e#)ujgJCHb_3A{@
zU7j|B^CaXwT(6u?H4v3!lIO7JXvdz<Zr8QQ<4;JfudE1@C?iD@AXR0UevfERXLs&8
z>y>|u>@f%u=&ROEW0FwA7!t`MRV`kbM?exPx2^i)oxhYUuGTzr=DVs$52=#;sPFMp
zBL}bKXK}kKyDEDXXyOTF!)oF03dM^)G1#HC^p>D7QAG+!7353J6d$UdYPvCl8N3Pn
zBH;$U4aA#jI;(RO^Hrs*Dl)M#RWlS5@Demc3PvIhAPnT2%GKrTYM`a)jT#o|$}w}x
zC(Zu8Wq28l|6E?F!^3EhayF`LkybC$rqgD!Qu9HRTn!5!Q(ioyY+TL71Xn&~Hm{L!
zLmu$CG@9WgIcAj5BCB4aO=G2M{a->=<m9jviBYvZxxMu3Mi+7ZvR8)W{A_K|D^KwS
z15q+|a?~j8UZjf>t)@kpi<T)t)oiIEQ`l(1b%l6&X}R%2p^a8kg@Be(Ir)O|g1;8f
zM%7)CyHcQ9zI0H_O7lQdqg+8Uc(mB1!nZt+DZgBUyIfz>z8q^oS*yh+u3TrKghZ80
z8?#JWi(bpDe6AdIq3}5WIMPPnU4y%#y+B`8Se3OrRg<}#yGb>tXi_U`p;5npr;N-d
zZnXxhtl-$&J*i!5qxxLav&?7SXW@C_<yh<v_pbJ-Rp2+d4nPf{p;E?PR#RS6VKv{f
z;JI)=j~#*J9@Vb2@f%cju6?0)U;aFgaNKuHc~|;W=&k6dFZ?@K(?rumO{K!I+-kvd
z9{m{kSn4j(`}L$4*QTDUjim0^;&(2(7>S*k2X0CwO^q7s*+!dH?wm|Er8vtPOJK1H
zXDNR^@#2Ri8m^s8&P>-##tGU9tqJ$nD@V=y)%&^ozxV4b^==d!swbu`ZEwPnlmM1r
zTy;4Mi5Ifxqpg)~>9~?IqcWK@ttXTwD)(b8#csYdl<Lh^eqU@9w@>BKVP2fok6A2q
z|1PW#<SC4?IcZW_)wb_w)>tb#n>k-NUjo}AH_0^it?sObco_Of`zQ+*brp7%cU9-i
zfEGaupgECwkwrFJfc26)al4&Su5!7?p_@R|WYNtryks!A(L-FYtgEyuKW7m%KWTIE
zov0DJF>00eEYd@Xe%|89#od&wYVJ@`AZ)VW=0v=`wAy&7&~~BeM8MssoqWT1!`}$#
zpz0~fTPawra5(60<#ynv(XP;5(SGt8J<NW?XhV2I;*~SG{yf9M=rugs;=xgocc^hm
z%c0T#;_f}8+FF)%(e35sOfV*yylf2EM3YUnP0mpyAuu^7A&~{k#sm{h27$n25IKpQ
zOfq1C5Ltv}qD0PF_=&a8d-wi&=iIT+*yH#zMA7}x)vc~sW6qvk)m6Ub(qG6oEYC~N
zZ3rR+PXbx?8`0vX9N>u52+w*FgsV}wMJqFJcs$~$#xzG1&*U33UrvtCIroLdw*nT*
zcE-H$eusWX7e@qQpgRge#Z|p@7RzKNIuoOb=fjt;mv7h})*TT8VG{#%#T*Ts+nz&Z
zL!Mwi+kU2}x{c_taHDGu`SXcW7#)fpPKqVLl1h*?ku;HBklZ1;LmEn=_~|wQ{>JW`
zz%qT;?U^t9DI{b;y?=>*B+-^_$?6+%uoH#QH<Cz&w1f~s0y@9^2s58@oBjMUl40oa
z5M4e=GKm4{B&lEsHl!)UFC;XiH^jPAu(OfBGsXG4pi0#JoFO~@#z<4k_QxVUk-(_I
z9_OB|9;O~p&s-0z=Vnh(k8DqlLXY>?Z}ggU!}P-pd=E(#;?d@Zj|n}W`5j6`Md*N0
zTRj?<$(6nJll2Qzu8cy={A3I<43s_YOLR+OO9{mIhRD4}_a1Mo_oVmm>B#9+y_3I<
ziKul-mAVgmk+S({DmQy_pX2?MulXtV#YNLKgEezCoizhB*qUKTJ7fg%4Kmi1qLE^V
zd4Vy)_+V~ftTDnEQVb6!-F_aDY4=h%)mVKiUqd&!sJCXaW?{^gUWkdGG%Y&qQNBBd
z4kLz1z{lZ{_(uC42o^F489p32oT_p1wJ{d8O(CBBwJ9<(pGf7gNuG8jOX*xq@hNVY
zZXRr&Ywm0wXvQ`V`?vd#_<!>s`<|kiVs!B0!05o|;MRflf$#z80nb6Y&%FP_<+sbO
z%duvMC)}w?jM*K{3$w1wLM;5`X)$S(tL_JM2Vw^aXK`o9vqoa{LahI!|M2C=<y5m%
zfQ@OLm0=Z+4^5H0IogPuCb`@3p5fP|6zk%=>8io1xvI{pfhug(Ft{B&0{#Xb`)a6R
zXgKg<z-Yi{;MRckfban60M9_W^*nfC|J#1o{#ca*TS@8!WAQf?V}O3pxD6BtlMAw*
z1^0l51gsmZ8XOv2QY&Xsv$eC;k~NYjZeWJdL@C{blVb+J0bmH#j~KT;GQK%cA#5|}
z;EZyqcB$L0*sj_}ZC5i_FxN0wG1m%AQ0h<k_WMrw&ii)wPWuk}cKQy8+al`b>!hos
zE2V48X6^#>d3xEaVnq@M-&Ie~ie&QGMNF+bMWJYbX{AAS6+?!uz#Zcq;)#A1U~=hj
z$p(r9h~gP$uYKVpp4Pou<>Pz<I7L(KTq}%4O{1`$Q=ZeF*yCxkDY6-|>FAlq*n13)
z64nxq60S|}nw*+!n#`N5)2aut+gRr5jH!$n{jHBum<&tWY2~JVmkR8rOVcoOjUw^1
zqJm#U%iz5Eg8dF^r}AXxV)N#4r(Dohs`Ffi`7mm2I?pp0WLq}{@+_BnM~<~TE<Lun
z5V`QYAiLlt?jK8E+_-pi@#I2V!cxZEcB^31c57{mb~AZva#M7(Zqwt~=K^-YdO=C_
zEky>oS&4%gpWeZ1iII?{b#Cp7eTWXr8A9Xi+-t<d86}wJqNSou6*Dc{-KY4MA4Ah2
zkzyJW?2PepL9%NVuT03wS^v5#VG&&#ZPP2#>)A`z%iHVHE8Tme_f7AUUhO+euYSB^
zDqyr_T4SPROlF#76lJVq^oaK9h4r%bQugZhBIDg`#68kY3Wkfo^ywl6SiHw=1cfc4
z8a=(}<l*_sOS}o;m)<fYz4qrpg~vCsbxAy<M~0`yD-HxL!XO<pls05U43zjA`mfn_
zCr=j-7q4x%ZSc0|wg<BtGlUt;3>6rn)R^$;_nGjS_v!GNCdSF^^cfIaOZS@hk_Jn=
zOGC>V?;7ND^>#xgL7d4Q)*cNYX@e1J_wfdL5KoziL8xOvF}AjMd}G~%w4SUf#3ZLI
zzKnm;e)6N^C=?Ct7T#*a!=ZETJoU`=G$7S7>Ph3QikA^~Zd)EqZcGp+FcXx&jFNW(
z+7F$8&O<w()6hX^Cv-q~4emAPB?Xppmx7kkJPJ+?77I36tJ4D5J+Gl|d;kmX_^M<M
zGPg8WH3yn2{uuhY{Z%TsB^VZbGdT1?=zYZpnl#bW8NBJw)47`sz4P1}cWr(+{Xl#T
z{(2`kB3Lz;E7;K`OJV@ALDOVk*W(P9m}Sn+`phE<@J8+W{|Np%5IlL`m1>?dohzNM
z+3d7%SNR9#D?s$e5M-^sfvg_5B2w?{Qiok5Yh>LP_sVJNo?G2^+ktpBoz(ly!M1Ol
zn4f(18-tBXtx9iYxM?=>HI~;G%!$rbZ%b_7I=Ok0?bp|`Xv+17#+rJC=2HajsrvQ8
zZ~4VOZE$$D{E@u6e5w4FT+l_xMUvl;)K2S8z;eK1z`7~V({O<ZaJZbjRV?zGmK7J6
z_ALB^d~9}Oc29OvHYz(h8zDa@?-%YHaUOm<oQ#%~I*JCtP0u9`64Dkjf>h#E&=B-s
z_H?#{`~!LNaGHpuaQ*NJ$+wzG9FwfaBg|2~%kJKi%xxUYpM2M))HC!on+h<P75v`j
z(dNma-|bH!*#+{&%wOa2eS2Y&xr!_N-cHPQy=(V;pJs?_<`i^eR`I)=hY-JGZ(k``
z#*Ja~;m@{X9;1S*Vq2-ZYQDU_W#0KxqEgiv5*fFKZw_bM_Ej$$anaD&Qm@fOMBpvd
zD~qPIH(wmnhKA>KA9bsDmv(P;Bf3G|Qr&(LC$uND<TNZVn0cj5)1Nc*N$dJY+dbE(
zW(arg-nKAvuXv?nVlZnst23)VtKD2(-{h_7?&@x~_j>QgV%8#hF}~ZfyC8xioFjsd
z#_UA~Z>y0c(7(Vt>-5c@#h%Wd${ySRH@Ls*+if~iya#V4EAQPn32D}LZK><St~;N2
z`ZhI7&9}@G<^y)VoP>Ez`OT*7M*9tW5Bn4}CpR0kOtuKlW9OUXg6f8_IOjc-k3_RX
z%iO%wys2xZSG(Vo#4^)S#$mLNrXNRh{Cvbb*S!6X`cBD7v{%PPJ26n`ewp{A%11UM
zwg$GvM~!m27M$)0-YS=DS#fsCFlAk3M`b@{TV(@f&A$0K0vmxXh)q!?L^V43nM#l9
zP(nIaDrbWpxOUmMPpxk&u8HkLg*i!**NE3gziNBn4|<j3gu|r6M3MwXUOG-X9x)>U
zeQ={ywpG=#MPFhZJ}!-|n$1gvMuj<nJBd57B%$Q&BQc3`ndW8=j6Sn(ZP&*?!0a3C
z(f9@2zqHlUte|{gatXVE-Pt%HJ&!&Of%U@fE!6Ks?xef+d-ZvZd(DY1HElI*G_CpJ
z{5FBdQU|5UHVHP#tBESA)On3MszniYyNJW6GmQ&&|M=F3R<2h21@(oJooLsNllD3s
zaKH3)LM1rQD6b)JQKwN)*MSq7@XzCrcJ?rPU3*7+KYLqy1A9&U{3s!hkQbDvs1m9g
zlgzHtt2&&J!G+*#(etf6^u?>;w?>=tPE=Tuq<KNSF#X2u;a%H{gG-&ZujL28OWw9g
zmfcVS|4;qE>OcmxmN>|_8iG31z`w-@jdqXbjV6u?w~b`33?D@hYRr~I&zJ&Y7Iw(b
za;|&><J-m;ws#J_&ipR@2p0sx)tjFbKP!IL%lu$D$=u64&^+TiD?cy4u)VA!co9x6
z$q6xpfh*gqqpHZN&8lVr`_ybT1Dh8fi9Q3rS^uaqoSvv!t#Y=;4tOSPabiKJ^3B)N
zZ?Zeumd*Cc6YmXF^@9hxtRboS-}P3X6PF_cZ>`Z)=T-St6II7mLsex}8C5OT7X#-5
zw+EsVNRyfPR1>0-5icYRL;#*en-0@QRjE~2Yp;RrL@91R6O_quiIdc4if?4gw{maD
zzoxDD-Q<Sr9}n-|v3OtlezhIde%v12Ue><d-rD}Yy`w#=9sLi=R}}AV7W`)WDdZna
zBfqQNP;95%z4P|H-52Q*Dm&7eJK{G%?=#xx+pk^+zI*BR>?PwXW~JYIZrc8~_M7f|
z)%V5kH{PeVZ?(_0x3qV*FSUdJGJ4k{nIqXGS#Dxn_IxrC*biEn-+%2>FR9;J+uYy}
zJUiZJT50O{O5Wj;(F&-z)H*|h^DpJZfC0!$r?a#D2P??~<%tW=+W^vvLJ5ik8v|+m
zzya)l#6VNOU;jzc4&M$R3%87pv`Ij-q_(taK>nr4nci96e(}oWfNj5P@&Zqr!Bxej
zJ27)l_5RU2g_ja3v<bJV-+)FQL2k8lyne|Td8_VrS`e0)9#G;#(}$*@iw}1`+zAT(
zpctgKEBBc+<9-Hd2D#~7Q!>*B^LOX(58YY|IthyTp!q>FsF?b9^ux`2+oap%$9L`o
zDSqheSn7~-lk{fy=6yxoOw~-^%$$C2o@}0U{(&@!G#T%m%v+OO0-RM``<%Jd;rBto
zd0zoPO7H4@<g%a!a>2P!0H^XP?aE>cukP0Ho78u>$N-F`?>IH|DyR!MhxF6S>$Th)
z7LB{3!hzHt)CbfjT+9H;B5&hL`loMGv(i65mkZH*BKu82NRP2xNiWhMz37zzKft|c
z(V_b&JT)9k?ZveXkSy^wsWjOuv5-ojAf`(W&V3@UL|gUI<caI^hxbD*vP!d7M^Gcj
zBhe#eBikdbBkxB#MzTiG4=KedEMyDb+RCoU(!NcWoqQ|$w(hM**4YSQBxfXk1T*5m
zrk!e(s`~=@j0=z$q5{lo8a1FRiPW0_i0Gppl4ccWZDgg6Y>mu~w2X9)ERBG1Ms_U%
zIRZ@r<vPYig<}9?PEg`}|7+`d0sV&Bss=D{<+z_Iv5C{mV7pjS%co*rYXz;6zc0rI
z^g-@Bt(^5gNKED`2h0~X1H=r(%zWDRwO8W%3lfXXpQh6d-HZ5YWk@aZ(b?Q<ik2*d
z^+%(dWj)(0&Gy|L60gvckA9snIoXw^{*`{)#El=3Zl16BxJkLbHde50-uLT#@AiuE
zfh(zKXkBn!sMp8qa|I{C<R8gH$b(}-Qg=VSWRRwoW{_rSeb~y_O4CZwN}cgwICLkJ
zB{=hAW{5#?81g$Zol~3IC=V&1H;tSHv?AXDa*<`oN@O0g6q(~-3-B7xK+Ypuk?)b6
z09il|fTOqvsX<8!80C~tEbG@<LGJ6{LVg8QB1-{-04x$^uvIt%sBLmE8-I@s0)!%?
z_4xrD$SI^Qz_xhE094p$0xexv7%xROAkUB&fEZ+ko>ZxE)Wg{CN*Z!hPgs#*Pb?zp
zSzDD}KKe8!PtVE|i&9dwvdxvK;uvMXN07*oDTX}FiH(n~{D%J~XC(mU2eSz<HPEH9
z(Lep6#9bvk$~a9k%{)ypO+C#tO)K_L?6DY?7`^#Zj;Bt`ddp7B{>yKd!OO<W3d{Od
zyaFr@EIw2|k9_EjO4*Tu#U4ocajRP7jFxk;rvY*KJs!K>xZbm#w2oSjUPp}2jr$?}
ziZ76NkmLsBfEfME66RuQkd(HR5v=lD<p^>#xIVouG5%nj97$W8j5I(_hJ~zy#+!;y
z04#;lhOokOJ7HZ|HoR0C07ISo9|f-uj87t6^%jsB#Tn(TW`x3X<s;1c_;U*4mW!Oc
zwg57mJ{wgiu}%z_7i$Nq;h%Zr9N{VFrO=e)m)(MH#l1dsgFF|fm!e~e$cWaE<H(`S
zG04WC)6mm61n%wO8wh_R73fph_+7^;2e4z8FeEC!M@~pC75C{mgA}zCgA_~4!xqLC
znih%{YDC14;*KJVe5PEcf`MZg{5w3IUYpb?2gyG+<uEJU3V)}bn_re+nV*+mnxA81
ztL`<J0iTDr!r#L?g=K|vggG3095g1?#?&TEN*Z(oK_1mMs8x-@w}V0OZg?I%5nh|}
zGKqR1>XRizjZ(0ikzeyW%Y*K0ViX)ow3bK1s_|eH94PD|d?0+{$UH7t<YQb-&uWoc
znV#}op+}Ej_B)M7uYct`?nlKD!ac?o&Xv(qLxx^XnkAwWv<zWP(WKo9mK>Irm6*y;
zQ&yW6n<`G?o`NC_O_abesW6_NBnz&}T4Qr(eP@@_`lPb)F}MR$ZH956bD@Ya&<v}G
zHO87^jj#Z$Zd0A74EmuTmER*jdSEG=gP@~_gM6)3DRM%~u^2je?hsTPJJUGRGm|uf
znu(r4)XvrVIruqVINWg{pClWPp2#R+DwYCCXiFIRRUWHsLAC~Gre`E-AJmdN&^jhN
z7&uI>e}o!A8=#BgjT*YPNRKg}^-E}0qa6qa(git!{6MxK1CZw2d?Nu$fCfPo*F!d<
zC)w6}<Wn!Fa&XQ>@;rjYkIMN+FSGpgbuE-wYiW;>3J0H6DxxE<p-dvQSA8b;lwaof
zdEBmL%u_mI;VJR|6x}gW`)6u$HA;O%j?<C>&R96HvHfYKVr&wzfG4(zeb3^zd{7vs
z_Eh?!Qn$-i#`DwZW^eFy4M?o<KB7LbjPZ}AlJ>eUbNp=$)bXuYYne8Y2tJj*3DxRa
z%UD%356)K6<{=J>Tq1r?QsS4g<094^mWj2UMIsp_LO3ZRDGa{;vPN-ck81ZVW3o@K
z$@MJ5hSM&kwHb&^zB1RGYeXjh;}!B<G2m%B@8uM0=A``ClSL1~pCN_uEPlBedzLX{
z!^C+wBob=@Lorf1j>J~A*M&CXu=XE_@GT<3L#*J{i3LPQjMQk_S!FNecMOG^;!CEE
z|9OR<!(s0l%ijEVd^&z+KuMLJJb4zp%pRTgjU<|G*(N%zPc540@7~J|e$dNfCDQA(
zzs0zq(b~RuOCZ^jH?@~P=KETTCXE~SAKi@IxgT>rCV&&-s1(C<#YS_}bJF$P^ggRZ
ztLO}Bt2?}MP-0SKvR|=db7pkTMdTnLZjjF!(Hd2sEuY|5aqJPVXkxn=Bb50R`HcE2
z6AnEN<8MUYs7kjKqg#CZluJxMjv|_(3T`QE)L9u4=^h!o^VccSlipHly1nxKY`;6#
znMO3xrCv-VZfEh7x9XE6<(W(L4ttuINc_%^Q|78*OQMT?Z}K<&=+b3BF`}n^k2}Me
zbo5S615DL+)OG1p1di>5&<t*w`#vBN@wA~IDY71ZDFN?Sk6$8G+rI6|!?D8<=D{sn
z@k|<bD)j7p{)5r~sfvN2xRhc2@bUA@hkS9wkbtq7Y?^K83^tB$9?L$h^f$~B{{&hl
zT(T^?@Bg0qNBlF@=-5owpC2wI&u)R^E(Ltv16kugdr*Cr`6^J?)iUX`PwP56Bggx>
zEw^6j5&P2^-}k<;M1#o-3czdS=XCNqV3jvTFL?5DND^X!GBKAFXO{aM%bI<Gtbqzw
z>6f<}H10irQk&|_kSK4ho38x3vQrlL1wUKf^YHwHgz!-<-|YtAH#Tsh$r4IYE3J@(
zGk)gloL`*X!?53TU$ecu>-1Y)JICGoPd|vi$@wBb!j5~mNd<XueAo9D?8A)?^S}KJ
zbzZW+;z@a^cAxit+1>nGqPMC)NPM`}akC@)opQxfL(2QXMqf>`43!=Tzl|Sxa(I{U
z_47;45?Yaaz~HT~8s^CriuDHdW>b8ORLm4)4`Loresw3F;}rXmup76F+--CVxzM~X
zmzwSL;o(Y{=`)d>)m|FC3-2Z+_Uuozaw@S&-xQC?ioQJ)pve99g7fKf?aIQBT3PI&
zG~=%h3p>r_ZjlK(xEg9hJ9!;wppP`x>1q`|7D9amwFeEJJ!$JQcy{C8=D`@xaYS-S
zSAYMC(d6c2huMDaJ*|J-?@)htyFS&D=u8LxbvzgU!^v_~qb(1^>gM~qMoc@N;+52I
z1&V(i-c4tI|BHdS*Un$Rs2?NI0rT3A^cQhp{9nG7E9ow5++7+LpqHGGdj+D-3pH`>
zkZSvbmG2YZIb0dO>sYHh+t2R5Y}(lxt<zlY0@IjIC8wqNt#^+^c=$-2rJmi3)fCdL
zsD1~M<aAfg&%@?%RptC181=DyOYsXT^ON0YP^|iZOTUe^m(_!+J5}=2aZd6mh5bnt
zurj}LJpHJgxDq*@L)I#xgd^>neidT#S<^RWFkeIFCdZvV*5#LzESjH}mg&k0q~%SY
zmd8!@(d~;6lm047KVyj>SQacBPVYEMJg8@``mkXHd``QP_nTfyxHhoJ#(|+0G4p0C
z+f(<V@TT0&hHpn{2H%9sk`ciH!h=Tz>Ip&nS^=DL@<qPLPY!uAMH<M6^{iu^i=qIB
z&*E=Mb$g3`7uG;z4QcC+v8{7L5%4S*-D{h)>^gt#cP5Sv$ZdrB8d}Hr&4%5Bt?U-a
zpJW(*U#>Yd*PJ?x1P*lQ;>!a2Q(B27J7$yw_Q3|PD|eG8-`-d@&F;=t76B3#J$eM8
zoKva8ARx4Jvc&MJ7{cKnu#e37F_?S4>C&>9IR!Y?L%_MXl<Y$O&gcm)^w82bH9(<!
zKyZ0_U$Q~3?DNJlO@r!o;+<u4AGKD%Jof_o0`J0;1-1pA1rC`%h)1`d$#B{(b1au!
zCR~<WHeY_Yth$6>hFsF1{~+(n+4uE{ZwAcs?j(5i`7QgcT&xiG-<(mLRb19fK4D4D
zjLnSK?BnYz?=K&)U9Ma4S~*!JUx`^6*tgw>%7;7!#uj|$q`Hszn(g+YIsDJ3C1Ed6
zoN#I^6_#3ps)?$J`hw~X)g9_kDn;tZ#g88V={o6vbORGD6MYliS*=-}?=M!VPpD(4
zG^sSHi{*l{Rna+9#Z%=t0}{^Y=ONU+)c3mU7b6$bEmYi<-2v_({+#;K`r`Tm??Ueq
zLw!lz5-!1n>3+#Py&|pk1e!cmJm7YMxwTpYV7g>Bf3|EkYc_ATbhbe9i)5i>t|Zbb
zfg_=0KViRQzj^<|e$_sFKV&}%tRYt3T<)LipY4w{0Z<^-0MX$Wg*rugx3k}fl}MJU
zJ?~AlO;}6N?N{wD?%(LATX9|itw^oNu2`;A?Wcl4iCO*nD@D1S!72q+g(jTkoL}x2
zTM%~$Y{o^#J;%w$dB<JGrN?iKzZriru1%dIo@D_j(6a@s0ciD-0h4;7dUbjpNS|@o
zIO{m&xb8R-u66y=GuxYIoF`J~>`*sTK!#*p7l*Q<zcl7HA{)!#+H?AIfH_?$Jt=*j
z;*6q+ak_OUXofLTzYyvWF_U+Uyt!T>o<EOt(RbB#HQ3SG(b>`8(PhzM(PPnJ0SK;B
zI_SexVEQmq*c+G;OdTc*Q<W;nFjz2<(UH-X0hBx3RnKQv?1Wi4>d^=F<hwii6McuW
zi!eeC#zM|;vOx{?I-8jMWIHVxJsD!oj?AJ-VLG^zdWHg0+YUk>(UZ65@Eg2>J%1W$
zKjDONn%o@O9NnDQ#4wI9jxmlhj=zLc((8Muc<6hWdc5&4@=*7X^-v|IjGLUDlpK{r
zOOBT~+#{y-QXGIe+X0M&Ci0<<u$eC+*`*i}2VjjeF)5#hbDd`l$^cuyG{QVVX0KSw
zQEMp|B%;YR&RHW~D!(!6TYJOVkOAW|F5*~cU+3s$=VkBZcw$d(NA5swALBr`b&sc5
zDo?6ds=Vb(OG!(9OIAxB0yE^e<H%y4X_x6>0R70To18<5S3;=Rj!Z*b5Sp}O@(^gF
z0w|(PeKHGMv@x-TK3YGA+-&S@d@@(Ko$I3JWh|PNHU=64q188B9+5Ww$y*YEN3Fx5
zSO^v>0cnCXK`$V8Aa|gl5JhO@_Q&XP#3*7MF$o$0O@J_SBXgsJ_*Li$GzOvx(S#QJ
zzRfHeMthiL`zFqRsl(6tW=a>v;5H7Uh`Ha=T4mdG7fKg$cE(TecMe03WY4t;%7m1w
znt-=5MZ^%f*_jgyW5eq^INC$<!-#V>!hQ6Yg{*}<B2R(L7nwq0NJOOVA;)3KRl-%t
zRrA#cVy<!cRmfFRfQC$YTX|q^V0IwVO!#4lnr!s@i>IQ6B)5s4=pv^iZ)Cf)Z0&?<
z9?y_4g&;y)I+<n5vxZ;3d*$?4Ad+5#zK5iMlrluQQ@)eBv*t&>`Gi|<#XIkJhC<wQ
z`Xr7DS^NVjj#LcxIU#m08HHblP~M(!>vx-Qn|JGQn|2#?>vS7<X`3QCD=H}<$uB8f
zLVwRPpTGCHK%7D%`dtm(oI)nQUF749$fzC~%e2bQdd!sbtmUTgG2NZWP+|l}?ImSm
z&a@i$udnQz?V2spMdpQu=yx8|Mv_NH^sp_3yAM7SvQ7o7TTnWWrl_%p_F3+yz0EHy
z%CLKB`qEUyRFIeeOJIm@E$SpHCQ>s}Gpd;VYl40M4~<Es_<pOG(`qj9!&E}@YS4TI
z-H4*WG4mPwb&)OpBlx-6&HT>%CzwKfuKjn&jF3582qXmJS5I?++o*e~J;=Y4FOP|{
z@2;_-fmeTTu&GQHas19+-MPtsG5Ew|%*542pbm~DX1n0^i1Fb=ziV{$weq#_bubpD
zTvhXkHnL(L<gD&+5^Nfj_84L0pG;*K<XIK*2=yswz&7{JI&KS+r;w+Ge$QErC#GDq
zC#J?4^+)@6OFFmOX9zFw^QEw)&<?7uQXjzO?fR;gjk{=OvMW=#$s&3e>ppU8tG49z
zjXK!ZL5v%@rIK2b2uT40Usl4br@*suf6#M_(ZmMV6ms8=7+gf1a=%gS(y_I#sWF`4
zW=cXNxePF?mgfx%yc2VxtBN$%Fz(?l;Gs-X9*`fP9;jK#x1Ip^R=x9iXH>&&q|fcB
zpCvp1cccc|7xy?+i4%7T7wD@LN{=Sk9gAz{X6(1Bjtx(YPk<N1)KIJw<{R#gU&URd
zETwD_Ri;&@wWb{OCDM)~^pz7v45d61B95WZf?8~2?~LPCHJKqfFtj9RB7TB@!+zr<
zbkrB^+b!<gVvneuujDmkF{CY3ouJ-;tJ@7!t;}?Z%;Z<5I+3OIuGR%RX#-n`sf8RI
z>!34@PEx2A6af{0{jwG2Jmoo?R1t+8ni`tUcS?3LaGrD)L}5`)C_hvvsuyLQ-7#T~
zwckK(RUXZpJKaQeqMl$2w{o4od(McMr`3RJK$YrPml+#pFQ*5nJ1BW<oO3tIhIXcU
zv%#|xfpXkrZ|dBxyx4l;H)iVUT2(iL-9jAm`o+M?VQno7(snWyEGU*bj?JZG!DA0%
zQW0W^8e)jvNCJvbM#vy!5h`KRSKnK=zqwgS>@(_wez2=xL6J`@ZgFf`9%GL0UE~t7
z3E{Ar0F1O_o26NWOa<Re@+Q}@aOg<v$~R~jQ;qD>OEE^Wn9iNMV%gEYit#z)=xrPX
zBIe8J$8^C&h<?*c(Oa=p&-&xBSGs$;hng6#Seba4gbiaIlNZwoBRNwH(?GOsG}Jak
z5SzM|AWp4;z$`+<T891<+>E3kjaKfJ@1^doS<1JZaPO`B%lj`w2)CF%qoYQa;6UmI
zm4tmkk3CpCow;Cv4y=GU8e+FCuAZC5Z-S3sors@ETp)smSclBl+-<*#ZA&gmuBC%b
z!KP4Cuc2425<B8MVl3h;63K|+^o=qS0~FUV8}x;Vcyjj&*avjOV2awq87ka_YCtu4
z)_XR1Qj!wQKR4I1J^C6JO+4;_jLJ-sr{tT2c;g3t?AKqGedbz6dI>iegSN^v43dj`
zYbR?L#&_r;Ozxyj(M^xa+$ZTK#U>Lr;x>>QjgCD~EOZh&d^B=2RlDiCYRq@pHr4cV
zx3K?r^g#hqNBM46r2O5)hx}1OK|*mVY(;vUZJf$%>NnLb<>cV`6!!9Ra&qlqVPSs~
zf5XD`5DRO6jE04g#B>U95A0X)4hWd=cKSA$@=b1l=|XHC!}IB8Py9Cup9!>W&%#`O
z#!AO5oHQ4y=oERZmugDRA^y3p$=)B`f3qSxpqOBg*gHVEvbAE_FVWADr1>J#RJz(<
z<Lq)@enoY_AgTO?nOUncJtzan{G5-Q?*$(hi;i@&qz*HeE4OA+3@3|$be2E(tY)8X
zrFvj3(JP7Xg_&t<qd(}ZXP;-q_-x|Z^fw^GLp1!=U)r60+Q+PzB?JNjS}%3Z#`hV1
zl(?DJ|6xMKOG=CrMH+M0Ab9DAT)mVe`z%Gq<BUfc%o%hUlo>3hRHpRAs8E!|m{3$2
zp;5aiVkoGL-PYYV_K;VPqJtSa`*sU=>vuoyF7MXtM(%FzHoMt+D|`ERL%l)Xmfos{
zL?h46-5s((dg+JKjMDVd6w*vrPcH$d{--*p4yOw8`tqjoZ{)S*?YqB(XHm0qA~_eS
zKZPHM^HVcXQ*!0&sg<V~@fTPGbZ3X>QFC!k=#`XD>BW}4<U|2BOQv)y%NO5u$A(){
zb8tzQpH?kygg+R?h4)coIBoR4m!%k>jVg03e7e`eq0|gqC_Ou(9ne#6v+T5H@pbo)
z@EmFmP7MQp?L9#ES-2{-0hfzh)l;9?4@%m(LITePgan@IP=8W<6np$Fg=osLuu`$|
zwX(6&unMr!wz9Xfwo<o(S?NAw;(v;LD#7aa^y29qR>h~iPdQjK6<Z_ynHnB8FgEDF
z0N5C;8ibog<e_6%V#i~lu~D%+6g*YJRjgGK`}WJPm)(}_mgSZq%MsrUVh>_fV~b-M
z5{(jl5^p8SC*~yvafa$g7nUF+4cIxcT)ldpdKx9^I$|wgo0atbv&0C_Wc{)d6WxYZ
zu&#CEXyL4WLp4})rL{jOQIRtSkU@N{*dORG=i<{dEo;_i16UiZ7<@7tEWWKzT1Kx=
zT^6oCZcwX~!{w#7U3OWs|9a&|e@-F?r=~%G_8EX^1XN8l;BwWo2CM+6^{4@f`lLvD
zW8rKhlG8M?(4m}OcU)Vz(m`eX5Sa?_K&~3_AdQV{s~ptF&ynf?JZFvraC`_U1-L+x
z=`$6H>qD#750HGtt!0f`(1vy6T0H~^Va8NK1|TnCHjye3H(@F*D|abkHj+a5`XA-4
z7mdg04aX@MAj;0O*Nc${fMjHu{#@Y@a;TWMkQd2Y%B&|<<0}URK%2$2=S-#Y8*_Xu
zjuO`K<ATL&dc)<WdM!1+)<^L5qwzE(W?bP2MKp%_A&FM45@{V+$+^|h+PIm1APAOq
z4nC?aq#BG~RSZIFLEaH}e+`8gqZBrBc+j!vO7tFD8C`@{%&yM%$a#<xku#88ob8yy
zkc&o_*qPS+VNAsnMHWsL6&<E8zl4^nkrHR0p+G!FJVG!d=n#|$77!JP9z+MC1hLFf
zsVhd|P`Dvn2Cfy?fs4ge;`(rFXucdXMLsz`#qx0_;c4MB;SRXgU^~1+xYOaQFdBXi
zPlCq^TRQeksv%R250nN=;0?kL9BC%Gi;V!)C>z<qRr<Uh<g{sZv5o6sfIVa|4330*
zt7qr8*r=&14tBv`2xA;=CcYP?npGFt*bnx@g@rd9MaFX-BjL`%5{}1Xo5f;=9=WTA
zgMIK}$JUaw#?`ljD{x2t7fDP5F}EzUrrM|enyN5-MH4mNYiz-4X=%A+8E>I$8PjFc
zz1l<5L(`kot=~P-Bhn?(n~*|{WyVrt8L%u8R2STylAfHN?4BZ?8uUzQkJBEdF{ja`
zQKqo~setrAIv^#G1xuyc8##rV8k)+OYMttsik+&Q>YG}t<g+yE<?Z6_EgM&<ovuBr
z?U>QpYM<$-?R4m@MbDfQ4Oy|ZmX5uX8c2lkh0<2ZOhfGhN7_l=Vi2GS<te+hYMeKL
zoHK1I_H^C4nvt!|9A_?<0{G=0J8d=0MARBMl=rsm&3gY~`aG%(WZYEcslIhSqh5<Q
z&hZ3p4b4c^UO13XFc(Sb`&Ati!~Qw8m9=R3H5?n8gxmHWEOmH4mwqYzN}8KFT5;)U
zFX`{J+oz|wr(>tAdq#T=d%=6%d)9k^z1ls}y+L<2m+rb=ukMqclV0*}nFyAc%<#-l
znNgV$W|3x}%*qcYRwiz(-``MK?_UoYBQ1{@>t3hNL+?57A@-#9V0%G(tb3Mw@q5Ed
zW<71uW?^R0X2tRARU7*oABZNn_t2n?kn!M+Z0He`2g<t9GZ9surYBmv9ouLG_1K`9
z;3)&@*CAb;=Rz6>p(+SKU5kss--f!-b?IUWQ!nJU+T3)b2b6ZBYz$O>GO;#sXZ^v3
z>iWQX=ooo<3^7+7!$$m3&U){-W?`m@Old%fP~*1M+#1wu0tWKR+6K?n63?_WNw*P$
zx+7T(W$FVAVfE6+W@ZaIGF1Uigj1r4Sa*Y^C=(!47hq0UJhwh7UZ0$BEnF}u9|Im?
zH@wDoN*Bxm3$LormyQb7hsQEYWefr<uT%&}w_RmjWWQupWaVa+m@9SehA7FFWK}+y
zeu*?U>HHYdM~b1h5&G_uGC49`k!$YLxgG)?#oaD?()6V5$<#xK$5Sus%?)MipUh}2
zjEuglGI#1c4N)f5Wni{X8Gl)4Zr-^VVoh31KOy2|H#Pf3$dDAv;3>T6Jhk9f_@g>x
ziL`)zNGRR;)udbH50%a%1y@TK%P*A`mAREA?n+C$JxZ1(m6iO{uaNF0OCNjsqA>Kf
zLPIX;lT*|6x$Zto>pjpY28KEzhbSO}m(aG$r5^p<s}la%$Id0LPWFt`uTbv(OSwHo
zQ87Y84(ZtX3U~LVsvba;BZH`ri;Et8Y0p+v6a9(EwyWgWsnOD2k8YGL{jf-eWAl`E
z-kxuK-HW;xBYIPMqk0oUx%S?=xi2QhrV^a!$A!x5-(r^Y?bQY0Hll-$>rTd_HO=-=
zOk;kOIuKryU#czv_Y{TAK)&GJFz9?r^@6lkyK@!#IiXg29n4t1BHTuJ(AjvZrrzEN
zgUqj0XMl@{zEIc49Or}7{nCy_nH<hb@ZOlBd_i^Fv>{=TQ{yN^>WBI=`){AV$|+}a
z^FQO4q)_g96!po<LeIj);;jYP!q`H=!qdVuTd?w3rDUaeC2u8vC0iC7irw>>Cx^5;
zqY|SAqk6hhx`u!3DW|)%`wMqr_Z+cevGRu3^a#Ur!z9B*!?dZ-Q|Vfd^ey}>3@ltN
z0vELwtGo8Pin>y}rn?%ty1Np)j%-{#Ts*!sR5au^l=vte?5-+#lr&U|O-mwuOb$M-
z_6=g-wnD=$8I!Zq&AC242kWcQL58$CA;&>rnwQXy%T>+U>w_PwIfEQ<P0>K~CE(y}
zRdvuH&9%m=cDa_ShN?CJMdCm=BaoekWaEu;LBZ=pcO2%i&248|2eyN~X_~^B_R?7Y
zvNMZ=#MKR+`J~yT*Q(~K%Bn^KpOb#@#3mW4TB=rA>kZT=-Q$S|=GT6=OPv!a&#Sgp
z9@tMB=h-k8K{?r@jZvsgyXm=o`+@gKoji&_jhb|qv+R}PqywI0<1*B&-JrvuBaa=A
z1CKM)n0O6T&Jp0)ER3F+7tgQFfm&=NOyEaxNlQEh#zQsf&SI0`$`zG?BYjs#7soHP
z6}7pwB~Yb}U1C1hlG;k)X>lafWaHyRUn$1ewr0o$F*!5cm<#pUSf7BFG63sp97=&e
zubOQaLe0_ZjUN*^r5whZbphyez{c5xYN-Lx^;vbCPu~YC?J6O$=VC%)PmK~IIVk&%
zms6}1!4_Z@urJsKtN{)HYlH2<*5D|i#v|X+wD0P-<AVF*tc<`)U~hrANH&J}zU9K@
z`sI(y%gZ&(k;|LQ%~rNxWv~wz3I>5K!Kyl{F6!G#+Zq9I$<LDMl5ojbNyO#TGr+$8
zzRteGz5-AmXbOA-)CSsPzo4?5S!a+li_V`=$0&YhCTB`)evP_o+O$Z4a{x9QmFLWb
zov0~w#f~Mp2+p8tx16x7Q7#OlBF#LbG>(o=s;DRjhDnhuXE3$~Mdw_NU9E+pc<h1m
zs77ZHwg<)IY>b^iF*!G3rJW^4JnOgYu%A#EXR{jExM%B@4t5;Huw}I6vvq4rek*S)
zXeJaDV^{7FQ^zrb#rD>C)o40pj!L({Y%bD|&$c3Fl2PSOW|-Din66*roZZ4iYc)*s
zqV+gvOK~QqHq+^6GhyHz$|H{>Wyu78Z&lpD_d`oMmsE%3nu_Mjg@#ee&1?MjHH7_}
zAc&<e#P)_bB7W>qcKG{+1d-_pv3<o9u|2mt5!!Jhk~`O(d0i9hp~Q^8Vy@Ynu1Uvr
z^&ydAmzhZ1K3?~>P3$e?y6^kf9gPw@DghJwD87d1iO|bcVuJ}WVrNH0?sqvvo~dOb
zbTvk7%7`bHqCJW2dtVV-SY9)kU6+`yM}l1w@9W_Lu7~?TWIg?pNM50dto|cJlKyv3
z*Mp{SUiaC5U0S>@&0Lq(i6!alCK|-)Qkg-C<Y!02sILDYkz6VgJKcj`6VhuUN*wJ`
zAMqcHL_s8Y6Tb?ZG!a)$^2jUb+A+c7#Xd+WR;=AUX6(pdo$~nIFZ$gu#peHL@H<6<
z<mhwz&&13p&(sr{V{Mc@@`6V#>{Dx0jJcdYi>QWMDP!|Mqo($45T$c9ab85+kdkel
z$EZ9$95T0bwCwv^#@m=zI&lTw+IxO+r)3t9D|qKY_t4LughdPa!&{9XTfg-t(+p(u
zQ5R<qOa-PARv@=P#Atlxfz&5HiG=aZHigNNNxbp-ZP1#~Vdk{i@T5<~@Z9SK-ub7E
zu>>z1`#CSm!gs;~<&pQ&V&4VF)qK#&$CH|q2RjDy2lJ})#q$hA7wU}ic7tWEBhr1+
zqo`fL*<$O*@;T9-$scLBw8gaTG<@1p+756TxDLbvmw-FiWz`Fk1(5}f1?C0mg*OWn
z3;YYp3u~=>FtZEZQ{Ia*Yh|Npqcfw960M2$k`ANJs;@@qlJk<Jl2{|l>K<G5emML{
zX`-a0!RSFXjV;fBabhhoQuxFwH`_q}Ohzr2qwB;~iL6nkHPf(oB9wi@X`-Pd!pNYi
z?4sq$B(U8K$G4Y!7J3?b!FrX_hR!^U*^fEU+|@kRJQ&^`J{~^sI!``LzA(6$JQF>y
zI~D$^|C8*e%g=(Vn^&DzIaicdm@B?Zv$NrgYtLs_D_iR|Yg#K>>tq}9erCAT(<V-d
z48%8=VdnU`SSfx#mE*(B)M<~ZHCw)ZQ+SJjpZf9nrusDAiPaByJhUk_eNjbj!_p_6
z1QWP8*yO8j8*2Rw6T2{uPKZauXHtH@w?gurE?tnDBb{=vXxP4wE>%#()_*8By+|x(
z`FnqATJ=j?_o1qEfS99)$g<OrHn=2xORNceyt+9omT+J+w3n_cW(yu#O&@4T@nBo?
zEfXdFd<Lcf<A6yL&%C@{o{1)5Q_{XOB}(vmz1?1(wQmpv+pY}_Y<&mCHA#9ww;N}p
z8i3&1+0q6Hu-94u-0zPQw{7$+WkZ2S+cyH|iT`%qY;l7q@fEIr129so)XeM~c;fXs
zL@A*1DO;{UWr$ib@@<9|YK)?vlr)Y#WSeYURWp=cwk<*bBQq(XA@?AezKq6<2hRuc
zm@rt2Bv~CXnTc3M`_F{l#yQvgIj<2^!^e|Lu%p=0l&wig8o5!EF#qPxsDwQofr3eH
zCp!oqgMa8t&h%!$K1F}zZfP!{2CiUF8ih8dFM!r$h>R%A$Wa~^K%NoknB)~P{D*50
zZo(}l#hpB+Luv7hc}<RyJ2<)XKM-<(${ZLo^ozqu2q!E|BZnM=FOdMg9WpCB6u)@F
zGMF9EpZai-@vb}B$5(gWw!E-?8z%UqiwLRRb!Y$hit=sxy(dE-AO6?jtS0=+b4u}a
z@c$Y2-@~Wh%(9tz3$%|zp*{P39xY1VbI<trO7m?x$CIJ>hil4V2hY0xbGQu>bD9IW
z4T~Jgjlmcl-V;xgR$dz^z?qy2Arv#S4)DJ<ewJ31z<WR_U>Usmd?Rd!@{I|ta>?jq
zJh<^gS#J3VF*8vky!HRPlPE6aZs38Co3J#O+?^5iLr`OCtD@krZFqi>8Z}ZUYJKbr
zdu^e5-RKEk<ow2*Mxd(K2svKkoMKL1Ccg>K0U;-N6m-kt=i-)Lt?~bSZ<-UBJBgPW
zVK`(cV0(0=rT^*C|NfchQ!(WFPd?{1L!)tTXJTm3S5hMDmFS-khCQ!KJKin%13T$0
z*_($V#;;uq-pnM^j0V(%9Tz+?R#V0O!&qhK%S}9@Ch{tbEZYm+ao7vF+Y%c6WkpDh
z%kHE8D5tS{PEAOU9ZwWS+*p&rj@3E)-np)L+*M?Bb`JjWxrcbt)raVulTk8X7ADP|
z0!rLX$Wz#7jqJAEczijI>fBL0QChA59g2qpq^UKCsF>$a{a-@9Qv@aqeThM*9=eN1
zNWZbgaNrrwsSv7}`3E>bh&1Rm?WnCi2P~R5dl=LG_k&6)c{CX(a4rDSFc?WZq;3pv
zRWZO!;^@!CL8=R1HgIVWDOiNd7gtQwAyeb0R#j2V362KtqmR+czYi!<fI4W!8;|7!
z@fQ#V!k;b$ZFv&7PzVPhY&)9;Gj~YY7%F}(+62e{4iPV&bt$}XO8BZ!#LRFsh0|<T
zxRf%4tNNiO;hGmC|7eM#8Nu3rKF$lSVd2Rp*oV<z9*O^%G%A66?aRTFBa<D313_LA
z_?h1BWU<<bkz(%CXC>Bz>tmjmX7L-VF4aU&U~bPSrP+PBN{G&t$;rXliHBUJN9VPD
zS;Do{1kEe<VlME%pZ^1)#F872<HK8>bBPCE!8P*8(e{Vt;)uZH3{U5T9tC@+|2s%3
z>(z6_8<reF{1Su)_F*Vrb5!i`g?O?w(RIWY=TEc}=MIl*oHK&tG7BQ`4<PqovAlVF
zXzN4k#`Ll;TzD=BH7v0#zZ@-m2yIMieKUy`#rvMq5Z5{R40s6$B`nz`e+SJYBriBz
z`d_?7LH`!*<bQ{Vy97T)jZQs}iW>d<-jw-gl$FynOIA9DzA2?11p$$`%Gk(X3tBE&
zs&f35C-ArUt)u@P55~F?Ds{|v!4j=R2fc#Z!bS4Vjft(Ab!c*&=Q*%3C_u?;GzQ0e
z&OfIvljT?Vw_23_%i6HVXz|a>vt6kj6Ls~wQ|>#~TMRFzlsXjdi|ACueu$#_#UR^T
z1}4As1g^#Z+@p&nPY`DbVTYv;WowR1A1aH7O3SZ}7T_h%Nr?V4Bf*D8Gs>Ac5x4^g
zKkPkk7T;*zAzNc)t6DOK8o~w(F3T<-9X}Lq3~AMv92LchpR<EB7qS^}SO_aD)Fpdo
zbnsBBF*x52-Y;|@S*({ME?lV0<A5nWgf&J5yspD6j4~a{HpU0Yd7)$QF6Z~=WSOp|
z>hAonDoB_u`9Cj@N=%fm(;>$@R%(W#DWz@&P7$5T*zhPlr(BC)3lejzTc7!rC-ArU
z|80-f>vh_oB$j@>=#9FAcA87x4#xTLW+UP%Y5NPyDB_T{F(N?C3!{l+UcXigq~pJ=
z4U(?^p<hf4grA3POCHff#Jv%;k;x`wGA-`W`BN4%<4wle<Z#4NZ6qOi+U$DeIs23P
z*uXv0VA^c($`L{eLzLyYjzBeJf2I<S{1J7hv!sVx7Hixy->&{%H^jKEUhRB3o~rDP
z{#m_MXs$>q;V`A$8BOmwR*@6JB)s`+LAG;flV5rQ*W%~@H{M0{vN#7N*ZvE4(QB!C
zY~ds`WJVkhV-Cd$cYK2amh}G5bcJ>J@jvydHY2cn!ZJtZ1_ORdsaHW<WVA9iItt>H
zYst#=YeC<P%Au3L@&x`Ce?Q}%BA(>@F+!Q8pc+RB5rM@GWoe=t4(-Kbq-EDIw;)eo
zNuHx?xToimAT_fus<;Tq3)m;#96rqTj;yj-Rxz#^A`FWv%PPmz9+Eajw<=F!>TtKu
zMdp+iveIx(5J6asOV$f`z5t+5MHue0O6s5!F$3X(WxC|BjBFj&LGBPfZ|Ab0L5G%&
zX#sCfwEk8L(7&t=iw$4@d3ok7bC?+j_olwJE8G?lsEB<ZMdD=jj`b!3-7f|WsW{jF
z(i6BAzxHaF4AHH+7pHdq3L&5Qr5Ya(A%lev<!NGk4(Y@*dA~fsSJ%W#E7GFZ@D}I4
zf!><ss^V24bg)$30xq1&`F)VQSza;ze?8+4)f+Qf<wZy8@CxT-b8-uLX?Q=#19h}e
zV$oXwQX65D5%{0(un^Va$IQQ~AQZ!o{&{&K|KHseb`gQf*iTVvPF5DIlnkj;-?|ij
zDF{4ahpGLQC-ArU1r#r}#e<|3Y)5<X+~>a|)H8EEaJmp)7<?#ac;pOn1EiFhhd2~#
z43pNR#r(a(0;!l~58wtMVxTt$qXsz6b54-DS&k!a1HuCfD$8*lJv!uReBY`rI{LS%
zX-;h+2Wa=d?GvZwy!%g<ibPe&cl?)?LQ>{Gbjr_Z?C-~_(bTuE3N#{B6|uol+)h^J
ztPdD|EyxJLGx<wT;9C6u?#C)pHwZ4|!R_?_zXL;5g|dHHDfYg<`=?H=|HlrDl_e_!
z!}Qd*9t9DRs>;}?C?}_13$g{FK)>_^uEqcF+<_s!JB$}<T(9G7qQB{%OV26De8J*f
z@nq*u=9Fc!n{d4lQNqXVtmtc1X!@6xqRZpMKXoeYCzBcKwAZLoKa6!J7Thg!V~rKY
zC0~6m_3Y}*wWA@p4YG|t5U=|^(Bpt`KXWNSH@D=kysxz9WUXhYzXF$0MLHTk82e~1
zV+hRL>H4RAgD20=AM7!w@kHT7)z`5npS~tPGiy^`%n-a^aOC_TK>PG<);^&Gm+>|E
zO8$i5iA&oVhfnYhfBiyv-fP^zciUq^;V%E)k#wwoaOk-Pm%p0-%646J{n-T2zl9>}
zh0X#H*7BF@>5I0DS(aJXuF@T^gOi6cww`VF1m<ngmIc>yDV<B(MTu4A`2fu$zaBCD
z;0N_yo~Q#8UzbVO8PR9Tk#Pxp%5R$&sd)w;vfwy;B;_+K`Ziwdkx*ZF`2{>V?)8~}
zbip9GIF6sj`Dkvs?uB_Q98|8kc3;U4?>x&~i(9Lj`sp`JT}dP?U01@xEZtYoVbaQ<
zQIo7^&8DtNFHs9=JjWi*J{E0tqGp>Xd-Lqa51Q*D2w&>7Hct+YX)hKBwKtQ!?}QO_
zc4E4&{@4Lo1Xi33cU@`i%vl7cc%@AJ{B*)$5m@h4Kh@Uj7c<53WA54U!ci;Nv8bPD
z1mUE4=M#aaHB*IoL1|(5S*B}3Tlq2tJB>`an|s=n>&Z{O{WHaLmPZ$u%a~7u)T@H7
zE0dqURkn?^scp7x1{!Vho$SzF1mb_HRtElIAer+vMJB1aLDpA_*T;8oU08Mh$TvHN
z$LHK>s~WI><kL267EZVcyArJoeC`&ye2;`AY>jjGqFpp@O$0CEUgL5=Gt1_4|2FL`
z$JzZJ+DO`q6WUq6V-6~{hZp2jYE&2GG?LGcIjApHHZ@<QJUtEs?K)P<)cysiY-@a1
zI~B--qb)CT%F;C36(wv_ht|qAZ#NSHcudVR0?0pk^k8>>Tm>db63S10Dl}*3eSUTL
zwdg30Z|tGN!;5GwSXN(_Vpr>uo|&EN-owgAm#MEhB~!)?Buh@kP6A^$F2|qm#nZU*
zTxt3H+g85n3_qcg*jSifT!?@v*0siIDJ$(KP$egXCEB$A*@Q4?_9OGnlcBXm%MWF?
zt$lA;O&82?eFeNs=V%d=z5hz|++9DxO`2p;?co}7$96GAT+tbhgZzY`6)zX}A{HEN
z+<spRA37MOMC@elFh|V3Hu|E*81d%D9`v`Mn-+lkB=<-tnCKsx3BKh1W2mfs_s>`5
zzp?(tD%bhG!p{12iSPUM*R^))UleLYw786E3n`uNhONCMMw@%&OePe8x@{~UNdIun
z^e=<=W}l=Py$ugVZ&WJWW+s*76z6)W3h{i0!lkz}qJ3`c+1)(2xrn|^bDJidmyDYR
z^vLjOBXP){_VD)mXoKG@)X7T7N@zfohOFlbf03d^Z@PxJQa>zTXve;<lV7;k%zEzf
z7YKdw+hQ%F(k-2A@M{{tO=KbSLoWGtl9X)E*NoHc7w=ExW$ya_(a2gM3$cAyfGca~
zMbEvT%l7-tPwwRQarl+|Uwm>Wce)&(x&7hx`taRfUvOFNPtcw3JF^vkQ<Rf=;Lq+W
z<feCM_*V*UuiYI@`JOVH<0gl^<}Hm+8D!}+Qk1V)eWl$@4_$9s5bj;_?n<EB9$X@D
z3wN$E1Q*UE+RiQk3m@LSKb_+~Fo0d$z6d9LH#_3FPxFazb;-7HqeG`M@J?WzmzLY-
zso~4Hd6qkY+{dB2lYTot$`2JjQ0&F3TuHkMJ*K`$Z5swML`D$4FRVG=6$!iks~)y+
z)2}Ho^Tf78+d}5x#3zvXvVqtQY~H=YuRGvQp!|vX9(;?(^pgdG?9;-H+>+0y!iN2n
zZBoZH7iU@iFF3|Hs2*O_1-npQ+{(gs2fU=Bx`4^bTeJl}e|8)p>lH?LpY`72=a5$F
z)K6`kqDA26Qyw8Mh=E<<Dcmb`o8p4?Eo)crfGo9z%%kuyLcdnxR5_V^cYykH_G3rc
zS_>IwB<01CMdCM#4cYi9&HsnB_ke2RUDw4`M3gGMgEWyQ(mRMWrGr%IH7HGb2}S80
z0cp~kfb`x$dJBXO5<&|QY61iZotypJ`+v^<pL6fJ`<#2$de$@VJeka_%zX2GllOb)
zeM5fq2dI?j?z79it68D=M0q7c5KDF?gC~W#^&*p5mCBjG(K&WCnt-Yayf=Y=@(AAe
z+)g}SlL#ETDD%GkhPu<(Boe!G{2VyslFob5Iguh$uOd3icqw20CP0s&>)VV+-wBa6
za-H_NV|71KlB2B9>zy-4F>6<0)dDY>y?SF?=Z4SEP4~BAL}UJTKLoGyS~Nf@deYbX
zONLWnN`WX$bl*aOTOg|W<RWH8HG|6}?R293PqtsF&d4Wc#EYb`J3mmcjrM+L%`iWQ
zPhj}A=)21;+F{=1uhB($+6`njh$P>4Y*SD~K(^p(nk@vH!fcNn5zy%#E|{qcP6zf+
zC~<yk=jm#$Ql;@WQ;I$hSW0AbYEx@{PqQ|jiN5?gC4~U7OBbth-XZq93n5()Fo}`o
zWda#Rd^f5Nr%yw3JD{p_>X}!SW~&NkqMr<{h*P0pGmKJ(H>n3Ep_uwE7NLKra#Pr?
z9eR}(UC5|Hj81VV?Glv#<qi;AcZ7ipId=d=U?1N&01;G)Xo}^8O6r|Vv6=L3MoXQP
znZ#*auGNl1YZyZj`}W66?3<|U;?!+j-`-MQOn_4mJHwBw=BkLs=^b|tHB9D$hc`b=
zy?*q=Z9OJVXYzBVtTZHV`(TEE9X4NRsZ0jN1c`VAVF58sF^@ahf%oOk=h(nRJCID9
z0A0l~FKNYD6-n&neAL{zNW{Q(hJyV~lwI8liQ|zorQ<1*MC}qC)p&u9ZoDG$2($0G
z1<P|?4=S+SzRyp-70B1Ut;?Uibwk+0%%&M5QEnlksGjxxhzL|}6sk)x>Rp4j@vo%a
zqS7h3DZw3!kF6)PJH$I$79)d&=~J*N?wuze8&3)amHd)lr&dkfxZNH!5$(HPb=@BM
z6c(4jak7BZ0k>+WOSKB?<dA2kx@y{QKBasp)Z^f2cy}<RQIvoQgsc}-ylfHFy9_nZ
zLL`eD;PIn7XFF~kn;zXp8U->rfyv8);`IX>y>;PH4f`u+H4^=>ClTc3ugg_sYmUjH
z$cx^V(=*lBrbIN<=#&Rz^>>W)Q475-R}Ai_5s)uulk3M72O09*;rNB#P0A#hU8V~f
zUM34FTsEX#Ed7ybf?o^IU9G&@Qic^>6+M~4nv&m<{g`;7a#UkF<==E(qLleZ{jXr1
zOWMoF{{Jz&WvnWyWl9K4?%a6Z!G)mT%-YD>IXJ02b~<)CMVvAmWuKa!*<9fI^BvL7
zU6&i)%H1a2R@D{*sz9CD0_F4TruM#$I}IK4ou*2_tQ`*~-ZYUHRZ`9_%ZPS4A9f(%
z^yR)(vzIQ?8hO-FjLx118X`|Sc;Pt5I9r3qN?RHrOs0wPm4q&tJBQm%X+wY9D}2QC
z0>B|h!Qb;#jLPnbDn)=aWwWQzvZIxgksBlhaz-YPw}@v;vEL<icXrXl+a*PxNoGtb
zN!<RlebP%4^O%v+N$+2Lng#LtxZ>gOg_eS%71wfm&U(^A?Qy**vbo#mc&p6bbzxo;
zxlugLm~po48V@MDblh!fSXmBGy39g&RjxGTx92D3TPPgmYbhi}*;05=RB$fp)Hm2U
zPbTC~E5M^FPr-X;Q-KC|-gjCz?58<@y6WzJ-DX@mA9OX{CEONY<?IFWd}j}!r+Ka_
zr2P1!ZHYj=vVonwo%8nFZTD^C?GG-dE|KR1T&9x0ytR)&>*MRX{TY2oePDDvS<Xvo
zeZLCUs=`8RgLm!LI>UvD>1<hSWy-?I4m^L1Tnjhchg%Zuv5p^o$EOm0CT%|R<sFtS
z;Wl0Mr{6#C8{zEJf42U;b07Z5m}`uShl5^^hL>Jfywu(HBVgy(lv<II3Oa>>L(0Ur
z@???T$LsqN-+tUVeE}lPeGnue?n7XG+YxL4c~nk;GM0b;!Zey;kRMAOpy=_|cB$^@
zCzv>FXLibCnRrLM3+Xq1fyLf7P6;{?M_%Xe`At4A)kmnIgyNUnfsGq{ab8)0+wF<I
zN6L7|5mJm<Loq<5h<IS<o${T1>)y3FOwH{Ge8(4kfd+@6YQ_-fhPKxr$f>;_g>5#Q
zUJG+gBEj&|aiHl~j1m@NVLcA7#p`W*hENo_U%B^z265H)pDDkOHTA|HSRB7Kz74B4
zS>!oLB7CP*lr%-X!?hE1^(PBq*8<A}od^0rYcQ!>+F-_BOR3cHo0x2oS2eK+Z+?N>
zl~9D}GX4DDl%rgUIJZF|gtwr;ZSvLhZ8Gr6jK^)T<9a5zuT3}HVDo2W!>7s_4xVJa
zcYB3uiOi14p31-?tSRE1X7>-5+T!dcBxOnSNtn#r%96p7y^_QlOVjJrn>(Mo@~`kS
z?Z7d2<Nl9sp|>FKDgQ$D)K=Ig=p3ok40H9mW){e%*@#2jXk?AW1RgMeyF8J1^Jaj7
z=?}Kofj?~qz)<j=pNZ`?ks+daf<E46K%jSN^2QgiRE1_7Y=(`4&O@)xyVBrs#r&|q
zs213BulC7Phim?>J?a~g;B>f~ZCrD|VQNe2mEG-@uWfs^u)uA_)%2ZXfkbQkmUB}J
zOxCMCg_>7!$>qDm%Zs(Wo&2koF1$7vJ_2^_DP-VXrM&QxLtenN9jQ)<v`W8fhEF1w
zkZv4V)OSvW64~IGR4CvM2}3kX2$;IWPa*M^Tuv)Y>$<$UE_KmqH{CbqjOwmP@sA1h
zsvmeNQiWB1)T=GB`E$~LmrhcDo1+3KLQUE1w6c#TAvsRI`#u7O0e?xJW)}it0PTQU
zKr0{xkPS!xqyriN9e_F|lmlx2*l$;C`vT<FgKB}7!`tDt@K%x03?$D<iZ2c@99Y(V
zx?DIf#ar1@wItIj(|!6i{fLny{V42;G$2VV(ex<F^2B;vqDsWgy2DUTpdj##EofY_
zZaLE=olgW60|eTbvM;xDdr4+d0|Db2&bPln3jkkRd{zONV|v;B<sb(yQ0B@qM4+r#
zBuy;1-CqUDSLf=Dmufu_kUn46^kRix!+PL0U3X#c8mJ23W<bQH@>>lrgG8U9E>BZz
zvqg~f2y_dJTbMUazz=GqF)R+wk2$j!GOmG@vgzbgz|<?rrA_Ja?sT`_D_Dty?HoDs
zDf;3{01c<zU6wvkv~8ED(*}mym>MqUsO}!Oo)R)HY<lbwfDeSt<{Ud)MuE8^?WmuS
z{&waW4+iSfVEz22DJdLIs9SC=WWGf5v=>~uh=@x+oiu_D`(O8<nJmupv=?r?7wH9%
zbju|`$pRik^Wj_$C3HOw;Zim1HW(r?j=YqdaoD*`vnO0xPd=#NaZ^I?mwE(7EtZ+Y
zziDT9XTA02=~1Z&6afM(xwoBPpMx^CO!@BG_u8Ed=6zHEn6!G|X3FN(WX7o0$g7l=
zU=TR#^8gqfM?h8P_HwqNeuqp>0`*`k;E0zWiChLk^{te)pxwZnt6yy^H<zSmo(YNP
zLs*DCz<OL|{C>AL8hFc(8sE*L+q<MwU0!kwDBlAMUPR4sT~R1q>W3nzyp+(~*RzCP
z?P022K>7ENJf-xAq^1t`$r!K3(m>7i+yYLEUeoY%He{QPc2#>u=Kv0+^N(nVjO5Dc
z{-r2N+GV<~8sb0G26p!s%-L_7^+8icL-|nBJ5YF~(^ccr`ab2#T_E*$YNF<N_%{)O
zTco}KtVYZvFnc=q78{9JzT1#4FtgR!x&b2=edbKu?xL?ukCNNAZss3&xzG1iLFbR}
z_9|`ec-G@6TO}pdXT3~^V*;mNp6>cjqs~R}((eS~QO-+3XF*pVx>hSo1NXA~DWT}f
zXzB*vKzJobm)rctihnXSug(6!O<N73S#3AjZMvX^ZeKVDTrf%@qY(LO_Z0_o3w*-{
z4MicLfc2;Z>Of@Wx;~}NfDHciU}q2G&lcDb=v)a6=s-xP-o2Wo*Kn6YIn}$%pq!eK
zAd!?h#cKiZCc*rD5yG~DE9q;s-}F%Uc}5GOd5Ru-iq61_kv`HDu(DM+@}cnZ$&>~+
zGPWz7ONL|4l$8Inv6ugg-Lo`-rbke|oj4V!OR9uz2m-a)V%0+rf7ekfsZF?o28!7_
z8EwX;!{DQde;b(63)WF>GNFO2@vo3S3+9iZNX~Sist2Z%J};Fp1;zZqg1W?Dda!4}
zE(zPr)lurXP4fLwOuA~(E8iBgym<$wC%3CdOS@jhAb_gZpa-HEOb;DQ(_fD}K!^^~
zi?qR*yxfs15*u+m2+>h`kyaQ0k>=BJaXh-@GQ+b1@xMU0r6Z-oFMvyYR!_`w9!Mj@
ztC-DlVt)GFM-#6!iVIL!k9)2hU?ZAaAyFG`H=`f}I>h?Jm3yK3TB)c;K`Z$cdPGe-
z>`-lh1oic+6KV~*Wz{+c@W`mz5nh>e%)UU=m@rJgM)N^;vgy4B0=#o1B$jHX>649?
z2Bjzwpz?&y+TTRT_rf6h!8X|X-&FmPCAXsebs{9H;ETk-lFK3wqOOk~(}kD*?bE79
z1fGK~GVS1J=oqRE=}OsfXBS2<`qr`udQubXwKjX-`HQC&qrf&~cWot#Lvj9MX4(W!
zWP%V6JbyiZaq@ZoqQJ)l9<PQFmYMUAE~|(5>CRt}TD6Yn?C*;Qe$t=6n5Jy)6yDN6
z3d=w|I?a9O!DgQu_uAcbDHX1=r=3XhyfH-yU=8S->x4>F(eO)((+<g!JwJty^A{u6
zPN+Q-cvXn=<?Z@WJ3n^9Eew?o-9oipQ>+4QJ~mzaazc4Pw=$fjzNJ-h?g%^Y2<J>X
zcK(F;={H^MRHF2YoKQ@EokF;0hI9L{(zst>)5W|Ava2;0BDv@&T?FwnY`U0pLRp#Q
zbj|9wj+>3P?)bTEwLrIg?m!23i#}&EcQ=KB4%w%@7eBn`FZKl50&W-8pj*m+ea!^A
zb@gr1%PjEVYb8n~2y>{mv3akIoP*2Ld4dCBBCm|Wwy~tY$uxG*J|~pF3G!}h^{?xy
z3*9<}Zb3WmGOSuF0nTwq@fFePy(8$%dGCeVyk>wXBg9d<1>&dI<O68B7;!?yLbr_C
z#?YP_j61?IP{&)3ri<iClviEr7+%{Lj#q}hM+SS_*q~Pi=2Yj*J9d^s{QR3*Fg<%2
z<l4OH;>Zcb+d9VUo?(VLQs%rP!>%ynl;iTj#ljM1G3khC7S+hSkSlUozu|ml>ZZar
zOnVlWWP12%Igq!=A9=Byq;5SnnphMFzbo5MW-wd!_aXARm2_5cj)#8^kPXOa61q#h
zFlq;%r7r`1qIoadCjbp-^WU^Xrwl~b(uY8#nM$^FTh^VE*4c26(H$UU!7`Lb#E}K+
z*vHct*Tc5rININ+<q)+%SZ8w4Eu5b-!)xIF2kPY4bqco0a2<72ygOKNG(&ft98l08
zowAx1^r9V2hG&sY_m@EfJkZAb*jQnHO$5A-WJZaOixrI%yHjFCqsa5ip9hI`1l(<#
z!j`Lj$i@~d%77*gge}w+GTt~!-{u5Zin@Y|rSTjeq+IMv>>=rZ@DT~3C7%v%$e-50
z)7onz$Mh;wJ)M-#O>syOc-wb1ck#m*6xhTFxqJ?7JVns2IN~fFR4<G#`Fk&XsByd)
z-pzU8#YkZy)xMvN$;rMTuDDMOnLM_!G$L0IVUGwTSsNyo<E)f05+&w{j3I;650wus
zjeJ{R*3IZ|?D(W{+5n>9sStbL#=XqYWzePWkU_g8vj0)^kIt$Sn_6%Nb7Zn5<eMmj
z#5rr+lgV&En4_hW2MopScSxif<fnxQ>pJ*2mMwzs>NkqZl#mP^K-C*CQG@Bwl2MG6
z0Q$1u79P;GAnr8WECdr?$?!+=Hy)rFY$be<e}Gky+51$SjRSG-=>dqcE@a8V%lH*`
zM8nPP8kz`6#Yy9J)|b*8ICDdalz};r);`C#D$9ALeEnX=;yUCb=|D6@No@i3`ub}h
z)?mM<%etjY7q<&-ld7bU#dR<bQQXDmnHfQL?bVtXk(YG)e&k1u{dD>)sUwKX*{?rk
z+1zO&z~#gXc6eZo`D##KkQUwmZ(5`I!2_G_ZfqsW%nygNL8Evm3W}F>^{?6ww|k<&
zwlWfkKOEq3pE+;OK)^dp-n`cFo2>b4$mx=Pv@)d!_m57yS>}U_c6bt)E1LZ!!nmAg
zx#@gi-JW-&>#4uRFdndf>Zu98%P@!ymEvHKXzIG!Urt%TTj{6eb2Lp^#XV+1V<sN3
zlTuV{%IWj*QpLzrypg-w;js4ID8);O6W6)X0@LO5<KfMV(I!fYThg-GF{9L3+lxq~
z2!P%&0CvSw7j(^1B~^CCRk^pv>h^QRb@sw@v*qJnt7kdY_03i}As6$CbGk>jq1+XG
zS?oMc#gaa*A(mX`oh^Z<V$Jf|%FDTVuA9RA(NLC7BY}Q@IT%v<_ob16_vTf@w0}y9
zXbwvws3YYhsS|kCr<B!@b~TU*xoEz^kE$|y(Ya?)^GPL?uX8b?Cw5(eQXIYMZ@Iy<
z%qV^yu+l~3hgM(p%VMm&MJ(n(Z2EK7D$mRU+r}l#!gD?lU+H(6Jn26g8mHq0IF6Ld
zq@VJ*(Par~m46x6k~lorJ%<vL+b_MgSLnHjLB=0JCG=SJSo>(;OJ#CPjUC)B=s3n~
zQcL=nrTYA3%d8F`lbf|4yOm49Vj28p+jGwI8UPbYM&cEZ{*qdUqXc@arunM2K<}M;
z&=pmIH<(6LtNpziR~8D|7JpSqvdf)yb|ay=RqnnFX+{ge8P?rKmEodIhr}+ta9G}W
z5AjNNDHdfEB(caX6AZ|S54e-|MM;#R47}&B&-_tWUgKixlODjF{bO~p9{<41Q6Nja
z>5}y14PyOjrLCjhC6}2&BNedXGnWbXR#@NC-){oDY$b0?W~2*jBCu@e*S#YOb|gu$
zno^B7y#W$~TR-(r2WtI}>ROT2bS5=jmNUNvxD;)K;S!=Ss6=ML`o7J$Ai$V!m%S{!
zV(dD}C!Dr1#j7Yo7*78Zg&4Sk1;Ph_yJ`?3<XZdma(fH1dBsuY8h`oYoh~i1|8D&N
z;<X>>uy?B}2Ju3|?uG^=uDZPCXzzL|uIhrdoE8JluPstBdus>N?F2&4daJI%GOdAs
zQhc)M+fI@`6vrDSX6jJ6&A=QgC^O^h)x8RP_j{Vz;=V3H`kp^*=+=6_RnRV=Hs&x6
zk6At#!j+44q>YZJlZ#bLX)yil&Mb(ku*~F9Ie#8-N3HZ~9F(ly(U!wThM6u1^5}y@
zkxmhCQDGAF<{Wpi&Bgk%VcgHYPc{3uq6qOFC&<MRzmf^4afQ)qjtwnb^Q5Js1zpV|
zD2?RSBc)ZBh=TX|(`Wf38-PtsYMa#Q8<LbnbYMx+is=iVK9+IGskl5pN4P|mN2lJ_
zo+ps!b~R$zk0GXH1jJee7d|qANUb;ZH_xyVB>m{8NKsTlzazhH3WH4rPqAos2+Don
ziA|h)YgEKu)G;N^2jOiLDP);?_c6;|*@0t6=Ixz=vdW#Vp8`bSx4>(01od`{(j^y|
z3Jfl~i*FXWAD_Q?*6F3MtMAcTmJWFOSU~+nK7(xkePVXHqh~MV6~ts;zqZ8>metbg
z{`yW+^Qjiuw}`0M5AUbrvlf#6K)inQCaG{o=h0M_?MOf%bnD!AyaU~`BH_1!&V&Oz
z=Bw?i?mhr38r+_d{b6X7VtUZX)L7ha2>A^8Z1E?%A@=EJ<78vadZuHdV`;>K^j2Vn
z1J}8kJ*4=$D)xX2GT+GMAmOOwaIjEyR)4DL%OL{s<?KjaZp`=&N$zaSNN!6GXf*nM
zs~l*=X!GUx%Yoh|(<T#yexzUo)+mw8p4{CSFrsNwa$t%n#Ihv(nmVuDyiJ3;G^SoE
zmzB%Pk%*J@`*7pn_tFtb$Vzh4cP~elWb6@3h@DMoEl4<l{@AN=Soufoys-YC;*G_W
z7p6r+XGPk-G8>9GHkCsUaEg>mYi<fN^<OSdk(c5^Ug~P;LY!tbp_swVzainkt08i+
zFQruYz0sfA8Tp1_9{qzt&qklw%1@Z5myQn|1D<aV^3JL^%jV0Z9I-#~o<29qTQoYb
z!YgSiZGuG2O3X+&6z!Vqnl$DvY8(J0%A^aW9q>vuN`f6Xcb}g67&VB0ptma1WiNS8
zme+|Xzp}lHNylhe5<SZnB?rxQ(#+gN@1mnrZnSQ+_+~41o%$;n^x`>qX5O5ZPszrX
zXt#W*vp@ZwQUCmd$R^=|@PV++H({-eV#(5u3P&x)k1`*3Ml5;cB=Y_8>1Q8|a8}4C
zji5b?p{3VOA_qScEu77r3+WmGka#Y`GfCjr^#;m6(ceii+4%%U-T@;!bcUO98uVWj
z@9Um%7A-I|&c9$gL!F^U46hWf6xgi0$|1@8(1|?`;*PJ&uS;iXchtyBn<gN?er1=e
z<cgotp3=^8on)K>XB#hjFP}Ap-^Sej@J*7|50vx&5U7$<ML18njW+{7L7x)Mz)uw}
znNP9(BRk*tYnc^QX)EoOozCu3-QeBed6ajWYP>g_3!G>wdw*(nVm51d>3k_Iq$`sP
zFR9uabg#PnikSA_Rl0m9WoA-HxhLxpX<BNgol4uIIm1iPYgZNE=+5U`3XCy|fy_9-
z2w{Y?_DhaSWeg$+kw?GSW0hi+W|?76U{6l#j|z_pX<mg<_09?mpavcbS+mj(|FUVf
zR@EJi-5F3lt>uHH6>tpD4oIpAEDLYhx7PeN_$3w-9~<AGIDl&vI=65>V^Au@H%Db(
zZ#&>?l`*%p;7B*oN^PiEIoEqgtGgJh*x(`y9BQ_Hd+<bwQi;;Bx*!9le84f-5XZ1M
z9cLP6y7+34CvJK1^I%0Bq#i);C5o8H_QL<XR2BPKa@$*zc86-)+u$l3<}&!q@jHxT
z@ckmyASy0l(O_^i?r4!KZYOSM(OM~rMImE7?Z8_tV>b=%t&*{phV)j-*fCf&$Q|?a
zTRnfB0W;V)sO;D}pQ=#@PS-5gm;xa+-8Hfq$P(Ag>1CG?dW!=or5WN`3f72+8I7-G
zRVM0*NMarqpIHQ@PZ%2|PVnayHHznXyfJcAdvg_XwkQsVjWaFkkFx?2&$8S?+(H`v
zTo3_jQ?~quFA^L3#V`Q@SKVUcV(M4JVt>R8A-kD~%*va6zgaOA$W|u&TJfsCWxB--
zPt+~b=f|ex4!#{R+()0QVs3V_VPbjt^y{9$6|j=gc;`&RM9En9j90DK!9vE`)MnXA
zhWN?|=d9!+QA}Oq6?+=#>E)KS+pp!JOegjEj2~4$s`kb}B4cPf0?HqFr<GecTS~qn
zZZ$2+T_e{^*T!AL##R9ZD-KSAUGvCSfr3ptH)Hf$gg5t5lqkv@S+~>{v%sNisN^pq
zeyN{Ifr}uaj!S``V9<OL=)G;|ZNATV%x=;c-WJ=9ZrvQui6Q1j-L7g8YN{-5rFUw&
z4Qu<_mVO)87TOkio7a}y7JHk}R?(K!*$3^1D%{OTjY_GQ?PS9OOw2X|rf({5L$CbN
z;g`N>X0)Y$FfbjM-Z|W{)M0!#eiL~m;9m!9xKg<p^i}Tgy*%@c-4&WAnz1)Q;@-UN
z_~A==Qt+nf;JfrGQ;P{b>uy<aXsP<Q<WH^5>8*9|ZI5}L-jQkJ3{UqA1lou61QL}5
z+x+|-d3v0<z{2|{QQittx6TJ~%P%_cNq7sjvje^p+!!}q`lC<J6G$vPz(GQT{;>r4
z22?|M3=HCZPE~kDK<e1MoUj+%9DqG9!LJ7xP~O<t1i=eGAAJ-+IhJ&eNNR7ygPNK?
zu%?z2_j`PLeWDZHuluPKq#ax%BQ&s`9%K4KP?}?Rbuk*W#iF>#^E2vl2J~pc$eq&P
zJOo6-`#btDikpJerXlTNk_E16=*J$i=}j#@EYnc3v?ryKGL)v_BIXS3Pn^3UuNarV
zR;<6|JTYM&fq(dx-=_A3fPvWGA->1zP*n2%@VW)WIiH?_y-Xv@Xg04Wk1%|4UCkrK
zu56t6U{+^R&xj-bQ`xG3C}*qvpVhB)L!nlyp|DjfnT_rzlhEbYwtw(8w5|*-7Ule2
z2IKnZG(}&XBIul-LQgY9<5CPSsi^RHdsz+3H6GPZPAV$V`itkrc50nWigd?ovRqQ>
zM|lqDzA|<fNn919A|f@X0fmWuQ5<;V&8XJ{Sbu3HHOOC``+zeK_tQNBdT{S!@B7aq
zJ)gWed1uGG*l&f#cR7d&<m}%Q%IDC^P@MTm>}V3vC=uB>AJI4%*$9tlyuz$D0||~?
zD=rKDG;Z25)gMCNE^%9iunL(}>PAP@ebJm1=rb>+qKU7YUP@-CxozPLi)09-4!j4`
zu)PLS-Ps}-dKMV@&f+CKu&j7(_cvpjvW~LJPN|AAwMM9m?iaY*e6NX_3fA&{HKH3c
zm28-8UFZ}e7^LOP-_zP$gmYf6Rc{_+Mg^lB*tVs88EBiy5F?Q3;>$M<i<zEJ;f{Z$
zM+DKnAk}cPl8iliE>K5FUB@S&VpD(dDX-kt6K9r0&%U%-kzlT3AuPt1t>C%9?pTa3
zQGusrpHocASkj;J_V8-gZ=Yvv(nhTl4QvgcYumg9h0d=Lq~SRC7##|O!o5~=W1{2^
zC9Hp2h(1XFhONXzEBOt}RFtVm^vQ+hz2e-bQ5#GyG!Hb{Zr17c+G%>8ex->>gpRx2
zJTMMX`Aq#OJ^DLS#yulRE{amQi0WdS7V#LXMDF>xk#8vk3`1XyMIV`p5=tM+F=T!r
zp`KM{dJJHCXk#ubrt_Ljr(3M#(N_L!(D(5D*bOEaA+-?V>($zQsu$6*?4pE0Ova43
zz2?pM)b9@I+WQ)g=-7YDOKW^BeHDwWa?KobA#Cr4`+Q-H!KR~h^<$LYKq*x}rsyRZ
zFdM!AU$lpT_b%EKz>s^4)aOILl^#j+Uu)C&e2K^RvtDH>_ySOuWx_0VE@Pi%_NP4k
zKCIds<XWlw%9Bk;R%qoYi+IhT*UN9in?dn6-noi}{tT;Wi_Q^4jYI@hoG!1#O6Mlz
z#;+~@#YzDKvHlZU082h&!VWwCjr`A?p%c>d0On~8>&r-0nZLv(6V*b6$odxv6l_!Z
z@*lpxjV4iGVt)RnPd*~;F)`_yzl2YYnZM$~EMQHHdE3WOe&#%qMn((9{^?piHmBr>
zR45>SK;z#<Z~h>577S6|cu&T|nZ3v2=dZoFf{K~FN8<Iby?f(#wRGb1eaU7EN*EMo
zpZ*Hd6b#BICX3C@XC!AS*;Z1J;k<-#&9URxw<jg<=bj;Q&z!UbN*fGyn0~1luRNo$
zwOA`{?yNelz+PF*McT)FR>l9R{#=`#v@|JlW>|jLn%RRtK|K9!mTKW&vd^^I%!oP$
z<%UG|bG<)Kt8F!EY<tW9ys{St{UE5b?VXucEdO)QUikM9f@)i=a>HvLhFqsJ%dBk6
ztgSkAjT&{-EL@)Q)Q5^^OIrz|^*0#3mmn?8ikumj{{&!e5J*@|e|w->==ogxpJaQ!
z-yiU+DX_{Fi0pYmKTy?MlI1P;gkC1lq`vi6DePp^o+mNny8p?DxuJs8p6#{23hS*@
zUsw1!`sp3R`W@L(VAMGg>7B){84CvMGOt0vh>KTzjJc1VYu}NS21d?w^%=B}a@JSo
z%K$Yx<8U5*18XFJ+1DcPd#~eFcFNUb8bDFf@z4h$B}qzjc21lB(q@rmCp+NyKrCBo
zr0!2<M=)Ro_QzimC<FHOMsVcKR}^%)0SLW(n^Cvkf#lKYyfBuI->03%GN4oAO0-2`
zQ*&!%0>ZK|IL6)N`WAL1ePn&zMZ8u&OL^cRXD%4?HPwPHCj7}O;^m)HBJ~GkPRqwM
z1sXP)SVzlt$##`aq$0oC4g>SH-_8bPzN{fmZX-9bRB8wTX^!9rWlC^46=rLEYxB;h
zma+*qP=jAgu1j++JhcocY1W{pKz1TXPty!BxjcWQH`v-%r2j{gJ>zi0AlsoQ$qJ^?
z>N7Q#<dp4>D$HPqO73jE6ZyMj;(hF!z2B2GKbRxvGqv$9iCr!GpN(>0tv)oVquRQp
zIZ;D@KuA3r{aC1EQ)x|URm&TnA)GxVX?g4&a;wnGZK_Rdr#RCcA)#QE?NeAey+Ded
z<XEfmND6I4d}cGo*6$Vi%yaT(Z`F7EiO6f-W@4wHj5X)acqd`fpShMEHOZMZV<AG?
zR-LwS(60lVDIfjz|12YUkEloP)l-JBcnh)eFB%qX<w4+8Hv<CuRXhVcvmWtt+|IDm
zLjpfMT5}eMAf&lKVK=%u)X9;3&}0g5Mef<luz=U)5|9I`IS9x4{FJa8c^t!oMc7L$
z9>KJ)7dEWw$eY#YTupS=dtdZ%_^Q{?H?c(vQD(P&0-L;!CxW526LcS5s~DE>ezE!T
z=(6}Yrc*Cv?;poSigjhMK!0|og46kxz*_;lIV`mk%?}peNZ1iY)-G+|qt7FC4|~Z!
zxQz=f1aA}e1<7(#okO>W(X`ETO4)o)o9AiVUN34V@`4_DPITYHVf{jCY#v0rE9-A}
zZ(+~wVeI`j`h|nvPB@+t)sU~yIK2s)#d|2PSAjTxBPC|{FL4u3#N{ZrX5MGJEZu7w
zqEm9-?ro9Cm07~;Z9$5~@wz&)qHnMgEyz^YKj4Bw3}4Ywd=3yo2M*ut6@rh*SGvMD
z$3tx_f(WXG@@hcue#eFUJXU=Jw6qH&@Ng)x!n~QiyP!E3CN4Zva}@G-iP{Lu(82z3
zY%ZVR*Pj#kKjiT2o>XibLjL;I6Zgg6uy5m=<Z`)Nr9$Z|L&{b^H9x8hW%x{QOeD4T
zXd7FkNA0t~HG$LD<p~_8P{^w1HlEk-tk0B71UIV;+eGM|d(A|MaGX_H@5hgNdJiKc
z9f4#F!Gmj0sQTJ-Lb`g*y>Ydz(;c6Kg8sb1F%8y9!>j70eMPkV@Qk)Gw07W3+V37?
z&)-Lv^EA2^I=$b;)g*e|fJ3qJFrh>2a%|3AM|wYOvtHlxN1dSruPYl8>>XFSZQlkX
zE!bQ9D6etbEQt0){i_)Xf6IzKyvtU2Gz=J?3NFPu9lmbT#@S7}ab~jze6*H~jVVqz
z66DWT9GD*RrlHngf&G)%_*H5|apB=Vc8qt;I$B?GDBuu$P>nUUM!E2$ZB>7P0QgKU
z?QgA36)3k>FGBnh_}=c(SRQsg*~=Sx!=GJTa+eRJdACs7hUL5k&)0&zg^l`!945O~
zY24=0>&7!ZYU?|-vgbs)Z7Yjpxkqn)-^jQ+am@#YIr^;-g5CqNkM^75kvJ`$5in%t
z=$GEl5BWn&0Vt<4PjR4xRI1ycwVLGn%QV_6v5qvrpSo=(>1mTa_jzBjYQQ9Bb>HyB
zO_RVP!rUlU(s3rqMiJ903GzbA`98eivLkR@#a$EptEroWd~^?WnxL<Q8*9Xg+|!-Q
zZM{wK2;I>P8U5ciY=S&u!La8&J9fBZxnlKSQYLUe$kCc-6K?JNMQ=k0Cy2#m0o$CT
zbow<)Z8Vi%?Jv}eSDUlJcc8wGb3f80{J>zN>H-nTA$a%~|4NueHc%enB8eN{{l0d9
zFVm-U$p0?8=nqnS0V)3THLhFQlR9%@bXR|y;oVVrM;c6fz~m8Quj_f@(OkDo9mXrP
zCa08!$(;7%A(ICC!gewp|MxH1Pt@ZG#8wQ_jzH?6%68)|n6S8^!6%NEGN~~YC#{{F
zq2xbEk&^*8sB439jp#c%wmE0Ro=W_08f8SoQ1{~T1#n}t-t$Vm$|Tt$$|Zb%i!UH;
zL{j*7oK>dQW7%U?r~(62A=|B5a)a&x%6j7Bc{{dqub(&0GWMD4ICk~Z<#3`^x%0;q
z-IfLqR4l0d@JB7M{T}4>C>vnsbi=D@=7w^8lJRkq(-psW??<v%ha-BgdqFbgCn@*0
z81)ca=P8m!?PJR}CCy>i9t2(tuF@~D#@ScjdDCR47H1Y<hNe)LSHxSxuNp&Zcw!ta
z9Pq4+s31KH6a$U_b!ow)OLEiq9z#gD`7=rU_}>M`WR2lRYh%Y$43{R6S6YbpyNzo4
z#;RU~$B1T&EcJb>Rh|}70?&c7m4!}1$h^gsxPw{vfkcfzdn2;%ENh{Y6yhabJVG%3
z@fFtA?>$#6)Z%cvCx2BI$e#V*&EjTKB39T}>n*(yoWyi90%9Gthq?k_KihSi=cXQ-
zjt%0?!m1uFuyh6;N|EIqt){^hId@%BlUdOC=zjaZllOCKFe@zGS~4jHka(oZpZ#t?
zVEDf;;(BZSj(%WDc9{Q#61)Ays=|HV>~|Di1#d_=S=XYmO1_225Wc|bBR7zFx`#7&
z)9w)f4Y*X+u?xc$$$cZB)0~GW?$cN+!#dx+*D3y`iZFNJ^$b-64VISGvrqW)v0qCP
zLTKLo4-wx}p-1`uY5%PFmU%SMYTN;g(d<?(EZmuqq3`8Y1Q&y)ffLUu9bG5$h-n1Z
zcf%LDaIVnicMSV0!8a`nInn<{qmr)aN-t4EHViEwmQ<e&{&?f9gwYT0Qp|3RI?E{L
zU&JTE9?9|hIFX4V*r*6%#$xbpK^`0%F^0$A?8ER||M~-rxobgR=bw>p_3Rx!`bKNA
zp-9;>so><E@E=W|Nd;5)1WJ<)1<HRj`+c9RKBN@mP5Bdi)Dmt8yFcgsMTp^b(}Hvd
zo_>6-CssN1p1sKLMS^NiERYmvsrP@BQtBR!!b)x=aFLe+fPU@~N~xL`v3sG$Ro%3y
zhXZWwE|EY~%Y1joOT8#kl`5Me(VDZx)|~q{Vc{>=@>C4c!;(M#kJ59ezC<0rI>wcK
z{X_-Y>pDifYyfs909(G=`elk>)zz>nYC*%c+WOsovEjLsOeZ8Bc?N5{!I*kQmb#q(
zqf{G*GdO>=Qoa5bdIz7$F$^3k7r~=Evo&{q)M#t2|K8!#NV390(pM?!e-M+q4M{*2
zH<;`F2DQygm!r!1?+P_J^=@ZD{Q8O^v3J>&&=!__RW|0I-Nxw!?M!qdlGy=DDKDZ!
zjSM+?IY%+g;-(_{cFqI4KGbu9fg}$rW;L5~Re|cs-4|;rY~F4=DlDrt8!8-_#e?<-
zq!uKqVH~f>e|Ee3@Hv68Z9fzi4p};gRrs-vl6(4EM(}^N3&eiz;>oF}9&E_}KApgA
zRVa<?2dDE;?8pOz(F?rq=ryeKrzs;93r({{Ln|hncIG(r_@7@t5bef(-kirU6aHx8
zDUGa^-2=5eYQb>K$nrtf{$pNVXcz^}2Rple7?sQX)3g7_CnQDlLA*oen2^BN{4qhP
znBM$r%^`nG@X@RLre7mpJ$c?smWDfR-nzso$P8!Yv@KZYu&F6$P1zdZTrX6V45G~U
zW{Sdjx%$;0BrAVizC@H55s~XkmRz8d_L%(no6ty23+BJfpi8Zp`1}B}(}EI4g_{?<
zN?I~e|FYEe<&skK?!m6v>l?h1!274XxwqKAj6*mn^F|a(T#5h5oQchMBJ(IHp;dss
z*j3aLiE7pQ7o?FN8LIAsbC$S2##vk8QNAT6A&a3UCNBr_T*PULNq5+mS{N&$CtBa8
zkE6*9N8ano2Sf}J5nnJd%Y-n#goV3be~V+}Oh#`=>;2~YH_S~TH^Np9wFsq0x|Md$
zU(hoa!3x~{zQ@H+9chV6D-ZrZiJU!33g;z{8OhfQnEiA@;-e0=h`Ct%aG%t?c~k!F
z>HpP~Rv#SPITxj8EQZ0{{W9a?r;l93F%gG@V&|ebjPO+$onK~fyxXA*;lC)#^E2SD
zcHd)=4DSl;kKXhi4~LJhi{XI{y~lgpC~ifL?rhsBdw@(f((vW}X}pal@9Kv{DXZNi
zk_JIIqle~fF11*^Td;n=cB-Cerhlg2(f8Y_{=1|?VOo2b7@Er6ZoS5a$7|?4-1EPa
znA*vDRQ>~9cyloFZo-QE+P}xA9v^8-n~n^s{7YhIGa;|Sp*CwL&E4S}A=8pRykzfZ
zK{%FIKb2=H<e~pgk9QR{MS@z1XJT`m9(u5p(8@ypRY@mboo)C3M@7wvpwE#Q%rfR@
zOC(<y91-gE0l@J7>hHc?F|E)am6Zg>_Z{=->%--@@3Az)vAu~Edt|;4l2q7Fv_ATm
zs8431^<jldno9(AxB<4Tp6oZ>r`F^TVV8Gq*tu7M5q{#{Y-dTacjAjGhe}UwUvx9F
zonwlFeqW6zxz-AjQU2FO%~v5oOl0_Z=8v)EUQoU1eu^7rKp?9p_igs6wa`Pu|C@Qo
zSRVF_0e3y`zfR`u1Nwb;W<wc=x{u95hlH7G)$Se0*)dLwh72$X66U!)j+L{cdjoq)
z6F%`TO14&yY2_BEdIp{fhgI{1#4<VHTl{CK#j@tFF8A5;U)xN6F{Znn7m_O+i?2F)
zEGBfkQbFvC9zH4AS2c8eUZw_U$g(UFvMCbl|1Bdh!urbv7i4WFo$A%W#uc%Ti-@Zg
z<|-MVmGt1jRnly}<TZJZJ!vBAuKyHDF7JggkM6V@OP^hGMs(ulR|RdC{eR~A-E8HH
zMx)65nNArr&+MBD3CeyI%Km5dQW1?fM`qNwTyl_w@quvm{cWR|&i<q8rY}gw8YKhy
z;`;Ayqt<+_6b1JGObqh#!P~x1O^EXMWZk7ADsd)HpSAuMMAn}p5vBZ=zhcrjS^nLW
zLtDD@D*pG#vwuJH9}^|7OehA0q|KU0^7CtI6$IaVPP*JG8zWNclKow?T;rr!xG7)2
zZGI|m=~P*u7v-FEfWyCY0zX{5n|yuK_6ifrVG+5L8h*4uGXTBURr|nGCB8QN?F!zN
zH#{INywFSxq(0vZaTVQq6ZuwC*|5~Ycj<AKCV}y{<X_*gf88gv8%A`6b8A<n!e_ES
zV=cX4`NU{w_k8%<MG)wf*#p;*3;scuDd#vG*C4TAE8M~K*F=s#ACOP`Q5qy~J*W&E
z5_8RI2|=n@U|W?Zz{jen0$Cgq;UJ9n3O;q-nam=bo}M`xRPZ?lX?lnfBf`bJc}9^2
z&sC&o&UiZtCHrx|O-`gu&Wn9KK9SnV*H;AP3Qn3ucx{TInGGJ56|o_z-p_{T<d^v3
z>yBzR;Op|{?S9lb&EMtIkqZAcsCi2DNl~*7SEx+07MJaBL=G;nq$2Mvp;GMTCp*bo
z<s*{}3zGgDnUbC4=MrIe-2KGxsAe@jh9;shpPl5HQ{$#!Hl5*;>)@ZkD=?+n9MR;C
zv9ut=E6|}T>Up6Xrmg!zH}pS~N4Yu&qjGZIUt5tYmU2$YUVIqWY#dU1k*tnyDxcR-
z;;JXcp+o{m`mWuQxE-Kf`g2;E*O`4h;Jt2(((ESi7snvUf!HU~^pZwW-d|ap^2}Yq
zz7_3wvwEaAH<2xyy9cg6eT(Tnpo{B{XS+sqcg@9=)lwuZ0|TCv1w3az$XDJE^FMy*
zEEz1Lemro``Gw64t|GT}pX;19<J^?v{^PCzt2S#2jsCe&<dKjz^WyP|R<`8tq~dg=
zFD)%p-K1tj9fjfSUc*?D9%01+tC0heE>Y;s!Fk@c-E$hJLGg|-q}0Z{Y)<nOU>~{s
zT+4Y9FrvJpIwwM`Z#q1ZlgPxHaM0N2$F``Nd**X~byDi$h?w{C{T%u0bXqQPC8A35
z@{tiQh>6*l)rp^IF*7N%W)8R&A1#TsQ;c4-<ujlr(=TY2(L%_ZCq_*@0Y3LlP!j^?
z>dC|dRhHMB16BN~M>p@OEiyUtj&y_sa(<JB)-)HB-u^JI#WwOBRUN-f=01L_+MC25
z;ba&CjB$yN>~8nC?*+D1BkwQRWKZvby!WmpVSAa|hpqVH&67xyS&zM6G;F`ftCoI8
ze3aMzNy6-#IU(PfE8I(qaag&3uPVvPt&=SC>;*&DXxhUOpUf&(sPF1V=LItM41o$I
zMzO84<sHmqm5LUTJ&6taA-Ehbc(g3<D|5ehh*p6UFuNU3@C;FHRn8S!4#<5}L^
zOY9kC*^5tPDtujRq>f)4kICJL23MFczFU{W?kAO-Zj${}p~vJ+-?~~3T!W2put+YJ
zu@w{YwuZ3FyP4a4x;qRgT2p^(pHoRE(1t`ulrz)d9i0$Z=ZyXx-Z!>-mp1>vsm<i0
zz&<}}*(==os#T6GI^B11zgU%YErCLf`c^<8PknPQYz*0BH|l*e;~eHq-bhh)Rbgu>
z!jwc{ZPMYN|FmT&TUo-Yuan5d>8QRe8vfWI2JN+eLv(nHGeRi&gRpHw+J;Eig?B%x
zEHWs1L~9%v!Bdr4NS6vBXFO*jQvdx<Ok)^s@K_<n=ZDq3s62TP(}$_=&vL+TB8IqN
zcCsyg3Z-9^rS-eT(p8;CSlxibOQw2<NgE}-BMOx!L8GqW+M`<9p^mw)xdT7SXJmoJ
zeMUF{WiO>OTva7=X5kC>Xx^~cF<(8cz>1i=FTZ#1(;n?7E-?kiu?FD@b;+XVuKV}s
zhkY>D(eJ}S54v(9771NbmNp}pA8H#;04ExD_S?H1F4DCNhudKu7%nP(NzoWrTvAnO
z)8~Bx{|)X_y|||CgJWvF{(Gl{(kmS7)%@AzSEO|-wV2Yaa`Jc{RIH;c8}rT}>-3Lt
zK`zJ4WgE;~8(4Zn3i;NATKwTJ(yhkVF6|Hha)n9cr(e8m$H8k3B!*)q3Ojj2ZDQ&&
zkvXo$9D`{&-Jc9tR$g^|dtYK(2dcX0Wa#|rY!j%b8_2oD&HR~=STy{0mEhMBHwt+1
zqXj!)wX-4<GT;xnXvdlo>k3C+iFW0<5V<0rUXQoni{hupBx5F1Gp^!Yswm^!#&E2i
z^MQnAja@$4PJqp`;;3=UQ$q98Gm&UfCHx<Kxjv5~<mw(OZ>lGW3P#EaJnYLgBqY~-
z_oyW3aZZ72xDUh2!wdeWZqNCY^wJKVBbNHIjFKgmXq4JA<x|oy*zi1*`ntdN&~n0Y
zB+E%;2Il5(_xmDj;xUa|XXJ_YPKS<fRht;BVKw{jzR~6&AjG9ZiuL%GFq5S>G1j&X
zFs!O~PKTD91jSZC&lfR-TBG+)wPzgRD8Cl7{&o8gd=;}UyG3lqpq`*ihttZa0|{2T
zzBC*b`6;j_vOWLC))}q8Wd=L-<4w;^Bk%f>e1p#g#4Gb;DLcC-Bm#=M2_-k``vtNT
zVz4Ghn3LPq?IJ8}2&~u~t^3<YqyCIWao8qvTP9oA;Z8-~@<!Z-N8Vzp8|*uCF3I;X
z5`z<}IxU~CXx7AW(w1r)4Ly-@apJmG&Vr0JNb#rcr>kr(z8mK(aCOXkl)?wm{xwg5
z!SOteZD*>a?g)q|Df;Y{J@3WOZ+`EGK+(hV47R4~<7eOMq&AYIK(|J&-Ax-o&gq*9
zwigEF@H}67p&Yj9&Sy=U-Hn>vaoXLD)xx6&88$lA1?Au>gB+W`*sMmnD?f-{2!6b@
zhl!|2Xt6#uuJwIsUl;Sq^E(FkIVxdb8^-_zAxO{SbyUL%kINm8%PkL|iL%s@riNsn
zBZpAGTzLvfF)(6OsBe>I-IbumK)IZp#6Gm|15=HzvO_Y7erTUAlS@PRhYhBmXPRq`
zPv4tqt;K1Jxkknd^(k>2X}!g12^M`DZsKltwW0CC|Htk(1@0vUVK7SuoR}zFv*Dhu
zfR<2F+Ia%VpTq{8REpB{lo>&=3y+h~0)__uSi>A@U4;2uh4{4PQce?W{QE{+)>&WM
zjy<ch{bnc-kxo~;<5F9a3QAW~1TnMN=3Rc&k%?U_9{yrz{hOQLoPzpQG=5rWZSk<L
zp>+p0zX=8Pm<k0dq2JG%kJpepm^(%G5h}4eE(wDQ4E(Iw8UG9`c^)TZ@eip}TNmTk
zPP^15#+PrDjVe=HvoQV{QV|}(M8yts`&g$)w%0Qf9k91$vSJXN$!fHbz;ir=?_(V%
z$uGx{J<|6+-J3J1{Bt7yxA0>ABc115GDMj8!A(HTdY!?MVfi_?o*xC5bTm2UCI_20
zTp1il>$SztW_N!=*DRtAEuWW3Vv1P~a)Par;Wg|p^CaR<XFE37Tv*Du8^OMj<PG2d
zhEuM9?6F^B@n-Yu^Mcnu20lGmpJ%>qy`SUsyO`F1SW8cq%nUR@S!Z}(>zXekBA#SZ
zCGxmP{zBW2FXIJfO)KAzL#y+<opih@?Zii{Nk4`P;apwf59GwN@X4}>x6<*_AGedj
zF!WwtFo*pIxIl}BrYH~mC|^YR<RzOc*vgGY7?FY`sSz@$4t9p80SyAw9J0wOs`u$u
z9vJ9F*%TS*ebuGj`1&lx#@z5xoy6cif11fZma}5E?s3$~`~}*!IwKC_d>L+_pWpv{
z=g+{mC5DWqM0vJzfHLAxKkqr?9{wZ|j5*K}@G%l{9^G(EZ|4C)_<f9?JL91mRqIRM
zL~}0FC}N0iYwZ3q-Rju=`jYhni)DtbgZs-2s|V@rQjIeB)k>o8IwjfT%}<G!jmKy)
zep{pA=E0%nnw#$UqnI)`eGe!Drvch4&9@|20o?40Z9EK9mc2G|aQ5P>Ea*U#a(0GN
z$)p}}?Syrl)H9KFe#uh*{?xpfeYX3He5cn}4Qp(x%oyPF=(Zc3gax`X1<HYi(d3+o
zs;HWPtvG?ZrIo?G*k@f-tM`hpsmmDpf50beaOpMjVei~y4yrWr&B)!()5Z2}2!ZLn
zruEnJ{$BQWsMH%TX0(?jkLTL?6Li&vu>;t#*H%Rk5ReQiO%%(rQ3vb=1ic^MS4r0w
zLvaEaHbDiMm|`^u<z<uMHZC8e;W97<oxSM~@L4fj)*T0O`V1OQMou<a+&CL_-tijF
z1&^;B|9mT1CJqbK-Z&LEV;H>LSjgGF0GxHNW4!jX&d>p)rkmn)_LPq#Exai<t)F9T
zVl<l3D*}pd+M}`yh(y859|o&}H=0{zpe`XIGURup1ybqgcZh4^Dw}HFA)DK-+^K;s
z>u&}&hxs$?=i+)^;M_U(lG7(=*F7aDYDX+nP_EagLbrzIA*p2g*QlIo=JxW(ybNQ%
zJIxHpO&ug7W7%ttSWU-raYl<USQ)u#0<HCrQhSTRz@UU7s;mw6g<Cw&oW4=&qy0&m
z*_#r~RE!|ADuo!Ym%twXceDVE-<Ix*TAljSl@<idJ(^}g&3UEuCw?SA=d7TXG5O}j
zK3vV_#lDh>%<iSue0*zwo^Dz>@awM9$x{o9i)hV~Aj<9U<9NwV){HBh7kb<z7q&Iw
zkyAMaC+rl-wPDJJaz*8(SJW2YvWtSGrIq{fw0DAZT4^{<2yT48f1)f@il5RqIN8wp
zWkfJr5w@!*w?bcpjMM(}sl-9(gq|Xq=PlAg>*J>qK_Q(~nuOOpGGJ9b%{HD-p5;{%
zy+%Be%``-nae(B9zx*2(LsVU3@hxOIyh3Ma75w?}febEE$RpfX7j*&keL&@88n%JM
zKw!|*7-&3+nt_JM$P2iYO!6jSHW!)N1w~ya&0bker?}I_Q{PYvemHN6zLk&1(ynTp
z;b*ezZ#V|wHnRqLu{N{$QqB@FofaojVV#4wtpac;(=y3x$Sdc^hhe{S+K$GKa?Y_Q
zgku^9CxowgB~GmT&;x<ER4b(g2Yky6uOU`}&<Z@-lyC+1*|Fm1u58dmg(mAs9z)O$
z&ejRmr_h}=<()K3851tK;yQOl3WnwooH^Ln(|s1&n)sNTogsty_sa9{N7@5&+c=8;
z4H+Co85}m!G84n!r}_;r`x1}R{ySPDwJly{AiYsy%T$}OaBqmuvS&mSJqdk_FD^7H
z9p<v-ohiZMA=7)C!_b;AUP<KQ&n{k`&~N8`pMdvzr)Vrw1$Lzu2idMabGa^?k2`|m
z-JL8yL2#_zzVW#>YhS>h#nr61hoN8hig44s0-)eRT+PCJ3b>jD_k{kL^6#<XYUbS|
z|2xTZ?Mr@*Wv@PZD4b$dfJ0kX!$(V7x1(dFl^QGc$30oLb>vxNW^P@Kg1K;`wUvr+
zmi1GK+8P#G33c<{Ck{gcVGa&Mad$i;al4-<wYbSyHu#Sov_GyI(zR^$GXs6mXTr99
zlVHrLE_d%&GrZmS#mnCc%@0#I-x&Qb+TH>xj%Mxm4M7tuxVr^+w*(Dt!5xB=;O+#s
z2@qT+I0O%_gF6haK?ipoWROGNcklh}{oU{0b=Fz;to84zr=ISvndw<QQ&s(Ys`%4v
z4luO4G#z;j;O8VT8!;-vpL_9_!6fVSjYN+~4euOw;TyU>I|^Th3a=?Qq8^9&J7Qjj
z`<TA?jeOk=e@ZEW0Kabf0e|$f@D_W$;koQmWfcju!)TttWBzZBWE10afv>SXBJe%Z
zDrPrUhgLa$zJav^Wy%7{V1awHy|7_@7TeOwAGGA{x05Bw-x^4G=YDO%zY+4bxcty!
zLQ_l=3<^|`T;~V|6h$?T#~02B4L33Jm|YXaiI;O2es^5!n?@MeqJ^3|=TsxizJps;
zd1mCe^FCH^1*?wL*|y7WN`zB$ll}GVVHcOoH7X9lF&I_RQBt%R6a5DjPjH`O^zZdu
z^zPex>iz{%&}O6Z<1WhZ2tuE{wPL`1j5RH0bl*ED&R>rxD#p>9yOSL8{srUw6aHCe
zB&5=Q)5IL{8&B$3kyFi|n!fW>>PrpNW&>HCN}BXJtkHvrZMVgx^D4e)fYoDNRObci
zy5G$Uu@Ha>7E4%?NW*Kf#Dmkj*Dy}6`D|ncN{ZJ40b%BxA&o{zc$qCMm<K|H-(DzN
z!?EUYyTZASPXz7i6kTt4;`ED=o`hPN5Tb?C60&N)5oC_Y#FH9(O>IRV&#lpKMCKFu
z!!0hwd@<tMqVQiYS9eNR_O)`&?r+lPFCc;nHBN%hlM=aAm6ksdhwm?8MEu1)yhG1S
zAsNK^FV$hEl_W{L8IwSn&$7n<E{XV20<X$^;wKf<fb~OD{8jw|B>`cX-`Bb?RkP@`
zO`NLa9NB9EC}ECZRYH1xV)ipXYQ^B^M@vSb&s1;K3K|dB_`o|F_*fkkl31`{#d>2r
zgzp_PJQ<oR$9Pa(ecFG?J+RKbLjaZP?aqSjSRV4hm%JmroXD^)3?ag`z<++RyR7Mv
zVjL1<lzmojAlwmWay>V1&3th=#i9r)q+<ZsQ-r3?q>`Bcs<HkzJLVA=oYb1r1TO1t
zp77h98K?NI=+B*qd8WlEV9p2S{=BKPU00DiEONte*}3%zH&0hGazh5Qr=d-+v|w$G
zQ`^@@N}Z*Q^#F^w&;Q$C7ME<3^0amZ!RU7*QdrjuLCGeS_FRz{fOApZF*TXNi6I3J
zy|_XvpLb+T43iC_KQML#)W|<F46^WQ%+Ih)NR1XAjGAg^GiTby8x&<161<A|vQHG(
zTfK_jb5>@ZuY`+UC&xil*zqwHY04C-^)(|0j%BC3V3;rGvt)#s_WvL3^E;JX(NJp@
zs=1LW{_lcP53bH5gfQK8TF?mPAH`G~<D$FaMX<I#Gb?f9hH(>>o1UV-DbwRM`gZv*
zylOMwKc@amQje)pkA%{XgatSXcdnGlmlj;IPXdqpyDl-zKUizOLLEiXz8~n=OzHj+
zW1pwmYU+y`Q;b$j1p!b3#44Ayl(AO_yz}x{95M9WNVT(=*_Ln5kZ%8wuGRNQglFjW
zxN=+QtpBw<r>&HqEKVBaKN*?|jO~4sKgmBC8qe(NXC(Gp*L50)!Zz*vr#P1?-(Eok
z^-b#?7L#QGU4G@+*hDwTr$6S{-!~_mPZmW-_$d}kaBmetau?SPVRHBD8w4@LOQ(u|
zkatpkb7-D;>L&CfFKgX$$`5!={91ILgCiTFua3;J*|zuo$0Uwzd)Mqg5^E#6{W*mf
z42=VrQQjd*>Qa1Beo+s{@!LbVztZIRxCbri7e;6^dLNIN5)D2jjE>wq{Z_>!mZKmG
z1YmT?BCqAapH9Ht?7r}IeIX|F;vep9JH=-)yvfHwnS6z?hY;-g^1V<HW!AfI%9J1e
z=^jj=`CGl>`E<{8Tq{DJ>0iIPe_+kiC`J0bIGTS~29)MMBs5s4{Hr9<exEkuznS}A
z$ldq>%^9-Gqj|^MY91HGEnd{ni#WGaJYRHuX$39^h5btDhq_`A{?%OWqu#V}^qrkr
z0PBA^KOLO?t=!Z$`&Zxp`pFsU2zD+GlrK(D7&x>W{CDk74g8yS_u4Kmjl8|tMcY!c
zR}@rE3W}~Lr+oJQFS<ViA}s4=*Eu~&vjYJI;qsd~*j~j_<V^AZ=cXxpe4mk-uutUC
zAzgh<%KX@01s*82%^}_7yh46;%7>Z<w#@qH(Hq&2L?%o1Ud5lOC6{pzWSVgvE~J!J
zYNJT%qey+F3#vrwGVi!%j@UJoh-f4~)-M&?=M~#Gs4d7;6Bz$!rv_;@3>we4s;MkX
zUkP{li$(i+*IO$mp{j3vyds3b#F?_P<mVV4h3UU$iYsiTy;b~~DVM}u;!LkOmOqsC
zQ81CoN`32J&Men&%0eF)$nq00CgqU#^1r%Hz8Bh~{7-is-Q?uI-CChZ&kgOGKY~^8
zKn-mUTPBNhm46l|GVSL_36=bh<{mfeono}uR4%x7_y5ggWs%fFu%&#xv;K$w?@0f_
zrIPnYfP5~W;t|Nglh=P2-Oc<TAuQ0{6t6uT78Ud=clIlH%F<ED(NWk~DZ6h=NuS6{
z^Dpq;9M<`!Oim)szk}0E{pg)Y77F;6h8)yymE7^gp4EnaZ3IUqIG1)}7-%re)-7u_
z4jAj0u7n72e()GiH4Fz}<WP_W4~}*B|EFYkI1<K8X|uXN2!+QBd3|I6>~E?);H9D@
ze&Sk|;#%$zXpVGp#d??rd+*VTxMGt(Ox-wqvMqE7K7oLeO48a>%nKFshEI2I68tK)
zE3rm*1w>p)$%Qa5$-=|i9Ep9_d7xcO3#bl7@Ml#ND`Wlwqq{VjhmlkB1UiSPEKo#z
z*vn|Y_vD5{dVkwrEJT)vJRvqjT-iaU&crbIVZu?X+3%eAMqy4I*_;e7+^anX%uh_J
zJ*wt~bzB9Mg-98EP@+XcELuk&E+8Py@!SKaU%;w)6`ex{7AOwB;W$q-C4-@=0u&EF
zYn(@jiopjpx-GPKrOV90w7Q{cUSG%c17z=8-xO7BktDH0rsd&_OgQJZ_Z3BUdJ=QB
zAr&^PhEsaY1vah<kiF#DNmiviedk|u*Z&8abo1J67I8HsZ)U?ZObM?TmYmzlIXEBx
z|8mD=kL)2eN*4-xcRTj^XP?llA$rEU&<H;Mp^aNvzPehI3-Mr*rT24YSm8T9DjXX!
zGzhnET+F>mUO}KrpXl_$u42upR#dQN${g#rh`)H{iH$TI<mwKerE=l*6HTzF6Ya*T
zh(8=$*)3u^d6wqtOHT%r>$m#<#e5QX_uU4$`YQGMoNFy{oPA@J6Zzt!rC2A*a9l0Q
z{^dFPH$WRHqEr5tr#cz!i8}JI@C<NEkJnHvAAbn`GEC_sSEjd2du8%~pKXbCInshd
zRua~Pa;tWWep!laFS*zE35QD9=PG{AJIxq>yu4LYg=8#SyTFF340CP1572GahO=b3
zefK7%Ww^aMDz~EF60yRCk4)D;Tef^!{n#Ahe!}UFEcskO5nBznj)3RT<*pp^WV>m_
z?H*+#Q6`{v&6d_ow?@;Xil)eWV6)L<-*11&SW$6Sc$3d753nj=cGmgY>bD<-n=7h{
z;(8<i0$Qp@u2ITKH-3NBuHqFTpUsk(R4t*|UZ}Fd3e<oO77WQb<zW|6^J87jke{Qv
zwQ!V7idL-&uhaq_ihq(@RHo5@isYAw+VG=AKJF8_CFzwfCH~aWDoZxg{B~hwk#=+<
zk*FU^=E~6l_lLbpT?_M8HU5Hw{-fbCTI?GWe`M3CP%GTUnvy5#O4#iwMr(MOzD4r$
z9C8b|dkrN&g8p@8V-6foh|D-)`a6xkdFYV(ag0UDf8p-CuK@!%|NO&wj+FZkP;lfc
zziH0%cS#`@h`COqgAi>RDN<p;z|YwBgI$CvKz$`aZ0qwL%@Fc>(i<oDNW!HM28o{e
z?w)x%UUmK4*(&PXNmcONY%ziD!@hJ$X^L(1%<!*Dy<sm#eOu@vwo;0RO&AZ4?C02I
z)q}ZA^*MvO-gHKo?U%7RNPDDnDc?WYE1|!8pj|9C26uHcRY>j61Mh$LK6EfwI~uCs
z_`2wCF!&^ieKGad7`!BwUW<40&0`2tlKBT^RiXNaE>|JP4JqmU>6|#P6MC)-+;m`i
zIZAx_W&B<Lxk+lg%+|0ME5H{P_Z(Y+$^QZ5&)x5_`O1%zWlPw7-}scs$MtZcTDG6u
zk7kGO58h5;%DnT8hF6iLwv7G0`syo&0J;$T6AAGg3wYjm4AJAv43#eq{?qj-j%SGR
zR;3_*CuvOuAYskHs}18DSGbGKFm3()NilGN19>Gp=`?MGYu2SKK7-V7>s7zz<Vj;P
z#ElfWtJ~LKp4>wOe1&!TvbFcNAk+8{ZLNbzuyytfSkv-s4&2F`7}C`S^G%-k8r}Vi
zMb<e{o^46II{wrqtoz5jF!aR4?~pKQANwCk=$Cv#+W(;Xof8lI_gqB(87cDIIZdSs
zaBlm%`EQ>JU-_Qtzem#jUH88_hICc9$%DX=(#=BeSLa3E%8rA;5Sj9Mscp=kf*X40
z=XBK{6jO$K|8DkXrieko|1Nx(RrEtm@8g2mlYMnS{k*vTA&?ac{=eofpLbaQ_0T7B
zJ^03F_P+!hFF2G;`E@d4xtccG&aJOYqp%Smb`B7CbCoZNFDkY)`Z@1>6=5yg#_}V$
zt(*Ldpikr0;d*jSIBNADMIQlu5C2vg3se#RdAwFMu{V3r4E(8DR&PwqS`hYq>rn3b
zc%3owE;GOzGY6AuOq6F4Y0CqhH1DsS!ge3b+gbr)OR^3}c?8f2c-U?L>z#4*<6Q1j
z-T$WP&npEY&NZ&vRg;X9ixJHL8~6F!rPuEAv)+xWO5n^+nKXSTcVQH@;1ji|Poq{C
zdG6dKH)afI96v{+EWY<i?Y^Bk|E^lhw5mF{2bl);vhMSp#oR^j798WUj$g}OX$zGs
z=azcwph+DB9UdIHqBYbsIOKavsknlRT&xv<8UqW|PIM1l@9sj`Y$JEUjiA{F78uh?
ztwP1lBPQhJcTb&~E8dcn=os1BQvCc$!94(^@Eihq_qYR6Nx3xu?>8njh<y-k1qj|d
zZF~Q;K({){)%%jChXeuT-IP_GZBtK#IW+VK6wYV*2y;JE)Y6VJ2Hj+H=SLB{(V<F>
zv-tYvpsUYSBdQEhD<e<ZM|^j@q1>=r_lTAfrOS{lU*XP%iLTKGRNp1`=GRJ>c>fVR
zbk_Giw?rs}+<`ErukiC_knkS2#~{n++}%>8;6V<=!Y-av4DL0}4?)k@?b3pMHAU3N
z7<%ZpkaukXSV<A}GKQ}DE%;npfR_0mPmCM)zLa`Ry($yPdkkhUe@Y)@yM<pq(zORh
z(2H|dlKl>?n?J^nwNJ~<V^uH+=jt9`|Kf(?fsQ9RV|upA$^Vgz)uY#+IbKK?|7Ucs
z(mu8m_eu4stCdh1`XXy?(X75fxSpi6ezx_nkN5g$<nz!fQ*@j7BfZBm$nKYlUwRR6
z{gE~f?40=_#9|0?IY4y>xj4HS#KXu|4<(1Cs5Z6`dGJBT5RPjb^9*=!q(7;7zs36D
zklvADCYHrgv)3Z&*(OHB&n%XWjJbV^Yu+bh=0oEZDSA%_Jx!UXF*XDEMv9)(K?hRi
zVMZHSU!MtR2NBMVq%vF@F}=7l{L!baES1EX1QWD+rF<N5YUVUUL3bS~1C153?UJ_E
zxn7^Vrz0Q3)&>r!Lk))>&5E5>4+l*cVRbqd4q^GPu_%SIn)jKp5A7XAdz*<SFSY5T
zl10)wV%)N0PB-bYUAa>hQ*A}O;x*N1kMWAAUhG63qB>%+bz1!DrgUffy5+V%^(oq_
z$B{P@QbXEbb)DAXOFulbU)s}acE-Q4u7wNUjBSIo3o?mEf<|dvbX}C@w+xD-<Fkp)
z?dm9{wS8!uDmf9tx;Q3gbY9y12t0X?5>72r8*8$S!`jA&Jpi^w4n_EYR+idk*It(H
zbnXpZ$2xtECY3n)(KF_`??v|OFM29PoYEQe&U$RJt$T3-Aje1}w~8X?aYNA~!b6Eg
z5EZYDC$`QvEBxO-koP$W^viwfm6!;M(N>OgN+8ltAR<XPsqcT1&Psjq{axT(NGguD
zF|~HH81cZ@YPruWHG{jqOtfv-MWRrE2WWViEj;R?EaSoPs|yck%_uV<|JR`I+Qa)B
z7nBQPq{N7k`DJOTL89+$mdXW(>|bM?lZCu8tiL!=G9OXBO-#D`o92Fws3&SLS_Zw^
zwD?3p1Dn>avc(nzy%ER9k}lGH?_@XFO=ta)DFATNo52l=9yy`DXwk9qJG2^NAljnM
zdmH0S=VIUSmN!Oy_-*wn&xuKhMs)xn;@0q!KSA26^tMO*KTW4tLMn3H=TLqQ!%LjM
z@2gx2hcYlpCB4;x+KrlXGFcJ@ot0nYWQLkIvQslapba44r~07R4p0g&eq;EUitfhD
zmx0|JsW0VVR@>m7acRpeE&dtLm;P>nBm(&ekyMg&_=m*hR7<xKhn`3=;1BBEv%O=Y
z72n*bw!a}031ccWDPf6w;xU82Fw*zXu4!&b=X8h`_UQ|Fsm4?j88cDWvVfXgea&oA
zsol3y@$Nv2gmPA9PA`*nN3m&EX=SW9&ranhmTUXKRLTH)%9iOUo83Ht3~x%=_E`7x
zwAGJ?Y!#MH^wHd7H#N!LLDz;-NyA*>qL$^!l&;z3TNR|xgu34gDXl!sP&9`Uixj=l
z5s7`TI0CN&I_e7m1N+&mo_o>Eh(NxefKXa!^hH37>nqeQsby<u9dB3P+pRxWIRQ(4
z<7758wrJR^Ik|{VC3$)@$49YfF?1y7Taoa2EwG4YA5qKR9-0yX8J03&^$Y%<lBPhF
z=k|$5JWsk7VJ}jDs|#Fc-JvWvFp!cq)lkjEgeMcj1;DW_SM_8XYEiNNBIc18SuJb}
zaFpddiDuk_#F_QQlx&*Eyq<pG4_JQ?5<j~PfB<jWoIs8z0T4|4d+|&7+sgp8fL|j|
z7R%LVpmAaUE%6!M>8bPxgmT6UJE}}QW*NIt?$5hK6>Bc~6?G6j<O;V9AFB$tbv^C<
zph8{<dU?}gwz-wBnXS@IAGw6x7)<{xY_^q=PfLHS0pd%&Bka`9y+ee|-g6w+*5tNK
zR?XkrXWP??TY*$-nQ4Q;Dy6?Y7a<HEvygntIHIy%5;&WE5IG)nk=0nlz0-W!#9TjT
z{vBt8*D@!!?o&m1NZXh1^HU6|0V5L92LpA=1~7;XqEE&<4YNujmoJ@-<y8f|D-PW)
z6%h-)SMCN5;42J+lb)tAgOjeSiurK7n?gniAH?3pn#v_jl64=~_Vei$-u&-mpG7AX
zp9%&E<m0^o(dXAjy>>15)qDS`&+Ri+ItL)tOl^B2#H%qioM^5depR>^FNQ0eexwuc
zB1#of-|%zl7O>DitpRa=I+OBRF2hrM3gD;Lsl&f}&^M@B^g+3Pvb8^*cI&#S-1u6W
zB@KDf=j^i9HotnZ%sh4FpE!Nu(IVVRPL)0nP`&1L<kLKOvICt6)__L{zjC^4kBp?H
zai2I?t*jcSze%8VqmxTuZc3n)OW=`{NT7Yr4QwPnRD3g#Tam<(K;cA>TzES1hNjtk
zUzt8xd0M{EUG*BP0bc!@Gdj>+wF0`#-YWE=9`_(M1GIT8tv^>iO*ly!i7NjrhY@Gj
zB8$Yq8y)HG`7X<O)|D2Zy2-Bld3Tmdca&}o%P-HJ7K^UMlAhYm4T-ritj|;=`yIq}
zabE>%M+a&Tr+nSFouC=qjrY9#&`KIJ$2v-T89||!6ldg=r)~C$;c~qyI#7u=0ktyE
zgaEyTaK6cuAX*Lbbzt<}h$i*f>eVfQ-RpW1ghCQ@t$5UmQ>yuF@rU~7$!dg|-*{JP
zbsZft<}f_21`RyOxTH@bRu3p`b8!G{E*0F)KxS7|x@W8J7T+)4X`_-DMMi9Dzb+jK
zr9CrlSOQCth_IN;cqPWM#7S3yb~#egkVhn0MnzuUUJUC^r?ICyte@lyB2@~dH&BAZ
zzr}fiDL4TyL6_}6A9Vfwp~bpiK@?z{l#(5^$^2FO6Uh(EY!io)=%Ze&AWxIeA<Jy1
zMy`~1%_L@)mgJ4Ku||6X7W==gwK5n+0`fv08W+0{!4yLBS%<6-KfHe5kKYf$_AkM<
z;$gLO_gzv57WEclyDbR#3%kC{4w{z!;Xc}5vHk4@?<mZNgkV2!nYh0ZAFr!82YkIu
zY9g^X>{dYJ?i`Jx3Y}Wu-KKXD?!)ZENS)a_09uW46+r^%)Fac(Rva*br;8~LD#<6$
zfLj&ZbLrun!L#WUd1Q^4t=DX$GbSzZ4}Ea-ov9RZkk)jZx3JYK^P02bQ(Ifdt)hu*
zV20IN{6o%AkD+z(vWSewu1?z(_?&_t)JH0;wh9q(FL?4HUaDGk3k34|yPeQg&ep8@
z<R`Xy<fjQcKDoN|J52l5PyAN4Y66*xu4WEf)ixy?PMDH!<b4G!0J9dL!p@MPkqKJO
z2UoES(EwTh7%Ugg+j77A_J@gX->lZXgWWkG#oY<hdVW((>$a17DDqWj(hk&H$7L9A
z%jiSnSD!f0{lLv<oHDE0<TP;;(yZHVUP6#JAASkWj5=t;&*s4k9Bxeiy#7Pi8NsTK
z&Dh!FQ_meN>3%O|^yJ7eCgEf)s~r{!b$+^yy=4{A;T>fZ`w5PJ)D=47(N1F?E%%jv
z3cV*F9#pALK7Hb^KDa?U+lQKc_B`2XZ=?ca#%`YJc-=4XmLYE<8ZE<Jt`vb<f6mUS
z(A*(zUI$$h?OtsffChY{<+fWusZT|Ds&GEdsCPweJ98Na<4+{5mHx*dFn>ZnrH6t$
zD@3ulr&QmRP5PC?quB#8du3%e8RT)Ib>+|m%2j!x2fopLj6XH2Om|4n7%h*Trfx|R
z?dy{u?$2Ha+FD+4IulfRbYiTUGpB`@cNz1+2$sg2=h>imcKsNrFI#kX;l6kSJ=^9Z
z(Xkz{98ACVKDP!B;i@Y=F@02jGai4!j0Q#{&pVz)c!r2lk>dfX<<Igxqhhh_dTZ><
zZob~YlQ5)Xn}a{((pJAppuhcPRp7{&sTAKV*YJxVpZt01YUw8V3N!XW{ZENX+Aovd
z)vNi*`h`E}8|GAe%9sYvh}zfK{-j^ZH7uyJ1loMA!>})!RcpyUnh~<gS|HFPIHK1o
zcboZQ4yzNcH9CxddK{e`7P~j_g^*2!*>*2nFQOc&X%)rJW@D#9WBA^y)>+jt1_Sss
zGnj7drfO{@0{ILxsCXufCM;2v>iBD~Lo63TwE%<$Xo<Vthgn-5jYj1ZSLsISIk${)
zLw;BBb@#T&m5;jx{8RcU9(z>HlDnnCS19Y`qVfPNq}^WcNJpT5xPOr&=rP2I5p4oE
z3B(TDN4-SslC00E&*|b=;#i{T>TbupjUynxdg!^XJ#ED@K|nnrx`@5)B8CJy$=`f?
z(gK|lJ(c^L68uRppObaeNBsv0-apohKZ)IQv5WCf(s18!7fSrc!o2sm2}S*rL_a6e
z6X1TZ_Vj)FZQYyC{yX<$(f1`_3}Vigv4mJOmR!_PI}0CU_6Qd2t&MttecM%DIt42o
zp6WItC4?%&oCjJa9~Z1YE^z!53-*U!8uDG>yN@KaSnB-gQ7vks?X%!NQVmb&5`V}6
z!{>hFc{Dgg6CTc;7rd9QIa!d#@80L2&KQqC%fn)vh~Tl7A|{M~&<XU!>??Q=;d%pc
zX18NI#<{L8+#uLUDGO~h{tXW9g(s}UAg;{eG5TuL%9nRWECH!2v5ulQ6CMwc^2nuq
z=~QJ&*h2j2x9_a_d8YtIt`ljL)9=`(0)5VObIx?1ckN{6LdkuugngGr^aHTX$~QaY
z37FiPV${HQ`M&BErpmX%P52W~-P@O_DePvK{o}iU{0Rz~Jn<Nr0K(Wuj+n<%oo`w>
znjFSQwnw(~cI6xtxFg~9<F!+Z@28CHz&uBKM|y>JWE?8F94bQ8Cs(PgVm$i3ochfi
zE$%qmF%;V)tSssWh08<tb;o)h_<74=y3-++YB=fAFD)mQ2WC`AUS#;x1&#kMTJD$n
z{LNk5mZ%I}W)Rb)@YbwQG{m60)^uFFOcV{ap6cVC?(=ec1*fWHI$NsEytc>@N_0eI
z-Dd}hw+rTj;{)3!=6D(Tkh7-cDg_~3Bre?CO9@WZ?G5lsX23l#FEYQis^=p~cCdDM
z$8D@1*y>>8kVAoQ8$H2&Vy!SSX0gb1Iq0+KV?6_^#hh5ITa<l!p@B}Lu~cZPXe(U1
z{PxJ@2o*m^(++u@0lAK*_`vSyt&2^6Eo67lp%#ZlPq-vYDz>P0%GxDX3x4>d_QbJX
zt2Fen%pIRqu*eT^4z}A-JI7qae0v-09>hDtW=o*vlcg2jT4;H0+%biR-`Do)%?bjF
z!^;qUxUP&B>q>#A^zS@zC|h6QtSM!`(ArN@+!PBP{9VKm1jDuLC_;l5v-b%>bOd+N
zdL|!@oG!1oBrf=Q+-6(C{T}9s^dXwXHrjq+XG_Y1@rx3|3}Lq9$9N9sa)DGi5n2HV
zWp%2~>dtsw2xVg(D1jWx9gq1=*nCAX8dZYknL!5TzWow0dU^PKR<SNsf)1Je3luS^
zBXh;vium?BIc^%qpuk^-NKEcYh+WZpWueRcU(81j+ue<Ih~0%<Ix2ZX=?7LaLmf~0
z(z{ziUq~Kd%nKZ?vkZ`%0^SM6yAy1_^}#*NJDT{m4*L;)@^zaI<~q&QEr!!%R1b<t
zFs=s6q*X2&n~yf~f5N^FV+r(;#D4*}QmN!81&Bws=Dc(eKs=8={fd429?!^8Y!lJ`
zl_O)f^;doaL@!?7A3b6r6yMj78#>Luga;(eE8p*JBGa9J9UZ{rV-UBd5uXpfH{rPL
zOx{G69Ka+F23`4#&a(6AgXZiX<ZG^kNAFY8*Xb&)sJ-MUJO_>59n<*@D%^cbxugLS
z(vlMZYUnqS;RiAK@YtgW(!{+wUdSbX!be#xlB}2Go0ZyUa<jnL!@nzoyY@5Pgmo1h
zt9$G^<bf$1#R+BnISlq0mpcQxe;*)Ya=#+43fnvNBS?*HHA3-f+tw@5in`S;OfrQg
z+ifXQQxw^iuR}iFG`fFl@<<$LDcM{Ot~;nb__4mCH2G!x%M16}FClc-PF!9M+ndYw
zo68bw%ibK42PIbsD>=(>FyT7kAP*Z4xTd11!KsDT>@VN=P|{)Rdmqo8nxQ|Sl;;>T
zVO{MjQ=%^y&YfuL`YByhiV}+w2c{Nks~2@Pz4b_t(XYLQyhOVXuIO!Xa(3EP7*+`+
zj8v#A8SL0Q59Ew0`86_L-C7)3c-HDJvdp`Pzm2Crv-#^{3*E1A4J4oFSNOfSHD0u&
zy!I3FUHvlf`+%3GaxSwq`}rfIo_lw0Ug;℘A>^SzFa|5A^yOyPW%VZo(v5+fQEl
zW=e^TjUyVGBy5%2OWI>{Q7lQ;hX-OVkz2Oc%dTbkeg-U(hi*G9K}N#wzwZi9TqDva
z^uOY252}2{(ax(}^X{A-Zc{gSO?ON}%*q#hzpk;*0d7*UF-tkbz6j@^NTs-qe|Jvv
z{**H4TNAR4t%Iop9Lce8@S!P`W4F7lod%oEaTV)BJ58XkEY3Mu&?y;v&Il2dXy7X9
z0dF20Hitr6NyRnc5+&|6D(I@oXE*%C@@XpEtLHwQ;iPnbxYzJr5L5I3mS;h+snYoN
z+(^1oys|RUv4;OnWDKGbCGC*`8|_XJo47slJ^+rV!OsWWax77uZ$5#Z=Qod|oHX*-
z0$UId2|i9~Z#RS(iJJ8iUmp5jAgFgIw#md>tLFV~F|A8H+aYJA^a66s%FaFIbZfC2
zs8@DA$~2p&_%xf4Kit*`Uew+eG@)AAE*QH`i_?KF@qpqhYRkJ`aEolb1N{MeY#GM)
z_a)oLZU&EJnX4nbOTKB3#wPbRH{RJd7gQH+A1J&&@5|x?J6F?y(+5wgqR2Ke$4_Ux
z0k18OKYu#o5yjj94}mE6DD|f1CB0zR*DJ=}wr#)%3Q|Iw*dboKQPdARw>4}R8+7in
z3r{0w6xkOb2uIOF<OmtN#)?0FIOp!CCv90$nr9@H@pgKc{1hDo6YUWPY2D|yD(KC4
z9zTrTM~@_JOPs*q-*2P2(Ai*~&a|EF`$^xMGWeSFo`rY!C=Fzs@eY>tJ@L0{G3-9n
zqko{-I5{m)sTfSG`*a1ioHJp)8Mw!_A+G&A3LXK-fo9CGF5{l(6ak9u-+sTwE6>>$
zC$YIpuS~s8RXH!Z-|j&A4CktF(+az7iHia4++AEt0MbhxSzDf()AYp2Z-kIAwZN$2
zW-HfLBn@!>P3vt~kL1G+-|rou#$w|N?swurpw;`Dny(|gDf4<y*Jf_Q9kK&>(+#lz
z?+yKF6@#ujt)nB}AGaPZILjwBip?X$mR2_6%ohmTo%|~vDYTw(cOF?|dR9;OcTfmy
zJf+=O7pyLDo$Cgpd{n-lrkN0WINGulw!APtY+>`b?*aNjYc2@<saD%SIvXbe6c3mb
zmM7w=op&+P1-AkZ;&S9`pR*}Pc}rO$$7U|Ly+Jr0wv4cDWM3Gz=ZHsZ<!tH&;gj!p
zi-An=P6&ZMJi8h=SfvZ*e|Uv63$yYUXLiZDjk|4c7@>R|Dh2fjr_#6Neg&($Xm^+1
z&2K5N&GaYX<1hfASQHeqR#L4OJ3L;S`brzGw_!1$4E`5;a33I}j5-J8r^%DMHLSZq
z*CRRF<BLn9;iJ0SqTjU4wZL2_)K8~8T6wy=JJ+K&mK0^>47Wakt`@^1h}(*#mM1^4
z%qkw`(!xiNBACk4GG-{fyozqyk_cN8B2YMKfhXv|*Uhd;xo*u==XBfpN<bg$`^f0;
z3gXr0Kp{3if)ugN%Tb4hkcwR%7&~c-%&%5$&M@$O@>71xMT&HDz~=MHbsQv~-|OI?
zFdt<q@&el1wiUKHT)y9m3<6DBK_lXf5W{em_M5CGLK`~RRCt=DU&5A3l2eCBNYb}i
z+22!=gyHC!OU(z{jE->{DdvFzjTL?YOxOLhhSK_t6!#6+GXyKQkk3~ER$|7-96lKy
z>BFN;^pmCGqn)R-qAW5d?RMGSrPbSQmf1vz;^{VGCXWv)(-vp_;#Vb0-oQ`2wdg>8
z-`mNWfGyLpN7SLUJdc*GnN9}}W9YrV%P^qyG~oK3omhWno>ewsw}`rZ#7CCG=$eCX
zVir%vq}C^mecS~1wnVU}^A3BGo~FbrIqeIvs=V@4zuBhiSK|CB=?$qW65f5k&G#y*
zD%=jmeFG0Nt)Adz;rm4&cEk<6n!wFZN#VU1ogh%x&uapa>YH-#+b7$VRl(emhTVln
zPN+61>q5Zc3xd0;k(tbnM=-!!1=$@|1RQ>n_SkE%6?|do6Y>BcH4)_v&;=tHdCh`8
zwLc-R0vZ!0P*!SIhxQ&UWglGPl`h4)3ynvAuiC+iXkwmV5cziavl=dUqxa<AdSD=~
zZhY01RMC2y$x>x+|D}BcT}yb$VN@LRZE}iN>TDbZNI~mK@%XyWy}gVVwknivY||(H
zIEDiO+OC}_@Jm6reL_|{#3{_4%#l5xJV5tZkuvT(^G^)@Cl}wen|~TZThu|i1b)G5
z{U;cc!uaSk!_ZQ%+Zrb17DSh0kfXuSGHYef?jHX=OB>FGvFD1FKa3#xita*8t^JTc
zZeveh`JU`jrQ(PEqv%ie1D9Ea%aA99%EI=smp=~}j%+XYBPoW<98jOyXTf^CproX+
z)q<vk;^j=sG0qfTU(69^Cz&<B!dp2>;TwKFcGyuhvuMR;qQo}7x3-yNx7{7uo14PB
zmesvs6Kzj}$Cg1*{LUNEx(#N*+n3&TNG{-Ww0dJmN^R~<&Bp4r-{|lrC;=?)+Xr%x
zE1C6H+V!)2JXq=UVU1G|cL+JVD!*kcuqi_n*qdANNc>qYsAOKw4vWS-5w?%bb*l-#
z4ZKYk%z~m@-zWkW#tbfz6^t%`rX#JfAOnD|N0UcVxd(1QE)3eR+S@ewRg4C5HL`7U
z8acHlD?GX^?oE9m;Ce3#F{nXp^CzJ(Y4Iw(r3(1m?x4&ych0cwdc2@8w4z`6B+1%5
z*4pnoZGYe=jV-fgNDJmP=0r9lRfN~q4@*kX|Cn}?8r@dP7x26sO2LHBnB<6mevKGF
zfUNb7&R_h7?G-xkW%H))w_Cr5hTA7qA7c(<*)qNvm@UqXXzcwx{XYET@qt85-+drj
znZuEfxak^MukK;M_Ko;09~5kN`)kEq_eA)qA&%J#_}b%+WOlbivK!+S$m+;u=w`>`
z3*|y57naXti!@=iG4<ID?RSgRB@W5kRU;Q*TKKIq0k@)^;dNh0YL=GbOc%^M{yOV*
zJg={L`sGEyme6hu-nMF)%L>Cc%QP<%b>SL*J6k<F#|Ls^Od7+__^JHqD-L|A2cx2w
zHm}6Y0cJ{flO!PeUjll9ID`9hz%K^vhU^)YFN_^L+hY2iQ+$8r)@V0|x|ubNNWyx0
z#?$)dzLYMR-OXkdBsn*EHQe$UcaN-Zn;S@!n6s74-l5GeYmcw^Z;LxVJpCXL%J<*o
zr^rjX)A&8y?KaE5w_0HMejjsR_d?8p$hewWi0wgY{ba-?Qw*!a>t!rG@u=OYUg1<<
z<vCgQFc2^IiW-I{m~bWpOsYcA3Ip-XVwgYA`ftkrektiH%z}b1!H_0Gf_qlM@%5m6
z#JEvovgYf#S6K^$Ii-%wB<%NwH^LdTmpFGdJ0Y-8PWvbhEzfM$H-)b?7Pw5)Ibz!w
z6bTAzwz>|wMCv7O-ra<>u@^?}*(atlTGou3wWor`a1?s5>or^D%S@Jf?0Veo!v$1Z
z0Y~`Z5tzS3H$2aD>s2yY$1GvJb3KTMfjV^U!*P)cy#<FPPECyoS#RbdD1JHg0(t=R
zL}#lT^jb7u@Wn0aHmo+R4l^4Ke~-1Npbd_VDZr^ywooF<y&w6Wu0ZuNk(w^$$A<~^
z+8=V&>a9N%_7Y@IlYSN0cd~6MAO-_J(&C}Qsh50YLXgK(4;}xw&$LX9Ah%qw6taEa
z;w(`m^1)vMCBA>)1cmXu<y=0e^xokXC#T3v!@eskDu+<Qf$p6R_3r`%M%GXeGmx<*
zB;c*jclOZEA-JtT4n@IyQfzXqxVOfr-AU#{jHV&ZdV;JmTJ0MCZ?aX{enxR9&wLbL
z_u_qr{>HL6$d=o*khn}Jbip=1ovJm*vP8E_o>%rWYip%Z(aKwUEeB0mRN-lcnIft8
zelmVC-)CO!OR1>=HGnw0S6*)E#iiUc+EU_Inpc{fs(zAw`u0DyN`|Gw@7kO7V$|n;
z9`xv3(YO^6Rvv44M0@RvU7>Osi<Xh&pw2kVpqi!i@u;<GP1T}Q=WWk&^|tF}Ytf1g
zfG8L+=A;dADJC=xab$Pfn=1v>ujk-<`Y$O(KlmD8&gw_yU2%vimQB;RrQGBn&n|Ch
zcxPr)#?5G4emo-*HB=#B*iG{;6i@?CUG!RANwj_NRc4<V?%BEG^VUB@Y-?LF$}IF4
zuf#E)bQpKQwb~7sdZHhj^f~Z|tlWJXKfyDeLEih?({!imSA5g_SoK&XphA%Yz+D{&
zP6KfXcFnJ<H}vng?>wDy#MFRq*(Mnd*rOZ{D)(G^3!Yb3CE4(~Te_2XYHF8%QZ%S^
znDdD6xiq}n*%0%q^w+spf6^1DA)f<HfpEb4JC`mSg3Fg!JtuyjD0Exb@^0sQqQ$~g
zP~}c-_8{L6#jwP%)HNtlR5Ecl6L%A-L+?C&MbsNrl2wv%*ApQcl+t&&x8D`M0AB-N
zGY%FdsgN)(6qTz8Gmh@)0S{;aU?nkr1zoWRKO}j<dKCTIkJc@nvzkmbS5;TvDyl_I
zGuZ3u%72xoAkEh=KtEtELKoT-$m{%0NT@~kmKLrt_Rt^8MfXHknO2h~L1?3=DSX6{
zeKV7M5d1uV>rmqoA>|AaeC+#Q_Go-z1L>U8giK2@rhSlKm1;IIi5WzY*t1{Vsn&`K
z-7$lGih^CK79$Bbu?u}9&IxD9)jDH5E4(X-7qNJKubX;2S3Ql{c*Qtohb{VK%%go{
zt7qn!Jb3C!gtrc2m-`5utsn~Kpx-l(5f4~R84qeO$ay(b9yaBy0z-h+I8(q}po8bj
zP=Z7Df$N({|K{JT;M0r5lWWvV)P(Sx(7Vt<%-gIhVP?#0tH<Db6r9k9Q*Zx>n|s|C
zI664@ax8BSsz!pV-I;Y}%zt=5RLrY&5Z#gy*!SQAbUM&(B-?R3IFHoEL<=dr6azd*
z*aqC5XFcd}Sc$@JsS(y;JV2z-L!uCRGqNsrpH%bS9>uPYyvNvu?>oBeD4?Sosk@uF
ztiXieUI)cbQs5&>AXq6392-in9AR!F(faL$U+y;)!B_2#bhjI>Hya0mWb5&jVY0_a
z59O!B<mZ1xbUNJqBS6P9*y44P1l^D?cD4|1_8n0&YYaiQxnS2P&m-6K#l6kCsX@D<
zPCF2W7rCzovF~-b4(9A@JKdlv<(pKz*Cgws(E}OLr`u^AEH|!6zTPixUE}|xmz3vw
z+VLtXbiix{v1K^mqYx^=PUMA7>P^@UeKamX$8gKQAIWwMvm;joR(d2<0_cq?kc^)k
z*62O&Q9SQQJ5<)Mvo`-IZ|xc#pJrkGVR`cbG63uEf+5!+loU)S(8*J&qm-^O!+k14
zU?FFI&%&V`CCgTZ%o16NJdnh`1&^BlGLtnSDzI0b)4q!DMK#~MZjjw_db{0nSiA9a
zZv32UEWbYJp()cLrxNc(D8q-OfkfVCkDPDrY%!LV+y{$fZ4Gm8rs$%2CEwHAF|vPK
zHKo!~Td^Sbifm1=ICl%hd)|nA4dIa9!j&o7<noyA`MQ~sm$B)m<=bo2SEE?8{K~pz
z7XD7AsO8Sok{YaOg~{WS)HZ&o0p(P>mADPwldn@BO=mP_GUhUFr{@$lPBih766{KU
zYs_q1^SqpMf9elX?e_Pv4Br#WN}S~dd-YE1Ui11F`Su4V=@lg7F<K?nST6}~kuF}e
zor`W>40#QRzZI`C+sbvuqMIwBw)-jnb0kVrS~E2ePuX0D<zv=@CdEwOy{7R@irmi}
zViujcQg^NVyAuDZPNsnX5ADxUt?zBQH_^59yTqi>ErNbZqDu}c&qTJy+tQ8~G^<K{
zCq{%>^AbZjZAlLyGoG^&N~$<NR6gRQmC={Tji@MTX{h@DOpj`{u_cyQ(4I1dsEH0_
z<XCcit!yl2mK_Ze(;f}C2+|A0em$dJSZuLBQ)ORJZ<fBO_c@l&xX1`_u%EvYaqgh$
z^8>mxlU=-pQO7^jq|la;^z&glpo+^aPzZ&0r4qw(YagDeHT>>}(05*K3UvwzyYP~3
zCssf)jp|t5e%@Qtd?9Q)kwURP-x;<2x6|j1cLMe@rFm+ogfCFH&;kpB;1o^L_NCmY
zhu1^`>ku$K$*qctHFP5Gf?tdOXfJLbcs*mY&vOY?bfZ7DaKpbSt}L$XAUA-cYt3ng
z%d9l}{u6Z?aR8Rw{LQfZQR9I@-YCC4wnozy@4UUV9rXd*jfiDcBc=P?&kb+P|3`)8
zf(fBrj&V_iIpZ1;MW_GQX1H{~48XKW?ExV<V`kJET(plr?_1~}hW|ygA!l@H=7>di
zIp^3!a9`Pt;XF8xa!$;RLjF<W;bjv>X}H=V*45iXKuN#JQ~4d4z3q(NWuNX9%c8q-
zTZf)Ac{f*w`Qf*RT6z`@)amqJs;nREI)BxfjCMNLa<B#$eBJ8#CBdp3Z8c~8N{^a(
zJfW7>I-%~PR(^qv&08u%h42E|iw=6p;f@7G^lF+$HS*!f^E%&Y%^!Fj?W)W@3)JN(
zZfBy12xDof;V$%)0yu9nU!ja4AXvQ&=7#G`3tUrV32~vv9};}t5lQDVhCq}ViRV1l
zqZiDb^b5C5kzJCFgTcBZ(*%AS0l~#=AycrLl!HO)<(=W3VHwK(9>s_;#gA1~lB&0x
zh|$61EU%MkF0tP3JTJjBKywv8{#7kU)Z}ATfJ{J`#XjWfYyi=ym#d?cUh<+fPOV5~
z!Z_qU{gHS-y%cOQ=U9k{o{C@NREUT$^)lE7uCq4K_+a%H_Cu{dab4yF_y=hfTXLT+
z!6yy=+seEf4);318ckJlW>B>%2M2mFY?oyi8Cl_?`gWd@M9lwP07V%{3{DJ=WvM7q
zg_1|fFa4JUkP=9lygoHjM8te<b3FC(E?JCKw@@WQ1w{e+>grYK;i=P)WDX!lrrVuB
z4qU@mv@hYwflF|mM}ceZ?;M3G8_C}M#z6UkjL-ld{15j?UlSQKTtiC`;=It35ciCG
z-jU3Jp}isH>Zg`h=cDx%ED_w|*4b5~mbpioOTGhZ0pB{GOyD1pGfw;v>F=W2sScUO
zUg}oVdB9r*DQ>d7LBU69?QIMVC0dU8!qU|^)0o7|*-Wym+vt?xL=w&AO(>c=+_>DB
zB`2c-Q66ZEU8w>MH=^?S#fVikEj5xji$loqKVS0Sb#GJjy_iSiLE1R<>!aL8sPTPq
zN7eUcx05}nJI1slJa&D=RKzUCB)%`N?}Lt*r3linS|6mideZZCdUc<`cQlMBJ$hoC
zATV*F3HO30`R8mi#rJ~jgc?*J>sAz)O&`wyJJIu4=U$&{W|rxQNp+v1IeqlbNK$W5
z)0kysUuj=ySy!rgD~4A#Cnlc*p~KptexH6vXrH)lLiK=7NR0zYv=h|O{FMSnGV$;a
zFR&*j@u?x@4cjTaId3%QqeWTJXn3FAHs37Kfl1Sf4nU8O82GMcVLq6vGfeH#-CWo)
zyc&nEB^K=D4yZ=nI^>1Ef9$#mwg{#Rh@6Cyz;s!5hDKghh$ILe0v2RBQy!dzy<fF9
zCD1JZYx61(&5z7=8y{?7Q{#$NDxV^uR!87pug8jV;DDBLnJP7uV?}8Lw>)oriBZHx
zg9U(=<Qy&P8&l;GD$zaptSbiKR6%hljsIc)W0<(OS>NXfq6Ruk(hnnzqMVTJo*4Z%
z+!*whzkf|UioQNt&71l=8-En#TLj7GJow-)g8G$V*KcbB01|&^;?IXY?|=N;V;~8;
zuFZS!NuPWaoqOKMte>(Ep0~K#02P$fW_HgS!zvtEhrwSVZ>SJR)48t<IIa$K#GKAZ
zLP$bE@4-!;LF4+n=wW^!M{&n04%}8RLP9SLLN7YzmjnUW=NeraRXZ^v$T9a`TCdr}
zVv~YG*^%05TDylrnb!R>w^;7!&DOQCP%A0%{hwF<CQgh9RfxT5KzQ`SJ3F!K04-sm
z?g*m|)^@AnESeU-I^vj)aVNBuAbs%O*!9{-+#u9qQN}Vh$!b%~x;U3QV?ATVXJ><B
z2T;q9OU8(3-Rs;F-e<U+eQ=6yM7;aFwi;h+r<U5N@EcX;G4uxU+lk3{sg`EC2;|<%
zAA&68Nat<KnYA@)wKuVzFS%A%2Uz`?v%^L_1fy^Q-mt&h_8|+6cFP^itcAoYVAEo8
ztzHkXGA6uCJMrJlT?XXR84nT=2UI=bZak20Jf!u&gynJ);JwElHS*t9J$)QRhXN%I
z#g*j0VN){5$#u9gezl;)9tg^0-um^45%cWb>t6Uhb*haZ+!86K_qQVCA96md$wVPE
ztI|5sNWV0Ei)4)m6;Hbjx>m6Y>bdzEc@~Zh0VkDq+@N;c%vDj}N_x>SGpra-SgX*7
zLO-1siKeAbW-F30Vp}W3zau&VPseQp`S!pAIg`v@C@q8%zAGSnmq*wEm<P!mit7j#
zlOha@=aYtoUHB&v2B4bVe~vsu#)e?h_pPdzsM!W)PBl;~S7H@m(kib;3A7deT)QN$
z_KKbNRWLg$kEpcknTC%nX`ppqiSlfcX%$KJ^kQ~&>S?omP1q!FAo8uzlbIbA{E^!f
zSZ>*!?Q*8o)5SVgjs>2L&~KpnvYg!LM(K0_?J3W|Y54N~w@_-Mn}Qjbb*6e>$8o4=
zrl^x%&}WRH&!AXYi$M}h<buz+&E?iCL?)8pvSsgv-{?%`w57T+B)w1SM(%k}VltT1
zli)z<Z;;QXML<JfHMsCxe4$_z+^W!-BpJ!PgRRY`{!~!${uRYfimvSEI?Vo@;Sxzl
zfTd8O+7L)bfUUqrlbor<(iEZN%vily8cAnW;xp4GFnn9x8&fk4*=MvC5FexS&s4d;
zL8?<OhnL(MY5bPzgq7-qI*^Hzg3Z7-MO{azr99FYoO-6z6H`e|ZXhFaL%-39*Yj1f
zj+7O7far9lCy==oyBxvdoUHfWhMhAMihWUJ*mG|~z!~a}RWre6MrQq&sZpz}$1pv1
zjjdtL&Ka;MT}F09J^S4q>)=C6MCdr18C7j`szgf!<KNls6q}h6$r1IoN=wATa|O>Q
zu!Oi{Y5Z*}+Wgm1um7$FHOH_AcTsu-=#GW@Z+pr9ybma*2JsO^;rOGe`=a;=@VRLH
zR23KdSI!ZzD6W|E(0y<7#PR1q>!*KuDxSTI6OX1!HcwS{&l^T<z`R>+fR5~<I7`Ui
zb+|tlkr&0w%<~?)asT0d)6HXX8=+&SL)6Q#<y}S|Jx{3&fS*&D#?h_F&S#)m`7ojJ
zLuG2J)k&fLc!GO=2Dk0g!Gbs2w|)*h?;xW<XHPVZiiSyj_@&(=RXv{vy?NJh;VPB~
zAt^3tZ`n2+>X3}f49Dbt?t;6|cb~0QRN5Gvb%i<4QHow-DH~7s(vXTj82M2SHK~9w
zn~vvBthDzqcQM~xR6U|p1osQx;x2_uj>RtEuH)`QE}h<y?-(dKDd#+9Vz9q=Qs$Eu
zkiJ9nL*l92t^DCme)Lhb)+O<=Sq!tub3`K_R04XH(Qp~s(SUV(vk$w3@2Grpaicym
zm2Q^p+$K}`eo$n4a4ujxpkwANwLiryo8;{_V_s^}x7;lIDED*5#X)E_O&6n7$kcPt
zafrrytT9d8b%R)xBEj4r_+p(^_K_$IDP|d}QC34(;GW!MgdXnp2rI6j1+m)>>K=}E
z-0mCduqKRwJObk=BVR^uo7mlg8h*3&>Y>pH$!7JQ$<bN#bYXjsDl>g!ePa`GeQ}cj
z{eZO>OE1<amnbP$qbpt=Nza8qbM0h&CV2DOcGJg=T$SFQ$G@#_TH&9b>pk~fx-$Yt
z`T5*pSY+8038m$d5n(A)=c15z)2gH4IQ)(zq@TQLnIKTi>Sv9|t)`_myG7oF>uZZ3
zMI!l{vtBL#{p{P>8y-v&0Hyr;nH*X#LnJP+henJDepDkueS=Xxk~f<(J4h6uf*rdP
zGbjKP*+|ssVPOBkLk{dw^)-{GSHn%qCuApKhd1Ulf;%6eO{7j#?mLK3oWx2S34c^F
zhf~NKpv|IAM2k}7!b)pJA2oxJCEI@_(yTJDWeLshXDI1&?qOi;lQ*Xut9bt@L55R~
zzLz#D2EDIepk-nnK@_0K6$6d|n+%#KD4M5KliY!^5<gMWFGNp5skoffKP6axB$+8r
z>1QC1Qc;hEM-m`E!bp{Z#nV624UqBEte1v;uOPUe+Kqo?Kv7*M{Db6bjekT#QPGMX
zK4kStL#V%<kfnY~MIxj;q9jB&!$A4~LkXK&$yZ)f;)sFLyG>>Xe_7Pvh=kHBRlyb>
za&};-%|}W{N;&H-XnhlGU)P}~J}6`7ZAgjMmGAkFcnM{F&}Ehk-3i9d$&i<8AwQzs
zNn`4->#i;0aU**vv3<T%bH*UUaG(rtax|&$qH=bbziw10N3>*r6<H7qEl|5mG6mWK
zU#FcI>=tIBc3bas(JnS|#JRJ%PK||fnbCYzLhPqNtf%{h-^IAD-xqQcqDTLFCzK+U
zB{jF>qZ*dx_E(ctlXkPf`H+QPOEZ^k_OOT?lY2JKC|*2Bk7v&d_DJ?>e07pNV#gLO
zc{}`Ew2#N;7+dgL@Y|Q&6sXtHr!C3SH*S{)eL^?O+t&guy$->vF#G&fZxG}V=+AI(
zi)9mu#))(ky%BCb9L{T+mBvopnH^E=U0tNZ59J~0m!bLvi;0zSh0>YT!UxA5y+M=G
zE?i^h!9fTD!E!Dl<gKY(@s6=cyH-OdB!X2L6|oml{ucm>Ky|-UgqIL!y(4@g+#<ax
zy(tU^r@mi!Kpr8F6dsf-<)?&U@&tK;FarGg1>sTf>sN$PVAczTC&8?j3S;H><@bg0
zVAkt|3G`0wBrxmGgy+GmtA!WjL-N<cH2I`_QkV&TeO7px^J`(Y(o|_GyaqO1C(H%6
zjTW}5v1+VP1Fo7Pd<X8CFZ{rt{R*afm0BUnYAf|x(BJFSZla%hyV^^1sJ+#JVg$J7
za4}hZQXMDesN>aXVv#ySog=p8&s4=u>H_s+@dkC1x=FkjoNlK$P~D^M5g$^k)oO7V
z_}WqNVb0XVN7XZGjW`-itxl{2#kPwRz{{G6Gqe_3l=up`SeCd@E7SUktF-&HiQ;kX
zIqf;g0Lz#r*})nXNKN^U%Tf#NU2Tcv(3WW*NKVcaBsVz1PAOB{tsRnb!3)kxS7Qxd
zBz4x$_(V!y`u*VdgB-xVU@Y_y(s88INav917<0%C{{@E){{xVkBRP;<NO4FhNSR3a
zNTo=vklG`4Lb@5LJ5n#CzDNU@=on0iIfhXZ9V3w{A&*0vgftatCej?F`ACb9mLRP}
zTH|fQhF|!<*;^Kuw|n#KLE2B}nBxf232%Ehc>m)X9W_Yj84F{U-uqt+Qz;2y22vp8
z;0B$QoJi4@jC#ee1g}2Lo3g#B5UCug4N?cB&R*NDWY5BSAoaHTDXd>ZpIf#A$&Q5$
zK^l%U3Tceh_OS8Z`X*b~8a54S7Sder`32tdi@j+XbgPio;(9hBZE3g`y5_K*Nc)fu
zA{|9Kg;a}lfgxB&(!Kxve*9l=?+ii;vHo*=o{zt7I3I!JMoL2RAmt(z|M;KZGiL=-
z+u!|PbarfXuW)V7E=b+1`~8Rhul&h>jBjU8s~#FlUOm;@IQ2p5|KooeZ!5jyZ9m#K
z2>PK&BfR5}moxgu|IV>U6XhnMA)yhW?$D%A4`D80F|Z=EEwE!~7ht#0p1?k#{ego*
zhXQ%75uu|)$A(S}of0}dbav>x(1oE@q02*86RvNNH-&Bm^0T``t3wZk9uGYodJbsG
z7S=grhs_b-Xin$=x=41B9Op;@W;*hLrH)p>_Kr>t8|Atg*d3Z)j=qioj=_#$z>$th
z;5f%5AlFZI%yi6g%y%quECH@`tZ{5`Y<6sS>~ZXO93ebGSOYvChFKe?h8e)XuwbAw
zEE<>)mWH#)6_y=V7*-zECagnP=di9}J;Hhe`-Ke*8$vidY*g5ou<>D&!=?deh0O(W
z%>u99!o^|B!d8W?4ci#DC2VKdz6Qi-1#<mSFP;jk4ZGkJojRc(Fo@(3X9UpgOagkG
zxxiv)MFX~Vc64@ec60W0_Hp)i4ss54j&P244&|je$9gprol_c+Yo<GAJLfqUI;)(^
z30F7BT)*DA$+^|J+ga^A1myB@;AzO`oOR)HxGg+@uz7>*2zLSF!c%~m;rYPQ@K(U~
z;hjjnIb5c^-NSo@_YEHqJ~(_>_{i|e@No?|2{<);X80V)^TQW~F9}~6zJ|9Ud;{U;
zdO3W1_#WW?@FU?T!fV3M*JA{WP=Q87U_@|)Ga{NWfiMl29Z?7@k7xtz5YZXfHKGTw
zcSJuR&owY&NW}1nQ4wPz#z#z!m=-ZBVs6BOh{eEV5vvHfyf$JZke}TWu`^;{*pP^W
z5l4ZiBKAepdhtS}7^z44MFtUu03%3_AlV(61oTAa0*fOnfNdi?M(UKS3$PnBJtO->
z_KzGCITSb|ax`#k<U}CXPl=o!IXiM*<if}*;PS}Tk?SKjMQ)AU9a$ZDi10Y!Y2dlY
zy2#xw*<}L;xS9hUE*CJ)m4dU#<;ryByGmWHT<u+*TsOPAyLtipx(2ug6Ap8YbXB^>
zxhA=$0%yAB0J&zqS8w4W*AmxC*BaM`ur`s$U7PFCwcWJ`2)%2+7mv73xN2PIqZpxD
zFGm?sfxzG>ConoH0hkt*4J?c*2eygo5Y;)VYgCWWiBY|y`b7<l8WJ@;Y7{RmYK&Ji
zK58;>8X?!rikcg>AZl^cvZz&rYa3*)-x#$eYG>5GsDn{Qfm}WnRU367T8!4C{i1`S
zLn4QAjE-oK-O))vPjoJ@IJyGZHo7CQOLRA2&*(ltp0|JWpy;8|Bcew~kBy!fJtcbj
zPjGhhyy%IpPSFdatD=`juZ~_Hy(xMt;qC^xI{Fasc=YM$bJ2A%ay`b_Vgi88V;nKA
zn7Eh}!c1U3$)z!^fbC;C0dJ1!4(t`v7dRkhFp%dO7Be!YGG<)Nq?oBOGh^n&%#T?V
zvm|CEa1G%G!p$+;f&A>AnEf$FVom^S2)TUT&D^Tna0j}B-A;EjVZu-3G<P<z&|MB}
z<L&_L?CuKWxq7&JyZgBZx`()jyGOalxW@x0yQcwXx#t2GxEBMLxmTf<wS*hpTiiR{
z``icJN8P8~wS*Tq#)`mwvAX+ctY2&pFeEkt=#EX|diTLtPi$^%F*FsiZDTvec8Tp4
z+cUOLY=7XO*rC7?v7@7_IL3~RoftbMc6#jW*m<yD7+VFL9lM-x9?G%w7Osw6AG;}b
zYwT{f8e1KE2zZ?EbnH1G^s#kua-1#H?Ue)Kn#VcfTyb%PDGitzmk%tBYXxi{*9mxY
zTz6ovxW2#vaf9QA#f^-sj2jobHEvSeRQIyDnQ>Dg&xxBFH$QHX`)J&fxRt;)gwVu#
z;x@!>j@ur$CvN{wkn4}cortSJ$>-x)yc%!B2gV1-JL98)TuuO{LC%gZ<kuBnPS_^C
zgC)mzj_(TW5#JlwFMc3!Nc?c%sQ59!@$r*^$QxT1KP`S%{M`5j@r&b^#jlEA`xD$4
zzXiB6eqa2-_@nWs;%nnC#AI?z5bH5PPw)c<C4?kIB)AijfF8o!gkoStLfeFnoRcJU
zN$8fqxeB;JLZ5{G34<KAgrNx|fTI(}S}S<MM7|CtOi7rYFgxr*!n}lqSTV5@B~&FW
zPgu=YrG)iZp|I8@Y)aUgu-myip*jJp9-l7>#}iH`oQrYsahp(=C@0$7!HEHh&4G?Y
zmo>%`<M{neOi9d4<aaY5u{6%X`ysJaV*A8SyiXEu2GW%#c2DdD?3*|szLu{ziGve|
zC62`E1J9pWnK&+SQly?ZHE||zPU3vaKPN8YUM_J-;>yG|@RmmsH@IrJpGn-DxIJ+X
z_c@9Cf$$`WM-opY)<myQJfFm(*YlAd>q%0RjHJM%;3Q{KbW%c6T2gjWVN!Wgo1_j&
zokOdVx+e7qJ)YD%sbA7S*bITq@T5^mW0J-vO-`DYG%IOt(t@PLNz0N}C9O@`=ok>*
zD``vkfTW#C`;rbO9ZfowR2x1&=|cFDWHDJ!_6u8^9F!aqb}AWMCE1;v6f-W_lboAe
zoLrIIHo2q4H<G&~cT4V>+$R~_k~50rLCHgtM<kC<9-BOo--YBU^(%Yw^yJxu^MDJJ
zh9p-dFHc^bygqqT^48?t$<@h+l8+~!PCl1hmm;UwQUX$%r#Mnv7N>RW$Mo7`@hFR>
zq@<)|hEBA2V@iHXDX>*ad$2f+jg(GKPs+_Hol?4|^h)WQG9YDe%CMA?DU~VXQYLXr
z$IO(ej`=AwQ|6@1x0qXKpOi(R?vy1dD^VA5)RZ+T8yvPUXUb;Bo|Nq=dr*6E%Koqm
zDMwOH0BcgtJBOySRMj~&yfoDams0~%gMrS}=%fXXMX3pn`Kf8C*{Ox8<*99wt9TEj
zc1Z1<+SMA{u3@P?QhSG8NbQ$8(78KxNb2y^QK@56$EQxV7-s6U)LE%>Qx~KzPF=?5
zMe3^5wW%Ay(!teJw^*3EGj*TEz*7%4!lQ(zcrB^5gcs7pG~HoK^GgeI3`h$}ivWuT
zqfT?DC8c@1axP&ppI>Pe-kt;>PHRipk+&+XOIo+Io@reynXpe<|Fl72tI~$1jQ}48
zD^44oHa2ad#evhNG{Wi5iQs!f(`Kj511{vqS!-IAg=x#vR$ELpZGGCNw5`sCX}i;^
zfzU&9DDAk#S`#+?h-s(!tWP^fSZ86noNfab1tU!lNN=9*0P_SdO?RcorKf~1NzY8r
z4_}gYD7_S8vL?M1cqZ;kdV34gJEh;8-aY1gdM~U{@XT&Cy>I#etefZ42SXl~J~F-1
zy)1nkUlGzLrB6+tnLa0WdiwnIMd?e@SEjE?-;lmJeS7+z^!@2a(oa~v-SXb?MtV*9
zc@Oib@Ww|yh9}VSgq~oJ(-ZAU@T7UNJ%zDtJ>{M@o(`VQ76)*j@^r;2K&y<WM|_+5
zHQLkL)6X-|GsH98Gs;7&t!KPva<TApcf?LD(R(>!zC(VhjdgFK64dwQ06R(Z0m
zbvd@$v(~M8HhQ*jF5%f3<MQnD9OP@d=O{`(<-uC)xsZWXIIdTQ&eyLDzc@!mP)3OR
zXhuYa+kG^Cd`43JN|E8o$jvCusK{vRRymhQnV-=yqf2rXzq*WW89g)lSf1A1Bcp%D
zAe1vSV?=x{Uvo1?XN-;AoiUNGQyEh-rf1B~n3u6Iqbg&0#_Ejq8Jl>&Wo)H#c4t&)
z9LhMJaXRCib2|6o8FgN^159k?#d=nABva;SX)<ku0lW>F%?TZuuFN?1z|54)O!uhF
zd}1SDCW);wOEX(pa%>$(<ic8z*`9md%=Vd`GH<qcMP_#|;wlp3GJ9qAO^mZ-j<6h%
zIXHGx=CI6>U=-jLnU$I2GACIqBC*wvm>CdTojEmbYUa#Ltp1tvGZ$GaK2{%K=90{n
znQN?7K669n=FIJJ+cWoMV%_I@XpUr_uvYoZnnrk@uTxo!V`c!!YL<}|h_xFlcvf(h
zGb<V^HP-R0gsilz?D&IOg<0jmHd!68I=izvV=YFXXLTj)Vf9Q_@2r0D!C3>dhQu$+
z8lE*OzBX%2*7z7#*5s^dS+la{W-Z8CoV6@#Ro2?9jagfOJG1t=#$_GMIvO!I>r_^4
z*pRFX*<!YywJh5&Yi)K=c1U(awmUm1Vs5r4J2$&HyCS=7cE{{4+1(=hyZUDLbPdk#
zlifdiP~@iUp^>|@M`VxA9-BQedrJ27?Ah7#vKP9JWLLRrvX^JC&R(CrDSK=7?(FL9
zL)pi@(ZQDN(^31f&t=!;$T_yC3poKf&2t<%uAI1>l!)5s<vE%4JUk~qr!=QkPWzlr
zkZ;cEp3^I*Z_a?6!8yZnM&?xJjLVsnGc{*s&YYb2Ig4_Z<gCnDld~abvlW3xR_AO-
z%teuo6;tHw$=RQC#ESBAPDDolYjVyb=E7Q^%c7!l)m#=`muut(<_70FbE9(;a?^4u
zBL{KI$mzM+k@Ip3bIWtRaaM#gw?lnAYsHwkohh!YM(l!!FSl!b?NMpDJ%AJ|<@U}+
z+~kdM+D49!4$2*vQ<}Oga$)Wels`OoRPLDE@wt<uM)4lVot8T*cdo@%BD>@+$X)EJ
z$z7JaDtdkH+T4w~TXJ{i?#n%B#e=y=b5G^g=3dAX^K{O0^8E6G@<I?(BeKqmAav&?
z<#`Y_BZ5xr$T2UMqUqrz7xP;3DlE)vn}_H)uS;}AWdFQwc|8&HBL2<mlh;3QkXIf`
zID+$~ywTpCMD&_B){AIW-o(5qdDHVIS~B76ym@>`Tjd@|GidMGTv_I&Xd6CM#mi
z+u8_sM~%;`jvAPEDDOD%G)Ep|CZ<@JcP_8aiYxQwd|Q4%)Z+Z+`HrZ?Tn~*aKhBCV
z^HUmOCTDT^`Glnw=C{gkkH``6V}7UnoAbLPT0|6?-z&dw{($JJ{K5IdfFtuOqu1w;
z%b%3fir<&~sf05lr{~Yf>ytk}e^J!F{3ZD-qbKIC$=?9W&H39Sg7f#}@6SKNV+U(J
z;=U_ps$0!JkzbR4zJL{|1xC#Ng20sd1;GVQzIGHu7bFy<afF;*P*_l2(59dRuyX@;
zE$C6uyP#jez=9zK!;x#071I@rDi~8RzF=~}w1Qa$a|;#}EG}49u&Q8fK`{599AoPW
zHWqA2U&6g*!A`<`vAG3^?+T6<oGPd-xKJn->anv6{bD_ZL4_fO5ryu;q(Tp2F87m#
z#a3*^v9O}BZDGg4E>@gX*sZW<VV}bOg@dx!7Y;2PQ8>DAY~jShDTUJuX9MRIE-b9#
zKC^H+;p)Qmg_{bu0(ZLy7FHJ?%IQ^jyzq2RFKbOHJXcs(Bp2C=0*aa!If`6GaYZRb
znML_UrA4h$mvJwee!i%EQKyKxMK>39FX~m)w`f4o;G$tgBa15I7Zi<)Usg1!Xlnf2
zqM1c=q83{#6vv|Z2|-v5Ar~#m*ljVl)CEOLidGh_DcVr9Ic84L_M$yS`-_egohYg)
zI-h@}pldNJ=v}N98wKNw1B-);oyF0`3B_r}*~Nv$<;87^JGjObcP?-icWqo+agXBO
z#r=v077r;NUOcLJO!4^Q$;H!(XBE#aUQoQacv<nP;<d#ai?<Z-EZ$dqu=r^4sp8t=
z3ngNSp0&2buOtW<QW8<z)r;<uq!?F;rzE$exTK<_ZDF61jwM}6x|Q@S=~L3bWKhY_
zk`X1NOU9N=ESXX=y<~RDypn|_Rs8;zEH7Cdf3#$M$)=L6CA*8;lvKOMl^iNLUUJ&H
zcO~aa>PqEOTWLVjg3{)tj#5`?Txkk0voyc7w6s-e`_fLOH<xzzM8^e`_KI_q_AMO%
z99%lAbYy8|>A2EKrBh310_PMSDxF`tsB}qs_tKT6Yr=+<ZYbScy1jHy>Hg9qr6)>j
zBK6YqWvomsGs*(Xg3Fv`(Par`X>prVmz8Cg6&5TmD=%wP)}i!7S?5T-tZP}1vffrL
zW&O$qmJKNzUN$PZs%%Wz__E0{`-^+ToG6=CHmhuI?CP=wv75>kmn|z>RkpTlW7(Fn
zon`yV4wfA)sVF-bx1sD*-1f5CvJ2&6LQuJ$5K-<|9#kGu9#QTtPb&A6=av_jSCqFc
z?^w{Uyi58Lj^*8~sK2~td7twB<%7zHmXF}<rF=AJDdl7NQ<U<F){NsEBW!{9NyR0z
zgO~8*lY#On<<rY&7YyO+d-*&bgO@Mlqp`fodOF1YLu_67@&YHyCni?Dx_rI6M?rb{
zCU+0-(;IrOQoc22e);aAHRaXihpec-{CN54@^k!NC&n?M?iTqfU{~cnpfAZblG8~}
z=Q0~5eFiy0ZUf9z2GQA`boP0Y#{xadKS^#wvQ<Jl$sH+gDlmognR0(Bhv)TBE#2e{
zj>;|E(tI5?GG!=GGCv~Co4_EsoTG9-a1rI2!CP{X<clk)RU=7%H^~_!XONsp^=5c+
zDB-<igEB9EDJKG}t+QOl*;}Zc)B{v|2gR48TEN?EzDD|Z!b)Ho*`)K917}g2hmvez
zFyRE!TX`2y|Kw30{+)WM51l2ww39SC*)VF=>!i7dYM)OnY)5*3l1r$Z2k7ixDrYaX
z-=D4>XD@!j`~2c3%5>5wlsB95_U7#;IgMnGoKO0`Bxh5}q$kXvvmQE|BlF(KQSPR8
z=949tGo;gGW8H<ZRN8WC8(kNTkPKx8*>g;l=aS`I>KVE^IhU{#S@xp3s;Dm9Bk_9P
z66r;b;`L@<j_NUJp5Q1alDvx}^i`y(B6%Lk^GL2Fxsv1)B%k227R>W<6tAx<gPf`K
zV1ja#qm)T?C6l~?qnJ#Z$CUvnA&;Z@xTT?%TtjG3OCDF>;5O>txXeoy2lEo-JE@$(
zl&dG%KSTB<RLei<Yzdt$q3aq(xRh+{UYtjoc_deoTuJf?lKFMD;I&Ktq}og9x}K$y
zcPax><6Ms7PO4=MwP6UAypVe49V%fbwf`L|VLG*cIPZUX2Hl0>ly^Ag?MQiNa=p@>
z&d%g#1(C}F-8Dh9G~80?M)nU7wj+&5_v<;1kok2D;0T#t*FcVtd8=A+gp9Tca|lIh
z+cnfSH`RU()%6_7ksMhKX{aZ~_Xufh%i(0>p=<F_IgCbHJJK`KGwOe8C(gbAxss#E
zs8@UQURCd=d)J%npHuEY$sceOpR+X7OYeD+u9WJU!^gI~jz;(#vYbOUM>r}mRO2$j
zIXo9MRV2?Nc^=7?Bv+Drg5(n<S3r*ED9)){kG8E+V57cI?Oa85H6gj0Mnw~^1|CUT
zr!=Sb<Z=zQ$CujBgtuAP!CNcc$i0EEgL-ub_0LSgJLqn{MV4o1v<Gk$&XDC9vLSon
z47ZVksP+kTFW#m;pFk~{K=nRISVgr@pm|+IJurdhbrto%1e(`X)B_V}^gc*EFoDl#
z`9Z=Jr1>}X`PEd{t5nz3ye{b(E^DC*$(DxKsD-KgUQeMmPx0#Kk^W}n4We?IQ#nD_
z)zQegK)8-tE?ZYht(9p!Q*TT2sZXjYS2dOYDOpz2oSn~SoN!+L7;+De!g;bh&%fg;
zPUR>~AS~f1oLA0p4M)h^NZv;B3X)e)UKizZk=&N@w&gPQ$!7UOjFwoA;%4f9k;~F>
z($LHmJIPz2d55Fe$<k08R#B_cNPdjud}Rl>R33+%K;?U=w0%^XgDfwQWh>IOqN_Ve
zHmx}dCoK(G`VqFHEB%yk9bIEPy2f>MjqT_f*U>e$qig(}+R&P}K{!eCG=u8uEkiFy
za1^cC+MCKhLG9_y^I~0aasR_hkQ3=Ddec=D@_Qk>IEsaow~+Ggpu8RE>{NLOm-$&%
zOZTplBdfJE)PA}a@ft$<-ZHD@_f8zm5i+hzyn!R+6(p~qyu4L;9HB?sgcmrnT56k}
zM$1yF-A=vNmTEslwePYtRAV1%!}nzWKG}RvXTPU8yMnH67wK1!eg);)MY&dx_iN5k
zSV6ri(a4!i_fDcdxrX{7gD}~;Qhr@>GF{^})Y=>AE`-osxRG+*$Svgx!bd6Bjg;$A
z%5@{}4anO_UP1B-%H<+^7s+8Hhmnl~^0OSp8|!NMI!^8Ult$M9YVDJjOxL)ddZVxG
z=Caiu?)`)VbbqJOwbu|HpkA6wE&qn2FqcZ0OO|=mavIyhc(Qzx>gr2%y-AjDl4UX3
zyh%3mWvs>0LmY+qRC{acy?DA8tt}1pOd^%vntCRYdZsn?Od|D6YwDRq>Y3Iw7fw*m
zw5Iuff+J+!OE*z34W`;nsw<f8xJh0vfy-(I^+|%Ip>Nk$C|kJ9>w^3k<Q3K!qw88t
z_VY=z+S1UK-bc8Qu6H%f+=VoA-=UsqLp}2j*}p@UJ<0MNn!jym{vMP6!Tl9S;TTyS
zQ#Nu9;V_Ou4dF56CDOb^@&J+tkbE1-w~_oI$sdw@oXR=QWg5>dcrB`pYHUG0-(L9_
z<QY765ZhDj=QyvHT5%N4SsH4|t<;8U!lPb%lv^sPTu&okRo;i@07p^fd6gJt9pn&Y
zHS{Ny54cQa)=?WO>8k524b}1j;dUy&j;?V#U1J?x<952nI=aT~bd7b?hV9gbI=bUM
zl?|w64M!o^JN^-6NNYI?`|A=oQY~w#mi<)PS}JWnm9~~j+pjF+^N1tb&wFVm?<GN^
z^*T~n1I=5+Gb73S9pib0aU9t(uZEZZFh|izSVZ^$zk`hKpcuiC(H#`?I70puauRP3
zqr1kA$+z>839G4v4^Umz{94#|B+sIHzq2%6dp|nMYiva=IYd`6jIQDk_0^}`QhJ+P
z3ZHu03>)Ebj_jCLjJyvLF6Q@9^6>kmoS=JWvC0sVS8_xz@m}3aHRgNqCDOda&(a84
z$M1{Wj_e(jcdI2+X$~r3A4fTqN^tPJkY6Hs0LcSLzK!JDNdAyyT7UWdl4I$vIpq1A
z19L?Ah&`pDH2z<sdWX{7-)6O(_nWkh_l&fQ#^jx(KWNF+l7rNT;|V9w*-dno7@aVI
zTJB3{htZWfl#gl5@Nsw_jmZ%lnKh?c$R-~N9EF=K4c`+)qMbp6N2r8*$tHyE(JsPi
zRLd@EPqfwl)Wf^19;W%Si~1*o=F2YXpAZ`1yQqIc$R|wW2$}a)BuC*BDt`%$oKL9a
zJzQ2k;3)2~G`wEr1OBuD@&J<g++0q1hg06=bS;}nvy?QOX~u1)mM^9L*-Y(RN_n4?
zyP>pNj>2=^xQ1H>k>w08KFV$QtQ0r!K9qJVoNapQIxrs9PUWc4wQEks<3X;mlV&Mt
z?3`C4a-{f+>xDyvB3aI{kZa^4WIsoF4_CK>?%D)8JAuwt@w3WFx~FHj9_+V@*e@^n
z4B5!s2L6_xJ*F1Xj3bXhnmW>K=NkB~mq;dW!1cl>92w;m9Tt-PK5j2>l1I>3<@ylP
z@1osp7}uj$U!q>+tHWkGyOe4<PxYQxr}MQyZ4Y@JX;zS?9ckVsj(wfQ(70aM%@OQt
zDsc=#t^tREy%HjGAJv-ltx2Cq`m5y6`8r7Duck5=5^rBkbuHvJ;v$NhtZ4lpjVm{4
zib>-pO$0?BzDf|6Ns~@-JtKdc?tLN=hZ<X|*F%1UN|;3@9H!?Rk(Nwzd@sc#H58jX
zXvtK<L_XgU$?~;tB8|PTDEeE@QTU2%?38N)<qD}QXZ*PVuXhZuSALyhf17d_@Eejl
zQ#nm3Zt^8fQ?8M7DQ+6YQJreZq<_zfqj||#D|ziLXlAXVS-gO*Yb{;N0%}hZ<y}JM
zC)M#aYa6w2BDHXv_3Vgp-9x$Zsm*h#PZCKp*NQ;-Gdj77um`o1`b`=@xST9C3%R{Y
z5uCn)qe}6M`V^m=I^(E5Kx;icTTq^-d$*LXt_PpFvb9EE<bFV<mTUC<LA{5{N#bYK
zk2xwExQ$pzG2;=6{f|=QJD1|kcdREHBxhOA4JgVcOJO7Bdee$D%@?VzMQGt`^aNvx
z)n<7CZ?pV3m#H6i(iJVI{_IQ7E8eB&6)NvH*?J~(y}Fe~IFAhp;YqlBr}tS6m+vE+
zBi^SImdy1{C}#I1eGKV+39GCq-YajVv1j%F+t55sS2vN`vxM3+k?y1Bjlq|~{w%E#
z*HcXWB0a^T=SA{5im%Vma|79W9;h6lk#>a3{K>8OIB8xX&Es5y=$>l^aTLyw#`3hZ
zatY(Dadq)DFj?IR{RVY3m&pSRrh4zBHVn2jbs}K|umxcWp`G$hpuB6Sh3`-chf@hN
zsD$BE!f<-3@H9OG8E!qD<0Zgj^Kx2|jfap~NY4o?sWirIq~3IA`_NO4-n@MEZeG4L
zfb5^68b6>KpR+Vnaue#$YSPDWS?oaGYzOIYq`uuj8dGb-*LSs+`+03Xm$k0c^StB$
z>n>246Y8cDa`|dnFJ7hRJXiB_q-VIj7D{b<hFTItB{Zit1W`X^&=b)MWHX6Icnw)*
zah@jIIEq;`;{rL;28ZW9IaLXvH3Awjn0S{+D;lw4<v4l2K;kepd~^w)difz|fDu$?
z2ysR7z*rGN8Gp93p39csCLXnyxR9I1=L{~(2S_u6Y-U&thswW+;(~b`<vijQy-2^9
zul`bN;sA@OZCkik(b^E-*h1xOruGcx{y~W&U$KpR%U1Fj1;mJSVh$}h=TU8n9UAgf
zVi58Fa~#DWVj~-^_(IDihQOZ$Iw(HcNAbmKI=h;#sKROk_ZwOpYUfPOe-K;o=%B=l
zRwTmZ7raR9omgmFj*Q|mF_D<qKC;<Ix$Y#Jlf=R9B%6a?w#GH9sm5;9Gpp-L`5mD)
z@1-_t6m6a5D9oXrq!<Kukn<%6$y+Hp*i3A2DP7%Qx~}`_9^Fs5Ug9WS!^=^si38IU
zX6YJY%f$JmYpCDO$+&iD5l6&^+)GTL5@`Jr!iew9A`Bz@a=PPFsD;P4_Yf}7xK+tN
zgwTx8X<pY6E>X`y^DmBwzj&M15`)dPMkCi_#+@aO6hSPmnC@UPl`xff6n|Eb$5Hao
z+GOYV3o;)wCpd?cEWZ&#{j-v5Fl#naEnKsWqQBYHhX+Z1ist(S(rhBl1dHLQv5a$m
z9`8?3pXM@uHw{ewI>w{Ci;!<8%iHNnL&y)P)bdY=tt}z8_6fCT54G?EV!2x=*K%sl
zaH?@Rapp?m%$rHSlq`49Sbd%B$&U%0)kNsuC)~q%KFXX*xsFpV;-%!<hmmj3Rymg&
zp+17%J4N#)mp`?T1NajgF_-54S$dkW^Z&8;HGokS*Zy-q_amFl&3<KfNqLk~ibyF&
zq=<PDF(M*TM8pUbX^My#5F<rIiijztlu|@Q9!A7K5djgAA|hg>7?Dy+Ddq8yQc8J9
zDW!;%A|<>3bAB_sY(mgjlz;Kb<(zwR?#!8)Gc#w-y*nTHhVu`_VF^!}UlsgSjkP_{
zoJiq&L!V=ix2qt>4>^yRJPr<%G+Nh>Agvmb^Chjm#PZj(BC~=xZ<#yTVw;aLEx$w|
z{MR|WNT4MTL5ip;^Gp1NP~fYe_E)Ag`L*GF(EITXXOpCnhZu9LEzB`uNWGi<vWG8?
zufqp;gma?5!)3JEqKxk#WDKPXqeO_Soj~4hKv_<(Z)S7?y#xFOl19j-_%5^*`7eQ-
z$&gb5$z73$OOdO;A-Ag`p%r4mlhNJ-=Rt5bn{2m-n{2B$!_R5XUzuEQ<GWUKa27M|
z?g`Ffj1<F=%1K}coGt8ESogrLJ_<VwP1?huCHxL(ms>P)xor4sO_AI0;JelU{w`;I
z4PWQv=rB@#iN(`R@|!2TwPJkJzEge&OIDH`v=G<ZTo&6ebIZPvyC?f;Rs!D%FGH)i
z60IVc_%TTss=k@?H^7egQd*2}<A1`p!Aj86q1%xBP74WzsLdN#g0|1Bp^!@$Yc=4U
z!gskr_$q!YzL3Z9jcz^iyj=d)VDUG`FT)0&f;ZLMYDrHI$o3Db_=1(kz9_=H08S--
zUvM~#HV`#<3f`2C6vrb)AMAj9Cv6J;9`HlT+hM!$8;SAs>v&oLofjgv&A}-|_(FU;
z4dL5qq5Q(nap|27o|t?G1b!Z+i=cF`!*?=RV^$Tuh#D-}TELPG1Cnn*T9+fO8zcv@
zo|E5@k+&Z~Z~wrT{6!YNCxf#HDb~PSyVCB!9Qy$1na~@@9fpuEAmj_kZKp(;;P*`~
zdlKJ=V|cGj!h>qfvFu{xuo+?<fSlJM=K#LSZiSUz5B^f{SEFTq6?xu_SU+cMhS1|)
zK&*#=Tl2SNl7A95zdKq2)2Hlf1$(oEwL=&sSHYV)g!+9N-%+nKn=lQ|ufTa0oL?n_
zlvXp0k8yZJ%Q2e23kkIdUkh()G)8JKI4>cU+Ysg@Sg`Bx^h*fYRMH6945RQnz|HWj
zZy(RK(0iHujUtz^-U}hO@Yg>B-*B`o7{?FtOc=5}rA#YZR|@-I$~3|>gI}>xeeGOC
zbZ1C=2y*Vnc%2VV@_z8=fb(^5=795G;LL>=8nyVV%Ut*&m$3xfjW0-e(>E>yU;cg_
zhZl4Sp8f+q<Ru8xjIE#bB4a~-F?a{xDu<c;E6G#vlc(WL|0(4E1H>JH+}?@&`~mqH
zfgJt;Pp8VK9A4~@9uDyJ(B2}(0>2LE-(;HXFnepI@YXg%W6wZ`-Qjf)#@D|MsEZNc
z{1BY?@Qrsl#^UY3n9rac!WeCWV=DjIOR;_e+?(@8W5jnb&QgkIe|$;13i)Xb{T#*9
z)~c47BWq_1Y<q?L*2i;N$P*aFJrQB<1^>^<%ZY|eV>oi_hMeihRR`p16Ey#A`AY%D
zvMG3DU4%E*DF}ba<S?(AWDm_IsEb~BH+hfWP4urIMSS1ZzoOa+ds)|@bw%Y{2{d^<
zH2E8FUPr8N7;DjYhND&RNc~&xL3TfAV*<*Eo@I{$=WT?6w``9E=O4-INzQ0~Low%>
zFEEV~Mewdvgi=@Gz2J8o#<~_^eutiW6+gAcSYwz*n67AJ{n115o3DNZoIa?RBhqWa
zw-J0NA$kyO)F70CQ?yu`25lJkbFb9ba$HM;1bkUF+QTPz(9=DromcVHqw1Z*{EV@F
zDLBm$W*5RVmtT;~{^;HPnMSVOMwrXcZr=vy74shG{2r#|?*fS{xQ}z*g#5jJBl5Wf
ztz{$fmV+9>+nj~BIUR3vdMA^tw|ScxV_JS^Lq6wntI+%Kj5TwD@i(RszK`)&;yi5d
z$THKsj_5-?|4N^UREoI0+4Esbiy&>KIhg40Fs3$!Ula7Fm}abPN9m@Zbla8hGyocA
z&U=a@b<SmZ27LMUdIfq}Hri)_X`&Q_^*=GTUX?U*Rlr_>bvt9SR8$rX_S5($u#2%B
zku*|#4teN~w4MW}92(mPPPy!Bu=58^{wg?#v9=7c!U%)!fyO%6<W}GxhlEzh`IE@`
zpONz?!Rd)GD-h;;c+-C$7Vmp<v_ijbhJHN?K3FSgvI|C*B1uEeFmUbwXBgh{-b0%&
zLvA00wB6uz0OxM}im?UX0iIW0H|KvJw+dr3V{IQ>b!{Tgi_?G0Sepnr`%Djo`JoJt
zQJ@)iPLJVhmHfSOFKTT7@-`f${tilwuZwyqINiZ11*eDnr4lwa3j7#wAN2PhK?A=A
zXD#p(>X*$~MDIemZe%+~BX2%NWVU`UA<PS~=SjqR4cg8}&R>It_X!%~#0cyY>(Y*D
zf7ecFN!{^Z>F00$E%gO_o`Akwe@TCx_bAnWt^Y><t-f8~ssBO$Bkw$_|BZJQHOLDy
zEW<W@yf-NC25Pk8J^zhDqsZuNTw^csJ&Uu7$`q6<7?Y-3ia}xsJu4^Pcu^syi0NXM
zs1#LVkys{HiZ!BI)QHVuo7gG#i2dS_I4Vwv)0(ciHNO_p;#xDUrPf9(5GS;b>3OMY
zb}i42)O*3g9hcwQ<vb=i`w8DfF)xg~1Lox0FO!~ppz)30sKC>Xh>KZ5@*PpDh9`^P
z?e$_iOQ?AkG_rA+E#SNf`k1*Bt&E>05%-YvswBpj^-HAhz_U2z?~w8rFd7e;vl#SS
zXyf>rMHcHWp?>Y8nhX$!G(oiHq4q1r2~*?}H!AW;yI&J+#5Y7IQ7DQ;vA9m$C~gzC
zi+*CD7%Ya0`^6~npcpG27LStN9}`bvkKl!33F-b-@tSyD{6cIHo5T*%{{M*Ii$96?
z#4+)KI4M393917_GigY$HJ9eqvb7w|q55d5{Rh>_m$k2Gt+ZZz-jOy?yF(kKm1;w@
zyR|ayUhR9@Xzlyjc<o_rg7%0uQJbVq)_$b@SevR%*XC$H*H&q-Xsfj~TDA73R-?VG
zy`%k7+iWj!w{(Av_i1;xbzkN#aJP4Nau>O;;r$EUgWTV7f0ySq)Bka#2wU@M0WC^-
zX`!{&+G!oMLc(3NZdy;R51=3AXb3$k)5^6ml$Q!^3Z*_vtJJErMcOiLCDO0aHf!6o
zo!TD2e(ezTl@r=&UDw^ZUk}x};(9Z^rQSv_NM9ZGBE4Aeo^kck`|1PqQsNG+bB!P<
z(nslI^$B!OU6b^w`V7K+&DQ6V#03;?F;UC)Rr*?ey}prT4%N3%&)lW&rNZ~q>FrN1
zVXw?+ZQji-*ql$enrZ!r`M%&8XoQVp=0d?=<S3-r%~%_XSlt*~iy50Xa9eX6M!LJ<
zXTBr&8z4(K%}?z<h}9doJ-oq_z;2U$s$IrIY$pw#pU|6WeS+x_E@NzrH1<Fmg%leZ
zYt3aWaJDfv4>P7xFs?Fw!li(mVvNEyQVyP$Ft#Q_!b#vgz*B%%82n3CE5=4^#`;=g
z07e<M^C!UxSpAS&{(kObj@ZVu*v**2Grf_+TZNF*3^LatZaag&qPH|=vz0Nbkk6(3
zI~3xs0PY05U*&=662zTr@UPgV;1?;pls#=Fp^CMHT&-eS+l!p|L`3Mi(Ax@KX#Pq5
z=|X(5f876>{o`naaYhN@j3t;rFo|HQ;>{qKO)!^W0rSjUXPh(9nfx)pVWv4VojJ}t
zXQ8vySy2y|x7u0fY#`X=Yz6Fac02n%1~|+?=ZJIMIh8BU0RFafeYpXGXl~Qo7P+l+
z+kFghm=3vxxm|L*<@O}#liLq4D0fJ189{mO7|`Q$D{`mgPS2f{TbWyxyC`>A2Jqi2
zbJyfn=hozI{utPnyEAuB?*80Exkmvfa!&{JfIHw<Ks1*v5IO_+J055jXh{%P&?Zn2
z=-3G0a7BUQK=(keK;L>WAW)i?n+Zb$BLbr`U~FJQqhL~CYG6iSc3^H`L4&Y3upF=|
zuokdBu(46FC9plPE3o%0I1o4tI2Je=NCeHsK+qd>f{|c8pn0$rplz@{pi{6j?p=dD
zg1v(!!GXcS!C}FXXTj*;xZuR#<d21E!I_XTCpZtVFt{|hBDlH^tP5^93pNF})`1<t
z-HnEQ!Gpmg!Q*GasgMZSA>UaL2t_ji<!%Ionuc10T8G+&I^>RN5cpYPs7t6@s3+(?
zp?-~mL7^d`vQYV1z%s@Vj1N_Wri7+93TA~WLsg+gX;>ConFfBohM+oB1A234TWDu!
zPiTMW5Ynm-M?)uYKONRT4#MuRKO73jGvkMwg<IBvHsON$fVdsQMd9Lb_i(RpU)%?T
zOB>A3IUqbVJR&?QJoYS@5S|pC8lG_$%nr}30}H~7)3!as7N>2cvT@<%;Z-Rc6kZ!%
zpJ_+ZZ6vc^Q+1Nk(Z=wWbe^||cV*^@ZAo}9*%Rvf;RDhJgb%C!OZ_T*EI66R4Q}t@
zlLU!~nQG4wFWo5}ejafmkw|`|d8AdOZKQqRB#$qVPLa;c=dwk*MtVegM@rbfMg~R(
zvz?3#i;Rqnj*R0mATlvB8Md9u%<VlgEiyA@pCfZ3^CAl)OS#;U6_M4fi^#gj2DY6n
z6R;_=HL@eJJF+iwFmfbvJaQ^e<k@+?yg*)*^$VSnE?I|pO=+A|<5^w{8h@0Y^IAtr
z^4jHfU>SH;nAat*TV78dchci*W*sS+keeD))L6iI;;}KWPhLOHTi&3&A*p&sc&a<p
zJ&nse=5g8b%JRyYmp6vS@Hq;2yk1=ocF1v=$19A-JO-!6Vp{>VAC#^B7&}Np-uT=~
z28^+(aaBQHMeb3C)EEg!jg1*&Wt}lHHBKtXn?mCtkA*z;(Ri3QJy6PkI6Te`m5{bs
z1bMUaDsivMTa>pfZzcF-Kl0Y(Rp-^@ZO+@4w=-`~-hQ-W>cc#Kpx;tI;{KF(DDP<A
ziM-Qni=ukejee2p2PwNqZHwiwos0U(HmN?s^~H7z@s$lct8dlsSIWMm@(&qgH>06w
zoa;Q=EZQ<1pTkpsi?)dtL_0=dccR77?$KV+zHGx`m#7TU0nyUv(C7%n`#2k<@)aGW
z?0AYlCL@f>Gs;@u9;eE~b~pv+vUTUMr_r(MK7s0?_zaw7Co^p&+sBlR%&><X7IHWY
zJ!2h2CxwfmQ=>DYv!inv*tg;OW}hayAi5YlvRTpP(N)p4(e)|+CAu-XCAvMj3wDhB
zj_BU#0r(SS)1rr?$D${riIh(eGh<%1XBhw4Zy;M2b7B!5qhtB8=CM|>wz2lHPO;9h
zuCX4m-m#L{z}Vo}u-M4h=-9Z}MEGOMUUFRcX3B4Z&!c=4$Wk)+S!{A_8rw_GSK6;j
z`C*AOHW-ldVU+K|ve+Ms&5X@qe<wCCwlEc+!*hA?H|Yz07L_fwG`0df_8U`>@)I+m
zzAu>a{W3x6^(?<G1?-EZpuSI+^3fXb&0?!1e5`NAzE`IIMLt*B@5=D8IIoCHVNyCd
zt8Y>Ni>-@osNb(*n_^p2K2~f;Y<Fy5>>%5sRJhoY*l}*xu~Tuu?I~@?I1KkWYJYr>
z+i_n!5RZax8gCJA9dE~w+27(F;)QG@;$7n1xP8WZ#`~P*#}LH(#RoB<Jrcl|A-feH
z5--EOJU%AX2f0tg$Hyz;Q{vOp{g3)pd{(@Y`&+y!z9_ydzB0ZhUd>}q3b?%dj>UT7
zGRJG;o8#N!J6Sf{kNBQAY;Y=k{80R8{6ze86TOMMiN8sRZBfP^%^jN*H7Vxtj{$a)
ze1az3u}|{=w#Q9Mn+)Z4%41=Z5!kI6`!ut@QhPP?djjvs%zEN|nmK%v^-VTnujXA%
z_OcJi_CIBt)4Mh^kUSn|xNY<9aIAN=cXK|sv;5}ytyqs-kNIu$+v8cM{LU;RziWOE
zw&nS~^GosvX6)I_J2vxv&1$D+)-UhY3_C{U=RKQo-;}?V+e3Qq<|FyXdB^5d`(YoP
z{SV&1nRjpIy_>;THkWsC=KY&lKKGN%eVo&6HT52l8l#B*(vUBeVXx=%FO6Xye_Z7`
zGD4U~8QUSye*~S4T_v(We-r!{!Fg9`=Ck$!#tHtN^I2D!(CjA6v73O?4^R7nE(TpJ
zX%1-~2Inw1hrvmLlVpx@kZI$fr1`1w0yr-)$MP|4`6P|FrxEuwq@8At)fr(rGe<X>
z)=fzx{0xMj0nShG^e2+W(^h!e3aNh^>3&<%$VsWh;Ecr6kw|wSVhv>4{%`2vzmdb%
z$VqESBX2HnT;TKo-9yrN`Ymw21v!6%oWDVSbI5OwkfjKNJeVcmmq=Rb3itr>b^!T2
z0LhSGNeRtS(kX~Lg*mRKOuL#&8c)B5r(c7FHz4f|Nkjf|aE?RT07xEyJV4tfv~Bzn
zVSWkzo#5XI`T@`nAj|}WnE<*M=w1jj5n(2R9s_y|=%+zH&9sJAq{&u<wr8U4=|!m1
zBFKCPGT#AzFZg>wLq9t7qaOu*6ybk|@V|rpZRp>I{Kp{wG0;Om4*|Ux^kUF!K(B$E
zw;<;&@LvM|CGh_W{$D|(t_{?+aXaYS5gu*QM4L2f!LLPrP%c}RYcu$pK|c!mQP6jT
zz8m4cf$-me%=VDk9%0aa%&8LN=`hg4@bsUM@K0#wK4|7X@Hc?JK}tglxfZdmMP2Mb
zUF<-}YJ{u?{}A|xz@HEPd>Ni4==qSJ4-V4RWV$G|E=xTar5KEKtB_(9=#HQ}f-VGI
zi15&i4bAAAAZHU&|1whlGSYe<X}ymy%MfN6Xp~V$8TGZG*CH-joq<+otww8K4L(}3
zAzSh@pq~MK3Fu2e!#WwTPS#Asoe8=IbPe)95BZ-5dK>6%h<hA;Z31IW+R4ShuvAtU
z62h_#fPWL>-UK<YfhKIADQjF>jHeNIJmQW=PQD8ItB?bY8PJ&JM@T=kfxfAuZ|W^U
zw}h?mz;1XTc|TIw4>?O9X9@UMgMT$-LXIW-co*=yfcAq%TJ9yBt{ZXPD5D!?v<=j(
z0Xf%0&h^N{E6BquphKWT2;W57bLemrWIh3DPaq`hybE^T+>X?@Lvjm9Zh=z30voWv
z2I|g0-I@I`-u*Y^D_bgUCenHtAzwzwc97f-`9XiN(O>jypu=k*c_qTHM0kt{rW_H_
z-!0kSha${S<Q$`t3!{<^yKOg>{R?^c6(sx$97r=DP5%*6{1H<53&Q*b5*~+y$3bIc
zwB^W%_M@Zy80C;tE^PwJ_+|9pWoVi2BVE`EQ`(9n2!8}={TBS+f?fc60m5MPF);cV
zAAtS<@(Yk|0rCUd25lj47V>6Z4mp=2Zhyq>4;n4OKua*DgPsl=Wi(JmV>am7(Bu|q
zatm78t!Nv!A}x3?7Q7b=`m~@=``5_NuMrnD;zEtsh-)LRiL^|a7Hq5m8*5w%`byB>
zf)1Yo=P9Iu@yn9F(-n|#1?a0lUj_PR&^JTER>a*3jlBnry$AY3&>tfFB!r)Y9DWx$
z{4V&nfPV|pMO(GdR;>=8J3!7f$e9Kj{ZvOk)lq9YYRw!CIio>C112<JAfJZJCu-k7
z?HjPDhP0@!fqo5f??K#qK%-xq=+{OJVPeSty~zK)pwU}x^i~(bxDdufD>BiFtg$G|
zScHeiXv1SPVeL&=dlO@&iLuha_+?=HvT_hN2VnvT69A1d+Qb-bz@{0nX$JCUAa6Rn
zCS7_>@EHvF3>MO|kd`?Laz=rE9`y5|7lB@c@UTvn^g_Wmz&FqW4YWY(ZG?Fn{5|0B
zL3v?IZP-!+K7auqKtG1O9Yb2M!zS#og)o-%6HqUvte4k8zYaNG$nipcCFEBk3~ZMv
zZPz-`>kz&-!uJLp2OS3u-5SuX0bkL8uV_z(%*n_nbfrsOp_iHHW#+q}-vy14+LYc1
zY@i7nsKJ-h;LF($L*~Os>mj7|5ageN{8Qk=b1>jJnByR49O#{(cOpEjjV`SX+Pr}_
zFK6k9<Kh(0(#c*-_}-71rPD*)B)(N=uFl<Jm?&%XjGbSK&0<TPc{>NipT%G5%-%86
zGj^J#=jz;X)*PKj&YGL^YI<hQW^;=9WAjOKwz=AT)qKmWF%O!5Hvev(;CDZ9fJ%8l
z9Hul+QhKK5rPLx?zSf*@E3K{8US8rbpp({F>#D9ET5qjH8>kJ|hG`=yC*!n<+GK5-
zHk0x&Pg|%h)mCV$wRP$m3D}@*(zdE=hqhbWrybOeXveivy3lRirw53N>P__)dTXNE
z=^gY!y^G#0eF?p%-be4J57LLIt4uG~$56QO$S36s;phocrF5v2@9O^}cohQAd6~;Q
z{~67ArMNL0^J{eG=zj)(8uR6x8lGN@`Nhm1z}VWx*lY{VF>?!Mtg)Pt;J3j1nuAQ+
z<p?tbxEtgjfwbe8=Tf5PyzqJgAJ4DR=YsPCH7};EP_t>o-!bE+`<eMN;uL1kgfN?C
zDew@UWuq-%Y5G<<2S@S|au#SE5{>|m23}-LL;VZnVH(f+!R(bjJikV-!OWNTpxYa-
zumprpV$MrY&A#CoE`Q`ORskfOWNh?C++xhH>BJl@XjZZw5G#WDGOZA1u9{!7G~N5g
ziV58N^h*Vw!*3EVpZeW5h~{3$eJ<70hKYNqcRfZuYa#Wjm(Z)YPo;X&pT!~SJr4Do
zUg$A{&|^lT$E5nnE81%4pp4|7ncaBy{Kl1a<~W``%Tcd0)3F(5J2Gyg6%g*I6=}tM
z2`w=r$+Nq9CAaXq2<Q^70evge+I67&;b}4G*Fo<@$Z??EpgZB|FA(b#`2Pid3-Esi
zeh1L4@ze%=7w8{K2~2DMgOG>tbd03&G$8W^&b|cCXKI5m0Z3>ET#BbVB*xP?(`vTk
zX<bK6e*KI2PXA}-J5gV9w>ER#t<SpJxjVQE-CfdGH$KZ6SD&-4e(phhay70pcR5{S
zh*SR>@2+r9p=&x_vv5@cSMj;i>RRSr*}%01@mIR5)m5Xe&F*b<?IhUKz_s6f$bB?@
zoj_Q5otBqJKkIUP{GN~}p1zuSTB@tfSyzFlV=66Ak*C;G>^|Y?c-Gb3)63J>(--Lt
zz*XuQN_YgvP}isiq_^>mMf^4?&3Y!NYm#RwT{8%JHE_*#Z}ZGeT@-6U`dTcnvo+;e
z?pZ~7TARMsdp6?QlA(#zwcWFe+Cu8$eC_odsCOMEIOaKtE8$6aP09Cqy$<0>x~&Xx
zS9|ll%^SE{dE0v1dpmhM<Lc_|p|0NE68d`}U4y*?GvuT%?=a5<KA~G(CEn4gOKE?A
zr#rWA?>MyFLEeep$=t@g(^wPUncP0SbBLOU(jM?G^e#n?mO{FeL@mX;0(I2UyV|>s
zDenf>zIPKeeb~E|`c9!|3-z0x-W~4K-rc0-q27HY;h^^jwdLvF<J8($dQW*4WC?1?
zd$Q~-pC>`-9-)>};~AP2$ckn)^~}v`k<~h@9p#wY|DLQ4DCKmjvE}ZXtir6O?jc!S
zvbvEh?z1QnLdw3vwOivZ&+6%I?iuB7oz;i<+bCQY>UG<)`Vm#=otHJp-7{-QR#{eg
z)|jmESrzEZ<?_m!lEuAsde*G0O1i4D7Ey1ll07zSS=LIVMk!^jq1>QfX4R17%B;;<
z+p>0M?a87(m~}|?Kkk92vyNtMrnWW|?QJ7HJ>hNZNo1Y&Z1m|qx6kkG;R{jiQf+yU
z_~O21zLuo91K#G8r$e4qzBaxBPr}!ct^n9TC%+=kNnac-kXtb7io?-GErzw^D<<ep
zC2!{5<LgEI(Z0UE0lp$%sgKh3jqr`~jrC3NO`>{P>YK{#-8aKG+c(#@z_%D}e2A=b
z-*ReegDKTjS(|-p>00mG=#B72&$jrc`nFSBZR_n!Pj*r6_i{TWJkWQ*ci4B#cQUKO
zm+(x;HoYUWy?n|%mo3}Lj`*fhIY)X&bNRCKJ)!L8*{w(`EwkIYyHG2QQ;zq!_hh%v
z?nHLxbarR56K%3iWOvQ(k=@%9&o1#T&K{UOnESQ&2x}{QSoX;5(LQ(fxa^74LdkMa
zi}a%noF-dUAVZME$=TCL7F#>CV1$H~K?^?ODbAkhK9oJjqi4^fCkrTCobod@dm&LF
z->U4To|fKmzNy(OvR7xX%ih3NFlEWIH+g2TrSr}3uJEqN-kQCG?A!=x>#}!e@8i@s
zrR;;Gkt1x)2v5yEl6^e;lwbI5zt6qRw@O+r*sjIiP5wakZf_5Nlyl;5O7%o-hyHHi
zZ_VvTUfv^=?>7E+Y?J&Qd`133ZzuN<e-~<32Pl;T*<Hz6RQkJlBmSQLKJ=uYe-O2d
z5&j{5JG&&i#9!uZ>#p>6_DprJ^p|@|{bT&&vsd^ls216>x1lj1;Th|n;+g87?w{o=
z_E%Ex*_PePU*#>Kb~%7*Y_Gq9dhk%PSp(hM{EPg{{3|^h{cHTy{u=*gceQ7+f17`&
zpETv)??2=}>KW=kK~jhMPv_{Kz9e}-_GJGc&(Q3W9CwaCCzKP<X_nKH^4O7NFD6?*
zG^b5YK~6{awwxkQo19|mOG7*da=KHT15`hWoL-)d*<Ew`QXQ328|msj;xF_J@D=0?
z$SKX~OL|z4Gc;#J&M04-oUu6*awg?W&6$xiJ7=u7E#2q(dgUz0SxljqQ*K-5tjbyI
z9i6j2XJgKmobCP^&kQfUbtQTy>HX7e$$q2RGVwIM6I=}+a)sbkf4e|WNW8{x3CuBa
z@TPK2;yHc`0bK-~pto>(8-pB&v341U(T_4s@A4dGHl+OlPZzK^Yi&b#4Nt2$6+>s*
z{t`G#5#EjPuk%ywIOypKtQkO<-iepk6K2|yZ&A~LTLV`}4(G%i4{4)Ou9=`ap<Jcl
zECOdO%Jmn-dK@JhixiuqEOSwojR;u={!rv(3R3sVcQ}@572xT5;5o?o0?^$Nei!mH
z44l<6UBr!mzX2T7h_(Yd>84VQLH={RhDnwk`8j})QRMKa33`ha>lho&5T;3zzoSg#
zbj9D1&k>NeOO>5DBOzxu!W>|16oK9i{ye;QEJG^ek;;Bq3&0%^ek}8i)8O<$8QUdJ
zV@=&@)*J8?#@Zp^z2M{{%mL5=@K=NL7jSw4cLIMsW8+$ApgroV26-EU)Q2G5y=XZm
zO4LfWpX9CSceEAARe))Cgt4ncwpG@Z9Yw4IOj}(M#s^M6*?KvynJ*=9d($RCW=VqA
z)s!Khi$Hr5w{aUw@Jf{+a8Jalfex<&UCJS~<A~J`^a+HlfrROxr-Hu&W#0^bOK?8G
z)5pNs1!<3gb2UQ#jWNCBqdh<a-H`JhD8(O<hrL|yHd>=Tlgn!!W=#5d4P|)^{rx%Q
zki#b+p{=UZ*C2s89npV7sF54+v=i`tw47~_xm9UQ>VflIj8g1{mLlM11D7CVnM(0A
zTH|T7>SJgjG9+uPDbr*<j=>Ian1R64!MP0~<47xxkXsO|24Uu?HpWj+q7_YGtR<AK
zi-C_mi`p-geOy{OZcFkFUA<)=p|@!6xrAN$Xi=~s#zDj#3=F$xE{Fb)a=ON%#P87;
zj-fAbTk4~1(J{1hsb}mKgtEw1HwBtGgfK6HUxre21AQa-3sAZppqGN*HL)GFTm^b0
zG=Gf0kt4;P%JLNOmp0VeO4R<Zz(<MnHxPF%>UxB%aSlVh2J5U)I{8gwu51IWLotiP
zkQI6jGC5>K+GJ(7V<_osC@ITa30;Mlwwpt%qmfD_@>U56y;a|5IRnrFTL2G29u6xT
z&bS2fH%r@?n2nk(z*sN~IVnJRfl-5HR%n}%tHJ0gydwQzlJ|)0i@H99Fe9aHM?R-Y
z?diWnUw#d(l*?5O{se@482mmc<4oA_-rzLH=pgmH2-uCM%~0MhDCr*HX~3r;xfr$I
z8MrxWDz%<1!0Xwv*Jr;azF5!pf9LxSjd4zi(42vEr}pX$GjpAR&frGDFoKZ;qt5~3
z6iiewxsfo9U}gg_N5MRTg^h%z1S=G*R<KUN26f*=u$5p3!R`iNAHl&!z!8Gu1g9kA
zl16jwx`49PgIr%d2z&yF5;Sc9S~MV+p>;iI*GT9<P)N|_9MDZcPX&D%3H=BLH2^~t
zlo6CS62=gWS5To~ih}9tK8v7|po(Bo1F(!>Wg}pXl2NUohG26&*wz5-tOt8O0qiF@
z)BqeMIMD!{t_PKkgMd!pR{f&^;Aa6pK}gZ@MnW@!mJNVgK^uaCMnXq|q6{d`fK-_7
z>fVc>FTsF}v@)So-G?>;Mi7ju7k_L$n9u-l+(`se31+DK>~rMjTrihlK?AUuV0i<u
zsvfM(u-%#VHf1Z79Sf{?()J~=(Wz@cQf(x&UQ_x`>1azvp10S{Q`(+n+JIF5Reg)c
zj8vNs?5f+QIURl;*h_GL;IIQ5!Q)HdnB;Sr0w)O)(!K^w2X->(C2-^z5R53>&gG@{
z9?W;r_Bq&`pp`6du&vZXu)PC&$ub#&od`M;bS3CP(3_xyAf;cWPmYUmGBt*+&d@W<
z87yV+vmk{Fj#T-oUr+VwC_Sd6>M0?|#^7j`w{aQq56ZIO@6mG1L)j)O-pC9X*8tQX
zm*+G93!O9LYvvf6f*l!9e|$}im*+E1MxDB2VGHNX7??5MrEL~LaI(5{ozGN!vL8X#
zBl#FXDpPQ&;!_{y@dN#Kt?W-h@+pE;R<=dKb*f*a`a#Mr>QWBuTyaJp;dWG{;wu|?
zR^O`MuTu6U)wdEV{~J`DZ_0>2RQ9(Z`8B~EGT%Ycb#R}u;S*FDsBHv~sCXY|f9l)u
zhQg%s+>kv^!GH`nS6UxuPp8&{`gStYRxWnV*vL$K=vHwT$Y;<2+2|noaKTd&*tg;O
zW}hY`6pw6Hh}vj~+m`ZQLevIBQDw)-?+9@lTqNyTh}vO@+n@3YLhY12<MF>n+PP2%
zIYx)b#|lxJA@Zd{oF=D5X@ocp@`plY%6_KoCELjk&KbX{;*1@IEF}YZq&TpbiyE-Q
z^=xq3hf#KzWwAdNVjqkAozVD<_$yU;+DU!E&!V!0Dip6U1G+T;^?ku14S>??S$<s#
zsxqLyPnYu1&c`>~@6`3bjyh-ju1p_mh>CkCLnrn67Wco<l(YL)X!;o+D@1;3s8ZUZ
zRJc%;Y}cVhvOT5k*c{ofxc%WyK5S^EqRCGURZGb1Z=o7#BSM>1``qT7?Z*&=b}Hy5
z0ez3`R%nm9??2NA(I=?fp`#i7kNQ>UgzRr2(odM|Vc0Flo)n<W`=p+@%wh5^!yzS`
z>_<4R%BjMK$^L}N{)EY23>QdS6eb%Sru>9Ce0MqiF`&HU6NJeJ46_f&=?{?Yl*hs_
z`F>&2LwJPLSD1XeFqNC%6T%aup2Cx4_%M|*Ouk!~{kBok{-<nnn93Vopn!QH*|x)r
zrQXA&hwv)d&cbV@9=RUF>(#T3O2!sx%fsY1g~|5`bKc3%2~)oflYbK?zb2fJ`i+>%
zj#2p|UUhe5dx(&K6Cs}_LcUC-RYv=1CjEg3`85&pX(F8zU)kIU`81KPQa<;S2>CV<
z@@*m|XWDA|JwT07Oh*RFFp<HMhm~j>2z!BrIT<vc_JCDsLSW{nToWW$qRBOAa@`r$
znyFQ0SXn05l*x5ua_yL0H6~Yz$u(kfU6@)ChV>M3{g+(%CD(kZ)n0Oimt5P0H9m4B
zmt4aoS8vI6TXL0_T$v?TW65<`a_yB`b%m8ya*dT-T_x95sTEan1&UlnCFk_Yl~Z!f
z6xOZCby9MLlw2DnS4FAyP;w;{=FQ60PjcOpTJa>;I>}W|Sl=X9Hpw+jYBiHw$0TP*
zLsxRul3cH(Rw~IgN|@Oz*CnYHNpcku)*s20M{>=PTx}#*7|FFoa#fLBPb60o$<;%0
z-H=={B-aY5RYG!o5a##FH9>MUkX#2OR{*KCKXTQNoShDh$u&M|b&p)vBUkju79v;i
zVEv9-xq~%3ay^b(gCkep$d!6>tqoS$$n`ZAW@xK5HCRm}*U`uoG;-~XTs0%t%czwy
zh~>spxh_Voh>>ey)G8RPf0654<O&zLwneULQR`XcN*2ugm+MpH$`rXKMXpAX>rmth
z6uI_9t~!zHP2?IAxw=HIE0HTo)LIhRYoGzSazw5Tk*h+~dJwDxQENajZ(mnyJ&>+k
zp^16dYJG=X*&)|-$kiNJ$01j6$h8}4)dun=S8B*L8gg}pT$iC%WXQD`Sbrf`UZ^z}
za<zqAzkn4MYHbBpRmk-eawUaaL!nkrVBLgTF(KDV$d#3HeFRchYa--o2-(u)OnbTZ
z0W~PsJE)Zos5QB|L9T0%D;nfl2DOSouJuFjkZTsyY6ZELP_9sbG`T84u1An75!4z4
zx%vR>3*?FewblUIlj{rQ$^yBjK&~c`>j>lu0=afTts2030l88@t`ShH1F$YYtq727
z0puzGSTi~EU(Wegv;E~fe`x{G-sG%)IiFw7<d<{!<?MYmZyz)E<y?I^OJDfJLjE<v
zNC;iTw4>VlLTG>2P6%B)rTtTwT2iNhLbr5Vxb-aEC%n3&=L(-5)+55N$Mq({(VOdE
z5dpoGeu)U_PwP*Mh|$fsLF8HG*8L*pZ|1*DH1S{VFBV_-f7d@$T<tIO-zTo~kMch#
zZuF1$KP+zcSNMM*Zt*|ne@)!#f8D=MOz>~?|3ysnAMu}{{Qdjp>_r+^n-a7jXid<L
zpaVf+#=Q$cH-er7eF*vy3?djpP)1NrFos|}K?T7Sg6Raa2r3Dx2o@<=MzE4#4M8<Q
z4Z&uDZ3H_B_7Ln>X&ySq{iwR1P~lGtVd;`@xe5F#Z->;K%3y^E;snhkKYedW&_?E!
zXGx^WY;`0kA}A*4F6CIgWO`O#f&m1jia(TK1i>gN*BVPOfnXBBRDu}<vkB%BEFf5{
z?#naosqm`^)~fql6>n|E^YsK93APYyC)h=>_spI3VjUnj{0Z(UT^u7gDRuct?$Al*
zo!W_&kn&MaijVX%fagZo-ZOX9<sK!MyM{v$QT0uHJO9kxZcfljyl9LxMjPXdiN<7O
z8epa|$Czg<G?p4GjMc_EV}r5D*lO%Bb{qSQgT@i#xN*ujWeU?aeP+OnnoZ3XW^1#Z
z*}*I{y8ybGJ@I!Ry84-e2!@ztX1O`W9B-^PD~zq?6mz;c3s7lRnTyP2=1OyoS#8#s
zo6T+JPWpR~x!*iw9yL#xr!C!bTYf8K#jR#mORJ4lV0E;LtYWLX)ywK@4X{eBq1Fg%
z6rLAZW336+Bx|ZQ!<uc)wH8>50n4pb*4hSPy|vNWV$8I*t7{is4bgk)I$#~PjuCxQ
zT?yM{u)TCSbVclZySd%UZVPB{cM@8nKXzm8$9pL!vOs%5t6iEwUryFROSI>`|A}7;
z{*$RaoD&7sOQ5@fmT@lw-3xKQLAWjW?RgJulEZNeAb)^)Ib*9o_M;d}bclC(PlT-R
z5nh2X&v3f6ple@89wvf+4`{ik^yQ%2%iJnF7Wh7dA(^#*G%qE*SC!~eJnfHM$^EFW
zM7i!p&WAE>>;&z`Q-N5|gEJg)Zv-a?^wo&_0Hoz0CszYo2-5*!h7fKCx*g~OvlIBk
zKzD!y@PRMK(*ivGrg;@(>mKB!6GAe5Ij;bsFj5awA#E+Bbp!njLNfja*=7zSvD}Nh
zH^K~t{8f<8n(5EyL?!z1*>MS+Qk(FCz6|tbpfBgss1oh@Y&znP1b;E;J2-VdvxVrl
zKpz2pm}yrOao2Er0KYw--avAepcH>cOW^zu;N8E4;B)g5AwHor5#ke56D#a8ZV#?U
zxIHjk`#RH!iS|#qJ-Cjte0x7**WW<D%ko_ZLH`r940AK^<p}v5;KAHNIB&IkWuEOP
z5xxqvjCBZkJ`R2h@Eyjk&L~}5;J=}~6?nQ5*aiMK5wZ)?It>0M$SeRywgkyJg{S=y
zehO0D1TCEcei*4=gOF&$E)LlabUV-m_D1keg1!`TB)=tc(iik4pl^qq|7PrVfkvBm
zyYaL?I6s24SGk2i!Z#t|GSHWSzMRi7qwv209RUs_)^*5p0rFgmT7DWO{X3o_Z}viP
z?f`xZ_&A>C5&nkjMbOJ3a~){e&R+(89Q>7_w}JkEbI2zuQ*I~2d!*hZsx`7a;!>-t
zb-nebzp1~#f1SUp{|0|||Be10{+s;0{5Si1`)~30@!#t2>%Yxk;=kSB&)?raz<-B-
zkpDaWQvcolVg7sk<^KEqWBm{L$N9hSpXh(ozt;bT|L|uh`BI)@sK7@MP!LtnG=pX!
zFHdW&Xb#s-(H#^NDxgtYBacs`k(}p)Y5i2#K`K1+hGhI*rtakm#$=>9Uj1D`x!q0I
zK5<YS5y!Ejmho{-)Y<hNm)M=&{XL)+5+6IjQ&_qGyW9cZ*2?H!&h?rk%PWlJJD^|S
zb^~0Hd=B&_z-)Kgsi)5aS0VgZ&=N<19|K>;T?Tp?q%8&hJvhGyy%S-We>qOYGHR2c
z(F6G$sKjNpf98<2=+%7w6mi%tUtaq<=SOl94+A#?Ml49UtabxJB5p1EPwms7_e16{
zK<@y31W#d`YX1kE_aKK)9hxF|GID3ludSx5ny!u74t<8P$2e@-R%hd|aoFlc{zx}#
zFuhrfrE8*HY#g?G)78)JXLYtZb1c4F<uWWi?MLzVa9nv2mu2uZnBHSk@q4GG@L7AE
zja!Wp<94IJafeZEJn8gtzUvHjhB{@=aA$;buQSpa?L6R&aUOKWI^TE3JC8UMokyJt
z=LgOYoypFRoGH$aou4?<oaxRC=W*u=XO{D{GuL^>nddz3EOwSSOPv>-WzLJva_41d
zrSppOs<Xy<%~|Wb?yPg(aH^g4BHtOD+>+el3`=fJZguVf9+_N`T;V*Bd^h>7GbZ_R
z@@41y$vMe6&conO0G^m!o?Pxc3Oo&ArbEu-c=`<JdBD#><}&bK1YQpOGUTrYy#{h#
z16~XKI`BH+^(<d#G8cRot?1I7p^&hUvG@<;*5sh%Am_Wu&B@Kqok)2I@ZG?}fkyz}
z2V4$38u&rrvA~Z2R{;M2_%Yy_z)t|r0)854%>{lIoGRewffoZW0bT*T68Kf%H-M`d
zi*Gum$?qq>PkFCQRyu>ZbX0;jlW$T97!MWAL^CP})5DTSl1HeX7!L<$1n|A8WK5R>
z-w)0xRZ8YOpvubhSm1}i8K=t4oC@F{08d9w9s@l?>451cfM)?eg`8IcKaKp)1%3u`
z=K(*9kX677QI_YB|L4J347>z*DN=a>_$8$|=D)1;$MnxZuTr{X&KtnhjD>F8N~4(1
zcrv+@tdVKl#5th0aaHmvqdd7VxzOn&+S1jYo-`Fr>B-y4w~Z3u+ZogImZBxq0)?Vl
zIFUR-wZM2NICp~{4m<+*-sJJ*and}~<-qrYGYWV#IAerYcuDh2j|F}RPsag20!{_+
z4}hm3{B)%F7&tQ!awg~}fM)?egD~@ep9QB1cp*5?gI)~01b8Xrya4<X@Cxu(0{<MG
zRlu);^9FD=@OsXb&`4+0EBQNT@|EN(!l1v0C5O>p&m^BA?RBDyY9aZH<S*#2e8H#s
z+$z3I7stFQd6Q^H_ch5iq;+a3q;<yS$-~LR6h0(Eq;*bz2=Lv&!+}RAO*1Z6+GYG8
z@K~iw#udOn0Deqqj`0(~vw)ukt^$4@crox2r4`02l_nU!0bI?P%2%%1N(<2f<=UIv
zOO{ENSGRlc2xHH6dqr3T#b^1?psU`$<Uf=D{KRsy=;FBloBUr95s`+1;8|n-`7qB}
z{<ARF3hwV*!)aM$vy*>H{t5JNlE1;dfqW-_ocwVrKgk#9q8^-lHTf!+oBMS7+3%9S
z!~GA*Kcpk`DA7<k_R&S{xeo7!<PD;+|Hy8@ZY%k9WEF^l`eDz?OZ|LNn}-~>Sebd+
zl-!i2-yv^KrIp;D+z*<{ajq<8>iVo_ze@f}H0B@o_WE)8-(Qn|P5(`KN$yJSsuL!W
zOr+_5B>#bX6?vE6q>FV&_05(e`9>1fg{_CUgDx5wxK|-Ox0jS&<8(Dtj*luo`5fY7
z{=uu@JJ)6XXXKUC`J3A-S-p>vn|z-9XetBfpV6i2>EmSMU#gv?!f;!-m9F~#8fw$^
z;)-HXTu0Ui$q$5wu7>jR^W@LPNBzs}%PCp)c<E<s0~_<t<T>&}wlCH8Kk8rozKVYh
z#XCp78kDK}2V}Ps?LI0@gU^1M{AHukQGJ7DvHiq7)hBoq{kVU+$fh@h{$%I}8g~fO
z8RXn0Z0Bz0ZsDi5gmRJNe9svtBJ^(XW6_k}1!jph&TOYjbZ{0pKNHu`d%$vWEqVXd
z;znmZjo`PF#6o`OARnop(T}9}C+U8YK9J};C=EZQ@f{k=N}W<+(EG@Dg^S)v22<L1
zIzxopxr=fTL=J+KgEAVg>0O1M-s{{eJoLsgl029DC}%;++4l&Kc19Eb0p|hA>lpHc
zbbgx=mh%whJB#u?UId(noe3oQ5$6$-LvJ|3;ddO7>r8Sckpz0zp;YK?hf4lqDrbnw
z`4hs^$WPLppE^IK+)gKN$#fob9wRw3oEenj<IdxhlbOy;lJJD{1U;Qa+Q}vD@H@m)
zP9>F&-j=9z^u9z-pCzrip|v1sZ3%Jc?TO?pBMo{<gD+G5S2`;x=RbE=QO;j+UZI??
zc2-lYSDjZW{2FH+<(%HDC>7SVPFE3h?S-zhplcs=odsR{&eFA=p=%et2@a(+Sl2FR
zm~#*1fHj^Ajk}<6H#F{n#$C?+&M4xr#$C{Oc811X(6}2Kcc5_(H12}N{m{6J-YO@P
zeAcxEUFSmAx#!Te3%Yhg*B;XKEaKGHubrV^m$Q&O(}44w^Bk3Bk+X;-v#wpxwHvzj
zI4?Ob5xv4$L44MGHuUa--rdl<1HF5ocNg^Thu&RE@2Q=V+LJG;QEqw@&aphC$@{2P
zj-hwyX;hZ!R0e);p2=^{*yE_B$RTJ$V|X*sQ4|pri|(SA=qm<@QZZDFNbLrt-^nZ0
z^j@H`7EQl`IpQmzd-4|y4eO`nifSEerscXfxi(spE2O`{m~z{kY~mzQO?fw*Yn>Z~
zaC$m7Qwi^I?hx6;bu5oX7M$A4Ahee|sW$F%hLLv5oZ-|y?{)5@)^xvfKP<w7q@jnL
zheVi4`Y>6CN1TZwMm1a^noysbOmF>cDgMKm<17%DP@TL<n(~veSu6Am;J>wcz<eVE
znAc06tWVQt>T~pY`a*rFzCvHEuhTc^oAj;v4t=-2Pd}(1(U0q=$Z6vfHUmb~Xlk@D
zS{v<*4o0ET#pq`AH2P2<8DtDG%8c^#^D)MFqr#YCOgCm3l}44Z$XI5qG}ai^MvbxA
z*k<fB_89w(L&j0#gmK!`O}FVcLuTA;X0|ljm<47>v&dLx7MtD8US?l&fLUq|HAk4E
z%(3PKbCNmLoMG%YXPa})1(ZL!%*Ez%eW|(1Tx+hUkQ>b{=5}+JxtE?CFb|u@&UH_x
zbJ9#$rscI9D`Mqa&8=2eTdTd%&gx`!wz^t9SgzIEDzOGygY{|FFl(eW+8U>CwI*7V
zt!dUwYmPO~T4*gz>#x2Z>*+Ifw^mrIjWO1`lzy!Z)+T+TwKb(jYlpSl+GicKj!^E7
zTc^^`Q~FhRTiCYkvjb^;*VDTlwVT>4jHao3D&6{eXT8|1?RIttyU^}pcT4O29Qw9<
z+I{SP_Mo)h)jh>e--p;`B)L3QFUB65bG|0sD`hWx5*Yg&h$lc}t-OYQDt--&b-mhR
zVC)Abo(66X&X++y1<Zbimi#Zs$GUB82KYY$A8UxU6Tot%{-1%dj$ix?_&*R5`zs`6
z4zUhiV9$f({{Rn!e7T##L_GZ`FjlN;zX!ezoUOpO0{;#8PDsFt`NVe+@)q#1R#;%g
zJiHaP?p(<HhryS-nqkKRZ89+Sdk|PdugUe+<=|l71%Waqu`fabJ3!Pv!}v5-R|~AJ
z7TC8S`7SV40P6<id>>DtEAbFGh^xiG$pigE(6xw*-6;|ug8w@3H}O=i*uDZ7>!g!i
z5E7hP?0BKwho@NQokWeO{o9~tZ72BHaY61Or>#SH?DQb_A<(dr7~59x7h|Te!dUzO
z82d@+SbeVT1MUw#_Bk-*zI2eO{TvuOM(A>NGS*~k4+G1*eHU@%jt;U0uK~RR;pKh+
zO~J>?Zv*);(26v)6SYHzY`ti=8g`h_P-_}mh}Z*+v^2RJ#AtA^;#|uH4gDukM(sv$
z-U5cSB-*p~M{u?S-wup+f^(3yBzDe7+>ekqf&VsecVO%wlFY(WNY=2Ui9m}I|A|su
z5B{6L*dIc?0Y2J^_Bc3?0keOOwk6sU1Yig5=ke5O;auXhb*^waINx+SI#)WKod0xg
zar)O8Uwf+Y)vIK*qo@2{!BR$jq!cO#Nx8mGypEqB9{VKS&ntGfw2w1dj02~~1@RI%
zmy5_F$~@D$M(z5@ci#80hFV%p-4m|)8P0aDQP)u|j#x5$H9aAD)MnREPpQ`0h#IXx
z?g=S2YaJ;hU)!|qVyD(i>!o&<WZ8Ywvi;fsK!{}ROpOR)39#(l&jY^(j2&XcUxCrm
z1jd5oqZzI7IpA@?*abn^UfKR--x&@(4_I1zSSs-~NRt-$4&Yy)^-8;q_Ag!rhD}RK
zT8=4iq+2!DZxm(uo~mQUgX*-L4(hp1K6VR-EFra(Td3ChJKq+~oT<)K@=4E*TR?aI
zcGmG<irt>P)hMn`|5E(c6uzD6X`@x2?4kOk7kx6Tfmk6585hk|tjy<(7i5&IBbBTu
zExmC$%arlaDb4>BQks8O4QHk^M?LL^TIz{6i;qj8v0Ch|>aLgS&7Y1`{^A|S)myd5
zPe-n7ryb9$Hf3w=M9}%XrLdgyk<vlwsgR({ryz$VosXQ3!p3hF`J~}|dfWZiC7n-A
z&Hq$tYW}BEQ}aKinwtM9)zth?t)}KTFm5zf!kh-jjZYf8{<!f;<Ikh;<JGwF0MWV1
z-(gQjgQsJ`)A7L5$%3cjho_SRPbUOVCk#&~3Qs2vPp1jKbu~@<JM-c1ED@JGFOb)B
zC8d|+v~<4av~pTImpb2YE_2#DS2;z_)lL^@fb(rWuN-+bl(%8fds`)G=|bo8qqX@-
z%1});HIc5lYIM3dOVJapwU2784>TfnW5=a3wB+{m&eJ!opYzFeW78d>tVsuYS17rl
zDR+R?C~UMQ&+ff_P#XoJ-=~uAv*q_y)}_4|@EN7h5hW;6*7uWXq3&qeSG6DhuKeld
zwQf2k>Gr}W0(_P!oxg78Um)GgzhJtVpD`j-(wK1Zj|g)KF6I$oJ=Hm%UNMg#ei4_0
z$Dj686aRn4pAG~Udi)uw{NIiQqd%oFq_Ju9$W=hS_p=?jxIRCtk?V}Di<7nc?9!0(
z2Y*U!qrN@8OQqBgZGl_DATi`qua&xK4G=EOu<1m=zX1>UOjGNt`t^nJ3sSZ9S*Fx4
zqu&m~`jXEst<PF}^Dmh8=3hYVaa!^#B!2l)-difnt%84PD574lNVAE~bH17(zYV3(
zj?yS_E=M|rNa-3%>(;c5O^vPtoq?PtrK)43H89e;Fw$mWq|L@i>tLkK#Yh{$NSlX|
zHja@tA0zFTFvd2+ZxgNY+r$<83nHI4)&SV*ZmPRMpl3YKjAxxg#?9tvbDTMmU@}qD
z%$epKa~{D$qL!K~%+=;Pf(=A%GPjyL%-sb0h&pH<F^`+4%;T1@Y|Cc_tf<wLpaoH_
zt#(!itB{}zQQfSbg!>TmBN${2vC6D+f-w|wJaH<lDFo9Ia+XzTRS_&AYFWK_0c)kT
zhM*cL)L5IXZ3H`s+GFjv4p~R76Xrqdw5?n1Y`5(v2(e5%Za1@A60{+zpsq~2qcz4Z
zA}F@I+r8|*_5iz-U?@=|>{0eudxAaIDko}^J=LCJ&nB2_FR%{Ti|yt1DuT84dV8b2
z#oli3BG^mR0sF9h%sxqwun)UTN~ML%OW>e<0awIYLx3{4@?Fhctq9r@)!x;~s&I8C
z=<4d^>S48W^>&rGdYf|)uhD<i&9!TwYp`n=!APP;Q|jYf6A32EI&w{O%_NXgYFzVN
z3kjA=eY#e-R$C`r>!dzi8(f<RwsJ_<4%cqiK7xZR#a`e#;yO-nigRtQa0|Ch;5)m$
zxC8E}yQw>B?sK<rx31fI)EQA7<mpg#+mbpJs-M-uJ%n?ObD_%IV>mDBB&Z5L2g=&%
zuCxZZs|Xem@cB=(+-q>g(`IWtPIuZvfU}&ab#-u`AUMtKtZuw|?X2Ek9^JK+Pj@=I
z4XX2=LVVH_wbnW<Ql9aIvz_=9r#gSxakudFB^bc%^CMg2RGj!!>KP&1pt;mDieN0a
zL3NtbBzvuAhG+KKZO}89U_rxe(6iXp++Kw?$baz}PHXuu&w6g3o{g@yo-Lm3c(#kr
zXi7cvEcP6>SK(PFoYHiR+6c7*KBvjmnV_rJOD%c7*YQTI6W)B*gsAfirjB3mP0UL%
z<opErJ0@masB<dhycao(<3sh{$$YslJ7$vTm=~dK!BhMms^OP(<8C~~i3-}Qc#7X5
z)%kchTSL16e5A{37=`*3Rl{iy2J)unPRQR(@$0I7DV}1Uj6MrbF}p+D1sWVV>p=ZB
zig_#=&WO-4k42uUr(FULX55(`(DL_I{CX=-<S;R(MSlt5e*=tN@O8|Qkn@7%@4Ry6
ziGi~O<$MNh4dVpzCg<rHn5&~>mP-;RtB7a8!8{@}4tf>%QvaR7mwWSrqv13X@jY;4
zx^hktep%KqJ4OD!tV6fvWuWn^v7CP*e|Od~H^#uc8Vx6q$eAJ9KfuR~2wl!3l)q5R
z-<sdYQ_TF)p>6rgwVX{Pf4|n`yb;u(_6jg&{>b08<*6M8Qde`6Fo(zZ0GywKlkp3<
z4!xO}8DhxU9dfP?YRbec9UZe!)T|hJf{mOXg5S;cO$Z5{8<>%$$rBIcX$F{2BG0tZ
zQSTP&-N0EcI_CeFXyFECv&hp$Oz2ksUtpXqAWso7FmFf5nOE?(O#EuELwh<-ZjtA)
zm~yrcX7w1dr06wCv<K=z+lVjQ{PRr9Gb)pE9!m#2l{0fN=ZAU_apZg|Ir~eiK^Qs5
zpp0o9EkT{$PzAo68*?c?H8GD%$J{pRWh@OnT1$X~Sz&U<6!kJbiK34R$>(*vr064r
z<@~FAAq_L!)LbvjMv(K_OxX)y6XZN14R#|bd)YI{xtuE{XTB|FPV!}OlsK>e@+2Hx
zwmr;xrKd;GN(q~C#;ly-BM=^~MaK*%L$(k(*Fw%BdmkyvxlDhAw$Ymm%t4Z82bqXv
z!|v(m9p((xN?9B4Dw^|vIal_T2#FbbCai=yTM0AnOxPSbFN^FCYa6{l&W<x+-*6&_
zLB8%p{5mDAqoDhRnUiCXPhRL;BQn1bjTWgHQ4e0AT<Dw&mHJFdbBy|>?!u)1(eFf=
zd7DM|v2;cLEpx|p7FRh-J>h!o+rWIW2OA|fGj{6t+fM&t{Afn2B7Szedb#g_nKPj}
zAsSzH{tbcOb|e2{{Q9}O>|=9x*?H!!vGI9EEzkJXRO(|d=&#pj>ahp%!o4*@IpA+v
zGB>F(jrk&azVTDDEK^qUp$lZ6H0N?*pzlXehl?&~`nqsYJ4tEg5~nw{me$U#&aI-2
z(~sKB*P*M+&~ggWxi!f@9EV>umFN0zo?oupG4$8Miy*JEC5*kuTEe)Cs3na5|J2J<
zBbKb;Wfw&ar}CVt=j9hgJ*RS=>i6R>bZx@}scU;Kd>$^#uqhMN=rUI2V%!C8_dU>t
zmcvqHjvC|st=kai+7c_sI~z|I`@c&snta=0C3%GtaOD$s*+r9cU9-_v_oKaXp1*&A
z^8D{NbJNh=njbypfY30?{@>LGd-J`i1#t^$!8*}+E&GAbsa8InSviI{kk*y<g{D42
zQ>Hj54r(pg%4?>2EB-=P=W11FG^LZ?zR=Z2wW~wokk*RFU>etS`fI`$+WLs`uBF!I
zi<b3?MnjW(V_IupSgywC%#yuQYpeRD_C>F3R7=a$*%!8~v2E?JILtdG^LJ^@P0|mG
ziC^gL<Gp-(gN?##)x{by_X29{)0v}fh*e@Oz8Z|D@EgRui>L&$4$k~GvJK_nIo0FE
zPAb)fY`vfLTzW23s(kwAu5>280By%Nph}9dORW2x)!v!XG5vWfpIq^}1HWm`rN1YN
z-J<$)R)gEA*3Q)6zRyh!*0rK0TI#NJPyD==(^4&Vw`#Mx*#Eg{vGr>-vz**FKd&W~
z>l1g1J=lL{9&swf0kQsbSyo-`FTj510<rkt%4=(AjnT!F-}$ij^TfimU(7pp{X6D3
zvrVKleR1Y|KHA9I3=e+2*m%+O+=f~_mtk$%W53u-BR%wWX}@5D*mRNC&Y99MeX*BE
zdf?R=qde~`crlmg^J5L>f3B>-{Lh&+nEyGm2J=66)<D+KI;xd3HMAM4NiMGPG~}(B
zXn7mbJ?V>b{kxZIB6i<B)3dgS?VpR1>Dc9jS9%z9FHw7)eE(BOG1Ke%q8DFG<+9W`
zQj`8l_IYXTpXYvDsb*1YqDuUGerK5jTQFBFP~U`j&ho$aSBg2%>>A{EHc{g)qHn16
z^*%0L4(*~Xg^AhjsW&R^BKpc(zcw=83&&ry<*5Hg$nQ`WYmKa>S~yc9n=ax}A=OjP
zlt{bi%VVjQmh!f=i}201eht<29w%J%B|6)0WdG`7E)(zM)`sLxNB{9VeA3L<&pK<S
zvm;N+xgclG@m@g$n!0}!WQOUbb<=ukeYAesAZ>_Nrj=`BwDDSnHbtAR&C)8hDs7Rr
zOk1g~!Qa(djka0artQ@BX#2H8+EML<c3RhUx9-<NdR%X&x76F{1$sxlNH5mA>%H{8
z`T)IDAF7Yg_UNPZvHApkl0LN#G}CA3v-P?90)4T*TwkTH)z?$ljrtaSyS_``s~^x0
z>&Nty$X_atseBUX3B%MX46orB5zeELZ!|Yr8ExtB_Q)@R(aGqHe5<@0U5y?L6t}nT
zHcF89Nyb29urUmIN4|}boNr^aF^==jz%*c@F`3I^OfzN*wZD|yS;~;R<KQGTL+-$I
z3^Yz{(&X+?a;Fw~qL&Phop=nKf+cr*(&P?OJ%E!4gWXdMtOC}*3L0nZXxQP#z!_6=
zS0o+#-)K_4JShu1Eg9H}O75;?{FreP(&Ra8T01<&E<`${$sKyM_dp{>?H$m6LKvLr
zWyo`-aPFBdPxrzOH*#+n{aXlw{g!mBWH<N}Z_UIGF>;qIL+*bg_lZHS40*;Ec04jG
zz(Fa@T=20gl8OCk<nBI(++9iT9ff^~Ozete;M_<P=VIwN1I@&aP5R|{ioI~uUPRbg
zO77hychAz~d316|DC}~iW8W;}C*WhBB<)&oz6~0C2+6&a4CqtGjz@+(8x6ZC8Q4F`
zzz$M!&nFZ6f$7*0$H2}#a`!BqcOH^^W$-vHcj6c?&YWAN!?MT_&C($rCTuy~oEx0(
z&W+9;^};nxhvOO0rc>-(=X7;?rbEfoGx<!R64CJKUa63L>Jsk>)F}h_@6Pq06Yjd&
zbwQwH^6W930GE)vr}-#Flfv;nJK1SV+K?S>=tR$K!E4eP47EO8!b;qA&};B!V_@w%
zLp8P6>0%a*u2pnjME7OqxUW?AH6L@YR`;57+|ws3%Jc4$sO6;GH%p$2h~ApOZcGX6
z^CZx664;l{K>reG!@35H_Gwy5gHbAJH|*bQaton0(4FXr)6fZM*Q%PoKHXA!I{itP
zd<tF}KvNLGPN`+0956_Xp*C0{ra*TU&>o*&#(X}(tT9kc@m8MEMgrEO7Q5diU@dE5
z@oL+GgA?#-vEx7j`)Spp?<8PPYOzOJE%wQir{vWR0gb)fYOyO=;$`$B-s?y17bEwK
zc|?5l>2RstT|Q~7#s5;QC8)txgp1J!J}UINpK*_3-St+$G;4IA`kVL28>aZYAK7S%
z!6)+eBFv}q_7bIpyJw!wE8C|!S5uzhh7&b$g1(lNXRN_OCUAmc0(-M1S_5O3wOZKi
z1Z;R>q>wv%$vu}a+7L_>A9qsU*PYJL)3taTn<!@2*%e@-xKMj?aX!vv7d7%L&!=qH
zHxT>LM#t`UUa@aDuh`wsEB1}&75k0`VplXecJX<|zV5tYcRjDzJrO$}yAXsjVmGFZ
za_E3ac>+IRs^0rg-5sdUyaoBt4+e;ZpCC@-!UfVc>CAncqS@l`POQ_^-y;=0Q_*t>
z*iU8eaw$n-`!$NJ!vrx&OcgW8TFfPCHf9+v$Lf~#Y5OMkvXQ%-U{_alrY`m<P2y}@
zHC|(vP<2Kt_N0^}R|5W90{&zI9%(In?*w*CtVOKaLU7>oC%z60Pd*{}P0v`!T3FiJ
zzX~~K@%X{#oOMHfCy7tKKZQKu^gc+7V0_W(-u+XN#~vNGV)pHNd@2&-D66T?c<XuI
zGP%WuAh!kj#%&ItrJ&JB!P{f{0UCOSYz;4>cHPQnw2hmM+l&%pxN)B`7JSY68r_Z9
zi?QXgmqh)2@_xv&(Jymzf0{d8h`^nJdxRbs9vCA$!EmsP2nUOUeZ;lFzQMktPw1`C
zc5!QHN9cdWo#9^L-r{@VKH=NNnDAZUyTthL-Qj!0!{JB5&x?uCHPK&+C9#)dFN@b>
z8)NT?b+KKsT{z*sm0<s`Eq3EGM7@8>j&xNfD^<QE@VUWuC_B_vXyGfvR|-9n%%l8A
zcSm;%Ep~hCcETfK>;dQopF}B)sb)xcaHjNU`Y$;wIV`bLT}5;apldr_d)4(JU3^dR
zs_3F{wYzF}B^S{(B{>EBRdjKfk%^JXQOQx6vXceLg0yT-=Nz(Ad4lZzbX}jkKAq-v
zc_jzIV?UGsw#l|<m5FK~^Y6@jCwvKCooAG9+^ZAS>3mmaTn=3==t}*)P+d%`noinD
z8?x!DlMmvjo})!5oh0X}%Td?7jO(X#@qIE~e2*vNtW(ZE{w96%9r<NhoQF((pP-9%
z&UxZ^ji^i1SwnTn`ff-zrP*lNgd3E7FmbSs><x(xNs$zZ_H=cli~de5P}l2p@qId7
zd{4E(MYW5P_tI6GEKQ7~i)GKIi_639L>J!R<zxW_EPw+G@MTzl=CA+-)YGSnF5wyB
zD$zT-p8ETD(bI>cr{Bv~o8r^x8@wWTg|LGif>#k;82nG7i-K1Z-8tBq=xc)45Z#4R
za#2dfgs-FYbfl*vJqzhsNY9}3W)OayQne^m8W*F#h}H;q^li$4Njcak?ASY$4;}en
z+cuS~;?49vN|urEaAUa8atGuNAbfZ3Fv7!gnR9RMNW$OG9Zz^d?gYYY5jC=icM2;o
zBruHZVp*U}m}DJC5dC1_C&Cr@Y2b0fvjVdS&koEcJTEYh@UH@UM0Vg0fukae>}Vd9
zs!6a3;V%W75oWzQ!P|mmL_ZpwM);{<72zep6~Z5UIk<-CUk3LGU+{zAKgbfF44xLg
zkSpX9F4)1G&~2d-qWg!wBRrwf&`_cu2#qKF!_ZHOGd(n&=oz7zgr5viu0l&fONBSI
zEVP{PiqHzeuZ7+q%=*m@y%(ZXLLY`cq>#0tTEfXtQn<pGhA$N!*xXRKFkDESqHq!6
z&f(64yM(FE!o^{#vvAjNSHj)H-3i|mzKQV7;hTjX?j63B=zigWB7jlC4&OtggdQFq
z9!`=+gh$ZR`@*9L&!=(29bOz>BAoEj@M_@;zZzaAa>8$fe?j~W;dhAM6#ktEhj)Ze
z2zTVF$koCX=@OwlM2aJnhe(e|55nJye2ehSky{A&joe1~_Q>soza9BD;X5LC5Uz}@
zB?&x=<m7!VuagMpeJih&@B?`jgrCZ*6h_`Nc`pig-XHV+D6;b2&-;K{*qZ3;B0#O}
z7lhx6zD0OrbR*$S(M^Q6Mz@Nr=(gxKqPIu46W$TsL3n3$Ct)6|g3;ece=j1@{n7ox
z6Fm?;K>R;P|4jI=(Z7m7%!vg=Zmeglr*Or3#d;C$9qUcFPppsd#rnqj3Qw#gM)i&{
zFDG_a>@K43j@?a9?}^<*Plv~b6NksboY>mfI-=i<y-ApRg%jHp`z3|k65B!{e;xZZ
z(c5C%i2iNtw-jbaYzNWr#@;3V?${pTj=dK<Nc_LW-WTq8EFLGHLD!-@zG^+RwZg_1
zwNLafxrVOgbdg=g-^<mtldhCKqrV#pOMY8d@|6lWEa<^>@two=rHgDn+r@NP<|~<X
z!fv6fN3sXT1g3c$;53?wrs+KFgdZ)#k}bp-l!|vcaXM2r=aX!V8=jMZ=j5UuUm$|$
zH<yv0bTipXZu{-wAzgu%-jU)2U|S5bEknqj+!Yu~*5+>5nR`f<rtHkUfqN;;$iPUV
z?+cU@|Ng)zqQ4gyP4oklo{scPq-P;L4e9AfPeXdV%S-%UvxCT`8x~E6g)(4+ETrc`
z4>ysX2R+I{kMg2NdC{Z1=s70(fQ`0m#qNyVDZFT@R%~o+EP1rLzL(mTuAeY^QrilN
z|F8eJwh8|}`TI29klc{Q<ip63SNc2T0nw<ep619FEPX45WvmC24`#GUQI|gNbXCuh
z5|p&exYR$0)ru~W@~0Y|F7hco!*izl(dFfDcAvbwjY(HZIGjA3=0BNyvR=ApmA8Q!
z|Acy$niPeiFfBpmN9q~rsxXqKw;k#$^fpet;Z3rx{BGnB*H7Hu)K_l_-$H$=5A`N3
z+&6q1^{EmHZBXbn<m0>+eNE`mwb8XizfQeLkFJZZqo;2~-=LmV9jzw%O_FOuF8B7A
z&ZD;n;N5rw(*n~(7Wp{S$=*B`c#P;7ff+<UPF{~0m>HN!oF~Zl(F0Ego+O$*AU*J3
zfjLA!6?ls1%0MO2PY0eRdTwAY#d;?23~|^?G6T;Bo+Y{}P(?J`7aJZE+t05EH~b?n
z{39>?BQLCv2mX;4HpmA*$P3@cOJ2_mVTK+LJx+e(O!9rq&=a92L{?~4Xco~=hMpw;
zZ1RT8&`Y70h|j){KXfv5lIRaZr-=X0&}j-&8%l_*um}snT3Dl+(8C7NX4oRy4%5gN
zc7@$UUmk9+?5+d<$P53-3;)Oq|Hupf$P53-3;)Oq|HvC2NIp>x>}C)ikT*OoJdPww
zKj<G}%2oKo@Q2hgPK8esT^p_?IuYi)CBsR23l<R}%!n4zMOMU!P~IYTgz^?~MO;L?
zBW|KS5f9PcNEU_nMY4(GkNAm`6LE;njRc4eMuJ3#B6&n#8R<myRgpqrME*1KpF|f$
ziip0Nye%uzIntRp*O1R;M6QioOEi04M&!CkSE8?vTu*ejNH?Nyh}=MQ_egh&bz|g4
z;;?sSMQ)1RM0C%{%|!Q(^rkSkkf&xv`b7E=|JKN@ME8yKCI0_o?_1!kDC_>8XKrVO
zbDf!U&diF4xUPsR5h5buN{B=o?}{5C65@u0gzJVxxFI4E5)#ph+eU;)%OxV-m5>k#
zk&t+i5Q&$FXd~Q+HX=YILfk$3|Nee6=ddix#j@M`_dK8P@A=K|x!<p6<{r%5^u*xA
zV94)H3<3X{#8AlZOALdgI8hAx*~DidAD(ys{D=hR>4}kvk>DRpj0XQ|;#JsxE%6%Y
zPZK`{-JIAA`Rj?FfxeM=1N6<ro1i-qKZohA1lAgfUncf|?oIp#l*Y3Vk7qF+&tg2D
z#dr=F;W=Q0=YSEO14eib7~nZzgy(<}o&!dB4jAF_FUWJi7|#JCJO_;M95BLjzzEO&
zTJh|!70>=!@pu{Jxt=#(26<-J%6-+{fYwg)yVg8|)7)RWzr?ENx9)!MZ@F)Q|Gj$<
z<Le*XKfq2MW^=mxNB56Hb&tF6fIs1$;L{1gySm+kcM3#1mr?|2K7x4&W*jurpjicG
z6QgN9fgWfQ(>G{$M$(r6qQc=WP@<LRnm0p#9R0{h_T%&DOD33)p)Wx{f>yrWd=ssF
zzxftgIj<1W&Ien=tq0K3r&>>2Gtk!OS<hPw(At-yt*^pL=oeTAox=L(a;$iUqqRSV
zbxt|fG%wI92JLvWU1uM*|BP0Qwu|;ygx(ZADO%S<Xj{AEe~SMVwZ8||Ypf6Mr8<N)
zzz-9zBzB^VuSMB@2lM^!B{w9uB;P_``x?sj4V30il;Uob-d>d5Z=C%owS&%|QAPt$
zHUlvuAM6fwhq=WlozG(i{;>Oq`$hLlv=7H|+HL<5>(mO)rEJb){yG%!^oKd+=Tw%J
zV_nlMw-k|(IiPJt?pgU|oA-X0Zx_fnRm>8Oq#K_VVqPZa6k(Z$*$QiupcxUm88c0B
z8S*lYkvC~(i;#JRd6kHnSDQH^fxOKXj(LOmQQ?|5nm38I=FMhzag}+i*;8C?=9{;R
zYs`<E{lvBAC(ZuiI<wHcOI&XjnZv~m?kTrk<h!YCUED$agK2+QS{JP4j_e4UBl3jw
zzohbXCf}s#ewcd~$i3!0>WmL_%g?QFCT(|GeG#80<5QfC@O2aX-P~gDI^)CM^?l}H
zOFiw34}04Gh}wT{uRG(zUiWXvN$+GnD#r56-`fEliMl_^KPef57BJSty4D<TmWdGW
zOGc5J5@8~y^ZE8);G!o?RiZbaEzx(@JH&5@cZz>B-X-~LvLgA-WTkV|dE0r%`HS;c
z=UwMLr@=|N(p6mD4Y*luE4Q^9awBfkjk%_4xp6n?I_~9e8}~~0D!09x<6h&heN5gN
zrke1zzbPI6h?psS+f<XI<#A!qR>Y<M8q|hUsR^ku4TTMTQgw}o8^<*sZYWGmXzbK@
zW8>)5lEw~=Ya6>aPCB3a)V_0VHuPy&nrfFyq?Cqr@M%(GcH<=Y&Zn5*X^*`B1#Rx)
zv(~iD(QLD%VMl6cswg!Q@m<X)!t)wRQgdjBy|Fi+2~3A=x(jdv*TtmeSlQMU)|J*(
zG$XKbt!u68tURle)j88z2F358eY5z&_~Q8Yl5Z!EC*Mh)Nd6^xGFhK&NT!mF&RVpM
zb<Qi!dgoPVgYy$Ur=$})3ExpC5dvlw2;~Y$uC%TMy~?@@k{l}+{I%A#;IFf;1I@G0
zhamJ$pq;JGeA<=X!&7+=Pxtol5SxWCT^wHw`n~w~go2oz6cTZ2<Q=}B@Q&T(REvb9
zdIYm)la(TfdUO;k?YEt`MF91QPNDwd{6(}vz51)T40Y>Wp`d=f2RjW;gV3FnlM)8i
zH6c;kbgcVP<AjDf*9z<Y)^2Oj3Ux0eEY!b<pxS4N5Nco?lBAmyQPf07#Hcnxa;1Bv
zu&GXp2x?`H2y?sd!ZWXdew(2iQz7mtsh=E;7W1%K8o!(REj~$8gnn)-N6Vfq+H=dM
z`&o9n-CRP8O^4sl5C7{I4PWIxMR1=I<&)!f?=wtqha@|*LozFKKjkuigcxl;<cItq
z%~(-xXSMsY{K#QHzH#P`3&w*7Y;qTHjyb2DdZ*D<UClKzH>x^OAH%N7$#)8ePJU36
zUqLPYNoG$*agL&FRsViZdq0Psp&be25V`sSpBPD@`7v{NHq*ubCTO}JoK62ea-;*^
zdC++rzCYnSE1YaQJ1K79aLS!$*q1XgXzHUkGnc&k?fG|cH|NIU*^5-YbyOTr&@LP#
zxCD1da1D$5LU8xs?(PyCLV)1zvbejuI}3{kC%8j!7QOu5_dDOY_n)4bb87m`bk9^*
zRaZUF@V4_o_&rvnCF`+d{K%nXn+d&~IK1g9&3md@gZKKu#^>=Xg>GmBINU<g@tp|r
z@CF|onfdRx;SM8z;;)S89AbWIL-U5FNhO`nPyNsxh$YD&wB)ldLOTN)_6-@!ugz?I
zyoQw|z7nsEmWG2Ug?;X#^~B6Zp9}dRo{rU>c%{tFxh#&h(S0Sj30?~&OP3ZXAAYL#
zPL<h&K#9Fc^G`_l?9uAHmYkoMoq}EPr@H96s%`dr$ri+Hmq<J5KS)GAe0TNACbp)w
z#up=X6sRoCUz-&V>oiSjkf@r0%?9u$HNysY+I8sv_Shflv8oLsyAU)pO)~!;m(+p!
z7xtGdW*F~;>)x=cOm$6k#Q}HTr|zvQ$6?+D%4^jQnm5xtZ9I7`=ldRFHNFi#9FG_0
z4xU&}j?Ru)#x023Qams<4<tMHiAzeKVo`_cxklJW>(IEO%}*`sK*pz5eAUJ=wzV>P
zR0ewMy6d{oW|L2TX^idVMV#bD$@8cjm9d#rgH<uxH@Nrw&?!st5Ff@>Y^D&;P3MkJ
zHjWgBCkvvBMf}qNKsX697nSa^N*d_$T_lHKi04;;u)17EE7>a8Pdn1NE$N2=cmulq
zRUKS9U#5^_$vHET8T4EZzYm4#JUC{IynKxt`Tq9JYfTk+15_fEgHZLPbsVFyzGUul
z?q^%*j3sUUxv#!&jv`2lF&di&3sy&3s%_950{I?>TgGUuXdvR!S0u#&|6XpoYg7i@
zy5h!z+Z8zRs8`YkSbA7jp6T%_7{DpBPgHG(A00$kr(=AAst-S+sqC8Zoec?1xgTN;
zyTk&beSS&ITMo*a79EyQgbRsU&by(eeRXE)ar@KOqk4yQv$aJ`(Ik>x141VP{{Jtm
z#JQyesuN4S%v^~iWC`_RxNJ-7x*k#yul*U7rjV1(;azyP{JDpczDin3_~Q6A1ghl|
z<a_!|krc~P)Uq#V>}IR&ui_~**XhE(#I(e-B&>x?N=k}PibYCBibIMSg`o&v{O|ha
zFY_T@ub$C2CmAQcTJ}~1Eo?nZyX}Lj+7{|oxFz&?c-vt2cR*4c5p*a1AJo*pF^T%x
zl>uh#7r$1#`QzX^nx+N%J55VnOGzGb@;2-?IObWkNEp%3(a@3c!X#lsM34a~Q1(%}
zkYaXWD)lLE8UUsTqG-)eukTjYrNqzW(>mOnpH|Qs?DMkognn!w+QDIb2ul-2fQ~5(
zT^iG54S5sR8hg^+oKELBd9>>D68IXlqGozx9)x*>KK(-NhwBgS7YhRRIvL?!7sbV*
zDt!jdvk9h~&jqH}>VEL!23v+5{5l9W#5EY+kL+hMYUb~Zsl!@=wYvu)cVzq{8Soi+
z$`r)Gc;p|$42y*;=`Z_N_8XxQHh>rVBX&GDxCN2_ms<Q?yyEj3-XY9Q#LeEpYaB%^
zt^|Tq#9x0x04yOouEg+%9V(o35bVuwv|wO1$PxyxcWo5b-vB!uLpViBgMIPCNsz)T
zhp{b=zk->RnP;M<Xmm|tC$}mAA8ghK8>$kjCKW6`EIgIqoPxemqOwSS5#7&WrxF69
z8$^frXGCXYXNb74LIrR^U;c)PM?$^K8sQ(ca?#S@<)fzpJ4s8UrXn>YQehW*8I26w
zSZZOGz>nOc9<V;_``>5$dSU*45~hgE`DH+%W}+=ZSZj)s(-7n#^7W`raJ1vYI>){&
zGsPhs?!W86rO*GwOb1wr3IM<uINCwlU=TtMfR7ueez}*_2w01xg|CaHi(VNFWna>r
zOp9{wLjgZ&4mQJe1a|elF7?R`PcLoZI}3U+rohHzW-Lei;6MR>b7_cXbyVtP6^<3Q
zKx{}{#yi|P=>m6K1muqX@ktNP!yLXg@^^3uNaO1#MUT3?z3de?LJ_f;+j78H?t9d8
zg?X=BaWQIdo7FR|=HY?S)!sBd4>f?BhqVRsU;p;%7qri*{Z&IE@(FN>#xYU1Vu0;Z
z8KYq-$@A|$F9v+y{8(pzg!ZeFB*Y&5i`I}u^mn^xv+hCS32!367%?(b-FBEJZ>_v>
zALe_nYVKNjvj)^z8`bWE#us4bi&G1XK+q(TX>1dO{{ty(42(}@qDEKMlD5c_M(^sN
z7^Hc1xlJUehDRb5-)ud|cmGL?><rfE!}JKb8K${kYYnE!b;DWI_JJzJj&uv%hr~1M
zzm^%n|A_$Ra_rwlVrn23?;_xX{}myCnK-rntGQHh=H4r56w(y}#k=$HN$nz7x;RmA
zuKl=d{FnE-<WyZRvL!-lrz%ZpaFtW+32pPs2E)dGA1EyU;8T6nGzC2@0^GoZ7yJZL
z!H#K$v2Q4d5QGiFhy$XQ{)R-eeqh{|+n&g)iK+>&LDU%L8EO&T#M&gQfswBHc)TqY
zh;uo2Nrn8)w_h4wn+FHO%zj4-5JLb5r_E~Yj~)9&xQWA;w=F)R?A%IbN_WIrEG9g*
z!#jK;Zn<=Xa3g<%@JNG_hiT?7ou76aAC7%!8dN`6IH+zUnJ=h<?3dF9R57o{#G_52
zE$^$5tu(ijwo|kV?&heYt7CNzycL^{rBS3k_6t;E6wxqIVn<sFzcS-~4p}$rFmqtX
zJcM<-_Ywt8Bhvqa!gNDF8_@&ST6h?>Ge}dj;<C`>;Vd2njky7cX&2X#f#$s^MqIU1
zEiG(qG;Km{Ol>@E!d}xO#zq1=KdzD>iGq7pB207{YZuhg=Z(%Q15<swm&$o_Fs>CQ
z;D&Oxi}GR8%8UcskUX1`#F7T0$yH?sMa@y4>4rJf^K!48=E<YTHg)G#)O}5#KtE2%
zHlIfI+~(YJ)V?*nW(m?&-_0o+>cIfo-f5JRq=0GG<<$GP4Im@zOWRX_cotuj;@JOb
z*b9;S>yXm0mM(GRt|8hytbJhz+srSJwXPVghMJ=s)=B}R__=d#OHY%R3vB?sz4)Zn
zKDfz27wpJJ;NdC?7ewSB)zYxa(l~d9ud$Z%*Cz~hZ6hznq37S{7J$wkMij$ZiJBpB
z@FKD-R)PZZ!t*F^L!tgw=CAhR9!4G8F_dTHNxiMS4Yu(j+jRT*)>pYcWQhAnx%po2
zduFlsVP^PTbR2f)BzIuYJ}&8_PEbo)%?t?9UfwVLNAMI!3X!{6#v_ZIf$^hPaY1_b
zphHKkFyH9_iCq9==Id`?Bzk7P!2~w>x^2xn+ZNO^VDcmBwH8ZxNc83xgE#iM8V(i<
z0oqJSE!FV^z_lj_Bq3Cdc}Dw+W?D+sPb;6jNG+H+dV^d)@p$4=PrUK+gcS5ijyKdB
zZk26`bGR5qu72s}9*mf-Dzm_uWd@DaV*h>Ql(GhS#sSxSF0VF5KFDbX?QNRy#~f)c
z&+j?a7>&uN=uJHnr1d0}Szfc>9oX-;b*d`W?Z$#37MeozXU76rbf9ft|47#>hAEsW
zuP&ZBC0Fts>N#~dxllk?^xp01fbu?Oz3_<k)rSLD&y?q^GpbZv1s~#@#Zb!aHcqZ_
z9tn<ifPM6%6PSl=2-jVHY=OQRudG14OfN~Vi(>9bzNOxpY7SCs_T~DX?S)y+!QwSh
zo(|i7338RHr8<>&WB#UF=lf~Sk$rvO%C4C&hep_}I|?e0PBC_)dwT7|{Kg>X-&^J%
zul6FLIKx>y!q?Tp;U0I4(|weh_WCiQdWCzseAs;O<l+;Ta=>nlYFPTl(3MVoVtb-O
z&)AKvJP4jltc|XMc*9)4GqD2Up;G)tw{I>zR^0(mO&5MCC?}t<?lF$;Ei|TPXePi4
z&<EcL$P3g~5G-R{tAoD1SFS0E=_cB$ZvORsz@3Yhmy_9WN>Uh6bDaB|{CR;h(e`Iq
zPyY>pydjO+PJ<mtZZTKKP2lCv$Apu%c?*DF>XFG^07<6KX+S`Vn!-eWN_E;i==0#`
zYr1sMz@4K>j-2?5<8)nFwfawDop<1^YInRxkrZVe|CEg08`+ctwzB~@#5oT;S7epj
zfaS0eEq|PeHvi)<#eV>M#6@!4FN`C`NF#j~D4ON@exz>lJJS1Qnxu)|AwS01{=H2$
z{#J->cpee8sSYKV?5c96ynKW&E@1$!@XOYKzLqEAA$W6pB~jN0|9K>)2MG`&7u%*W
z%2%YTPBKq-izUgTn2zl2irLW0m1|?05}QD!zJUtY;%s@7=-SAEWx^BCH^OVObl~I-
zLkbn0c~Q#9C6Pj>KinLPylZ-Q{|#O3wVyrk-gI7-xt!%n24iAY;1fs(d?mY&ng;5B
zj!m0IdMLaj4b%PBxy2rUdTmf;FnFVbaiW6}sk2Ekk6BP?@Yz7OH(^Zv4IX-qfT0->
zD~87Y^0lNc=?LdE;Me+;Wx!#_wPUHUCGu05+M8=*&@qJc%u}4CjP<cn(fy%ectm7V
zekkqhF0hbi<jns(%v79&IGtjUv;Rx;URtLlr;||0gz?x#T0mA=A9uyFBAZ-yKWATp
zy<NuS-U+}ji{TGVvsaRx3GR<Xs~zQWp5vyZ3zF<liPX_KxvqRuP|^b*zEEw_gGBHf
zf!afv+dRN@W>L*AB_*_8x#u9cM&qM*4}NYAw|m0V>XD!%;^;iZWEkKDccvGQT4{Z%
zU`v4c4Q(#SZk$i7N@hc;fcm*J(@JO$EE+vLLT9x>NpP&rkJ^?)kf_j>y`xqcknk`s
z2YyRe;AuD#W44AA8=CmT`9_wlE<=Q|YYZVbnR@5*JR2*7`?w3Peh=&u0i$)tBhO#C
zg(N#K3FZ99t%)Ye1SUJjpHr8@U`|u6%kwz?G$LxfGRh6J8&3El-ks?(dqvu0G-G->
za4P0y6u$(nWIy_`+v`cWyhv0--WlymB^{^rv)aRc97Dc%CFv3k<7(%+uzoXTlWzm%
zrN>qluBip&x_^=7UeFnbxolRn_mHPr5BFNlCHdlLyDL^?%tkhR*_pl57XMPYufv}_
za5kAxlI~#XO`+ltE@iz2LpF3XA%72e!ApGwmZz5?YWMGG%32EJrTG4oimqYX3_ap5
zj$EE%+ec)(Jq?IF(yOjOc@m6!o^K^DCg1m35m>W1%pQ+ydZR5b=oDx8Qv_R;brx&+
z1kD<Vt<PpkYc?OVnYQGtUSM#%dqtb;k`I_{m{YM^Nu*g%zp6~$_Xq6ZGN?O-aa9^`
zmX7eQh+HoW9eWoy@P*#c4y)Evp(gdz@8TB=EuG2Pxqf-_NV1(6SnF9=>Xa;U>QNno
ziX@!OgPc45$%A$uo@0(+ifQDxf}iWX6Ld;tuR+VvZv%N0pI1g*6|-0CUp1$ch@FSM
zg+APl#dVH*0H<ECA#l-vR4R)=m)uw4meh*nSC_9+jks@iu0Q!NFZfr%5yFHNEaJ~t
zk05_vudBw^$+pcl!}KHkc1(IhPvL_U2Gn)rbJKCTbA$Vu@d@7*?Nd`~<?RzovCt8N
zBu7SD8UN;&dfMkgT90Dx2A+Z;04oiUpuw}7H^PZed3o2%0H>>*XtbtCqzU9n^VaW6
z>J{Xxcl*CC*Mp#OrBLj%$vJnS*IsHBPt(SVx75jcm2IF-ZuM>aB3)qnVo7lRZG0{k
z8iGPE68|?WwB~BmX7qh{0R#cK^`An)UBNFuLwbAv#u>2z*tM`pQIlX21LOP3deL%8
zOVOr+D^avE*jSM@;3@)}o;$y^5<NEmo%%~|MB&tXfE*TR+A9O9!8}J}5W)Y1U<WaH
z-&)5QMc;$b7hTUg*lEL5{zUwVc-OQP^TO+gm3k>IAvrOk{0G{w;w>*)fB@&ay>t>O
zIw8swxRB?b7oEqFcb2E0*Hv{Q`V_n_iYOK)HWH-Por7Y#r6IzZg)|AX|MZyelsS!J
z<lgFc_@mXYHMnHJzr;y1SISDWm0+4@O;``!4*)<T#3G-(VvCDKj>S}h7Y_N9Lw+7&
z3A=hfX%WKIk7Mjfxi-TQY_`j@ni+ZU@wpS;U!K}?Yp+)}r3z+o;Dz>3H;Am);X&ex
zc+}RY2j7>>3I6=gd$IGKUjq(O4Zer%R!oi(ToW}_&zOPuUoRLTDYOR_x${q9I)i!K
z*imVLIMyU%K^s_yXl{`=W?qh?K2nboD1Dglq2du=E=K;H`dCm=(M+$x3PHV?l}FjH
zGEb9(K!XsqEvYXZnJ`Ik$?;wy-_5KG`Rh?i;TK^^(l*hc&7+F@_u_YT{vUYZJHAiH
z_C0IunppuKydMy+OR*<^F3bF*^Ydf5UR}amiVme(P{};A7;tbeBt1`styrQMH7?11
zw<d?+917av4rW{%<v3CKp?eeg>jlsmVEpkv*@ty9`VR=7D9CWnaL9<srk+c!7*2Kq
zk++ha=7ji(_7e-{@;Uk-F;m9Z&>0CpCW3!P4FNzn>E(0B#J|p;XVo!Ze*zKffivm<
zTxr8L$sU~yK?DAnCM_quj=KjeNT#$;dlQt&TLvPV(q64dk48p>0LuD^JyS}#pv0~4
zza^hBo242)3y=LbJ`I2UDNhxD33%TrPk9^G6G#Yz?_XYHKd{BGNw{*<bM<;JZNmF8
z)xHM|dZZ2D0{-uL`n!A&R_yg-IbG~069OUFXiNGJkoQ+e{P+<=_^%*kt;l>-7{^ID
zhi_T{Hap0HUN_-Bw3BDN@YA!15z^J>AV*)rMS8TjHh#aum$jK|t=u^CU7lrKM1Lw_
zr4Wjc)2Y-D45@p`dpN|Pftj5dwVAHCBHtI@be<+0e$r)m2-~Do#o<ORek5$T7Kz}y
zJO3g3cdUE#tx;EMji>p$=k=dQ5BzIbNzYA4h;NHSf~5%mG$aXU`tzkfeCc6He6i%=
z@dvx3g(d&Q%8%cZltLOX;AocK>x8ANC0Qf%TI%<ZTlj5NcX!Stq`4s&<oQ%;+=X8n
zNfw@sq_(Ccb)NwXod$ZZacU_+AD!8SR~5}TCiuPnKA-%0KH1#^5y8v%egQ5n*iCq|
z8eWX=Tdp3-K_;I`(9lfZT);6RmWGZI4lJYIuwCgFmiVx6eq9Wqjh~qiB-ss3Vz?#(
zWq`#Q9AKAR>@-C6bh#iK*W@<*rB5s74hYR5PniOF7s#<Zp0H276#wcVBi!uo1vrL3
zg6L3L5j8TND8F5Qa$=rc6h!U<&SH8C%Nc9O-Ed+yu>VW+UH(t&aL!z0tWwHNW>3#}
ziU}hJFipY%@1RSP`!jm3hMbVZBB+(;e_gDM{MQ9P`XlFi7oM|og5brV&BF=bjq&<^
zpxx(HDS^*_#v9r{7*lY^ofVLY?5~S0YxvVcj^S{%;3~f@D%<h`#u=N2wQ-oiVU=Tx
zoVLYWs~M(~E%@3Km3WIbw%PC4F#Y_-9ZeG}w(nIdI$>2iiwsQWwjN9ZHgu=ll`SK#
zKL5y06+JXN!q!o}4LbrP6+Mt7?u>lWg!;+tW9vp%an2a-+<a2>jUi10OLC`scd|a{
zCnuMk<j=G|6<q@x_J5X|JhJ_$sptfL;q+l=tV(G9@_`9Hn>!rP{PpL9ZXYNn@;9<u
z6v^R}hIo0P(52BDT5PQP2w7Bm5#g$ALBY2D&b+6_h${dC>OYjt;U6R%?K}t1KkQ1`
zD0TzkbFO6TW??T0?>u;*24NIKFji5@V$=e@JprR*acW+|?*l!sYJ_`>GsC(4gB0FG
z<~bDh{$Ygdl0|fhFQ9kIVULu*cB`}1Y*`-+t$G5>AqVRf&Yg+3cq;+(P~1LY%?I37
zP~VMy@kU#}uH8xy)EVq)skXxL$anGjoN>3e6%Yqa1Y0T+^xji$Y)U+Gjwl<C(JkHB
zf?JHoEeSg#8$&(g7yo^oC0=iUSa0c5UnCvo&0nOagx@gC;4$}5az*a?!p<iv1(I*$
z5O2_E`hV-#9XE2U$+{bnDC!Ybq|2ZpKJ2_sbn~ZeF095n@^f`0$h?mk+75lge?2O0
zB*s7rDA8gr=8%?tP1p#+%MY6J=_H#KTp7E9=zWA%lIFRniyF{Bs%)s_cU4&ucTeQ4
zNzdov%=x1yGha+{2T;w@jYPU*{AqBUE<2dCb7fn`<+&z0n?y&Ic=T;)yrd$nI7w@^
ze6)@SUgDucB5szetbSzdj2#U68u+*l_{Q^%a6Ove&5OTqOnOwxLdDyXAW?E8a9~R|
zbat{n2BER%&&31jz`h&q;um%S&!UYSG7x_1m9=x3CnMN$xF|XYlFHGQzyLzL)^@Q@
zRNGPo;(gsy+nVJ#==<x%69);GQ^O2zxQCasR;oQBC$$68Jd<sJm!U1;j~!<l&>Mzg
z#AU^~hHHAc&IVV<lB>0bYjfr;HP^S!wG$cMx9E*+@asNSvAaApYjuKYBeGJ)`S+t#
z+Uu_)R69%5k&)G-Cp@`k_MRB%*=dUYCAk%Plc99Ai8q{FJKJWs*OdLmU2x0w(%&<k
z*SI6ul(ivuYsA%EjRCKwr60jAyhaTQD|AhVoDxaIy6=|#nQIl2Z<5$9X>lT+G`@@O
z1IN=fznoP~bD*CVSjZj*G>-cN>L_mkHB0f$w*Kj<*rmFot|s3(_gT96cY|WE5x-uR
zI|lri;?=jeU}?~29b6o1XZe`N64{#Y21ppQP1|dkYGMPWv_~<7HXcrWk%y$mQntyK
z?E><Z8^8AGBHg=0>TyW1(}>Qu4yPF3qtuJ;vC{AO$qV#|e#<J~)h>H)%1F}Pm*jZ>
z?Uo~#5s_j4d9;Im@4PHD!F^#0Rg>2~Z@Ybve01ouHhfL`=O|hVDT;fiy_nbiNyooX
zfbP4kcuzP_$xrg3NUhFLMe9lv-R(|IqTAfz!}M}Oz@1XD>@S5E9EX&D+D*O*>yLB=
zU{LOy6;!av?-ql<Yuc{8pkU*hkl>HOW@EwZ0-iLt7z}@;>r%~Q8)CmkJ7UjXL)32J
z?7VU{u0qYK0uFWe^7ag<U79Ta#XL30vwFvM@}M>8<WOFvii&RyVU*|g&uN6k$BJaC
z!8!V3eCuWL<UYHI&e;T9%NLZ0hLl3yV5uzkknQ68qShd(wHx+`On<l`g$p_7Img`A
zAPB9jbMVV$5=uno9sdye-6r+;l}<#agWCT{{(pyNQPTkF>Z)AAV~+vV989O!W02Ut
zwvXA8S$;XjYeNabwbos^Y7xz%SZ(>34}nDN1GL57#kL!VMqjCM{UKf=NUxwq#K#e@
zIm<^_DUz9uH_UdP)B=tv<9F)#C=0iGy&{}Tmz;I41InHG%YZ*^NL{)=(mq{6hJ~3#
zpR0e>HY`r!6${MxDGF{?I~(F}?(wLx7UINfl=v3@va0g(<``Y9`Z~^&+(a!r;eTR<
z19To%JmH=^ZE|D-%Y{RRPP18K^0~&V-Aia8`jEpapDgq{R4VP0Zi9`Y>kGs9Sj(b3
zFW}uf0qRJ~Y-Tm+;FrpL{d4{~g5|?deGe&h<en9uqGH0_o*kc(#)P{|M`gSeZeF9R
zT~XD01#kY1`XeJ;(wA|hB6S9}VtS5bS@WQJdF`S~&1QOmWa7PC7kR!a8yhY6`8%7O
z6@{}R{8G3D<70aFN`95>;*<*41qqv`cFFZp2Q|-%rv<TNWUeA}>*7Vpi3NUJp+=z2
zdoDIfb+Xk?)7T1Hm1t(oJEw!qN#o=ShJB5Ph(Lb!ES^v)-Hpe4#X&_*&HY^DP2Qul
zUli~gs2nnTaQOYv#jmOR+h+O2?ER7ZqjT2=AgVOpewQ#i>Ri&XpoeXgp8G$fH<@8K
z(`Gh^mPsXGkvKEzY?!=Yk=HH@?YBrpAej}(;ip6FL!v_x!cT<Qgjn?GNgs>hEf5&t
zP+=!vD_~FHbYTVH5PxC+M!*i@4!ZjrCGzQ<)M+`$BWO*;U>Nr$Uxi>4*$vGNp#^i_
zD@f021WUFgaJblhOwVc;<BKQeF5)9R3M|~OW9Ub1kO&aWfXngsvqMgRO)iHSnf4<7
z{;ugCkysJd!LEQ@B<w}FV7P&}n3*6pB>SIi%W3$8Fb-%gMqWlpt?`oKY}^2(HRWA!
zmPmk;#ITVm;eKJn%uFPv>inNWQ(U9FGI(#bhad;D2)z&=Z?e#MrM!Vg5*L#5KKGy#
zkE9JZaPRG}6aOGlCuu4udW^|Y8x6-46DuaY20h;R1f`R-Wi9|P4Y3@@V+HxZx999!
z=k_W)`LFavqb21EM)pOEreh#Q!ST=nfB-hY$F;&<^;WvMu^?;uv*o`Q9~t9HMx#ae
zWP6wa$ZMy)r1SB1PIy6WxExN&L0&=SA{edEAc<j_0`j$=y$QW8-1@}yQZMCjElAa=
zbw>%kH@&bsyzh8_rJT+6t9(J}!w62UDjE{QU+>y@r(+cu)_l3EL^|7vD_*qRIa7R!
zOaG{KY30QzjSku{gmpy8h7V-__5jSIroNw%5u|-e18;prYBW)6<@6xb_XF{ekiFbc
ze*gQI2|5LYNM)u?0$HV)(x;B9?yhaLjXt_$TzPpJ6&a%JE;4-_9B196`PagF&|tYD
zV7ek?x-!O7weL#{>TqIU4)a13234pCpmFQt*1q@}#H9FTDO9i*0Y0$!Q>3aGHooc`
zystBSAcmSn7hvKlUKZqE`bq@BSML}`R*89y-tPrU^lTPTXY#3{+ClmdTgH&0Ve!`D
z6itgL38FmQDC=SQ8r&!p(`ro=Nt)*~`<viMhT;5Pw_uw)byFE5gw%dcQv)OR)Ss3s
zF$$?vYw!zN1t?nxTN9L~M2~`QyT31BsUo;IZ93{W<HFplu?daAn2mqR4j8!~5lQ`6
zTk|9@M6@=)v3x8ZxS9ML`gzTy(j2c~Tq`2Sz370$d%5WJ+U2J8x{rmceCA0bP&YJ-
zxCj!c+o*rDHjne@N5tDB1^XvfhxL}v>OQzNR;@MQCm(N`vLO<NJr6(-5V0-)qVd6X
zuvcrIvF1$8FNBZRrppNvgKNt1sdQqPZHJn-(XK}`Z&4`t>A<=)-XQkZicMiDV(2pU
zv36f_|Jj!v!VWUWQyz?Z$V=3^Bzjn;qaBBb_e*FU)`@P!_wc%5Er<gat7!rOlWBI{
zOk{H1tk%v@#3P>599%;b48nf(Z<V?k0$b%PuZ)>F`U9=J5%&5{UJ^32@_Q%iMlP3U
z-qm6H%>#{Lz|AGjtWXM?oUVn~&sPOf6#2O3($okr_FG}Lj(gz@x?9EH_0Pc`SE_EB
zdYyrty|R(=T)_&4b4SIt5sp0v31n4jrYs#l$;^LHtvA^^lJ4P=k9j8enInwBk)VsS
zM=mm{3M<%>?ZTeH^bq}kzw2W4kNtTb&_*n%A*f@!9-^Q>V#91({+JM#sxJj3forPi
zg(z{E*ca+c33RMD5*Og|Y$u<P1c=)*Ke7fpi*|nWuDa8gUQ8srg&@3>o8=BG*1nZW
zcCgP0wxEA0ZfmsJy{X>jF)&k+T_|f5D2mw?D$jm?`-v?}u=@^Q)3m7LIURe=auVl_
zd66n8#U$MRy}D=kirhvZg&;o5K}zhEu;h?`I@)cMgn=>uIC58W|KgRwpaC5}>&DFW
zMl?`}`74yhGw*mMq_l!unk!JDgSU>BR4_lGP5z6z+=Q#9#i1}eR>EylsV(`HwIJFQ
zN+4bBnXiwyW5M{bRaJ{UkUFWt1uFyt%9T{%raSv1@ACUT9pH`dsWaGbxSS_WLI5!+
zllTA-Kyxi!aOu+??~s%T`pcA7g1wph66$+Bpvvp;y98Kt$#1aSBV|6)hNa<;`U+{3
z%RA2{ruSeJ-ol2WS5>KP7G%TiyOwI$@-=ppo#m0NtQfO@R7&vgq;S%Y(70P);As;l
z|LGg<LHG>f)u=h%gn5(SY2npS<3s#}xFgZNV-r>6hgFqxK0<6*pj)XUwD9R=)$L>f
zX|781%+<|@50E2w%u;@E{Ns@#T8r`s!=C1HTt&yy=dDI%BQNdut64cvyr{B?w(YJ`
zN1`bkiieA{PD9SMB{{7$H<iL2t|;7ivNT2A-6fcIepaEjd_bgrGCz^dn)|GdZ<8oO
z!V4V2&1X-8Sgy=e*9v~~LXzRW5ET-4Pw;q6A{uV$OojNXDl+!uX6q|&6I}H~I~WT~
zHGq2duCv0HULl9wbvokRWp6`o+VtB2cvZ!#ug5m~j(OLlx0BwFh$F$ox7<yqcZ%ae
z&IzvjwBzsWzOSrBoDs`l$70S18L-k0=WEI=eM+4fS&<^cmK)in>NjT%){=+dn7_{@
z`o~_R<5KkdCIXkke-23pv<C09D2iO-2TJ8n=w`{4UXX44%Jh>CqF2jq7X+^0Cu+VR
zH?h}+=n(C0(!C?*?!}7>PI+4OD4i)r<>J$|xsOKs(s==z*jpdDp770}@F~K>SDH&L
zR7w0c&f^qiLqR<WUdMH)WkX{)yL1mI`_`H=%8`k&38ZX=etRvYRYm3Wo5TkyLII9=
zAxuCS`>IP>8{25ZFJ3kTpfMyHg)(8BP2P+ZogFKnj8j=vxKaYc4{73n!8RQk`?Id#
zB)I&9V?LL_DGEIs=PSjS@47b5+ni0U-eGrRaW;=U>0>S90h1-4sNOATWE*D__@;Lf
z)_X9|RY12xNrEb{kNe}B=VwWvr9#nl^@IyOD7sb{J4iEt;9vKQES*cn;G;4<M#@)F
zUQK~U0otJ@E$dUP6*b$dyT7byrVnz&hBup3f-`!i-FDSn0jFJZOR6lBvrw{<8w0hs
z?2c!}E%uX%_tsG-`Mtf+mV;*Z*Jx)}g0xpFc`Ai<!YYNeFSO_?dzK=qRx-$HFKRF9
z!j?dFBTKO>hIKtQn#;nqhTHdOj?z6+>jA6(W*+t~nRd>$&vsh=@c_xAVz0Wdu~@@}
zNhxpws9%d7em$7p+!=abd%p*V1;!3YzdeQ2p9}I*4v(+bOD>M{dx_`7mEakOGJfm5
z*?O@0YKyx2fy}QP>S{?**bY5JzPX!$NPPj+h68sg=^aAdo@XzKk4C7fN>pH@Zg1;p
z({@eEV~K#HJ^vewfq4(c7%Cc9!7g&o@Nf?7TL5%N|G2HSK$nh8V==ERK_KA}e;tg6
z_6vgXxT&dUp3qC(eg_9;{MXd5p-F}n-F>1Dk4XGAe0>c;C<#o@`qtXL+_pbxbp{-4
zwSaMNnu2lq=!NNt%tqbQ1$GB=@|YYfmR@ZmiEp!4&&H31Qp;0`c8^>bwy1K<F_!2P
z!m@AnDHIAb&?iY&hv;Wv#1zAcSG|d9lqG+dY_;Ab6RSGkdPi9xn*2h^6Kp(dXwDn~
zz39D1?a}%G<!+@rcjWJeNj}Pzf7Q2V^ASk~2j2`Y+1S2=KkcQ(LvX&El$GLF00=gj
zJ$?)2Ys`mJZU5qp{yGx(&01EfIhn7%;FP&zET_KZln!-IgijoQBEDWcCfVF2A&b#+
z)J2=&V2rU%U1Q?AOV!$Eo(X%Gk~OOPF}SNZL0YA8ZwZz9q*_r&aeZ3Nz^^9lqSaH<
z7IKwwd-82)ZZTOGa-4h=9%G@5sT0XA$kZIh^|0LPd<69<(nc7%yMF+Dux_=a2s+et
zD~UqXi;?v;gBhwG2|`-4sEu8xgV>en=0Cj+TKiX2Vp4IwjR1tTVvGYMgJUfG<#7bw
z^Lj?FF6}G@!+@b;6a#s&DH8GwH&~>JSft*pG2sNOSat#M%LLcUuSWH;+7gBs*{AoG
zPcMAUeti3WLkz_u>Eu&|bv;WEH`WkJ4`(g?^v!-Zs=Yw1Fujv6D1-FUoXgrb*aK!Q
z4Z3t)Y*@ZTZvj0~QWa(0g=sWoRv{ADFPxd(M^$;H9|`&8xIZoEaCF63;XfJuIAb2N
z-(vw*nY@{&tprV7{7L2q)q0&76wFDp95(^>N1R);mv|g3gP8XNAjZzEHdw2h{daHR
z1Twqvg4$uj=06Wr5O2@@RDj<Cra8f6qqZumczbF;X{2i1iX21fy@ru@<Tcu+#>XaO
z4vQ6wSvUDVV0Tf)`8v|oZ~-^O-N%&SOR!cpdF1BS%pVdT>$M`bmgV0h6xeU_zE;oO
z4*-W3Rl-A-Y7dtz+bq2U9bpS~Rg#x9<04uY`MIdfWedwk{9j(Nd`q2wNKO2QNo_VP
zF*q)GA}1jk1KG7WuGoq>i5F|<xcr`ca9JJMlm}{4A_sF*pAX0_YsEJ29;72Vurp$f
zzFuL<#NR7gW~f~_CKRLY-37RKTQeViMvIS)kJ!+A$>qQ??c>Q>ru<XpWPncwom_xB
ztQxq1eEo6=(x?3Pc8X1Q<ad1hJAiOruAYaO5H1RF+O%Aaus&T#A=@7Y-2NMi7=)51
z_9q>b8PB7nL~g+ir;Xm1<zN=d+7~ss^Irs37%y$>dT;VU76d|6hd!(3t{iB>*!uay
z)h-{rXArS%Qu@Dd(xg(DK<lEi=4CehGw1|vHyX-IwQZIT?74L9NA#-81NYfBCC)H1
z0%-M`AnCR9u<j!K%>RPfpOrTuTgUWGoCC3HbPvyFMi~$Yyv5TqsZlqC6*dL>jAGQ(
z9s`Z;#W(EE-s_lkS-khYOW(X$<vSFn(1@)l@dXxH>o9FMmZp5LAMo|5g0m{&*s}QX
zP~g7cT{r-{$u#MT*_fq~vyH3_$HBZ!ff#*duz~FUX*GS|rlQkzg{CXD{Of@qJh|q)
zUv$ki#$Wst#IzFqKXW#~szixjf6~u>Ov>}*Do!gP)1>YWH#OE6-%x_0eXOO1ABbaZ
zCamtiWez^sPRv_|9|%#&+;J_phV6QzpD|AZb02AC=J|CnE8GXgaun2ycz~T{z(F3H
zYO_afnWT`xxt!03Kpjmc4gj{H#A_r0fJ$=B3LSIK$7&?PfrHqPsyuZDooPp>DaS-n
zJyWhN&%VHS+A-HRkXq!4wb3xEC=R5Zsz%&L6|JrBHNPouJ&&nM49BWMd>f3LvXOdv
z;>Um&ge_~jC@ouXM_%%XuwmX2^kX!BxRNhvxRUPo@x7Yt)<LrTCM|LiF0jRPoS|r5
z|IQhsD9SFsk&z)Z$zZ*>E1@zzX;uVN)_QR-X_)zA((qpQGhXOBE4{{1z?@0kr)RQA
zQcEg}yY)4e^OJ22&zcU+wPD*J6id9vx76wDxigU=vP1uzkwFGRoTJTE)69o^&rTxf
z#cvr;Hmzy>F8>P-b4>n*zlMC0%@_p#3~_b<9WL<W((*4QMYpQk`&BD$@k|p-ijO2X
ztk>lVR|MMd(W4RQW^V(ZS;q_nJ`;?>wIfL!O<CDU-EIjTpeh`>!r<x+J_q-HFp7g<
zPL4MG3RfMInu@_sR3S*AYKavq8gwp$sXCOI)vU7>M~^5BU2F!M`Y|1L+HzC~^#b=X
zYB8C#&W4y1Z-N`!v0d|Qg7!qngsXzw80X1ziO<7@KXZ$;%O%xkpjDbW&=zJ+^GhpW
zF=-o$*?x>7NKO@uvEzeSQL>xL;@vM)gs0LSQp-5pC`M@klRXs~y<%?xZ>f1%3Xu<4
z*1@ul{p@3S!=G0ww(kG-S_Ev+&<Q}Uv~efp;PNB0&LMJ^1<jhgtPz3-Ql-}~UIyMg
ze|#S)V?Ti;Su$L|(G#%seERRdrqF_ChSSiS?^f3U5v+U!1Cb5`<Gl=0<9T9DnQof&
zXGmhO8kBvSBlzdfN#~EhxzGbh-IAD-cXr|Vh}Jk)c!C&&6yiSSepF@-0fyaa|9CU!
zjYG^p<jPz>sLQk_dWTyBs0Wb-I`t!2@-FtHgmKG~CKhcITIHNlc8Ebz{mj12X@zGS
zbPi5MsV>FlnIw~b)d=d>n-`;yQnFh?EKaV+T#=;-YsP&1?ERBr$Rv<{z?F!;-@Hpe
zB~A4KYJ#+e0V9#64Wad(@kn*Bov%M`QcM$GlWt(OC%=4+>D8Q`lcrI6LA#)t+SZr#
zu33zc^v+x|vRS{fqMB5-nHTsydoNcDn>KoPbSCW8n3zv$-5EV4edtSk=hN_FyR@$b
zj+ZQR^XE$yMHCK&wpd#X)wO4uHl;u>TzpY@feW}4FDw}MEW&HBDW2jHKXEDLyOh1_
z1Q9?K`?Wa-wdC(@Nv+jFzel?Z<}~?^Ga_Gz2IvsRKpa!V{;j9=Yz~Pf`<=|Vg7g|Q
zxRcsP%V#{i7uV>KW(gF+ujUK`?)nYg#N--a9UYyL5eV3-0?`jH@rdI_#^;Mib^Ur=
z^M&7PuX<s92UL%@W@_Ke4UnIGV|Wh;O4Q^`;ARJp<8)d|HDm{lCUQIz%}$6qwFN|g
zHl1RSw)WfGN~!LV@*E$+zO_;NWCq#yDjLNq-}*&0wk?9Y72nG9Tby$UM!uT7e*0Sp
z$Rz>)vD}@U^Wd`Sl?L;d15TFcj?J4-W4fJ4FJc{2!;&>*5sPZrMbq<{l^2<~#;q4r
zI?CV{>TKF{svOiXt+jQk7p3S|l<ix&Wtq&m6f<)b7K_=0)tExc=!kl4h|L<B_`r}q
z2)%BfI?nrTGA?o+#)vIapY1H?Kiq}4Ze^gW{VL0mXJRGYFD|1KYB|nn{F!N2h3VRM
zOwKxWywbS66l?16vmL)!I+mZc;I8zkk$E4Z?AnN5grrbWmWc(k?rci0n;*Ftid4c|
z)d<_H;LGJ_j#S)ca}mWq?9kVz;F#9W%0*WYu@DcSaj1-_)3!xyk(4A8lfC{ewuY8Q
z86vB%6R*z_%iENxdXVX$z|@5HPBFiRX3iwvFz+|+V%~;Ni}J@Tvvm%|VkjfuLD_<#
zp^-V?$yK$=vRd+6Kv;&8JW)ZEiW2tsl#1JbkvSubrbg}B>t(nM635*6<IL_9&-n*I
zvRIih>h1lNObku%M_GN(xJ69znq@CZzuGlq;#5&p?q$;`@~Dk;iZsU5j#a%Pl2+1P
z(s+w%1SJdwR7=LYjs@FNlWZtsC&JbEN4o&o<x_Dd?8iy+eYjb(vem)X>HNs=Yec+$
z8g@XMV#+)_*oa-0C|XO&#J?j8Z7x2|*bKL%G^$M|Ej!K{#36emZf)VuZ9y2pue_h5
zB8zK1W$d2?4zZR>Ul1oN;pE^!V#1QJXTr!<8Aoo^_(p0o{N<)%HG{EDr#d*R)lT{2
zNi1!Ih3h!({t1jk63=(eNHs}7kJ9wi)l!2xm&*@6SCX&B;#<iwJLT8a@>cttpo<Wp
zcT$D97@P}8)@x;wk$9aoL|S{W1swA)Iu<Dt!Ma6`)uA)<T=Fs?Jwk$NHQ*CB&uoD5
z0)IV~-o_c@u%PU5;-TU4@QBp~nunDINAPo4mPZEvG!WTWYqa>j_J|)N-r?CV-hq#Z
zgJEje1doH-6mQJ9C+>{NE&vcB?OM=l?iNYy#I%R}aFAB=(t4|7n=fdyVn*Q*eDoGd
zbh6M>kICutM7Ay}T1jpRa{ZDncJlQF(bv!du)eKAK_xKSWx3oU#anYI3?^aF*Xc@u
zd&*pT#k%_TLbb{D^yMtRkG6}YDa)>0X=Yr3M8-MTkzT>R!V%FGct-3UTySUDC=35)
zz1<~PlFe0>qZxa~8`@(s=gq$0KU(*~+k@#ymVTT~PjQpz8#bzOzSB6uduCVOHFa6|
zo=LUMvvt`sZxpt{={3kY$?8HrJ6Xf;!4>;Pz!U4qg4ev09qE?WrjmGjFhL19`)fcK
z@#8Cd+#itCx~(!sa0pV=<NqjxqF!DjSb%nEkoEs61T=8x2MfdhmPgY6vHCW}yMKc+
zOD-%bMJ<0zm~<^s#Y}wm?lf>g^6t`hDO;nr-IcisAxj311B&F+qgAXM>M33_t2|Vn
z$_5s~4^K2pbr;}lWL*I{cTz&xm6Hn^)~ikY`ZKGC>o+iuR(|C`L&JiLc}&y&7OBmW
zcPycAWOGXOQz*1e-r4@*n=tO8!jt?=X{7U*Cl!9~f&*2d$WShbW*9rE1<IpCmn3Mr
zVg)VCJ+@navncjzAq9;m!lLNWqH9`nfvEZut=!F?x2EBDGv25qHzfne-9kQEDte+z
zq3%OD`v7v9{7i{0qEJzblIzO1w5T}@t5v}w%OXB>st|+9*m(_aSyma>71=bj#V})o
z5m{DQ*A>z<T&v_2YWoD>2SV|z5~Eq&%+ly-$-|exoIx)XTI4f;h2lqVl3XF@oS!mU
zkVSsmY<H4T$|*GfTcd`KD5ec^DVDsp@v94pYmqlgNV-gyhRD1cfUl6{yKR%H4U3g!
z{`-y5+;Z#r3+1{ZIO0Md6VKB4G@g!?LkFb8xo!}e`qgw+IZN_EGbt4~v$DEgp<!ds
zw5~&ZmOs+K%1_0~+(&4!bwDMOntd-6zO*f4lN=Rk>rjFSm*c2ee$W<{q9zb;t>kph
zn?6kX9#`HanHc<qhat1^>!Bx45uWdABz`Mc6Om($J&iPwVy~M&WecFzt9SF8eM7T@
zW9`RgOI|mB+Eyr~P{o#^qoKmMQ<wE!$xZ*`pc)ms9%33;m7CGn(0<IxI89!8aU3T{
zwS10rSSBNt>|lAz#i)qKlKNvJWt)^k97&QyFX^^mh*s?P$1xh0a8(5P{|1Vv$}NFo
zPu?62@RL`muSLV9khDT_PpcGNUb|1B>y#C-!p+AL;7gRH0pQEGVmIXba-C<vZvHXx
z<th%Wf-z27TK6t#R-(tM3oUmHwf&fQD@(FsyrbWYY>gqSQa^a!DC%JTBX4xhL|^Ai
z3%j5^hRN+A)2>G7$RVHpIqsYg&3z%?H=phzOI()|@Z6?5Im&ePt*x);^U(ZtE^Br=
z3!`CT%TL2E6hobVz4`IJH;l$S>h8-?pDEn#5vd_(!<8$=mpza!k5s~NaGklNbSm-$
zHdXm%Km`&;Et5V$oUOWv=)w)abnmvJK}WEqyx8)Y&*>dTPG1+@Q6xqrr?;9iX3QB=
zX8<r|-*()gSvXu&)1Z(q!zJnLCja7VsgTuvNb3wqk?qa*Bz%;QuhUc4JkT>}&2)8k
zeVm2vIOIo6XXZMB)~nR3g=C<jbg~5Jfoj8pJpxS@o#u@2_c+bHBuw0t;%Ts)t%56C
z;XPw(d&)JGey{wIVO)%5n2!(SqAH`(o>Y*PZ_~|0v8|q@Mj99K-AwjUy=MD?)5#au
z&oRkO3V|f(b%pHRI|-_hLa-w&Ef9EaDS33M-*`ZfshhvTXvZ|m959GhsJS7>WJLct
zl^4D+ZXN$Ql{une)f}4wRE{}0clkB+_&DMpHGb=gSCytBFKgqEV!2>1#xm`3dnsed
za%)_LjMG={A23uTlZ}7*uC`jfzCf9@!|4w5IDmI-(_WD0Fu2s74P7|?>dtzBHtj#b
z?M`>r4G0j?m+N3X#&AcOcW6SOawof%n#Va^^>@de=fBPMChW$->`@1o{gwJs;n&N!
zk5Ni8FM3zSRI%RsW8dbJ@QUA3zD2_d#;J(|tLW%H878n+a_tv?0$&8xzWT97l%eu5
zh7pXb-25KO`!&Bg34=S;bV!@TG5beX#wHzY8Cm_0yx^+u6L{dVd75!j)nmPBTvycj
zOSg@psbMRmqA3`m-ZkH-<}|f34gj%eUl`W7#y;c1hE^TZF>X;{5<l5=T4s@CGAucP
zK%y#Lum(Gi0y<Ng+RXXKi!OQC^}aRrqEJu6;nE%Ru1Zb1ac^^8*Mj6OY*$7uLoym$
z^D2J5MaJtirtc}T?@y3p<JczQpz<`v^1etTFg8%HGgqZ7*s$i-RBA|Gss)&54Q9!n
zePx>W{j8)xA5ssiM_`UrwLTx?@^ghKu-YvdN5qr93sB5pL!w>TjF?}qHI_1zTam0M
zv-yBgkQ%0HKfMPwpWt#+)8KjlGb*89jo~>L&&rx878MqztC)*_S0GR1Ea9hp=frSH
zu<k0Kp46$7yDv&U6~o=R=RYKD7%FZ|APZ-#Fi+0qThOUvt};t1t^cM-z*(Z>W$`AF
zKGZ0hKGDItlUYifKklnScc?%o_O5=#XF41R#NN79G;|v4??&cP&b(h)u>x2nND1n@
zv+l$?18^5K=T?MoEy;sB{`Exe&ydGFP@k=K3Peh#s>gZQy$6kX5<_Qn44O;GNUUcJ
z&`;N7-d4V-T^LG52N-3x)Mq>X{_f@&x>=y9D8P+=f7#<|klRHZ6%BWo4dmozvbVC7
zY|Gxp6s9P0vM#)QO)SKnHHg0Ye6}Dm^|oTYBrkx?c}yilVfxCqe}t~k#<|#U`0b5n
z`z2k^Q7Lqo?^k4&-2?KOAX47d{fHG$fic4*i>ffKK(t}WdK$v}%u7zU(qE4%GJ^ED
zHYVRhusP4U9ZE>W+R69c7+DHB^QXTAq=<FK&q^0ZUt7g~<dX+pm<LGCEiLoLLX0G*
z{mf=UPJcI36X<Jggg}m3rZLcF6`gZr7?M3*e9N^|WlRGG1aJdXWIDc%4&c}Yd^y;H
zpTe1s7(O?n;3^cJ(~0>m5P?kZw;C)9a`-yALwv*H9jml|t^f~b2Id?xFSZ|+u;uuF
zZ~|)6ZTC?|I{ThWohC^pGsShUEgCvn$2%8J8LGLjCs&8K+~hR%Z2f0XS*tlvCp!jj
zE#mp~)&hz8cPKZ#U^#v%b(E}mUwZK*S4FDk&_x~04a>;4xC$PHE`IQzn9h-xhXlwS
z${fh3><aD)(g24VVuLy(Is1e{KGD8*6sxF`T);RKIPC_?Gu~boC8(+0I3^NHP`}As
z=FUzY%ywnVwGgD9OUKO7$IJ~J?Anw6KwN`emZW{1JZ`6~3{Vv0J@v(S!VnJYd~#$(
z?ej{@9AlGU-tNx2vU%+>-*oCut1v;HxB2SGfd4Etq#q%Xb%0_)c>SjDW0qRFt<fge
zmP3krL#}chMp}3OX0Yk&VY3I2DUlHBbHrY*KO8W43_dE#+;h>CX{oF4(;RDdbKDzv
zeS8)g(e{$++H8O8+_<RZv@&6s_pS>)3FMJ_QIZR}S5)}E8xH#q#<G!P$_v+io5>36
zrdgBB*tgGX5L(WmKTVQz&G9J;C<4<zO2Dt-y`FcKerLQwW&tOHn5`}Fv)W?3jpmJ+
zz2)~FX8LQ|qW!Z!NU8WY1&hzjar8!LU~5M1&8wm;$-1*<wj)1;FLEgrFpD+J*r#hg
zOFVDyn{XspyfOOyG*-_~oYIulK~iBtJ}ouV9(=dYWkJx8=@q#=&^dW(?%&T0c$*+K
z+OP*2#W)>RZGC&C*sy9C^j%_Z3R}foqB?~vW3CifNzHWpaeSKxj@~~8&^}&uy}}40
z+~N=XAlq5bc)fc<BkHEwohj9%u_#mCk+}2;>En4G@E`T#-8Do?6zeAb;)uoLWLq%r
z&G2R!7Og(lH7#F$(0%dTz4;uf?Eo~L;s$XsP4ex-zK)pAwy(AK+t}(`H#PVhpEdiN
zzpU_^ciCn)Z#1yBtS)ITX|8B4Yp(L$ad}j)_jOO5TNyff+UOYEncj)}B<MRpnn6uH
z=8(DoyP5{Wx<9KmD;F#19;Vxi;*df6@aMs^@QrX__-l9vwkKT#b};rm^|``YYOC-}
z8m>&bdZIUb99Y&M#V#3*R&30PJ%Mu_)auy&cJkU+)nWCDhSQa~3-R0t7|Z(O*_iOa
zLOOid(4ThSJpceBP9my2#-_z0jcqZI=1gws4{XhJ47xw5bbw#$h5Eb(YA%Nq`u)!R
zQvF8P9J|dIGkQ2MGs3`Bi;;_rCsK=Yi^L~;k$*ZGbXK1+8;2_vv)86P3$ioMPpq~y
zTb8C?iSoD|jUjIVOZ`)+9Kn$Cd(;h2>&D%SbPf0Bi_Mon-ySED^2fkc<q1Bzqs<Tb
zHUB);e`!h6ne3D71OFYOXEb*_BwjK)bG38}wB4=`y%`r|=e6RvQN|omlZ{xP=<T_=
zwDa=3Ls9Bx<tVZqm?}~n>?jIb{=QB>T_i0&3p-jTG;|yL^2K2hvobkL?1EK(eEn6y
z#q;v%tC+QaAM=i0+uA!Xndn3npa=P=1?-5t@Z8Ktz~Y?)74)9I$Uv1~x_;VcPa1V`
zZTmgVlO#T`XWvboaK~}S(ci>$DjRPPX*!5t`ab}hKxDt{=j`W2Tl<uKN?c{1w(CWE
zJ7uTDHE|KYOytH}$3voXJQ9zH8{@IKE4s#SjCT{a#s8Y<E<WbI>TVEUaW}fJiKpCO
zx_iV|-5U3RcskQZ6*lRk{_m$*5p`#^)Ftmb#s3NEM7h|Xx4$3+m+~Q$Z=WWm{C_{q
z(l2Alb4($=_r80|j!5xb^E>8zv&vj(zF@8}Uo>ArN-B|p=Mm@k?0P$e_{z8z*W-bB
z7GfQYhY;&n+>FQLiMSJY5$~??o8sLN=Zzd!tiUYQLfx}ov$kRd(=?`q9Mh%mJEofX
zO>-G?_qhxDKAe63{`>Yl%<mf+m0siUJ4eQv<IM5qqiFY1T;?2g-gVw{Qm%A$H{fQu
zt+<u-l4OcCnq1=b#qTTBxo6En7MP37#pV+8d*)K}2j-9bG3=mu#5``kW1cWiS;87_
zJz$NpK5vb-9<m;`O06$i<E$@P<E`hd1=e@1h1Mc#F^_gXw$}MGnBQ9at>5{xm<B6l
zHDV@{p21vaf5g7o?rz^=_poo{S<Hi|Tchn#%wnG4ISkEUzHNWUUSNOMe!*TrbC`Im
zc=)VYj5mi#&tOUt4<||!Ur3Bed@=EOVsc_i;;V`2i5ZDmnAxOfG@+!Gygb<^c}22q
z@~Y&u$&VyECqJ6(lDsK-Yx0g{pX8m%zR6D{?@Hd29Gtv2IV5>s@`2<-$&%#5$<pK_
z$n^lm$lfUbKGr}HwFY4{zY62!F0`-R_U}a(9yNROs7ZI7q<clvIwB`<9a;8aY5h}5
zi`vdH=d@GrG`hl7UBkWX?DFvc8~Xmsqm@5rzXJ1hdK(aZQ;>Ei4Zp26P+QIHfY^SB
ze@jTA_zm$+@sGy4w9pG+{em^ir-X=qI)0B(;`d_xqVxL2;2t8ueG=`w^!cZUF8OU)
zlydLuFFydyqJ24fGm{f_V)XVU$Q1LV4y~QF^m{7VE$u3W{k<v;vHc9@n6$61*e}@|
zU_*F4AJ3b;ovyQNnYTDM@t$ED-oK)}?}GTY5k1&GeQ8d{sD2oT(Y<gNMQl8mx#rCr
z&gbLwE+_?c(c&069HKY6)A!+|NxORny$#dZ>HM#=%lU=>F0LGo*BP6t7l!YK{;jYR
zcEvfqzL2q@lds6vE933>f0jQNnzP&aHEQ#I=MN&%LO3t95RS?&1-sPQW$SaoT#-qM
zwCm0>{oxtY_~m}6?YMM2^Oc;Br5RhA{Sma+Tayp)oQS^tL;HQRo7w)C?UbJrM-8cU
zkcXYQmU^*#F;h3r<Y&58WO1)bz3J1|4C@<K`FZ?UbpbzyV%FpJ<qQ2@{I}eHzfFBN
z_s-NeH|?2!$vyL1&3fjKpcnqU-}`<WJ?@M4k9d`zqFxtsq}}m9VKx^`IEfn)J^Wty
zF79`SB_8to-pSnCej_n2@x#Qv#5+{i(Z}A3{`7(5^U3ceS0rCbzLorA^4;WV=l*kQ
z$B#038Z$>We+zB=7JBz9#=+N|P0ml9&Fq?LY#WhY<*w#jNjN6!mpe%=od%2<_a$aE
zY2*AwMe!21))>nAJ}2blI|DiNvFF%Z(~`aTsB`SS+@gPDIG!E-IOed;wdb)3DN5-V
z7&%YTE=>zAe|(-e)2=qv0hB+N-n;QuTp}nB_NCKBeNkz~7=Ms*jB?%HZ2yv7=3UgK
zLM}<qxVe-#doF%z?{2}xy7Q(ot7-mZdeXC9zjEH(4Z!tpty;`U8c^d!W?blysX^;A
zA?dK0wnyg_o=?<c<@mYj)!A1sn3rMH;vCdq)L;M2eYZ5L!DpAug?#hgin3V<KNcOE
z#A3sF^H@hKy2k42=QO#?YvS%FEte<9-Fpu-yKN!e8(WMi)){dMH6MKv^+#v-Mby`g
z<lgR)bbp6_iFzgKllF3-bO3!)ihCjIfvESPzGr28RkQx*HoxB~&Ga{~Bz97t!~IJ0
zbZ%@honttz7iu}pQ~lZnQ>~?Y+ZIY_(|PN(hWh+F>pfev5bsSb#@h=`#cZ~1a!3nd
z{q($H1-Sj}q4tB;bJzQFtD!}pJ#d?A9?ze)oWJbu{PEl@{+8aXxi9~7-uB+Sx47$l
zxehe#EBsV<=XRQQyQKxU=Z2XcEfmr1qOO~V>A6k6+qn;)h@9<45k?Dh<~N-ESUJ=>
zwIbU&;M9rB1%1$@O^axU*=+Oofs~0!Exhx2E&7?wVw>10_K1DrfH)+MiIbupaiBL~
zDKOoTp=+TO?=3w1fAW78_5OiGC;OL9sWd7@`r9)64H^HNB>V*u|9d0+r4j$@BHp(|
z_$wm*H$(VqA^vwl_zNN4w?Vw`f%snnY4Y_C@4FvoeeuKl)`$0f5B{=;_e~G)YaaaV
zj^;Ct*U#H~H@CU<JmbT;E%|2`>T%3(pgq2O$*#QqRk40&w=`z8<i@M*2HH(4%pBWd
z-Z<ovL-R&0X(cW-EFK@#^Nx+%E|3$_EN@}-Zpp=&(LtImjSJh(+XpJ>Mc%vQc%@T+
z%_WC1Dr3L-EU)DdM)@J!*utFa{2`=gh0Rm(#szE4nUr_Eh#MpQKIQnR<a6wHL5t(>
z8|TgE^N&w&Tp-^PE#yMW_D6E8;w|Re1w!!8D9?`3_De`b^U{3tLiL41X<m=t6c?J)
zO6$(|8Or%q20PB1`peR*zswu2z1%o1!!V`yxzp*@HUFf0TJ$#1d?(9kE$%=(!{Xz#
z+ax~WSWZHG(s7+D#9hvnPCGHsY45ZbgPiM}8^k@%N1Ts}q0Ws?S8=~{v(sIC*6HEg
zDjuMBg^SNQy`4M6gU+2!U-5b86VAQjA>Lb<=%%t;i6^sz*_N0^`(c?kf<BJf{}ax$
z!r|Ltw7=!J1Km%%gWP-Ed)?2tL*4t_;qC+O=iHI*=iSlnLvD#%>W*<AamTukx@G)s
zZ`wmSAx=p8y1n^f9wHaAIPWOWD6hOc5`GP%8v6794|0fV#Wdl)P1LIubdq+7d%Bl;
zTJJVwx4vLmoO{nv<NA%d%q@SED9g0`e_Z@76o;nuV&^|B4m8(4A*9@`^+bGfKj6Ce
zG4l@8J*t5nxd!HO4eZ1<urt@dk8us`%QdioYhZt_frVTHi?{~f!!__;u7N|i2Hwv#
za5&e%5nKaDat$2CHE=Z7z!I*3rCbA_;2JoUYv42gAGEP=V**^^V=l13*FPvM@%80R
zWGkESYd+xc(pV2{YVy3biN2#5(&=9C56*+R=gEWJ|H5=%Dr)|QxYTC&N;ySNhngiT
z<Xor)a*13H*#cmtTqD=ZO>!%^1#$=EyV<M;a_{?S>(gIIlk1hBVk(YYt_YZ}QQD>z
z>`zg0l#ZaCm2OH;rMH}=^y9Bvbmnhc6eC1(JyI#5|7$}s7CsPHrc6?%!fXcka^m3o
z5Tz3QJf#YzOO<L_qpVWOAYZF&fV8br3A^)@d5Gt7&^7RFvpkIuPQ%Yxh-q8Icbl>k
z{2pK*zkdc#;CIR+^j!<NQaK4%_4M5e#24{Xx~X9~UA2`m?#IvlV(t6-R;@Va`?UPN
zXrk+w@>@{lZld&VT=4v6Jbo9P_<!wv2V4|M(|6Cz5+ts>3+y&1Nf8xr!2l*qm=hvm
zj(~tlP*KtI6w$*R&wv?oRut2jvz&UIVmv*?91#`0Gs3>rHA@gsJP+l0zVGSzO>Iwg
znCk9-S6BDUPV=~HF8;fg@c0~&TM7AJVWB|9e5}yF4gEur;yWiiK7Ymk*y2BJ!OtWA
zER#^ojs4RZ($>S!amX2fetd(Uea8e5%lIqMkN^8--|_%DjZuj%QYprfA;o_;i}J9q
zkO0NqEZBd#HCMRDct^1;^^tBydIafXOdHK))|R>tla|#Fq{7<Z@xNUHzS}QULyG@?
zV*gFn>=4*GqZ=!W<^k?FO7OdXgulo_*$%73jbDqQddMG$afacj+7IXve8a{0Gb6W`
ztg)=gzZ$>4ja}dj<uLjNCs=%(@*Ct=7SBo~j6}jYf<%LjIRcI;WEPxpWC`$B!ZrKm
z!7P$McH;kujzBL=CKvDv`ZvjaNSOxlGJwy%IrIi%X5qWi_<TCwPSMzx*;na-dLU)!
zb;SR_n~EI#3ISpJdO;|Ai{26Wj#@tcn<Wzwh&w_PO+TcO7}F2)Ifk53NbwB}%%5oR
zIg+LoQv3%?Rt8cdq<e|DhAWWz_=bosSTU}$nqXx(E33n`6yIYo*X}XZL*|d~Gsv|2
zNp(<mA*?JTp_J^ui!pip6Tl{o)Yk75pzN3h^~?NApoT@xdaPm5zYl9U8tXYbKCAC&
z+^<07WI$bK$Il|UI#S%v8#HCs9q~;GQJ*oZ7&ue1^<UOb{Kms;_Mf_}JNU0?)HGQ;
z`Ap=G1X`0>^jY0ldqP^0txLe~ovjhGUX$n9`V#otv-Moo2mTS}6U=e|e!({h*p9lK
zOhK}rC>!QHN6!BgSpd1sKYFj=d<ni$@Ff!Ge^-Mc@Z)ziIAT%o33~2YO7<?Q`JP2G
z4X@PZd6DH*dJKE(qx6H)8kiF`R<$N7)h^X8Vwdx_H`ShmTq+_y5AhUv+UIhS`Li*=
z3g5A@!W37Eyn~fC4W~`<M-eFm%v($&N_DkJsT@h}`wG`S5fAd9$^td|C+6K9(<GO^
z4{7SCydcd^)lO~Rd1GJ4*uB0m_6>~P`!lgWZmrZJW%)S%%_61wIR337<jIeQ+eOHe
zKmMH}<jEiZZjtqqA8q%FtfBlV?iX1{`BOY7vX=5A`eBjvlt0CzB5NvtipNDrRj}7Q
zDMG4(Dbk9Ns$hzzMYbS&lZgEnwk#ejO?r`SSTN1AB3rRwn&(BfV_9t~J}1qKB3rUx
znv5dbvS6B*MYd+yoK)FwKfWrmJqxD!tH>5DnC9;yWRqy?SWG42;B^tQ6_(~r5waDQ
z=Iv)?<GB<_MR-TSil|5_QmE4;XnsdKGy6LEqfq2$)y-TBHs`Rsd={b^|8cy$SDNI!
zsW3d?qZ<blxL0xk*$Q$z#Peg$$MO_NRXcw!_>c0Boi|dqk9h1Vpg>Hh4X~F<=9?S|
z3P_nJ)!~o$qx0qdIal!R>?>y#sU@|d*3_2T(Q>prb)Zhvg}TwI)SY_JTC@(WOY6}_
z)QdKu&1ehSlD49)X&c&>dee5)hqkAkX;<2l_M&}gAPu1dD0?&25puNzd%%i<=7-#^
zi2!%71!_m_hy?Cbj_APM$`f6<qXW@{yE*}Np)SC8qiztVDy>TNK?-+L3MBD>&|0(>
zF#w6`5JQlvF2t-y>k%W6t`RW?3B8C3NZEv#f~3vhULY-zg1oK3-<q~2r9tjCL<X|A
z1&%lMCUPi4JIKd}`T(arZBG<Xp3V@nEA2|mpj<tH-;4Gl=1{&qAW0w%gwPNgLM))H
z10XaEO00x3>kA!(4p3$$4Uf_Yv@vZAC1En@&~CIFl(swV4kd}AQAD5c&aYU1a*0qc
zC!I+{@*m_h$24g<{#|h1gELioeOj}QU4!q6=1NYi3B`E(01}|Nr#S`lPNLZZM;aXG
zG|NS)G^gOa0rx%!F>YvXXzzatuFq+<<J-f<Bm?AnTq{G0_AV)6i8ZISSE(RJYIYLM
z0aharR-<@C&?JkxK=U^#VFx9>uPrlBO)u8=Sl-B-7^ic5$DmeH*)L01Y!cklOxLW2
z-(NJFQ3eCR;eJG8W$~_Xj?tV$e=6wj6`K9<n?P(utQLa=$zPSsk`%Mk_C3}kp|qM%
zE%%0Ixi*3$`Q}d3OEU_``UI?Z3uuKsh?1O92<l(NOR8ov^q>7=3l-b_7m@!62fh6^
zDM`n4)H&>nSMmqt;Ncs)uk07a=(N^a0%DMj7wecE2O~lP{O;HE&53smdrTU%+HyE|
zYPH6>Vw5CWGY#l!rm4WP(?HwoK^ZFL#Mr6TQTITaJ;m842(#z{a%ux8;$ji>&0UBR
z>@y54tX^{DS%I?bB8`ei1gLk9&xU`dwhLnT>zt;arr$@`_e3iO{i!(;cz+^wG2$Ul
zu4$x%9E^(D{eq$23)+7V@;m3m$epeI4zVs3zkUU*GfeI$CFH)SJOShzy8M_dImfK&
zlEY)RP5Xth+mUbPG@&>?B#7ED>m_Kx%cu+0IWcnkMH1*ywyv?N*zVr1pq|v^%;&`(
z3ND;{Q^(q(xa{MvbN{Aa6jy5$HD>+yI86l7u$=2WeeFy7U2)iQns}ss`M6gK`U-V!
z<X<|}ZgbIFB@g#D-nj<qy+$zhD?Xb?an!>hq^-X)`M<6Q=5qAN*SX@6;Sl)`ahh;a
zf=+W5X&5O%r#Xo9Yh@@NJmjA-E68_u+P+z$Z9!}p(bOO%=)~32uhvn;;<Rm1qJ2|z
z8uzbESS<bGv+g_f5p7!pkP>uS8>Umvb)K0@ajg&(<uuWs2`hT$R6Kg}>?Z;Yz9@O|
zVA6(^xYOE`3kwY^`pL+*@0$kX`#AQLzNE(sQ9rc$%H+k<FCy|?m&DUCaqM;{CGJYt
zhQYNG&H0?`e}vBBd2*n|<kz;vzZ~l{k(xcY&VCH$S|*xgO`2wfCIRM|$27MYGI6x1
zLaG42*q()c!ikt1PD;{=GK?T4=(OX-*RC~x`|;unT=6|q(^SjxRw3WrY1<;A(6H|`
zc7M{2`i@Skqc)NfbmBU<=1)@MPDDk?y05ljip6RBMTyGrrB3^_@P_7&IL?>ElOypt
zIlfg?VsAugWw?|*3;q7}fN#+(&|K7Boh->WFErbU_Km<2!Gnm&<nOm4P|%6x)~wC(
zl|(&=cTOQC_<jNTMsG}fxyyNiS&5XO6W6sh$3I@-*7Pgkch$O+l7IIgiu}Xp{@=zG
z_RRe|JDw=$NIIGjI);uV68aOJMD*wsI+YmH>2ww`rL*aLBBu-K5~8B<bQvi_SJGr+
zP0!KGqy@c7uab839=%U|=u`TX_|oSzgLJSIEG49qrLm<k>0)VNX+gSL+FII@ZkG0z
z_N2R|qopJ10r&0>_Z~?&`Xl|3@N^U%MFct;q>+F$V~7rop)o|4js?l|K(e2RK8>ZZ
zq!b-b#}flOfleTXbRwNdjOZkg+Zg1YLQLpXklqxepH8H72Ax4l)0uQ8k<nRD9yyd}
zHpHAm=RnEl(z(Qp&ZF~)IgO)n#DdO;(kh{}3!$`&=psVtV!D`E(j`!SD=2?Flz$o2
zLRqMVl~4<-=qh4ESJTzRmad^|h#g%^*AjcWj;<r+=z6-Il&2f$2I4?B(v747-9$GL
zN4lAACKc%xx`kAt2{eIJrd#P&;zYO6ZN!--(nR7yx6|#U3f)0>5H;ONcM?~+i|!(B
zbT{1%IsZa`Ayw%fx`$Mwd+A<Mo$jOiNDaE5?kDc_06joF=s|jr)TD>#AySJTriV#w
zdW0S!b?8xgl+>li=rQ6+kJIC%9z8)%koxo_O(G5Guk=^ake;HaNF#cho+e)O3_SyP
z{Ehxb8q;KG`zFx#=SWkULQ_aHdY+yq&FKYt0nl)fUL-B)C3=apqL%?5tq~t>03Y{A
zTY4W*;*BV22Pk<Ch<QO@koGhK5aWx8X@H37fQa!!#B@Z&bV9@!17g~V|7s9A37r5j
z3_Sv(M}p|lLG<X-Xc`TOVHna!43$C*8PIWb93X}v$q12TjOZ~z^qA7gbTS}@VW>2s
zM~3K;BYG6{XZkZ>g`vkBabtnFQ6gegh!~29$;Qf3x)iX&5K|TrV@+4k6@V3n8(YMU
z9U{gaQBn?3QXWy_fGDYeC~-uT*dt0RB1#+(C6y2*_K1&)h>yyM4=2QjGa|zgk>P^K
za6n{K1Y{fpKf^>7#Dp3#;fk1WLo~P`8Y%-CP6EP`029>^6ZVJ+2gF20#6)$(gacxt
z2BM)NqQL>t;ErwYL9f&6fWq7KHlXkUeE=wYNFM?U83O7e0zBy}`U+5(Ni#`(O9M*-
zw&y=F!heOu;<rl$X(MS%LZoe^ZAd9;PiarW_9>9+l+q~$++NaNgp>A>1`=KxB<)9Z
zr30j)#6TJ@9Y~C%gQbIssdR{RIFU+!kp4i-q(4eW6LaYpX$(<G$4SQ#OKGfh0<n@#
zmChyB(go6$q@r}S^f0ML3_(Fk37_X=*Id4n*Zz9r7hJU8ZxO%V!k1-VYRUdii}oum
z>>Dk8`2qYO{2ogUejGoEpP}W?#V@g}<u~)&@e3>`*tb>qE86d>Jm>!wzoR0U2nvA;
zHiCoTB)AD4f~Vjmv=F=nKcSn@M+g?egh*k85G}+Cv5-RzNHIm2CBz9!gq6a2Awk$F
z>??$dxg8Obgk<4@a20qrh5JI9kRiMgvLq6rg~UK2m6%JcBzD|GVW-4V;v%UgsU@i|
zX`(G}-csi+J5ot2iI1d{SPzmOk^o6RvD6@!pCm#uR5DT$qvebBfK)O;GEFjDTPJyH
zMzVmP0dYl&Ip?hzeh=grFIg?wDA}g1nF4hp*)2IBIi{@{q#{R4Pf5;7E@^9w@{c9r
z_hkrZAKVX$|A|pfgZ_(1y^wPN{VR~-ztp)Y=*Ry-a}$x`m(2LX=zokf06EW)_CU@R
zq)U(*GfKvzKNV>w<Rqay9HxpudI@P`jB^m_K#Up4C_csH_*Tf@i?lj&EYUv+X?@I7
z5BWop^BnyzkoH2(Rm^QSqgiYfiOXDy{98!9@s6i3{s*M}k$(^UaY!+LZVdWMVf;+Y
zQ@qzsq~$RV=1kgPXhXcCD04py{R3%xlo@M4=!Uc|#zEP52jm!{e+0&Vh5pIte}^;@
z<Mc-US)?tH^A!Cj(2p(7i)q7<-bUIEb2yE0nxg+E`WGWL!Z@*vN~$7f8B+X?9glU+
z-$jb0;C@5@Uq}%Z+zs^WqJIe12I7P>MLxC#-yAtdk&eYU!?4D%mUyv6c=U_-bjFx#
zP!eo$ehboy$U)rl*gD*Mq`sJg5&ok;3cr5BgH~?(UGy-Mdn2CSg?<J5OzwBEIiAz!
zOgIHcIUCM_bK=}M56+YG;#z1A1?SEAaoxB+<O&xIzA$L{?U*CW^AI<JoZzC#87`Ka
z0>5|3U2YcS4Y_l1aE!p*mvAc~cb4~hE&+1)1e(C@guCp^))5kH8zC9#BBXMpBF-LS
z{mw&*{aip43cq7rV~-WE4-43G63kOTO(FI=vDF1ci7+#_7YSQ(dyC-Ds7@dBW51Qu
zKq^7bIP`ZxYJhYU@~@$PF46_axsEg)?}GYHuts`57j4?UfqF#Pg%q`nq$X1AdqRK~
zL+q;=L&-???`~<U?}8xKDr*rv|JjEYJ(}wO0X3D|&rWE28~bHF?gaF?6Cd|E7RLG=
z#%9NJj$$e?{vil~{5Tu3hjV}{C+KC`o(X-;1HV@fd2=nGS9-(vA%5AO<?WY~w+ZxG
zb}AsRE7>(gHXucvM%E$4ag7W>irO3hrOuJ{ShJ#T#6Cn&`{7rdI4CQlsQC$wVg$!N
z5{fh)=_;iAkygOmP*;<lNJZV-0sV+~l8DqDV~Tzp{qe2G?ACR`I%lm59H~FFW-zqn
z5b03qV(Aj;3TTzJQvA{zv4Ipe#DO@$=|J4T&vuIUg3~RhHn7hT99u~}q}ad3Q5E0b
z=g3dmyR#kKN015N7o_E-b)*fx3%<beVfF!>%uev;nsIG7U#<(+i|fk`;0AF~+$e4w
zH;J18XSRPXw<za&Ik%SE%xy>h9_|qGPjF|r6z&RlgS*Q;=ALtZb02t~*XK=m1;&GP
zJmqb82i^&<^PZ4~cjG;B?v*!xmX4*#mM>ezY&o;jz{z{^UQ8Cg1@Fz|#p~=i*>Y?1
z=Kc6?>_qvqW!K7$vgemO{|PdoT##3uevpAQ9eYCt(sb+-8A#KyXJjBv$NrIlG#z_M
z22$n^LjPecO~-zdfixX^PX^L->_Zty)3GOIAWg^qlz}uIdsPO~bnIIhNYk;0Wgtz*
zewKkW9eY~_(sb-|8A#Ky=Vc&G$Nrarl=+jHANpK6_O=Y9>Db#ckfs-~Spez(X*LUJ
zz(TAR(1f1a!vyUYt=$4v3)(DTsq6s@<q%pbv%oe1s|2)a9NH}F$zv`7bns3%A~E-U
z+z~D*$0Eu;lDP}q)ocv$I7i^Cp&mn<f<t?OL+h8XoU2he+!IZ-Dn;v>L#tb~)j83c
z^+SrbCFpySZKLuQ$a#$v=M>ypq-Zm1XH2Md`7`Jj?OSm+fp-z-O}sb@sD(5QsW_{;
zkJL+BiWDqG3YG#W@2V|JN{+5Z^mC{ixj=0xSWFeh#G2vWYNciTj@q)b9NuVkDMOeV
z_aPJ!_Bmb7vMh&Zk@}p&QAsNsj#k_eq}A~5m(l-}6toqpmYA*Z{{z17{FmW7rBHk;
z{{g=9S}IkG!&2eU9^!BoE$(#8iK`)1@xHi<!KG>M&UVIVftHG?)InN7>L{%wtt_n~
zb(L0=)|Pro>q#3*yGgrCr+ij2HY4lw)o0Nq+JrP1DcXzL6&7bK5n7hq{XF_2dqiq4
z?fTz4iv}+CSLm&IXVKBnQ)8juvz{A^JvL4|i(UdpH0ItSXBO=N^Ju0A*5iEIi`$vg
zV{yjIqg~JAdIl%XLdBIN(c&J2^c-@;bvU&2VJ^=6Hs}}Q<II*nj%|P|YTORwi0eH#
zW8iU}LtK?1;u@YOQgN1!IzlLo99)Ov(e@XxuS$?FbVfd|U<o*rmtc<)aOH*<XYaq}
z>G@(m+>9KQO<XDD@k^+JB2S;M_x~JvwAcZ><V8;`pl1r8hiUyOh@K@{^sIy<7ISAv
z$wtpkL=PJa_Q73_WTQvB9#{qI4p$d>arFh)Bm{BA3^g1ta=Ic_BVQa7P&4tPk&kPG
zLd#tA@U@X6jsqD;aphKA+0&xu7;?}e5?Uk0RUaWR7smqX2?=rpM3qnnDb8&L97!a@
z(T{6!0wPjqi#g!B4j+viab!cJ@@P4TYr+B|Oc2*{2IT1j|3lK3A_?0-5c@Q)oAF{x
zh-=Mfb5X({LJqDAi|b$_k_23D6>$ApT>TSL@*oMVI_)~!@H|MGmy0A3c@nfJ1RwO{
zcM^rP+;){<{u0z5lD^1C9Vz^c99-X%h%13H$VVIq;xmH>=-10dq=+P8SRN#y{UfnO
z|4XE;v`Av#<eh?F-#3z$lU9_vNUKY0NZq9#(wfp*(z@RbU2L`e!aq9ydr&B1q71gj
z6QsDdD~^K#t}}@ihG+$f8cslzaHy;J*+|#r>JL#DY7h<DwSTlMd9+qJT;b)ju#LrW
zY8xV;0s2upiYvbYKD*#Cz98n0PrU?OArmSg6>)Pf7yZH`q-Z^BpV;8aH6Mi>JCp&n
zCXdfR#Bp4}Cn3TFq`1DtClXR%9_B2qUj!OIo`*5(&JFB32ej;*z~c1Iu|q_gUK}g%
z=^rOPfx)#vej574=W^l<;Ty{%*dvwX){>}?M7u)N^jd`A7$VMLzMVW095Y4xM}p(6
zM4#kn7K!+j32RS4`$ssVm50qJ;_%DUvV4}ko3tug_jNw9@4trzVKcO}VmXU(W(>MQ
zt6yMd90@by5zNZYog0IOnT48VCCrT1Lu~d$DhzYqiF4!pGvg#KS^Ta)wg-+af@pV&
z`X0aeEIvOK?Om-dFhLH^o3&3iam*2)h70)ANNc?y=EV8#M>ZIaa{T4oo+Cb8<;C75
zKFLKbqa8~VkcuOxh$QhT6KW7%)F9&MR7op;3d)~?@&gqtw53SNw%MR88Q{nHG2c=v
zKZ}XaaJANUs#eaFY~3W_JUib?OVj^7zbg3rDvLeG<N+T#<Z#vq@zD6ev8RaROX9F2
zxrB~>|2y#bl6J`7X8$R&7kB$FD&)u)7j#7F($h=NAVd}@>rZ%Ds4NQiS8Yhl<X&=L
z(n#(n_anZF<BAKUgW{6n9tkw_HuE7v%zVu{lPI$wvmi3cEX1ro8ErPkY#oVF?opm5
z8&rv^M6zF%r23T{P+e7B#a+K`pw|&nhXk;_6iHt94)^CVk_E|vW&Lr--XXG~aG!RN
zb3e$NC%P<*a1h!b=s>osEsH}q77Hko0JNTx?U~EoCt>gMNJu<M0KXk69(NyPe@CXk
z*yqIAads&6ee#YAhTl3c$9N|moKv<h=eUoQ?IFg?9AxgS{J1X+Cv%4@CT~xu|3D&<
z^_7JX9ocZ%4^ZN1vKd5A_M7Z?sF_sREn>{}Y$5t=#};BP?<ns?RPsJ@e?sMB<>QEj
ze4>03QOXy}7ZFSOQh7YFl5dc2B)mLPzMTm2)AG~MvKQqSiGlp3{3ZC`$lnkHg`Pr>
zm?$h2mc&%iRne7{R`gNyAu`1<#V{gQ{Gj-OC=}xr<B6GKh63bKY*1_<WfWT!TY&CW
z>?MYZgNlPdk1I})vWka_hs0Wurg#eUt>P`j&s1a)J+qo-HKCP!%sLPo#Egzve`qls
zvw>y<iNfrX*(Hec#Ow*s*JiJYp1F~^5zt!Zb%3@tZws`ud1s*A&3gb{WWEUKR`abu
z_nYqrnqr;;RAa6orWO?}DiEnfTZ^_p7g{VNIu=VUmJ&USH5O}t9<n$DG|3_f=q(GV
zRpnmgUSgv>sys@l^0@LiQ7V4}9N8+*D$hb_iZTWG7nB!(e@S_XSShb4uMk0bRe2TS
z{Hgqtm@2O;uM?^Art&6m?kevRh4Q}gJ}IMos(eapRc%ylh_1?8<xNy7AC(WWQ2DBS
zNhy_|$`5EKRVQMi>Za;ON~?OPdJr>JFI6vMtqM{FL8=f{2*l~H>JKzj6$&v2ss=*L
z!K%R!bBJmPvHmt_=ai%lAX!AaFC0#ADB%>*et_Zp69<dsggyFyX#XGDiy!TW5bdwH
zPC(878LBgd%oACjS=BSwX0FZJsY%eZ((K6;vYKUm(D3Z*hA=|T(v*W=m?wQ$n%O7w
zYUa5tFNo^{F?BV5AI@an&5Fxfl63*UVDFN3NF&uu$;~$_0>TUA%kG?$FHiIV{e5A?
z4VJ<9D;pq-fIcut7D)_bLt*qa#t}^lxEVlX(4tFl*90l{7#?~|Um`$CHWr3JdI8c8
z0Dq_~4E*7;aJElA<S0OnY>XTX`3jIPjFhrrkh`EAFN4g2!5;$m;P4)-SC%nzHgkb6
zS2H)@{%kRq7%87ApMffPp?pE~lrNPpiN5kL<zK`=`C9p!lv2J`z9qc!z4AT8$y8<%
z9c7j>3)+!W@q|<9sC0;-N>8OvBq{@y0TEP&DnnwRGFBNAxyn>!N@OajN(L<}SILR7
z%1mVjd<&HYk*bs`CA7Px$_hBvDr=%p*{bY_sj8f+9H64Ssys0RiM<gCVKA4K5dDI!
zjTX-_sC8x!vacPo7Vd>D7s*;p49A!(oFm4pWuSJUW}#l8PQd~RGV2dDv<U8I@Fi^k
zDa85>0zd2Z9HwUVYm9ZuVfh6tKab_t!}1GQegVrb!Sd^1`2{S$E|#Ci^7B}Jy)P)g
z3!=^ij!0JitmTMUR(?dS7>+R`|0~NcT9gjNCBH?<1+(4%;1IMYyT8E726FZTIYkM%
z&*cI28de|=9>xoQ!YP6jLC67Y<F2s0@|lYL4@e5vjMEYh#+N9wSZ`1%bHXl@EpS{e
zG%Nr{);jspv3u~iyP>X9Pie0#r!22@P*xE6SjvKYPBWZ{`;~7eM7c}(3$YdX+*071
zf2aMl**@-`%F)VMqyz3`7=k+)hT)#>Y`0p_2&5(Mv}yLGyP~Qx#d2qPeoZRe^Yfpl
zvi_=6Q@<h=_f@HQ+?Dj7*WvQ-mrB$1AEyFzXr|(ht^YV38LZjC(tYV3y0|khOE(wy
zbp2=PSe-<CRq1woMd`j4Sv=^YuW9Xw@6^x4+D~BVaktyfvM#vGt+%qBHcz(Ct_1Sy
z3N7QKtwC$l1L7=0l$Y&xD(-R0atuI8a;~`^nJ+)OUYB_|=UN~ClaePCY=g0Ra%Y^b
z`8i<kdF9E07smpbrP6|kd-`%@5n*qQ=z^YYD(kK^R(dMgp4gr+-<c^}AzKY|otv^-
zvKO)p*-JLRk@uB{%EROX+5AR6T|NWmGkfLx<d@`^<yYl5<+tQ_<!|L#FjE-~vywzM
z-!L;VGd0_0wjJgbPt0D!TtaE?40DOPZ1!N@-#pBGn)!5?Lu`e)LyGwg^Owq=ggvK<
zEA;dv<4W+z-b*-2vgd#G_x1J1Iq4|=SASn$e<TU(k7<Nsh14D6FDiu3G(;fo4PIDC
zuTO?>7$W5G#CCHa^$UrQHY`}KtOo50Jq2Py6xyA3=dw4(bk+m)Vm*q#tJ5SWe>+mA
zko-BYkXhbk3q6^<+4*|u806$tj(8T57t9p2lG+q{^4cd>dF8yTGo{EHh>#633;wzq
z5RCHFz`x0#9oqaQ38<}@b?sYt3v<4jE1w7%hP%QS7IFqHtwKWhP8w+;A)hW2%*B;Q
zl<Zk1E0b5Drw+D-651H%S8$fo?h?xbkIheHaIp3=%Bj^(I#DHXS1TPy?MPdv(4NV&
zed7z|Z~p{;eBpeyJAI)&KcUdNPlwhw5ZIHA^51E8#Vd7TcBQX0B#l506VjB~OQg9{
zt~4htVftK#v{hOwZHTYZPH9K{logfEq@%Km(v@^mR#jFbJ(ccC57Jv%OIe%vLpkb^
zKxIQ^BNC)+tZYI;l+Bf$Nq?NTjf8od0U1M$sGLlL5=xYu650dicN3tECo6v@_Bf|=
zf)*nDKJ9q~&Lr(`ah=K9-wSzoSM&I97UR9{!<m-nIwQ~Tn|x<>S(CnTxsQCJ+*u`9
z?k_yqJ3;?c7QrCLuLdh-9~?(W5=kZ($W@>>$$jLdkqq(%Xcl?HNjL*e%9(RkaM*E<
z;A5u?SB<O1)#sXUt>AEh!w0Dg*NN-F1#tbi2-Gm|ax4IXPwNQU^MtT5$xY;QZGoCH
zzvczmf|T(U+Eg(ldpCcA?;H|t28+WzWRwTpp?Sc?0ZkVDNRxRN<ex(SD4^H*S&V99
zGJi7n0dtGP&{oJfg`9^NrxoVL#uCDE13C*Sa)d4za~!i<xW3H3(bZ%BmgDhX;erBV
zqMuJkdKT$j)NHH<A~`npSNhT!-IvavRhck@7T2kMAw=b<st6+qdspT|@to{WB%FTn
z=f|1g=}7v)5rJ>q^n;e~M<#%NoJ|&xc(R&ogmX37Ms@=Zj*(M9&yq`kj7#J;c?jdh
zEBIx{J8~P$E?v%u6Gu6Qsq2WZ2U<)qRGMl!0aazqV1A_bNEKTD5sWhl<D9`bXONG6
z&1{Ux{0fa4IgF~1DzaW-d`1c0g<yQ5VKZBz<)fXJ6^zu0^@dD*rv~#Rnm$O?q~M$w
zuRn~;bFK4sUgiSaIsHLt4YYb=RcoSB?NaRm%L+%>tlvHv3aQ_n`s&n0=KVhNGkF^k
zz4s28S3eVjmF;fkj8E(ekKwPQiwNKLnQ$h5(l-fZWw-jgWN&sC5&rn|;U9d92sik5
z;aN#Vgpc@_;YobNXXWcvMEI=Fgnzr1{cjBYwrFII!-M^jGVHx*?XEFp=BZ=K{H$B5
zQf#x>*T$S4A0Ja@9I&E!j&n6sm(ta#Y$EVfhp2n&8dTN=V<X0$=Opp%)$P<yc{o<f
z%SKz_qntXVE$KrBlW;PC1d>QNJ=vkQ&6Al#u|oK9!$sfie($Xh&aJ&=jek48azDn$
zC_AWQBuCXT!iIQ(=XhSuzR`0cD!K+YgoX@4flsK7bEM^TK(1jZrqDs6E9X13ca^J4
zvkQH>LC4;MgG0iCBE!R6rD_w#)RXJ^1O|kLhXuHnRa-HRf!wThi2tDQ!Qp))Z5o9S
ziU=RnJ2C`P*s85rxFA>NhWmzu20FKo>>V0m<K3u%x~zq<YYlZxwY#f(b&u**yTGMK
zo=f$Z#BU;*vD%P@8_FfE+j{%BR#2B0FUy8C3W*2~9Ax9wzOhZ?_HAl4sqW_CT-Dv(
z-Pxmodkxp}YJ0InR)v<Rec+&>A^w5t7|t$l4Rbm~h~Z2L@D2DFjw724?Jd`yn&7CY
zap!1ocinN0LmG^itzERP8sBT#rY1WLj5n@2Z``Eu!!1j!UJmY|3IDJ&&Uwz?mi80=
zZkPCAVMo8r)~A<O|K(oq(?JT}!t2dMv!?OR2Ghxw)8h}d2>8|Gz^y5jA0Lgay0h{j
zn((&50$p{4N9sQLvFP7h^okpJ=ho5iT{CJmy)8A|Fla)zQRNz$Tw1@zw%UZN8;8xf
zcgu9-&la)vQ&s0r4m`2y?*wnBrCrW+N#IV-jycA?H{%1-!VXvv=kYo-C-s=>KBd&s
z1AT9Xg<iZF-{RVh*-J+J_=kDlLtLdQZ7aO%a_`NHGEYn-fA?=(R`KJZfVtPs{-SA;
z-0$FEYhHkUv?7Kp1vR3hE(29s#zbN+QCv9qw_CylSJV5d*)Kc~y1whmo0dWhm9dv7
z)#lL(`)Y6g@M#iZ@U;H>q3;tbCmgMwXsY&Q5v(Px)h*S{<D14ej%^ei85vQlN)`V>
z16)G0+sVa0JhVzg{}9Hl5-}(|V2FR@;3_%I$XXE_5m4y@QPiDu^`T?x=;(2rq?Njb
zx>@$Mnvbocy}__y!wS1W;Goas9I2KwdCN<T)CSpE3i|mvq`*)T*OmPFY(=xlcfD%{
z%`SH+eENa<sWn$SwVvp-wzH?3LBBH}x>-o#)NNBVM$3P?QT~Xemj3HDce%tHVT}UY
z+^p-;IHKZ^l(r#l&7%^NfAD;!+Sq#Q<{@rA<#guFxYF$EL$CKUdYgCd@!QtQ9p)_c
z>2~;#x`JN%rB)S&Cmwy>qPnrF^$OSHf1amyQ!A9JR^L5&Ni(ZSLnbv^e5IoA_O<Q<
z6ibq#2JBL;A0M^CJ>UR0EA4vy(LGB`eP`=*xjH)0v88NDwV26O9DBJ-Uj)$$F@vwA
zy1h@Wy5dg#>bCpbySfF3pT1K0A=le~=DZ2_A3smvx4eDb?L+FAqt!-jZ+G3&I?X5T
zojOLB12y(2j~YAnXyTg@W4s?}P>mhSTWf}(#zuV;W#OoH5Ienf-td4xoAx0=VUR0R
zWHxSUS69?#?rINLS2r~r)kJNUd#R56Ch}>+g-?VRsf{K~+FkCb-t-00!_7W8^!hMp
zg44TKE9Om@+ho^@(>*6vsa4gb?98ZlBiC8Sa63kvru&3bO`aT||N6b8OvX<J8oRJ%
z89{ZAS5V$_wEjynyMce&ojqn#p2`<gzu^(#8(uqYQ{z(V=7$eVSI;*(J@nVtgXfqJ
zJ2!dn?34OG**q<~w)%^KM{Y)vmXlKcocZKZRMymYn|e*CyZ;yK&3)z_JU(vgjLny}
zR6g(fzWUYQ2F|))R+Bcc|LM{CLnCiW+cmrJf+RI-wL-7@z0Ss&BNrvz?{ep-zb-8>
zwVt;6?l_CXmrgA$!=21*wnjdy>O9+KZf}m1TTZqeXn$&KSjDbmo_T~tzucQ9H++(<
zjiRAOMvCgDJX1G0BXcW#E~lpodDPYEOMS-u-mB(gP0*2UDM@=b>^drsQ~R*s(h|@`
zE1Rkt=O1aRsomJ6j=Zv4RkhmHt+Ky|x>}#=fxVrp)$CKvxtd#54`+|6HQby7JgU3)
z?d|4Py;@)Yk5pi@uz-8sI_G27Te!R1?Fe0aY6w5)(<-n~4HX_S7_}h41#k=~1^_es
z_GH9a?e47hKo!_Kj|%Ld25Tjc3T#~D4YIZ1XKoRxHe!OyIZh+t)g)hc7Gijg=$cz!
z>v+UF$-eFKc2Sp~zRCP;|HVTu-dg%SZJ!j<ROjNc(`mOq%<np<XK4?|LpqJ+Hx~?_
zu&?iiYkQyY9qf12wU25Ly7|ou(q;DiNmge{%{jZk%1ga&mHEj%O}qY8x!UBV(>u8z
zZDX~??v(VmD>2e_)t_&+OPXG8^_a=26|C;|Ei=*6MblAeeK>4vyxWuQiB-J)y6bK=
zo03$<f7f86JC{Z{m{ywGc#Ydw&$*r*n-8;}n6*`Ua?(A0vv$WTcX91nv)|mcD<|}y
z>lpsx*yhLk8(W;|(`L*LU)pq9+^Wz+VHHlisbHP-)MlOG))&c!3ufQ$w>V_%vKp5|
zZL)s4s5!cOUX4;&brpx>6zdMfo_Q8?cteMBjg&i@{S*~@_HD}Ida6GZ6CX@n8eDEd
zaP4&`quV$<(6?>npSkE~v({C2`1NXgxy3IY(=;yExAt7wsQ<4~zi-{!fBM(~;|HyO
zyz2eZ>-1914*|c1dg|XBId<!&eJl3-@cUf9l_NTxmNo5@V*Bhvonx+sud8?lta1<U
z<y~)=*NnFDhLaDB>h$-?pz*!0Er~mpH05-7(_4pJW<TBfcY-=JtzYxCkLC_d+OK~s
ztM*@;2fOQT^ZQ+OVeenFPmQ<Ai0;R=-Dx>yaN_x{cJ*p?Ql?Hw4?5O-O_e{(Pp;eJ
zY+5z1nPv9PG#VP?`Rv#g=VcOpTC=y$uJgYO%V7}EgF)b#I0zW@HV+mz+_B1U!uCXU
zYEWvH!^EF6oB}wNxd3Q%RjDmLVwTDQE5NX_s5i^y>P?^Ua8RBA-H^T^{=FjuZ5j-T
z3=SU@5;>eHceT5^n!2j1TlK2ynxNd>T=BB1nq8Kh4PBIeU%G6-*3@gwW>p&5-$iw6
z|Lr@+=eM)>-jsY@*`}On`nfgdT5XC{+mwEychPr_S@YSJ4QFkR>!x<NO8P(iVSn00
zJ=51FlDOv+&sd+XT5kN}j8{QcP9J`FFrm!j2W?g?J8a+n)YNy4e=l{m$Ck4R4JFIp
zt{(7n&}GLzo3u}eJ$uiwiA#lzv28o}7~K_|-uIg^Lmf8$WoPx`ccU)NOMGZMZ`7L<
z`Ahv>?L&RGH=ePy8EMh9Z|MpZ`>vgL_q^_y7R%p`TT{BJqEyV%aZfu$WpNA2c<cW}
zr0OP5cipgWviF#?@6s)0qZ+slJF_sg_Sm17_2ze!G2Z&&^}=mjvRzAG&0C$LM{EqU
z_4@{>ku_@59F3!+7T_n3J}=a|Wa_(&sYC+!i&aZ?OKHahGmdeHdQ6<Co5##hkC_^+
zFxeQ>tG-`_dH2f8KUBJ9(0)$myDOLZuk8KJ;Ta<xzR7%9i}+QWS`F^>N>A<*sP+~I
zh30A)hvFN>H;AqG<#usS@F2J&Q{^}y_~sc9nyH(pz48nQ9{<E9X60xk=K6*9Fx0hl
z-lU`51g{#`A8p?>>{{~hcCERsE|CMfh8oE?Bp>);`fisCvgK1k`|R$>pKfC#_nv=!
zME%<x_ipL5!0J{RE_UPIsEo;H(`s|+w+~D=&`Fxw?Dq5aX4l(pn05ET)P5JE58t1i
zp<CrA;nB=W<?JHf|NY@^)O;7?*Lt@j_9@#ep4Q)B(45`NYAy<LKHkpcai4DW%;P58
z)Vr-m-QJ#YZ86lfZskFSNslAyYJM`1ryeorJ?;7B-4;*UOdfr_dgUG~4nEoUqhZ4z
zF0>zHo31{!H!84OSI)vfVUluH5%*V}U;1`RbguH??N701+W9?P95H*q#+t1z{5|~O
zdgX{d6`w6%Sh1S!FxuzWx@AMHW1btHblUrSqr`h}(|+7>XXV<+>bu(<A80Rg7;0F@
zXUf1XO&TfoB_<}c4oX_uP!m1eHhPJfy6?k=vK};PiJk4)Mvp2#+WV^68K(<Z+@f1K
zRBBePXP3u*&sN`<zxY(G@cm;dMCz7KA8LDWVa(wQzB{+}t2=So(B9j_mdRHiT;KG$
zEIf0P+kkCZsqK=c*#Fvh|Kc*^WdVF$=PjM5@4jn$Z%4u@|Lsw}Iu{zacyFAYuqtXp
zV*K18^p9EN<wNYMxUJO>i|;z6{K5EV<4)OLdQ!ISuM5(f-+avlhEFv7F)1YJe%RwR
z^O9XFYD|uI?RKTL<+3a9sw}DJ(!sp{uksa{>KMHd>KL6q*+YTJ3~|RlA^$XB%!F^E
zirv&|u|rn;k`9?WBXEUb!^2Hoy{0&5)WAzuHM=bF8A}XbaO~jO*ulft0ex=6^LK-!
zRxX>agsqQ}wyw4(V`nGZr421B^?%gGd;M-*4=QQCXY^5{ve(`FpO9TKeC}~%zHUNN
z&5NAEwc+`R#=`@~kDA@9+<+}hnlE}3+#@A*Vf$?cPDi)=v99vw5v8_Vp4<6UFRJsX
z@6d;CJ`S=f4>ss~|DNcztNWE>F2axv!7opTzO2=4nfa?Gdv1CJYzzyi9<@5&-_-eh
z{h#05xuIu#vD@%f%_}}IJ`gV-c3^hhXYcP+?jp5r?dQ0B#Gsq9TDzL}xbpOAqnTs>
z_+i@*v6g>$Zk^Ko;l#G%XvVTCo$t=5?Yy~ar{lXkv)s-n3U#+`+cL{zRLbILr@z|x
z&9tpv{%FmxfYI&uEHd4svLAQ))gB>s>g%4*&-xskGJE{KL$;CSdnz4wo~hvIQ9iC_
ziyFU=+&XKsmHnD^ebahd_q*lTd~weSx65}wZ`;z-=h%*p^~wp)&yDC><)Zzai0-EC
znhZ;PLvHQc$j9`&cE~JozvYDvEg#feX8Op!`99@tuaS-K9zHr~#LYnu%B3D`GXMCq
zBUT-+jh&j-y19DIhH0s3U6*e8a6O^#?ZflN{P6VB)0PjKS6m}^T)pPUpy>OP`b72I
zR%P7fj*Ge-9Omfw;%Vqn$LUVf>$|r-eCsE#iN{K{I(}hQqbiYeUWdJjvgza`@7`<9
z0?)Qp$6ZaBU~ywfn^$ua_BDwg5SMcE(u65FW9L&CJ0BG?{N)awh0aS<ISCZJ#Hg$R
zX-|fbKBN(8@bS1>U{KCG;~C^!i+7#T=of`fn_G|9oOC^BKe3v+i#WKkCDgX@t>at9
zHvdP9KG1KW*FtB_nUwTYSMBNMhQnNsJj0xi+FRWw&oI~U%Z9nn<R7UXvy=&MBN;PK
zJ!ZCg%*>ohauL*H#;WUO-;U?Zs}?oQ3JCWf3?&N*?LBC?f5c#y;K)#Q{hSPVb+xi?
zHf2aF5=eqbZ!&=NBoVl(976obaJU*wB7x6Vm_y+V1D}gcnZhPwK^d{D;%@p5r!MEO
zL<ZR{G@M)dmjA5z4d?!tGTdm!;lQ3QPM&X$4muY)HtRsWhX$u=A8fjA#mkUu{s--<
zubS6AaNLX^CpYo#aK&iW$Q0Vr>SdjVlYP!6WcI(~spnF0;r+Unt1j#)Gi-Lv+m8Z%
z^{N{+!v3ZF$JH|;$4-59+JSFU>BuDM-j(Zgj21o(ei!UAC%#g>O8q-E_qQ$;64oVd
z?%lDk4o!dAr1Fgqwa@Oa{w%Eg=6hQzJUx5;rOB50j`QMLo76ST(4Tn8`ly@o_VeS;
z$z7LhZ(h^jgu#&$n>OFu_Qy4|3GEtp@^BkifsWq#s=}KaPPJ@8;<k037#tS9W>@6V
z`Z~I+xk`?nG4<rF`x+ifZ2i}*>7%W}&3<gWX6U{8l>%2B?e5bj_GlUZ8uMaPufBYf
zVZLlZg<HR^ns+w6yMKc_UG)}?_tYJxdro)j5NpMO-o1A`|MP^U<UneJlO~SoHv+4q
z&HH;<x4BoyrDaX_cYZl<RjHQEr1PV#&ytGAw=P^&uko<5)lZ}>U%qt22)lR9=2&ld
z-_$<(uO)8|_TSZV-t8wtqG;M<_xZz>Ej5=C?SqHh-}3Im<R^yFk3(v2`JjF(X*Df1
zbx5fH%(~|m`?YC%FuJ4NvZ&H-wj-W3FxXn}{n|4tyB}UQVPVICer=jHKGg8ng+sd<
zL^tc7Ieh8i{h^`#e)SnFHy+{rn`?|DK^-I6$a9=}%$$-QxC&nm%zZc#Kjs)yK3Wi$
z5?qb)K6wEta<2?sP1Jcq&D8d}2_>$e+A?Q*t(lhb;?fvdYQ_DbGsf+FLT{)8@+2{G
z^;7%CSBiEdt+8Vbf-c4$-t>j;WJ7$Rqp?mG1pMCM3ns&tIYi}MdpJ~G+pkAQL`6xZ
zcBOKP*?Z4XLdI#7lw+YZ7)+R945BDSo=4<d6zQNO(n+EsROqD886gr;<dkE5YwwK?
z&-=dL_5AUD*LPjtn0xkK_qy-3?zQ&X_iz37?z%cM<oKjdZqcko<a55dogT+_J6x4N
zu<X;Z4K{0hKE!mY&JkYB>+4LvLc5&2ZH-kdvWzO}`my@ciCq*k-`0V?fQQ~s^FN|h
z?d+OAx}(-^O{T7V>z%H!ieGuRKA^0Bi}BQ?ggH;U-bAxvp4B^NT|UBh)4IlOu1e3S
zj*y77E@ky`K3Dgyt2~{SSXvsJA=#%Yu{qjwsA+HPnmR52+okR88j%xCl-ry%T-6JN
z&t4-(4_(`Hvo<}m?oO;!568e#GU0a1+acy0k-BH;%iP>@YO{)_Ra1sOE0;fV=_$x~
zUzNj*pYg&u%hgFe-6ynm<WRfKC!bn7{}cLYTy@pnOedk8W^WNw{Yyi8Zry?Jp9b!p
z-xJQ#`ut2&E3`ho<VCtfft9to_qF6~l>@$$x>Id=3tDfKbUGC(MLbQiw3qr)oRa;%
z$kF#2q9#AXD`lR*qdRG)oRyg^J*&aG_Hlfk>g1WPTPkwjth*&=qUo7nKi8*Wqeo)M
z>d+6z5I8e8CpxlurH^!``t<~vfxFw?4u)B9@5R>IZOf01))d@n59yPv-REc$&a=y>
zUo##Elu$O6(fyjxkz{(>;DmkcV&9x_L^7bJ@SR(ew{ibf(}(j_@4LVr!sRKd>oThb
zbU!p-&398vy-j)6Hj;X$bJO4*gU1J>zJ^P-e>~?<`?V=2wcwyy>eqsb?JiYY6KPp*
zABNw*@u6<u>l)vj$EXD3Fyc{u5Rjk|LHDapuPyhLeHW;DKj-eb`22JJ?ajU|1?}&1
z4X*Om*B;qUZ~kldW#@>%5t-!HxAirr<7F;hFx<Vf_h?0A*9NQk>RYE(@5;0P<Y_X0
z{^I!=FF#veII=+f`Wq@&;j7!j=rCEPrLo|`zz1`+u02l5ALfg4c#d8|0f+65o$>8=
zh{6nr1Ysu{8lq}CY%h*JpC^RWm@HlFL|GpZRnz5oIRI-mPl&0!ARFl4+X6o`KQAH2
zoyBwF<8~$jM~;BYbB169^kgckX3BBqf*AZD7$p>D-X0!q9Cr@rmn5pGDT;M&&NpD`
z8nZnhHI^f&;0paj)v(^NSOi=TAzy$uz7~s22r(!iOeWjIki&I$5kgcH9*bHCtwN}D
z;OoYA_JXKHBRV?#oe)eWddFJT=elta2&VqfY+$={ew_uDknP5GSj%&E<A5;L%)l5e
zA(%qAnEQDE^IrqRhhpY!FU0FcCloUTvHq|ZRkMO%8s3VgCbU&lO^@fmcf{sveB`SP
zL3d;AV4k3RbG`+S3k*3BO#eLutmDzEi;zI&*wqE26mkS0OgFZWqszg(Mb*}Gc+Nr>
z2qmFp%x`pY>`eM(YaH2_J1c+4s{dA@!mza7_6qIDw16`ApecfB0?|va_pdDc{9Q|h
zwWV^`@`G2Lk0zHmHIrQCTsZ$O!#*G?+d}4+(f32=&BDI-XD@2ImiTS>>&rVGQ=iLT
zd=~|_zx|C`p@A(mQJSuiZ_>+;_Bhi6*SK6Tf4TZhc4?59WdExf)RI?e6SoI9)k)l5
z6sTw|uBxy&vQ2CA!I`V$?Q%>Ha`s*$sS7uy1qEe8U8n8^Y@WA3J=v~LM{M3q>;AyO
z*lg{tQz2hhs3!-noN%DXQRP(S^h>EBIj!*;6`S9dhi4z&p(3Ia(XzU&D)nGs;q+Ek
zWJ*?;uAIM2%y0`Lz9m|7M9eh0$G>lad+O4M6O`>Qw3!?JA)>4!+~{aXy>w5pxZdr+
ziuoO<W`}Kdt<sKxYDK05FD()-xmg5BuN}-ZEEARAL7!5cxKVSU_vuO>c*I#eO3iQs
z>5=N~PVJBU&^^P#;SP3w@CU8R^;)+VJ^Rudd8e*?@LXt<+>*;$1>gJ)_ZFUdX%Gc}
z?;Y&ze3BCXvDPe1)OzX~aV_NwkE+r<0?;)QX&N5~mxM(0v{(#Ws!+PobI$I8i?wUO
z`p7Q~t-e;pt4803pFK&+l=LGdDxcpbp=39&w}7@K+*B{EW&aiRH8;A>g?m%GpX;T~
zG>+c!Wd6ORg9n&`Z8u*m2~-_?vrxopznWdA@laQB<jQBX{6vaqc}uS4Q|ZZ}Jx-m|
z4_CD+y5;X+&T71PamR?beYToX?}MBBF3N@t?$BjvIyt!6YzRM4;Bj0$FK1!PxlqH!
zSz@!*5BiRDi)03?^*J{^dQk<x4k&kw%sV?zMSaJ0ac9aEuN4dO<_PQFm)+Y-4NtnV
zEVeXYZHM@WdnVt!caID;yuYRkxjVej_>ebG{m8zA2WwxxVH{Rz5{tQ(C~|jl-pmpA
z(=&}K3e2`B2ShL{kA*Bq7Hv^YnDprlzo$EgCGXI;wAJBqaAe%N;uBV%m0sRsfj#Zf
zAm_y*X*U}3AxnDdvuFcZu_C(kya4fKyzr1|dt3Ij*e|)gX`#XqAIAO&N(zg!Ze9TQ
zq}`vNLwRNK5sSNP?oPRX_29j@f(Z4j?@_AFH?r;9olYGK$z_#2zw<0_wvBK5ohUJL
zFH7C>VTFYfBC)n*d8X?V6Sq^-r`)f~JzRr6GBnVLHd&p-3Y%no_ieUMqto^mAGw>S
zXbl-z$E=XDH1zaCnHMXWM(akLf}N9d#GQr$kJ4lx-6R<>$nz>INM&isMTTLdgfeUY
z{_uMFV{T0E(+{*CUKEkPwae7x4Ucg^<??#g1WykKV~Zm<kM7N6)L(6)7Wbq<%nX&<
zxutXOuSt`r-*w|-MoCRU{A06WlgHayb?&G6)7IBc9gwc9@QpHAow8Ih1JX7OgA@*D
zskT1Z`cS?$Mc*dFCgga(%CU2*7UnY&go<^o1yx+@qARmvGQ3yFn1n^_6&md<Ok<ZY
z6)UH;*Zk4Dz<ZMAqXjM7n>yHHWlFR)6Gn7;n$$|ty^re*?q8mkr)4sk#@b@EK`r^7
z-u@ybhFz=GMGqJE$L8|}cWj@AIF=^`C&B5fBK0=-@EQ$7_JtK)l#2bDUST^Jqmp`y
zVNKgG%h}ef<dEyf`BEPw5Be^CzFGP8mh#Nt7>6^O5!)J1z<HSlE4>0+&7R)hEjY{F
zFPSXf+Oi(ZU~IH>gCnhP)}`|7z|69(VG8**PMZVz-)Fz`&e-1J{(?Gi%c;lTxmi1;
zWr^G-9nDWqmnqK9zxuj`1$}Igj*UAhoKW&*A$P*c{Yh_(V^YiL<g?jDu65P$`iuV6
z5xw#cYcAhj=lSkUL6_0{sEs<-H6M50&5#b|bx1x|I&^JI%Ca*7=8eN_717uShrF~V
z6<W_MuRVT*QlEJ$>cL;y!I>IzE^?V_nY*)gynKG&;LqOK(;L<n=gZe8eK1_PV3%n^
z__8wx{-}z2Rb!;+X4Q~jx>9)Vf~ou?n|0|N%gbT~NjI>mPB?n`QGv{vX_eLSODi^*
zW-Zaqlnt6YQ2d~x?$LXtJbz`zvi7*(i9V^zZk46Uwae=js(u~rmUy*mg|lvC4CzFu
zP<Q%3HZwBSu&11-#b}iF-VyWgMLpDPC_<NQdd7>9*UMTzYv#SKciYuJ`^K#ai_pE2
z`DMYtc}tpCvy`hQhjv@GxNX3<efp<VWMxUR<A{@7)dq2?OJR~9<o2>%`yx-;D*NlU
z*t(MhqTP|^?yJ*dJa0uS({{TlTj=K^?C=y-g$X13gt3;TSMqLmF7dx=&NXfIj_(>t
z7u5C+&OK92Yuc1O{r$R2)1OY?RbTaVg}mM?M{l2Ri;T0TS6R%~iR@Z_VyaMQdOuk=
zGPV8W*DEQOo+TB>mirZl2W>z_G-o)kH@zEvajHa>XI9tC1nTGJ4`yDQ?=%*uf1Xm+
zx;votxlf9ZX~<4migxJZ!)NBlStc<OQ;Pd}i<>vSnlaPU(8VHUU)js0FFT$sTPTs2
zJh$pX2l`ATXMK{LQtzCc{Ocy?x<hWd9y~Hvzoje1Q@d;OeZ{kn^%O{J1sUDk#$Ng0
z+0`%f=6gDXN+#alxxg>wL{ODO@s!p-|LEd|O0c3khwGA+VvFi~62uP($>LpHXHv{k
z@xDfLzfJG%Bq_z36t%*?+_Ifkbc+?s3R_{>iLG&G_nO?%2r*5a_2#%z+U561{^fdc
zk0Xm(8~o!*VHzPlJ|o<xv2kD5STwImk@VeLUEL}+$<d^pU2)vd;O3GPpFVlT;^Teq
z*ViVtbJ|vyIX}F^yPmi__YzkxH|o$OD8<JkI!-S4^Q&cNW!swUX(w_!CzQ`%Tswxc
zqSqC?RXThAQsqg3nnL+%S66--d#Jf;>zA_|S!Az;AunS6Qm<8;H|S?AqEhU01l`$h
zR1XGh_G>npdPPOQrO>8w^{%InSQ7?q#oBsRZ(T9F6z?apdyh)1ddJtv{e$x=Pq#g|
zembe_mLdO$-|3^Nw>+Ci-ip~ua?GT686bL6n<^(sEs--0+WjW+&(vvBpO%{~dK{UJ
z-dgl_-Pvg}%Z>MnwN4Z3;!c%ey$*71qe@>0^E;-wN6baFc1B>{%oZx;;lPl(^_Tf8
z{I62nx+B6jJs7fl($@VfmtnZu_fS{U^Z1Xmq&m`H(EJ&unH^BT;IvX($r40p5w@lN
zy!Of?lQd^+opZ*}YK|Qx-?OYYT_E4ruP9Tb2aDDJp<eXI?)k+brj{P}TLRwj#XU-_
z6|2%0UKKHso$A6XOm9fq6qa-q;gnZIwv|pXOLw?eEM2NCIr(J1*q&1=;S0WeJUJBD
zc6i^%MaO4Y<@N4A*O9kniIde$<x6*1HJ%shN;6A0!zYuSP9E-R^6C40dB*`if0-v1
zw6N(J4Zh(2^}YAlhBv=e=9G=tjMbfM{cqYA-(?v!9?;&|y&$V5a-*grY%S%ynaLN<
zYA%=^v@ptOqK9_s>C<36Nc?FE{>5C}G<&jE<=d0~*}72fIq3;wYvE+v9NTv{kzBtU
zb53R+E1%fKF1kgT*dtcaot!Xm#AB~yWwo9HZM`Y4PIaX3ru)rOk;PXgL){hXQ@WSP
zJq`w!O7e_hcm5}z61lbo4X3=tJ(kF^*J^&M*HPT%QTye+>e0&^+TKr*mRVGow<OKS
zOJ6Z#&bMs_p4W})Xn(0(*|s%)YRJ{a@9JxKL1y{$tR$*(_5?SUT+3r$U6FB^xmu4J
za(Va3)ECU2E~{;m%saQtGV)bx4mDoBXvnE(mz~?$TcTQpPT|J_Wv8^roSHf#c?~u>
z!!@BSqqgDUpmOOl{W!NGeM18qu<)rmik14i^l}<hhV-Og51+R2UHDYWHqLFLYU(l-
zkV|b9IFpa4T<I_@rZ*;NeDQxD=@c$ZlI`Ns9O9NbtN1inidC8OcIH%{c74@qb$*{y
zUHy5xpmTQqGwtkl?H6nK`d!;4f&coi#nZM<Dfl#1$0~8=@=YZoYqgMu?^LN%5ekh#
z5rK}y%lA*Tjr%eo>$c^JyRv2_`(?kE1p|}Nvf$ebzfHPvVTk>A28h5va|FPKaAu_s
zLoikW2%A2jMi@&p#R$R=Zh^74F>1jCZh(kk+z_W6rWli93iuuv)3Sj`s(^<8fk`Af
zI8b2(`~nMOjw6@-pG`Kh1sKB{=Z;={Z-E2H3&Nwu*d$*F*bK(V2u`(;?acWpNcd+0
zG|F`tFp61>QXPzKvUps;c{d994rUx7<izDU3OGbZkUe0lJdC?Kavg-DC0ys=j<M6<
z`7ZQ>-YTpG1e>D>sf{yW1q-GbDF4iNAwc>ZIZmJ<Kz0eziMy>DqrIzu&kqZHj35@^
z0TaPsEY8b=?Z6SRdCnY2g9JXBkcK|^XhMJm{#H*$2se8t2NyQr(7+l6<|Gn=d4Uoc
zKagSk0Mm&Qp@f-4iGm*xDp4X1$Y|X!4rE>2grY|rh>oa4V-)-VlMuX)iuVVTK+GTr
zDz1cKA|xvA2g7TLI>HYo+N9#KzzEST6^{j`jQY_q2bePIhnv6@A|xsUucH!CQ+0^a
zXz#cZrV#_9;vK=XQ9s-SrsM7;8r~61$K6RZVhnVmO&T!<1`!L57z2Zdg+`1)hnPqj
zF$U(SB{2pjaRF$=7??yXG-3=)TuGu4V_=T<hc}H<h&q%g(TG_hrU#`F<3n&iltDyI
z#=AxJh*r?i5;0m74+7OAT0!v<q54FeC_V;MpNJC$V*rb7bX8%?4!b+X*R+GT0K1Fv
zTL@q2*b3(IIOBJj2j2tp$K~%CYU~k}4TOR}1ffD?@JA(4AcTy4sVE6T=-8J`r$Hzk
z`;sX@fEiIsr9<FLr;#BB{w32uP9xz72_iE<JHQ$fG6S?vgK?ptRB%LaA%mwZ2pyaQ
z!S!@d2ZTZb_6%?i1O?BJP~d|J8T5pb!8s7j9wjqyLC6#crGh#jWE#*>LA*e4J>~-h
zx2MBk5HL6g^&lopa6O0>1wx#IcCmgb6o?GQf(gn1V*oi16RdCWAHCp$*^|lGi~ymb
z;K;y*2I3)8KrFZb9o7~mm<<)Q0|aHzAUe=tg3!PbOd%#Hzy~^r1rzL?fuOk1K@4DS
z$;1zZM8!@h#Ls96S7Eb<pWx>7u@VEbWZ<Q(V~?@02Xh$I*g&hW*0D!=pj$fj+z-GA
zSU6ZE_7Dv_f{HN}{%mXvqsFp7h4TM5`&0f&_D6_(K_-$N8NcC4V>zA3WE3KO|B~VV
zFXwb3<5KbT_D?eW|87nPcQlT51gN4E0^JZi4Wpx&MO++|fEf~kj|lyb`JTWK1P6$J
zkni<~Re<6M_V2U51_{+C76XcRgz6J;j}raq6RQUWL;0V>3H&)aktcoz3JMKNde|4C
zz!(l-*#jgz1_}F8z?Ntf6ex@zKmd~SI1nIM;u{45ga82?2r&I95RgHV90vlB?S23O
zk%)010QTcRfMCgg6bL{p<3NDvLGs0f1~ME52skKUzGI+(`~(V^9s>bPu;e}t1n>_a
zKtX~Z0|H<_4g_E}#(@C54jBgm6eRyKAOIPbPC;=&0BF!DR9p~DPXp&bP%sB{0F0QR
zAf=B31OUfzfB@$Vkd84y07dvm071jdX=4EKZ{Y$a0o22P2w(x21WEuzahL&Hcu)fH
z4NBvffxiSIR?I4FNf5|_t&N|N1%JzfLkopG1}zvN8ABE(-y2XA@Xl!+*Ab&Y_<Jpk
z-~6B?UO#h^pIkAz0>})|04_tAGuhxx6W{qK2e9UTbhg%8=mOq;DcJMv-4!vC#bFD%
ze4Z}Gf)sSs5fXw8ngUZ05{j-O(N~g4D}kLc-|@dQ0sP0&8xRRd!I<kH;Cu0%gzC^n
z@a|3sne(BIy856QbFL7)|5D&k$g6}LFQJ#}PB*Weia*7=Q^0W&1=}%nhA2iwhz~@i
zP*4iwMCix}9R=G1yb9ut>##l0Z#psqBc9l2%nmR73ms_v7dtXSrBK1NVV^NyOvm^a
zzF^<?yB!HE_1|<968*QB5fT;K|NUYIbPTXZ`b|dz{OVU7m;)H>Re!MqIt1LFzvvJ^
zGQfWK7abX)QGd4sW20ib9qjXCyf8xhTOTkD+}gj{k?GXm#(`ZUaNCdD2?cEMj#PlZ
tCB|Rv;%gG;-+Zw2iS=v7_2+;qPi(K)0wKN@KuZ*aD!P2Ro{7Hbe*vT34B-F(
literal 0
HcmV?d00001
diff --git a/GPIO/ATSAME54/hal_gpio.h b/GPIO/ATSAME54/hal_gpio.h
new file mode 100644
index 0000000..390445f
--- /dev/null
+++ b/GPIO/ATSAME54/hal_gpio.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2017, Alex Taradov <alex@taradov.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _HAL_GPIO_H_
+#define _HAL_GPIO_H_
+
+/*- Definitions -------------------------------------------------------------*/
+#define HAL_GPIO_PORTA 0
+#define HAL_GPIO_PORTB 1
+#define HAL_GPIO_PORTC 2
+
+#define HAL_GPIO_PMUX_A 0
+#define HAL_GPIO_PMUX_B 1
+#define HAL_GPIO_PMUX_C 2
+#define HAL_GPIO_PMUX_D 3
+#define HAL_GPIO_PMUX_E 4
+#define HAL_GPIO_PMUX_F 5
+#define HAL_GPIO_PMUX_G 6
+#define HAL_GPIO_PMUX_H 7
+#define HAL_GPIO_PMUX_I 8
+
+#define HAL_GPIO_PIN(name, port, pin) \
+ static inline void HAL_GPIO_##name##_set(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \
+ (void)HAL_GPIO_##name##_set; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_clr(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].OUTCLR.reg = (1 << pin); \
+ (void)HAL_GPIO_##name##_clr; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_toggle(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].OUTTGL.reg = (1 << pin); \
+ (void)HAL_GPIO_##name##_toggle; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_write(int value) \
+ { \
+ if (value) \
+ PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \
+ else \
+ PORT->Group[HAL_GPIO_PORT##port].OUTCLR.reg = (1 << pin); \
+ (void)HAL_GPIO_##name##_write; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_in(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].DIRCLR.reg = (1 << pin); \
+ PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_INEN; \
+ PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PULLEN; \
+ (void)HAL_GPIO_##name##_in; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_out(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].DIRSET.reg = (1 << pin); \
+ PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_INEN; \
+ (void)HAL_GPIO_##name##_out; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_pullup(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \
+ PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PULLEN; \
+ (void)HAL_GPIO_##name##_pullup; \
+ } \
+ \
+ static inline int HAL_GPIO_##name##_read(void) \
+ { \
+ return (PORT->Group[HAL_GPIO_PORT##port].IN.reg & (1 << pin)) != 0; \
+ (void)HAL_GPIO_##name##_read; \
+ } \
+ \
+ static inline int HAL_GPIO_##name##_state(void) \
+ { \
+ return (PORT->Group[HAL_GPIO_PORT##port].DIR.reg & (1 << pin)) != 0; \
+ (void)HAL_GPIO_##name##_state; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_pmuxen(int mux) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PMUXEN; \
+ if (pin & 1) \
+ PORT->Group[HAL_GPIO_PORT##port].PMUX[pin>>1].bit.PMUXO = mux; \
+ else \
+ PORT->Group[HAL_GPIO_PORT##port].PMUX[pin>>1].bit.PMUXE = mux; \
+ (void)HAL_GPIO_##name##_pmuxen; \
+ } \
+ \
+ static inline void HAL_GPIO_##name##_pmuxdis(void) \
+ { \
+ PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PMUXEN; \
+ (void)HAL_GPIO_##name##_pmuxdis; \
+ } \
+
+#endif // _HAL_GPIO_H_
+
diff --git a/GPIO/ATSAME54/include/component/ac.h b/GPIO/ATSAME54/include/component/ac.h
new file mode 100644
index 0000000..56bcf99
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/ac.h
@@ -0,0 +1,598 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_AC_COMPONENT_
+#define _SAME54_AC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAME54_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2501
+#define REV_AC 0x100
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
+ uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
+#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
+#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
+#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
+#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
+#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
+#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
+#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
+#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN:1; /*!< bit: 4 Window x */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
+#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
+#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
+#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
+
+#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
+#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
+#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
+ uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t OUT:2; /*!< bit: 28..29 Output */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
+#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
+#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
+#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
+#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
+#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
+#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
+#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
+#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
+#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
+#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
+#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
+ uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
+ uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :3; /*!< bit: 0.. 2 Reserved */
+ uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
+#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
+#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
+#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
+#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
+#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
+#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
+#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
+#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
+#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
+
+/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
+ uint16_t :14; /*!< bit: 2..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
+#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
+
+#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
+#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
+#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
+#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
+ __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
+ RoReg8 Reserved1[0x1];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
+ RoReg8 Reserved2[0x2];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved3[0x8];
+ __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
+ __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_AC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/adc.h b/GPIO/ATSAME54/include/component/adc.h
new file mode 100644
index 0000000..969fa01
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/adc.h
@@ -0,0 +1,871 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ADC_COMPONENT_
+#define _SAME54_ADC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAME54_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2500
+#define REV_ADC 0x100
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t :1; /*!< bit: 2 Reserved */
+ uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
+ uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :4; /*!< bit: 11..14 Reserved */
+ uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
+#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
+#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
+#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
+#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
+#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
+#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
+#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */
+#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
+#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
+#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
+#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
+#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
+#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
+#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
+#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
+#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
+#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
+#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)
+#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
+ uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
+ uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
+ uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
+#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
+#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
+#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
+#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
+#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
+#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint16_t :2; /*!< bit: 5.. 6 Reserved */
+ uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */
+ uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint16_t :2; /*!< bit: 13..14 Reserved */
+ uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
+#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
+#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */
+#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
+#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
+#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */
+ uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
+ uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
+#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
+#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
+#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
+#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */
+#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
+#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */
+#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */
+#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */
+#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
+#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
+#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */
+#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
+#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
+#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
+#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */
+#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */
+#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */
+#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
+#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
+#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
+#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
+#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
+#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
+#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
+#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
+#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
+#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
+#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
+#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
+#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
+#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
+#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
+#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
+#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
+#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
+ __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
+ __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
+#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
+#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
+#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */
+#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
+#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */
+#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)
+#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
+#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
+ uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */
+ uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */
+ uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */
+ uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */
+ uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */
+ uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */
+ uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */
+ uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */
+ uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
+#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
+#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
+#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
+#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
+#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
+#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
+#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
+#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
+#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
+#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
+#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
+#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
+#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
+#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
+#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
+#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
+#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
+#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
+#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
+#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
+#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
+#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
+#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
+#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
+#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
+
+/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_DSEQDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
+#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
+
+#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
+#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
+#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
+#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
+
+/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
+ uint32_t CTRLB:1; /*!< bit: 1 Control B */
+ uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
+ uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
+ uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
+ uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
+ uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
+ uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
+ uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
+ uint32_t :22; /*!< bit: 9..30 Reserved */
+ uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_DSEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
+#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
+
+#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */
+#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
+#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */
+#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
+#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */
+#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
+#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */
+#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
+#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
+#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
+#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
+#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
+#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
+#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
+#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */
+#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
+#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */
+#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
+#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
+#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
+#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
+
+/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
+ uint32_t CTRLB:1; /*!< bit: 1 Control B */
+ uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
+ uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
+ uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
+ uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
+ uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
+ uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
+ uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
+ uint32_t :22; /*!< bit: 9..30 Reserved */
+ uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_DSEQSTAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
+#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
+
+#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */
+#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
+#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */
+#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
+#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */
+#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
+#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */
+#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
+#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
+#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
+#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
+#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
+#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
+#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
+#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */
+#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
+#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */
+#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
+#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
+#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
+#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */
+#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
+
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */
+#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */
+
+#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */
+#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
+#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
+#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
+#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
+#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
+#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
+#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
+#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
+#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
+#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
+#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
+#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
+ RoReg8 Reserved1[0x1];
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */
+ RoReg8 Reserved2[0x17];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */
+ __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */
+ __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
+ __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
+ __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */
+ RoReg8 Reserved3[0x2];
+ __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */
+ RoReg8 Reserved4[0x2];
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_ADC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/aes.h b/GPIO/ATSAME54/include/component/aes.h
new file mode 100644
index 0000000..e878941
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/aes.h
@@ -0,0 +1,375 @@
+/**
+ * \file
+ *
+ * \brief Component description for AES
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_AES_COMPONENT_
+#define _SAME54_AES_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AES */
+/* ========================================================================== */
+/** \addtogroup SAME54_AES Advanced Encryption Standard */
+/*@{*/
+
+#define AES_U2238
+#define REV_AES 0x220
+
+/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
+ uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
+ uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
+ uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
+ uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
+ uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
+ uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
+ uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AES_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
+#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
+
+#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
+#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
+#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
+#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
+#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
+#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
+#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
+#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
+#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
+#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
+#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
+#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
+#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
+#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
+#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
+#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
+#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
+#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
+#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
+#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
+#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
+#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
+#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
+#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
+#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
+#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
+#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
+#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
+#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
+#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
+#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
+#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
+#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
+#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
+#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
+#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
+
+/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
+ uint8_t NEWMSG:1; /*!< bit: 1 New message */
+ uint8_t EOM:1; /*!< bit: 2 End of message */
+ uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
+#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
+
+#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
+#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
+#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
+#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
+#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
+#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
+#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
+#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
+#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
+
+/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
+ uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
+#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
+#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
+#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
+#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
+#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
+
+/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
+ uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
+#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
+
+#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
+#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
+#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
+#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
+#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
+
+/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
+ __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
+#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
+
+#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
+#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
+#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
+#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
+#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
+
+/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_DATABUFPTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
+#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
+
+#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
+#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
+#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
+#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
+
+/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AES_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
+#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
+
+#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
+#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
+#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
+
+/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_KEYWORD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
+#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
+#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
+
+/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_INDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
+#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
+#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
+
+/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_INTVECTV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
+#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
+#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
+
+/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_HASHKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
+#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
+#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
+
+/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_GHASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
+#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
+#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
+
+/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_CIPLEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
+#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
+#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
+
+/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} AES_RANDSEED_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
+#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
+#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
+
+/** \brief AES hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
+ __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
+ __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
+ __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
+ __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
+ __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
+ RoReg8 Reserved1[0x2];
+ __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
+ RoReg8 Reserved2[0xC];
+ __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
+ __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
+ RoReg8 Reserved3[0x10];
+ __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
+ __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
+ RoReg8 Reserved4[0x4];
+ __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
+ __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
+} Aes;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_AES_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/can.h b/GPIO/ATSAME54/include/component/can.h
new file mode 100644
index 0000000..5006d57
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/can.h
@@ -0,0 +1,3193 @@
+/**
+ * \file
+ *
+ * \brief Component description for CAN
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CAN_COMPONENT_
+#define _SAME54_CAN_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR CAN */
+/* ========================================================================== */
+/** \addtogroup SAME54_CAN Control Area Network */
+/*@{*/
+
+#define CAN_U2003
+#define REV_CAN 0x321
+
+/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :20; /*!< bit: 0..19 Reserved */
+ uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */
+ uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */
+ uint32_t REL:4; /*!< bit: 28..31 Core Release */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_CREL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */
+#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */
+
+#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */
+#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos)
+#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
+#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */
+#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos)
+#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
+#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */
+#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos)
+#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
+#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */
+
+/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ENDN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */
+#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */
+
+#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */
+#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)
+#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
+#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */
+
+/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_MRCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
+#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
+
+#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */
+#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
+#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
+#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
+#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */
+#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */
+#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos)
+#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */
+
+/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */
+ uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */
+ uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */
+ uint32_t :2; /*!< bit: 21..22 Reserved */
+ uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_DBTP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
+#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
+
+#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
+#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos)
+#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
+#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */
+#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos)
+#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
+#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */
+#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos)
+#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
+#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
+#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos)
+#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
+#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
+#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos)
+#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */
+
+/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */
+ uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */
+ uint32_t RX:1; /*!< bit: 7 Receive Pin */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TEST_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */
+#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */
+
+#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */
+#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos)
+#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */
+#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
+#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */
+#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */
+#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
+#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
+#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)
+#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */
+#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos)
+#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */
+
+/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */
+ uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RWD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */
+#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */
+
+#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */
+#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos)
+#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
+#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */
+#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos)
+#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
+#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */
+
+/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INIT:1; /*!< bit: 0 Initialization */
+ uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */
+ uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */
+ uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */
+ uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */
+ uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */
+ uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */
+ uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */
+ uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */
+ uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */
+ uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */
+ uint32_t TXP:1; /*!< bit: 14 Transmit Pause */
+ uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_CCCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */
+#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */
+
+#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */
+#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos)
+#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */
+#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos)
+#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
+#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos)
+#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
+#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos)
+#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */
+#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos)
+#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */
+#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos)
+#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
+#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos)
+#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */
+#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos)
+#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */
+#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos)
+#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
+#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos)
+#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
+#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos)
+#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
+#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos)
+#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */
+#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos)
+#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */
+#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos)
+#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */
+
+/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */
+ uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */
+ uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_NBTP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
+#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
+
+#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
+#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos)
+#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
+#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
+#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos)
+#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
+#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
+#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos)
+#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
+#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
+#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos)
+#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
+#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */
+
+/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */
+ uint32_t :14; /*!< bit: 2..15 Reserved */
+ uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TSCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
+#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
+
+#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */
+#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
+#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
+#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
+#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */
+#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)
+#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
+#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos)
+#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
+#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */
+
+/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TSCV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
+#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
+
+#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */
+#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos)
+#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
+#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */
+
+/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */
+ uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TOCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
+#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
+
+#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */
+#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos)
+#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */
+#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
+#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */
+#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
+#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
+#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
+#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)
+#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */
+#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos)
+#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
+#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */
+
+/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TOCV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */
+#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
+
+#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */
+#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos)
+#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
+#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */
+
+/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */
+ uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */
+ uint32_t RP:1; /*!< bit: 15 Receive Error Passive */
+ uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ECR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */
+#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */
+
+#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */
+#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos)
+#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
+#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */
+#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos)
+#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
+#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */
+#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos)
+#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */
+#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos)
+#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
+#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */
+
+/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */
+ uint32_t ACT:2; /*!< bit: 3.. 4 Activity */
+ uint32_t EP:1; /*!< bit: 5 Error Passive */
+ uint32_t EW:1; /*!< bit: 6 Warning Status */
+ uint32_t BO:1; /*!< bit: 7 Bus_Off Status */
+ uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */
+ uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */
+ uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */
+ uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */
+ uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_PSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */
+#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */
+
+#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */
+#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
+#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
+#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
+#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
+#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
+#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
+#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
+#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
+#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
+#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)
+#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */
+#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
+#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
+#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
+#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */
+#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */
+#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)
+#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */
+#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos)
+#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */
+#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos)
+#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */
+#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos)
+#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */
+#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
+#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
+#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
+#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
+#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
+#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
+#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
+#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
+#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
+#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)
+#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
+#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos)
+#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
+#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos)
+#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */
+#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos)
+#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */
+#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos)
+#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
+#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos)
+#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
+#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */
+
+/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */
+ uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TDCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
+#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
+
+#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
+#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos)
+#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
+#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
+#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos)
+#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
+#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */
+
+/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */
+ uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */
+ uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */
+ uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */
+ uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */
+ uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */
+ uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */
+ uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */
+ uint32_t HPM:1; /*!< bit: 8 High Priority Message */
+ uint32_t TC:1; /*!< bit: 9 Timestamp Completed */
+ uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */
+ uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */
+ uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */
+ uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */
+ uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */
+ uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */
+ uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */
+ uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */
+ uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */
+ uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */
+ uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */
+ uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */
+ uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */
+ uint32_t EP:1; /*!< bit: 23 Error Passive */
+ uint32_t EW:1; /*!< bit: 24 Warning Status */
+ uint32_t BO:1; /*!< bit: 25 Bus_Off Status */
+ uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */
+ uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */
+ uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */
+ uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_IR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */
+#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */
+
+#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */
+#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos)
+#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
+#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos)
+#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */
+#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos)
+#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
+#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos)
+#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */
+#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos)
+#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
+#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos)
+#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
+#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos)
+#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
+#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos)
+#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */
+#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos)
+#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */
+#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos)
+#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */
+#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos)
+#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */
+#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos)
+#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */
+#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos)
+#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
+#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos)
+#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */
+#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos)
+#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
+#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos)
+#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */
+#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos)
+#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */
+#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos)
+#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */
+#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos)
+#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
+#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos)
+#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */
+#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos)
+#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */
+#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos)
+#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */
+#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos)
+#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */
+#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos)
+#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */
+#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos)
+#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */
+#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos)
+#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */
+#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos)
+#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
+#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos)
+#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */
+#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos)
+#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */
+#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos)
+#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */
+
+/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */
+ uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */
+ uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */
+ uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */
+ uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */
+ uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */
+ uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */
+ uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */
+ uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */
+ uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */
+ uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */
+ uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */
+ uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */
+ uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */
+ uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */
+ uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */
+ uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */
+ uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */
+ uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */
+ uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */
+ uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */
+ uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */
+ uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */
+ uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */
+ uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */
+ uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */
+ uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */
+ uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */
+ uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */
+ uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_IE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */
+#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */
+
+#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
+#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos)
+#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
+#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos)
+#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
+#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos)
+#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
+#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos)
+#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
+#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos)
+#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
+#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos)
+#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
+#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos)
+#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
+#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos)
+#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
+#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos)
+#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
+#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos)
+#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
+#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos)
+#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
+#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos)
+#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
+#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos)
+#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
+#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos)
+#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
+#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos)
+#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
+#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos)
+#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
+#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos)
+#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
+#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos)
+#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
+#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos)
+#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
+#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos)
+#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
+#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos)
+#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
+#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos)
+#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
+#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos)
+#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */
+#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos)
+#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */
+#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos)
+#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
+#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos)
+#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
+#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos)
+#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
+#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos)
+#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
+#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos)
+#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */
+#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos)
+#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */
+
+/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */
+ uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */
+ uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */
+ uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */
+ uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */
+ uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */
+ uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */
+ uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */
+ uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */
+ uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */
+ uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */
+ uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */
+ uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */
+ uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */
+ uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */
+ uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */
+ uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */
+ uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */
+ uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */
+ uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */
+ uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */
+ uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */
+ uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */
+ uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */
+ uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */
+ uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */
+ uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */
+ uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */
+ uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */
+ uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ILS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */
+#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
+
+#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
+#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos)
+#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
+#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos)
+#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
+#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos)
+#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
+#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos)
+#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
+#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos)
+#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
+#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos)
+#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
+#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos)
+#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
+#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos)
+#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
+#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos)
+#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
+#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos)
+#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
+#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos)
+#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
+#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos)
+#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
+#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos)
+#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
+#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos)
+#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
+#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos)
+#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
+#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos)
+#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
+#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos)
+#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
+#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos)
+#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
+#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos)
+#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
+#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos)
+#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
+#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos)
+#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
+#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos)
+#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
+#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos)
+#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */
+#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos)
+#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */
+#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos)
+#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
+#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos)
+#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
+#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos)
+#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
+#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos)
+#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
+#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos)
+#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */
+#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos)
+#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */
+
+/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */
+ uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_ILE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */
+#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
+
+#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
+#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos)
+#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
+#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos)
+#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */
+
+/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */
+ uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */
+ uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */
+ uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_GFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */
+#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
+
+#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */
+#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos)
+#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */
+#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos)
+#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
+#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
+#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
+#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
+#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
+#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)
+#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
+#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
+#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
+#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
+#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
+#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)
+#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */
+
+/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */
+ uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_SIDFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
+#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
+
+#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
+#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos)
+#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
+#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */
+#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos)
+#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
+#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */
+
+/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */
+ uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
+#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
+
+#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
+#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos)
+#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
+#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */
+#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos)
+#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
+#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */
+
+/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
+#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
+
+#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */
+#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos)
+#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
+#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */
+
+/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */
+ uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */
+ uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */
+ uint32_t FLST:1; /*!< bit: 15 Filter List */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_HPMS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */
+#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */
+
+#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */
+#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos)
+#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos))
+#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */
+#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos))
+#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */
+#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */
+#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */
+#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */
+#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos)
+#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */
+#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos)
+#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos))
+#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */
+#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos)
+#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */
+
+/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ND0:1; /*!< bit: 0 New Data 0 */
+ uint32_t ND1:1; /*!< bit: 1 New Data 1 */
+ uint32_t ND2:1; /*!< bit: 2 New Data 2 */
+ uint32_t ND3:1; /*!< bit: 3 New Data 3 */
+ uint32_t ND4:1; /*!< bit: 4 New Data 4 */
+ uint32_t ND5:1; /*!< bit: 5 New Data 5 */
+ uint32_t ND6:1; /*!< bit: 6 New Data 6 */
+ uint32_t ND7:1; /*!< bit: 7 New Data 7 */
+ uint32_t ND8:1; /*!< bit: 8 New Data 8 */
+ uint32_t ND9:1; /*!< bit: 9 New Data 9 */
+ uint32_t ND10:1; /*!< bit: 10 New Data 10 */
+ uint32_t ND11:1; /*!< bit: 11 New Data 11 */
+ uint32_t ND12:1; /*!< bit: 12 New Data 12 */
+ uint32_t ND13:1; /*!< bit: 13 New Data 13 */
+ uint32_t ND14:1; /*!< bit: 14 New Data 14 */
+ uint32_t ND15:1; /*!< bit: 15 New Data 15 */
+ uint32_t ND16:1; /*!< bit: 16 New Data 16 */
+ uint32_t ND17:1; /*!< bit: 17 New Data 17 */
+ uint32_t ND18:1; /*!< bit: 18 New Data 18 */
+ uint32_t ND19:1; /*!< bit: 19 New Data 19 */
+ uint32_t ND20:1; /*!< bit: 20 New Data 20 */
+ uint32_t ND21:1; /*!< bit: 21 New Data 21 */
+ uint32_t ND22:1; /*!< bit: 22 New Data 22 */
+ uint32_t ND23:1; /*!< bit: 23 New Data 23 */
+ uint32_t ND24:1; /*!< bit: 24 New Data 24 */
+ uint32_t ND25:1; /*!< bit: 25 New Data 25 */
+ uint32_t ND26:1; /*!< bit: 26 New Data 26 */
+ uint32_t ND27:1; /*!< bit: 27 New Data 27 */
+ uint32_t ND28:1; /*!< bit: 28 New Data 28 */
+ uint32_t ND29:1; /*!< bit: 29 New Data 29 */
+ uint32_t ND30:1; /*!< bit: 30 New Data 30 */
+ uint32_t ND31:1; /*!< bit: 31 New Data 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_NDAT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */
+#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */
+
+#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */
+#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos)
+#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */
+#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos)
+#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */
+#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos)
+#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */
+#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos)
+#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */
+#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos)
+#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */
+#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos)
+#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */
+#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos)
+#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */
+#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos)
+#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */
+#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos)
+#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */
+#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos)
+#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */
+#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos)
+#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */
+#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos)
+#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */
+#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos)
+#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */
+#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos)
+#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */
+#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos)
+#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */
+#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos)
+#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */
+#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos)
+#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */
+#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos)
+#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */
+#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos)
+#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */
+#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos)
+#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */
+#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos)
+#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */
+#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos)
+#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */
+#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos)
+#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */
+#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos)
+#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */
+#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos)
+#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */
+#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos)
+#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */
+#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos)
+#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */
+#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos)
+#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */
+#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos)
+#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */
+#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos)
+#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */
+#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos)
+#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */
+#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos)
+#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */
+
+/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ND32:1; /*!< bit: 0 New Data 32 */
+ uint32_t ND33:1; /*!< bit: 1 New Data 33 */
+ uint32_t ND34:1; /*!< bit: 2 New Data 34 */
+ uint32_t ND35:1; /*!< bit: 3 New Data 35 */
+ uint32_t ND36:1; /*!< bit: 4 New Data 36 */
+ uint32_t ND37:1; /*!< bit: 5 New Data 37 */
+ uint32_t ND38:1; /*!< bit: 6 New Data 38 */
+ uint32_t ND39:1; /*!< bit: 7 New Data 39 */
+ uint32_t ND40:1; /*!< bit: 8 New Data 40 */
+ uint32_t ND41:1; /*!< bit: 9 New Data 41 */
+ uint32_t ND42:1; /*!< bit: 10 New Data 42 */
+ uint32_t ND43:1; /*!< bit: 11 New Data 43 */
+ uint32_t ND44:1; /*!< bit: 12 New Data 44 */
+ uint32_t ND45:1; /*!< bit: 13 New Data 45 */
+ uint32_t ND46:1; /*!< bit: 14 New Data 46 */
+ uint32_t ND47:1; /*!< bit: 15 New Data 47 */
+ uint32_t ND48:1; /*!< bit: 16 New Data 48 */
+ uint32_t ND49:1; /*!< bit: 17 New Data 49 */
+ uint32_t ND50:1; /*!< bit: 18 New Data 50 */
+ uint32_t ND51:1; /*!< bit: 19 New Data 51 */
+ uint32_t ND52:1; /*!< bit: 20 New Data 52 */
+ uint32_t ND53:1; /*!< bit: 21 New Data 53 */
+ uint32_t ND54:1; /*!< bit: 22 New Data 54 */
+ uint32_t ND55:1; /*!< bit: 23 New Data 55 */
+ uint32_t ND56:1; /*!< bit: 24 New Data 56 */
+ uint32_t ND57:1; /*!< bit: 25 New Data 57 */
+ uint32_t ND58:1; /*!< bit: 26 New Data 58 */
+ uint32_t ND59:1; /*!< bit: 27 New Data 59 */
+ uint32_t ND60:1; /*!< bit: 28 New Data 60 */
+ uint32_t ND61:1; /*!< bit: 29 New Data 61 */
+ uint32_t ND62:1; /*!< bit: 30 New Data 62 */
+ uint32_t ND63:1; /*!< bit: 31 New Data 63 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_NDAT2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */
+#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */
+
+#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */
+#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos)
+#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */
+#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos)
+#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */
+#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos)
+#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */
+#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos)
+#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */
+#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos)
+#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */
+#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos)
+#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */
+#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos)
+#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */
+#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos)
+#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */
+#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos)
+#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */
+#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos)
+#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */
+#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos)
+#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */
+#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos)
+#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */
+#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos)
+#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */
+#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos)
+#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */
+#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos)
+#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */
+#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos)
+#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */
+#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos)
+#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */
+#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos)
+#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */
+#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos)
+#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */
+#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos)
+#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */
+#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos)
+#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */
+#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos)
+#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */
+#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos)
+#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */
+#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos)
+#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */
+#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos)
+#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */
+#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos)
+#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */
+#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos)
+#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */
+#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos)
+#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */
+#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos)
+#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */
+#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos)
+#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */
+#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos)
+#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */
+#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos)
+#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */
+
+/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */
+ uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */
+ uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0C_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */
+#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */
+
+#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */
+#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos)
+#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos))
+#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */
+#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos)
+#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos))
+#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */
+#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos)
+#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos))
+#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */
+#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos)
+#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */
+
+/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */
+ uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0S_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */
+#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */
+
+#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */
+#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos)
+#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos))
+#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */
+#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos)
+#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos))
+#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */
+#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos)
+#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos))
+#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */
+#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos)
+#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */
+#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos)
+#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */
+
+/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0A_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */
+#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */
+
+#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */
+#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos)
+#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos))
+#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */
+
+/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */
+#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */
+
+#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */
+#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos)
+#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos))
+#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */
+
+/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */
+ uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */
+ uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1C_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */
+#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */
+
+#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */
+#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos)
+#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos))
+#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */
+#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos)
+#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos))
+#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */
+#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos)
+#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos))
+#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */
+#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos)
+#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */
+
+/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */
+ uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */
+ uint32_t :4; /*!< bit: 26..29 Reserved */
+ uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1S_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */
+#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */
+
+#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */
+#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos)
+#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos))
+#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */
+#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos)
+#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos))
+#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */
+#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos)
+#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos))
+#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */
+#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos)
+#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */
+#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos)
+#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */
+#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos))
+#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */
+#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */
+#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */
+#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */
+#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos)
+#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */
+
+/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1A_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */
+#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */
+
+#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */
+#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos)
+#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos))
+#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */
+
+/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */
+#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */
+
+#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */
+#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos))
+#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
+#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
+#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
+#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
+#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
+#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
+#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
+#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos)
+#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */
+#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos))
+#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
+#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
+#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
+#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
+#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
+#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
+#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
+#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos)
+#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */
+#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos))
+#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */
+#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */
+#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */
+#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */
+#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */
+#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */
+#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */
+#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */
+#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos)
+#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */
+
+/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */
+ uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */
+ uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */
+#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */
+
+#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */
+#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos)
+#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos))
+#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */
+#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos)
+#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos))
+#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */
+#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos)
+#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos))
+#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */
+#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos)
+#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */
+
+/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */
+ uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXFQS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */
+#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */
+
+#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */
+#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos)
+#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos))
+#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */
+#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos)
+#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos))
+#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */
+#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos)
+#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos))
+#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */
+#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos)
+#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */
+
+/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */
+#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */
+
+#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */
+#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos))
+#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */
+#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */
+#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */
+#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */
+#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */
+#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */
+#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */
+#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */
+#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos)
+#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */
+
+/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */
+ uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */
+ uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */
+ uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */
+ uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */
+ uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */
+ uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */
+ uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */
+ uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */
+ uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */
+ uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */
+ uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */
+ uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */
+ uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */
+ uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */
+ uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */
+ uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */
+ uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */
+ uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */
+ uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */
+ uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */
+ uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */
+ uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */
+ uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */
+ uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */
+ uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */
+ uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */
+ uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */
+ uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */
+ uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */
+ uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */
+ uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBRP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */
+#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */
+
+#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */
+#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos)
+#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */
+#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos)
+#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */
+#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos)
+#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */
+#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos)
+#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */
+#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos)
+#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */
+#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos)
+#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */
+#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos)
+#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */
+#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos)
+#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */
+#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos)
+#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */
+#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos)
+#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */
+#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos)
+#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */
+#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos)
+#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */
+#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos)
+#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */
+#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos)
+#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */
+#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos)
+#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */
+#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos)
+#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */
+#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos)
+#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */
+#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos)
+#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */
+#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos)
+#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */
+#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos)
+#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */
+#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos)
+#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */
+#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos)
+#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */
+#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos)
+#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */
+#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos)
+#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */
+#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos)
+#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */
+#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos)
+#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */
+#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos)
+#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */
+#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos)
+#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */
+#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos)
+#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */
+#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos)
+#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */
+#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos)
+#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */
+#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos)
+#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */
+
+/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AR0:1; /*!< bit: 0 Add Request 0 */
+ uint32_t AR1:1; /*!< bit: 1 Add Request 1 */
+ uint32_t AR2:1; /*!< bit: 2 Add Request 2 */
+ uint32_t AR3:1; /*!< bit: 3 Add Request 3 */
+ uint32_t AR4:1; /*!< bit: 4 Add Request 4 */
+ uint32_t AR5:1; /*!< bit: 5 Add Request 5 */
+ uint32_t AR6:1; /*!< bit: 6 Add Request 6 */
+ uint32_t AR7:1; /*!< bit: 7 Add Request 7 */
+ uint32_t AR8:1; /*!< bit: 8 Add Request 8 */
+ uint32_t AR9:1; /*!< bit: 9 Add Request 9 */
+ uint32_t AR10:1; /*!< bit: 10 Add Request 10 */
+ uint32_t AR11:1; /*!< bit: 11 Add Request 11 */
+ uint32_t AR12:1; /*!< bit: 12 Add Request 12 */
+ uint32_t AR13:1; /*!< bit: 13 Add Request 13 */
+ uint32_t AR14:1; /*!< bit: 14 Add Request 14 */
+ uint32_t AR15:1; /*!< bit: 15 Add Request 15 */
+ uint32_t AR16:1; /*!< bit: 16 Add Request 16 */
+ uint32_t AR17:1; /*!< bit: 17 Add Request 17 */
+ uint32_t AR18:1; /*!< bit: 18 Add Request 18 */
+ uint32_t AR19:1; /*!< bit: 19 Add Request 19 */
+ uint32_t AR20:1; /*!< bit: 20 Add Request 20 */
+ uint32_t AR21:1; /*!< bit: 21 Add Request 21 */
+ uint32_t AR22:1; /*!< bit: 22 Add Request 22 */
+ uint32_t AR23:1; /*!< bit: 23 Add Request 23 */
+ uint32_t AR24:1; /*!< bit: 24 Add Request 24 */
+ uint32_t AR25:1; /*!< bit: 25 Add Request 25 */
+ uint32_t AR26:1; /*!< bit: 26 Add Request 26 */
+ uint32_t AR27:1; /*!< bit: 27 Add Request 27 */
+ uint32_t AR28:1; /*!< bit: 28 Add Request 28 */
+ uint32_t AR29:1; /*!< bit: 29 Add Request 29 */
+ uint32_t AR30:1; /*!< bit: 30 Add Request 30 */
+ uint32_t AR31:1; /*!< bit: 31 Add Request 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */
+#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */
+
+#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */
+#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos)
+#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */
+#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos)
+#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */
+#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos)
+#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */
+#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos)
+#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */
+#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos)
+#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */
+#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos)
+#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */
+#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos)
+#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */
+#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos)
+#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */
+#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos)
+#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */
+#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos)
+#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */
+#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos)
+#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */
+#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos)
+#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */
+#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos)
+#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */
+#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos)
+#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */
+#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos)
+#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */
+#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos)
+#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */
+#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos)
+#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */
+#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos)
+#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */
+#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos)
+#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */
+#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos)
+#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */
+#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos)
+#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */
+#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos)
+#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */
+#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos)
+#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */
+#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos)
+#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */
+#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos)
+#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */
+#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos)
+#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */
+#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos)
+#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */
+#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos)
+#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */
+#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos)
+#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */
+#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos)
+#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */
+#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos)
+#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */
+#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos)
+#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */
+
+/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */
+ uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */
+ uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */
+ uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */
+ uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */
+ uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */
+ uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */
+ uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */
+ uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */
+ uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */
+ uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */
+ uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */
+ uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */
+ uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */
+ uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */
+ uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */
+ uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */
+ uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */
+ uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */
+ uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */
+ uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */
+ uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */
+ uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */
+ uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */
+ uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */
+ uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */
+ uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */
+ uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */
+ uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */
+ uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */
+ uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */
+ uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */
+#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */
+
+#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */
+#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos)
+#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */
+#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos)
+#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */
+#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos)
+#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */
+#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos)
+#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */
+#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos)
+#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */
+#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos)
+#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */
+#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos)
+#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */
+#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos)
+#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */
+#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos)
+#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */
+#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos)
+#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */
+#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos)
+#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */
+#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos)
+#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */
+#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos)
+#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */
+#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos)
+#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */
+#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos)
+#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */
+#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos)
+#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */
+#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos)
+#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */
+#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos)
+#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */
+#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos)
+#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */
+#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos)
+#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */
+#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos)
+#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */
+#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos)
+#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */
+#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos)
+#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */
+#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos)
+#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */
+#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos)
+#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */
+#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos)
+#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */
+#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos)
+#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */
+#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos)
+#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */
+#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos)
+#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */
+#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos)
+#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */
+#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos)
+#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */
+#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos)
+#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */
+
+/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */
+ uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */
+ uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */
+ uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */
+ uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */
+ uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */
+ uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */
+ uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */
+ uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */
+ uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */
+ uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */
+ uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */
+ uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */
+ uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */
+ uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */
+ uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */
+ uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */
+ uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */
+ uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */
+ uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */
+ uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */
+ uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */
+ uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */
+ uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */
+ uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */
+ uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */
+ uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */
+ uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */
+ uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */
+ uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */
+ uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */
+ uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBTO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */
+#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */
+
+#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */
+#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos)
+#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */
+#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos)
+#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */
+#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos)
+#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */
+#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos)
+#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */
+#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos)
+#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */
+#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos)
+#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */
+#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos)
+#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */
+#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos)
+#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */
+#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos)
+#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */
+#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos)
+#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */
+#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos)
+#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */
+#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos)
+#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */
+#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos)
+#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */
+#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos)
+#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */
+#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos)
+#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */
+#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos)
+#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */
+#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos)
+#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */
+#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos)
+#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */
+#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos)
+#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */
+#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos)
+#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */
+#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos)
+#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */
+#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos)
+#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */
+#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos)
+#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */
+#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos)
+#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */
+#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos)
+#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */
+#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos)
+#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */
+#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos)
+#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */
+#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos)
+#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */
+#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos)
+#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */
+#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos)
+#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */
+#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos)
+#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */
+#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos)
+#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */
+
+/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */
+ uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */
+ uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */
+ uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */
+ uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */
+ uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */
+ uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */
+ uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */
+ uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */
+ uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */
+ uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */
+ uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */
+ uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */
+ uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */
+ uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */
+ uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */
+ uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */
+ uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */
+ uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */
+ uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */
+ uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */
+ uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */
+ uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */
+ uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */
+ uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */
+ uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */
+ uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */
+ uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */
+ uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */
+ uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */
+ uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */
+ uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */
+#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */
+
+#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */
+#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos)
+#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */
+#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos)
+#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */
+#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos)
+#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */
+#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos)
+#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */
+#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos)
+#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */
+#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos)
+#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */
+#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos)
+#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */
+#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos)
+#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */
+#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos)
+#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */
+#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos)
+#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */
+#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos)
+#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */
+#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos)
+#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */
+#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos)
+#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */
+#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos)
+#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */
+#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos)
+#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */
+#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos)
+#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */
+#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos)
+#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */
+#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos)
+#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */
+#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos)
+#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */
+#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos)
+#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */
+#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos)
+#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */
+#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos)
+#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */
+#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos)
+#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */
+#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos)
+#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */
+#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos)
+#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */
+#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos)
+#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */
+#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos)
+#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */
+#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos)
+#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */
+#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos)
+#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */
+#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos)
+#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */
+#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos)
+#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */
+#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos)
+#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */
+
+/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */
+ uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */
+ uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */
+ uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */
+ uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */
+ uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */
+ uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */
+ uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */
+ uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */
+ uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */
+ uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */
+ uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */
+ uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */
+ uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */
+ uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */
+ uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */
+ uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */
+ uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */
+ uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */
+ uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */
+ uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */
+ uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */
+ uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */
+ uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */
+ uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */
+ uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */
+ uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */
+ uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */
+ uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */
+ uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */
+ uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */
+ uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBTIE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */
+#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */
+
+#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */
+#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos)
+#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */
+#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos)
+#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */
+#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos)
+#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */
+#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos)
+#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */
+#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos)
+#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */
+#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos)
+#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */
+#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos)
+#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */
+#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos)
+#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */
+#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos)
+#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */
+#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos)
+#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */
+#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos)
+#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */
+#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos)
+#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */
+#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos)
+#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */
+#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos)
+#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */
+#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos)
+#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */
+#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos)
+#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */
+#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos)
+#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */
+#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos)
+#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */
+#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos)
+#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */
+#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos)
+#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */
+#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos)
+#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */
+#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos)
+#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */
+#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos)
+#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */
+#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos)
+#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */
+#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos)
+#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */
+#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos)
+#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */
+#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos)
+#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */
+#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos)
+#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */
+#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos)
+#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */
+#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos)
+#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */
+#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos)
+#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */
+#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos)
+#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */
+
+/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */
+ uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */
+ uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */
+ uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */
+ uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */
+ uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */
+ uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */
+ uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */
+ uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */
+ uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */
+ uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */
+ uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */
+ uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */
+ uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */
+ uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */
+ uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */
+ uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */
+ uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */
+ uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */
+ uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */
+ uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */
+ uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */
+ uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */
+ uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */
+ uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */
+ uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */
+ uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */
+ uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */
+ uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */
+ uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */
+ uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */
+ uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBCIE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */
+#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */
+
+#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */
+#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos)
+#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */
+#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos)
+#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */
+#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos)
+#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */
+#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos)
+#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */
+#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos)
+#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */
+#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos)
+#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */
+#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos)
+#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */
+#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos)
+#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */
+#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos)
+#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */
+#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos)
+#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */
+#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos)
+#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */
+#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos)
+#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */
+#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos)
+#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */
+#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos)
+#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */
+#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos)
+#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */
+#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos)
+#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */
+#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos)
+#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */
+#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos)
+#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */
+#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos)
+#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */
+#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos)
+#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */
+#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos)
+#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */
+#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos)
+#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */
+#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos)
+#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */
+#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos)
+#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */
+#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos)
+#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */
+#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos)
+#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */
+#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos)
+#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */
+#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos)
+#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */
+#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos)
+#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */
+#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos)
+#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */
+#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos)
+#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */
+#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos)
+#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */
+
+/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */
+ uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */
+#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */
+
+#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */
+#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos)
+#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos))
+#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */
+#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos)
+#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos))
+#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */
+#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos)
+#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos))
+#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */
+
+/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */
+ uint32_t :3; /*!< bit: 21..23 Reserved */
+ uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */
+ uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */
+#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */
+
+#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */
+#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos)
+#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos))
+#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */
+#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos)
+#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos))
+#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */
+#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos)
+#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos))
+#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */
+#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos)
+#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */
+#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos)
+#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */
+
+/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */
+#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */
+
+#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */
+#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos)
+#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos))
+#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */
+
+/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */
+#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */
+
+#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */
+#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos)
+#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos))
+#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */
+#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos)
+#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */
+#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos)
+#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */
+#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos)
+#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */
+
+/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
+ uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */
+#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */
+
+#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */
+#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos)
+#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos))
+#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */
+#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos)
+#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos))
+#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */
+#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos)
+#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */
+#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos)
+#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */
+#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos)
+#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos))
+#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */
+#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos)
+#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */
+
+/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXBE_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */
+#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */
+
+#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */
+#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos)
+#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos))
+#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */
+#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos)
+#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos))
+#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */
+#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos)
+#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos))
+#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */
+#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos)
+#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos))
+#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */
+
+/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0E_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */
+#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */
+
+#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */
+#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos)
+#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos))
+#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */
+#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos)
+#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */
+#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos)
+#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */
+#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos)
+#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */
+
+/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
+ uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0E_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */
+#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */
+
+#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */
+#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos)
+#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos))
+#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */
+#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos)
+#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos))
+#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */
+#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos)
+#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */
+#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos)
+#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */
+#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos)
+#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos))
+#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */
+#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos)
+#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */
+
+/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF0E_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */
+#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */
+
+#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */
+#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos)
+#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos))
+#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */
+#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos)
+#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos))
+#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */
+#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos)
+#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos))
+#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */
+#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos)
+#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos))
+#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */
+
+/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1E_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */
+#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */
+
+#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */
+#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos)
+#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos))
+#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */
+#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos)
+#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */
+#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos)
+#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */
+#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos)
+#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */
+
+/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */
+ uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1E_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */
+#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */
+
+#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */
+#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos)
+#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos))
+#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */
+#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos)
+#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos))
+#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */
+#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos)
+#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */
+#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos)
+#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */
+#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos)
+#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos))
+#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */
+#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos)
+#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */
+
+/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_RXF1E_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */
+#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */
+
+#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */
+#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos)
+#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos))
+#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */
+#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos)
+#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos))
+#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */
+#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos)
+#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos))
+#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */
+#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos)
+#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos))
+#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */
+
+/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */
+ uint32_t :5; /*!< bit: 11..15 Reserved */
+ uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */
+ uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */
+ uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_SIDFE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */
+#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */
+
+#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */
+#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos)
+#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos))
+#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */
+#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos)
+#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos))
+#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */
+#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos))
+#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */
+#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */
+#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */
+#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */
+#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */
+#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */
+#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */
+#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */
+#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos)
+#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */
+#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos))
+#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */
+#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */
+#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */
+#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos)
+#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */
+
+/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Identifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */
+#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */
+
+#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */
+#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos)
+#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos))
+#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */
+#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos)
+#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */
+#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos)
+#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */
+#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos)
+#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */
+
+/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t DLC:4; /*!< bit: 16..19 Identifier */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */
+ uint32_t MM:8; /*!< bit: 24..31 Message Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */
+#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */
+
+#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */
+#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos)
+#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos))
+#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */
+#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos)
+#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */
+#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos)
+#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */
+#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos)
+#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */
+#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos)
+#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos))
+#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */
+
+/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */
+ uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */
+ uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */
+ uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXBE_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */
+#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */
+
+#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */
+#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos)
+#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos))
+#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */
+#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos)
+#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos))
+#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */
+#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos)
+#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos))
+#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */
+#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos)
+#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos))
+#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */
+
+/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:29; /*!< bit: 0..28 Identifier */
+ uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */
+ uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */
+ uint32_t ESI:1; /*!< bit: 31 Error State Indicator */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */
+#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */
+
+#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */
+#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos)
+#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos))
+#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */
+#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos)
+#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */
+#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos)
+#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */
+#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos)
+#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */
+
+/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */
+ uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */
+ uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */
+ uint32_t FDF:1; /*!< bit: 21 FD Format */
+ uint32_t ET:2; /*!< bit: 22..23 Event Type */
+ uint32_t MM:8; /*!< bit: 24..31 Message Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_TXEFE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */
+#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */
+
+#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */
+#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos)
+#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos))
+#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */
+#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos)
+#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos))
+#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */
+#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos)
+#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */
+#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos)
+#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */
+#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos)
+#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos))
+#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */
+#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */
+#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos)
+#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos)
+#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */
+#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos)
+#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos))
+#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */
+
+/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */
+ uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDFE_0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */
+#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */
+
+#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */
+#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos)
+#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos))
+#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */
+#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos))
+#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */
+#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */
+#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */
+#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */
+#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */
+#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */
+#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */
+#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */
+#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos)
+#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */
+
+/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CAN_XIDFE_1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */
+#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */
+
+#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */
+#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos)
+#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos))
+#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */
+#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos))
+#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */
+#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */
+#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */
+#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */
+#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos)
+#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */
+
+/** \brief CAN APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */
+ __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */
+ __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */
+ __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */
+ __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */
+ __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */
+ __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */
+ __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */
+ __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */
+ __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */
+ __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */
+ __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */
+ RoReg8 Reserved1[0x10];
+ __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */
+ __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */
+ __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */
+ RoReg8 Reserved2[0x4];
+ __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */
+ __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */
+ __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */
+ __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */
+ RoReg8 Reserved3[0x20];
+ __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */
+ __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */
+ __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */
+ RoReg8 Reserved4[0x4];
+ __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */
+ __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */
+ __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */
+ __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */
+ __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */
+ __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */
+ __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */
+ __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */
+ __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */
+ __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */
+ __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */
+ __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */
+ __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */
+ __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */
+ __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */
+ __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */
+ __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */
+ __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */
+ __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */
+ __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */
+ __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */
+ __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */
+ RoReg8 Reserved5[0x8];
+ __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */
+ __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */
+ __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */
+} Can;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_rxbe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */
+ __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */
+ __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */
+} CanMramRxbe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_rxf0e hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */
+ __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */
+ __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */
+} CanMramRxf0e
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_rxf1e hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */
+ __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */
+ __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */
+} CanMramRxf1e
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_sidfe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */
+} CanMramSidfe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_txbe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */
+ __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */
+ __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */
+} CanMramTxbe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_txefe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */
+ __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */
+} CanMramTxefe
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief CAN Mram_xifde hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */
+ __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */
+} CanMramXifde
+#ifdef __GNUC__
+ __attribute__ ((aligned (4)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_CAN_MRAM_RXBE
+
+#define SECTION_CAN_MRAM_RXF0E
+
+#define SECTION_CAN_MRAM_RXF1E
+
+#define SECTION_CAN_MRAM_SIDFE
+
+#define SECTION_CAN_MRAM_TXBE
+
+#define SECTION_CAN_MRAM_TXEFE
+
+#define SECTION_CAN_MRAM_XIFDE
+
+/*@}*/
+
+#endif /* _SAME54_CAN_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/ccl.h b/GPIO/ATSAME54/include/component/ccl.h
new file mode 100644
index 0000000..658789e
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/ccl.h
@@ -0,0 +1,228 @@
+/**
+ * \file
+ *
+ * \brief Component description for CCL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CCL_COMPONENT_
+#define _SAME54_CCL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR CCL */
+/* ========================================================================== */
+/** \addtogroup SAME54_CCL Configurable Custom Logic */
+/*@{*/
+
+#define CCL_U2225
+#define REV_CCL 0x110
+
+/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} CCL_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
+#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
+
+#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
+#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
+#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
+#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
+#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
+#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
+#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
+
+/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} CCL_SEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
+#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
+
+#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
+#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
+#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
+#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
+#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
+#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
+#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
+#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
+
+/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
+ uint32_t :2; /*!< bit: 2.. 3 Reserved */
+ uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
+ uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
+ uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
+ uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
+ uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
+ uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
+ uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CCL_LUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
+#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
+
+#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
+#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
+#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
+#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
+#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
+#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
+#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
+#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
+#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
+#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
+#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
+#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
+#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
+#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
+#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
+#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
+#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
+#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
+#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
+#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
+#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
+#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
+#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
+#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
+#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
+#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
+#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
+#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
+#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
+#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
+#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
+#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
+#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
+#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
+#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
+#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
+#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
+#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
+#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
+#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
+
+/** \brief CCL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
+ RoReg8 Reserved2[0x2];
+ __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
+} Ccl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_CCL_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/cmcc.h b/GPIO/ATSAME54/include/component/cmcc.h
new file mode 100644
index 0000000..82a4e72
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/cmcc.h
@@ -0,0 +1,357 @@
+/**
+ * \file
+ *
+ * \brief Component description for CMCC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CMCC_COMPONENT_
+#define _SAME54_CMCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR CMCC */
+/* ========================================================================== */
+/** \addtogroup SAME54_CMCC Cortex M Cache Controller */
+/*@{*/
+
+#define CMCC_U2015
+#define REV_CMCC 0x600
+
+/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
+ uint32_t :2; /*!< bit: 2.. 3 Reserved */
+ uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
+ uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
+ uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
+ uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
+ uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_TYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
+#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
+
+#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
+#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
+#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
+#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
+#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
+#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
+#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
+#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
+#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
+#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
+#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
+#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
+#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
+#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
+#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
+#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
+
+/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
+ uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
+#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
+
+#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
+#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
+#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
+#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
+#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
+#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
+
+/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
+#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
+
+#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
+#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
+#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
+
+/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_SR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
+#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
+
+#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
+#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
+#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
+
+/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_LCKWAY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
+#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
+
+#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
+#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
+#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
+#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
+
+/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MAINT0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
+#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
+
+#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
+#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
+#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
+
+/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
+ uint32_t :16; /*!< bit: 12..27 Reserved */
+ uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MAINT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
+#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
+
+#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
+#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
+#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
+#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
+#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
+#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
+
+/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
+#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
+
+#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
+#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
+#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
+#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
+#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
+#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
+
+/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
+#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
+
+#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
+#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
+#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
+
+/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
+#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
+
+#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
+#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
+#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
+
+/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} CMCC_MSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
+#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
+
+#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
+#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
+#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
+#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
+
+/** \brief CMCC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
+ __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
+ __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
+ __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
+ __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
+ RoReg8 Reserved1[0xC];
+ __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
+ __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
+ __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
+ __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
+ __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
+ __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
+} Cmcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_CMCC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/dac.h b/GPIO/ATSAME54/include/component/dac.h
new file mode 100644
index 0000000..522b119
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/dac.h
@@ -0,0 +1,544 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DAC_COMPONENT_
+#define _SAME54_DAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_DAC Digital-to-Analog Converter */
+/*@{*/
+
+#define DAC_U2502
+#define REV_DAC 0x100
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */
+#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */
+ uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */
+#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
+#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
+#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */
+#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */
+#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */
+#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */
+#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */
+ uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */
+ uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */
+ uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */
+ uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */
+ uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */
+ uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */
+ uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */
+ uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */
+ uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */
+ uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
+#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
+#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
+#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
+#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
+#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
+#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
+#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
+#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
+#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
+#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
+#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
+#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
+#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
+#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
+#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
+#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
+#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
+#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
+#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
+#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
+#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
+#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
+#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
+#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
+ uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
+ uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
+ uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
+ uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
+ uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
+ uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
+ uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
+ uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
+ uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
+ uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
+#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
+#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
+#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
+#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
+#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
+#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
+#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
+#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
+#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
+#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
+#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
+#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
+#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
+ uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
+ uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
+ uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
+ uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
+ uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
+ uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
+ uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
+ uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
+ uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
+ uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
+#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
+#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
+#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
+#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
+#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
+#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
+#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
+#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
+#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
+#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
+#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
+#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
+#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
+#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
+#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
+#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */
+ __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */
+ __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
+ __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
+ __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */
+ __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */
+ __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */
+ __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */
+ __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
+ __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */
+ __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */
+#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
+#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */
+#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */
+#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
+#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
+#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
+#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
+#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
+#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
+#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
+#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */
+#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
+#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */
+#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
+#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */
+#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
+#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
+#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */
+#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
+#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */
+#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
+#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */
+#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
+#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
+#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */
+ uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */
+ uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */
+ uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */
+ uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
+#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
+#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
+#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
+#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */
+#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
+#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
+#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
+#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
+#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
+#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
+#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */
+#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
+#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
+#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */
+ uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */
+ uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */
+ uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */
+ uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */
+ uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DAC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
+#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */
+#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
+#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
+#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
+#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
+#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
+#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
+#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
+#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */
+#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
+#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
+#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
+#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
+#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
+#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
+#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
+#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
+#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
+#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
+
+/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */
+ uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */
+ uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DACCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */
+#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
+
+#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */
+#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
+#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */
+#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
+#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */
+#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
+#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
+#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */
+#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
+#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */
+#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
+#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */
+#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
+#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */
+#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
+#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */
+#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
+#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
+#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */
+#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
+#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
+#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */
+#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */
+
+#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */
+#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
+#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
+
+/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */
+#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
+
+#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */
+#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
+#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */
+
+/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */
+#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */
+
+#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */
+#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
+#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
+#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
+ __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
+ __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
+ __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
+ __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x3];
+ __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_DAC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/dmac.h b/GPIO/ATSAME54/include/component/dmac.h
new file mode 100644
index 0000000..3e4a729
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/dmac.h
@@ -0,0 +1,1416 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DMAC_COMPONENT_
+#define _SAME54_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2503
+#define REV_DMAC 0x100
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t :6; /*!< bit: 2.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */
+#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
+#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
+#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */
+#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
+#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
+#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t CRCERR:1; /*!< bit: 2 CRC Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */
+#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
+#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */
+ uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */
+ uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */
+ uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */
+ uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */
+ uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */
+ uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */
+ uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */
+ uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */
+ uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */
+ uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */
+ uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */
+ uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */
+ uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */
+ uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */
+ uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */
+ uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */
+ uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */
+ uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */
+ uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */
+ uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */
+ uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */
+ uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */
+ uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
+#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
+#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
+#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
+#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
+#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
+#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
+#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
+#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t CRCERR:1; /*!< bit: 12 CRC Error */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */
+#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
+#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */
+ uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */
+ uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */
+ uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */
+ uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */
+ uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */
+ uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */
+ uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */
+ uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */
+ uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */
+ uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */
+ uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */
+ uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */
+ uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */
+ uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */
+ uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */
+ uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */
+ uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */
+ uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */
+ uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
+#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
+#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
+#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
+#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
+#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
+#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
+#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
+#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
+#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
+#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
+#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
+#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
+#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
+#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
+#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
+#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
+#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
+#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
+#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */
+ uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */
+ uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */
+ uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */
+ uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */
+ uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */
+ uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */
+ uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */
+ uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */
+ uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */
+ uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */
+ uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */
+ uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */
+ uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */
+ uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */
+ uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */
+ uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */
+ uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */
+ uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */
+ uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
+#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
+#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
+#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
+#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
+#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
+#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
+#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
+#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
+#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
+#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
+#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
+#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
+#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
+#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
+#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
+#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
+#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
+#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
+#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
+#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
+#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
+#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
+#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
+#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
+#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
+#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
+#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
+#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
+#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
+#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
+#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
+#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
+#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
+#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
+#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
+#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
+#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
+#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
+#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */
+ uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */
+ uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */
+ uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */
+ uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */
+ uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */
+ uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */
+ uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */
+ uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */
+ uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */
+ uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */
+ uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */
+ uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */
+ uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */
+ uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */
+ uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */
+ uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */
+ uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */
+ uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */
+ uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */
+#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
+#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */
+#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
+#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */
+#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
+#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */
+#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
+#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */
+#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
+#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */
+#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
+#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */
+#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
+#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */
+#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
+#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */
+#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
+#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */
+#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
+#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */
+#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
+#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */
+#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
+#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */
+#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
+#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */
+#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
+#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */
+#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
+#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */
+#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
+#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */
+#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
+#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */
+#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
+#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */
+#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
+#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */
+#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
+#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */
+ uint32_t :5; /*!< bit: 15..19 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */
+ uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
+#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
+#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
+#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */
+#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
+#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
+#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
+#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
+#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */
+#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
+#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
+#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
+#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
+#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */
+#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
+#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
+#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
+#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
+#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
+#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
+#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
+
+#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHPRILVL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
+#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
+
+#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
+#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
+#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
+#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
+#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
+#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
+#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
+#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
+#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
+#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
+#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */
+
+/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */
+ uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */
+ uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHEVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
+#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
+
+#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
+#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
+#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */
+#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
+#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
+#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
+#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
+#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
+#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
+#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */
+#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
+#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
+#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
+#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
+#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
+#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
+#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
+#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
+#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
+#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
+
+#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
+#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
+#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */
+#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */
+#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
+#define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
+#define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
+#define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
+#define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
+#define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
+#define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
+#define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK _U_(0xFF1F) /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+#define DMAC_BTCNT_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCNT reset_value) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK _U_(0xFFFF) /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
+#define DMAC_SRCADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SRCADDR reset_value) Block Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // CRC mode
+ uint32_t CHKINIT:32; /*!< bit: 0..31 CRC Checksum Initial Value */
+ } CRC; /*!< Structure used for CRC */
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
+
+// CRC mode
+#define DMAC_DSTADDR_CRC_CHKINIT_Pos 0 /**< \brief (DMAC_DSTADDR_CRC) CRC Checksum Initial Value */
+#define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
+#define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
+#define DMAC_DSTADDR_CRC_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR_CRC) MASK Register */
+
+#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DmacChannel hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B */
+ __IO DMAC_CHPRILVL_Type CHPRILVL; /**< \brief Offset: 0x05 (R/W 8) Channel n Priority Level */
+ __IO DMAC_CHEVCTRL_Type CHEVCTRL; /**< \brief Offset: 0x06 (R/W 8) Channel n Event Control */
+ RoReg8 Reserved1[0x5];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear */
+ __IO DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0F (R/W 8) Channel n Status */
+} DmacChannel;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x2];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x4];
+ DmacChannel Channel[32]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+ __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#ifdef __GNUC__
+ #define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".hsram")))
+#elif defined(__ICCARM__)
+ #define SECTION_DMAC_DESCRIPTOR @".hsram"
+#endif
+
+/*@}*/
+
+#endif /* _SAME54_DMAC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/dsu.h b/GPIO/ATSAME54/include/component/dsu.h
new file mode 100644
index 0000000..7868241
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/dsu.h
@@ -0,0 +1,1244 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DSU_COMPONENT_
+#define _SAME54_DSU_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAME54_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2410
+#define REV_DSU 0x100
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */
+ uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */
+ uint8_t CE:1; /*!< bit: 4 Chip-Erase */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */
+ uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
+#define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */
+#define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */
+#define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */
+#define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos)
+#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */
+#define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos)
+#define DSU_CTRL_MASK _U_(0xDD) /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */
+ uint8_t TDCCD0:1; /*!< bit: 6 Test Debug Communication Channel 0 Dirty */
+ uint8_t TDCCD1:1; /*!< bit: 7 Test Debug Communication Channel 1 Dirty */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t TDCCD:2; /*!< bit: 6.. 7 Test Debug Communication Channel x Dirty */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */
+#define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
+#define DSU_STATUSB_TDCCD0_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_TDCCD0 (_U_(1) << DSU_STATUSB_TDCCD0_Pos)
+#define DSU_STATUSB_TDCCD1_Pos 7 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_TDCCD1 (_U_(1) << DSU_STATUSB_TDCCD1_Pos)
+#define DSU_STATUSB_TDCCD_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */
+#define DSU_STATUSB_TDCCD_Msk (_U_(0x3) << DSU_STATUSB_TDCCD_Pos)
+#define DSU_STATUSB_TDCCD(value) (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos))
+#define DSU_STATUSB_MASK _U_(0xFF) /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */
+#define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos)
+#define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
+#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Number */
+ uint32_t SERIES:6; /*!< bit: 16..21 Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */
+#define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */
+#define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */
+#define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define DSU_DID_SERIES_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
+#define DSU_DID_SERIES_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, USB */
+#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos)
+#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */
+#define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define DSU_DID_FAMILY_0_Val _U_(0x0) /**< \brief (DSU_DID) General purpose microcontroller */
+#define DSU_DID_FAMILY_1_Val _U_(0x1) /**< \brief (DSU_DID) PicoPower */
+#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos)
+#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ */
+#define DSU_DID_PROCESSOR_CM23_Val _U_(0x2) /**< \brief (DSU_DID) Cortex-M23 */
+#define DSU_DID_PROCESSOR_CM3_Val _U_(0x3) /**< \brief (DSU_DID) Cortex-M3 */
+#define DSU_DID_PROCESSOR_CM4_Val _U_(0x5) /**< \brief (DSU_DID) Cortex-M4 */
+#define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6) /**< \brief (DSU_DID) Cortex-M4 with FPU */
+#define DSU_DID_PROCESSOR_CM33_Val _U_(0x7) /**< \brief (DSU_DID) Cortex-M33 */
+#define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LQOS:2; /*!< bit: 0.. 1 Latency Quality Of Service */
+ uint32_t DCCDMALEVEL:2; /*!< bit: 2.. 3 DMA Trigger Level */
+ uint32_t ETBRAMEN:1; /*!< bit: 4 Trace Control */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CFG_OFFSET 0x001C /**< \brief (DSU_CFG offset) Configuration */
+#define DSU_CFG_RESETVALUE _U_(0x00000002) /**< \brief (DSU_CFG reset_value) Configuration */
+
+#define DSU_CFG_LQOS_Pos 0 /**< \brief (DSU_CFG) Latency Quality Of Service */
+#define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos)
+#define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))
+#define DSU_CFG_DCCDMALEVEL_Pos 2 /**< \brief (DSU_CFG) DMA Trigger Level */
+#define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos)
+#define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))
+#define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0) /**< \brief (DSU_CFG) Trigger rises when DCC is empty */
+#define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1) /**< \brief (DSU_CFG) Trigger rises when DCC is full */
+#define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos)
+#define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos)
+#define DSU_CFG_ETBRAMEN_Pos 4 /**< \brief (DSU_CFG) Trace Control */
+#define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
+#define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */
+
+/* -------- DSU_MBCTRL : (DSU Offset: 0x0040) (R/W 32) MBIST Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 MBIST Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 MBIST Enable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBCTRL_OFFSET 0x0040 /**< \brief (DSU_MBCTRL offset) MBIST Control */
+#define DSU_MBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBCTRL reset_value) MBIST Control */
+
+#define DSU_MBCTRL_SWRST_Pos 0 /**< \brief (DSU_MBCTRL) MBIST Software Reset */
+#define DSU_MBCTRL_SWRST (_U_(0x1) << DSU_MBCTRL_SWRST_Pos)
+#define DSU_MBCTRL_ENABLE_Pos 1 /**< \brief (DSU_MBCTRL) MBIST Enable */
+#define DSU_MBCTRL_ENABLE (_U_(0x1) << DSU_MBCTRL_ENABLE_Pos)
+#define DSU_MBCTRL_MASK _U_(0x00000003) /**< \brief (DSU_MBCTRL) MASK Register */
+
+/* -------- DSU_MBCONFIG : (DSU Offset: 0x0044) (R/W 32) MBIST Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ALGO:5; /*!< bit: 0.. 4 MBIST Algorithm */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t DEFRDMARGIN:1; /*!< bit: 6 Force Default Read Margin */
+ uint32_t DBG:1; /*!< bit: 7 Enable Debug Mode */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBCONFIG_OFFSET 0x0044 /**< \brief (DSU_MBCONFIG offset) MBIST Configuration */
+#define DSU_MBCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBCONFIG reset_value) MBIST Configuration */
+
+#define DSU_MBCONFIG_ALGO_Pos 0 /**< \brief (DSU_MBCONFIG) MBIST Algorithm */
+#define DSU_MBCONFIG_ALGO_Msk (_U_(0x1F) << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO(value) (DSU_MBCONFIG_ALGO_Msk & ((value) << DSU_MBCONFIG_ALGO_Pos))
+#define DSU_MBCONFIG_ALGO_MEMCLEAR_Val _U_(0x0) /**< \brief (DSU_MBCONFIG) Memory Clear (1n) */
+#define DSU_MBCONFIG_ALGO_VERIFY_Val _U_(0x1) /**< \brief (DSU_MBCONFIG) Memory Verify (1n) */
+#define DSU_MBCONFIG_ALGO_CLEARVER_Val _U_(0x2) /**< \brief (DSU_MBCONFIG) Memory Clear and Verify (2n) */
+#define DSU_MBCONFIG_ALGO_ADDR_DEC_Val _U_(0x3) /**< \brief (DSU_MBCONFIG) Address Decoder (2n) */
+#define DSU_MBCONFIG_ALGO_MARCH_LR_Val _U_(0x4) /**< \brief (DSU_MBCONFIG) March LR (14n) */
+#define DSU_MBCONFIG_ALGO_MARCH_SR_Val _U_(0x5) /**< \brief (DSU_MBCONFIG) March SR (14n) */
+#define DSU_MBCONFIG_ALGO_MARCH_SS_Val _U_(0x6) /**< \brief (DSU_MBCONFIG) March SS (22n) */
+#define DSU_MBCONFIG_ALGO_CRC_UP_Val _U_(0x8) /**< \brief (DSU_MBCONFIG) CRC increasing address (1n) */
+#define DSU_MBCONFIG_ALGO_CRC_DOWN_Val _U_(0x9) /**< \brief (DSU_MBCONFIG) CRC decreasing address (1n) */
+#define DSU_MBCONFIG_ALGO_MEMCLEAR (DSU_MBCONFIG_ALGO_MEMCLEAR_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_VERIFY (DSU_MBCONFIG_ALGO_VERIFY_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_CLEARVER (DSU_MBCONFIG_ALGO_CLEARVER_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_ADDR_DEC (DSU_MBCONFIG_ALGO_ADDR_DEC_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_MARCH_LR (DSU_MBCONFIG_ALGO_MARCH_LR_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_MARCH_SR (DSU_MBCONFIG_ALGO_MARCH_SR_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_MARCH_SS (DSU_MBCONFIG_ALGO_MARCH_SS_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_CRC_UP (DSU_MBCONFIG_ALGO_CRC_UP_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_ALGO_CRC_DOWN (DSU_MBCONFIG_ALGO_CRC_DOWN_Val << DSU_MBCONFIG_ALGO_Pos)
+#define DSU_MBCONFIG_DEFRDMARGIN_Pos 6 /**< \brief (DSU_MBCONFIG) Force Default Read Margin */
+#define DSU_MBCONFIG_DEFRDMARGIN (_U_(0x1) << DSU_MBCONFIG_DEFRDMARGIN_Pos)
+#define DSU_MBCONFIG_DBG_Pos 7 /**< \brief (DSU_MBCONFIG) Enable Debug Mode */
+#define DSU_MBCONFIG_DBG (_U_(0x1) << DSU_MBCONFIG_DBG_Pos)
+#define DSU_MBCONFIG_MASK _U_(0x000000DF) /**< \brief (DSU_MBCONFIG) MASK Register */
+
+/* -------- DSU_MBWORD : (DSU Offset: 0x0048) (R/W 32) MBIST Background Word -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 MBIST Background Word */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBWORD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBWORD_OFFSET 0x0048 /**< \brief (DSU_MBWORD offset) MBIST Background Word */
+#define DSU_MBWORD_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBWORD reset_value) MBIST Background Word */
+
+#define DSU_MBWORD_DATA_Pos 0 /**< \brief (DSU_MBWORD) MBIST Background Word */
+#define DSU_MBWORD_DATA_Msk (_U_(0xFFFFFFFF) << DSU_MBWORD_DATA_Pos)
+#define DSU_MBWORD_DATA(value) (DSU_MBWORD_DATA_Msk & ((value) << DSU_MBWORD_DATA_Pos))
+#define DSU_MBWORD_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_MBWORD) MASK Register */
+
+/* -------- DSU_MBGSTAT : (DSU Offset: 0x004C) (R/W 32) MBIST Global Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ALLDONE:1; /*!< bit: 0 MBIST Completed */
+ uint32_t FAILED:1; /*!< bit: 1 MBIST Failed */
+ uint32_t ERRINFO:1; /*!< bit: 2 MBIST Error Info Present */
+ uint32_t CONFIGURED:1; /*!< bit: 3 MBIST Configuration Sent */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBGSTAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBGSTAT_OFFSET 0x004C /**< \brief (DSU_MBGSTAT offset) MBIST Global Status */
+#define DSU_MBGSTAT_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBGSTAT reset_value) MBIST Global Status */
+
+#define DSU_MBGSTAT_ALLDONE_Pos 0 /**< \brief (DSU_MBGSTAT) MBIST Completed */
+#define DSU_MBGSTAT_ALLDONE (_U_(0x1) << DSU_MBGSTAT_ALLDONE_Pos)
+#define DSU_MBGSTAT_FAILED_Pos 1 /**< \brief (DSU_MBGSTAT) MBIST Failed */
+#define DSU_MBGSTAT_FAILED (_U_(0x1) << DSU_MBGSTAT_FAILED_Pos)
+#define DSU_MBGSTAT_ERRINFO_Pos 2 /**< \brief (DSU_MBGSTAT) MBIST Error Info Present */
+#define DSU_MBGSTAT_ERRINFO (_U_(0x1) << DSU_MBGSTAT_ERRINFO_Pos)
+#define DSU_MBGSTAT_CONFIGURED_Pos 3 /**< \brief (DSU_MBGSTAT) MBIST Configuration Sent */
+#define DSU_MBGSTAT_CONFIGURED (_U_(0x1) << DSU_MBGSTAT_CONFIGURED_Pos)
+#define DSU_MBGSTAT_MASK _U_(0x0000000F) /**< \brief (DSU_MBGSTAT) MASK Register */
+
+/* -------- DSU_MBDFAIL : (DSU Offset: 0x0050) (R/ 32) MBIST Fail Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Error Data Read */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBDFAIL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBDFAIL_OFFSET 0x0050 /**< \brief (DSU_MBDFAIL offset) MBIST Fail Data */
+#define DSU_MBDFAIL_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBDFAIL reset_value) MBIST Fail Data */
+
+#define DSU_MBDFAIL_DATA_Pos 0 /**< \brief (DSU_MBDFAIL) Error Data Read */
+#define DSU_MBDFAIL_DATA_Msk (_U_(0xFFFFFFFF) << DSU_MBDFAIL_DATA_Pos)
+#define DSU_MBDFAIL_DATA(value) (DSU_MBDFAIL_DATA_Msk & ((value) << DSU_MBDFAIL_DATA_Pos))
+#define DSU_MBDFAIL_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_MBDFAIL) MASK Register */
+
+/* -------- DSU_MBDEXP : (DSU Offset: 0x0054) (R/ 32) MBIST Expected Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Expected Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBDEXP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBDEXP_OFFSET 0x0054 /**< \brief (DSU_MBDEXP offset) MBIST Expected Data */
+#define DSU_MBDEXP_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBDEXP reset_value) MBIST Expected Data */
+
+#define DSU_MBDEXP_DATA_Pos 0 /**< \brief (DSU_MBDEXP) Expected Data */
+#define DSU_MBDEXP_DATA_Msk (_U_(0xFFFFFFFF) << DSU_MBDEXP_DATA_Pos)
+#define DSU_MBDEXP_DATA(value) (DSU_MBDEXP_DATA_Msk & ((value) << DSU_MBDEXP_DATA_Pos))
+#define DSU_MBDEXP_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_MBDEXP) MASK Register */
+
+/* -------- DSU_MBAFAIL : (DSU Offset: 0x0058) (R/ 32) MBIST Fail Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:14; /*!< bit: 0..13 Error Address */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBAFAIL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBAFAIL_OFFSET 0x0058 /**< \brief (DSU_MBAFAIL offset) MBIST Fail Address */
+#define DSU_MBAFAIL_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBAFAIL reset_value) MBIST Fail Address */
+
+#define DSU_MBAFAIL_ADDR_Pos 0 /**< \brief (DSU_MBAFAIL) Error Address */
+#define DSU_MBAFAIL_ADDR_Msk (_U_(0x3FFF) << DSU_MBAFAIL_ADDR_Pos)
+#define DSU_MBAFAIL_ADDR(value) (DSU_MBAFAIL_ADDR_Msk & ((value) << DSU_MBAFAIL_ADDR_Pos))
+#define DSU_MBAFAIL_MASK _U_(0x00003FFF) /**< \brief (DSU_MBAFAIL) MASK Register */
+
+/* -------- DSU_MBCONTEXT : (DSU Offset: 0x005C) (R/ 32) MBIST Fail Context -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SUBSTEP:5; /*!< bit: 0.. 4 Algorithm Sub-step */
+ uint32_t STEP:5; /*!< bit: 5.. 9 Algorithm Step */
+ uint32_t PORT:1; /*!< bit: 10 DPRAM Port Index */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBCONTEXT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBCONTEXT_OFFSET 0x005C /**< \brief (DSU_MBCONTEXT offset) MBIST Fail Context */
+#define DSU_MBCONTEXT_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBCONTEXT reset_value) MBIST Fail Context */
+
+#define DSU_MBCONTEXT_SUBSTEP_Pos 0 /**< \brief (DSU_MBCONTEXT) Algorithm Sub-step */
+#define DSU_MBCONTEXT_SUBSTEP_Msk (_U_(0x1F) << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_SUBSTEP(value) (DSU_MBCONTEXT_SUBSTEP_Msk & ((value) << DSU_MBCONTEXT_SUBSTEP_Pos))
+#define DSU_MBCONTEXT_SUBSTEP_R0_1_Val _U_(0x1) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_SUBSTEP_R1_1_Val _U_(0x3) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_SUBSTEP_R0_2_Val _U_(0x5) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_SUBSTEP_R1_2_Val _U_(0x7) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_SUBSTEP_R0_3_Val _U_(0x9) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_SUBSTEP_R1_3_Val _U_(0xB) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_SUBSTEP_R0_1 (DSU_MBCONTEXT_SUBSTEP_R0_1_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_SUBSTEP_R1_1 (DSU_MBCONTEXT_SUBSTEP_R1_1_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_SUBSTEP_R0_2 (DSU_MBCONTEXT_SUBSTEP_R0_2_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_SUBSTEP_R1_2 (DSU_MBCONTEXT_SUBSTEP_R1_2_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_SUBSTEP_R0_3 (DSU_MBCONTEXT_SUBSTEP_R0_3_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_SUBSTEP_R1_3 (DSU_MBCONTEXT_SUBSTEP_R1_3_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
+#define DSU_MBCONTEXT_STEP_Pos 5 /**< \brief (DSU_MBCONTEXT) Algorithm Step */
+#define DSU_MBCONTEXT_STEP_Msk (_U_(0x1F) << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP(value) (DSU_MBCONTEXT_STEP_Msk & ((value) << DSU_MBCONTEXT_STEP_Pos))
+#define DSU_MBCONTEXT_STEP_DOWN_R0W1_Val _U_(0x2) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R1W0R0W1_Val _U_(0x3) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R1W0_Val _U_(0x4) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R0W1R1W0_Val _U_(0x5) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R0_Val _U_(0x6) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1_Val _U_(0x7) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0_Val _U_(0x8) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1_Val _U_(0x9) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0_Val _U_(0xA) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_UP_R0R0_Val _U_(0xC) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1_Val _U_(0xE) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_DOWN_R1R1_Val _U_(0xF) /**< \brief (DSU_MBCONTEXT) */
+#define DSU_MBCONTEXT_STEP_DOWN_R0W1 (DSU_MBCONTEXT_STEP_DOWN_R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R1W0R0W1 (DSU_MBCONTEXT_STEP_UP_R1W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R1W0 (DSU_MBCONTEXT_STEP_UP_R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R0W1R1W0 (DSU_MBCONTEXT_STEP_UP_R0W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R0 (DSU_MBCONTEXT_STEP_UP_R0_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1 (DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0 (DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1 (DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0 (DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_UP_R0R0 (DSU_MBCONTEXT_STEP_UP_R0R0_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1 (DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_STEP_DOWN_R1R1 (DSU_MBCONTEXT_STEP_DOWN_R1R1_Val << DSU_MBCONTEXT_STEP_Pos)
+#define DSU_MBCONTEXT_PORT_Pos 10 /**< \brief (DSU_MBCONTEXT) DPRAM Port Index */
+#define DSU_MBCONTEXT_PORT (_U_(0x1) << DSU_MBCONTEXT_PORT_Pos)
+#define DSU_MBCONTEXT_MASK _U_(0x000007FF) /**< \brief (DSU_MBCONTEXT) MASK Register */
+
+/* -------- DSU_MBENABLE0 : (DSU Offset: 0x0060) (R/W 32) MBIST Memory Enable 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE0:1; /*!< bit: 0 Memory 0 MBIST Enable */
+ uint32_t ENABLE1:1; /*!< bit: 1 Memory 1 MBIST Enable */
+ uint32_t ENABLE2:1; /*!< bit: 2 Memory 2 MBIST Enable */
+ uint32_t ENABLE3:1; /*!< bit: 3 Memory 3 MBIST Enable */
+ uint32_t ENABLE4:1; /*!< bit: 4 Memory 4 MBIST Enable */
+ uint32_t ENABLE5:1; /*!< bit: 5 Memory 5 MBIST Enable */
+ uint32_t ENABLE6:1; /*!< bit: 6 Memory 6 MBIST Enable */
+ uint32_t ENABLE7:1; /*!< bit: 7 Memory 7 MBIST Enable */
+ uint32_t ENABLE8:1; /*!< bit: 8 Memory 8 MBIST Enable */
+ uint32_t ENABLE9:1; /*!< bit: 9 Memory 9 MBIST Enable */
+ uint32_t ENABLE10:1; /*!< bit: 10 Memory 10 MBIST Enable */
+ uint32_t ENABLE11:1; /*!< bit: 11 Memory 11 MBIST Enable */
+ uint32_t ENABLE12:1; /*!< bit: 12 Memory 12 MBIST Enable */
+ uint32_t ENABLE13:1; /*!< bit: 13 Memory 13 MBIST Enable */
+ uint32_t ENABLE14:1; /*!< bit: 14 Memory 14 MBIST Enable */
+ uint32_t ENABLE15:1; /*!< bit: 15 Memory 15 MBIST Enable */
+ uint32_t ENABLE16:1; /*!< bit: 16 Memory 16 MBIST Enable */
+ uint32_t ENABLE17:1; /*!< bit: 17 Memory 17 MBIST Enable */
+ uint32_t ENABLE18:1; /*!< bit: 18 Memory 18 MBIST Enable */
+ uint32_t ENABLE19:1; /*!< bit: 19 Memory 19 MBIST Enable */
+ uint32_t ENABLE20:1; /*!< bit: 20 Memory 20 MBIST Enable */
+ uint32_t ENABLE21:1; /*!< bit: 21 Memory 21 MBIST Enable */
+ uint32_t ENABLE22:1; /*!< bit: 22 Memory 22 MBIST Enable */
+ uint32_t ENABLE23:1; /*!< bit: 23 Memory 23 MBIST Enable */
+ uint32_t ENABLE24:1; /*!< bit: 24 Memory 24 MBIST Enable */
+ uint32_t ENABLE25:1; /*!< bit: 25 Memory 25 MBIST Enable */
+ uint32_t ENABLE26:1; /*!< bit: 26 Memory 26 MBIST Enable */
+ uint32_t ENABLE27:1; /*!< bit: 27 Memory 27 MBIST Enable */
+ uint32_t ENABLE28:1; /*!< bit: 28 Memory 28 MBIST Enable */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t ENABLE:29; /*!< bit: 0..28 Memory x MBIST Enable */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBENABLE0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBENABLE0_OFFSET 0x0060 /**< \brief (DSU_MBENABLE0 offset) MBIST Memory Enable 0 */
+#define DSU_MBENABLE0_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBENABLE0 reset_value) MBIST Memory Enable 0 */
+
+#define DSU_MBENABLE0_ENABLE0_Pos 0 /**< \brief (DSU_MBENABLE0) Memory 0 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE0 (_U_(1) << DSU_MBENABLE0_ENABLE0_Pos)
+#define DSU_MBENABLE0_ENABLE1_Pos 1 /**< \brief (DSU_MBENABLE0) Memory 1 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE1 (_U_(1) << DSU_MBENABLE0_ENABLE1_Pos)
+#define DSU_MBENABLE0_ENABLE2_Pos 2 /**< \brief (DSU_MBENABLE0) Memory 2 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE2 (_U_(1) << DSU_MBENABLE0_ENABLE2_Pos)
+#define DSU_MBENABLE0_ENABLE3_Pos 3 /**< \brief (DSU_MBENABLE0) Memory 3 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE3 (_U_(1) << DSU_MBENABLE0_ENABLE3_Pos)
+#define DSU_MBENABLE0_ENABLE4_Pos 4 /**< \brief (DSU_MBENABLE0) Memory 4 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE4 (_U_(1) << DSU_MBENABLE0_ENABLE4_Pos)
+#define DSU_MBENABLE0_ENABLE5_Pos 5 /**< \brief (DSU_MBENABLE0) Memory 5 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE5 (_U_(1) << DSU_MBENABLE0_ENABLE5_Pos)
+#define DSU_MBENABLE0_ENABLE6_Pos 6 /**< \brief (DSU_MBENABLE0) Memory 6 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE6 (_U_(1) << DSU_MBENABLE0_ENABLE6_Pos)
+#define DSU_MBENABLE0_ENABLE7_Pos 7 /**< \brief (DSU_MBENABLE0) Memory 7 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE7 (_U_(1) << DSU_MBENABLE0_ENABLE7_Pos)
+#define DSU_MBENABLE0_ENABLE8_Pos 8 /**< \brief (DSU_MBENABLE0) Memory 8 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE8 (_U_(1) << DSU_MBENABLE0_ENABLE8_Pos)
+#define DSU_MBENABLE0_ENABLE9_Pos 9 /**< \brief (DSU_MBENABLE0) Memory 9 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE9 (_U_(1) << DSU_MBENABLE0_ENABLE9_Pos)
+#define DSU_MBENABLE0_ENABLE10_Pos 10 /**< \brief (DSU_MBENABLE0) Memory 10 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE10 (_U_(1) << DSU_MBENABLE0_ENABLE10_Pos)
+#define DSU_MBENABLE0_ENABLE11_Pos 11 /**< \brief (DSU_MBENABLE0) Memory 11 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE11 (_U_(1) << DSU_MBENABLE0_ENABLE11_Pos)
+#define DSU_MBENABLE0_ENABLE12_Pos 12 /**< \brief (DSU_MBENABLE0) Memory 12 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE12 (_U_(1) << DSU_MBENABLE0_ENABLE12_Pos)
+#define DSU_MBENABLE0_ENABLE13_Pos 13 /**< \brief (DSU_MBENABLE0) Memory 13 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE13 (_U_(1) << DSU_MBENABLE0_ENABLE13_Pos)
+#define DSU_MBENABLE0_ENABLE14_Pos 14 /**< \brief (DSU_MBENABLE0) Memory 14 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE14 (_U_(1) << DSU_MBENABLE0_ENABLE14_Pos)
+#define DSU_MBENABLE0_ENABLE15_Pos 15 /**< \brief (DSU_MBENABLE0) Memory 15 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE15 (_U_(1) << DSU_MBENABLE0_ENABLE15_Pos)
+#define DSU_MBENABLE0_ENABLE16_Pos 16 /**< \brief (DSU_MBENABLE0) Memory 16 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE16 (_U_(1) << DSU_MBENABLE0_ENABLE16_Pos)
+#define DSU_MBENABLE0_ENABLE17_Pos 17 /**< \brief (DSU_MBENABLE0) Memory 17 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE17 (_U_(1) << DSU_MBENABLE0_ENABLE17_Pos)
+#define DSU_MBENABLE0_ENABLE18_Pos 18 /**< \brief (DSU_MBENABLE0) Memory 18 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE18 (_U_(1) << DSU_MBENABLE0_ENABLE18_Pos)
+#define DSU_MBENABLE0_ENABLE19_Pos 19 /**< \brief (DSU_MBENABLE0) Memory 19 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE19 (_U_(1) << DSU_MBENABLE0_ENABLE19_Pos)
+#define DSU_MBENABLE0_ENABLE20_Pos 20 /**< \brief (DSU_MBENABLE0) Memory 20 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE20 (_U_(1) << DSU_MBENABLE0_ENABLE20_Pos)
+#define DSU_MBENABLE0_ENABLE21_Pos 21 /**< \brief (DSU_MBENABLE0) Memory 21 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE21 (_U_(1) << DSU_MBENABLE0_ENABLE21_Pos)
+#define DSU_MBENABLE0_ENABLE22_Pos 22 /**< \brief (DSU_MBENABLE0) Memory 22 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE22 (_U_(1) << DSU_MBENABLE0_ENABLE22_Pos)
+#define DSU_MBENABLE0_ENABLE23_Pos 23 /**< \brief (DSU_MBENABLE0) Memory 23 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE23 (_U_(1) << DSU_MBENABLE0_ENABLE23_Pos)
+#define DSU_MBENABLE0_ENABLE24_Pos 24 /**< \brief (DSU_MBENABLE0) Memory 24 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE24 (_U_(1) << DSU_MBENABLE0_ENABLE24_Pos)
+#define DSU_MBENABLE0_ENABLE25_Pos 25 /**< \brief (DSU_MBENABLE0) Memory 25 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE25 (_U_(1) << DSU_MBENABLE0_ENABLE25_Pos)
+#define DSU_MBENABLE0_ENABLE26_Pos 26 /**< \brief (DSU_MBENABLE0) Memory 26 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE26 (_U_(1) << DSU_MBENABLE0_ENABLE26_Pos)
+#define DSU_MBENABLE0_ENABLE27_Pos 27 /**< \brief (DSU_MBENABLE0) Memory 27 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE27 (_U_(1) << DSU_MBENABLE0_ENABLE27_Pos)
+#define DSU_MBENABLE0_ENABLE28_Pos 28 /**< \brief (DSU_MBENABLE0) Memory 28 MBIST Enable */
+#define DSU_MBENABLE0_ENABLE28 (_U_(1) << DSU_MBENABLE0_ENABLE28_Pos)
+#define DSU_MBENABLE0_ENABLE_Pos 0 /**< \brief (DSU_MBENABLE0) Memory x MBIST Enable */
+#define DSU_MBENABLE0_ENABLE_Msk (_U_(0x1FFFFFFF) << DSU_MBENABLE0_ENABLE_Pos)
+#define DSU_MBENABLE0_ENABLE(value) (DSU_MBENABLE0_ENABLE_Msk & ((value) << DSU_MBENABLE0_ENABLE_Pos))
+#define DSU_MBENABLE0_MASK _U_(0x1FFFFFFF) /**< \brief (DSU_MBENABLE0) MASK Register */
+
+/* -------- DSU_MBBUSY0 : (DSU Offset: 0x0068) (R/ 32) MBIST Memory Busy 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSY0:1; /*!< bit: 0 Memory 0 BIST Busy */
+ uint32_t BUSY1:1; /*!< bit: 1 Memory 1 BIST Busy */
+ uint32_t BUSY2:1; /*!< bit: 2 Memory 2 BIST Busy */
+ uint32_t BUSY3:1; /*!< bit: 3 Memory 3 BIST Busy */
+ uint32_t BUSY4:1; /*!< bit: 4 Memory 4 BIST Busy */
+ uint32_t BUSY5:1; /*!< bit: 5 Memory 5 BIST Busy */
+ uint32_t BUSY6:1; /*!< bit: 6 Memory 6 BIST Busy */
+ uint32_t BUSY7:1; /*!< bit: 7 Memory 7 BIST Busy */
+ uint32_t BUSY8:1; /*!< bit: 8 Memory 8 BIST Busy */
+ uint32_t BUSY9:1; /*!< bit: 9 Memory 9 BIST Busy */
+ uint32_t BUSY10:1; /*!< bit: 10 Memory 10 BIST Busy */
+ uint32_t BUSY11:1; /*!< bit: 11 Memory 11 BIST Busy */
+ uint32_t BUSY12:1; /*!< bit: 12 Memory 12 BIST Busy */
+ uint32_t BUSY13:1; /*!< bit: 13 Memory 13 BIST Busy */
+ uint32_t BUSY14:1; /*!< bit: 14 Memory 14 BIST Busy */
+ uint32_t BUSY15:1; /*!< bit: 15 Memory 15 BIST Busy */
+ uint32_t BUSY16:1; /*!< bit: 16 Memory 16 BIST Busy */
+ uint32_t BUSY17:1; /*!< bit: 17 Memory 17 BIST Busy */
+ uint32_t BUSY18:1; /*!< bit: 18 Memory 18 BIST Busy */
+ uint32_t BUSY19:1; /*!< bit: 19 Memory 19 BIST Busy */
+ uint32_t BUSY20:1; /*!< bit: 20 Memory 20 BIST Busy */
+ uint32_t BUSY21:1; /*!< bit: 21 Memory 21 BIST Busy */
+ uint32_t BUSY22:1; /*!< bit: 22 Memory 22 BIST Busy */
+ uint32_t BUSY23:1; /*!< bit: 23 Memory 23 BIST Busy */
+ uint32_t BUSY24:1; /*!< bit: 24 Memory 24 BIST Busy */
+ uint32_t BUSY25:1; /*!< bit: 25 Memory 25 BIST Busy */
+ uint32_t BUSY26:1; /*!< bit: 26 Memory 26 BIST Busy */
+ uint32_t BUSY27:1; /*!< bit: 27 Memory 27 BIST Busy */
+ uint32_t BUSY28:1; /*!< bit: 28 Memory 28 BIST Busy */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSY:29; /*!< bit: 0..28 Memory x BIST Busy */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBBUSY0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBBUSY0_OFFSET 0x0068 /**< \brief (DSU_MBBUSY0 offset) MBIST Memory Busy 0 */
+#define DSU_MBBUSY0_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBBUSY0 reset_value) MBIST Memory Busy 0 */
+
+#define DSU_MBBUSY0_BUSY0_Pos 0 /**< \brief (DSU_MBBUSY0) Memory 0 BIST Busy */
+#define DSU_MBBUSY0_BUSY0 (_U_(1) << DSU_MBBUSY0_BUSY0_Pos)
+#define DSU_MBBUSY0_BUSY1_Pos 1 /**< \brief (DSU_MBBUSY0) Memory 1 BIST Busy */
+#define DSU_MBBUSY0_BUSY1 (_U_(1) << DSU_MBBUSY0_BUSY1_Pos)
+#define DSU_MBBUSY0_BUSY2_Pos 2 /**< \brief (DSU_MBBUSY0) Memory 2 BIST Busy */
+#define DSU_MBBUSY0_BUSY2 (_U_(1) << DSU_MBBUSY0_BUSY2_Pos)
+#define DSU_MBBUSY0_BUSY3_Pos 3 /**< \brief (DSU_MBBUSY0) Memory 3 BIST Busy */
+#define DSU_MBBUSY0_BUSY3 (_U_(1) << DSU_MBBUSY0_BUSY3_Pos)
+#define DSU_MBBUSY0_BUSY4_Pos 4 /**< \brief (DSU_MBBUSY0) Memory 4 BIST Busy */
+#define DSU_MBBUSY0_BUSY4 (_U_(1) << DSU_MBBUSY0_BUSY4_Pos)
+#define DSU_MBBUSY0_BUSY5_Pos 5 /**< \brief (DSU_MBBUSY0) Memory 5 BIST Busy */
+#define DSU_MBBUSY0_BUSY5 (_U_(1) << DSU_MBBUSY0_BUSY5_Pos)
+#define DSU_MBBUSY0_BUSY6_Pos 6 /**< \brief (DSU_MBBUSY0) Memory 6 BIST Busy */
+#define DSU_MBBUSY0_BUSY6 (_U_(1) << DSU_MBBUSY0_BUSY6_Pos)
+#define DSU_MBBUSY0_BUSY7_Pos 7 /**< \brief (DSU_MBBUSY0) Memory 7 BIST Busy */
+#define DSU_MBBUSY0_BUSY7 (_U_(1) << DSU_MBBUSY0_BUSY7_Pos)
+#define DSU_MBBUSY0_BUSY8_Pos 8 /**< \brief (DSU_MBBUSY0) Memory 8 BIST Busy */
+#define DSU_MBBUSY0_BUSY8 (_U_(1) << DSU_MBBUSY0_BUSY8_Pos)
+#define DSU_MBBUSY0_BUSY9_Pos 9 /**< \brief (DSU_MBBUSY0) Memory 9 BIST Busy */
+#define DSU_MBBUSY0_BUSY9 (_U_(1) << DSU_MBBUSY0_BUSY9_Pos)
+#define DSU_MBBUSY0_BUSY10_Pos 10 /**< \brief (DSU_MBBUSY0) Memory 10 BIST Busy */
+#define DSU_MBBUSY0_BUSY10 (_U_(1) << DSU_MBBUSY0_BUSY10_Pos)
+#define DSU_MBBUSY0_BUSY11_Pos 11 /**< \brief (DSU_MBBUSY0) Memory 11 BIST Busy */
+#define DSU_MBBUSY0_BUSY11 (_U_(1) << DSU_MBBUSY0_BUSY11_Pos)
+#define DSU_MBBUSY0_BUSY12_Pos 12 /**< \brief (DSU_MBBUSY0) Memory 12 BIST Busy */
+#define DSU_MBBUSY0_BUSY12 (_U_(1) << DSU_MBBUSY0_BUSY12_Pos)
+#define DSU_MBBUSY0_BUSY13_Pos 13 /**< \brief (DSU_MBBUSY0) Memory 13 BIST Busy */
+#define DSU_MBBUSY0_BUSY13 (_U_(1) << DSU_MBBUSY0_BUSY13_Pos)
+#define DSU_MBBUSY0_BUSY14_Pos 14 /**< \brief (DSU_MBBUSY0) Memory 14 BIST Busy */
+#define DSU_MBBUSY0_BUSY14 (_U_(1) << DSU_MBBUSY0_BUSY14_Pos)
+#define DSU_MBBUSY0_BUSY15_Pos 15 /**< \brief (DSU_MBBUSY0) Memory 15 BIST Busy */
+#define DSU_MBBUSY0_BUSY15 (_U_(1) << DSU_MBBUSY0_BUSY15_Pos)
+#define DSU_MBBUSY0_BUSY16_Pos 16 /**< \brief (DSU_MBBUSY0) Memory 16 BIST Busy */
+#define DSU_MBBUSY0_BUSY16 (_U_(1) << DSU_MBBUSY0_BUSY16_Pos)
+#define DSU_MBBUSY0_BUSY17_Pos 17 /**< \brief (DSU_MBBUSY0) Memory 17 BIST Busy */
+#define DSU_MBBUSY0_BUSY17 (_U_(1) << DSU_MBBUSY0_BUSY17_Pos)
+#define DSU_MBBUSY0_BUSY18_Pos 18 /**< \brief (DSU_MBBUSY0) Memory 18 BIST Busy */
+#define DSU_MBBUSY0_BUSY18 (_U_(1) << DSU_MBBUSY0_BUSY18_Pos)
+#define DSU_MBBUSY0_BUSY19_Pos 19 /**< \brief (DSU_MBBUSY0) Memory 19 BIST Busy */
+#define DSU_MBBUSY0_BUSY19 (_U_(1) << DSU_MBBUSY0_BUSY19_Pos)
+#define DSU_MBBUSY0_BUSY20_Pos 20 /**< \brief (DSU_MBBUSY0) Memory 20 BIST Busy */
+#define DSU_MBBUSY0_BUSY20 (_U_(1) << DSU_MBBUSY0_BUSY20_Pos)
+#define DSU_MBBUSY0_BUSY21_Pos 21 /**< \brief (DSU_MBBUSY0) Memory 21 BIST Busy */
+#define DSU_MBBUSY0_BUSY21 (_U_(1) << DSU_MBBUSY0_BUSY21_Pos)
+#define DSU_MBBUSY0_BUSY22_Pos 22 /**< \brief (DSU_MBBUSY0) Memory 22 BIST Busy */
+#define DSU_MBBUSY0_BUSY22 (_U_(1) << DSU_MBBUSY0_BUSY22_Pos)
+#define DSU_MBBUSY0_BUSY23_Pos 23 /**< \brief (DSU_MBBUSY0) Memory 23 BIST Busy */
+#define DSU_MBBUSY0_BUSY23 (_U_(1) << DSU_MBBUSY0_BUSY23_Pos)
+#define DSU_MBBUSY0_BUSY24_Pos 24 /**< \brief (DSU_MBBUSY0) Memory 24 BIST Busy */
+#define DSU_MBBUSY0_BUSY24 (_U_(1) << DSU_MBBUSY0_BUSY24_Pos)
+#define DSU_MBBUSY0_BUSY25_Pos 25 /**< \brief (DSU_MBBUSY0) Memory 25 BIST Busy */
+#define DSU_MBBUSY0_BUSY25 (_U_(1) << DSU_MBBUSY0_BUSY25_Pos)
+#define DSU_MBBUSY0_BUSY26_Pos 26 /**< \brief (DSU_MBBUSY0) Memory 26 BIST Busy */
+#define DSU_MBBUSY0_BUSY26 (_U_(1) << DSU_MBBUSY0_BUSY26_Pos)
+#define DSU_MBBUSY0_BUSY27_Pos 27 /**< \brief (DSU_MBBUSY0) Memory 27 BIST Busy */
+#define DSU_MBBUSY0_BUSY27 (_U_(1) << DSU_MBBUSY0_BUSY27_Pos)
+#define DSU_MBBUSY0_BUSY28_Pos 28 /**< \brief (DSU_MBBUSY0) Memory 28 BIST Busy */
+#define DSU_MBBUSY0_BUSY28 (_U_(1) << DSU_MBBUSY0_BUSY28_Pos)
+#define DSU_MBBUSY0_BUSY_Pos 0 /**< \brief (DSU_MBBUSY0) Memory x BIST Busy */
+#define DSU_MBBUSY0_BUSY_Msk (_U_(0x1FFFFFFF) << DSU_MBBUSY0_BUSY_Pos)
+#define DSU_MBBUSY0_BUSY(value) (DSU_MBBUSY0_BUSY_Msk & ((value) << DSU_MBBUSY0_BUSY_Pos))
+#define DSU_MBBUSY0_MASK _U_(0x1FFFFFFF) /**< \brief (DSU_MBBUSY0) MASK Register */
+
+/* -------- DSU_MBSTATUS0 : (DSU Offset: 0x0070) (R/W 32) MBIST Memory Status 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t STATUS0:1; /*!< bit: 0 Memory 0 MBIST Status */
+ uint32_t STATUS1:1; /*!< bit: 1 Memory 1 MBIST Status */
+ uint32_t STATUS2:1; /*!< bit: 2 Memory 2 MBIST Status */
+ uint32_t STATUS3:1; /*!< bit: 3 Memory 3 MBIST Status */
+ uint32_t STATUS4:1; /*!< bit: 4 Memory 4 MBIST Status */
+ uint32_t STATUS5:1; /*!< bit: 5 Memory 5 MBIST Status */
+ uint32_t STATUS6:1; /*!< bit: 6 Memory 6 MBIST Status */
+ uint32_t STATUS7:1; /*!< bit: 7 Memory 7 MBIST Status */
+ uint32_t STATUS8:1; /*!< bit: 8 Memory 8 MBIST Status */
+ uint32_t STATUS9:1; /*!< bit: 9 Memory 9 MBIST Status */
+ uint32_t STATUS10:1; /*!< bit: 10 Memory 10 MBIST Status */
+ uint32_t STATUS11:1; /*!< bit: 11 Memory 11 MBIST Status */
+ uint32_t STATUS12:1; /*!< bit: 12 Memory 12 MBIST Status */
+ uint32_t STATUS13:1; /*!< bit: 13 Memory 13 MBIST Status */
+ uint32_t STATUS14:1; /*!< bit: 14 Memory 14 MBIST Status */
+ uint32_t STATUS15:1; /*!< bit: 15 Memory 15 MBIST Status */
+ uint32_t STATUS16:1; /*!< bit: 16 Memory 16 MBIST Status */
+ uint32_t STATUS17:1; /*!< bit: 17 Memory 17 MBIST Status */
+ uint32_t STATUS18:1; /*!< bit: 18 Memory 18 MBIST Status */
+ uint32_t STATUS19:1; /*!< bit: 19 Memory 19 MBIST Status */
+ uint32_t STATUS20:1; /*!< bit: 20 Memory 20 MBIST Status */
+ uint32_t STATUS21:1; /*!< bit: 21 Memory 21 MBIST Status */
+ uint32_t STATUS22:1; /*!< bit: 22 Memory 22 MBIST Status */
+ uint32_t STATUS23:1; /*!< bit: 23 Memory 23 MBIST Status */
+ uint32_t STATUS24:1; /*!< bit: 24 Memory 24 MBIST Status */
+ uint32_t STATUS25:1; /*!< bit: 25 Memory 25 MBIST Status */
+ uint32_t STATUS26:1; /*!< bit: 26 Memory 26 MBIST Status */
+ uint32_t STATUS27:1; /*!< bit: 27 Memory 27 MBIST Status */
+ uint32_t STATUS28:1; /*!< bit: 28 Memory 28 MBIST Status */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t STATUS:29; /*!< bit: 0..28 Memory x MBIST Status */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MBSTATUS0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MBSTATUS0_OFFSET 0x0070 /**< \brief (DSU_MBSTATUS0 offset) MBIST Memory Status 0 */
+#define DSU_MBSTATUS0_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBSTATUS0 reset_value) MBIST Memory Status 0 */
+
+#define DSU_MBSTATUS0_STATUS0_Pos 0 /**< \brief (DSU_MBSTATUS0) Memory 0 MBIST Status */
+#define DSU_MBSTATUS0_STATUS0 (_U_(1) << DSU_MBSTATUS0_STATUS0_Pos)
+#define DSU_MBSTATUS0_STATUS1_Pos 1 /**< \brief (DSU_MBSTATUS0) Memory 1 MBIST Status */
+#define DSU_MBSTATUS0_STATUS1 (_U_(1) << DSU_MBSTATUS0_STATUS1_Pos)
+#define DSU_MBSTATUS0_STATUS2_Pos 2 /**< \brief (DSU_MBSTATUS0) Memory 2 MBIST Status */
+#define DSU_MBSTATUS0_STATUS2 (_U_(1) << DSU_MBSTATUS0_STATUS2_Pos)
+#define DSU_MBSTATUS0_STATUS3_Pos 3 /**< \brief (DSU_MBSTATUS0) Memory 3 MBIST Status */
+#define DSU_MBSTATUS0_STATUS3 (_U_(1) << DSU_MBSTATUS0_STATUS3_Pos)
+#define DSU_MBSTATUS0_STATUS4_Pos 4 /**< \brief (DSU_MBSTATUS0) Memory 4 MBIST Status */
+#define DSU_MBSTATUS0_STATUS4 (_U_(1) << DSU_MBSTATUS0_STATUS4_Pos)
+#define DSU_MBSTATUS0_STATUS5_Pos 5 /**< \brief (DSU_MBSTATUS0) Memory 5 MBIST Status */
+#define DSU_MBSTATUS0_STATUS5 (_U_(1) << DSU_MBSTATUS0_STATUS5_Pos)
+#define DSU_MBSTATUS0_STATUS6_Pos 6 /**< \brief (DSU_MBSTATUS0) Memory 6 MBIST Status */
+#define DSU_MBSTATUS0_STATUS6 (_U_(1) << DSU_MBSTATUS0_STATUS6_Pos)
+#define DSU_MBSTATUS0_STATUS7_Pos 7 /**< \brief (DSU_MBSTATUS0) Memory 7 MBIST Status */
+#define DSU_MBSTATUS0_STATUS7 (_U_(1) << DSU_MBSTATUS0_STATUS7_Pos)
+#define DSU_MBSTATUS0_STATUS8_Pos 8 /**< \brief (DSU_MBSTATUS0) Memory 8 MBIST Status */
+#define DSU_MBSTATUS0_STATUS8 (_U_(1) << DSU_MBSTATUS0_STATUS8_Pos)
+#define DSU_MBSTATUS0_STATUS9_Pos 9 /**< \brief (DSU_MBSTATUS0) Memory 9 MBIST Status */
+#define DSU_MBSTATUS0_STATUS9 (_U_(1) << DSU_MBSTATUS0_STATUS9_Pos)
+#define DSU_MBSTATUS0_STATUS10_Pos 10 /**< \brief (DSU_MBSTATUS0) Memory 10 MBIST Status */
+#define DSU_MBSTATUS0_STATUS10 (_U_(1) << DSU_MBSTATUS0_STATUS10_Pos)
+#define DSU_MBSTATUS0_STATUS11_Pos 11 /**< \brief (DSU_MBSTATUS0) Memory 11 MBIST Status */
+#define DSU_MBSTATUS0_STATUS11 (_U_(1) << DSU_MBSTATUS0_STATUS11_Pos)
+#define DSU_MBSTATUS0_STATUS12_Pos 12 /**< \brief (DSU_MBSTATUS0) Memory 12 MBIST Status */
+#define DSU_MBSTATUS0_STATUS12 (_U_(1) << DSU_MBSTATUS0_STATUS12_Pos)
+#define DSU_MBSTATUS0_STATUS13_Pos 13 /**< \brief (DSU_MBSTATUS0) Memory 13 MBIST Status */
+#define DSU_MBSTATUS0_STATUS13 (_U_(1) << DSU_MBSTATUS0_STATUS13_Pos)
+#define DSU_MBSTATUS0_STATUS14_Pos 14 /**< \brief (DSU_MBSTATUS0) Memory 14 MBIST Status */
+#define DSU_MBSTATUS0_STATUS14 (_U_(1) << DSU_MBSTATUS0_STATUS14_Pos)
+#define DSU_MBSTATUS0_STATUS15_Pos 15 /**< \brief (DSU_MBSTATUS0) Memory 15 MBIST Status */
+#define DSU_MBSTATUS0_STATUS15 (_U_(1) << DSU_MBSTATUS0_STATUS15_Pos)
+#define DSU_MBSTATUS0_STATUS16_Pos 16 /**< \brief (DSU_MBSTATUS0) Memory 16 MBIST Status */
+#define DSU_MBSTATUS0_STATUS16 (_U_(1) << DSU_MBSTATUS0_STATUS16_Pos)
+#define DSU_MBSTATUS0_STATUS17_Pos 17 /**< \brief (DSU_MBSTATUS0) Memory 17 MBIST Status */
+#define DSU_MBSTATUS0_STATUS17 (_U_(1) << DSU_MBSTATUS0_STATUS17_Pos)
+#define DSU_MBSTATUS0_STATUS18_Pos 18 /**< \brief (DSU_MBSTATUS0) Memory 18 MBIST Status */
+#define DSU_MBSTATUS0_STATUS18 (_U_(1) << DSU_MBSTATUS0_STATUS18_Pos)
+#define DSU_MBSTATUS0_STATUS19_Pos 19 /**< \brief (DSU_MBSTATUS0) Memory 19 MBIST Status */
+#define DSU_MBSTATUS0_STATUS19 (_U_(1) << DSU_MBSTATUS0_STATUS19_Pos)
+#define DSU_MBSTATUS0_STATUS20_Pos 20 /**< \brief (DSU_MBSTATUS0) Memory 20 MBIST Status */
+#define DSU_MBSTATUS0_STATUS20 (_U_(1) << DSU_MBSTATUS0_STATUS20_Pos)
+#define DSU_MBSTATUS0_STATUS21_Pos 21 /**< \brief (DSU_MBSTATUS0) Memory 21 MBIST Status */
+#define DSU_MBSTATUS0_STATUS21 (_U_(1) << DSU_MBSTATUS0_STATUS21_Pos)
+#define DSU_MBSTATUS0_STATUS22_Pos 22 /**< \brief (DSU_MBSTATUS0) Memory 22 MBIST Status */
+#define DSU_MBSTATUS0_STATUS22 (_U_(1) << DSU_MBSTATUS0_STATUS22_Pos)
+#define DSU_MBSTATUS0_STATUS23_Pos 23 /**< \brief (DSU_MBSTATUS0) Memory 23 MBIST Status */
+#define DSU_MBSTATUS0_STATUS23 (_U_(1) << DSU_MBSTATUS0_STATUS23_Pos)
+#define DSU_MBSTATUS0_STATUS24_Pos 24 /**< \brief (DSU_MBSTATUS0) Memory 24 MBIST Status */
+#define DSU_MBSTATUS0_STATUS24 (_U_(1) << DSU_MBSTATUS0_STATUS24_Pos)
+#define DSU_MBSTATUS0_STATUS25_Pos 25 /**< \brief (DSU_MBSTATUS0) Memory 25 MBIST Status */
+#define DSU_MBSTATUS0_STATUS25 (_U_(1) << DSU_MBSTATUS0_STATUS25_Pos)
+#define DSU_MBSTATUS0_STATUS26_Pos 26 /**< \brief (DSU_MBSTATUS0) Memory 26 MBIST Status */
+#define DSU_MBSTATUS0_STATUS26 (_U_(1) << DSU_MBSTATUS0_STATUS26_Pos)
+#define DSU_MBSTATUS0_STATUS27_Pos 27 /**< \brief (DSU_MBSTATUS0) Memory 27 MBIST Status */
+#define DSU_MBSTATUS0_STATUS27 (_U_(1) << DSU_MBSTATUS0_STATUS27_Pos)
+#define DSU_MBSTATUS0_STATUS28_Pos 28 /**< \brief (DSU_MBSTATUS0) Memory 28 MBIST Status */
+#define DSU_MBSTATUS0_STATUS28 (_U_(1) << DSU_MBSTATUS0_STATUS28_Pos)
+#define DSU_MBSTATUS0_STATUS_Pos 0 /**< \brief (DSU_MBSTATUS0) Memory x MBIST Status */
+#define DSU_MBSTATUS0_STATUS_Msk (_U_(0x1FFFFFFF) << DSU_MBSTATUS0_STATUS_Pos)
+#define DSU_MBSTATUS0_STATUS(value) (DSU_MBSTATUS0_STATUS_Msk & ((value) << DSU_MBSTATUS0_STATUS_Pos))
+#define DSU_MBSTATUS0_MASK _U_(0x1FFFFFFF) /**< \brief (DSU_MBSTATUS0) MASK Register */
+
+/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */
+#define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */
+
+#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */
+#define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos)
+#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
+#define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */
+
+/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ENTRY0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY0_OFFSET 0x1000 /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */
+#define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */
+
+#define DSU_ENTRY0_EPRES_Pos 0 /**< \brief (DSU_ENTRY0) Entry Present */
+#define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
+#define DSU_ENTRY0_FMT_Pos 1 /**< \brief (DSU_ENTRY0) Format */
+#define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
+#define DSU_ENTRY0_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY0) Address Offset */
+#define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
+#define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
+#define DSU_ENTRY0_MASK _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */
+
+/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/ 32) CoreSight ROM Table Entry 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ENTRY1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY1_OFFSET 0x1004 /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */
+#define DSU_ENTRY1_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */
+#define DSU_ENTRY1_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) CoreSight ROM Table End */
+#define DSU_END_RESETVALUE _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */
+
+#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
+#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */
+#define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
+#define DSU_PID5_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */
+#define DSU_PID5_MASK _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */
+
+/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
+#define DSU_PID6_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */
+#define DSU_PID6_MASK _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */
+
+/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
+#define DSU_PID7_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */
+#define DSU_PID7_MASK _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ __IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */
+ RoReg8 Reserved2[0x20];
+ __IO DSU_MBCTRL_Type MBCTRL; /**< \brief Offset: 0x0040 (R/W 32) MBIST Control */
+ __IO DSU_MBCONFIG_Type MBCONFIG; /**< \brief Offset: 0x0044 (R/W 32) MBIST Configuration */
+ __IO DSU_MBWORD_Type MBWORD; /**< \brief Offset: 0x0048 (R/W 32) MBIST Background Word */
+ __IO DSU_MBGSTAT_Type MBGSTAT; /**< \brief Offset: 0x004C (R/W 32) MBIST Global Status */
+ __I DSU_MBDFAIL_Type MBDFAIL; /**< \brief Offset: 0x0050 (R/ 32) MBIST Fail Data */
+ __I DSU_MBDEXP_Type MBDEXP; /**< \brief Offset: 0x0054 (R/ 32) MBIST Expected Data */
+ __I DSU_MBAFAIL_Type MBAFAIL; /**< \brief Offset: 0x0058 (R/ 32) MBIST Fail Address */
+ __I DSU_MBCONTEXT_Type MBCONTEXT; /**< \brief Offset: 0x005C (R/ 32) MBIST Fail Context */
+ __IO DSU_MBENABLE0_Type MBENABLE0; /**< \brief Offset: 0x0060 (R/W 32) MBIST Memory Enable 0 */
+ RoReg8 Reserved3[0x4];
+ __I DSU_MBBUSY0_Type MBBUSY0; /**< \brief Offset: 0x0068 (R/ 32) MBIST Memory Busy 0 */
+ RoReg8 Reserved4[0x4];
+ __IO DSU_MBSTATUS0_Type MBSTATUS0; /**< \brief Offset: 0x0070 (R/W 32) MBIST Memory Status 0 */
+ RoReg8 Reserved5[0x7C];
+ __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
+ RoReg8 Reserved6[0xF08];
+ __I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */
+ __I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */
+ RoReg8 Reserved7[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */
+ __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */
+ __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_DSU_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/eic.h b/GPIO/ATSAME54/include/component/eic.h
new file mode 100644
index 0000000..61ad254
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/eic.h
@@ -0,0 +1,497 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_EIC_COMPONENT_
+#define _SAME54_EIC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAME54_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2254
+#define REV_EIC 0x300
+
+/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control A */
+#define EIC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRLA reset_value) Control A */
+
+#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */
+#define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
+#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */
+#define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
+#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */
+#define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
+#define EIC_CTRLA_MASK _U_(0x13) /**< \brief (EIC_CTRLA) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense Configuration */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t NMIASYNCH:1; /*!< bit: 4 Asynchronous Edge Detection Mode */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
+#define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */
+#define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High-level detection */
+#define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
+#define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
+#define EIC_NMICTRL_MASK _U_(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint16_t :15; /*!< bit: 1..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE _U_(0x0000) /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK _U_(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy Status */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy Status */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
+#define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
+#define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
+#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
+#define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
+#define EIC_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Enable */
+#define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Enable */
+#define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt */
+#define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ASYNCH:16; /*!< bit: 0..15 Asynchronous Edge Detection Mode */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_ASYNCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
+#define EIC_ASYNCH_RESETVALUE _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
+
+#define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
+#define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
+#define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
+#define EIC_ASYNCH_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
+#define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
+
+#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
+#define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */
+#define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
+#define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */
+#define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
+#define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */
+#define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
+#define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */
+#define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
+#define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */
+#define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
+#define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */
+#define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
+#define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */
+#define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
+#define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */
+#define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
+
+/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEBOUNCEN:16; /*!< bit: 0..15 Debouncer Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_DEBOUNCEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_DEBOUNCEN_OFFSET 0x30 /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
+#define EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
+
+#define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0 /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
+#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
+#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
+#define EIC_DEBOUNCEN_MASK _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
+
+/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PRESCALER0:3; /*!< bit: 0.. 2 Debouncer Prescaler */
+ uint32_t STATES0:1; /*!< bit: 3 Debouncer number of states */
+ uint32_t PRESCALER1:3; /*!< bit: 4.. 6 Debouncer Prescaler */
+ uint32_t STATES1:1; /*!< bit: 7 Debouncer number of states */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t TICKON:1; /*!< bit: 16 Pin Sampler frequency selection */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_DPRESCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_DPRESCALER_OFFSET 0x34 /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
+#define EIC_DPRESCALER_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
+
+#define EIC_DPRESCALER_PRESCALER0_Pos 0 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
+#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
+#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
+#define EIC_DPRESCALER_STATES0_Pos 3 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
+#define EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
+#define EIC_DPRESCALER_PRESCALER1_Pos 4 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
+#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
+#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
+#define EIC_DPRESCALER_STATES1_Pos 7 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
+#define EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
+#define EIC_DPRESCALER_TICKON_Pos 16 /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
+#define EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
+#define EIC_DPRESCALER_MASK _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
+
+/* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/ 32) Pin State -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINSTATE:16; /*!< bit: 0..15 Pin State */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_PINSTATE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_PINSTATE_OFFSET 0x38 /**< \brief (EIC_PINSTATE offset) Pin State */
+#define EIC_PINSTATE_RESETVALUE _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
+
+#define EIC_PINSTATE_PINSTATE_Pos 0 /**< \brief (EIC_PINSTATE) Pin State */
+#define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
+#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
+#define EIC_PINSTATE_MASK _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
+ __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
+ RoReg8 Reserved1[0xC];
+ __IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
+ __IO EIC_DPRESCALER_Type DPRESCALER; /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
+ __I EIC_PINSTATE_Type PINSTATE; /**< \brief Offset: 0x38 (R/ 32) Pin State */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_EIC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/evsys.h b/GPIO/ATSAME54/include/component/evsys.h
new file mode 100644
index 0000000..0fc836f
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/evsys.h
@@ -0,0 +1,587 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_EVSYS_COMPONENT_
+#define _SAME54_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAME54_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2504
+#define REV_EVSYS 0x100
+
+/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRLA_OFFSET 0x000 /**< \brief (EVSYS_CTRLA offset) Control */
+#define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */
+
+#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */
+#define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
+#define EVSYS_CTRLA_MASK _U_(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */
+
+/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */
+ uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */
+ uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */
+ uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */
+ uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */
+ uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */
+ uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */
+ uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */
+ uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */
+ uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */
+ uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */
+ uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */
+ uint32_t CHANNEL12:1; /*!< bit: 12 Channel 12 Software Selection */
+ uint32_t CHANNEL13:1; /*!< bit: 13 Channel 13 Software Selection */
+ uint32_t CHANNEL14:1; /*!< bit: 14 Channel 14 Software Selection */
+ uint32_t CHANNEL15:1; /*!< bit: 15 Channel 15 Software Selection */
+ uint32_t CHANNEL16:1; /*!< bit: 16 Channel 16 Software Selection */
+ uint32_t CHANNEL17:1; /*!< bit: 17 Channel 17 Software Selection */
+ uint32_t CHANNEL18:1; /*!< bit: 18 Channel 18 Software Selection */
+ uint32_t CHANNEL19:1; /*!< bit: 19 Channel 19 Software Selection */
+ uint32_t CHANNEL20:1; /*!< bit: 20 Channel 20 Software Selection */
+ uint32_t CHANNEL21:1; /*!< bit: 21 Channel 21 Software Selection */
+ uint32_t CHANNEL22:1; /*!< bit: 22 Channel 22 Software Selection */
+ uint32_t CHANNEL23:1; /*!< bit: 23 Channel 23 Software Selection */
+ uint32_t CHANNEL24:1; /*!< bit: 24 Channel 24 Software Selection */
+ uint32_t CHANNEL25:1; /*!< bit: 25 Channel 25 Software Selection */
+ uint32_t CHANNEL26:1; /*!< bit: 26 Channel 26 Software Selection */
+ uint32_t CHANNEL27:1; /*!< bit: 27 Channel 27 Software Selection */
+ uint32_t CHANNEL28:1; /*!< bit: 28 Channel 28 Software Selection */
+ uint32_t CHANNEL29:1; /*!< bit: 29 Channel 29 Software Selection */
+ uint32_t CHANNEL30:1; /*!< bit: 30 Channel 30 Software Selection */
+ uint32_t CHANNEL31:1; /*!< bit: 31 Channel 31 Software Selection */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHANNEL:32; /*!< bit: 0..31 Channel x Software Selection */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_SWEVT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_SWEVT_OFFSET 0x004 /**< \brief (EVSYS_SWEVT offset) Software Event */
+#define EVSYS_SWEVT_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
+
+#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
+#define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
+#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
+#define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
+#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
+#define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
+#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
+#define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
+#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
+#define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
+#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
+#define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
+#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
+#define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
+#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
+#define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
+#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
+#define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
+#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
+#define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
+#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
+#define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
+#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
+#define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
+#define EVSYS_SWEVT_CHANNEL12_Pos 12 /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
+#define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
+#define EVSYS_SWEVT_CHANNEL13_Pos 13 /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
+#define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
+#define EVSYS_SWEVT_CHANNEL14_Pos 14 /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
+#define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
+#define EVSYS_SWEVT_CHANNEL15_Pos 15 /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
+#define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
+#define EVSYS_SWEVT_CHANNEL16_Pos 16 /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
+#define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
+#define EVSYS_SWEVT_CHANNEL17_Pos 17 /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
+#define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
+#define EVSYS_SWEVT_CHANNEL18_Pos 18 /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
+#define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
+#define EVSYS_SWEVT_CHANNEL19_Pos 19 /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
+#define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
+#define EVSYS_SWEVT_CHANNEL20_Pos 20 /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
+#define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
+#define EVSYS_SWEVT_CHANNEL21_Pos 21 /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
+#define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
+#define EVSYS_SWEVT_CHANNEL22_Pos 22 /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
+#define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
+#define EVSYS_SWEVT_CHANNEL23_Pos 23 /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
+#define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
+#define EVSYS_SWEVT_CHANNEL24_Pos 24 /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
+#define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
+#define EVSYS_SWEVT_CHANNEL25_Pos 25 /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
+#define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
+#define EVSYS_SWEVT_CHANNEL26_Pos 26 /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
+#define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
+#define EVSYS_SWEVT_CHANNEL27_Pos 27 /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
+#define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
+#define EVSYS_SWEVT_CHANNEL28_Pos 28 /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
+#define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
+#define EVSYS_SWEVT_CHANNEL29_Pos 29 /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
+#define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
+#define EVSYS_SWEVT_CHANNEL30_Pos 30 /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
+#define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
+#define EVSYS_SWEVT_CHANNEL31_Pos 31 /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
+#define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
+#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
+#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
+#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
+#define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
+
+/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W 8) Priority Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRI:4; /*!< bit: 0.. 3 Channel Priority Number */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t RREN:1; /*!< bit: 7 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_PRICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_PRICTRL_OFFSET 0x008 /**< \brief (EVSYS_PRICTRL offset) Priority Control */
+#define EVSYS_PRICTRL_RESETVALUE _U_(0x00) /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
+
+#define EVSYS_PRICTRL_PRI_Pos 0 /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
+#define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
+#define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
+#define EVSYS_PRICTRL_RREN_Pos 7 /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
+#define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
+#define EVSYS_PRICTRL_MASK _U_(0x8F) /**< \brief (EVSYS_PRICTRL) MASK Register */
+
+/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t OVR:1; /*!< bit: 8 Channel Overrun */
+ uint16_t EVD:1; /*!< bit: 9 Channel Event Detected */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t READY:1; /*!< bit: 14 Ready */
+ uint16_t BUSY:1; /*!< bit: 15 Busy */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EVSYS_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTPEND_OFFSET 0x010 /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
+#define EVSYS_INTPEND_RESETVALUE _U_(0x4000) /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
+
+#define EVSYS_INTPEND_ID_Pos 0 /**< \brief (EVSYS_INTPEND) Channel ID */
+#define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
+#define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
+#define EVSYS_INTPEND_OVR_Pos 8 /**< \brief (EVSYS_INTPEND) Channel Overrun */
+#define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
+#define EVSYS_INTPEND_EVD_Pos 9 /**< \brief (EVSYS_INTPEND) Channel Event Detected */
+#define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
+#define EVSYS_INTPEND_READY_Pos 14 /**< \brief (EVSYS_INTPEND) Ready */
+#define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
+#define EVSYS_INTPEND_BUSY_Pos 15 /**< \brief (EVSYS_INTPEND) Busy */
+#define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
+#define EVSYS_INTPEND_MASK _U_(0xC30F) /**< \brief (EVSYS_INTPEND) MASK Register */
+
+/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTSTATUS_OFFSET 0x014 /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
+#define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
+
+#define EVSYS_INTSTATUS_CHINT0_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
+#define EVSYS_INTSTATUS_CHINT1_Pos 1 /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
+#define EVSYS_INTSTATUS_CHINT2_Pos 2 /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
+#define EVSYS_INTSTATUS_CHINT3_Pos 3 /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
+#define EVSYS_INTSTATUS_CHINT4_Pos 4 /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
+#define EVSYS_INTSTATUS_CHINT5_Pos 5 /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
+#define EVSYS_INTSTATUS_CHINT6_Pos 6 /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
+#define EVSYS_INTSTATUS_CHINT7_Pos 7 /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
+#define EVSYS_INTSTATUS_CHINT8_Pos 8 /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
+#define EVSYS_INTSTATUS_CHINT9_Pos 9 /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
+#define EVSYS_INTSTATUS_CHINT10_Pos 10 /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
+#define EVSYS_INTSTATUS_CHINT11_Pos 11 /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
+#define EVSYS_INTSTATUS_CHINT_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
+#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
+#define EVSYS_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
+
+/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_BUSYCH_OFFSET 0x018 /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
+#define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
+
+#define EVSYS_BUSYCH_BUSYCH0_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
+#define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
+#define EVSYS_BUSYCH_BUSYCH1_Pos 1 /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
+#define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
+#define EVSYS_BUSYCH_BUSYCH2_Pos 2 /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
+#define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
+#define EVSYS_BUSYCH_BUSYCH3_Pos 3 /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
+#define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
+#define EVSYS_BUSYCH_BUSYCH4_Pos 4 /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
+#define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
+#define EVSYS_BUSYCH_BUSYCH5_Pos 5 /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
+#define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
+#define EVSYS_BUSYCH_BUSYCH6_Pos 6 /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
+#define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
+#define EVSYS_BUSYCH_BUSYCH7_Pos 7 /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
+#define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
+#define EVSYS_BUSYCH_BUSYCH8_Pos 8 /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
+#define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
+#define EVSYS_BUSYCH_BUSYCH9_Pos 9 /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
+#define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
+#define EVSYS_BUSYCH_BUSYCH10_Pos 10 /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
+#define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
+#define EVSYS_BUSYCH_BUSYCH11_Pos 11 /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
+#define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
+#define EVSYS_BUSYCH_BUSYCH_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel x */
+#define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
+#define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
+#define EVSYS_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
+
+/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/ 32) Ready Users -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t READYUSR0:1; /*!< bit: 0 Ready User for Channel 0 */
+ uint32_t READYUSR1:1; /*!< bit: 1 Ready User for Channel 1 */
+ uint32_t READYUSR2:1; /*!< bit: 2 Ready User for Channel 2 */
+ uint32_t READYUSR3:1; /*!< bit: 3 Ready User for Channel 3 */
+ uint32_t READYUSR4:1; /*!< bit: 4 Ready User for Channel 4 */
+ uint32_t READYUSR5:1; /*!< bit: 5 Ready User for Channel 5 */
+ uint32_t READYUSR6:1; /*!< bit: 6 Ready User for Channel 6 */
+ uint32_t READYUSR7:1; /*!< bit: 7 Ready User for Channel 7 */
+ uint32_t READYUSR8:1; /*!< bit: 8 Ready User for Channel 8 */
+ uint32_t READYUSR9:1; /*!< bit: 9 Ready User for Channel 9 */
+ uint32_t READYUSR10:1; /*!< bit: 10 Ready User for Channel 10 */
+ uint32_t READYUSR11:1; /*!< bit: 11 Ready User for Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t READYUSR:12; /*!< bit: 0..11 Ready User for Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_READYUSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_READYUSR_OFFSET 0x01C /**< \brief (EVSYS_READYUSR offset) Ready Users */
+#define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
+
+#define EVSYS_READYUSR_READYUSR0_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
+#define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
+#define EVSYS_READYUSR_READYUSR1_Pos 1 /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
+#define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
+#define EVSYS_READYUSR_READYUSR2_Pos 2 /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
+#define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
+#define EVSYS_READYUSR_READYUSR3_Pos 3 /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
+#define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
+#define EVSYS_READYUSR_READYUSR4_Pos 4 /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
+#define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
+#define EVSYS_READYUSR_READYUSR5_Pos 5 /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
+#define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
+#define EVSYS_READYUSR_READYUSR6_Pos 6 /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
+#define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
+#define EVSYS_READYUSR_READYUSR7_Pos 7 /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
+#define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
+#define EVSYS_READYUSR_READYUSR8_Pos 8 /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
+#define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
+#define EVSYS_READYUSR_READYUSR9_Pos 9 /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
+#define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
+#define EVSYS_READYUSR_READYUSR10_Pos 10 /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
+#define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
+#define EVSYS_READYUSR_READYUSR11_Pos 11 /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
+#define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
+#define EVSYS_READYUSR_READYUSR_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
+#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
+#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
+#define EVSYS_READYUSR_MASK _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */
+ uint32_t :2; /*!< bit: 12..13 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */
+ uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET 0x020 /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
+#define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
+
+#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */
+#define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
+#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
+#define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
+#define EVSYS_CHANNEL_MASK _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Disable */
+ uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTENCLR_OFFSET 0x024 /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
+#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
+
+#define EVSYS_CHINTENCLR_OVR_Pos 0 /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
+#define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
+#define EVSYS_CHINTENCLR_EVD_Pos 1 /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
+#define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
+#define EVSYS_CHINTENCLR_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENCLR) MASK Register */
+
+/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Enable */
+ uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTENSET_OFFSET 0x025 /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
+#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
+
+#define EVSYS_CHINTENSET_OVR_Pos 0 /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
+#define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
+#define EVSYS_CHINTENSET_EVD_Pos 1 /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
+#define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
+#define EVSYS_CHINTENSET_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENSET) MASK Register */
+
+/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVR:1; /*!< bit: 0 Channel Overrun */
+ __I uint8_t EVD:1; /*!< bit: 1 Channel Event Detected */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTFLAG_OFFSET 0x026 /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
+#define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
+
+#define EVSYS_CHINTFLAG_OVR_Pos 0 /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
+#define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
+#define EVSYS_CHINTFLAG_EVD_Pos 1 /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
+#define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
+#define EVSYS_CHINTFLAG_MASK _U_(0x03) /**< \brief (EVSYS_CHINTFLAG) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/ 8) CHANNEL Channel n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RDYUSR:1; /*!< bit: 0 Ready User */
+ uint8_t BUSYCH:1; /*!< bit: 1 Busy Channel */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET 0x027 /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
+#define EVSYS_CHSTATUS_RESETVALUE _U_(0x01) /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
+
+#define EVSYS_CHSTATUS_RDYUSR_Pos 0 /**< \brief (EVSYS_CHSTATUS) Ready User */
+#define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
+#define EVSYS_CHSTATUS_BUSYCH_Pos 1 /**< \brief (EVSYS_CHSTATUS) Busy Channel */
+#define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
+#define EVSYS_CHSTATUS_MASK _U_(0x03) /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL:6; /*!< bit: 0.. 5 Channel Event Selection */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET 0x120 /**< \brief (EVSYS_USER offset) User Multiplexer n */
+#define EVSYS_USER_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
+
+#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define EVSYS_USER_MASK _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
+
+/** \brief EvsysChannel hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
+ __IO EVSYS_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear */
+ __IO EVSYS_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set */
+ __IO EVSYS_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear */
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x007 (R/ 8) Channel n Status */
+} EvsysChannel;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x004 ( /W 32) Software Event */
+ __IO EVSYS_PRICTRL_Type PRICTRL; /**< \brief Offset: 0x008 (R/W 8) Priority Control */
+ RoReg8 Reserved2[0x7];
+ __IO EVSYS_INTPEND_Type INTPEND; /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
+ RoReg8 Reserved3[0x2];
+ __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */
+ __I EVSYS_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x018 (R/ 32) Busy Channels */
+ __I EVSYS_READYUSR_Type READYUSR; /**< \brief Offset: 0x01C (R/ 32) Ready Users */
+ EvsysChannel Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
+ __IO EVSYS_USER_Type USER[67]; /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_EVSYS_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/freqm.h b/GPIO/ATSAME54/include/component/freqm.h
new file mode 100644
index 0000000..09a6408
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/freqm.h
@@ -0,0 +1,233 @@
+/**
+ * \file
+ *
+ * \brief Component description for FREQM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_FREQM_COMPONENT_
+#define _SAME54_FREQM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR FREQM */
+/* ========================================================================== */
+/** \addtogroup SAME54_FREQM Frequency Meter */
+/*@{*/
+
+#define FREQM_U2257
+#define REV_FREQM 0x110
+
+/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
+#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
+
+#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
+#define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
+#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
+#define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
+#define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
+
+/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START:1; /*!< bit: 0 Start Measurement */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
+#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
+
+#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
+#define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
+#define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
+
+/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} FREQM_CFGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
+#define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
+
+#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
+#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
+#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
+#define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
+
+/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
+#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
+
+#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
+#define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
+#define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
+
+/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
+#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
+
+#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
+#define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
+#define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
+
+/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
+#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
+
+#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
+#define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
+#define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
+
+/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
+ uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} FREQM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
+#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
+
+#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
+#define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
+#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
+#define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
+#define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
+
+/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} FREQM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
+#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
+
+#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
+#define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
+#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
+#define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
+#define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
+
+/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} FREQM_VALUE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
+#define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
+
+#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
+#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
+#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
+#define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
+
+/** \brief FREQM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
+ __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
+ __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
+ RoReg8 Reserved1[0x4];
+ __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
+ __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
+ __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
+ __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
+ __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
+ __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
+} Freqm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_FREQM_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/gclk.h b/GPIO/ATSAME54/include/component/gclk.h
new file mode 100644
index 0000000..fb4be84
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/gclk.h
@@ -0,0 +1,272 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_GCLK_COMPONENT_
+#define _SAME54_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAME54_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2122
+#define REV_GCLK 0x120
+
+/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
+#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */
+
+#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
+#define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
+#define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */
+
+/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */
+ uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */
+ uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */
+ uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */
+ uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */
+ uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */
+ uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */
+ uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */
+ uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */
+ uint32_t GENCTRL9:1; /*!< bit: 11 Generic Clock Generator Control 9 Synchronization Busy bits */
+ uint32_t GENCTRL10:1; /*!< bit: 12 Generic Clock Generator Control 10 Synchronization Busy bits */
+ uint32_t GENCTRL11:1; /*!< bit: 13 Generic Clock Generator Control 11 Synchronization Busy bits */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Busy bits */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
+#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
+
+#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
+#define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
+#define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
+#define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
+#define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
+#define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
+#define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
+#define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
+#define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
+#define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
+#define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
+#define GCLK_SYNCBUSY_GENCTRL9_Pos 11 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
+#define GCLK_SYNCBUSY_GENCTRL10_Pos 12 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
+#define GCLK_SYNCBUSY_GENCTRL11_Pos 13 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_MASK _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 10 Output Off Value */
+ uint32_t OE:1; /*!< bit: 11 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
+#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) DFLL output */
+#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL0 output */
+#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL1 output */
+#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
+#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
+#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
+#define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
+ uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_PCHCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
+#define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
+
+#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
+#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
+#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
+#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
+#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
+#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
+#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
+#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
+#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
+#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
+#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
+#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
+#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
+#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
+#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
+#define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
+#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
+#define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
+#define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
+ RoReg8 Reserved2[0x18];
+ __IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
+ RoReg8 Reserved3[0x30];
+ __IO GCLK_PCHCTRL_Type PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_GCLK_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/gmac.h b/GPIO/ATSAME54/include/component/gmac.h
new file mode 100644
index 0000000..5d01b51
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/gmac.h
@@ -0,0 +1,2593 @@
+/**
+ * \file
+ *
+ * \brief Component description for GMAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_GMAC_COMPONENT_
+#define _SAME54_GMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GMAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_GMAC Ethernet MAC */
+/*@{*/
+
+#define GMAC_U2005
+#define REV_GMAC 0x100
+
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) (R/W 32) Network Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t LBL:1; /*!< bit: 1 Loop Back Local */
+ uint32_t RXEN:1; /*!< bit: 2 Receive Enable */
+ uint32_t TXEN:1; /*!< bit: 3 Transmit Enable */
+ uint32_t MPE:1; /*!< bit: 4 Management Port Enable */
+ uint32_t CLRSTAT:1; /*!< bit: 5 Clear Statistics Registers */
+ uint32_t INCSTAT:1; /*!< bit: 6 Increment Statistics Registers */
+ uint32_t WESTAT:1; /*!< bit: 7 Write Enable for Statistics Registers */
+ uint32_t BP:1; /*!< bit: 8 Back pressure */
+ uint32_t TSTART:1; /*!< bit: 9 Start Transmission */
+ uint32_t THALT:1; /*!< bit: 10 Transmit Halt */
+ uint32_t TXPF:1; /*!< bit: 11 Transmit Pause Frame */
+ uint32_t TXZQPF:1; /*!< bit: 12 Transmit Zero Quantum Pause Frame */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t SRTSM:1; /*!< bit: 15 Store Receive Time Stamp to Memory */
+ uint32_t ENPBPR:1; /*!< bit: 16 Enable PFC Priority-based Pause Reception */
+ uint32_t TXPBPF:1; /*!< bit: 17 Transmit PFC Priority-based Pause Frame */
+ uint32_t FNP:1; /*!< bit: 18 Flush Next Packet */
+ uint32_t LPI:1; /*!< bit: 19 Low Power Idle Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NCR_OFFSET 0x000 /**< \brief (GMAC_NCR offset) Network Control Register */
+#define GMAC_NCR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NCR reset_value) Network Control Register */
+
+#define GMAC_NCR_LBL_Pos 1 /**< \brief (GMAC_NCR) Loop Back Local */
+#define GMAC_NCR_LBL (_U_(0x1) << GMAC_NCR_LBL_Pos)
+#define GMAC_NCR_RXEN_Pos 2 /**< \brief (GMAC_NCR) Receive Enable */
+#define GMAC_NCR_RXEN (_U_(0x1) << GMAC_NCR_RXEN_Pos)
+#define GMAC_NCR_TXEN_Pos 3 /**< \brief (GMAC_NCR) Transmit Enable */
+#define GMAC_NCR_TXEN (_U_(0x1) << GMAC_NCR_TXEN_Pos)
+#define GMAC_NCR_MPE_Pos 4 /**< \brief (GMAC_NCR) Management Port Enable */
+#define GMAC_NCR_MPE (_U_(0x1) << GMAC_NCR_MPE_Pos)
+#define GMAC_NCR_CLRSTAT_Pos 5 /**< \brief (GMAC_NCR) Clear Statistics Registers */
+#define GMAC_NCR_CLRSTAT (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos)
+#define GMAC_NCR_INCSTAT_Pos 6 /**< \brief (GMAC_NCR) Increment Statistics Registers */
+#define GMAC_NCR_INCSTAT (_U_(0x1) << GMAC_NCR_INCSTAT_Pos)
+#define GMAC_NCR_WESTAT_Pos 7 /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
+#define GMAC_NCR_WESTAT (_U_(0x1) << GMAC_NCR_WESTAT_Pos)
+#define GMAC_NCR_BP_Pos 8 /**< \brief (GMAC_NCR) Back pressure */
+#define GMAC_NCR_BP (_U_(0x1) << GMAC_NCR_BP_Pos)
+#define GMAC_NCR_TSTART_Pos 9 /**< \brief (GMAC_NCR) Start Transmission */
+#define GMAC_NCR_TSTART (_U_(0x1) << GMAC_NCR_TSTART_Pos)
+#define GMAC_NCR_THALT_Pos 10 /**< \brief (GMAC_NCR) Transmit Halt */
+#define GMAC_NCR_THALT (_U_(0x1) << GMAC_NCR_THALT_Pos)
+#define GMAC_NCR_TXPF_Pos 11 /**< \brief (GMAC_NCR) Transmit Pause Frame */
+#define GMAC_NCR_TXPF (_U_(0x1) << GMAC_NCR_TXPF_Pos)
+#define GMAC_NCR_TXZQPF_Pos 12 /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
+#define GMAC_NCR_TXZQPF (_U_(0x1) << GMAC_NCR_TXZQPF_Pos)
+#define GMAC_NCR_SRTSM_Pos 15 /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
+#define GMAC_NCR_SRTSM (_U_(0x1) << GMAC_NCR_SRTSM_Pos)
+#define GMAC_NCR_ENPBPR_Pos 16 /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
+#define GMAC_NCR_ENPBPR (_U_(0x1) << GMAC_NCR_ENPBPR_Pos)
+#define GMAC_NCR_TXPBPF_Pos 17 /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
+#define GMAC_NCR_TXPBPF (_U_(0x1) << GMAC_NCR_TXPBPF_Pos)
+#define GMAC_NCR_FNP_Pos 18 /**< \brief (GMAC_NCR) Flush Next Packet */
+#define GMAC_NCR_FNP (_U_(0x1) << GMAC_NCR_FNP_Pos)
+#define GMAC_NCR_LPI_Pos 19 /**< \brief (GMAC_NCR) Low Power Idle Enable */
+#define GMAC_NCR_LPI (_U_(0x1) << GMAC_NCR_LPI_Pos)
+#define GMAC_NCR_MASK _U_(0x000F9FFE) /**< \brief (GMAC_NCR) MASK Register */
+
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) (R/W 32) Network Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SPD:1; /*!< bit: 0 Speed */
+ uint32_t FD:1; /*!< bit: 1 Full Duplex */
+ uint32_t DNVLAN:1; /*!< bit: 2 Discard Non-VLAN FRAMES */
+ uint32_t JFRAME:1; /*!< bit: 3 Jumbo Frame Size */
+ uint32_t CAF:1; /*!< bit: 4 Copy All Frames */
+ uint32_t NBC:1; /*!< bit: 5 No Broadcast */
+ uint32_t MTIHEN:1; /*!< bit: 6 Multicast Hash Enable */
+ uint32_t UNIHEN:1; /*!< bit: 7 Unicast Hash Enable */
+ uint32_t MAXFS:1; /*!< bit: 8 1536 Maximum Frame Size */
+ uint32_t :3; /*!< bit: 9..11 Reserved */
+ uint32_t RTY:1; /*!< bit: 12 Retry Test */
+ uint32_t PEN:1; /*!< bit: 13 Pause Enable */
+ uint32_t RXBUFO:2; /*!< bit: 14..15 Receive Buffer Offset */
+ uint32_t LFERD:1; /*!< bit: 16 Length Field Error Frame Discard */
+ uint32_t RFCS:1; /*!< bit: 17 Remove FCS */
+ uint32_t CLK:3; /*!< bit: 18..20 MDC CLock Division */
+ uint32_t DBW:2; /*!< bit: 21..22 Data Bus Width */
+ uint32_t DCPF:1; /*!< bit: 23 Disable Copy of Pause Frames */
+ uint32_t RXCOEN:1; /*!< bit: 24 Receive Checksum Offload Enable */
+ uint32_t EFRHD:1; /*!< bit: 25 Enable Frames Received in Half Duplex */
+ uint32_t IRXFCS:1; /*!< bit: 26 Ignore RX FCS */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t IPGSEN:1; /*!< bit: 28 IP Stretch Enable */
+ uint32_t RXBP:1; /*!< bit: 29 Receive Bad Preamble */
+ uint32_t IRXER:1; /*!< bit: 30 Ignore IPG GRXER */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NCFGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NCFGR_OFFSET 0x004 /**< \brief (GMAC_NCFGR offset) Network Configuration Register */
+#define GMAC_NCFGR_RESETVALUE _U_(0x00080000) /**< \brief (GMAC_NCFGR reset_value) Network Configuration Register */
+
+#define GMAC_NCFGR_SPD_Pos 0 /**< \brief (GMAC_NCFGR) Speed */
+#define GMAC_NCFGR_SPD (_U_(0x1) << GMAC_NCFGR_SPD_Pos)
+#define GMAC_NCFGR_FD_Pos 1 /**< \brief (GMAC_NCFGR) Full Duplex */
+#define GMAC_NCFGR_FD (_U_(0x1) << GMAC_NCFGR_FD_Pos)
+#define GMAC_NCFGR_DNVLAN_Pos 2 /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
+#define GMAC_NCFGR_DNVLAN (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos)
+#define GMAC_NCFGR_JFRAME_Pos 3 /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
+#define GMAC_NCFGR_JFRAME (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos)
+#define GMAC_NCFGR_CAF_Pos 4 /**< \brief (GMAC_NCFGR) Copy All Frames */
+#define GMAC_NCFGR_CAF (_U_(0x1) << GMAC_NCFGR_CAF_Pos)
+#define GMAC_NCFGR_NBC_Pos 5 /**< \brief (GMAC_NCFGR) No Broadcast */
+#define GMAC_NCFGR_NBC (_U_(0x1) << GMAC_NCFGR_NBC_Pos)
+#define GMAC_NCFGR_MTIHEN_Pos 6 /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
+#define GMAC_NCFGR_MTIHEN (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos)
+#define GMAC_NCFGR_UNIHEN_Pos 7 /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
+#define GMAC_NCFGR_UNIHEN (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos)
+#define GMAC_NCFGR_MAXFS_Pos 8 /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
+#define GMAC_NCFGR_MAXFS (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos)
+#define GMAC_NCFGR_RTY_Pos 12 /**< \brief (GMAC_NCFGR) Retry Test */
+#define GMAC_NCFGR_RTY (_U_(0x1) << GMAC_NCFGR_RTY_Pos)
+#define GMAC_NCFGR_PEN_Pos 13 /**< \brief (GMAC_NCFGR) Pause Enable */
+#define GMAC_NCFGR_PEN (_U_(0x1) << GMAC_NCFGR_PEN_Pos)
+#define GMAC_NCFGR_RXBUFO_Pos 14 /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
+#define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos)
+#define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))
+#define GMAC_NCFGR_LFERD_Pos 16 /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
+#define GMAC_NCFGR_LFERD (_U_(0x1) << GMAC_NCFGR_LFERD_Pos)
+#define GMAC_NCFGR_RFCS_Pos 17 /**< \brief (GMAC_NCFGR) Remove FCS */
+#define GMAC_NCFGR_RFCS (_U_(0x1) << GMAC_NCFGR_RFCS_Pos)
+#define GMAC_NCFGR_CLK_Pos 18 /**< \brief (GMAC_NCFGR) MDC CLock Division */
+#define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos)
+#define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))
+#define GMAC_NCFGR_DBW_Pos 21 /**< \brief (GMAC_NCFGR) Data Bus Width */
+#define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos)
+#define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))
+#define GMAC_NCFGR_DCPF_Pos 23 /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
+#define GMAC_NCFGR_DCPF (_U_(0x1) << GMAC_NCFGR_DCPF_Pos)
+#define GMAC_NCFGR_RXCOEN_Pos 24 /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
+#define GMAC_NCFGR_RXCOEN (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos)
+#define GMAC_NCFGR_EFRHD_Pos 25 /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
+#define GMAC_NCFGR_EFRHD (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos)
+#define GMAC_NCFGR_IRXFCS_Pos 26 /**< \brief (GMAC_NCFGR) Ignore RX FCS */
+#define GMAC_NCFGR_IRXFCS (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos)
+#define GMAC_NCFGR_IPGSEN_Pos 28 /**< \brief (GMAC_NCFGR) IP Stretch Enable */
+#define GMAC_NCFGR_IPGSEN (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos)
+#define GMAC_NCFGR_RXBP_Pos 29 /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
+#define GMAC_NCFGR_RXBP (_U_(0x1) << GMAC_NCFGR_RXBP_Pos)
+#define GMAC_NCFGR_IRXER_Pos 30 /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */
+#define GMAC_NCFGR_IRXER (_U_(0x1) << GMAC_NCFGR_IRXER_Pos)
+#define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \brief (GMAC_NCFGR) MASK Register */
+
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) (R/ 32) Network Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t MDIO:1; /*!< bit: 1 MDIO Input Status */
+ uint32_t IDLE:1; /*!< bit: 2 PHY Management Logic Idle */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NSR_OFFSET 0x008 /**< \brief (GMAC_NSR offset) Network Status Register */
+#define GMAC_NSR_RESETVALUE _U_(0x00000004) /**< \brief (GMAC_NSR reset_value) Network Status Register */
+
+#define GMAC_NSR_MDIO_Pos 1 /**< \brief (GMAC_NSR) MDIO Input Status */
+#define GMAC_NSR_MDIO (_U_(0x1) << GMAC_NSR_MDIO_Pos)
+#define GMAC_NSR_IDLE_Pos 2 /**< \brief (GMAC_NSR) PHY Management Logic Idle */
+#define GMAC_NSR_IDLE (_U_(0x1) << GMAC_NSR_IDLE_Pos)
+#define GMAC_NSR_MASK _U_(0x00000006) /**< \brief (GMAC_NSR) MASK Register */
+
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) (R/W 32) User Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MII:1; /*!< bit: 0 MII Mode */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_UR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UR_OFFSET 0x00C /**< \brief (GMAC_UR offset) User Register */
+#define GMAC_UR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UR reset_value) User Register */
+
+#define GMAC_UR_MII_Pos 0 /**< \brief (GMAC_UR) MII Mode */
+#define GMAC_UR_MII (_U_(0x1) << GMAC_UR_MII_Pos)
+#define GMAC_UR_MASK _U_(0x00000001) /**< \brief (GMAC_UR) MASK Register */
+
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) (R/W 32) DMA Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FBLDO:5; /*!< bit: 0.. 4 Fixed Burst Length for DMA Data Operations: */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t ESMA:1; /*!< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */
+ uint32_t ESPA:1; /*!< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */
+ uint32_t RXBMS:2; /*!< bit: 8.. 9 Receiver Packet Buffer Memory Size Select */
+ uint32_t TXPBMS:1; /*!< bit: 10 Transmitter Packet Buffer Memory Size Select */
+ uint32_t TXCOEN:1; /*!< bit: 11 Transmitter Checksum Generation Offload Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DRBS:8; /*!< bit: 16..23 DMA Receive Buffer Size */
+ uint32_t DDRP:1; /*!< bit: 24 DMA Discard Receive Packets */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_DCFGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_DCFGR_OFFSET 0x010 /**< \brief (GMAC_DCFGR offset) DMA Configuration Register */
+#define GMAC_DCFGR_RESETVALUE _U_(0x00020704) /**< \brief (GMAC_DCFGR reset_value) DMA Configuration Register */
+
+#define GMAC_DCFGR_FBLDO_Pos 0 /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
+#define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos)
+#define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))
+#define GMAC_DCFGR_ESMA_Pos 6 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
+#define GMAC_DCFGR_ESMA (_U_(0x1) << GMAC_DCFGR_ESMA_Pos)
+#define GMAC_DCFGR_ESPA_Pos 7 /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
+#define GMAC_DCFGR_ESPA (_U_(0x1) << GMAC_DCFGR_ESPA_Pos)
+#define GMAC_DCFGR_RXBMS_Pos 8 /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos)
+#define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))
+#define GMAC_DCFGR_TXPBMS_Pos 10 /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_TXPBMS (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos)
+#define GMAC_DCFGR_TXCOEN_Pos 11 /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
+#define GMAC_DCFGR_TXCOEN (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos)
+#define GMAC_DCFGR_DRBS_Pos 16 /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
+#define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos)
+#define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))
+#define GMAC_DCFGR_DDRP_Pos 24 /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
+#define GMAC_DCFGR_DDRP (_U_(0x1) << GMAC_DCFGR_DDRP_Pos)
+#define GMAC_DCFGR_MASK _U_(0x01FF0FDF) /**< \brief (GMAC_DCFGR) MASK Register */
+
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) (R/W 32) Transmit Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t UBR:1; /*!< bit: 0 Used Bit Read */
+ uint32_t COL:1; /*!< bit: 1 Collision Occurred */
+ uint32_t RLE:1; /*!< bit: 2 Retry Limit Exceeded */
+ uint32_t TXGO:1; /*!< bit: 3 Transmit Go */
+ uint32_t TFC:1; /*!< bit: 4 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TXCOMP:1; /*!< bit: 5 Transmit Complete */
+ uint32_t UND:1; /*!< bit: 6 Transmit Underrun */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t HRESP:1; /*!< bit: 8 HRESP Not OK */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSR_OFFSET 0x014 /**< \brief (GMAC_TSR offset) Transmit Status Register */
+#define GMAC_TSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSR reset_value) Transmit Status Register */
+
+#define GMAC_TSR_UBR_Pos 0 /**< \brief (GMAC_TSR) Used Bit Read */
+#define GMAC_TSR_UBR (_U_(0x1) << GMAC_TSR_UBR_Pos)
+#define GMAC_TSR_COL_Pos 1 /**< \brief (GMAC_TSR) Collision Occurred */
+#define GMAC_TSR_COL (_U_(0x1) << GMAC_TSR_COL_Pos)
+#define GMAC_TSR_RLE_Pos 2 /**< \brief (GMAC_TSR) Retry Limit Exceeded */
+#define GMAC_TSR_RLE (_U_(0x1) << GMAC_TSR_RLE_Pos)
+#define GMAC_TSR_TXGO_Pos 3 /**< \brief (GMAC_TSR) Transmit Go */
+#define GMAC_TSR_TXGO (_U_(0x1) << GMAC_TSR_TXGO_Pos)
+#define GMAC_TSR_TFC_Pos 4 /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_TSR_TFC (_U_(0x1) << GMAC_TSR_TFC_Pos)
+#define GMAC_TSR_TXCOMP_Pos 5 /**< \brief (GMAC_TSR) Transmit Complete */
+#define GMAC_TSR_TXCOMP (_U_(0x1) << GMAC_TSR_TXCOMP_Pos)
+#define GMAC_TSR_UND_Pos 6 /**< \brief (GMAC_TSR) Transmit Underrun */
+#define GMAC_TSR_UND (_U_(0x1) << GMAC_TSR_UND_Pos)
+#define GMAC_TSR_HRESP_Pos 8 /**< \brief (GMAC_TSR) HRESP Not OK */
+#define GMAC_TSR_HRESP (_U_(0x1) << GMAC_TSR_HRESP_Pos)
+#define GMAC_TSR_MASK _U_(0x0000017F) /**< \brief (GMAC_TSR) MASK Register */
+
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) (R/W 32) Receive Buffer Queue Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Receive Buffer Queue Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RBQB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RBQB_OFFSET 0x018 /**< \brief (GMAC_RBQB offset) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RBQB reset_value) Receive Buffer Queue Base Address */
+
+#define GMAC_RBQB_ADDR_Pos 2 /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos)
+#define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))
+#define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_RBQB) MASK Register */
+
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) (R/W 32) Transmit Buffer Queue Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Transmit Buffer Queue Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBQB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBQB_OFFSET 0x01C /**< \brief (GMAC_TBQB offset) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBQB reset_value) Transmit Buffer Queue Base Address */
+
+#define GMAC_TBQB_ADDR_Pos 2 /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos)
+#define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))
+#define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \brief (GMAC_TBQB) MASK Register */
+
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) (R/W 32) Receive Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BNA:1; /*!< bit: 0 Buffer Not Available */
+ uint32_t REC:1; /*!< bit: 1 Frame Received */
+ uint32_t RXOVR:1; /*!< bit: 2 Receive Overrun */
+ uint32_t HNO:1; /*!< bit: 3 HRESP Not OK */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RSR_OFFSET 0x020 /**< \brief (GMAC_RSR offset) Receive Status Register */
+#define GMAC_RSR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSR reset_value) Receive Status Register */
+
+#define GMAC_RSR_BNA_Pos 0 /**< \brief (GMAC_RSR) Buffer Not Available */
+#define GMAC_RSR_BNA (_U_(0x1) << GMAC_RSR_BNA_Pos)
+#define GMAC_RSR_REC_Pos 1 /**< \brief (GMAC_RSR) Frame Received */
+#define GMAC_RSR_REC (_U_(0x1) << GMAC_RSR_REC_Pos)
+#define GMAC_RSR_RXOVR_Pos 2 /**< \brief (GMAC_RSR) Receive Overrun */
+#define GMAC_RSR_RXOVR (_U_(0x1) << GMAC_RSR_RXOVR_Pos)
+#define GMAC_RSR_HNO_Pos 3 /**< \brief (GMAC_RSR) HRESP Not OK */
+#define GMAC_RSR_HNO (_U_(0x1) << GMAC_RSR_HNO_Pos)
+#define GMAC_RSR_MASK _U_(0x0000000F) /**< \brief (GMAC_RSR) MASK Register */
+
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) (R/W 32) Interrupt Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t :3; /*!< bit: 15..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ISR_OFFSET 0x024 /**< \brief (GMAC_ISR offset) Interrupt Status Register */
+#define GMAC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ISR reset_value) Interrupt Status Register */
+
+#define GMAC_ISR_MFS_Pos 0 /**< \brief (GMAC_ISR) Management Frame Sent */
+#define GMAC_ISR_MFS (_U_(0x1) << GMAC_ISR_MFS_Pos)
+#define GMAC_ISR_RCOMP_Pos 1 /**< \brief (GMAC_ISR) Receive Complete */
+#define GMAC_ISR_RCOMP (_U_(0x1) << GMAC_ISR_RCOMP_Pos)
+#define GMAC_ISR_RXUBR_Pos 2 /**< \brief (GMAC_ISR) RX Used Bit Read */
+#define GMAC_ISR_RXUBR (_U_(0x1) << GMAC_ISR_RXUBR_Pos)
+#define GMAC_ISR_TXUBR_Pos 3 /**< \brief (GMAC_ISR) TX Used Bit Read */
+#define GMAC_ISR_TXUBR (_U_(0x1) << GMAC_ISR_TXUBR_Pos)
+#define GMAC_ISR_TUR_Pos 4 /**< \brief (GMAC_ISR) Transmit Underrun */
+#define GMAC_ISR_TUR (_U_(0x1) << GMAC_ISR_TUR_Pos)
+#define GMAC_ISR_RLEX_Pos 5 /**< \brief (GMAC_ISR) Retry Limit Exceeded */
+#define GMAC_ISR_RLEX (_U_(0x1) << GMAC_ISR_RLEX_Pos)
+#define GMAC_ISR_TFC_Pos 6 /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_ISR_TFC (_U_(0x1) << GMAC_ISR_TFC_Pos)
+#define GMAC_ISR_TCOMP_Pos 7 /**< \brief (GMAC_ISR) Transmit Complete */
+#define GMAC_ISR_TCOMP (_U_(0x1) << GMAC_ISR_TCOMP_Pos)
+#define GMAC_ISR_ROVR_Pos 10 /**< \brief (GMAC_ISR) Receive Overrun */
+#define GMAC_ISR_ROVR (_U_(0x1) << GMAC_ISR_ROVR_Pos)
+#define GMAC_ISR_HRESP_Pos 11 /**< \brief (GMAC_ISR) HRESP Not OK */
+#define GMAC_ISR_HRESP (_U_(0x1) << GMAC_ISR_HRESP_Pos)
+#define GMAC_ISR_PFNZ_Pos 12 /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_ISR_PFNZ (_U_(0x1) << GMAC_ISR_PFNZ_Pos)
+#define GMAC_ISR_PTZ_Pos 13 /**< \brief (GMAC_ISR) Pause Time Zero */
+#define GMAC_ISR_PTZ (_U_(0x1) << GMAC_ISR_PTZ_Pos)
+#define GMAC_ISR_PFTR_Pos 14 /**< \brief (GMAC_ISR) Pause Frame Transmitted */
+#define GMAC_ISR_PFTR (_U_(0x1) << GMAC_ISR_PFTR_Pos)
+#define GMAC_ISR_DRQFR_Pos 18 /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
+#define GMAC_ISR_DRQFR (_U_(0x1) << GMAC_ISR_DRQFR_Pos)
+#define GMAC_ISR_SFR_Pos 19 /**< \brief (GMAC_ISR) PTP Sync Frame Received */
+#define GMAC_ISR_SFR (_U_(0x1) << GMAC_ISR_SFR_Pos)
+#define GMAC_ISR_DRQFT_Pos 20 /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
+#define GMAC_ISR_DRQFT (_U_(0x1) << GMAC_ISR_DRQFT_Pos)
+#define GMAC_ISR_SFT_Pos 21 /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
+#define GMAC_ISR_SFT (_U_(0x1) << GMAC_ISR_SFT_Pos)
+#define GMAC_ISR_PDRQFR_Pos 22 /**< \brief (GMAC_ISR) PDelay Request Frame Received */
+#define GMAC_ISR_PDRQFR (_U_(0x1) << GMAC_ISR_PDRQFR_Pos)
+#define GMAC_ISR_PDRSFR_Pos 23 /**< \brief (GMAC_ISR) PDelay Response Frame Received */
+#define GMAC_ISR_PDRSFR (_U_(0x1) << GMAC_ISR_PDRSFR_Pos)
+#define GMAC_ISR_PDRQFT_Pos 24 /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
+#define GMAC_ISR_PDRQFT (_U_(0x1) << GMAC_ISR_PDRQFT_Pos)
+#define GMAC_ISR_PDRSFT_Pos 25 /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
+#define GMAC_ISR_PDRSFT (_U_(0x1) << GMAC_ISR_PDRSFT_Pos)
+#define GMAC_ISR_SRI_Pos 26 /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
+#define GMAC_ISR_SRI (_U_(0x1) << GMAC_ISR_SRI_Pos)
+#define GMAC_ISR_WOL_Pos 28 /**< \brief (GMAC_ISR) Wake On LAN */
+#define GMAC_ISR_WOL (_U_(0x1) << GMAC_ISR_WOL_Pos)
+#define GMAC_ISR_TSUCMP_Pos 29 /**< \brief (GMAC_ISR) Tsu timer comparison */
+#define GMAC_ISR_TSUCMP (_U_(0x1) << GMAC_ISR_TSUCMP_Pos)
+#define GMAC_ISR_MASK _U_(0x37FC7CFF) /**< \brief (GMAC_ISR) MASK Register */
+
+/* -------- GMAC_IER : (GMAC Offset: 0x028) ( /W 32) Interrupt Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
+ uint32_t :2; /*!< bit: 16..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IER_OFFSET 0x028 /**< \brief (GMAC_IER offset) Interrupt Enable Register */
+
+#define GMAC_IER_MFS_Pos 0 /**< \brief (GMAC_IER) Management Frame Sent */
+#define GMAC_IER_MFS (_U_(0x1) << GMAC_IER_MFS_Pos)
+#define GMAC_IER_RCOMP_Pos 1 /**< \brief (GMAC_IER) Receive Complete */
+#define GMAC_IER_RCOMP (_U_(0x1) << GMAC_IER_RCOMP_Pos)
+#define GMAC_IER_RXUBR_Pos 2 /**< \brief (GMAC_IER) RX Used Bit Read */
+#define GMAC_IER_RXUBR (_U_(0x1) << GMAC_IER_RXUBR_Pos)
+#define GMAC_IER_TXUBR_Pos 3 /**< \brief (GMAC_IER) TX Used Bit Read */
+#define GMAC_IER_TXUBR (_U_(0x1) << GMAC_IER_TXUBR_Pos)
+#define GMAC_IER_TUR_Pos 4 /**< \brief (GMAC_IER) Transmit Underrun */
+#define GMAC_IER_TUR (_U_(0x1) << GMAC_IER_TUR_Pos)
+#define GMAC_IER_RLEX_Pos 5 /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
+#define GMAC_IER_RLEX (_U_(0x1) << GMAC_IER_RLEX_Pos)
+#define GMAC_IER_TFC_Pos 6 /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IER_TFC (_U_(0x1) << GMAC_IER_TFC_Pos)
+#define GMAC_IER_TCOMP_Pos 7 /**< \brief (GMAC_IER) Transmit Complete */
+#define GMAC_IER_TCOMP (_U_(0x1) << GMAC_IER_TCOMP_Pos)
+#define GMAC_IER_ROVR_Pos 10 /**< \brief (GMAC_IER) Receive Overrun */
+#define GMAC_IER_ROVR (_U_(0x1) << GMAC_IER_ROVR_Pos)
+#define GMAC_IER_HRESP_Pos 11 /**< \brief (GMAC_IER) HRESP Not OK */
+#define GMAC_IER_HRESP (_U_(0x1) << GMAC_IER_HRESP_Pos)
+#define GMAC_IER_PFNZ_Pos 12 /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IER_PFNZ (_U_(0x1) << GMAC_IER_PFNZ_Pos)
+#define GMAC_IER_PTZ_Pos 13 /**< \brief (GMAC_IER) Pause Time Zero */
+#define GMAC_IER_PTZ (_U_(0x1) << GMAC_IER_PTZ_Pos)
+#define GMAC_IER_PFTR_Pos 14 /**< \brief (GMAC_IER) Pause Frame Transmitted */
+#define GMAC_IER_PFTR (_U_(0x1) << GMAC_IER_PFTR_Pos)
+#define GMAC_IER_EXINT_Pos 15 /**< \brief (GMAC_IER) External Interrupt */
+#define GMAC_IER_EXINT (_U_(0x1) << GMAC_IER_EXINT_Pos)
+#define GMAC_IER_DRQFR_Pos 18 /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
+#define GMAC_IER_DRQFR (_U_(0x1) << GMAC_IER_DRQFR_Pos)
+#define GMAC_IER_SFR_Pos 19 /**< \brief (GMAC_IER) PTP Sync Frame Received */
+#define GMAC_IER_SFR (_U_(0x1) << GMAC_IER_SFR_Pos)
+#define GMAC_IER_DRQFT_Pos 20 /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
+#define GMAC_IER_DRQFT (_U_(0x1) << GMAC_IER_DRQFT_Pos)
+#define GMAC_IER_SFT_Pos 21 /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
+#define GMAC_IER_SFT (_U_(0x1) << GMAC_IER_SFT_Pos)
+#define GMAC_IER_PDRQFR_Pos 22 /**< \brief (GMAC_IER) PDelay Request Frame Received */
+#define GMAC_IER_PDRQFR (_U_(0x1) << GMAC_IER_PDRQFR_Pos)
+#define GMAC_IER_PDRSFR_Pos 23 /**< \brief (GMAC_IER) PDelay Response Frame Received */
+#define GMAC_IER_PDRSFR (_U_(0x1) << GMAC_IER_PDRSFR_Pos)
+#define GMAC_IER_PDRQFT_Pos 24 /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
+#define GMAC_IER_PDRQFT (_U_(0x1) << GMAC_IER_PDRQFT_Pos)
+#define GMAC_IER_PDRSFT_Pos 25 /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
+#define GMAC_IER_PDRSFT (_U_(0x1) << GMAC_IER_PDRSFT_Pos)
+#define GMAC_IER_SRI_Pos 26 /**< \brief (GMAC_IER) TSU Seconds Register Increment */
+#define GMAC_IER_SRI (_U_(0x1) << GMAC_IER_SRI_Pos)
+#define GMAC_IER_WOL_Pos 28 /**< \brief (GMAC_IER) Wake On LAN */
+#define GMAC_IER_WOL (_U_(0x1) << GMAC_IER_WOL_Pos)
+#define GMAC_IER_TSUCMP_Pos 29 /**< \brief (GMAC_IER) Tsu timer comparison */
+#define GMAC_IER_TSUCMP (_U_(0x1) << GMAC_IER_TSUCMP_Pos)
+#define GMAC_IER_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IER) MASK Register */
+
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) ( /W 32) Interrupt Disable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded or Late Collision */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
+ uint32_t :2; /*!< bit: 16..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On LAN */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IDR_OFFSET 0x02C /**< \brief (GMAC_IDR offset) Interrupt Disable Register */
+
+#define GMAC_IDR_MFS_Pos 0 /**< \brief (GMAC_IDR) Management Frame Sent */
+#define GMAC_IDR_MFS (_U_(0x1) << GMAC_IDR_MFS_Pos)
+#define GMAC_IDR_RCOMP_Pos 1 /**< \brief (GMAC_IDR) Receive Complete */
+#define GMAC_IDR_RCOMP (_U_(0x1) << GMAC_IDR_RCOMP_Pos)
+#define GMAC_IDR_RXUBR_Pos 2 /**< \brief (GMAC_IDR) RX Used Bit Read */
+#define GMAC_IDR_RXUBR (_U_(0x1) << GMAC_IDR_RXUBR_Pos)
+#define GMAC_IDR_TXUBR_Pos 3 /**< \brief (GMAC_IDR) TX Used Bit Read */
+#define GMAC_IDR_TXUBR (_U_(0x1) << GMAC_IDR_TXUBR_Pos)
+#define GMAC_IDR_TUR_Pos 4 /**< \brief (GMAC_IDR) Transmit Underrun */
+#define GMAC_IDR_TUR (_U_(0x1) << GMAC_IDR_TUR_Pos)
+#define GMAC_IDR_RLEX_Pos 5 /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
+#define GMAC_IDR_RLEX (_U_(0x1) << GMAC_IDR_RLEX_Pos)
+#define GMAC_IDR_TFC_Pos 6 /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IDR_TFC (_U_(0x1) << GMAC_IDR_TFC_Pos)
+#define GMAC_IDR_TCOMP_Pos 7 /**< \brief (GMAC_IDR) Transmit Complete */
+#define GMAC_IDR_TCOMP (_U_(0x1) << GMAC_IDR_TCOMP_Pos)
+#define GMAC_IDR_ROVR_Pos 10 /**< \brief (GMAC_IDR) Receive Overrun */
+#define GMAC_IDR_ROVR (_U_(0x1) << GMAC_IDR_ROVR_Pos)
+#define GMAC_IDR_HRESP_Pos 11 /**< \brief (GMAC_IDR) HRESP Not OK */
+#define GMAC_IDR_HRESP (_U_(0x1) << GMAC_IDR_HRESP_Pos)
+#define GMAC_IDR_PFNZ_Pos 12 /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IDR_PFNZ (_U_(0x1) << GMAC_IDR_PFNZ_Pos)
+#define GMAC_IDR_PTZ_Pos 13 /**< \brief (GMAC_IDR) Pause Time Zero */
+#define GMAC_IDR_PTZ (_U_(0x1) << GMAC_IDR_PTZ_Pos)
+#define GMAC_IDR_PFTR_Pos 14 /**< \brief (GMAC_IDR) Pause Frame Transmitted */
+#define GMAC_IDR_PFTR (_U_(0x1) << GMAC_IDR_PFTR_Pos)
+#define GMAC_IDR_EXINT_Pos 15 /**< \brief (GMAC_IDR) External Interrupt */
+#define GMAC_IDR_EXINT (_U_(0x1) << GMAC_IDR_EXINT_Pos)
+#define GMAC_IDR_DRQFR_Pos 18 /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
+#define GMAC_IDR_DRQFR (_U_(0x1) << GMAC_IDR_DRQFR_Pos)
+#define GMAC_IDR_SFR_Pos 19 /**< \brief (GMAC_IDR) PTP Sync Frame Received */
+#define GMAC_IDR_SFR (_U_(0x1) << GMAC_IDR_SFR_Pos)
+#define GMAC_IDR_DRQFT_Pos 20 /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
+#define GMAC_IDR_DRQFT (_U_(0x1) << GMAC_IDR_DRQFT_Pos)
+#define GMAC_IDR_SFT_Pos 21 /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
+#define GMAC_IDR_SFT (_U_(0x1) << GMAC_IDR_SFT_Pos)
+#define GMAC_IDR_PDRQFR_Pos 22 /**< \brief (GMAC_IDR) PDelay Request Frame Received */
+#define GMAC_IDR_PDRQFR (_U_(0x1) << GMAC_IDR_PDRQFR_Pos)
+#define GMAC_IDR_PDRSFR_Pos 23 /**< \brief (GMAC_IDR) PDelay Response Frame Received */
+#define GMAC_IDR_PDRSFR (_U_(0x1) << GMAC_IDR_PDRSFR_Pos)
+#define GMAC_IDR_PDRQFT_Pos 24 /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
+#define GMAC_IDR_PDRQFT (_U_(0x1) << GMAC_IDR_PDRQFT_Pos)
+#define GMAC_IDR_PDRSFT_Pos 25 /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
+#define GMAC_IDR_PDRSFT (_U_(0x1) << GMAC_IDR_PDRSFT_Pos)
+#define GMAC_IDR_SRI_Pos 26 /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
+#define GMAC_IDR_SRI (_U_(0x1) << GMAC_IDR_SRI_Pos)
+#define GMAC_IDR_WOL_Pos 28 /**< \brief (GMAC_IDR) Wake On LAN */
+#define GMAC_IDR_WOL (_U_(0x1) << GMAC_IDR_WOL_Pos)
+#define GMAC_IDR_TSUCMP_Pos 29 /**< \brief (GMAC_IDR) Tsu timer comparison */
+#define GMAC_IDR_TSUCMP (_U_(0x1) << GMAC_IDR_TSUCMP_Pos)
+#define GMAC_IDR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IDR) MASK Register */
+
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) (R/ 32) Interrupt Mask Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFS:1; /*!< bit: 0 Management Frame Sent */
+ uint32_t RCOMP:1; /*!< bit: 1 Receive Complete */
+ uint32_t RXUBR:1; /*!< bit: 2 RX Used Bit Read */
+ uint32_t TXUBR:1; /*!< bit: 3 TX Used Bit Read */
+ uint32_t TUR:1; /*!< bit: 4 Transmit Underrun */
+ uint32_t RLEX:1; /*!< bit: 5 Retry Limit Exceeded */
+ uint32_t TFC:1; /*!< bit: 6 Transmit Frame Corruption Due to AHB Error */
+ uint32_t TCOMP:1; /*!< bit: 7 Transmit Complete */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t ROVR:1; /*!< bit: 10 Receive Overrun */
+ uint32_t HRESP:1; /*!< bit: 11 HRESP Not OK */
+ uint32_t PFNZ:1; /*!< bit: 12 Pause Frame with Non-zero Pause Quantum Received */
+ uint32_t PTZ:1; /*!< bit: 13 Pause Time Zero */
+ uint32_t PFTR:1; /*!< bit: 14 Pause Frame Transmitted */
+ uint32_t EXINT:1; /*!< bit: 15 External Interrupt */
+ uint32_t :2; /*!< bit: 16..17 Reserved */
+ uint32_t DRQFR:1; /*!< bit: 18 PTP Delay Request Frame Received */
+ uint32_t SFR:1; /*!< bit: 19 PTP Sync Frame Received */
+ uint32_t DRQFT:1; /*!< bit: 20 PTP Delay Request Frame Transmitted */
+ uint32_t SFT:1; /*!< bit: 21 PTP Sync Frame Transmitted */
+ uint32_t PDRQFR:1; /*!< bit: 22 PDelay Request Frame Received */
+ uint32_t PDRSFR:1; /*!< bit: 23 PDelay Response Frame Received */
+ uint32_t PDRQFT:1; /*!< bit: 24 PDelay Request Frame Transmitted */
+ uint32_t PDRSFT:1; /*!< bit: 25 PDelay Response Frame Transmitted */
+ uint32_t SRI:1; /*!< bit: 26 TSU Seconds Register Increment */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t WOL:1; /*!< bit: 28 Wake On Lan */
+ uint32_t TSUCMP:1; /*!< bit: 29 Tsu timer comparison */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IMR_OFFSET 0x030 /**< \brief (GMAC_IMR offset) Interrupt Mask Register */
+#define GMAC_IMR_RESETVALUE _U_(0x3FFFFFFF) /**< \brief (GMAC_IMR reset_value) Interrupt Mask Register */
+
+#define GMAC_IMR_MFS_Pos 0 /**< \brief (GMAC_IMR) Management Frame Sent */
+#define GMAC_IMR_MFS (_U_(0x1) << GMAC_IMR_MFS_Pos)
+#define GMAC_IMR_RCOMP_Pos 1 /**< \brief (GMAC_IMR) Receive Complete */
+#define GMAC_IMR_RCOMP (_U_(0x1) << GMAC_IMR_RCOMP_Pos)
+#define GMAC_IMR_RXUBR_Pos 2 /**< \brief (GMAC_IMR) RX Used Bit Read */
+#define GMAC_IMR_RXUBR (_U_(0x1) << GMAC_IMR_RXUBR_Pos)
+#define GMAC_IMR_TXUBR_Pos 3 /**< \brief (GMAC_IMR) TX Used Bit Read */
+#define GMAC_IMR_TXUBR (_U_(0x1) << GMAC_IMR_TXUBR_Pos)
+#define GMAC_IMR_TUR_Pos 4 /**< \brief (GMAC_IMR) Transmit Underrun */
+#define GMAC_IMR_TUR (_U_(0x1) << GMAC_IMR_TUR_Pos)
+#define GMAC_IMR_RLEX_Pos 5 /**< \brief (GMAC_IMR) Retry Limit Exceeded */
+#define GMAC_IMR_RLEX (_U_(0x1) << GMAC_IMR_RLEX_Pos)
+#define GMAC_IMR_TFC_Pos 6 /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IMR_TFC (_U_(0x1) << GMAC_IMR_TFC_Pos)
+#define GMAC_IMR_TCOMP_Pos 7 /**< \brief (GMAC_IMR) Transmit Complete */
+#define GMAC_IMR_TCOMP (_U_(0x1) << GMAC_IMR_TCOMP_Pos)
+#define GMAC_IMR_ROVR_Pos 10 /**< \brief (GMAC_IMR) Receive Overrun */
+#define GMAC_IMR_ROVR (_U_(0x1) << GMAC_IMR_ROVR_Pos)
+#define GMAC_IMR_HRESP_Pos 11 /**< \brief (GMAC_IMR) HRESP Not OK */
+#define GMAC_IMR_HRESP (_U_(0x1) << GMAC_IMR_HRESP_Pos)
+#define GMAC_IMR_PFNZ_Pos 12 /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IMR_PFNZ (_U_(0x1) << GMAC_IMR_PFNZ_Pos)
+#define GMAC_IMR_PTZ_Pos 13 /**< \brief (GMAC_IMR) Pause Time Zero */
+#define GMAC_IMR_PTZ (_U_(0x1) << GMAC_IMR_PTZ_Pos)
+#define GMAC_IMR_PFTR_Pos 14 /**< \brief (GMAC_IMR) Pause Frame Transmitted */
+#define GMAC_IMR_PFTR (_U_(0x1) << GMAC_IMR_PFTR_Pos)
+#define GMAC_IMR_EXINT_Pos 15 /**< \brief (GMAC_IMR) External Interrupt */
+#define GMAC_IMR_EXINT (_U_(0x1) << GMAC_IMR_EXINT_Pos)
+#define GMAC_IMR_DRQFR_Pos 18 /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
+#define GMAC_IMR_DRQFR (_U_(0x1) << GMAC_IMR_DRQFR_Pos)
+#define GMAC_IMR_SFR_Pos 19 /**< \brief (GMAC_IMR) PTP Sync Frame Received */
+#define GMAC_IMR_SFR (_U_(0x1) << GMAC_IMR_SFR_Pos)
+#define GMAC_IMR_DRQFT_Pos 20 /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
+#define GMAC_IMR_DRQFT (_U_(0x1) << GMAC_IMR_DRQFT_Pos)
+#define GMAC_IMR_SFT_Pos 21 /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
+#define GMAC_IMR_SFT (_U_(0x1) << GMAC_IMR_SFT_Pos)
+#define GMAC_IMR_PDRQFR_Pos 22 /**< \brief (GMAC_IMR) PDelay Request Frame Received */
+#define GMAC_IMR_PDRQFR (_U_(0x1) << GMAC_IMR_PDRQFR_Pos)
+#define GMAC_IMR_PDRSFR_Pos 23 /**< \brief (GMAC_IMR) PDelay Response Frame Received */
+#define GMAC_IMR_PDRSFR (_U_(0x1) << GMAC_IMR_PDRSFR_Pos)
+#define GMAC_IMR_PDRQFT_Pos 24 /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
+#define GMAC_IMR_PDRQFT (_U_(0x1) << GMAC_IMR_PDRQFT_Pos)
+#define GMAC_IMR_PDRSFT_Pos 25 /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
+#define GMAC_IMR_PDRSFT (_U_(0x1) << GMAC_IMR_PDRSFT_Pos)
+#define GMAC_IMR_SRI_Pos 26 /**< \brief (GMAC_IMR) TSU Seconds Register Increment */
+#define GMAC_IMR_SRI (_U_(0x1) << GMAC_IMR_SRI_Pos)
+#define GMAC_IMR_WOL_Pos 28 /**< \brief (GMAC_IMR) Wake On Lan */
+#define GMAC_IMR_WOL (_U_(0x1) << GMAC_IMR_WOL_Pos)
+#define GMAC_IMR_TSUCMP_Pos 29 /**< \brief (GMAC_IMR) Tsu timer comparison */
+#define GMAC_IMR_TSUCMP (_U_(0x1) << GMAC_IMR_TSUCMP_Pos)
+#define GMAC_IMR_MASK _U_(0x37FCFCFF) /**< \brief (GMAC_IMR) MASK Register */
+
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) (R/W 32) PHY Maintenance Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:16; /*!< bit: 0..15 PHY Data */
+ uint32_t WTN:2; /*!< bit: 16..17 Write Ten */
+ uint32_t REGA:5; /*!< bit: 18..22 Register Address */
+ uint32_t PHYA:5; /*!< bit: 23..27 PHY Address */
+ uint32_t OP:2; /*!< bit: 28..29 Operation */
+ uint32_t CLTTO:1; /*!< bit: 30 Clause 22 Operation */
+ uint32_t WZO:1; /*!< bit: 31 Write ZERO */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MAN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MAN_OFFSET 0x034 /**< \brief (GMAC_MAN offset) PHY Maintenance Register */
+#define GMAC_MAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MAN reset_value) PHY Maintenance Register */
+
+#define GMAC_MAN_DATA_Pos 0 /**< \brief (GMAC_MAN) PHY Data */
+#define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos)
+#define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))
+#define GMAC_MAN_WTN_Pos 16 /**< \brief (GMAC_MAN) Write Ten */
+#define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos)
+#define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))
+#define GMAC_MAN_REGA_Pos 18 /**< \brief (GMAC_MAN) Register Address */
+#define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos)
+#define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))
+#define GMAC_MAN_PHYA_Pos 23 /**< \brief (GMAC_MAN) PHY Address */
+#define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos)
+#define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))
+#define GMAC_MAN_OP_Pos 28 /**< \brief (GMAC_MAN) Operation */
+#define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos)
+#define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))
+#define GMAC_MAN_CLTTO_Pos 30 /**< \brief (GMAC_MAN) Clause 22 Operation */
+#define GMAC_MAN_CLTTO (_U_(0x1) << GMAC_MAN_CLTTO_Pos)
+#define GMAC_MAN_WZO_Pos 31 /**< \brief (GMAC_MAN) Write ZERO */
+#define GMAC_MAN_WZO (_U_(0x1) << GMAC_MAN_WZO_Pos)
+#define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MAN) MASK Register */
+
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) (R/ 32) Received Pause Quantum Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RPQ:16; /*!< bit: 0..15 Received Pause Quantum */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RPQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RPQ_OFFSET 0x038 /**< \brief (GMAC_RPQ offset) Received Pause Quantum Register */
+#define GMAC_RPQ_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RPQ reset_value) Received Pause Quantum Register */
+
+#define GMAC_RPQ_RPQ_Pos 0 /**< \brief (GMAC_RPQ) Received Pause Quantum */
+#define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos)
+#define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos))
+#define GMAC_RPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RPQ) MASK Register */
+
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) (R/W 32) Transmit Pause Quantum Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TPQ:16; /*!< bit: 0..15 Transmit Pause Quantum */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TPQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPQ_OFFSET 0x03C /**< \brief (GMAC_TPQ offset) Transmit Pause Quantum Register */
+#define GMAC_TPQ_RESETVALUE _U_(0x0000FFFF) /**< \brief (GMAC_TPQ reset_value) Transmit Pause Quantum Register */
+
+#define GMAC_TPQ_TPQ_Pos 0 /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
+#define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos)
+#define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))
+#define GMAC_TPQ_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPQ) MASK Register */
+
+/* -------- GMAC_TPSF : (GMAC Offset: 0x040) (R/W 32) TX partial store and forward Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TPB1ADR:10; /*!< bit: 0.. 9 TX packet buffer address */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t ENTXP:1; /*!< bit: 31 Enable TX partial store and forward operation */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TPSF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPSF_OFFSET 0x040 /**< \brief (GMAC_TPSF offset) TX partial store and forward Register */
+#define GMAC_TPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_TPSF reset_value) TX partial store and forward Register */
+
+#define GMAC_TPSF_TPB1ADR_Pos 0 /**< \brief (GMAC_TPSF) TX packet buffer address */
+#define GMAC_TPSF_TPB1ADR_Msk (_U_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos)
+#define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))
+#define GMAC_TPSF_ENTXP_Pos 31 /**< \brief (GMAC_TPSF) Enable TX partial store and forward operation */
+#define GMAC_TPSF_ENTXP (_U_(0x1) << GMAC_TPSF_ENTXP_Pos)
+#define GMAC_TPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_TPSF) MASK Register */
+
+/* -------- GMAC_RPSF : (GMAC Offset: 0x044) (R/W 32) RX partial store and forward Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RPB1ADR:10; /*!< bit: 0.. 9 RX packet buffer address */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t ENRXP:1; /*!< bit: 31 Enable RX partial store and forward operation */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RPSF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RPSF_OFFSET 0x044 /**< \brief (GMAC_RPSF offset) RX partial store and forward Register */
+#define GMAC_RPSF_RESETVALUE _U_(0x000003FF) /**< \brief (GMAC_RPSF reset_value) RX partial store and forward Register */
+
+#define GMAC_RPSF_RPB1ADR_Pos 0 /**< \brief (GMAC_RPSF) RX packet buffer address */
+#define GMAC_RPSF_RPB1ADR_Msk (_U_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos)
+#define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))
+#define GMAC_RPSF_ENRXP_Pos 31 /**< \brief (GMAC_RPSF) Enable RX partial store and forward operation */
+#define GMAC_RPSF_ENRXP (_U_(0x1) << GMAC_RPSF_ENRXP_Pos)
+#define GMAC_RPSF_MASK _U_(0x800003FF) /**< \brief (GMAC_RPSF) MASK Register */
+
+/* -------- GMAC_RJFML : (GMAC Offset: 0x048) (R/W 32) RX Jumbo Frame Max Length Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FML:14; /*!< bit: 0..13 Frame Max Length */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RJFML_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RJFML_OFFSET 0x048 /**< \brief (GMAC_RJFML offset) RX Jumbo Frame Max Length Register */
+#define GMAC_RJFML_RESETVALUE _U_(0x00003FFF) /**< \brief (GMAC_RJFML reset_value) RX Jumbo Frame Max Length Register */
+
+#define GMAC_RJFML_FML_Pos 0 /**< \brief (GMAC_RJFML) Frame Max Length */
+#define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos)
+#define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))
+#define GMAC_RJFML_MASK _U_(0x00003FFF) /**< \brief (GMAC_RJFML) MASK Register */
+
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) (R/W 32) Hash Register Bottom [31:0] -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_HRB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_HRB_OFFSET 0x080 /**< \brief (GMAC_HRB offset) Hash Register Bottom [31:0] */
+#define GMAC_HRB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRB reset_value) Hash Register Bottom [31:0] */
+
+#define GMAC_HRB_ADDR_Pos 0 /**< \brief (GMAC_HRB) Hash Address */
+#define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos)
+#define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))
+#define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRB) MASK Register */
+
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) (R/W 32) Hash Register Top [63:32] -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Hash Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_HRT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_HRT_OFFSET 0x084 /**< \brief (GMAC_HRT offset) Hash Register Top [63:32] */
+#define GMAC_HRT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_HRT reset_value) Hash Register Top [63:32] */
+
+#define GMAC_HRT_ADDR_Pos 0 /**< \brief (GMAC_HRT) Hash Address */
+#define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos)
+#define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))
+#define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_HRT) MASK Register */
+
+/* -------- GMAC_SAB : (GMAC Offset: 0x088) (R/W 32) SA Specific Address Bottom [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAB_OFFSET 0x088 /**< \brief (GMAC_SAB offset) Specific Address Bottom [31:0] Register */
+#define GMAC_SAB_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAB reset_value) Specific Address Bottom [31:0] Register */
+
+#define GMAC_SAB_ADDR_Pos 0 /**< \brief (GMAC_SAB) Specific Address 1 */
+#define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos)
+#define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))
+#define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAB) MASK Register */
+
+/* -------- GMAC_SAT : (GMAC Offset: 0x08C) (R/W 32) SA Specific Address Top [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAT_OFFSET 0x08C /**< \brief (GMAC_SAT offset) Specific Address Top [47:32] Register */
+#define GMAC_SAT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAT reset_value) Specific Address Top [47:32] Register */
+
+#define GMAC_SAT_ADDR_Pos 0 /**< \brief (GMAC_SAT) Specific Address 1 */
+#define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos)
+#define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))
+#define GMAC_SAT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAT) MASK Register */
+
+/* -------- GMAC_TIDM : (GMAC Offset: 0x0A8) (R/W 32) Type ID Match Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TID:16; /*!< bit: 0..15 Type ID Match 1 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TIDM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TIDM_OFFSET 0x0A8 /**< \brief (GMAC_TIDM offset) Type ID Match Register */
+#define GMAC_TIDM_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TIDM reset_value) Type ID Match Register */
+
+#define GMAC_TIDM_TID_Pos 0 /**< \brief (GMAC_TIDM) Type ID Match 1 */
+#define GMAC_TIDM_TID_Msk (_U_(0xFFFF) << GMAC_TIDM_TID_Pos)
+#define GMAC_TIDM_TID(value) (GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))
+#define GMAC_TIDM_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TIDM) MASK Register */
+
+/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) (R/W 32) Wake on LAN -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IP:16; /*!< bit: 0..15 IP address */
+ uint32_t MAG:1; /*!< bit: 16 Event enable */
+ uint32_t ARP:1; /*!< bit: 17 LAN ARP req */
+ uint32_t SA1:1; /*!< bit: 18 WOL specific address reg 1 */
+ uint32_t MTI:1; /*!< bit: 19 WOL LAN multicast */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_WOL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_WOL_OFFSET 0x0B8 /**< \brief (GMAC_WOL offset) Wake on LAN */
+#define GMAC_WOL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_WOL reset_value) Wake on LAN */
+
+#define GMAC_WOL_IP_Pos 0 /**< \brief (GMAC_WOL) IP address */
+#define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos)
+#define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))
+#define GMAC_WOL_MAG_Pos 16 /**< \brief (GMAC_WOL) Event enable */
+#define GMAC_WOL_MAG (_U_(0x1) << GMAC_WOL_MAG_Pos)
+#define GMAC_WOL_ARP_Pos 17 /**< \brief (GMAC_WOL) LAN ARP req */
+#define GMAC_WOL_ARP (_U_(0x1) << GMAC_WOL_ARP_Pos)
+#define GMAC_WOL_SA1_Pos 18 /**< \brief (GMAC_WOL) WOL specific address reg 1 */
+#define GMAC_WOL_SA1 (_U_(0x1) << GMAC_WOL_SA1_Pos)
+#define GMAC_WOL_MTI_Pos 19 /**< \brief (GMAC_WOL) WOL LAN multicast */
+#define GMAC_WOL_MTI (_U_(0x1) << GMAC_WOL_MTI_Pos)
+#define GMAC_WOL_MASK _U_(0x000FFFFF) /**< \brief (GMAC_WOL) MASK Register */
+
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) (R/W 32) IPG Stretch Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FL:16; /*!< bit: 0..15 Frame Length */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IPGS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IPGS_OFFSET 0x0BC /**< \brief (GMAC_IPGS offset) IPG Stretch Register */
+#define GMAC_IPGS_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IPGS reset_value) IPG Stretch Register */
+
+#define GMAC_IPGS_FL_Pos 0 /**< \brief (GMAC_IPGS) Frame Length */
+#define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos)
+#define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))
+#define GMAC_IPGS_MASK _U_(0x0000FFFF) /**< \brief (GMAC_IPGS) MASK Register */
+
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) (R/W 32) Stacked VLAN Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VLAN_TYPE:16; /*!< bit: 0..15 User Defined VLAN_TYPE Field */
+ uint32_t :15; /*!< bit: 16..30 Reserved */
+ uint32_t ESVLAN:1; /*!< bit: 31 Enable Stacked VLAN Processing Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SVLAN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SVLAN_OFFSET 0x0C0 /**< \brief (GMAC_SVLAN offset) Stacked VLAN Register */
+#define GMAC_SVLAN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SVLAN reset_value) Stacked VLAN Register */
+
+#define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
+#define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos)
+#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))
+#define GMAC_SVLAN_ESVLAN_Pos 31 /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
+#define GMAC_SVLAN_ESVLAN (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos)
+#define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \brief (GMAC_SVLAN) MASK Register */
+
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) (R/W 32) Transmit PFC Pause Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEV:8; /*!< bit: 0.. 7 Priority Enable Vector */
+ uint32_t PQ:8; /*!< bit: 8..15 Pause Quantum */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TPFCP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPFCP_OFFSET 0x0C4 /**< \brief (GMAC_TPFCP offset) Transmit PFC Pause Register */
+#define GMAC_TPFCP_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TPFCP reset_value) Transmit PFC Pause Register */
+
+#define GMAC_TPFCP_PEV_Pos 0 /**< \brief (GMAC_TPFCP) Priority Enable Vector */
+#define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos)
+#define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))
+#define GMAC_TPFCP_PQ_Pos 8 /**< \brief (GMAC_TPFCP) Pause Quantum */
+#define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos)
+#define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))
+#define GMAC_TPFCP_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TPFCP) MASK Register */
+
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Specific Address 1 Mask */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAMB1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAMB1_OFFSET 0x0C8 /**< \brief (GMAC_SAMB1 offset) Specific Address 1 Mask Bottom [31:0] Register */
+#define GMAC_SAMB1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMB1 reset_value) Specific Address 1 Mask Bottom [31:0] Register */
+
+#define GMAC_SAMB1_ADDR_Pos 0 /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
+#define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos)
+#define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))
+#define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SAMB1) MASK Register */
+
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:16; /*!< bit: 0..15 Specific Address 1 Mask */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SAMT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAMT1_OFFSET 0x0CC /**< \brief (GMAC_SAMT1 offset) Specific Address 1 Mask Top [47:32] Register */
+#define GMAC_SAMT1_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SAMT1 reset_value) Specific Address 1 Mask Top [47:32] Register */
+
+#define GMAC_SAMT1_ADDR_Pos 0 /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
+#define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos)
+#define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))
+#define GMAC_SAMT1_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SAMT1) MASK Register */
+
+/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NANOSEC:21; /*!< bit: 0..20 1588 Timer Nanosecond comparison value */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_NSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NSC_OFFSET 0x0DC /**< \brief (GMAC_NSC offset) Tsu timer comparison nanoseconds Register */
+#define GMAC_NSC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_NSC reset_value) Tsu timer comparison nanoseconds Register */
+
+#define GMAC_NSC_NANOSEC_Pos 0 /**< \brief (GMAC_NSC) 1588 Timer Nanosecond comparison value */
+#define GMAC_NSC_NANOSEC_Msk (_U_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos)
+#define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))
+#define GMAC_NSC_MASK _U_(0x001FFFFF) /**< \brief (GMAC_NSC) MASK Register */
+
+/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) (R/W 32) Tsu timer second comparison Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SEC:32; /*!< bit: 0..31 1588 Timer Second comparison value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SCL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCL_OFFSET 0x0E0 /**< \brief (GMAC_SCL offset) Tsu timer second comparison Register */
+#define GMAC_SCL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCL reset_value) Tsu timer second comparison Register */
+
+#define GMAC_SCL_SEC_Pos 0 /**< \brief (GMAC_SCL) 1588 Timer Second comparison value */
+#define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos)
+#define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))
+#define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_SCL) MASK Register */
+
+/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) (R/W 32) Tsu timer second comparison Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SEC:16; /*!< bit: 0..15 1588 Timer Second comparison value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCH_OFFSET 0x0E4 /**< \brief (GMAC_SCH offset) Tsu timer second comparison Register */
+#define GMAC_SCH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCH reset_value) Tsu timer second comparison Register */
+
+#define GMAC_SCH_SEC_Pos 0 /**< \brief (GMAC_SCH) 1588 Timer Second comparison value */
+#define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos)
+#define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))
+#define GMAC_SCH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_SCH) MASK Register */
+
+/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFTSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTSH_OFFSET 0x0E8 /**< \brief (GMAC_EFTSH offset) PTP Event Frame Transmitted Seconds High Register */
+#define GMAC_EFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSH reset_value) PTP Event Frame Transmitted Seconds High Register */
+
+#define GMAC_EFTSH_RUD_Pos 0 /**< \brief (GMAC_EFTSH) Register Update */
+#define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos)
+#define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos))
+#define GMAC_EFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFTSH) MASK Register */
+
+/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) (R/ 32) PTP Event Frame Received Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFRSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRSH_OFFSET 0x0EC /**< \brief (GMAC_EFRSH offset) PTP Event Frame Received Seconds High Register */
+#define GMAC_EFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSH reset_value) PTP Event Frame Received Seconds High Register */
+
+#define GMAC_EFRSH_RUD_Pos 0 /**< \brief (GMAC_EFRSH) Register Update */
+#define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos)
+#define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos))
+#define GMAC_EFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_EFRSH) MASK Register */
+
+/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFTSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTSH_OFFSET 0x0F0 /**< \brief (GMAC_PEFTSH offset) PTP Peer Event Frame Transmitted Seconds High Register */
+#define GMAC_PEFTSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSH reset_value) PTP Peer Event Frame Transmitted Seconds High Register */
+
+#define GMAC_PEFTSH_RUD_Pos 0 /**< \brief (GMAC_PEFTSH) Register Update */
+#define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos)
+#define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos))
+#define GMAC_PEFTSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFTSH) MASK Register */
+
+/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:16; /*!< bit: 0..15 Register Update */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFRSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRSH_OFFSET 0x0F4 /**< \brief (GMAC_PEFRSH offset) PTP Peer Event Frame Received Seconds High Register */
+#define GMAC_PEFRSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSH reset_value) PTP Peer Event Frame Received Seconds High Register */
+
+#define GMAC_PEFRSH_RUD_Pos 0 /**< \brief (GMAC_PEFRSH) Register Update */
+#define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos)
+#define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos))
+#define GMAC_PEFRSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PEFRSH) MASK Register */
+
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXO:32; /*!< bit: 0..31 Transmitted Octets */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_OTLO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OTLO_OFFSET 0x100 /**< \brief (GMAC_OTLO offset) Octets Transmitted [31:0] Register */
+#define GMAC_OTLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTLO reset_value) Octets Transmitted [31:0] Register */
+
+#define GMAC_OTLO_TXO_Pos 0 /**< \brief (GMAC_OTLO) Transmitted Octets */
+#define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos)
+#define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos))
+#define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_OTLO) MASK Register */
+
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXO:16; /*!< bit: 0..15 Transmitted Octets */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_OTHI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OTHI_OFFSET 0x104 /**< \brief (GMAC_OTHI offset) Octets Transmitted [47:32] Register */
+#define GMAC_OTHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OTHI reset_value) Octets Transmitted [47:32] Register */
+
+#define GMAC_OTHI_TXO_Pos 0 /**< \brief (GMAC_OTHI) Transmitted Octets */
+#define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos)
+#define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos))
+#define GMAC_OTHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_OTHI) MASK Register */
+
+/* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FTX:32; /*!< bit: 0..31 Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_FT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FT_OFFSET 0x108 /**< \brief (GMAC_FT offset) Frames Transmitted Register */
+#define GMAC_FT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FT reset_value) Frames Transmitted Register */
+
+#define GMAC_FT_FTX_Pos 0 /**< \brief (GMAC_FT) Frames Transmitted without Error */
+#define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos)
+#define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos))
+#define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FT) MASK Register */
+
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) (R/ 32) Broadcast Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BFTX:32; /*!< bit: 0..31 Broadcast Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BCFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BCFT_OFFSET 0x10C /**< \brief (GMAC_BCFT offset) Broadcast Frames Transmitted Register */
+#define GMAC_BCFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFT reset_value) Broadcast Frames Transmitted Register */
+
+#define GMAC_BCFT_BFTX_Pos 0 /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
+#define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos)
+#define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos))
+#define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFT) MASK Register */
+
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFTX:32; /*!< bit: 0..31 Multicast Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MFT_OFFSET 0x110 /**< \brief (GMAC_MFT offset) Multicast Frames Transmitted Register */
+#define GMAC_MFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFT reset_value) Multicast Frames Transmitted Register */
+
+#define GMAC_MFT_MFTX_Pos 0 /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
+#define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos)
+#define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos))
+#define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFT) MASK Register */
+
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PFTX:16; /*!< bit: 0..15 Pause Frames Transmitted Register */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PFT_OFFSET 0x114 /**< \brief (GMAC_PFT offset) Pause Frames Transmitted Register */
+#define GMAC_PFT_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFT reset_value) Pause Frames Transmitted Register */
+
+#define GMAC_PFT_PFTX_Pos 0 /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
+#define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos)
+#define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos))
+#define GMAC_PFT_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFT) MASK Register */
+
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 64 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BFT64_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BFT64_OFFSET 0x118 /**< \brief (GMAC_BFT64 offset) 64 Byte Frames Transmitted Register */
+#define GMAC_BFT64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFT64 reset_value) 64 Byte Frames Transmitted Register */
+
+#define GMAC_BFT64_NFTX_Pos 0 /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
+#define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos)
+#define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos))
+#define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFT64) MASK Register */
+
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT127_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT127_OFFSET 0x11C /**< \brief (GMAC_TBFT127 offset) 65 to 127 Byte Frames Transmitted Register */
+#define GMAC_TBFT127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT127 reset_value) 65 to 127 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT127_NFTX_Pos 0 /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
+#define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos)
+#define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos))
+#define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT127) MASK Register */
+
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT255_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT255_OFFSET 0x120 /**< \brief (GMAC_TBFT255 offset) 128 to 255 Byte Frames Transmitted Register */
+#define GMAC_TBFT255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT255 reset_value) 128 to 255 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT255_NFTX_Pos 0 /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
+#define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos)
+#define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos))
+#define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT255) MASK Register */
+
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT511_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT511_OFFSET 0x124 /**< \brief (GMAC_TBFT511 offset) 256 to 511 Byte Frames Transmitted Register */
+#define GMAC_TBFT511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT511 reset_value) 256 to 511 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT511_NFTX_Pos 0 /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
+#define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos)
+#define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos))
+#define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT511) MASK Register */
+
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT1023_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT1023_OFFSET 0x128 /**< \brief (GMAC_TBFT1023 offset) 512 to 1023 Byte Frames Transmitted Register */
+#define GMAC_TBFT1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1023 reset_value) 512 to 1023 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT1023_NFTX_Pos 0 /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
+#define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos)
+#define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos))
+#define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1023) MASK Register */
+
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFT1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT1518_OFFSET 0x12C /**< \brief (GMAC_TBFT1518 offset) 1024 to 1518 Byte Frames Transmitted Register */
+#define GMAC_TBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFT1518 reset_value) 1024 to 1518 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT1518_NFTX_Pos 0 /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
+#define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos)
+#define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos))
+#define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1518) MASK Register */
+
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFTX:32; /*!< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_GTBFT1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_GTBFT1518_OFFSET 0x130 /**< \brief (GMAC_GTBFT1518 offset) Greater Than 1518 Byte Frames Transmitted Register */
+#define GMAC_GTBFT1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_GTBFT1518 reset_value) Greater Than 1518 Byte Frames Transmitted Register */
+
+#define GMAC_GTBFT1518_NFTX_Pos 0 /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
+#define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos)
+#define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos))
+#define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_GTBFT1518) MASK Register */
+
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TXUNR:10; /*!< bit: 0.. 9 Transmit Underruns */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TUR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TUR_OFFSET 0x134 /**< \brief (GMAC_TUR offset) Transmit Underruns Register */
+#define GMAC_TUR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TUR reset_value) Transmit Underruns Register */
+
+#define GMAC_TUR_TXUNR_Pos 0 /**< \brief (GMAC_TUR) Transmit Underruns */
+#define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos)
+#define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos))
+#define GMAC_TUR_MASK _U_(0x000003FF) /**< \brief (GMAC_TUR) MASK Register */
+
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SCOL:18; /*!< bit: 0..17 Single Collision */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_SCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCF_OFFSET 0x138 /**< \brief (GMAC_SCF offset) Single Collision Frames Register */
+#define GMAC_SCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_SCF reset_value) Single Collision Frames Register */
+
+#define GMAC_SCF_SCOL_Pos 0 /**< \brief (GMAC_SCF) Single Collision */
+#define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos)
+#define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos))
+#define GMAC_SCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_SCF) MASK Register */
+
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) (R/ 32) Multiple Collision Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MCOL:18; /*!< bit: 0..17 Multiple Collision */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MCF_OFFSET 0x13C /**< \brief (GMAC_MCF offset) Multiple Collision Frames Register */
+#define GMAC_MCF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MCF reset_value) Multiple Collision Frames Register */
+
+#define GMAC_MCF_MCOL_Pos 0 /**< \brief (GMAC_MCF) Multiple Collision */
+#define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos)
+#define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos))
+#define GMAC_MCF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_MCF) MASK Register */
+
+/* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XCOL:10; /*!< bit: 0.. 9 Excessive Collisions */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EC_OFFSET 0x140 /**< \brief (GMAC_EC offset) Excessive Collisions Register */
+#define GMAC_EC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EC reset_value) Excessive Collisions Register */
+
+#define GMAC_EC_XCOL_Pos 0 /**< \brief (GMAC_EC) Excessive Collisions */
+#define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos)
+#define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos))
+#define GMAC_EC_MASK _U_(0x000003FF) /**< \brief (GMAC_EC) MASK Register */
+
+/* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LCOL:10; /*!< bit: 0.. 9 Late Collisions */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_LC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_LC_OFFSET 0x144 /**< \brief (GMAC_LC offset) Late Collisions Register */
+#define GMAC_LC_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LC reset_value) Late Collisions Register */
+
+#define GMAC_LC_LCOL_Pos 0 /**< \brief (GMAC_LC) Late Collisions */
+#define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos)
+#define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos))
+#define GMAC_LC_MASK _U_(0x000003FF) /**< \brief (GMAC_LC) MASK Register */
+
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEFT:18; /*!< bit: 0..17 Deferred Transmission */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_DTF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_DTF_OFFSET 0x148 /**< \brief (GMAC_DTF offset) Deferred Transmission Frames Register */
+#define GMAC_DTF_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_DTF reset_value) Deferred Transmission Frames Register */
+
+#define GMAC_DTF_DEFT_Pos 0 /**< \brief (GMAC_DTF) Deferred Transmission */
+#define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos)
+#define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos))
+#define GMAC_DTF_MASK _U_(0x0003FFFF) /**< \brief (GMAC_DTF) MASK Register */
+
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) (R/ 32) Carrier Sense Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CSR:10; /*!< bit: 0.. 9 Carrier Sense Error */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_CSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_CSE_OFFSET 0x14C /**< \brief (GMAC_CSE offset) Carrier Sense Errors Register */
+#define GMAC_CSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_CSE reset_value) Carrier Sense Errors Register */
+
+#define GMAC_CSE_CSR_Pos 0 /**< \brief (GMAC_CSE) Carrier Sense Error */
+#define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos)
+#define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos))
+#define GMAC_CSE_MASK _U_(0x000003FF) /**< \brief (GMAC_CSE) MASK Register */
+
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received [31:0] Received -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXO:32; /*!< bit: 0..31 Received Octets */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ORLO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ORLO_OFFSET 0x150 /**< \brief (GMAC_ORLO offset) Octets Received [31:0] Received */
+#define GMAC_ORLO_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORLO reset_value) Octets Received [31:0] Received */
+
+#define GMAC_ORLO_RXO_Pos 0 /**< \brief (GMAC_ORLO) Received Octets */
+#define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos)
+#define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos))
+#define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_ORLO) MASK Register */
+
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received [47:32] Received -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXO:16; /*!< bit: 0..15 Received Octets */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ORHI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ORHI_OFFSET 0x154 /**< \brief (GMAC_ORHI offset) Octets Received [47:32] Received */
+#define GMAC_ORHI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ORHI reset_value) Octets Received [47:32] Received */
+
+#define GMAC_ORHI_RXO_Pos 0 /**< \brief (GMAC_ORHI) Received Octets */
+#define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos)
+#define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos))
+#define GMAC_ORHI_MASK _U_(0x0000FFFF) /**< \brief (GMAC_ORHI) MASK Register */
+
+/* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FRX:32; /*!< bit: 0..31 Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_FR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FR_OFFSET 0x158 /**< \brief (GMAC_FR offset) Frames Received Register */
+#define GMAC_FR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FR reset_value) Frames Received Register */
+
+#define GMAC_FR_FRX_Pos 0 /**< \brief (GMAC_FR) Frames Received without Error */
+#define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos)
+#define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos))
+#define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_FR) MASK Register */
+
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) (R/ 32) Broadcast Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BFRX:32; /*!< bit: 0..31 Broadcast Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BCFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BCFR_OFFSET 0x15C /**< \brief (GMAC_BCFR offset) Broadcast Frames Received Register */
+#define GMAC_BCFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BCFR reset_value) Broadcast Frames Received Register */
+
+#define GMAC_BCFR_BFRX_Pos 0 /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
+#define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos)
+#define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos))
+#define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFR) MASK Register */
+
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MFRX:32; /*!< bit: 0..31 Multicast Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_MFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MFR_OFFSET 0x160 /**< \brief (GMAC_MFR offset) Multicast Frames Received Register */
+#define GMAC_MFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_MFR reset_value) Multicast Frames Received Register */
+
+#define GMAC_MFR_MFRX_Pos 0 /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
+#define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos)
+#define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos))
+#define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_MFR) MASK Register */
+
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PFRX:16; /*!< bit: 0..15 Pause Frames Received Register */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PFR_OFFSET 0x164 /**< \brief (GMAC_PFR offset) Pause Frames Received Register */
+#define GMAC_PFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PFR reset_value) Pause Frames Received Register */
+
+#define GMAC_PFR_PFRX_Pos 0 /**< \brief (GMAC_PFR) Pause Frames Received Register */
+#define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos)
+#define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos))
+#define GMAC_PFR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_PFR) MASK Register */
+
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 64 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_BFR64_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BFR64_OFFSET 0x168 /**< \brief (GMAC_BFR64 offset) 64 Byte Frames Received Register */
+#define GMAC_BFR64_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_BFR64 reset_value) 64 Byte Frames Received Register */
+
+#define GMAC_BFR64_NFRX_Pos 0 /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
+#define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos)
+#define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos))
+#define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_BFR64) MASK Register */
+
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) (R/ 32) 65 to 127 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 65 to 127 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR127_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR127_OFFSET 0x16C /**< \brief (GMAC_TBFR127 offset) 65 to 127 Byte Frames Received Register */
+#define GMAC_TBFR127_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR127 reset_value) 65 to 127 Byte Frames Received Register */
+
+#define GMAC_TBFR127_NFRX_Pos 0 /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
+#define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos)
+#define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos))
+#define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR127) MASK Register */
+
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 128 to 255 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR255_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR255_OFFSET 0x170 /**< \brief (GMAC_TBFR255 offset) 128 to 255 Byte Frames Received Register */
+#define GMAC_TBFR255_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR255 reset_value) 128 to 255 Byte Frames Received Register */
+
+#define GMAC_TBFR255_NFRX_Pos 0 /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
+#define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos)
+#define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos))
+#define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR255) MASK Register */
+
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 256 to 511 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR511_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR511_OFFSET 0x174 /**< \brief (GMAC_TBFR511 offset) 256 to 511Byte Frames Received Register */
+#define GMAC_TBFR511_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR511 reset_value) 256 to 511Byte Frames Received Register */
+
+#define GMAC_TBFR511_NFRX_Pos 0 /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
+#define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos)
+#define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos))
+#define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR511) MASK Register */
+
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 512 to 1023 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR1023_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR1023_OFFSET 0x178 /**< \brief (GMAC_TBFR1023 offset) 512 to 1023 Byte Frames Received Register */
+#define GMAC_TBFR1023_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1023 reset_value) 512 to 1023 Byte Frames Received Register */
+
+#define GMAC_TBFR1023_NFRX_Pos 0 /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
+#define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos)
+#define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos))
+#define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1023) MASK Register */
+
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 1024 to 1518 Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TBFR1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR1518_OFFSET 0x17C /**< \brief (GMAC_TBFR1518 offset) 1024 to 1518 Byte Frames Received Register */
+#define GMAC_TBFR1518_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TBFR1518 reset_value) 1024 to 1518 Byte Frames Received Register */
+
+#define GMAC_TBFR1518_NFRX_Pos 0 /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
+#define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos)
+#define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos))
+#define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1518) MASK Register */
+
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NFRX:32; /*!< bit: 0..31 1519 to Maximum Byte Frames Received without Error */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TMXBFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TMXBFR_OFFSET 0x180 /**< \brief (GMAC_TMXBFR offset) 1519 to Maximum Byte Frames Received Register */
+#define GMAC_TMXBFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TMXBFR reset_value) 1519 to Maximum Byte Frames Received Register */
+
+#define GMAC_TMXBFR_NFRX_Pos 0 /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
+#define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos)
+#define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos))
+#define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TMXBFR) MASK Register */
+
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t UFRX:10; /*!< bit: 0.. 9 Undersize Frames Received */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_UFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UFR_OFFSET 0x184 /**< \brief (GMAC_UFR offset) Undersize Frames Received Register */
+#define GMAC_UFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UFR reset_value) Undersize Frames Received Register */
+
+#define GMAC_UFR_UFRX_Pos 0 /**< \brief (GMAC_UFR) Undersize Frames Received */
+#define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos)
+#define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos))
+#define GMAC_UFR_MASK _U_(0x000003FF) /**< \brief (GMAC_UFR) MASK Register */
+
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OFRX:10; /*!< bit: 0.. 9 Oversized Frames Received */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_OFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OFR_OFFSET 0x188 /**< \brief (GMAC_OFR offset) Oversize Frames Received Register */
+#define GMAC_OFR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_OFR reset_value) Oversize Frames Received Register */
+
+#define GMAC_OFR_OFRX_Pos 0 /**< \brief (GMAC_OFR) Oversized Frames Received */
+#define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos)
+#define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos))
+#define GMAC_OFR_MASK _U_(0x000003FF) /**< \brief (GMAC_OFR) MASK Register */
+
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) (R/ 32) Jabbers Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JRX:10; /*!< bit: 0.. 9 Jabbers Received */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_JR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_JR_OFFSET 0x18C /**< \brief (GMAC_JR offset) Jabbers Received Register */
+#define GMAC_JR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_JR reset_value) Jabbers Received Register */
+
+#define GMAC_JR_JRX_Pos 0 /**< \brief (GMAC_JR) Jabbers Received */
+#define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos)
+#define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos))
+#define GMAC_JR_MASK _U_(0x000003FF) /**< \brief (GMAC_JR) MASK Register */
+
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FCKR:10; /*!< bit: 0.. 9 Frame Check Sequence Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_FCSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FCSE_OFFSET 0x190 /**< \brief (GMAC_FCSE offset) Frame Check Sequence Errors Register */
+#define GMAC_FCSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_FCSE reset_value) Frame Check Sequence Errors Register */
+
+#define GMAC_FCSE_FCKR_Pos 0 /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
+#define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos)
+#define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos))
+#define GMAC_FCSE_MASK _U_(0x000003FF) /**< \brief (GMAC_FCSE) MASK Register */
+
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LFER:10; /*!< bit: 0.. 9 Length Field Frame Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_LFFE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_LFFE_OFFSET 0x194 /**< \brief (GMAC_LFFE offset) Length Field Frame Errors Register */
+#define GMAC_LFFE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_LFFE reset_value) Length Field Frame Errors Register */
+
+#define GMAC_LFFE_LFER_Pos 0 /**< \brief (GMAC_LFFE) Length Field Frame Errors */
+#define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos)
+#define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos))
+#define GMAC_LFFE_MASK _U_(0x000003FF) /**< \brief (GMAC_LFFE) MASK Register */
+
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXSE:10; /*!< bit: 0.. 9 Receive Symbol Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RSE_OFFSET 0x198 /**< \brief (GMAC_RSE offset) Receive Symbol Errors Register */
+#define GMAC_RSE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RSE reset_value) Receive Symbol Errors Register */
+
+#define GMAC_RSE_RXSE_Pos 0 /**< \brief (GMAC_RSE) Receive Symbol Errors */
+#define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos)
+#define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos))
+#define GMAC_RSE_MASK _U_(0x000003FF) /**< \brief (GMAC_RSE) MASK Register */
+
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) (R/ 32) Alignment Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AER:10; /*!< bit: 0.. 9 Alignment Errors */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_AE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_AE_OFFSET 0x19C /**< \brief (GMAC_AE offset) Alignment Errors Register */
+#define GMAC_AE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_AE reset_value) Alignment Errors Register */
+
+#define GMAC_AE_AER_Pos 0 /**< \brief (GMAC_AE) Alignment Errors */
+#define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos)
+#define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos))
+#define GMAC_AE_MASK _U_(0x000003FF) /**< \brief (GMAC_AE) MASK Register */
+
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) (R/ 32) Receive Resource Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXRER:18; /*!< bit: 0..17 Receive Resource Errors */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RRE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RRE_OFFSET 0x1A0 /**< \brief (GMAC_RRE offset) Receive Resource Errors Register */
+#define GMAC_RRE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RRE reset_value) Receive Resource Errors Register */
+
+#define GMAC_RRE_RXRER_Pos 0 /**< \brief (GMAC_RRE) Receive Resource Errors */
+#define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos)
+#define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos))
+#define GMAC_RRE_MASK _U_(0x0003FFFF) /**< \brief (GMAC_RRE) MASK Register */
+
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) (R/ 32) Receive Overrun Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXOVR:10; /*!< bit: 0.. 9 Receive Overruns */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_ROE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ROE_OFFSET 0x1A4 /**< \brief (GMAC_ROE offset) Receive Overrun Register */
+#define GMAC_ROE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_ROE reset_value) Receive Overrun Register */
+
+#define GMAC_ROE_RXOVR_Pos 0 /**< \brief (GMAC_ROE) Receive Overruns */
+#define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos)
+#define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos))
+#define GMAC_ROE_MASK _U_(0x000003FF) /**< \brief (GMAC_ROE) MASK Register */
+
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) (R/ 32) IP Header Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HCKER:8; /*!< bit: 0.. 7 IP Header Checksum Errors */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_IHCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IHCE_OFFSET 0x1A8 /**< \brief (GMAC_IHCE offset) IP Header Checksum Errors Register */
+#define GMAC_IHCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_IHCE reset_value) IP Header Checksum Errors Register */
+
+#define GMAC_IHCE_HCKER_Pos 0 /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
+#define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos)
+#define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos))
+#define GMAC_IHCE_MASK _U_(0x000000FF) /**< \brief (GMAC_IHCE) MASK Register */
+
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) (R/ 32) TCP Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TCKER:8; /*!< bit: 0.. 7 TCP Checksum Errors */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TCE_OFFSET 0x1AC /**< \brief (GMAC_TCE offset) TCP Checksum Errors Register */
+#define GMAC_TCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TCE reset_value) TCP Checksum Errors Register */
+
+#define GMAC_TCE_TCKER_Pos 0 /**< \brief (GMAC_TCE) TCP Checksum Errors */
+#define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos)
+#define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos))
+#define GMAC_TCE_MASK _U_(0x000000FF) /**< \brief (GMAC_TCE) MASK Register */
+
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) (R/ 32) UDP Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t UCKER:8; /*!< bit: 0.. 7 UDP Checksum Errors */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_UCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UCE_OFFSET 0x1B0 /**< \brief (GMAC_UCE offset) UDP Checksum Errors Register */
+#define GMAC_UCE_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_UCE reset_value) UDP Checksum Errors Register */
+
+#define GMAC_UCE_UCKER_Pos 0 /**< \brief (GMAC_UCE) UDP Checksum Errors */
+#define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos)
+#define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos))
+#define GMAC_UCE_MASK _U_(0x000000FF) /**< \brief (GMAC_UCE) MASK Register */
+
+/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LSBTIR:16; /*!< bit: 0..15 Lower Significant Bits of Timer Increment */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TISUBN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TISUBN_OFFSET 0x1BC /**< \brief (GMAC_TISUBN offset) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define GMAC_TISUBN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TISUBN reset_value) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+
+#define GMAC_TISUBN_LSBTIR_Pos 0 /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment */
+#define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos)
+#define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))
+#define GMAC_TISUBN_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TISUBN) MASK Register */
+
+/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TCS:16; /*!< bit: 0..15 Timer Count in Seconds */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSH_OFFSET 0x1C0 /**< \brief (GMAC_TSH offset) 1588 Timer Seconds High [15:0] Register */
+#define GMAC_TSH_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSH reset_value) 1588 Timer Seconds High [15:0] Register */
+
+#define GMAC_TSH_TCS_Pos 0 /**< \brief (GMAC_TSH) Timer Count in Seconds */
+#define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos)
+#define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))
+#define GMAC_TSH_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TSH) MASK Register */
+
+/* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VTS:32; /*!< bit: 0..31 Value of Timer Seconds Register Capture */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSSSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSSSL_OFFSET 0x1C8 /**< \brief (GMAC_TSSSL offset) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define GMAC_TSSSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSSL reset_value) 1588 Timer Sync Strobe Seconds [31:0] Register */
+
+#define GMAC_TSSSL_VTS_Pos 0 /**< \brief (GMAC_TSSSL) Value of Timer Seconds Register Capture */
+#define GMAC_TSSSL_VTS_Msk (_U_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos)
+#define GMAC_TSSSL_VTS(value) (GMAC_TSSSL_VTS_Msk & ((value) << GMAC_TSSSL_VTS_Pos))
+#define GMAC_TSSSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSSSL) MASK Register */
+
+/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VTN:30; /*!< bit: 0..29 Value Timer Nanoseconds Register Capture */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSSN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSSN_OFFSET 0x1CC /**< \brief (GMAC_TSSN offset) 1588 Timer Sync Strobe Nanoseconds Register */
+#define GMAC_TSSN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSSN reset_value) 1588 Timer Sync Strobe Nanoseconds Register */
+
+#define GMAC_TSSN_VTN_Pos 0 /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */
+#define GMAC_TSSN_VTN_Msk (_U_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos)
+#define GMAC_TSSN_VTN(value) (GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))
+#define GMAC_TSSN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TSSN) MASK Register */
+
+/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TCS:32; /*!< bit: 0..31 Timer Count in Seconds */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSL_OFFSET 0x1D0 /**< \brief (GMAC_TSL offset) 1588 Timer Seconds [31:0] Register */
+#define GMAC_TSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TSL reset_value) 1588 Timer Seconds [31:0] Register */
+
+#define GMAC_TSL_TCS_Pos 0 /**< \brief (GMAC_TSL) Timer Count in Seconds */
+#define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos)
+#define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))
+#define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_TSL) MASK Register */
+
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TNS:30; /*!< bit: 0..29 Timer Count in Nanoseconds */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TN_OFFSET 0x1D4 /**< \brief (GMAC_TN offset) 1588 Timer Nanoseconds Register */
+#define GMAC_TN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TN reset_value) 1588 Timer Nanoseconds Register */
+
+#define GMAC_TN_TNS_Pos 0 /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
+#define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos)
+#define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))
+#define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_TN) MASK Register */
+
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ITDT:30; /*!< bit: 0..29 Increment/Decrement */
+ uint32_t :1; /*!< bit: 30 Reserved */
+ uint32_t ADJ:1; /*!< bit: 31 Adjust 1588 Timer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TA_OFFSET 0x1D8 /**< \brief (GMAC_TA offset) 1588 Timer Adjust Register */
+#define GMAC_TA_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TA reset_value) 1588 Timer Adjust Register */
+
+#define GMAC_TA_ITDT_Pos 0 /**< \brief (GMAC_TA) Increment/Decrement */
+#define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos)
+#define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))
+#define GMAC_TA_ADJ_Pos 31 /**< \brief (GMAC_TA) Adjust 1588 Timer */
+#define GMAC_TA_ADJ (_U_(0x1) << GMAC_TA_ADJ_Pos)
+#define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \brief (GMAC_TA) MASK Register */
+
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CNS:8; /*!< bit: 0.. 7 Count Nanoseconds */
+ uint32_t ACNS:8; /*!< bit: 8..15 Alternative Count Nanoseconds */
+ uint32_t NIT:8; /*!< bit: 16..23 Number of Increments */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TI_OFFSET 0x1DC /**< \brief (GMAC_TI offset) 1588 Timer Increment Register */
+#define GMAC_TI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TI reset_value) 1588 Timer Increment Register */
+
+#define GMAC_TI_CNS_Pos 0 /**< \brief (GMAC_TI) Count Nanoseconds */
+#define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos)
+#define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))
+#define GMAC_TI_ACNS_Pos 8 /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
+#define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos)
+#define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))
+#define GMAC_TI_NIT_Pos 16 /**< \brief (GMAC_TI) Number of Increments */
+#define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos)
+#define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))
+#define GMAC_TI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TI) MASK Register */
+
+/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFTSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTSL_OFFSET 0x1E0 /**< \brief (GMAC_EFTSL offset) PTP Event Frame Transmitted Seconds Low Register */
+#define GMAC_EFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTSL reset_value) PTP Event Frame Transmitted Seconds Low Register */
+
+#define GMAC_EFTSL_RUD_Pos 0 /**< \brief (GMAC_EFTSL) Register Update */
+#define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos)
+#define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos))
+#define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFTSL) MASK Register */
+
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) (R/ 32) PTP Event Frame Transmitted Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFTN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTN_OFFSET 0x1E4 /**< \brief (GMAC_EFTN offset) PTP Event Frame Transmitted Nanoseconds */
+#define GMAC_EFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFTN reset_value) PTP Event Frame Transmitted Nanoseconds */
+
+#define GMAC_EFTN_RUD_Pos 0 /**< \brief (GMAC_EFTN) Register Update */
+#define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos)
+#define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos))
+#define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFTN) MASK Register */
+
+/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFRSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRSL_OFFSET 0x1E8 /**< \brief (GMAC_EFRSL offset) PTP Event Frame Received Seconds Low Register */
+#define GMAC_EFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRSL reset_value) PTP Event Frame Received Seconds Low Register */
+
+#define GMAC_EFRSL_RUD_Pos 0 /**< \brief (GMAC_EFRSL) Register Update */
+#define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos)
+#define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos))
+#define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_EFRSL) MASK Register */
+
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) (R/ 32) PTP Event Frame Received Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_EFRN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRN_OFFSET 0x1EC /**< \brief (GMAC_EFRN offset) PTP Event Frame Received Nanoseconds */
+#define GMAC_EFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_EFRN reset_value) PTP Event Frame Received Nanoseconds */
+
+#define GMAC_EFRN_RUD_Pos 0 /**< \brief (GMAC_EFRN) Register Update */
+#define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos)
+#define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos))
+#define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_EFRN) MASK Register */
+
+/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFTSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTSL_OFFSET 0x1F0 /**< \brief (GMAC_PEFTSL offset) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define GMAC_PEFTSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTSL reset_value) PTP Peer Event Frame Transmitted Seconds Low Register */
+
+#define GMAC_PEFTSL_RUD_Pos 0 /**< \brief (GMAC_PEFTSL) Register Update */
+#define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos)
+#define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos))
+#define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFTSL) MASK Register */
+
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFTN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTN_OFFSET 0x1F4 /**< \brief (GMAC_PEFTN offset) PTP Peer Event Frame Transmitted Nanoseconds */
+#define GMAC_PEFTN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFTN reset_value) PTP Peer Event Frame Transmitted Nanoseconds */
+
+#define GMAC_PEFTN_RUD_Pos 0 /**< \brief (GMAC_PEFTN) Register Update */
+#define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos)
+#define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos))
+#define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFTN) MASK Register */
+
+/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:32; /*!< bit: 0..31 Register Update */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFRSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRSL_OFFSET 0x1F8 /**< \brief (GMAC_PEFRSL offset) PTP Peer Event Frame Received Seconds Low Register */
+#define GMAC_PEFRSL_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRSL reset_value) PTP Peer Event Frame Received Seconds Low Register */
+
+#define GMAC_PEFRSL_RUD_Pos 0 /**< \brief (GMAC_PEFRSL) Register Update */
+#define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos)
+#define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos))
+#define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFRSL) MASK Register */
+
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) (R/ 32) PTP Peer Event Frame Received Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUD:30; /*!< bit: 0..29 Register Update */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_PEFRN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRN_OFFSET 0x1FC /**< \brief (GMAC_PEFRN offset) PTP Peer Event Frame Received Nanoseconds */
+#define GMAC_PEFRN_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_PEFRN reset_value) PTP Peer Event Frame Received Nanoseconds */
+
+#define GMAC_PEFRN_RUD_Pos 0 /**< \brief (GMAC_PEFRN) Register Update */
+#define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos)
+#define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos))
+#define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFRN) MASK Register */
+
+/* -------- GMAC_RLPITR : (GMAC Offset: 0x270) (R/ 32) Receive LPI transition Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RLPITR:16; /*!< bit: 0..15 Count number of times transition from rx normal idle to low power idle */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RLPITR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RLPITR_OFFSET 0x270 /**< \brief (GMAC_RLPITR offset) Receive LPI transition Register */
+#define GMAC_RLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITR reset_value) Receive LPI transition Register */
+
+#define GMAC_RLPITR_RLPITR_Pos 0 /**< \brief (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle */
+#define GMAC_RLPITR_RLPITR_Msk (_U_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos)
+#define GMAC_RLPITR_RLPITR(value) (GMAC_RLPITR_RLPITR_Msk & ((value) << GMAC_RLPITR_RLPITR_Pos))
+#define GMAC_RLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_RLPITR) MASK Register */
+
+/* -------- GMAC_RLPITI : (GMAC Offset: 0x274) (R/ 32) Receive LPI Time Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_RLPITI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RLPITI_OFFSET 0x274 /**< \brief (GMAC_RLPITI offset) Receive LPI Time Register */
+#define GMAC_RLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_RLPITI reset_value) Receive LPI Time Register */
+
+#define GMAC_RLPITI_RLPITI_Pos 0 /**< \brief (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
+#define GMAC_RLPITI_RLPITI_Msk (_U_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos)
+#define GMAC_RLPITI_RLPITI(value) (GMAC_RLPITI_RLPITI_Msk & ((value) << GMAC_RLPITI_RLPITI_Pos))
+#define GMAC_RLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_RLPITI) MASK Register */
+
+/* -------- GMAC_TLPITR : (GMAC Offset: 0x278) (R/ 32) Receive LPI transition Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TLPITR:16; /*!< bit: 0..15 Count number of times enable LPI tx bit 20 goes from low to high */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TLPITR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TLPITR_OFFSET 0x278 /**< \brief (GMAC_TLPITR offset) Receive LPI transition Register */
+#define GMAC_TLPITR_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITR reset_value) Receive LPI transition Register */
+
+#define GMAC_TLPITR_TLPITR_Pos 0 /**< \brief (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high */
+#define GMAC_TLPITR_TLPITR_Msk (_U_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos)
+#define GMAC_TLPITR_TLPITR(value) (GMAC_TLPITR_TLPITR_Msk & ((value) << GMAC_TLPITR_TLPITR_Pos))
+#define GMAC_TLPITR_MASK _U_(0x0000FFFF) /**< \brief (GMAC_TLPITR) MASK Register */
+
+/* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) (R/ 32) Receive LPI Time Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TLPITI:24; /*!< bit: 0..23 Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GMAC_TLPITI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TLPITI_OFFSET 0x27C /**< \brief (GMAC_TLPITI offset) Receive LPI Time Register */
+#define GMAC_TLPITI_RESETVALUE _U_(0x00000000) /**< \brief (GMAC_TLPITI reset_value) Receive LPI Time Register */
+
+#define GMAC_TLPITI_TLPITI_Pos 0 /**< \brief (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
+#define GMAC_TLPITI_TLPITI_Msk (_U_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos)
+#define GMAC_TLPITI_TLPITI(value) (GMAC_TLPITI_TLPITI_Msk & ((value) << GMAC_TLPITI_TLPITI_Pos))
+#define GMAC_TLPITI_MASK _U_(0x00FFFFFF) /**< \brief (GMAC_TLPITI) MASK Register */
+
+/** \brief GmacSa hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GMAC_SAB_Type SAB; /**< \brief Offset: 0x000 (R/W 32) Specific Address Bottom [31:0] Register */
+ __IO GMAC_SAT_Type SAT; /**< \brief Offset: 0x004 (R/W 32) Specific Address Top [47:32] Register */
+} GmacSa;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief GMAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GMAC_NCR_Type NCR; /**< \brief Offset: 0x000 (R/W 32) Network Control Register */
+ __IO GMAC_NCFGR_Type NCFGR; /**< \brief Offset: 0x004 (R/W 32) Network Configuration Register */
+ __I GMAC_NSR_Type NSR; /**< \brief Offset: 0x008 (R/ 32) Network Status Register */
+ __IO GMAC_UR_Type UR; /**< \brief Offset: 0x00C (R/W 32) User Register */
+ __IO GMAC_DCFGR_Type DCFGR; /**< \brief Offset: 0x010 (R/W 32) DMA Configuration Register */
+ __IO GMAC_TSR_Type TSR; /**< \brief Offset: 0x014 (R/W 32) Transmit Status Register */
+ __IO GMAC_RBQB_Type RBQB; /**< \brief Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address */
+ __IO GMAC_TBQB_Type TBQB; /**< \brief Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address */
+ __IO GMAC_RSR_Type RSR; /**< \brief Offset: 0x020 (R/W 32) Receive Status Register */
+ __IO GMAC_ISR_Type ISR; /**< \brief Offset: 0x024 (R/W 32) Interrupt Status Register */
+ __O GMAC_IER_Type IER; /**< \brief Offset: 0x028 ( /W 32) Interrupt Enable Register */
+ __O GMAC_IDR_Type IDR; /**< \brief Offset: 0x02C ( /W 32) Interrupt Disable Register */
+ __I GMAC_IMR_Type IMR; /**< \brief Offset: 0x030 (R/ 32) Interrupt Mask Register */
+ __IO GMAC_MAN_Type MAN; /**< \brief Offset: 0x034 (R/W 32) PHY Maintenance Register */
+ __I GMAC_RPQ_Type RPQ; /**< \brief Offset: 0x038 (R/ 32) Received Pause Quantum Register */
+ __IO GMAC_TPQ_Type TPQ; /**< \brief Offset: 0x03C (R/W 32) Transmit Pause Quantum Register */
+ __IO GMAC_TPSF_Type TPSF; /**< \brief Offset: 0x040 (R/W 32) TX partial store and forward Register */
+ __IO GMAC_RPSF_Type RPSF; /**< \brief Offset: 0x044 (R/W 32) RX partial store and forward Register */
+ __IO GMAC_RJFML_Type RJFML; /**< \brief Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register */
+ RoReg8 Reserved1[0x34];
+ __IO GMAC_HRB_Type HRB; /**< \brief Offset: 0x080 (R/W 32) Hash Register Bottom [31:0] */
+ __IO GMAC_HRT_Type HRT; /**< \brief Offset: 0x084 (R/W 32) Hash Register Top [63:32] */
+ GmacSa Sa[4]; /**< \brief Offset: 0x088 GmacSa groups */
+ __IO GMAC_TIDM_Type TIDM[4]; /**< \brief Offset: 0x0A8 (R/W 32) Type ID Match Register */
+ __IO GMAC_WOL_Type WOL; /**< \brief Offset: 0x0B8 (R/W 32) Wake on LAN */
+ __IO GMAC_IPGS_Type IPGS; /**< \brief Offset: 0x0BC (R/W 32) IPG Stretch Register */
+ __IO GMAC_SVLAN_Type SVLAN; /**< \brief Offset: 0x0C0 (R/W 32) Stacked VLAN Register */
+ __IO GMAC_TPFCP_Type TPFCP; /**< \brief Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register */
+ __IO GMAC_SAMB1_Type SAMB1; /**< \brief Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */
+ __IO GMAC_SAMT1_Type SAMT1; /**< \brief Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register */
+ RoReg8 Reserved2[0xC];
+ __IO GMAC_NSC_Type NSC; /**< \brief Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register */
+ __IO GMAC_SCL_Type SCL; /**< \brief Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register */
+ __IO GMAC_SCH_Type SCH; /**< \brief Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register */
+ __I GMAC_EFTSH_Type EFTSH; /**< \brief Offset: 0x0E8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */
+ __I GMAC_EFRSH_Type EFRSH; /**< \brief Offset: 0x0EC (R/ 32) PTP Event Frame Received Seconds High Register */
+ __I GMAC_PEFTSH_Type PEFTSH; /**< \brief Offset: 0x0F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */
+ __I GMAC_PEFRSH_Type PEFRSH; /**< \brief Offset: 0x0F4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */
+ RoReg8 Reserved3[0x8];
+ __I GMAC_OTLO_Type OTLO; /**< \brief Offset: 0x100 (R/ 32) Octets Transmitted [31:0] Register */
+ __I GMAC_OTHI_Type OTHI; /**< \brief Offset: 0x104 (R/ 32) Octets Transmitted [47:32] Register */
+ __I GMAC_FT_Type FT; /**< \brief Offset: 0x108 (R/ 32) Frames Transmitted Register */
+ __I GMAC_BCFT_Type BCFT; /**< \brief Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */
+ __I GMAC_MFT_Type MFT; /**< \brief Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */
+ __I GMAC_PFT_Type PFT; /**< \brief Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */
+ __I GMAC_BFT64_Type BFT64; /**< \brief Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */
+ __I GMAC_TBFT127_Type TBFT127; /**< \brief Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */
+ __I GMAC_TBFT255_Type TBFT255; /**< \brief Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */
+ __I GMAC_TBFT511_Type TBFT511; /**< \brief Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */
+ __I GMAC_TBFT1023_Type TBFT1023; /**< \brief Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */
+ __I GMAC_TBFT1518_Type TBFT1518; /**< \brief Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */
+ __I GMAC_GTBFT1518_Type GTBFT1518; /**< \brief Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */
+ __I GMAC_TUR_Type TUR; /**< \brief Offset: 0x134 (R/ 32) Transmit Underruns Register */
+ __I GMAC_SCF_Type SCF; /**< \brief Offset: 0x138 (R/ 32) Single Collision Frames Register */
+ __I GMAC_MCF_Type MCF; /**< \brief Offset: 0x13C (R/ 32) Multiple Collision Frames Register */
+ __I GMAC_EC_Type EC; /**< \brief Offset: 0x140 (R/ 32) Excessive Collisions Register */
+ __I GMAC_LC_Type LC; /**< \brief Offset: 0x144 (R/ 32) Late Collisions Register */
+ __I GMAC_DTF_Type DTF; /**< \brief Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */
+ __I GMAC_CSE_Type CSE; /**< \brief Offset: 0x14C (R/ 32) Carrier Sense Errors Register */
+ __I GMAC_ORLO_Type ORLO; /**< \brief Offset: 0x150 (R/ 32) Octets Received [31:0] Received */
+ __I GMAC_ORHI_Type ORHI; /**< \brief Offset: 0x154 (R/ 32) Octets Received [47:32] Received */
+ __I GMAC_FR_Type FR; /**< \brief Offset: 0x158 (R/ 32) Frames Received Register */
+ __I GMAC_BCFR_Type BCFR; /**< \brief Offset: 0x15C (R/ 32) Broadcast Frames Received Register */
+ __I GMAC_MFR_Type MFR; /**< \brief Offset: 0x160 (R/ 32) Multicast Frames Received Register */
+ __I GMAC_PFR_Type PFR; /**< \brief Offset: 0x164 (R/ 32) Pause Frames Received Register */
+ __I GMAC_BFR64_Type BFR64; /**< \brief Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */
+ __I GMAC_TBFR127_Type TBFR127; /**< \brief Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */
+ __I GMAC_TBFR255_Type TBFR255; /**< \brief Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */
+ __I GMAC_TBFR511_Type TBFR511; /**< \brief Offset: 0x174 (R/ 32) 256 to 511Byte Frames Received Register */
+ __I GMAC_TBFR1023_Type TBFR1023; /**< \brief Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */
+ __I GMAC_TBFR1518_Type TBFR1518; /**< \brief Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */
+ __I GMAC_TMXBFR_Type TMXBFR; /**< \brief Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */
+ __I GMAC_UFR_Type UFR; /**< \brief Offset: 0x184 (R/ 32) Undersize Frames Received Register */
+ __I GMAC_OFR_Type OFR; /**< \brief Offset: 0x188 (R/ 32) Oversize Frames Received Register */
+ __I GMAC_JR_Type JR; /**< \brief Offset: 0x18C (R/ 32) Jabbers Received Register */
+ __I GMAC_FCSE_Type FCSE; /**< \brief Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */
+ __I GMAC_LFFE_Type LFFE; /**< \brief Offset: 0x194 (R/ 32) Length Field Frame Errors Register */
+ __I GMAC_RSE_Type RSE; /**< \brief Offset: 0x198 (R/ 32) Receive Symbol Errors Register */
+ __I GMAC_AE_Type AE; /**< \brief Offset: 0x19C (R/ 32) Alignment Errors Register */
+ __I GMAC_RRE_Type RRE; /**< \brief Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */
+ __I GMAC_ROE_Type ROE; /**< \brief Offset: 0x1A4 (R/ 32) Receive Overrun Register */
+ __I GMAC_IHCE_Type IHCE; /**< \brief Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */
+ __I GMAC_TCE_Type TCE; /**< \brief Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */
+ __I GMAC_UCE_Type UCE; /**< \brief Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */
+ RoReg8 Reserved4[0x8];
+ __IO GMAC_TISUBN_Type TISUBN; /**< \brief Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+ __IO GMAC_TSH_Type TSH; /**< \brief Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */
+ RoReg8 Reserved5[0x4];
+ __IO GMAC_TSSSL_Type TSSSL; /**< \brief Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */
+ __IO GMAC_TSSN_Type TSSN; /**< \brief Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */
+ __IO GMAC_TSL_Type TSL; /**< \brief Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */
+ __IO GMAC_TN_Type TN; /**< \brief Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */
+ __O GMAC_TA_Type TA; /**< \brief Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */
+ __IO GMAC_TI_Type TI; /**< \brief Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */
+ __I GMAC_EFTSL_Type EFTSL; /**< \brief Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */
+ __I GMAC_EFTN_Type EFTN; /**< \brief Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds */
+ __I GMAC_EFRSL_Type EFRSL; /**< \brief Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */
+ __I GMAC_EFRN_Type EFRN; /**< \brief Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds */
+ __I GMAC_PEFTSL_Type PEFTSL; /**< \brief Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */
+ __I GMAC_PEFTN_Type PEFTN; /**< \brief Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds */
+ __I GMAC_PEFRSL_Type PEFRSL; /**< \brief Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */
+ __I GMAC_PEFRN_Type PEFRN; /**< \brief Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds */
+ RoReg8 Reserved6[0x70];
+ __I GMAC_RLPITR_Type RLPITR; /**< \brief Offset: 0x270 (R/ 32) Receive LPI transition Register */
+ __I GMAC_RLPITI_Type RLPITI; /**< \brief Offset: 0x274 (R/ 32) Receive LPI Time Register */
+ __I GMAC_TLPITR_Type TLPITR; /**< \brief Offset: 0x278 (R/ 32) Receive LPI transition Register */
+ __I GMAC_TLPITI_Type TLPITI; /**< \brief Offset: 0x27C (R/ 32) Receive LPI Time Register */
+} Gmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_GMAC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/hmatrixb.h b/GPIO/ATSAME54/include/component/hmatrixb.h
new file mode 100644
index 0000000..bb11a1b
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/hmatrixb.h
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_HMATRIXB_COMPONENT_
+#define _SAME54_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAME54_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB 0x214
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_HMATRIXB_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/i2s.h b/GPIO/ATSAME54/include/component/i2s.h
new file mode 100644
index 0000000..cd8dca8
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/i2s.h
@@ -0,0 +1,747 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_I2S_COMPONENT_
+#define _SAME54_I2S_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAME54_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S 0x200
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t TXEN:1; /*!< bit: 4 Tx Serializer Enable */
+ uint8_t RXEN:1; /*!< bit: 5 Rx Serializer Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE _U_(0x00) /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0 (_U_(1) << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1 (_U_(1) << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_TXEN_Pos 4 /**< \brief (I2S_CTRLA) Tx Serializer Enable */
+#define I2S_CTRLA_TXEN (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
+#define I2S_CTRLA_RXEN_Pos 5 /**< \brief (I2S_CTRLA) Rx Serializer Enable */
+#define I2S_CTRLA_RXEN (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
+#define I2S_CTRLA_MASK _U_(0x3F) /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */
+ uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */
+ uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */
+ uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */
+ uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */
+ uint32_t MCKEN:1; /*!< bit: 14 Master Clock Enable */
+ uint32_t MCKOUTINV:1; /*!< bit: 15 Master Clock Output Invert */
+ uint32_t MCKDIV:6; /*!< bit: 16..21 Master Clock Division Factor */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t MCKOUTDIV:6; /*!< bit: 24..29 Master Clock Output Division Factor */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos 9 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_FSOUTINV_Pos 10 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos 11 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos 13 /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos 14 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos 15 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_MASK _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0 (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1 (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0 (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1 (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0 (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1 (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0 (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1 (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK _U_(0x3333) /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0 (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1 (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0 (_U_(1) << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1 (_U_(1) << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0 (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1 (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0 (_U_(1) << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1 (_U_(1) << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK _U_(0x3333) /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ __I uint16_t :2; /*!< bit: 10..11 Reserved */
+ __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ __I uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ __I uint16_t :2; /*!< bit: 10..11 Reserved */
+ __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ __I uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0 (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1 (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0 (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1 (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0 (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1 (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0 (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1 (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK _U_(0x3333) /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t TXEN:1; /*!< bit: 4 Tx Serializer Enable Synchronization Status */
+ uint16_t RXEN:1; /*!< bit: 5 Rx Serializer Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXDATA:1; /*!< bit: 8 Tx Data Synchronization Status */
+ uint16_t RXDATA:1; /*!< bit: 9 Rx Data Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t :12; /*!< bit: 4..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0 (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1 (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_TXEN_Pos 4 /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
+#define I2S_SYNCBUSY_TXEN (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
+#define I2S_SYNCBUSY_RXEN_Pos 5 /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
+#define I2S_SYNCBUSY_RXEN (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
+#define I2S_SYNCBUSY_TXDATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
+#define I2S_SYNCBUSY_TXDATA (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
+#define I2S_SYNCBUSY_RXDATA_Pos 9 /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
+#define I2S_SYNCBUSY_RXDATA (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
+#define I2S_SYNCBUSY_MASK _U_(0x033F) /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_TXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_TXCTRL_OFFSET 0x20 /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
+#define I2S_TXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
+
+#define I2S_TXCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
+#define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
+#define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
+#define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
+#define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
+#define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXSAME_Pos 4 /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
+#define I2S_TXCTRL_TXSAME (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
+#define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
+#define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
+#define I2S_TXCTRL_SLOTADJ (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
+#define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
+#define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_TXCTRL) Data Word Size */
+#define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
+#define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_TXCTRL) 32 bits */
+#define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_TXCTRL) 24 bits */
+#define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_TXCTRL) 20 bits */
+#define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_TXCTRL) 18 bits */
+#define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_TXCTRL) 16 bits */
+#define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
+#define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_TXCTRL) 8 bits */
+#define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
+#define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
+#define I2S_TXCTRL_WORDADJ (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
+#define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
+#define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_EXTEND_Pos 13 /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
+#define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
+#define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Extend with zeroes */
+#define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Extend with ones */
+#define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
+#define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
+#define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_BITREV_Pos 15 /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
+#define I2S_TXCTRL_BITREV (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS0 (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
+#define I2S_TXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS1 (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
+#define I2S_TXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS2 (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
+#define I2S_TXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS3 (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
+#define I2S_TXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS4 (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
+#define I2S_TXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS5 (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
+#define I2S_TXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS6 (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
+#define I2S_TXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS7 (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
+#define I2S_TXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
+#define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
+#define I2S_TXCTRL_MONO_Pos 24 /**< \brief (I2S_TXCTRL) Mono Mode */
+#define I2S_TXCTRL_MONO (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Normal mode */
+#define I2S_TXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
+#define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_DMA_Pos 25 /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
+#define I2S_TXCTRL_DMA (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Single DMA channel */
+#define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
+#define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_MASK _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
+
+/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_RXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_RXCTRL_OFFSET 0x24 /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
+#define I2S_RXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
+
+#define I2S_RXCTRL_SERMODE_Pos 0 /**< \brief (I2S_RXCTRL) Serializer Mode */
+#define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
+#define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Receive */
+#define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_CLKSEL_Pos 5 /**< \brief (I2S_RXCTRL) Clock Unit Selection */
+#define I2S_RXCTRL_CLKSEL (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
+#define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
+#define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
+#define I2S_RXCTRL_SLOTADJ (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
+#define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
+#define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_RXCTRL) Data Word Size */
+#define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
+#define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_RXCTRL) 32 bits */
+#define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_RXCTRL) 24 bits */
+#define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_RXCTRL) 20 bits */
+#define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_RXCTRL) 18 bits */
+#define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_RXCTRL) 16 bits */
+#define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
+#define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_RXCTRL) 8 bits */
+#define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
+#define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
+#define I2S_RXCTRL_WORDADJ (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
+#define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
+#define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_EXTEND_Pos 13 /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
+#define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
+#define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Extend with zeroes */
+#define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Extend with ones */
+#define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
+#define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
+#define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_BITREV_Pos 15 /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
+#define I2S_RXCTRL_BITREV (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS0 (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
+#define I2S_RXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS1 (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
+#define I2S_RXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS2 (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
+#define I2S_RXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS3 (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
+#define I2S_RXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS4 (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
+#define I2S_RXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS5 (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
+#define I2S_RXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS6 (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
+#define I2S_RXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS7 (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
+#define I2S_RXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
+#define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
+#define I2S_RXCTRL_MONO_Pos 24 /**< \brief (I2S_RXCTRL) Mono Mode */
+#define I2S_RXCTRL_MONO (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Normal mode */
+#define I2S_RXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
+#define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_DMA_Pos 25 /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
+#define I2S_RXCTRL_DMA (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Single DMA channel */
+#define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
+#define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_RXLOOP_Pos 26 /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
+#define I2S_RXCTRL_RXLOOP (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
+#define I2S_RXCTRL_MASK _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
+
+/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_TXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_TXDATA_OFFSET 0x30 /**< \brief (I2S_TXDATA offset) Tx Data */
+#define I2S_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
+
+#define I2S_TXDATA_DATA_Pos 0 /**< \brief (I2S_TXDATA) Sample Data */
+#define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
+#define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
+#define I2S_TXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
+
+/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/ 32) Rx Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_RXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_RXDATA_OFFSET 0x34 /**< \brief (I2S_RXDATA offset) Rx Data */
+#define I2S_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
+
+#define I2S_RXDATA_DATA_Pos 0 /**< \brief (I2S_RXDATA) Sample Data */
+#define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
+#define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
+#define I2S_RXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_TXCTRL_Type TXCTRL; /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
+ __IO I2S_RXCTRL_Type RXCTRL; /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
+ RoReg8 Reserved6[0x8];
+ __O I2S_TXDATA_Type TXDATA; /**< \brief Offset: 0x30 ( /W 32) Tx Data */
+ __I I2S_RXDATA_Type RXDATA; /**< \brief Offset: 0x34 (R/ 32) Rx Data */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_I2S_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/icm.h b/GPIO/ATSAME54/include/component/icm.h
new file mode 100644
index 0000000..1b8fd5e
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/icm.h
@@ -0,0 +1,582 @@
+/**
+ * \file
+ *
+ * \brief Component description for ICM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ICM_COMPONENT_
+#define _SAME54_ICM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ICM */
+/* ========================================================================== */
+/** \addtogroup SAME54_ICM Integrity Check Monitor */
+/*@{*/
+
+#define ICM_U2010
+#define REV_ICM 0x120
+
+/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WBDIS:1; /*!< bit: 0 Write Back Disable */
+ uint32_t EOMDIS:1; /*!< bit: 1 End of Monitoring Disable */
+ uint32_t SLBDIS:1; /*!< bit: 2 Secondary List Branching Disable */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t BBC:4; /*!< bit: 4.. 7 Bus Burden Control */
+ uint32_t ASCD:1; /*!< bit: 8 Automatic Switch To Compare Digest */
+ uint32_t DUALBUFF:1; /*!< bit: 9 Dual Input Buffer */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t UIHASH:1; /*!< bit: 12 User Initial Hash Value */
+ uint32_t UALGO:3; /*!< bit: 13..15 User SHA Algorithm */
+ uint32_t HAPROT:6; /*!< bit: 16..21 Region Hash Area Protection */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t DAPROT:6; /*!< bit: 24..29 Region Descriptor Area Protection */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_CFG_OFFSET 0x00 /**< \brief (ICM_CFG offset) Configuration */
+#define ICM_CFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */
+
+#define ICM_CFG_WBDIS_Pos 0 /**< \brief (ICM_CFG) Write Back Disable */
+#define ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos)
+#define ICM_CFG_EOMDIS_Pos 1 /**< \brief (ICM_CFG) End of Monitoring Disable */
+#define ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
+#define ICM_CFG_SLBDIS_Pos 2 /**< \brief (ICM_CFG) Secondary List Branching Disable */
+#define ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
+#define ICM_CFG_BBC_Pos 4 /**< \brief (ICM_CFG) Bus Burden Control */
+#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos)
+#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
+#define ICM_CFG_ASCD_Pos 8 /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
+#define ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos)
+#define ICM_CFG_DUALBUFF_Pos 9 /**< \brief (ICM_CFG) Dual Input Buffer */
+#define ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
+#define ICM_CFG_UIHASH_Pos 12 /**< \brief (ICM_CFG) User Initial Hash Value */
+#define ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos)
+#define ICM_CFG_UALGO_Pos 13 /**< \brief (ICM_CFG) User SHA Algorithm */
+#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
+#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< \brief (ICM_CFG) SHA1 Algorithm */
+#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< \brief (ICM_CFG) SHA256 Algorithm */
+#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< \brief (ICM_CFG) SHA224 Algorithm */
+#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_HAPROT_Pos 16 /**< \brief (ICM_CFG) Region Hash Area Protection */
+#define ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
+#define ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
+#define ICM_CFG_DAPROT_Pos 24 /**< \brief (ICM_CFG) Region Descriptor Area Protection */
+#define ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
+#define ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
+#define ICM_CFG_MASK _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */
+
+/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 ICM Enable */
+ uint32_t DISABLE:1; /*!< bit: 1 ICM Disable Register */
+ uint32_t SWRST:1; /*!< bit: 2 Software Reset */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t REHASH:4; /*!< bit: 4.. 7 Recompute Internal Hash */
+ uint32_t RMDIS:4; /*!< bit: 8..11 Region Monitoring Disable */
+ uint32_t RMEN:4; /*!< bit: 12..15 Region Monitoring Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_CTRL_OFFSET 0x04 /**< \brief (ICM_CTRL offset) Control */
+
+#define ICM_CTRL_ENABLE_Pos 0 /**< \brief (ICM_CTRL) ICM Enable */
+#define ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
+#define ICM_CTRL_DISABLE_Pos 1 /**< \brief (ICM_CTRL) ICM Disable Register */
+#define ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
+#define ICM_CTRL_SWRST_Pos 2 /**< \brief (ICM_CTRL) Software Reset */
+#define ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos)
+#define ICM_CTRL_REHASH_Pos 4 /**< \brief (ICM_CTRL) Recompute Internal Hash */
+#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos)
+#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
+#define ICM_CTRL_RMDIS_Pos 8 /**< \brief (ICM_CTRL) Region Monitoring Disable */
+#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
+#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
+#define ICM_CTRL_RMEN_Pos 12 /**< \brief (ICM_CTRL) Region Monitoring Enable */
+#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos)
+#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
+#define ICM_CTRL_MASK _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */
+
+/* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 ICM Controller Enable Register */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t RAWRMDIS:4; /*!< bit: 8..11 RAW Region Monitoring Disabled Status */
+ uint32_t RMDIS:4; /*!< bit: 12..15 Region Monitoring Disabled Status */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_SR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_SR_OFFSET 0x08 /**< \brief (ICM_SR offset) Status */
+#define ICM_SR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */
+
+#define ICM_SR_ENABLE_Pos 0 /**< \brief (ICM_SR) ICM Controller Enable Register */
+#define ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos)
+#define ICM_SR_RAWRMDIS_Pos 8 /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
+#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
+#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
+#define ICM_SR_RMDIS_Pos 12 /**< \brief (ICM_SR) Region Monitoring Disabled Status */
+#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos)
+#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
+#define ICM_SR_MASK _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */
+
+/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Enable */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Enable */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Enable */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition detected Interrupt Enable */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Enable */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Enable */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IER_OFFSET 0x10 /**< \brief (ICM_IER offset) Interrupt Enable */
+
+#define ICM_IER_RHC_Pos 0 /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
+#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos)
+#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
+#define ICM_IER_RDM_Pos 4 /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
+#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos)
+#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
+#define ICM_IER_RBE_Pos 8 /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
+#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos)
+#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
+#define ICM_IER_RWC_Pos 12 /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
+#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos)
+#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
+#define ICM_IER_REC_Pos 16 /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
+#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos)
+#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
+#define ICM_IER_RSU_Pos 20 /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
+#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos)
+#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
+#define ICM_IER_URAD_Pos 24 /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
+#define ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos)
+#define ICM_IER_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */
+
+/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Disable */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Disable */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Disable */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition detected Interrupt Disable */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Disable */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IDR_OFFSET 0x14 /**< \brief (ICM_IDR offset) Interrupt Disable */
+#define ICM_IDR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */
+
+#define ICM_IDR_RHC_Pos 0 /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
+#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos)
+#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
+#define ICM_IDR_RDM_Pos 4 /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
+#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos)
+#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
+#define ICM_IDR_RBE_Pos 8 /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
+#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos)
+#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
+#define ICM_IDR_RWC_Pos 12 /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
+#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos)
+#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
+#define ICM_IDR_REC_Pos 16 /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
+#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos)
+#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
+#define ICM_IDR_RSU_Pos 20 /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
+#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos)
+#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
+#define ICM_IDR_URAD_Pos 24 /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
+#define ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos)
+#define ICM_IDR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */
+
+/* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Mask */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Mask */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Mask */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Mask */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Mask */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Mask */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IMR_OFFSET 0x18 /**< \brief (ICM_IMR offset) Interrupt Mask */
+#define ICM_IMR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */
+
+#define ICM_IMR_RHC_Pos 0 /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
+#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos)
+#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
+#define ICM_IMR_RDM_Pos 4 /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
+#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos)
+#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
+#define ICM_IMR_RBE_Pos 8 /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
+#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos)
+#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
+#define ICM_IMR_RWC_Pos 12 /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
+#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos)
+#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
+#define ICM_IMR_REC_Pos 16 /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
+#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos)
+#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
+#define ICM_IMR_RSU_Pos 20 /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
+#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos)
+#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
+#define ICM_IMR_URAD_Pos 24 /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
+#define ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos)
+#define ICM_IMR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */
+
+/* -------- ICM_ISR : (ICM Offset: 0x1C) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed */
+ uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch */
+ uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error */
+ uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected */
+ uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected */
+ uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Detected */
+ uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Status */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_ISR_OFFSET 0x1C /**< \brief (ICM_ISR offset) Interrupt Status */
+#define ICM_ISR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */
+
+#define ICM_ISR_RHC_Pos 0 /**< \brief (ICM_ISR) Region Hash Completed */
+#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos)
+#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
+#define ICM_ISR_RDM_Pos 4 /**< \brief (ICM_ISR) Region Digest Mismatch */
+#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos)
+#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
+#define ICM_ISR_RBE_Pos 8 /**< \brief (ICM_ISR) Region Bus Error */
+#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos)
+#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
+#define ICM_ISR_RWC_Pos 12 /**< \brief (ICM_ISR) Region Wrap Condition Detected */
+#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos)
+#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
+#define ICM_ISR_REC_Pos 16 /**< \brief (ICM_ISR) Region End bit Condition Detected */
+#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos)
+#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
+#define ICM_ISR_RSU_Pos 20 /**< \brief (ICM_ISR) Region Status Updated Detected */
+#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos)
+#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
+#define ICM_ISR_URAD_Pos 24 /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
+#define ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos)
+#define ICM_ISR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */
+
+/* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t URAT:3; /*!< bit: 0.. 2 Undefined Register Access Trace */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_UASR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_UASR_OFFSET 0x20 /**< \brief (ICM_UASR offset) Undefined Access Status */
+#define ICM_UASR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */
+
+#define ICM_UASR_URAT_Pos 0 /**< \brief (ICM_UASR) Undefined Register Access Trace */
+#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
+#define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1) /**< \brief (ICM_UASR) CFG modified during active monitoring */
+#define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2) /**< \brief (ICM_UASR) DSCR modified during active monitoring */
+#define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3) /**< \brief (ICM_UASR) HASH modified during active monitoring */
+#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< \brief (ICM_UASR) Write-only register read access */
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_MASK _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */
+
+/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t DASA:26; /*!< bit: 6..31 Descriptor Area Start Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_DSCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_DSCR_OFFSET 0x30 /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */
+#define ICM_DSCR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */
+
+#define ICM_DSCR_DASA_Pos 6 /**< \brief (ICM_DSCR) Descriptor Area Start Address */
+#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
+#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
+#define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */
+
+/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :7; /*!< bit: 0.. 6 Reserved */
+ uint32_t HASA:25; /*!< bit: 7..31 Hash Area Start Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_HASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_HASH_OFFSET 0x34 /**< \brief (ICM_HASH offset) Region Hash Area Start Address */
+#define ICM_HASH_RESETVALUE _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */
+
+#define ICM_HASH_HASA_Pos 7 /**< \brief (ICM_HASH) Hash Area Start Address */
+#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
+#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
+#define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */
+
+/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t VAL:32; /*!< bit: 0..31 Initial Hash Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_UIHVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_UIHVAL_OFFSET 0x38 /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */
+#define ICM_UIHVAL_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */
+
+#define ICM_UIHVAL_VAL_Pos 0 /**< \brief (ICM_UIHVAL) Initial Hash Value */
+#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
+#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
+#define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */
+
+/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RADDR_OFFSET 0x00 /**< \brief (ICM_RADDR offset) Region Start Address */
+#define ICM_RADDR_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */
+
+/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */
+ uint32_t WRAP:1; /*!< bit: 1 Region Wrap */
+ uint32_t EOM:1; /*!< bit: 2 End of Monitoring */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */
+ uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */
+ uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */
+ uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */
+ uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */
+ uint32_t SUIEN:1; /*!< bit: 9 Region Status Updated Interrupt Enable */
+ uint32_t PROCDLY:1; /*!< bit: 10 SHA Processing Delay */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t ALGO:3; /*!< bit: 12..14 SHA Algorithm */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t MRPROT:6; /*!< bit: 24..29 Memory Region AHB Protection */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RCFG_OFFSET 0x04 /**< \brief (ICM_RCFG offset) Region Configuration */
+#define ICM_RCFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */
+
+#define ICM_RCFG_CDWBN_Pos 0 /**< \brief (ICM_RCFG) Compare Digest Write Back */
+#define ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_CDWBN_COMP_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_WRAP_Pos 1 /**< \brief (ICM_RCFG) Region Wrap */
+#define ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_WRAP_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WRAP_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_EOM_Pos 2 /**< \brief (ICM_RCFG) End of Monitoring */
+#define ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_EOM_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_EOM_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_RHIEN_Pos 4 /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */
+#define ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_RHIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_RHIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_DMIEN_Pos 5 /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */
+#define ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_DMIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_DMIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_BEIEN_Pos 6 /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */
+#define ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_BEIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_BEIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_WCIEN_Pos 7 /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */
+#define ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_WCIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WCIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_ECIEN_Pos 8 /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */
+#define ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_ECIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_ECIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_SUIEN_Pos 9 /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */
+#define ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_SUIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_SUIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_PROCDLY_Pos 10 /**< \brief (ICM_RCFG) SHA Processing Delay */
+#define ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1) /**< \brief (ICM_RCFG) */
+#define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_ALGO_Pos 12 /**< \brief (ICM_RCFG) SHA Algorithm */
+#define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos)
+#define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
+#define ICM_RCFG_MRPROT_Pos 24 /**< \brief (ICM_RCFG) Memory Region AHB Protection */
+#define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
+#define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
+#define ICM_RCFG_MASK _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */
+
+/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TRSIZE:16; /*!< bit: 0..15 Transfer Size */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RCTRL_OFFSET 0x08 /**< \brief (ICM_RCTRL offset) Region Control */
+
+#define ICM_RCTRL_TRSIZE_Pos 0 /**< \brief (ICM_RCTRL) Transfer Size */
+#define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
+#define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
+#define ICM_RCTRL_MASK _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */
+
+/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} ICM_RNEXT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RNEXT_OFFSET 0x0C /**< \brief (ICM_RNEXT offset) Region Next Address */
+#define ICM_RNEXT_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */
+
+/** \brief ICM APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ICM_CFG_Type CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration */
+ __O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */
+ __I ICM_SR_Type SR; /**< \brief Offset: 0x08 (R/ 32) Status */
+ RoReg8 Reserved1[0x4];
+ __O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */
+ __O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */
+ __I ICM_IMR_Type IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask */
+ __I ICM_ISR_Type ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status */
+ __I ICM_UASR_Type UASR; /**< \brief Offset: 0x20 (R/ 32) Undefined Access Status */
+ RoReg8 Reserved2[0xC];
+ __IO ICM_DSCR_Type DSCR; /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
+ __IO ICM_HASH_Type HASH; /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */
+ __O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */
+} Icm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief ICM Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ICM_RADDR_Type RADDR; /**< \brief Offset: 0x00 (R/W 32) Region Start Address */
+ __IO ICM_RCFG_Type RCFG; /**< \brief Offset: 0x04 (R/W 32) Region Configuration */
+ __IO ICM_RCTRL_Type RCTRL; /**< \brief Offset: 0x08 (R/W 32) Region Control */
+ __IO ICM_RNEXT_Type RNEXT; /**< \brief Offset: 0x0C (R/W 32) Region Next Address */
+} IcmDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_ICM_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAME54_ICM_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/mclk.h b/GPIO/ATSAME54/include/component/mclk.h
new file mode 100644
index 0000000..c7a8659
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/mclk.h
@@ -0,0 +1,484 @@
+/**
+ * \file
+ *
+ * \brief Component description for MCLK
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_MCLK_COMPONENT_
+#define _SAME54_MCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR MCLK */
+/* ========================================================================== */
+/** \addtogroup SAME54_MCLK Main Clock */
+/*@{*/
+
+#define MCLK_U2408
+#define REV_MCLK 0x100
+
+/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
+#define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
+#define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
+#define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */
+
+/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
+#define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
+
+#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
+#define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
+#define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */
+
+/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
+#define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */
+#define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
+#define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */
+
+/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_HSDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_HSDIV_OFFSET 0x04 /**< \brief (MCLK_HSDIV offset) HS Clock Division */
+#define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
+
+#define MCLK_HSDIV_DIV_Pos 0 /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
+#define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
+#define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
+#define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_HSDIV) Divide by 1 */
+#define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
+#define MCLK_HSDIV_MASK _U_(0xFF) /**< \brief (MCLK_HSDIV) MASK Register */
+
+/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} MCLK_CPUDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_CPUDIV_OFFSET 0x05 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
+#define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
+
+#define MCLK_CPUDIV_DIV_Pos 0 /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
+#define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
+#define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */
+#define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */
+#define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */
+#define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */
+#define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */
+#define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */
+#define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */
+#define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */
+#define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */
+
+/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */
+ uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */
+ uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */
+ uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */
+ uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */
+ uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */
+ uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */
+ uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */
+ uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */
+ uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */
+ uint32_t CAN0_:1; /*!< bit: 17 CAN0 AHB Clock Mask */
+ uint32_t CAN1_:1; /*!< bit: 18 CAN1 AHB Clock Mask */
+ uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */
+ uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */
+ uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */
+ uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */
+ uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */
+#define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
+
+#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
+#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
+#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
+#define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
+#define MCLK_AHBMASK_DSU_Pos 4 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
+#define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
+#define MCLK_AHBMASK_HMATRIX_Pos 5 /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
+#define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
+#define MCLK_AHBMASK_NVMCTRL_Pos 6 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
+#define MCLK_AHBMASK_HSRAM_Pos 7 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
+#define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
+#define MCLK_AHBMASK_CMCC_Pos 8 /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
+#define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
+#define MCLK_AHBMASK_DMAC_Pos 9 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
+#define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
+#define MCLK_AHBMASK_USB_Pos 10 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
+#define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
+#define MCLK_AHBMASK_BKUPRAM_Pos 11 /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
+#define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
+#define MCLK_AHBMASK_PAC_Pos 12 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
+#define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
+#define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
+#define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
+#define MCLK_AHBMASK_GMAC_Pos 14 /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */
+#define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
+#define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
+#define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
+#define MCLK_AHBMASK_CAN0_Pos 17 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */
+#define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
+#define MCLK_AHBMASK_CAN1_Pos 18 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */
+#define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
+#define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
+#define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
+#define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
+#define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
+#define MCLK_AHBMASK_QSPI_2X_Pos 21 /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
+#define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22 /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
+#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
+#define MCLK_AHBMASK_MASK _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
+
+/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */
+ uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */
+ uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */
+ uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */
+ uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */
+ uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */
+ uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */
+ uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */
+#define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
+
+#define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
+#define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
+#define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
+#define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
+#define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
+#define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
+#define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
+#define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
+#define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
+#define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
+#define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
+#define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
+#define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
+#define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
+#define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
+#define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
+#define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
+#define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
+#define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
+#define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
+#define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
+#define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
+#define MCLK_APBAMASK_SERCOM0_Pos 12 /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
+#define MCLK_APBAMASK_SERCOM1_Pos 13 /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
+#define MCLK_APBAMASK_TC0_Pos 14 /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
+#define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
+#define MCLK_APBAMASK_TC1_Pos 15 /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
+#define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
+#define MCLK_APBAMASK_MASK _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
+
+/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */
+ uint32_t :1; /*!< bit: 8 Reserved */
+ uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */
+ uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */
+ uint32_t TAL_:1; /*!< bit: 15 TAL APB Clock Enable */
+ uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */
+#define MCLK_APBBMASK_RESETVALUE _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
+
+#define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
+#define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
+#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
+#define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
+#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
+#define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
+#define MCLK_APBBMASK_PORT_Pos 4 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
+#define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
+#define MCLK_APBBMASK_HMATRIX_Pos 6 /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
+#define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
+#define MCLK_APBBMASK_EVSYS_Pos 7 /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
+#define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
+#define MCLK_APBBMASK_SERCOM2_Pos 9 /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
+#define MCLK_APBBMASK_SERCOM3_Pos 10 /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
+#define MCLK_APBBMASK_TCC0_Pos 11 /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
+#define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
+#define MCLK_APBBMASK_TCC1_Pos 12 /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
+#define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
+#define MCLK_APBBMASK_TC2_Pos 13 /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
+#define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
+#define MCLK_APBBMASK_TC3_Pos 14 /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
+#define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
+#define MCLK_APBBMASK_TAL_Pos 15 /**< \brief (MCLK_APBBMASK) TAL APB Clock Enable */
+#define MCLK_APBBMASK_TAL (_U_(0x1) << MCLK_APBBMASK_TAL_Pos)
+#define MCLK_APBBMASK_RAMECC_Pos 16 /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
+#define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
+#define MCLK_APBBMASK_MASK _U_(0x0001FED7) /**< \brief (MCLK_APBBMASK) MASK Register */
+
+/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */
+ uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */
+ uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */
+ uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */
+ uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */
+ uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */
+ uint32_t :1; /*!< bit: 12 Reserved */
+ uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */
+ uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */
+ uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
+#define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
+
+#define MCLK_APBCMASK_GMAC_Pos 2 /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */
+#define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
+#define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
+#define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
+#define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
+#define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
+#define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
+#define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
+#define MCLK_APBCMASK_TC5_Pos 6 /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
+#define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
+#define MCLK_APBCMASK_PDEC_Pos 7 /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
+#define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
+#define MCLK_APBCMASK_AC_Pos 8 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
+#define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
+#define MCLK_APBCMASK_AES_Pos 9 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
+#define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
+#define MCLK_APBCMASK_TRNG_Pos 10 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
+#define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
+#define MCLK_APBCMASK_ICM_Pos 11 /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
+#define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
+#define MCLK_APBCMASK_QSPI_Pos 13 /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
+#define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
+#define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
+#define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
+#define MCLK_APBCMASK_MASK _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */
+
+/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */
+ uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */
+ uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */
+ uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */
+ uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */
+ uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */
+ uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */
+ uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */
+ uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */
+ uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */
+ uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MCLK_APBDMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */
+#define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
+
+#define MCLK_APBDMASK_SERCOM4_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
+#define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
+#define MCLK_APBDMASK_SERCOM6_Pos 2 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
+#define MCLK_APBDMASK_SERCOM7_Pos 3 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
+#define MCLK_APBDMASK_TCC4_Pos 4 /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
+#define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
+#define MCLK_APBDMASK_TC6_Pos 5 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
+#define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
+#define MCLK_APBDMASK_TC7_Pos 6 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
+#define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
+#define MCLK_APBDMASK_ADC0_Pos 7 /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
+#define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
+#define MCLK_APBDMASK_ADC1_Pos 8 /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
+#define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
+#define MCLK_APBDMASK_DAC_Pos 9 /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
+#define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
+#define MCLK_APBDMASK_I2S_Pos 10 /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
+#define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
+#define MCLK_APBDMASK_PCC_Pos 11 /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
+#define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
+#define MCLK_APBDMASK_MASK _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
+
+/** \brief MCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ RoReg8 Reserved1[0x1];
+ __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */
+ __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */
+ __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
+ __I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */
+ __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */
+ RoReg8 Reserved2[0xA];
+ __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
+ __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
+ __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
+ __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
+ __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
+} Mclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_MCLK_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/nvmctrl.h b/GPIO/ATSAME54/include/component/nvmctrl.h
new file mode 100644
index 0000000..c25c16e
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/nvmctrl.h
@@ -0,0 +1,861 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_NVMCTRL_COMPONENT_
+#define _SAME54_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME54_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2409
+#define REV_NVMCTRL 0x100
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t AUTOWS:1; /*!< bit: 2 Auto Wait State Enable */
+ uint16_t SUSPEN:1; /*!< bit: 3 Suspend Enable */
+ uint16_t WMODE:2; /*!< bit: 4.. 5 Write Mode */
+ uint16_t PRM:2; /*!< bit: 6.. 7 Power Reduction Mode during Sleep */
+ uint16_t RWS:4; /*!< bit: 8..11 NVM Read Wait States */
+ uint16_t AHBNS0:1; /*!< bit: 12 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
+ uint16_t AHBNS1:1; /*!< bit: 13 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
+ uint16_t CACHEDIS0:1; /*!< bit: 14 AHB0 Cache Disable */
+ uint16_t CACHEDIS1:1; /*!< bit: 15 AHB1 Cache Disable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE _U_(0x0004) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_AUTOWS_Pos 2 /**< \brief (NVMCTRL_CTRLA) Auto Wait State Enable */
+#define NVMCTRL_CTRLA_AUTOWS (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos)
+#define NVMCTRL_CTRLA_SUSPEN_Pos 3 /**< \brief (NVMCTRL_CTRLA) Suspend Enable */
+#define NVMCTRL_CTRLA_SUSPEN (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos)
+#define NVMCTRL_CTRLA_WMODE_Pos 4 /**< \brief (NVMCTRL_CTRLA) Write Mode */
+#define NVMCTRL_CTRLA_WMODE_Msk (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
+#define NVMCTRL_CTRLA_WMODE_MAN_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLA) Manual Write */
+#define NVMCTRL_CTRLA_WMODE_ADW_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLA) Automatic Double Word Write */
+#define NVMCTRL_CTRLA_WMODE_AQW_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLA) Automatic Quad Word */
+#define NVMCTRL_CTRLA_WMODE_AP_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLA) Automatic Page Write */
+#define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_PRM_Pos 6 /**< \brief (NVMCTRL_CTRLA) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLA_PRM_Msk (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
+#define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
+#define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */
+#define NVMCTRL_CTRLA_PRM_MANUAL_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
+#define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_RWS_Pos 8 /**< \brief (NVMCTRL_CTRLA) NVM Read Wait States */
+#define NVMCTRL_CTRLA_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos)
+#define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
+#define NVMCTRL_CTRLA_AHBNS0_Pos 12 /**< \brief (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
+#define NVMCTRL_CTRLA_AHBNS0 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos)
+#define NVMCTRL_CTRLA_AHBNS1_Pos 13 /**< \brief (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
+#define NVMCTRL_CTRLA_AHBNS1 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos)
+#define NVMCTRL_CTRLA_CACHEDIS0_Pos 14 /**< \brief (NVMCTRL_CTRLA) AHB0 Cache Disable */
+#define NVMCTRL_CTRLA_CACHEDIS0 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos)
+#define NVMCTRL_CTRLA_CACHEDIS1_Pos 15 /**< \brief (NVMCTRL_CTRLA) AHB1 Cache Disable */
+#define NVMCTRL_CTRLA_CACHEDIS1 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos)
+#define NVMCTRL_CTRLA_MASK _U_(0xFFFC) /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLB) Command */
+#define NVMCTRL_CTRLB_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
+#define NVMCTRL_CTRLB_CMD_EP_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */
+#define NVMCTRL_CTRLB_CMD_EB_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */
+#define NVMCTRL_CTRLB_CMD_WP_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */
+#define NVMCTRL_CTRLB_CMD_WQW_Val _U_(0x4) /**< \brief (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */
+#define NVMCTRL_CTRLB_CMD_SWRST_Val _U_(0x10) /**< \brief (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */
+#define NVMCTRL_CTRLB_CMD_LR_Val _U_(0x11) /**< \brief (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLB_CMD_UR_Val _U_(0x12) /**< \brief (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLB_CMD_SPRM_Val _U_(0x13) /**< \brief (NVMCTRL_CTRLB) Sets the power reduction mode. */
+#define NVMCTRL_CTRLB_CMD_CPRM_Val _U_(0x14) /**< \brief (NVMCTRL_CTRLB) Clears the power reduction mode. */
+#define NVMCTRL_CTRLB_CMD_PBC_Val _U_(0x15) /**< \brief (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */
+#define NVMCTRL_CTRLB_CMD_SSB_Val _U_(0x16) /**< \brief (NVMCTRL_CTRLB) Set Security Bit */
+#define NVMCTRL_CTRLB_CMD_BKSWRST_Val _U_(0x17) /**< \brief (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */
+#define NVMCTRL_CTRLB_CMD_CELCK_Val _U_(0x18) /**< \brief (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */
+#define NVMCTRL_CTRLB_CMD_CEULCK_Val _U_(0x19) /**< \brief (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */
+#define NVMCTRL_CTRLB_CMD_SBPDIS_Val _U_(0x1A) /**< \brief (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */
+#define NVMCTRL_CTRLB_CMD_CBPDIS_Val _U_(0x1B) /**< \brief (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */
+#define NVMCTRL_CTRLB_CMD_ASEES0_Val _U_(0x30) /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */
+#define NVMCTRL_CTRLB_CMD_ASEES1_Val _U_(0x31) /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */
+#define NVMCTRL_CTRLB_CMD_SEERALOC_Val _U_(0x32) /**< \brief (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */
+#define NVMCTRL_CTRLB_CMD_SEEFLUSH_Val _U_(0x33) /**< \brief (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode */
+#define NVMCTRL_CTRLB_CMD_LSEE_Val _U_(0x34) /**< \brief (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */
+#define NVMCTRL_CTRLB_CMD_USEE_Val _U_(0x35) /**< \brief (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */
+#define NVMCTRL_CTRLB_CMD_LSEER_Val _U_(0x36) /**< \brief (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */
+#define NVMCTRL_CTRLB_CMD_USEER_Val _U_(0x37) /**< \brief (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */
+#define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SEEFLUSH (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLB) Command Execution */
+#define NVMCTRL_CTRLB_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos)
+#define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
+#define NVMCTRL_CTRLB_CMDEX_KEY_Val _U_(0xA5) /**< \brief (NVMCTRL_CTRLB) Execution Key */
+#define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos)
+#define NVMCTRL_CTRLB_MASK _U_(0xFF7F) /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/ 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :12; /*!< bit: 19..30 Reserved */
+ uint32_t SEE:1; /*!< bit: 31 SmartEEPROM Supported */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE _U_(0x00060000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_SEE_Pos 31 /**< \brief (NVMCTRL_PARAM) SmartEEPROM Supported */
+#define NVMCTRL_PARAM_SEE (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos)
+#define NVMCTRL_PARAM_MASK _U_(0x8007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Clear */
+ uint16_t ADDRE:1; /*!< bit: 1 Address Error */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Clear */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Clear */
+ uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Clear */
+ uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Clear */
+ uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Clear */
+ uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Clear */
+ uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Clear */
+ uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Clear */
+ uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Clear */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_DONE_Pos 0 /**< \brief (NVMCTRL_INTENCLR) Command Done Interrupt Clear */
+#define NVMCTRL_INTENCLR_DONE (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos)
+#define NVMCTRL_INTENCLR_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Address Error */
+#define NVMCTRL_INTENCLR_ADDRE (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos)
+#define NVMCTRL_INTENCLR_PROGE_Pos 2 /**< \brief (NVMCTRL_INTENCLR) Programming Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_PROGE (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos)
+#define NVMCTRL_INTENCLR_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTENCLR) Lock Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_LOCKE (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos)
+#define NVMCTRL_INTENCLR_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_ECCSE (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos)
+#define NVMCTRL_INTENCLR_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_ECCDE (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos)
+#define NVMCTRL_INTENCLR_NVME_Pos 6 /**< \brief (NVMCTRL_INTENCLR) NVM Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_NVME (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos)
+#define NVMCTRL_INTENCLR_SUSP_Pos 7 /**< \brief (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear */
+#define NVMCTRL_INTENCLR_SUSP (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos)
+#define NVMCTRL_INTENCLR_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear */
+#define NVMCTRL_INTENCLR_SEESFULL (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos)
+#define NVMCTRL_INTENCLR_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear */
+#define NVMCTRL_INTENCLR_SEESOVF (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos)
+#define NVMCTRL_INTENCLR_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear */
+#define NVMCTRL_INTENCLR_SEEWRC (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos)
+#define NVMCTRL_INTENCLR_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Enable */
+ uint16_t ADDRE:1; /*!< bit: 1 Address Error Interrupt Enable */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Enable */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Enable */
+ uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Enable */
+ uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Enable */
+ uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Enable */
+ uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Enable */
+ uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Enable */
+ uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Enable */
+ uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Enable */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET 0x0E /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_DONE_Pos 0 /**< \brief (NVMCTRL_INTENSET) Command Done Interrupt Enable */
+#define NVMCTRL_INTENSET_DONE (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos)
+#define NVMCTRL_INTENSET_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTENSET) Address Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ADDRE (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos)
+#define NVMCTRL_INTENSET_PROGE_Pos 2 /**< \brief (NVMCTRL_INTENSET) Programming Error Interrupt Enable */
+#define NVMCTRL_INTENSET_PROGE (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos)
+#define NVMCTRL_INTENSET_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTENSET) Lock Error Interrupt Enable */
+#define NVMCTRL_INTENSET_LOCKE (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos)
+#define NVMCTRL_INTENSET_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ECCSE (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos)
+#define NVMCTRL_INTENSET_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ECCDE (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos)
+#define NVMCTRL_INTENSET_NVME_Pos 6 /**< \brief (NVMCTRL_INTENSET) NVM Error Interrupt Enable */
+#define NVMCTRL_INTENSET_NVME (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos)
+#define NVMCTRL_INTENSET_SUSP_Pos 7 /**< \brief (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable */
+#define NVMCTRL_INTENSET_SUSP (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos)
+#define NVMCTRL_INTENSET_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable */
+#define NVMCTRL_INTENSET_SEESFULL (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos)
+#define NVMCTRL_INTENSET_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable */
+#define NVMCTRL_INTENSET_SEESOVF (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos)
+#define NVMCTRL_INTENSET_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable */
+#define NVMCTRL_INTENSET_SEEWRC (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos)
+#define NVMCTRL_INTENSET_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t DONE:1; /*!< bit: 0 Command Done */
+ __I uint16_t ADDRE:1; /*!< bit: 1 Address Error */
+ __I uint16_t PROGE:1; /*!< bit: 2 Programming Error */
+ __I uint16_t LOCKE:1; /*!< bit: 3 Lock Error */
+ __I uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error */
+ __I uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error */
+ __I uint16_t NVME:1; /*!< bit: 6 NVM Error */
+ __I uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Operation */
+ __I uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full */
+ __I uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow */
+ __I uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed */
+ __I uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET 0x10 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_DONE_Pos 0 /**< \brief (NVMCTRL_INTFLAG) Command Done */
+#define NVMCTRL_INTFLAG_DONE (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos)
+#define NVMCTRL_INTFLAG_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Address Error */
+#define NVMCTRL_INTFLAG_ADDRE (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos)
+#define NVMCTRL_INTFLAG_PROGE_Pos 2 /**< \brief (NVMCTRL_INTFLAG) Programming Error */
+#define NVMCTRL_INTFLAG_PROGE (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos)
+#define NVMCTRL_INTFLAG_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTFLAG) Lock Error */
+#define NVMCTRL_INTFLAG_LOCKE (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos)
+#define NVMCTRL_INTFLAG_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTFLAG) ECC Single Error */
+#define NVMCTRL_INTFLAG_ECCSE (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos)
+#define NVMCTRL_INTFLAG_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTFLAG) ECC Dual Error */
+#define NVMCTRL_INTFLAG_ECCDE (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos)
+#define NVMCTRL_INTFLAG_NVME_Pos 6 /**< \brief (NVMCTRL_INTFLAG) NVM Error */
+#define NVMCTRL_INTFLAG_NVME (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos)
+#define NVMCTRL_INTFLAG_SUSP_Pos 7 /**< \brief (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation */
+#define NVMCTRL_INTFLAG_SUSP (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos)
+#define NVMCTRL_INTFLAG_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTFLAG) Active SEES Full */
+#define NVMCTRL_INTFLAG_SEESFULL (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos)
+#define NVMCTRL_INTFLAG_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTFLAG) Active SEES Overflow */
+#define NVMCTRL_INTFLAG_SEESOVF (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos)
+#define NVMCTRL_INTFLAG_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTFLAG) SEE Write Completed */
+#define NVMCTRL_INTFLAG_SEEWRC (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos)
+#define NVMCTRL_INTFLAG_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) (R/ 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t READY:1; /*!< bit: 0 Ready to accept a command */
+ uint16_t PRM:1; /*!< bit: 1 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 2 NVM Page Buffer Active Loading */
+ uint16_t SUSP:1; /*!< bit: 3 NVM Write Or Erase Operation Is Suspended */
+ uint16_t AFIRST:1; /*!< bit: 4 BANKA First */
+ uint16_t BPDIS:1; /*!< bit: 5 Boot Loader Protection Disable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t BOOTPROT:4; /*!< bit: 8..11 Boot Loader Protection Size */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET 0x12 /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_READY_Pos 0 /**< \brief (NVMCTRL_STATUS) Ready to accept a command */
+#define NVMCTRL_STATUS_READY (_U_(0x1) << NVMCTRL_STATUS_READY_Pos)
+#define NVMCTRL_STATUS_PRM_Pos 1 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos 2 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_SUSP_Pos 3 /**< \brief (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended */
+#define NVMCTRL_STATUS_SUSP (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos)
+#define NVMCTRL_STATUS_AFIRST_Pos 4 /**< \brief (NVMCTRL_STATUS) BANKA First */
+#define NVMCTRL_STATUS_AFIRST (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos)
+#define NVMCTRL_STATUS_BPDIS_Pos 5 /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Disable */
+#define NVMCTRL_STATUS_BPDIS (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos)
+#define NVMCTRL_STATUS_BOOTPROT_Pos 8 /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Size */
+#define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos)
+#define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
+#define NVMCTRL_STATUS_MASK _U_(0x0F3F) /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:24; /*!< bit: 0..23 NVM Address */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET 0x14 /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK _U_(0x00FFFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) (R/ 32) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RUNLOCK:32; /*!< bit: 0..31 Region Un-Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_RUNLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_RUNLOCK_OFFSET 0x18 /**< \brief (NVMCTRL_RUNLOCK offset) Lock Section */
+#define NVMCTRL_RUNLOCK_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_RUNLOCK reset_value) Lock Section */
+
+#define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0 /**< \brief (NVMCTRL_RUNLOCK) Region Un-Lock Bits */
+#define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)
+#define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
+#define NVMCTRL_RUNLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_RUNLOCK) MASK Register */
+
+/* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) (R/ 32) Page Buffer Load Data x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Page Buffer Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_PBLDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PBLDATA_OFFSET 0x1C /**< \brief (NVMCTRL_PBLDATA offset) Page Buffer Load Data x */
+#define NVMCTRL_PBLDATA_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA reset_value) Page Buffer Load Data x */
+
+#define NVMCTRL_PBLDATA_DATA_Pos 0 /**< \brief (NVMCTRL_PBLDATA) Page Buffer Data */
+#define NVMCTRL_PBLDATA_DATA_Msk (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos)
+#define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
+#define NVMCTRL_PBLDATA_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA) MASK Register */
+
+/* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) (R/ 32) ECC Error Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:24; /*!< bit: 0..23 Error Address */
+ uint32_t :4; /*!< bit: 24..27 Reserved */
+ uint32_t TYPEL:2; /*!< bit: 28..29 Low Double-Word Error Type */
+ uint32_t TYPEH:2; /*!< bit: 30..31 High Double-Word Error Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_ECCERR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ECCERR_OFFSET 0x24 /**< \brief (NVMCTRL_ECCERR offset) ECC Error Status Register */
+#define NVMCTRL_ECCERR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ECCERR reset_value) ECC Error Status Register */
+
+#define NVMCTRL_ECCERR_ADDR_Pos 0 /**< \brief (NVMCTRL_ECCERR) Error Address */
+#define NVMCTRL_ECCERR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos)
+#define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
+#define NVMCTRL_ECCERR_TYPEL_Pos 28 /**< \brief (NVMCTRL_ECCERR) Low Double-Word Error Type */
+#define NVMCTRL_ECCERR_TYPEL_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
+#define NVMCTRL_ECCERR_TYPEL_NONE_Val _U_(0x0) /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
+#define NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1) /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
+#define NVMCTRL_ECCERR_TYPEL_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
+#define NVMCTRL_ECCERR_TYPEL_NONE (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEL_DUAL (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEH_Pos 30 /**< \brief (NVMCTRL_ECCERR) High Double-Word Error Type */
+#define NVMCTRL_ECCERR_TYPEH_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
+#define NVMCTRL_ECCERR_TYPEH_NONE_Val _U_(0x0) /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
+#define NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1) /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
+#define NVMCTRL_ECCERR_TYPEH_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
+#define NVMCTRL_ECCERR_TYPEH_NONE (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_TYPEH_DUAL (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_MASK _U_(0xF0FFFFFF) /**< \brief (NVMCTRL_ECCERR) MASK Register */
+
+/* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ECCDIS:1; /*!< bit: 0 Debugger ECC Read Disable */
+ uint8_t ECCELOG:1; /*!< bit: 1 Debugger ECC Error Tracking Mode */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_DBGCTRL_OFFSET 0x28 /**< \brief (NVMCTRL_DBGCTRL offset) Debug Control */
+#define NVMCTRL_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_DBGCTRL reset_value) Debug Control */
+
+#define NVMCTRL_DBGCTRL_ECCDIS_Pos 0 /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Read Disable */
+#define NVMCTRL_DBGCTRL_ECCDIS (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos)
+#define NVMCTRL_DBGCTRL_ECCELOG_Pos 1 /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode */
+#define NVMCTRL_DBGCTRL_ECCELOG (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos)
+#define NVMCTRL_DBGCTRL_MASK _U_(0x03) /**< \brief (NVMCTRL_DBGCTRL) MASK Register */
+
+/* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WMODE:1; /*!< bit: 0 Write Mode */
+ uint8_t APRDIS:1; /*!< bit: 1 Automatic Page Reallocation Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_SEECFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_SEECFG_OFFSET 0x2A /**< \brief (NVMCTRL_SEECFG offset) SmartEEPROM Configuration Register */
+#define NVMCTRL_SEECFG_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_SEECFG reset_value) SmartEEPROM Configuration Register */
+
+#define NVMCTRL_SEECFG_WMODE_Pos 0 /**< \brief (NVMCTRL_SEECFG) Write Mode */
+#define NVMCTRL_SEECFG_WMODE (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos)
+#define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0) /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */
+#define NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1) /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested */
+#define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
+#define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
+#define NVMCTRL_SEECFG_APRDIS_Pos 1 /**< \brief (NVMCTRL_SEECFG) Automatic Page Reallocation Disable */
+#define NVMCTRL_SEECFG_APRDIS (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos)
+#define NVMCTRL_SEECFG_MASK _U_(0x03) /**< \brief (NVMCTRL_SEECFG) MASK Register */
+
+/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) (R/ 32) SmartEEPROM Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ASEES:1; /*!< bit: 0 Active SmartEEPROM Sector */
+ uint32_t LOAD:1; /*!< bit: 1 Page Buffer Loaded */
+ uint32_t BUSY:1; /*!< bit: 2 Busy */
+ uint32_t LOCK:1; /*!< bit: 3 SmartEEPROM Write Access Is Locked */
+ uint32_t RLOCK:1; /*!< bit: 4 SmartEEPROM Write Access To Register Address Space Is Locked */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t SBLK:4; /*!< bit: 8..11 Blocks Number In a Sector */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PSZ:3; /*!< bit: 16..18 SmartEEPROM Page Size */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_SEESTAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_SEESTAT_OFFSET 0x2C /**< \brief (NVMCTRL_SEESTAT offset) SmartEEPROM Status Register */
+#define NVMCTRL_SEESTAT_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_SEESTAT reset_value) SmartEEPROM Status Register */
+
+#define NVMCTRL_SEESTAT_ASEES_Pos 0 /**< \brief (NVMCTRL_SEESTAT) Active SmartEEPROM Sector */
+#define NVMCTRL_SEESTAT_ASEES (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos)
+#define NVMCTRL_SEESTAT_LOAD_Pos 1 /**< \brief (NVMCTRL_SEESTAT) Page Buffer Loaded */
+#define NVMCTRL_SEESTAT_LOAD (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos)
+#define NVMCTRL_SEESTAT_BUSY_Pos 2 /**< \brief (NVMCTRL_SEESTAT) Busy */
+#define NVMCTRL_SEESTAT_BUSY (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos)
+#define NVMCTRL_SEESTAT_LOCK_Pos 3 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked */
+#define NVMCTRL_SEESTAT_LOCK (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos)
+#define NVMCTRL_SEESTAT_RLOCK_Pos 4 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked */
+#define NVMCTRL_SEESTAT_RLOCK (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos)
+#define NVMCTRL_SEESTAT_SBLK_Pos 8 /**< \brief (NVMCTRL_SEESTAT) Blocks Number In a Sector */
+#define NVMCTRL_SEESTAT_SBLK_Msk (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos)
+#define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
+#define NVMCTRL_SEESTAT_PSZ_Pos 16 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Page Size */
+#define NVMCTRL_SEESTAT_PSZ_Msk (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos)
+#define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
+#define NVMCTRL_SEESTAT_MASK _U_(0x00070F1F) /**< \brief (NVMCTRL_SEESTAT) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __O NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 ( /W 16) Control B */
+ RoReg8 Reserved2[0x2];
+ __I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set */
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */
+ __I NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x12 (R/ 16) Status */
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) Address */
+ __I NVMCTRL_RUNLOCK_Type RUNLOCK; /**< \brief Offset: 0x18 (R/ 32) Lock Section */
+ __I NVMCTRL_PBLDATA_Type PBLDATA[2]; /**< \brief Offset: 0x1C (R/ 32) Page Buffer Load Data x */
+ __I NVMCTRL_ECCERR_Type ECCERR; /**< \brief Offset: 0x24 (R/ 32) ECC Error Status Register */
+ __IO NVMCTRL_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x28 (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO NVMCTRL_SEECFG_Type SEECFG; /**< \brief Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register */
+ RoReg8 Reserved4[0x1];
+ __I NVMCTRL_SEESTAT_Type SEESTAT; /**< \brief Offset: 0x2C (R/ 32) SmartEEPROM Status Register */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_CB
+
+#define SECTION_NVMCTRL_CBW0
+
+#define SECTION_NVMCTRL_CBW1
+
+#define SECTION_NVMCTRL_CBW2
+
+#define SECTION_NVMCTRL_CBW3
+
+#define SECTION_NVMCTRL_CBW4
+
+#define SECTION_NVMCTRL_CBW5
+
+#define SECTION_NVMCTRL_CBW6
+
+#define SECTION_NVMCTRL_CBW7
+
+#define SECTION_NVMCTRL_FS
+
+#define SECTION_NVMCTRL_GB
+
+#define SECTION_NVMCTRL_SW0
+
+#define SECTION_NVMCTRL_SW1
+
+#define SECTION_NVMCTRL_SW2
+
+#define SECTION_NVMCTRL_SW3
+
+#define SECTION_NVMCTRL_SW4
+
+#define SECTION_NVMCTRL_SW5
+
+#define SECTION_NVMCTRL_SW6
+
+#define SECTION_NVMCTRL_SW7
+
+#define SECTION_NVMCTRL_TEMP_LOG
+
+#define SECTION_NVMCTRL_TEMP_LOG_W0
+
+#define SECTION_NVMCTRL_TEMP_LOG_W1
+
+#define SECTION_NVMCTRL_TEMP_LOG_W2
+
+#define SECTION_NVMCTRL_TEMP_LOG_W3
+
+#define SECTION_NVMCTRL_TEMP_LOG_W4
+
+#define SECTION_NVMCTRL_TEMP_LOG_W5
+
+#define SECTION_NVMCTRL_TEMP_LOG_W6
+
+#define SECTION_NVMCTRL_TEMP_LOG_W7
+
+#define SECTION_NVMCTRL_TLATCH
+
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
+#define AC_FUSES_BIAS0_Pos 0 /**< \brief (NVMCTRL_SW0) PAIR0 Bias Calibration */
+#define AC_FUSES_BIAS0_Msk (_U_(0x3) << AC_FUSES_BIAS0_Pos)
+#define AC_FUSES_BIAS0(value) (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos))
+
+#define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
+#define ADC0_FUSES_BIASCOMP_Pos 2 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
+#define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
+#define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
+
+#define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
+#define ADC0_FUSES_BIASR2R_Pos 8 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
+#define ADC0_FUSES_BIASR2R_Msk (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos)
+#define ADC0_FUSES_BIASR2R(value) (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos))
+
+#define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
+#define ADC0_FUSES_BIASREFBUF_Pos 5 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
+#define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
+#define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
+
+#define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
+#define ADC1_FUSES_BIASCOMP_Pos 16 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
+#define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
+#define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
+
+#define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
+#define ADC1_FUSES_BIASR2R_Pos 22 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
+#define ADC1_FUSES_BIASR2R_Msk (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos)
+#define ADC1_FUSES_BIASR2R(value) (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos))
+
+#define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
+#define ADC1_FUSES_BIASREFBUF_Pos 19 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
+#define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
+#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
+
+#define FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER
+#define FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */
+#define FUSES_BOD12USERLEVEL_Msk (_U_(0x3F) << FUSES_BOD12USERLEVEL_Pos)
+#define FUSES_BOD12USERLEVEL(value) (FUSES_BOD12USERLEVEL_Msk & ((value) << FUSES_BOD12USERLEVEL_Pos))
+
+#define FUSES_BOD12_ACTION_ADDR NVMCTRL_USER
+#define FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */
+#define FUSES_BOD12_ACTION_Msk (_U_(0x3) << FUSES_BOD12_ACTION_Pos)
+#define FUSES_BOD12_ACTION(value) (FUSES_BOD12_ACTION_Msk & ((value) << FUSES_BOD12_ACTION_Pos))
+
+#define FUSES_BOD12_DIS_ADDR NVMCTRL_USER
+#define FUSES_BOD12_DIS_Pos 16 /**< \brief (NVMCTRL_USER) BOD12 Disable */
+#define FUSES_BOD12_DIS_Msk (_U_(0x1) << FUSES_BOD12_DIS_Pos)
+
+#define FUSES_BOD12_HYST_ADDR NVMCTRL_USER
+#define FUSES_BOD12_HYST_Pos 25 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
+#define FUSES_BOD12_HYST_Msk (_U_(0x1) << FUSES_BOD12_HYST_Pos)
+
+#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos 1 /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos 9 /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_DIS_ADDR NVMCTRL_USER
+#define FUSES_BOD33_DIS_Pos 0 /**< \brief (NVMCTRL_USER) BOD33 Disable */
+#define FUSES_BOD33_DIS_Msk (_U_(0x1) << FUSES_BOD33_DIS_Pos)
+
+#define FUSES_BOD33_HYST_ADDR NVMCTRL_USER
+#define FUSES_BOD33_HYST_Pos 11 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk (_U_(0xF) << FUSES_BOD33_HYST_Pos)
+#define FUSES_BOD33_HYST(value) (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos))
+
+#define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
+#define FUSES_HOT_ADC_VAL_CTAT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature CTAT */
+#define FUSES_HOT_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos)
+#define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos))
+
+#define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_PTAT_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature PTAT */
+#define FUSES_HOT_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos)
+#define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
+#define FUSES_ROOM_ADC_VAL_CTAT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature CTAT */
+#define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos)
+#define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos))
+
+#define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_PTAT_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature PTAT */
+#define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos)
+#define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos 26 /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 0 /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+#define NVMCTRL_FUSES_SEEPSZ_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_SEEPSZ_Pos 4 /**< \brief (NVMCTRL_USER) Size Of SmartEEPROM Page */
+#define NVMCTRL_FUSES_SEEPSZ_Msk (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos)
+#define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos))
+
+#define NVMCTRL_FUSES_SEESBLK_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_SEESBLK_Pos 0 /**< \brief (NVMCTRL_USER) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector */
+#define NVMCTRL_FUSES_SEESBLK_Msk (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos)
+#define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos))
+
+#define RAMECC_FUSES_ECCDIS_ADDR (NVMCTRL_USER + 4)
+#define RAMECC_FUSES_ECCDIS_Pos 7 /**< \brief (NVMCTRL_USER) RAM ECC Disable fuse */
+#define RAMECC_FUSES_ECCDIS_Msk (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos)
+
+#define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
+#define USB_FUSES_TRANSN_Pos 0 /**< \brief (NVMCTRL_SW0) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
+#define USB_FUSES_TRANSP_Pos 5 /**< \brief (NVMCTRL_SW0) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
+#define USB_FUSES_TRIM_Pos 10 /**< \brief (NVMCTRL_SW0) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk (_U_(0x7) << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_ALWAYSON_Pos 17 /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_ENABLE_Pos 16 /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos 26 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_PER_Pos 18 /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos 30 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_Pos 22 /**< \brief (NVMCTRL_USER) WDT Window */
+#define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
+#define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
+
+/*@}*/
+
+#endif /* _SAME54_NVMCTRL_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/osc32kctrl.h b/GPIO/ATSAME54/include/component/osc32kctrl.h
new file mode 100644
index 0000000..893c006
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/osc32kctrl.h
@@ -0,0 +1,303 @@
+/**
+ * \file
+ *
+ * \brief Component description for OSC32KCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_OSC32KCTRL_COMPONENT_
+#define _SAME54_OSC32KCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME54_OSC32KCTRL 32kHz Oscillators Control */
+/*@{*/
+
+#define OSC32KCTRL_U2400
+#define REV_OSC32KCTRL 0x100
+
+/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
+
+/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTENSET_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
+
+/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
+ __I uint32_t :1; /*!< bit: 1 Reserved */
+ __I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
+ __I uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
+
+/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
+ uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
+#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
+
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
+#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
+#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
+#define OSC32KCTRL_STATUS_MASK _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
+
+/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSC32KCTRL_RTCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
+
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} OSC32KCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
+#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
+#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
+#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
+#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
+#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
+#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
+#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
+#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
+#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
+#define OSC32KCTRL_XOSC32K_CGM_Pos 13 /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
+#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
+#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
+#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
+#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
+
+/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */
+ uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */
+ uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSC32KCTRL_CFDCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
+#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
+
+#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
+#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
+#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
+#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
+#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSC32KCTRL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
+#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
+
+#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
+#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
+#define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */
+ uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
+ uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSC32KCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
+#define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
+#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
+#define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
+#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
+#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
+#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
+#define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
+
+/** \brief OSC32KCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */
+ RoReg8 Reserved1[0x3];
+ __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ __IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */
+ __IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */
+ RoReg8 Reserved2[0x4];
+ __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+} Osc32kctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/oscctrl.h b/GPIO/ATSAME54/include/component/oscctrl.h
new file mode 100644
index 0000000..2873841
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/oscctrl.h
@@ -0,0 +1,793 @@
+/**
+ * \file
+ *
+ * \brief Component description for OSCCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_OSCCTRL_COMPONENT_
+#define _SAME54_OSCCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR OSCCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME54_OSCCTRL Oscillators Control */
+/*@{*/
+
+#define OSCCTRL_U2401
+#define REV_OSCCTRL 0x100
+
+/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CFDEO0:1; /*!< bit: 0 Clock 0 Failure Detector Event Output Enable */
+ uint8_t CFDEO1:1; /*!< bit: 1 Clock 1 Failure Detector Event Output Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CFDEO:2; /*!< bit: 0.. 1 Clock x Failure Detector Event Output Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_EVCTRL_OFFSET 0x00 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
+#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
+
+#define OSCCTRL_EVCTRL_CFDEO0_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
+#define OSCCTRL_EVCTRL_CFDEO1_Pos 1 /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
+#define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
+#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
+#define OSCCTRL_EVCTRL_MASK _U_(0x03) /**< \brief (OSCCTRL_EVCTRL) MASK Register */
+
+/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
+ uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
+ uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
+ uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
+ uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
+ uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
+ uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
+ uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
+ uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
+ uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
+ uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENCLR_OFFSET 0x04 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
+#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
+#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
+#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
+#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
+
+/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
+ uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
+ uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
+ uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
+ uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
+ uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
+ uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
+ uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
+ uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
+ uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
+ uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENSET_OFFSET 0x08 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSCCTRL_INTENSET_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
+#define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
+#define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
+#define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
+#define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
+#define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
+#define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
+#define OSCCTRL_INTENSET_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
+#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
+#define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
+#define OSCCTRL_INTENSET_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
+#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */
+
+/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
+ __I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
+ __I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
+ __I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
+ __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
+ __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
+ __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
+ __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
+ __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
+ __I uint32_t :3; /*!< bit: 13..15 Reserved */
+ __I uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
+ __I uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
+ __I uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout */
+ __I uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
+ __I uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
+ __I uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout */
+ __I uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
+ __I uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
+ __I uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTFLAG_OFFSET 0x0C /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
+#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
+#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
+#define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
+#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
+#define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
+#define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
+#define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
+#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */
+#define OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */
+#define OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */
+#define OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */
+#define OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */
+#define OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */
+#define OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */
+#define OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */
+#define OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
+
+/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/ 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
+ uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
+ uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
+ uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
+ uint32_t XOSCCKSW0:1; /*!< bit: 4 XOSC 0 Clock Switch */
+ uint32_t XOSCCKSW1:1; /*!< bit: 5 XOSC 1 Clock Switch */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
+ uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
+ uint32_t DPLL0TO:1; /*!< bit: 18 DPLL0 Timeout */
+ uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
+ uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
+ uint32_t DPLL1TO:1; /*!< bit: 26 DPLL1 Timeout */
+ uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
+ uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
+ uint32_t XOSCCKSW:2; /*!< bit: 4.. 5 XOSC x Clock Switch */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_STATUS_OFFSET 0x10 /**< \brief (OSCCTRL_STATUS offset) Status */
+#define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */
+
+#define OSCCTRL_STATUS_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */
+#define OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
+#define OSCCTRL_STATUS_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */
+#define OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
+#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC x Ready */
+#define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
+#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
+#define OSCCTRL_STATUS_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
+#define OSCCTRL_STATUS_XOSCCKSW0_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW1_Pos 5 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
+#define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */
+#define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
+#define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
+#define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
+#define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
+#define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
+#define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
+#define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
+#define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
+#define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
+#define OSCCTRL_STATUS_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */
+#define OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
+#define OSCCTRL_STATUS_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */
+#define OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
+#define OSCCTRL_STATUS_DPLL0TO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */
+#define OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
+#define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */
+#define OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
+#define OSCCTRL_STATUS_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */
+#define OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
+#define OSCCTRL_STATUS_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */
+#define OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
+#define OSCCTRL_STATUS_DPLL1TO_Pos 26 /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */
+#define OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
+#define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */
+#define OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
+#define OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */
+
+/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t LOWBUFGAIN:1; /*!< bit: 8 Low Buffer Gain Enable */
+ uint32_t IPTAT:2; /*!< bit: 9..10 Oscillator Current Reference */
+ uint32_t IMULT:4; /*!< bit: 11..14 Oscillator Current Multiplier */
+ uint32_t ENALC:1; /*!< bit: 15 Automatic Loop Control Enable */
+ uint32_t CFDEN:1; /*!< bit: 16 Clock Failure Detector Enable */
+ uint32_t SWBEN:1; /*!< bit: 17 Xosc Clock Switch Enable */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t STARTUP:4; /*!< bit: 20..23 Start-Up Time */
+ uint32_t CFDPRESC:4; /*!< bit: 24..27 Clock Failure Detector Prescaler */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_XOSCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_XOSCCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */
+#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */
+
+#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
+#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
+#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
+#define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
+#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
+#define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
+#define OSCCTRL_XOSCCTRL_IPTAT_Pos 9 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */
+#define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
+#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
+#define OSCCTRL_XOSCCTRL_IMULT_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */
+#define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
+#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
+#define OSCCTRL_XOSCCTRL_ENALC_Pos 15 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */
+#define OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
+#define OSCCTRL_XOSCCTRL_CFDEN_Pos 16 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */
+#define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
+#define OSCCTRL_XOSCCTRL_SWBEN_Pos 17 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
+#define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP_Pos 20 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
+#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
+#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
+#define OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */
+#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */
+
+#define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */
+#define OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DFLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MODE:1; /*!< bit: 0 Operating Mode Selection */
+ uint8_t STABLE:1; /*!< bit: 1 Stable DFLL Frequency */
+ uint8_t LLAW:1; /*!< bit: 2 Lose Lock After Wake */
+ uint8_t USBCRM:1; /*!< bit: 3 USB Clock Recovery Mode */
+ uint8_t CCDIS:1; /*!< bit: 4 Chill Cycle Disable */
+ uint8_t QLDIS:1; /*!< bit: 5 Quick Lock Disable */
+ uint8_t BPLCKC:1; /*!< bit: 6 Bypass Coarse Lock */
+ uint8_t WAITLOCK:1; /*!< bit: 7 Wait Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRLB_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */
+#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */
+
+#define OSCCTRL_DFLLCTRLB_MODE_Pos 0 /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */
+#define OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
+#define OSCCTRL_DFLLCTRLB_STABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */
+#define OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
+#define OSCCTRL_DFLLCTRLB_LLAW_Pos 2 /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */
+#define OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
+#define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3 /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */
+#define OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
+#define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4 /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */
+#define OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
+#define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5 /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */
+#define OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
+#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */
+#define OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
+#define OSCCTRL_DFLLCTRLB_MASK _U_(0xFF) /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */
+ uint32_t :2; /*!< bit: 8.. 9 Reserved */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLVAL_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
+#define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
+#define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
+#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
+#define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
+#define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
+#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
+#define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
+#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
+#define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
+
+/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:8; /*!< bit: 16..23 Fine Maximum Step */
+ uint32_t :2; /*!< bit: 24..25 Reserved */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLMUL_OFFSET 0x28 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
+#define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
+#define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
+#define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
+#define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
+#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
+#define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
+#define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
+#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
+#define OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
+
+/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
+ uint8_t DFLLCTRLB:1; /*!< bit: 2 DFLLCTRLB Synchronization Busy */
+ uint8_t DFLLVAL:1; /*!< bit: 3 DFLLVAL Synchronization Busy */
+ uint8_t DFLLMUL:1; /*!< bit: 4 DFLLMUL Synchronization Busy */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLSYNC_OFFSET 0x2C /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define OSCCTRL_DFLLSYNC_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2 /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3 /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4 /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
+#define OSCCTRL_DFLLSYNC_MASK _U_(0x1E) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLA_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */
+#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */
+#define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */
+#define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLRATIO_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
+#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
+#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */
+ uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */
+ uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */
+ uint32_t DCOFILTER:3; /*!< bit: 12..14 Sigma-Delta DCO Filter Selection */
+ uint32_t DCOEN:1; /*!< bit: 15 DCO Filter Enable */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLB_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */
+#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_WUF_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
+#define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
+#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
+#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
+#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
+#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
+#define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
+#define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
+#define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
+#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
+#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
+#define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15 /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */
+#define OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
+#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
+#define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/ 32) DPLL DPLL Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */
+ uint32_t DPLLRATIO:1; /*!< bit: 2 DPLL Loop Divider Ratio Synchronization Status */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLSYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
+#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
+
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
+
+/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/ 32) DPLL DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint32_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} OSCCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSTATUS_OFFSET 0x40 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
+#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
+#define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
+#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
+#define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief OscctrlDpll hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x00 (R/W 8) DPLL Control A */
+ RoReg8 Reserved1[0x3];
+ __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */
+ __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */
+ __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) DPLL Synchronization Busy */
+ __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x10 (R/ 32) DPLL Status */
+} OscctrlDpll;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief OSCCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x00 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x3];
+ __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */
+ __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */
+ __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
+ __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/ 32) Status */
+ __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
+ __IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DFLL48M Control A */
+ RoReg8 Reserved2[0x3];
+ __IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB; /**< \brief Offset: 0x20 (R/W 8) DFLL48M Control B */
+ RoReg8 Reserved3[0x3];
+ __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */
+ __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */
+ __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x2C (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved4[0x3];
+ OscctrlDpll Dpll[2]; /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */
+} Oscctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_OSCCTRL_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/pac.h b/GPIO/ATSAME54/include/component/pac.h
new file mode 100644
index 0000000..a16eca1
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/pac.h
@@ -0,0 +1,690 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PAC_COMPONENT_
+#define _SAME54_PAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAME54_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2120
+#define REV_PAC 0x120
+
+/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */
+ uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */
+#define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
+
+#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */
+#define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
+#define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
+#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */
+#define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
+#define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */
+#define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */
+#define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */
+#define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */
+#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
+
+/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */
+#define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */
+
+#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
+#define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
+#define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */
+
+/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
+#define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
+
+#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
+#define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
+#define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */
+
+/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */
+#define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
+
+#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
+#define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
+#define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */
+
+/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
+ __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */
+ __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */
+ __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */
+ __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */
+ __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */
+ __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */
+ __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */
+ __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */
+ __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */
+ __I uint32_t HPB3_:1; /*!< bit: 10 HPB3 */
+ __I uint32_t PUKCC_:1; /*!< bit: 11 PUKCC */
+ __I uint32_t SDHC0_:1; /*!< bit: 12 SDHC0 */
+ __I uint32_t SDHC1_:1; /*!< bit: 13 SDHC1 */
+ __I uint32_t QSPI_:1; /*!< bit: 14 QSPI */
+ __I uint32_t BKUPRAM_:1; /*!< bit: 15 BKUPRAM */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGAHB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
+#define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
+
+#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */
+#define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
+#define PAC_INTFLAGAHB_FLASH_ALT_Pos 1 /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */
+#define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
+#define PAC_INTFLAGAHB_SEEPROM_Pos 2 /**< \brief (PAC_INTFLAGAHB) SEEPROM */
+#define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
+#define PAC_INTFLAGAHB_RAMCM4S_Pos 3 /**< \brief (PAC_INTFLAGAHB) RAMCM4S */
+#define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
+#define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4 /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */
+#define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
+#define PAC_INTFLAGAHB_RAMDMAWR_Pos 5 /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */
+#define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
+#define PAC_INTFLAGAHB_RAMDMACICM_Pos 6 /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */
+#define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
+#define PAC_INTFLAGAHB_HPB0_Pos 7 /**< \brief (PAC_INTFLAGAHB) HPB0 */
+#define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
+#define PAC_INTFLAGAHB_HPB1_Pos 8 /**< \brief (PAC_INTFLAGAHB) HPB1 */
+#define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
+#define PAC_INTFLAGAHB_HPB2_Pos 9 /**< \brief (PAC_INTFLAGAHB) HPB2 */
+#define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
+#define PAC_INTFLAGAHB_HPB3_Pos 10 /**< \brief (PAC_INTFLAGAHB) HPB3 */
+#define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
+#define PAC_INTFLAGAHB_PUKCC_Pos 11 /**< \brief (PAC_INTFLAGAHB) PUKCC */
+#define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
+#define PAC_INTFLAGAHB_SDHC0_Pos 12 /**< \brief (PAC_INTFLAGAHB) SDHC0 */
+#define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
+#define PAC_INTFLAGAHB_SDHC1_Pos 13 /**< \brief (PAC_INTFLAGAHB) SDHC1 */
+#define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
+#define PAC_INTFLAGAHB_QSPI_Pos 14 /**< \brief (PAC_INTFLAGAHB) QSPI */
+#define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
+#define PAC_INTFLAGAHB_BKUPRAM_Pos 15 /**< \brief (PAC_INTFLAGAHB) BKUPRAM */
+#define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
+#define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
+
+/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t PAC_:1; /*!< bit: 0 PAC */
+ __I uint32_t PM_:1; /*!< bit: 1 PM */
+ __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */
+ __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */
+ __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */
+ __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */
+ __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */
+ __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */
+ __I uint32_t WDT_:1; /*!< bit: 8 WDT */
+ __I uint32_t RTC_:1; /*!< bit: 9 RTC */
+ __I uint32_t EIC_:1; /*!< bit: 10 EIC */
+ __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */
+ __I uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 */
+ __I uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 */
+ __I uint32_t TC0_:1; /*!< bit: 14 TC0 */
+ __I uint32_t TC1_:1; /*!< bit: 15 TC1 */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
+#define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
+
+#define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */
+#define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
+#define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */
+#define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
+#define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */
+#define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
+#define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */
+#define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
+#define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */
+#define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
+#define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
+#define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
+#define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */
+#define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
+#define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */
+#define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
+#define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */
+#define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
+#define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */
+#define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
+#define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */
+#define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
+#define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */
+#define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
+#define PAC_INTFLAGA_SERCOM0_Pos 12 /**< \brief (PAC_INTFLAGA) SERCOM0 */
+#define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
+#define PAC_INTFLAGA_SERCOM1_Pos 13 /**< \brief (PAC_INTFLAGA) SERCOM1 */
+#define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
+#define PAC_INTFLAGA_TC0_Pos 14 /**< \brief (PAC_INTFLAGA) TC0 */
+#define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
+#define PAC_INTFLAGA_TC1_Pos 15 /**< \brief (PAC_INTFLAGA) TC1 */
+#define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
+#define PAC_INTFLAGA_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */
+
+/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t USB_:1; /*!< bit: 0 USB */
+ __I uint32_t DSU_:1; /*!< bit: 1 DSU */
+ __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */
+ __I uint32_t CMCC_:1; /*!< bit: 3 CMCC */
+ __I uint32_t PORT_:1; /*!< bit: 4 PORT */
+ __I uint32_t DMAC_:1; /*!< bit: 5 DMAC */
+ __I uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX */
+ __I uint32_t EVSYS_:1; /*!< bit: 7 EVSYS */
+ __I uint32_t :1; /*!< bit: 8 Reserved */
+ __I uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 */
+ __I uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 */
+ __I uint32_t TCC0_:1; /*!< bit: 11 TCC0 */
+ __I uint32_t TCC1_:1; /*!< bit: 12 TCC1 */
+ __I uint32_t TC2_:1; /*!< bit: 13 TC2 */
+ __I uint32_t TC3_:1; /*!< bit: 14 TC3 */
+ __I uint32_t TAL_:1; /*!< bit: 15 TAL */
+ __I uint32_t RAMECC_:1; /*!< bit: 16 RAMECC */
+ __I uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
+#define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
+
+#define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */
+#define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
+#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */
+#define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
+#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */
+#define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
+#define PAC_INTFLAGB_CMCC_Pos 3 /**< \brief (PAC_INTFLAGB) CMCC */
+#define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
+#define PAC_INTFLAGB_PORT_Pos 4 /**< \brief (PAC_INTFLAGB) PORT */
+#define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
+#define PAC_INTFLAGB_DMAC_Pos 5 /**< \brief (PAC_INTFLAGB) DMAC */
+#define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
+#define PAC_INTFLAGB_HMATRIX_Pos 6 /**< \brief (PAC_INTFLAGB) HMATRIX */
+#define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
+#define PAC_INTFLAGB_EVSYS_Pos 7 /**< \brief (PAC_INTFLAGB) EVSYS */
+#define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
+#define PAC_INTFLAGB_SERCOM2_Pos 9 /**< \brief (PAC_INTFLAGB) SERCOM2 */
+#define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
+#define PAC_INTFLAGB_SERCOM3_Pos 10 /**< \brief (PAC_INTFLAGB) SERCOM3 */
+#define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
+#define PAC_INTFLAGB_TCC0_Pos 11 /**< \brief (PAC_INTFLAGB) TCC0 */
+#define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
+#define PAC_INTFLAGB_TCC1_Pos 12 /**< \brief (PAC_INTFLAGB) TCC1 */
+#define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
+#define PAC_INTFLAGB_TC2_Pos 13 /**< \brief (PAC_INTFLAGB) TC2 */
+#define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
+#define PAC_INTFLAGB_TC3_Pos 14 /**< \brief (PAC_INTFLAGB) TC3 */
+#define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
+#define PAC_INTFLAGB_TAL_Pos 15 /**< \brief (PAC_INTFLAGB) TAL */
+#define PAC_INTFLAGB_TAL (_U_(0x1) << PAC_INTFLAGB_TAL_Pos)
+#define PAC_INTFLAGB_RAMECC_Pos 16 /**< \brief (PAC_INTFLAGB) RAMECC */
+#define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
+#define PAC_INTFLAGB_MASK _U_(0x0001FEFF) /**< \brief (PAC_INTFLAGB) MASK Register */
+
+/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t CAN0_:1; /*!< bit: 0 CAN0 */
+ __I uint32_t CAN1_:1; /*!< bit: 1 CAN1 */
+ __I uint32_t GMAC_:1; /*!< bit: 2 GMAC */
+ __I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */
+ __I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */
+ __I uint32_t TC4_:1; /*!< bit: 5 TC4 */
+ __I uint32_t TC5_:1; /*!< bit: 6 TC5 */
+ __I uint32_t PDEC_:1; /*!< bit: 7 PDEC */
+ __I uint32_t AC_:1; /*!< bit: 8 AC */
+ __I uint32_t AES_:1; /*!< bit: 9 AES */
+ __I uint32_t TRNG_:1; /*!< bit: 10 TRNG */
+ __I uint32_t ICM_:1; /*!< bit: 11 ICM */
+ __I uint32_t PUKCC_:1; /*!< bit: 12 PUKCC */
+ __I uint32_t QSPI_:1; /*!< bit: 13 QSPI */
+ __I uint32_t CCL_:1; /*!< bit: 14 CCL */
+ __I uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
+#define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
+
+#define PAC_INTFLAGC_CAN0_Pos 0 /**< \brief (PAC_INTFLAGC) CAN0 */
+#define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
+#define PAC_INTFLAGC_CAN1_Pos 1 /**< \brief (PAC_INTFLAGC) CAN1 */
+#define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
+#define PAC_INTFLAGC_GMAC_Pos 2 /**< \brief (PAC_INTFLAGC) GMAC */
+#define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
+#define PAC_INTFLAGC_TCC2_Pos 3 /**< \brief (PAC_INTFLAGC) TCC2 */
+#define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
+#define PAC_INTFLAGC_TCC3_Pos 4 /**< \brief (PAC_INTFLAGC) TCC3 */
+#define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
+#define PAC_INTFLAGC_TC4_Pos 5 /**< \brief (PAC_INTFLAGC) TC4 */
+#define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
+#define PAC_INTFLAGC_TC5_Pos 6 /**< \brief (PAC_INTFLAGC) TC5 */
+#define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
+#define PAC_INTFLAGC_PDEC_Pos 7 /**< \brief (PAC_INTFLAGC) PDEC */
+#define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
+#define PAC_INTFLAGC_AC_Pos 8 /**< \brief (PAC_INTFLAGC) AC */
+#define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
+#define PAC_INTFLAGC_AES_Pos 9 /**< \brief (PAC_INTFLAGC) AES */
+#define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
+#define PAC_INTFLAGC_TRNG_Pos 10 /**< \brief (PAC_INTFLAGC) TRNG */
+#define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
+#define PAC_INTFLAGC_ICM_Pos 11 /**< \brief (PAC_INTFLAGC) ICM */
+#define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
+#define PAC_INTFLAGC_PUKCC_Pos 12 /**< \brief (PAC_INTFLAGC) PUKCC */
+#define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
+#define PAC_INTFLAGC_QSPI_Pos 13 /**< \brief (PAC_INTFLAGC) QSPI */
+#define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
+#define PAC_INTFLAGC_CCL_Pos 14 /**< \brief (PAC_INTFLAGC) CCL */
+#define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
+#define PAC_INTFLAGC_MASK _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */
+
+/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 */
+ __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */
+ __I uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 */
+ __I uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 */
+ __I uint32_t TCC4_:1; /*!< bit: 4 TCC4 */
+ __I uint32_t TC6_:1; /*!< bit: 5 TC6 */
+ __I uint32_t TC7_:1; /*!< bit: 6 TC7 */
+ __I uint32_t ADC0_:1; /*!< bit: 7 ADC0 */
+ __I uint32_t ADC1_:1; /*!< bit: 8 ADC1 */
+ __I uint32_t DAC_:1; /*!< bit: 9 DAC */
+ __I uint32_t I2S_:1; /*!< bit: 10 I2S */
+ __I uint32_t PCC_:1; /*!< bit: 11 PCC */
+ __I uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_INTFLAGD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
+#define PAC_INTFLAGD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
+
+#define PAC_INTFLAGD_SERCOM4_Pos 0 /**< \brief (PAC_INTFLAGD) SERCOM4 */
+#define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
+#define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */
+#define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
+#define PAC_INTFLAGD_SERCOM6_Pos 2 /**< \brief (PAC_INTFLAGD) SERCOM6 */
+#define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
+#define PAC_INTFLAGD_SERCOM7_Pos 3 /**< \brief (PAC_INTFLAGD) SERCOM7 */
+#define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
+#define PAC_INTFLAGD_TCC4_Pos 4 /**< \brief (PAC_INTFLAGD) TCC4 */
+#define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
+#define PAC_INTFLAGD_TC6_Pos 5 /**< \brief (PAC_INTFLAGD) TC6 */
+#define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
+#define PAC_INTFLAGD_TC7_Pos 6 /**< \brief (PAC_INTFLAGD) TC7 */
+#define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
+#define PAC_INTFLAGD_ADC0_Pos 7 /**< \brief (PAC_INTFLAGD) ADC0 */
+#define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
+#define PAC_INTFLAGD_ADC1_Pos 8 /**< \brief (PAC_INTFLAGD) ADC1 */
+#define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
+#define PAC_INTFLAGD_DAC_Pos 9 /**< \brief (PAC_INTFLAGD) DAC */
+#define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
+#define PAC_INTFLAGD_I2S_Pos 10 /**< \brief (PAC_INTFLAGD) I2S */
+#define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
+#define PAC_INTFLAGD_PCC_Pos 11 /**< \brief (PAC_INTFLAGD) PCC */
+#define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
+#define PAC_INTFLAGD_MASK _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */
+
+/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */
+ uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */
+ uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */
+ uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */
+ uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */
+ uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */
+ uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */
+ uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */
+ uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */
+ uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */
+ uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Protect Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Protect Enable */
+ uint32_t TC0_:1; /*!< bit: 14 TC0 APB Protect Enable */
+ uint32_t TC1_:1; /*!< bit: 15 TC1 APB Protect Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
+#define PAC_STATUSA_RESETVALUE _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
+
+#define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
+#define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
+#define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */
+#define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
+#define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
+#define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
+#define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
+#define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
+#define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
+#define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
+#define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
+#define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
+#define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
+#define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
+#define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
+#define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
+#define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
+#define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
+#define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
+#define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
+#define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
+#define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
+#define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
+#define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
+#define PAC_STATUSA_SERCOM0_Pos 12 /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */
+#define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
+#define PAC_STATUSA_SERCOM1_Pos 13 /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */
+#define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
+#define PAC_STATUSA_TC0_Pos 14 /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */
+#define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos)
+#define PAC_STATUSA_TC1_Pos 15 /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */
+#define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos)
+#define PAC_STATUSA_MASK _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */
+
+/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */
+ uint32_t CMCC_:1; /*!< bit: 3 CMCC APB Protect Enable */
+ uint32_t PORT_:1; /*!< bit: 4 PORT APB Protect Enable */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC APB Protect Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Protect Enable */
+ uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Protect Enable */
+ uint32_t :1; /*!< bit: 8 Reserved */
+ uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Protect Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Protect Enable */
+ uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Protect Enable */
+ uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Protect Enable */
+ uint32_t TC2_:1; /*!< bit: 13 TC2 APB Protect Enable */
+ uint32_t TC3_:1; /*!< bit: 14 TC3 APB Protect Enable */
+ uint32_t TAL_:1; /*!< bit: 15 TAL APB Protect Enable */
+ uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Protect Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
+#define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
+
+#define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */
+#define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos)
+#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
+#define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
+#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
+#define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
+#define PAC_STATUSB_CMCC_Pos 3 /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */
+#define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
+#define PAC_STATUSB_PORT_Pos 4 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
+#define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
+#define PAC_STATUSB_DMAC_Pos 5 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
+#define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
+#define PAC_STATUSB_HMATRIX_Pos 6 /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */
+#define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
+#define PAC_STATUSB_EVSYS_Pos 7 /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */
+#define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
+#define PAC_STATUSB_SERCOM2_Pos 9 /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */
+#define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
+#define PAC_STATUSB_SERCOM3_Pos 10 /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */
+#define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
+#define PAC_STATUSB_TCC0_Pos 11 /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */
+#define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
+#define PAC_STATUSB_TCC1_Pos 12 /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */
+#define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
+#define PAC_STATUSB_TC2_Pos 13 /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */
+#define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos)
+#define PAC_STATUSB_TC3_Pos 14 /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */
+#define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos)
+#define PAC_STATUSB_TAL_Pos 15 /**< \brief (PAC_STATUSB) TAL APB Protect Enable */
+#define PAC_STATUSB_TAL (_U_(0x1) << PAC_STATUSB_TAL_Pos)
+#define PAC_STATUSB_RAMECC_Pos 16 /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */
+#define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
+#define PAC_STATUSB_MASK _U_(0x0001FEFF) /**< \brief (PAC_STATUSB) MASK Register */
+
+/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CAN0_:1; /*!< bit: 0 CAN0 APB Protect Enable */
+ uint32_t CAN1_:1; /*!< bit: 1 CAN1 APB Protect Enable */
+ uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Protect Enable */
+ uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */
+ uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */
+ uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */
+ uint32_t TC5_:1; /*!< bit: 6 TC5 APB Protect Enable */
+ uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Protect Enable */
+ uint32_t AC_:1; /*!< bit: 8 AC APB Protect Enable */
+ uint32_t AES_:1; /*!< bit: 9 AES APB Protect Enable */
+ uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Protect Enable */
+ uint32_t ICM_:1; /*!< bit: 11 ICM APB Protect Enable */
+ uint32_t PUKCC_:1; /*!< bit: 12 PUKCC APB Protect Enable */
+ uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Protect Enable */
+ uint32_t CCL_:1; /*!< bit: 14 CCL APB Protect Enable */
+ uint32_t :17; /*!< bit: 15..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
+#define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
+
+#define PAC_STATUSC_CAN0_Pos 0 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */
+#define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
+#define PAC_STATUSC_CAN1_Pos 1 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */
+#define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
+#define PAC_STATUSC_GMAC_Pos 2 /**< \brief (PAC_STATUSC) GMAC APB Protect Enable */
+#define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
+#define PAC_STATUSC_TCC2_Pos 3 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
+#define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
+#define PAC_STATUSC_TCC3_Pos 4 /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
+#define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
+#define PAC_STATUSC_TC4_Pos 5 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
+#define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
+#define PAC_STATUSC_TC5_Pos 6 /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */
+#define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos)
+#define PAC_STATUSC_PDEC_Pos 7 /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */
+#define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
+#define PAC_STATUSC_AC_Pos 8 /**< \brief (PAC_STATUSC) AC APB Protect Enable */
+#define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
+#define PAC_STATUSC_AES_Pos 9 /**< \brief (PAC_STATUSC) AES APB Protect Enable */
+#define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos)
+#define PAC_STATUSC_TRNG_Pos 10 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
+#define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
+#define PAC_STATUSC_ICM_Pos 11 /**< \brief (PAC_STATUSC) ICM APB Protect Enable */
+#define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos)
+#define PAC_STATUSC_PUKCC_Pos 12 /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */
+#define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
+#define PAC_STATUSC_QSPI_Pos 13 /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */
+#define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
+#define PAC_STATUSC_CCL_Pos 14 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
+#define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
+#define PAC_STATUSC_MASK _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */
+
+/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Protect Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */
+ uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Protect Enable */
+ uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Protect Enable */
+ uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Protect Enable */
+ uint32_t TC6_:1; /*!< bit: 5 TC6 APB Protect Enable */
+ uint32_t TC7_:1; /*!< bit: 6 TC7 APB Protect Enable */
+ uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Protect Enable */
+ uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Protect Enable */
+ uint32_t DAC_:1; /*!< bit: 9 DAC APB Protect Enable */
+ uint32_t I2S_:1; /*!< bit: 10 I2S APB Protect Enable */
+ uint32_t PCC_:1; /*!< bit: 11 PCC APB Protect Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_STATUSD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
+#define PAC_STATUSD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
+
+#define PAC_STATUSD_SERCOM4_Pos 0 /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */
+#define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
+#define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
+#define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
+#define PAC_STATUSD_SERCOM6_Pos 2 /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */
+#define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
+#define PAC_STATUSD_SERCOM7_Pos 3 /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */
+#define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
+#define PAC_STATUSD_TCC4_Pos 4 /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */
+#define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
+#define PAC_STATUSD_TC6_Pos 5 /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */
+#define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos)
+#define PAC_STATUSD_TC7_Pos 6 /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */
+#define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos)
+#define PAC_STATUSD_ADC0_Pos 7 /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */
+#define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
+#define PAC_STATUSD_ADC1_Pos 8 /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */
+#define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
+#define PAC_STATUSD_DAC_Pos 9 /**< \brief (PAC_STATUSD) DAC APB Protect Enable */
+#define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos)
+#define PAC_STATUSD_I2S_Pos 10 /**< \brief (PAC_STATUSD) I2S APB Protect Enable */
+#define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos)
+#define PAC_STATUSD_PCC_Pos 11 /**< \brief (PAC_STATUSD) PCC APB Protect Enable */
+#define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos)
+#define PAC_STATUSD_MASK _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */
+ __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */
+ RoReg8 Reserved1[0x3];
+ __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */
+ __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */
+ RoReg8 Reserved2[0x6];
+ __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
+ __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
+ __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
+ __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
+ __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
+ RoReg8 Reserved3[0x10];
+ __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */
+ __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */
+ __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */
+ __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PAC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/pcc.h b/GPIO/ATSAME54/include/component/pcc.h
new file mode 100644
index 0000000..cf4330b
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/pcc.h
@@ -0,0 +1,251 @@
+/**
+ * \file
+ *
+ * \brief Component description for PCC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PCC_COMPONENT_
+#define _SAME54_PCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PCC */
+/* ========================================================================== */
+/** \addtogroup SAME54_PCC Parallel Capture Controller */
+/*@{*/
+
+#define PCC_U2017
+#define REV_PCC 0x110
+
+/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */
+ uint32_t :3; /*!< bit: 1.. 3 Reserved */
+ uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t SCALE:1; /*!< bit: 8 Scale data */
+ uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */
+ uint32_t HALFS:1; /*!< bit: 10 Half Sampling */
+ uint32_t FRSTS:1; /*!< bit: 11 First sample */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */
+ uint32_t :11; /*!< bit: 19..29 Reserved */
+ uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_MR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_MR_OFFSET 0x00 /**< \brief (PCC_MR offset) Mode Register */
+#define PCC_MR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
+
+#define PCC_MR_PCEN_Pos 0 /**< \brief (PCC_MR) Parallel Capture Enable */
+#define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
+#define PCC_MR_DSIZE_Pos 4 /**< \brief (PCC_MR) Data size */
+#define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
+#define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
+#define PCC_MR_SCALE_Pos 8 /**< \brief (PCC_MR) Scale data */
+#define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
+#define PCC_MR_ALWYS_Pos 9 /**< \brief (PCC_MR) Always Sampling */
+#define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
+#define PCC_MR_HALFS_Pos 10 /**< \brief (PCC_MR) Half Sampling */
+#define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
+#define PCC_MR_FRSTS_Pos 11 /**< \brief (PCC_MR) First sample */
+#define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
+#define PCC_MR_ISIZE_Pos 16 /**< \brief (PCC_MR) Input Data Size */
+#define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
+#define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
+#define PCC_MR_CID_Pos 30 /**< \brief (PCC_MR) Clear If Disabled */
+#define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
+#define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
+#define PCC_MR_MASK _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
+
+/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IER_OFFSET 0x04 /**< \brief (PCC_IER offset) Interrupt Enable Register */
+#define PCC_IER_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
+
+#define PCC_IER_DRDY_Pos 0 /**< \brief (PCC_IER) Data Ready Interrupt Enable */
+#define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
+#define PCC_IER_OVRE_Pos 1 /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
+#define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
+#define PCC_IER_MASK _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
+
+/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IDR_OFFSET 0x08 /**< \brief (PCC_IDR offset) Interrupt Disable Register */
+#define PCC_IDR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
+
+#define PCC_IDR_DRDY_Pos 0 /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
+#define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
+#define PCC_IDR_OVRE_Pos 1 /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
+#define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
+#define PCC_IDR_MASK _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
+
+/* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IMR_OFFSET 0x0C /**< \brief (PCC_IMR offset) Interrupt Mask Register */
+#define PCC_IMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
+
+#define PCC_IMR_DRDY_Pos 0 /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
+#define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
+#define PCC_IMR_OVRE_Pos 1 /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
+#define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
+#define PCC_IMR_MASK _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
+
+/* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */
+ uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_ISR_OFFSET 0x10 /**< \brief (PCC_ISR offset) Interrupt Status Register */
+#define PCC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
+
+#define PCC_ISR_DRDY_Pos 0 /**< \brief (PCC_ISR) Data Ready Interrupt Status */
+#define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
+#define PCC_ISR_OVRE_Pos 1 /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
+#define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
+#define PCC_ISR_MASK _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
+
+/* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_RHR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_RHR_OFFSET 0x14 /**< \brief (PCC_RHR offset) Reception Holding Register */
+#define PCC_RHR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
+
+#define PCC_RHR_RDATA_Pos 0 /**< \brief (PCC_RHR) Reception Data */
+#define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
+#define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
+#define PCC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
+
+/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_WPMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_WPMR_OFFSET 0xE0 /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
+#define PCC_WPMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
+
+#define PCC_WPMR_WPEN_Pos 0 /**< \brief (PCC_WPMR) Write Protection Enable */
+#define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
+#define PCC_WPMR_WPKEY_Pos 8 /**< \brief (PCC_WPMR) Write Protection Key */
+#define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
+#define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
+#define PCC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
+
+/* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PCC_WPSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_WPSR_OFFSET 0xE4 /**< \brief (PCC_WPSR offset) Write Protection Status Register */
+#define PCC_WPSR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
+
+#define PCC_WPSR_WPVS_Pos 0 /**< \brief (PCC_WPSR) Write Protection Violation Source */
+#define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
+#define PCC_WPSR_WPVSRC_Pos 8 /**< \brief (PCC_WPSR) Write Protection Violation Status */
+#define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
+#define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
+#define PCC_WPSR_MASK _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
+
+/** \brief PCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */
+ __O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
+ __O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
+ __I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */
+ __I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */
+ __I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */
+ RoReg8 Reserved1[0xC8];
+ __IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
+ __I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */
+} Pcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PCC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/pdec.h b/GPIO/ATSAME54/include/component/pdec.h
new file mode 100644
index 0000000..996b941
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/pdec.h
@@ -0,0 +1,726 @@
+/**
+ * \file
+ *
+ * \brief Component description for PDEC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PDEC_COMPONENT_
+#define _SAME54_PDEC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PDEC */
+/* ========================================================================== */
+/** \addtogroup SAME54_PDEC Quadrature Decodeur */
+/*@{*/
+
+#define PDEC_U2263
+#define REV_PDEC 0x100
+
+/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:2; /*!< bit: 2.. 3 Operation Mode */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t CONF:3; /*!< bit: 8..10 PDEC Configuration */
+ uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
+ uint32_t :2; /*!< bit: 12..13 Reserved */
+ uint32_t SWAP:1; /*!< bit: 14 PDEC Phase A and B Swap */
+ uint32_t PEREN:1; /*!< bit: 15 Period Enable */
+ uint32_t PINEN0:1; /*!< bit: 16 PDEC Input From Pin 0 Enable */
+ uint32_t PINEN1:1; /*!< bit: 17 PDEC Input From Pin 1 Enable */
+ uint32_t PINEN2:1; /*!< bit: 18 PDEC Input From Pin 2 Enable */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t PINVEN0:1; /*!< bit: 20 IO Pin 0 Invert Enable */
+ uint32_t PINVEN1:1; /*!< bit: 21 IO Pin 1 Invert Enable */
+ uint32_t PINVEN2:1; /*!< bit: 22 IO Pin 2 Invert Enable */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t ANGULAR:3; /*!< bit: 24..26 Angular Counter Length */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t MAXCMP:4; /*!< bit: 28..31 Maximum Consecutive Missing Pulses */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t PINEN:3; /*!< bit: 16..18 PDEC Input From Pin x Enable */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t PINVEN:3; /*!< bit: 20..22 IO Pin x Invert Enable */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLA_OFFSET 0x00 /**< \brief (PDEC_CTRLA offset) Control A */
+#define PDEC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
+
+#define PDEC_CTRLA_SWRST_Pos 0 /**< \brief (PDEC_CTRLA) Software Reset */
+#define PDEC_CTRLA_SWRST (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
+#define PDEC_CTRLA_ENABLE_Pos 1 /**< \brief (PDEC_CTRLA) Enable */
+#define PDEC_CTRLA_ENABLE (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
+#define PDEC_CTRLA_MODE_Pos 2 /**< \brief (PDEC_CTRLA) Operation Mode */
+#define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
+#define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< \brief (PDEC_CTRLA) QDEC operating mode */
+#define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< \brief (PDEC_CTRLA) HALL operating mode */
+#define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< \brief (PDEC_CTRLA) COUNTER operating mode */
+#define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (PDEC_CTRLA) Run in Standby */
+#define PDEC_CTRLA_RUNSTDBY (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
+#define PDEC_CTRLA_CONF_Pos 8 /**< \brief (PDEC_CTRLA) PDEC Configuration */
+#define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
+#define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
+#define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
+#define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< \brief (PDEC_CTRLA) Decoder direction */
+#define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< \brief (PDEC_CTRLA) Secure decoder direction */
+#define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< \brief (PDEC_CTRLA) Auto correction mode */
+#define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_ALOCK_Pos 11 /**< \brief (PDEC_CTRLA) Auto Lock */
+#define PDEC_CTRLA_ALOCK (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
+#define PDEC_CTRLA_SWAP_Pos 14 /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
+#define PDEC_CTRLA_SWAP (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
+#define PDEC_CTRLA_PEREN_Pos 15 /**< \brief (PDEC_CTRLA) Period Enable */
+#define PDEC_CTRLA_PEREN (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
+#define PDEC_CTRLA_PINEN0_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
+#define PDEC_CTRLA_PINEN0 (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
+#define PDEC_CTRLA_PINEN1_Pos 17 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
+#define PDEC_CTRLA_PINEN1 (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
+#define PDEC_CTRLA_PINEN2_Pos 18 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
+#define PDEC_CTRLA_PINEN2 (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
+#define PDEC_CTRLA_PINEN_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
+#define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
+#define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
+#define PDEC_CTRLA_PINVEN0_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
+#define PDEC_CTRLA_PINVEN0 (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
+#define PDEC_CTRLA_PINVEN1_Pos 21 /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
+#define PDEC_CTRLA_PINVEN1 (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
+#define PDEC_CTRLA_PINVEN2_Pos 22 /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
+#define PDEC_CTRLA_PINVEN2 (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
+#define PDEC_CTRLA_PINVEN_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
+#define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
+#define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
+#define PDEC_CTRLA_ANGULAR_Pos 24 /**< \brief (PDEC_CTRLA) Angular Counter Length */
+#define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
+#define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
+#define PDEC_CTRLA_MAXCMP_Pos 28 /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
+#define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
+#define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
+#define PDEC_CTRLA_MASK _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
+
+/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t :3; /*!< bit: 2.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLBCLR_OFFSET 0x04 /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
+#define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
+
+#define PDEC_CTRLBCLR_LUPD_Pos 1 /**< \brief (PDEC_CTRLBCLR) Lock Update */
+#define PDEC_CTRLBCLR_LUPD (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
+#define PDEC_CTRLBCLR_CMD_Pos 5 /**< \brief (PDEC_CTRLBCLR) Command */
+#define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
+#define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBCLR) No action */
+#define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
+#define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
+#define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
+#define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
+#define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
+#define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBCLR) MASK Register */
+
+/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t :3; /*!< bit: 2.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLBSET_OFFSET 0x05 /**< \brief (PDEC_CTRLBSET offset) Control B Set */
+#define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
+
+#define PDEC_CTRLBSET_LUPD_Pos 1 /**< \brief (PDEC_CTRLBSET) Lock Update */
+#define PDEC_CTRLBSET_LUPD (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
+#define PDEC_CTRLBSET_CMD_Pos 5 /**< \brief (PDEC_CTRLBSET) Command */
+#define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
+#define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBSET) No action */
+#define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
+#define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
+#define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
+#define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
+#define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
+#define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBSET) MASK Register */
+
+/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */
+ uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */
+ uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */
+ uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */
+ uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */
+ uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} PDEC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_EVCTRL_OFFSET 0x06 /**< \brief (PDEC_EVCTRL offset) Event Control */
+#define PDEC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (PDEC_EVCTRL reset_value) Event Control */
+
+#define PDEC_EVCTRL_EVACT_Pos 0 /**< \brief (PDEC_EVCTRL) Event Action */
+#define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
+#define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (PDEC_EVCTRL) Event action disabled */
+#define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
+#define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (PDEC_EVCTRL) Count on event */
+#define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVINV_Pos 2 /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
+#define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
+#define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
+#define PDEC_EVCTRL_EVEI_Pos 5 /**< \brief (PDEC_EVCTRL) Event Input Enable */
+#define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
+#define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
+#define PDEC_EVCTRL_OVFEO_Pos 8 /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define PDEC_EVCTRL_OVFEO (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
+#define PDEC_EVCTRL_ERREO_Pos 9 /**< \brief (PDEC_EVCTRL) Error Output Event Enable */
+#define PDEC_EVCTRL_ERREO (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
+#define PDEC_EVCTRL_DIREO_Pos 10 /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
+#define PDEC_EVCTRL_DIREO (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
+#define PDEC_EVCTRL_VLCEO_Pos 11 /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
+#define PDEC_EVCTRL_VLCEO (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
+#define PDEC_EVCTRL_MCEO0_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
+#define PDEC_EVCTRL_MCEO0 (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
+#define PDEC_EVCTRL_MCEO1_Pos 13 /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
+#define PDEC_EVCTRL_MCEO1 (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
+#define PDEC_EVCTRL_MCEO_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
+#define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
+#define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
+#define PDEC_EVCTRL_MASK _U_(0x3FFF) /**< \brief (PDEC_EVCTRL) MASK Register */
+
+/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Disable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Disable */
+ uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Disable */
+ uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Disable */
+ uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Disable */
+ uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTENCLR_OFFSET 0x08 /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
+#define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PDEC_INTENCLR_OVF_Pos 0 /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
+#define PDEC_INTENCLR_OVF (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
+#define PDEC_INTENCLR_ERR_Pos 1 /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
+#define PDEC_INTENCLR_ERR (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
+#define PDEC_INTENCLR_DIR_Pos 2 /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
+#define PDEC_INTENCLR_DIR (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
+#define PDEC_INTENCLR_VLC_Pos 3 /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
+#define PDEC_INTENCLR_VLC (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
+#define PDEC_INTENCLR_MC0_Pos 4 /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
+#define PDEC_INTENCLR_MC0 (_U_(1) << PDEC_INTENCLR_MC0_Pos)
+#define PDEC_INTENCLR_MC1_Pos 5 /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
+#define PDEC_INTENCLR_MC1 (_U_(1) << PDEC_INTENCLR_MC1_Pos)
+#define PDEC_INTENCLR_MC_Pos 4 /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
+#define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
+#define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
+#define PDEC_INTENCLR_MASK _U_(0x3F) /**< \brief (PDEC_INTENCLR) MASK Register */
+
+/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Enable */
+ uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Enable */
+ uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTENSET_OFFSET 0x09 /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
+#define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
+
+#define PDEC_INTENSET_OVF_Pos 0 /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
+#define PDEC_INTENSET_OVF (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
+#define PDEC_INTENSET_ERR_Pos 1 /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
+#define PDEC_INTENSET_ERR (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
+#define PDEC_INTENSET_DIR_Pos 2 /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
+#define PDEC_INTENSET_DIR (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
+#define PDEC_INTENSET_VLC_Pos 3 /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
+#define PDEC_INTENSET_VLC (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
+#define PDEC_INTENSET_MC0_Pos 4 /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
+#define PDEC_INTENSET_MC0 (_U_(1) << PDEC_INTENSET_MC0_Pos)
+#define PDEC_INTENSET_MC1_Pos 5 /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
+#define PDEC_INTENSET_MC1 (_U_(1) << PDEC_INTENSET_MC1_Pos)
+#define PDEC_INTENSET_MC_Pos 4 /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
+#define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos)
+#define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
+#define PDEC_INTENSET_MASK _U_(0x3F) /**< \brief (PDEC_INTENSET) MASK Register */
+
+/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */
+ __I uint8_t ERR:1; /*!< bit: 1 Error */
+ __I uint8_t DIR:1; /*!< bit: 2 Direction Change */
+ __I uint8_t VLC:1; /*!< bit: 3 Velocity */
+ __I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */
+ __I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTFLAG_OFFSET 0x0A /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PDEC_INTFLAG_OVF_Pos 0 /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
+#define PDEC_INTFLAG_OVF (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
+#define PDEC_INTFLAG_ERR_Pos 1 /**< \brief (PDEC_INTFLAG) Error */
+#define PDEC_INTFLAG_ERR (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
+#define PDEC_INTFLAG_DIR_Pos 2 /**< \brief (PDEC_INTFLAG) Direction Change */
+#define PDEC_INTFLAG_DIR (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
+#define PDEC_INTFLAG_VLC_Pos 3 /**< \brief (PDEC_INTFLAG) Velocity */
+#define PDEC_INTFLAG_VLC (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
+#define PDEC_INTFLAG_MC0_Pos 4 /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
+#define PDEC_INTFLAG_MC0 (_U_(1) << PDEC_INTFLAG_MC0_Pos)
+#define PDEC_INTFLAG_MC1_Pos 5 /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
+#define PDEC_INTFLAG_MC1 (_U_(1) << PDEC_INTFLAG_MC1_Pos)
+#define PDEC_INTFLAG_MC_Pos 4 /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
+#define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
+#define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
+#define PDEC_INTFLAG_MASK _U_(0x3F) /**< \brief (PDEC_INTFLAG) MASK Register */
+
+/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t QERR:1; /*!< bit: 0 Quadrature Error Flag */
+ uint16_t IDXERR:1; /*!< bit: 1 Index Error Flag */
+ uint16_t MPERR:1; /*!< bit: 2 Missing Pulse Error flag */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t WINERR:1; /*!< bit: 4 Window Error Flag */
+ uint16_t HERR:1; /*!< bit: 5 Hall Error Flag */
+ uint16_t STOP:1; /*!< bit: 6 Stop */
+ uint16_t DIR:1; /*!< bit: 7 Direction Status Flag */
+ uint16_t PRESCBUFV:1; /*!< bit: 8 Prescaler Buffer Valid */
+ uint16_t FILTERBUFV:1; /*!< bit: 9 Filter Buffer Valid */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t CCBUFV0:1; /*!< bit: 12 Compare Channel 0 Buffer Valid */
+ uint16_t CCBUFV1:1; /*!< bit: 13 Compare Channel 1 Buffer Valid */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t CCBUFV:2; /*!< bit: 12..13 Compare Channel x Buffer Valid */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} PDEC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_STATUS_OFFSET 0x0C /**< \brief (PDEC_STATUS offset) Status */
+#define PDEC_STATUS_RESETVALUE _U_(0x0040) /**< \brief (PDEC_STATUS reset_value) Status */
+
+#define PDEC_STATUS_QERR_Pos 0 /**< \brief (PDEC_STATUS) Quadrature Error Flag */
+#define PDEC_STATUS_QERR (_U_(0x1) << PDEC_STATUS_QERR_Pos)
+#define PDEC_STATUS_IDXERR_Pos 1 /**< \brief (PDEC_STATUS) Index Error Flag */
+#define PDEC_STATUS_IDXERR (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
+#define PDEC_STATUS_MPERR_Pos 2 /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
+#define PDEC_STATUS_MPERR (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
+#define PDEC_STATUS_WINERR_Pos 4 /**< \brief (PDEC_STATUS) Window Error Flag */
+#define PDEC_STATUS_WINERR (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
+#define PDEC_STATUS_HERR_Pos 5 /**< \brief (PDEC_STATUS) Hall Error Flag */
+#define PDEC_STATUS_HERR (_U_(0x1) << PDEC_STATUS_HERR_Pos)
+#define PDEC_STATUS_STOP_Pos 6 /**< \brief (PDEC_STATUS) Stop */
+#define PDEC_STATUS_STOP (_U_(0x1) << PDEC_STATUS_STOP_Pos)
+#define PDEC_STATUS_DIR_Pos 7 /**< \brief (PDEC_STATUS) Direction Status Flag */
+#define PDEC_STATUS_DIR (_U_(0x1) << PDEC_STATUS_DIR_Pos)
+#define PDEC_STATUS_PRESCBUFV_Pos 8 /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
+#define PDEC_STATUS_PRESCBUFV (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
+#define PDEC_STATUS_FILTERBUFV_Pos 9 /**< \brief (PDEC_STATUS) Filter Buffer Valid */
+#define PDEC_STATUS_FILTERBUFV (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
+#define PDEC_STATUS_CCBUFV0_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
+#define PDEC_STATUS_CCBUFV0 (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
+#define PDEC_STATUS_CCBUFV1_Pos 13 /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
+#define PDEC_STATUS_CCBUFV1 (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
+#define PDEC_STATUS_CCBUFV_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
+#define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
+#define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
+#define PDEC_STATUS_MASK _U_(0x33F7) /**< \brief (PDEC_STATUS) MASK Register */
+
+/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_DBGCTRL_OFFSET 0x0F /**< \brief (PDEC_DBGCTRL offset) Debug Control */
+#define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
+
+#define PDEC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
+#define PDEC_DBGCTRL_DBGRUN (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
+#define PDEC_DBGCTRL_MASK _U_(0x01) /**< \brief (PDEC_DBGCTRL) MASK Register */
+
+/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/ 32) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Control B Synchronization Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */
+ uint32_t PRESC:1; /*!< bit: 4 Prescaler Synchronization Busy */
+ uint32_t FILTER:1; /*!< bit: 5 Filter Synchronization Busy */
+ uint32_t COUNT:1; /*!< bit: 6 Count Synchronization Busy */
+ uint32_t CC0:1; /*!< bit: 7 Compare Channel 0 Synchronization Busy */
+ uint32_t CC1:1; /*!< bit: 8 Compare Channel 1 Synchronization Busy */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :7; /*!< bit: 0.. 6 Reserved */
+ uint32_t CC:2; /*!< bit: 7.. 8 Compare Channel x Synchronization Busy */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_SYNCBUSY_OFFSET 0x10 /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
+#define PDEC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
+
+#define PDEC_SYNCBUSY_SWRST_Pos 0 /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
+#define PDEC_SYNCBUSY_SWRST (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
+#define PDEC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
+#define PDEC_SYNCBUSY_ENABLE (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
+#define PDEC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
+#define PDEC_SYNCBUSY_CTRLB (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
+#define PDEC_SYNCBUSY_STATUS_Pos 3 /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
+#define PDEC_SYNCBUSY_STATUS (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
+#define PDEC_SYNCBUSY_PRESC_Pos 4 /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
+#define PDEC_SYNCBUSY_PRESC (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
+#define PDEC_SYNCBUSY_FILTER_Pos 5 /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
+#define PDEC_SYNCBUSY_FILTER (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
+#define PDEC_SYNCBUSY_COUNT_Pos 6 /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
+#define PDEC_SYNCBUSY_COUNT (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
+#define PDEC_SYNCBUSY_CC0_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
+#define PDEC_SYNCBUSY_CC0 (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
+#define PDEC_SYNCBUSY_CC1_Pos 8 /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
+#define PDEC_SYNCBUSY_CC1 (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
+#define PDEC_SYNCBUSY_CC_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
+#define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
+#define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
+#define PDEC_SYNCBUSY_MASK _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
+
+/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRESC:4; /*!< bit: 0.. 3 Prescaler Value */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_PRESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_PRESC_OFFSET 0x14 /**< \brief (PDEC_PRESC offset) Prescaler Value */
+#define PDEC_PRESC_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
+
+#define PDEC_PRESC_PRESC_Pos 0 /**< \brief (PDEC_PRESC) Prescaler Value */
+#define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
+#define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESC) No division */
+#define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESC) Divide by 2 */
+#define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESC) Divide by 4 */
+#define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESC) Divide by 8 */
+#define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESC) Divide by 16 */
+#define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESC) Divide by 32 */
+#define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESC) Divide by 64 */
+#define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESC) Divide by 128 */
+#define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESC) Divide by 256 */
+#define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESC) Divide by 512 */
+#define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESC) Divide by 1024 */
+#define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_MASK _U_(0x0F) /**< \brief (PDEC_PRESC) MASK Register */
+
+/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FILTER:8; /*!< bit: 0.. 7 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_FILTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_FILTER_OFFSET 0x15 /**< \brief (PDEC_FILTER offset) Filter Value */
+#define PDEC_FILTER_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTER reset_value) Filter Value */
+
+#define PDEC_FILTER_FILTER_Pos 0 /**< \brief (PDEC_FILTER) Filter Value */
+#define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
+#define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
+#define PDEC_FILTER_MASK _U_(0xFF) /**< \brief (PDEC_FILTER) MASK Register */
+
+/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PRESCBUF:4; /*!< bit: 0.. 3 Prescaler Buffer Value */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_PRESCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_PRESCBUF_OFFSET 0x18 /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
+#define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
+
+#define PDEC_PRESCBUF_PRESCBUF_Pos 0 /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
+#define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
+#define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESCBUF) No division */
+#define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESCBUF) Divide by 2 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESCBUF) Divide by 4 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESCBUF) Divide by 8 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESCBUF) Divide by 16 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESCBUF) Divide by 32 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESCBUF) Divide by 64 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESCBUF) Divide by 128 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESCBUF) Divide by 256 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESCBUF) Divide by 512 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_MASK _U_(0x0F) /**< \brief (PDEC_PRESCBUF) MASK Register */
+
+/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FILTERBUF:8; /*!< bit: 0.. 7 Filter Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PDEC_FILTERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_FILTERBUF_OFFSET 0x19 /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
+#define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
+
+#define PDEC_FILTERBUF_FILTERBUF_Pos 0 /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
+#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
+#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
+#define PDEC_FILTERBUF_MASK _U_(0xFF) /**< \brief (PDEC_FILTERBUF) MASK Register */
+
+/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_COUNT_OFFSET 0x1C /**< \brief (PDEC_COUNT offset) Counter Value */
+#define PDEC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
+
+#define PDEC_COUNT_COUNT_Pos 0 /**< \brief (PDEC_COUNT) Counter Value */
+#define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
+#define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
+#define PDEC_COUNT_MASK _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
+
+/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:16; /*!< bit: 0..15 Channel Compare Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CC_OFFSET 0x20 /**< \brief (PDEC_CC offset) Channel n Compare Value */
+#define PDEC_CC_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
+
+#define PDEC_CC_CC_Pos 0 /**< \brief (PDEC_CC) Channel Compare Value */
+#define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos)
+#define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
+#define PDEC_CC_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
+
+/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCBUF:16; /*!< bit: 0..15 Channel Compare Buffer Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PDEC_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CCBUF_OFFSET 0x30 /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
+#define PDEC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
+
+#define PDEC_CCBUF_CCBUF_Pos 0 /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
+#define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
+#define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
+#define PDEC_CCBUF_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
+
+/** \brief PDEC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */
+ RoReg8 Reserved2[0x1];
+ __IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I PDEC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */
+ __IO PDEC_FILTER_Type FILTER; /**< \brief Offset: 0x15 (R/W 8) Filter Value */
+ RoReg8 Reserved3[0x2];
+ __IO PDEC_PRESCBUF_Type PRESCBUF; /**< \brief Offset: 0x18 (R/W 8) Prescaler Buffer Value */
+ __IO PDEC_FILTERBUF_Type FILTERBUF; /**< \brief Offset: 0x19 (R/W 8) Filter Buffer Value */
+ RoReg8 Reserved4[0x2];
+ __IO PDEC_COUNT_Type COUNT; /**< \brief Offset: 0x1C (R/W 32) Counter Value */
+ __IO PDEC_CC_Type CC[2]; /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
+ RoReg8 Reserved5[0x8];
+ __IO PDEC_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
+} Pdec;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PDEC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/picop.h b/GPIO/ATSAME54/include/component/picop.h
new file mode 100644
index 0000000..77a656e
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/picop.h
@@ -0,0 +1,1321 @@
+/**
+ * \file
+ *
+ * \brief Component description for PICOP
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PICOP_COMPONENT_
+#define _SAME54_PICOP_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PICOP */
+/* ========================================================================== */
+/** \addtogroup SAME54_PICOP PicoProcessor */
+/*@{*/
+
+#define PICOP_U2232
+#define REV_PICOP 0x200
+
+/* -------- PICOP_ID : (PICOP Offset: 0x000) (R/W 32) ID n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:32; /*!< bit: 0..31 ID String 0 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_ID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_ID_OFFSET 0x000 /**< \brief (PICOP_ID offset) ID n */
+#define PICOP_ID_RESETVALUE 0x00000000ul /**< \brief (PICOP_ID reset_value) ID n */
+
+#define PICOP_ID_ID_Pos 0 /**< \brief (PICOP_ID) ID String 0 */
+#define PICOP_ID_ID_Msk (0xFFFFFFFFul << PICOP_ID_ID_Pos)
+#define PICOP_ID_ID(value) (PICOP_ID_ID_Msk & ((value) << PICOP_ID_ID_Pos))
+#define PICOP_ID_MASK 0xFFFFFFFFul /**< \brief (PICOP_ID) MASK Register */
+
+/* -------- PICOP_CONFIG : (PICOP Offset: 0x020) (R/W 32) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ISA:2; /*!< bit: 0.. 1 Instruction Set Architecture */
+ uint32_t ASP:1; /*!< bit: 2 Aligned Stack Pointer */
+ uint32_t MARRET:1; /*!< bit: 3 Misaligned implicit long return register (GCC compatibility) */
+ uint32_t RRET:4; /*!< bit: 4.. 7 Implicit return word register */
+ uint32_t PCEXEN:1; /*!< bit: 8 PC_EX register enabled for reduced interrupt latency */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_CONFIG_OFFSET 0x020 /**< \brief (PICOP_CONFIG offset) Configuration */
+#define PICOP_CONFIG_RESETVALUE 0x00000000ul /**< \brief (PICOP_CONFIG reset_value) Configuration */
+
+#define PICOP_CONFIG_ISA_Pos 0 /**< \brief (PICOP_CONFIG) Instruction Set Architecture */
+#define PICOP_CONFIG_ISA_Msk (0x3ul << PICOP_CONFIG_ISA_Pos)
+#define PICOP_CONFIG_ISA(value) (PICOP_CONFIG_ISA_Msk & ((value) << PICOP_CONFIG_ISA_Pos))
+#define PICOP_CONFIG_ISA_AVR8_Val 0x0ul /**< \brief (PICOP_CONFIG) AVR8 ISA, AVR8SP=1 */
+#define PICOP_CONFIG_ISA_AVR16C_Val 0x1ul /**< \brief (PICOP_CONFIG) AVR16 ISA fully compatible with AVR8 ISA, AVR8SP=1 */
+#define PICOP_CONFIG_ISA_AVR16E_Val 0x2ul /**< \brief (PICOP_CONFIG) AVR16 ISA extended, AVR8SP=1 */
+#define PICOP_CONFIG_ISA_AVR16_Val 0x3ul /**< \brief (PICOP_CONFIG) AVR16 ISA extended, AVR8SP=0 */
+#define PICOP_CONFIG_ISA_AVR8 (PICOP_CONFIG_ISA_AVR8_Val << PICOP_CONFIG_ISA_Pos)
+#define PICOP_CONFIG_ISA_AVR16C (PICOP_CONFIG_ISA_AVR16C_Val << PICOP_CONFIG_ISA_Pos)
+#define PICOP_CONFIG_ISA_AVR16E (PICOP_CONFIG_ISA_AVR16E_Val << PICOP_CONFIG_ISA_Pos)
+#define PICOP_CONFIG_ISA_AVR16 (PICOP_CONFIG_ISA_AVR16_Val << PICOP_CONFIG_ISA_Pos)
+#define PICOP_CONFIG_ASP_Pos 2 /**< \brief (PICOP_CONFIG) Aligned Stack Pointer */
+#define PICOP_CONFIG_ASP (0x1ul << PICOP_CONFIG_ASP_Pos)
+#define PICOP_CONFIG_MARRET_Pos 3 /**< \brief (PICOP_CONFIG) Misaligned implicit long return register (GCC compatibility) */
+#define PICOP_CONFIG_MARRET (0x1ul << PICOP_CONFIG_MARRET_Pos)
+#define PICOP_CONFIG_RRET_Pos 4 /**< \brief (PICOP_CONFIG) Implicit return word register */
+#define PICOP_CONFIG_RRET_Msk (0xFul << PICOP_CONFIG_RRET_Pos)
+#define PICOP_CONFIG_RRET(value) (PICOP_CONFIG_RRET_Msk & ((value) << PICOP_CONFIG_RRET_Pos))
+#define PICOP_CONFIG_PCEXEN_Pos 8 /**< \brief (PICOP_CONFIG) PC_EX register enabled for reduced interrupt latency */
+#define PICOP_CONFIG_PCEXEN (0x1ul << PICOP_CONFIG_PCEXEN_Pos)
+#define PICOP_CONFIG_MASK 0x000001FFul /**< \brief (PICOP_CONFIG) MASK Register */
+
+/* -------- PICOP_CTRL : (PICOP Offset: 0x024) (R/W 32) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MAPUEXCEPT:1; /*!< bit: 0 Enable exception for illegal access */
+ uint32_t WPICACHE:1; /*!< bit: 1 Write protect iCache */
+ uint32_t WPVEC:2; /*!< bit: 2.. 3 Write protect vectors */
+ uint32_t WPCTX:2; /*!< bit: 4.. 5 Write protect contexts */
+ uint32_t WPCODE:4; /*!< bit: 6.. 9 Write protect code */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_CTRL_OFFSET 0x024 /**< \brief (PICOP_CTRL offset) Control */
+#define PICOP_CTRL_RESETVALUE 0x00000000ul /**< \brief (PICOP_CTRL reset_value) Control */
+
+#define PICOP_CTRL_MAPUEXCEPT_Pos 0 /**< \brief (PICOP_CTRL) Enable exception for illegal access */
+#define PICOP_CTRL_MAPUEXCEPT (0x1ul << PICOP_CTRL_MAPUEXCEPT_Pos)
+#define PICOP_CTRL_WPICACHE_Pos 1 /**< \brief (PICOP_CTRL) Write protect iCache */
+#define PICOP_CTRL_WPICACHE (0x1ul << PICOP_CTRL_WPICACHE_Pos)
+#define PICOP_CTRL_WPVEC_Pos 2 /**< \brief (PICOP_CTRL) Write protect vectors */
+#define PICOP_CTRL_WPVEC_Msk (0x3ul << PICOP_CTRL_WPVEC_Pos)
+#define PICOP_CTRL_WPVEC(value) (PICOP_CTRL_WPVEC_Msk & ((value) << PICOP_CTRL_WPVEC_Pos))
+#define PICOP_CTRL_WPVEC_NONE_Val 0x0ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPVEC_RSTNMI_Val 0x1ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPVEC_NONE (PICOP_CTRL_WPVEC_NONE_Val << PICOP_CTRL_WPVEC_Pos)
+#define PICOP_CTRL_WPVEC_RSTNMI (PICOP_CTRL_WPVEC_RSTNMI_Val << PICOP_CTRL_WPVEC_Pos)
+#define PICOP_CTRL_WPCTX_Pos 4 /**< \brief (PICOP_CTRL) Write protect contexts */
+#define PICOP_CTRL_WPCTX_Msk (0x3ul << PICOP_CTRL_WPCTX_Pos)
+#define PICOP_CTRL_WPCTX(value) (PICOP_CTRL_WPCTX_Msk & ((value) << PICOP_CTRL_WPCTX_Pos))
+#define PICOP_CTRL_WPCTX_NONE_Val 0x0ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCTX_CTX0_Val 0x1ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCTX_CTX01_Val 0x2ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCTX_CTX012_Val 0x3ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCTX_NONE (PICOP_CTRL_WPCTX_NONE_Val << PICOP_CTRL_WPCTX_Pos)
+#define PICOP_CTRL_WPCTX_CTX0 (PICOP_CTRL_WPCTX_CTX0_Val << PICOP_CTRL_WPCTX_Pos)
+#define PICOP_CTRL_WPCTX_CTX01 (PICOP_CTRL_WPCTX_CTX01_Val << PICOP_CTRL_WPCTX_Pos)
+#define PICOP_CTRL_WPCTX_CTX012 (PICOP_CTRL_WPCTX_CTX012_Val << PICOP_CTRL_WPCTX_Pos)
+#define PICOP_CTRL_WPCODE_Pos 6 /**< \brief (PICOP_CTRL) Write protect code */
+#define PICOP_CTRL_WPCODE_Msk (0xFul << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE(value) (PICOP_CTRL_WPCODE_Msk & ((value) << PICOP_CTRL_WPCODE_Pos))
+#define PICOP_CTRL_WPCODE_NONE_Val 0x0ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_256B_Val 0x1ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_512B_Val 0x2ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_768B_Val 0x3ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_1024B_Val 0x4ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_1280B_Val 0x5ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_1536B_Val 0x6ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_1792B_Val 0x7ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_2048B_Val 0x8ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_2304B_Val 0x9ul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_2560B_Val 0xAul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_2816B_Val 0xBul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_3072B_Val 0xCul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_3328B_Val 0xDul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_3584B_Val 0xEul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_3840B_Val 0xFul /**< \brief (PICOP_CTRL) */
+#define PICOP_CTRL_WPCODE_NONE (PICOP_CTRL_WPCODE_NONE_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_256B (PICOP_CTRL_WPCODE_256B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_512B (PICOP_CTRL_WPCODE_512B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_768B (PICOP_CTRL_WPCODE_768B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_1024B (PICOP_CTRL_WPCODE_1024B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_1280B (PICOP_CTRL_WPCODE_1280B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_1536B (PICOP_CTRL_WPCODE_1536B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_1792B (PICOP_CTRL_WPCODE_1792B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_2048B (PICOP_CTRL_WPCODE_2048B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_2304B (PICOP_CTRL_WPCODE_2304B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_2560B (PICOP_CTRL_WPCODE_2560B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_2816B (PICOP_CTRL_WPCODE_2816B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_3072B (PICOP_CTRL_WPCODE_3072B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_3328B (PICOP_CTRL_WPCODE_3328B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_3584B (PICOP_CTRL_WPCODE_3584B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_WPCODE_3840B (PICOP_CTRL_WPCODE_3840B_Val << PICOP_CTRL_WPCODE_Pos)
+#define PICOP_CTRL_MASK 0x000003FFul /**< \brief (PICOP_CTRL) MASK Register */
+
+/* -------- PICOP_CMD : (PICOP Offset: 0x028) (R/W 32) Command -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // CMD mode
+ uint32_t CMD:4; /*!< bit: 0.. 3 Command */
+ uint32_t :12; /*!< bit: 4..15 Reserved */
+ uint32_t UNLOCK:16; /*!< bit: 16..31 Unlock */
+ } CMD; /*!< Structure used for CMD */
+ struct { // STATUS mode
+ uint32_t CTTSEX:1; /*!< bit: 0 Context Task Switch */
+ uint32_t IL0EX:1; /*!< bit: 1 Interrupt Level 0 Exception */
+ uint32_t IL1EX:1; /*!< bit: 2 Interrupt Level 1 Exception */
+ uint32_t IL2EX:1; /*!< bit: 3 Interrupt Level 2 Exception */
+ uint32_t IL3EX:1; /*!< bit: 4 Interrupt Level 3 Exception */
+ uint32_t IL4EX:1; /*!< bit: 5 Interrupt Level 4 Exception */
+ uint32_t NMIEX:1; /*!< bit: 6 NMI Exception */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t EXCEPT:1; /*!< bit: 8 Exception */
+ uint32_t AVR16:1; /*!< bit: 9 AVR16 Mode */
+ uint32_t OCDCOF:1; /*!< bit: 10 OCD Change of Flow */
+ uint32_t :5; /*!< bit: 11..15 Reserved */
+ uint32_t UPC:8; /*!< bit: 16..23 Microcode State */
+ uint32_t :3; /*!< bit: 24..26 Reserved */
+ uint32_t STATE:5; /*!< bit: 27..31 System State */
+ } STATUS; /*!< Structure used for STATUS */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_CMD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_CMD_OFFSET 0x028 /**< \brief (PICOP_CMD offset) Command */
+#define PICOP_CMD_RESETVALUE 0x00000000ul /**< \brief (PICOP_CMD reset_value) Command */
+
+// CMD mode
+#define PICOP_CMD_CMD_CMD_Pos 0 /**< \brief (PICOP_CMD_CMD) Command */
+#define PICOP_CMD_CMD_CMD_Msk (0xFul << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD(value) (PICOP_CMD_CMD_CMD_Msk & ((value) << PICOP_CMD_CMD_CMD_Pos))
+#define PICOP_CMD_CMD_CMD_NOACTION_Val 0x0ul /**< \brief (PICOP_CMD_CMD) No action */
+#define PICOP_CMD_CMD_CMD_STOP_Val 0x1ul /**< \brief (PICOP_CMD_CMD) Wait for ongoing execution to complete, then stop */
+#define PICOP_CMD_CMD_CMD_RESET_Val 0x2ul /**< \brief (PICOP_CMD_CMD) Stop, reset and stop */
+#define PICOP_CMD_CMD_CMD_RESTART_Val 0x3ul /**< \brief (PICOP_CMD_CMD) Stop, reset and run */
+#define PICOP_CMD_CMD_CMD_ABORT_Val 0x4ul /**< \brief (PICOP_CMD_CMD) Abort, reset and stop */
+#define PICOP_CMD_CMD_CMD_RUN_Val 0x5ul /**< \brief (PICOP_CMD_CMD) Start execution (from unlocked stopped state) */
+#define PICOP_CMD_CMD_CMD_RUNLOCK_Val 0x6ul /**< \brief (PICOP_CMD_CMD) Start execution and lock */
+#define PICOP_CMD_CMD_CMD_RUNOCD_Val 0x7ul /**< \brief (PICOP_CMD_CMD) Start execution and enable host-controlled OCD */
+#define PICOP_CMD_CMD_CMD_UNLOCK_Val 0x8ul /**< \brief (PICOP_CMD_CMD) Unlock and run */
+#define PICOP_CMD_CMD_CMD_NMI_Val 0x9ul /**< \brief (PICOP_CMD_CMD) Trigger a NMI */
+#define PICOP_CMD_CMD_CMD_WAKEUP_Val 0xAul /**< \brief (PICOP_CMD_CMD) Force a wakeup from sleep (if in sleep) */
+#define PICOP_CMD_CMD_CMD_NOACTION (PICOP_CMD_CMD_CMD_NOACTION_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_STOP (PICOP_CMD_CMD_CMD_STOP_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_RESET (PICOP_CMD_CMD_CMD_RESET_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_RESTART (PICOP_CMD_CMD_CMD_RESTART_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_ABORT (PICOP_CMD_CMD_CMD_ABORT_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_RUN (PICOP_CMD_CMD_CMD_RUN_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_RUNLOCK (PICOP_CMD_CMD_CMD_RUNLOCK_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_RUNOCD (PICOP_CMD_CMD_CMD_RUNOCD_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_UNLOCK (PICOP_CMD_CMD_CMD_UNLOCK_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_NMI (PICOP_CMD_CMD_CMD_NMI_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_CMD_WAKEUP (PICOP_CMD_CMD_CMD_WAKEUP_Val << PICOP_CMD_CMD_CMD_Pos)
+#define PICOP_CMD_CMD_UNLOCK_Pos 16 /**< \brief (PICOP_CMD_CMD) Unlock */
+#define PICOP_CMD_CMD_UNLOCK_Msk (0xFFFFul << PICOP_CMD_CMD_UNLOCK_Pos)
+#define PICOP_CMD_CMD_UNLOCK(value) (PICOP_CMD_CMD_UNLOCK_Msk & ((value) << PICOP_CMD_CMD_UNLOCK_Pos))
+#define PICOP_CMD_CMD_MASK 0xFFFF000Ful /**< \brief (PICOP_CMD_CMD) MASK Register */
+
+// STATUS mode
+#define PICOP_CMD_STATUS_CTTSEX_Pos 0 /**< \brief (PICOP_CMD_STATUS) Context Task Switch */
+#define PICOP_CMD_STATUS_CTTSEX (0x1ul << PICOP_CMD_STATUS_CTTSEX_Pos)
+#define PICOP_CMD_STATUS_IL0EX_Pos 1 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 0 Exception */
+#define PICOP_CMD_STATUS_IL0EX (0x1ul << PICOP_CMD_STATUS_IL0EX_Pos)
+#define PICOP_CMD_STATUS_IL1EX_Pos 2 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 1 Exception */
+#define PICOP_CMD_STATUS_IL1EX (0x1ul << PICOP_CMD_STATUS_IL1EX_Pos)
+#define PICOP_CMD_STATUS_IL2EX_Pos 3 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 2 Exception */
+#define PICOP_CMD_STATUS_IL2EX (0x1ul << PICOP_CMD_STATUS_IL2EX_Pos)
+#define PICOP_CMD_STATUS_IL3EX_Pos 4 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 3 Exception */
+#define PICOP_CMD_STATUS_IL3EX (0x1ul << PICOP_CMD_STATUS_IL3EX_Pos)
+#define PICOP_CMD_STATUS_IL4EX_Pos 5 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 4 Exception */
+#define PICOP_CMD_STATUS_IL4EX (0x1ul << PICOP_CMD_STATUS_IL4EX_Pos)
+#define PICOP_CMD_STATUS_NMIEX_Pos 6 /**< \brief (PICOP_CMD_STATUS) NMI Exception */
+#define PICOP_CMD_STATUS_NMIEX (0x1ul << PICOP_CMD_STATUS_NMIEX_Pos)
+#define PICOP_CMD_STATUS_EXCEPT_Pos 8 /**< \brief (PICOP_CMD_STATUS) Exception */
+#define PICOP_CMD_STATUS_EXCEPT (0x1ul << PICOP_CMD_STATUS_EXCEPT_Pos)
+#define PICOP_CMD_STATUS_AVR16_Pos 9 /**< \brief (PICOP_CMD_STATUS) AVR16 Mode */
+#define PICOP_CMD_STATUS_AVR16 (0x1ul << PICOP_CMD_STATUS_AVR16_Pos)
+#define PICOP_CMD_STATUS_OCDCOF_Pos 10 /**< \brief (PICOP_CMD_STATUS) OCD Change of Flow */
+#define PICOP_CMD_STATUS_OCDCOF (0x1ul << PICOP_CMD_STATUS_OCDCOF_Pos)
+#define PICOP_CMD_STATUS_UPC_Pos 16 /**< \brief (PICOP_CMD_STATUS) Microcode State */
+#define PICOP_CMD_STATUS_UPC_Msk (0xFFul << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC(value) (PICOP_CMD_STATUS_UPC_Msk & ((value) << PICOP_CMD_STATUS_UPC_Pos))
+#define PICOP_CMD_STATUS_UPC_EXEC_Val 0x0ul /**< \brief (PICOP_CMD_STATUS) Normal execution (no ucode) */
+#define PICOP_CMD_STATUS_UPC_EXEC_NOBRK_Val 0x1ul /**< \brief (PICOP_CMD_STATUS) Normal execution with break disabled */
+#define PICOP_CMD_STATUS_UPC_EXEC_NOP_Val 0x2ul /**< \brief (PICOP_CMD_STATUS) OCD NOP override execution (break disabled) */
+#define PICOP_CMD_STATUS_UPC_EXEC_IMM_Val 0x3ul /**< \brief (PICOP_CMD_STATUS) OCD IMM override execution (break disabled) */
+#define PICOP_CMD_STATUS_UPC_ICACHE_FLUSH_Val 0x4ul /**< \brief (PICOP_CMD_STATUS) Flush instruction cache */
+#define PICOP_CMD_STATUS_UPC_HALT_Val 0x10ul /**< \brief (PICOP_CMD_STATUS) HALT execution (shutdown) */
+#define PICOP_CMD_STATUS_UPC_HALTED_Val 0x11ul /**< \brief (PICOP_CMD_STATUS) Execution halted (shutdown) */
+#define PICOP_CMD_STATUS_UPC_SLEEP_Val 0x17ul /**< \brief (PICOP_CMD_STATUS) Wait until safe to go to sleeping state */
+#define PICOP_CMD_STATUS_UPC_SLEEPING_Val 0x18ul /**< \brief (PICOP_CMD_STATUS) Sleeping / reset cycle 0 */
+#define PICOP_CMD_STATUS_UPC_WAKEUP_RST1_Val 0x19ul /**< \brief (PICOP_CMD_STATUS) Reset cycle 1 */
+#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP_Val 0x1Aul /**< \brief (PICOP_CMD_STATUS) SLEEP: Context Restore CCR..SP */
+#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY_Val 0x1Bul /**< \brief (PICOP_CMD_STATUS) SLEEP: Context Restore Z..Y */
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_Val 0x20ul /**< \brief (PICOP_CMD_STATUS) OCD state: No break (sr.upc[1:0] == 2'b00) */
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_NOP_Val 0x21ul /**< \brief (PICOP_CMD_STATUS) OCD state: NOP override (sr.upc[1:0] == 2'b01) */
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_IMM_Val 0x22ul /**< \brief (PICOP_CMD_STATUS) OCD state: IMM override (sr.upc[1:0] == 2'b10) */
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP_Val 0x23ul /**< \brief (PICOP_CMD_STATUS) OCD state: SLEEP instruction (sr.upc[1:0] == 2'b11) */
+#define PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT_Val 0x28ul /**< \brief (PICOP_CMD_STATUS) Breakpoint (sr.upc[0] == 1'b0) */
+#define PICOP_CMD_STATUS_UPC_OCD_BREAKI_Val 0x29ul /**< \brief (PICOP_CMD_STATUS) Breakpoint instruction (sr.upc[0] == 1'b1) */
+#define PICOP_CMD_STATUS_UPC_CANCEL_EX_Val 0x2Eul /**< \brief (PICOP_CMD_STATUS) Cancel exception */
+#define PICOP_CMD_STATUS_UPC_IRQ_Val 0x2Ful /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save CCR..SP */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_0_Val 0x30ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+0+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_1_Val 0x31ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+1+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_2_Val 0x32ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+2+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_3_Val 0x33ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+3+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_4_Val 0x34ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+4+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_5_Val 0x35ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+5+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_6_Val 0x36ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+6+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_7_Val 0x37ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+7+1}.l */
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_PC_Val 0x38ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save (SR):PC */
+#define PICOP_CMD_STATUS_UPC_IRQ_ACK_Val 0x39ul /**< \brief (PICOP_CMD_STATUS) IRQ: Acknowledge cycle */
+#define PICOP_CMD_STATUS_UPC_EXCEPT_Val 0x3Aul /**< \brief (PICOP_CMD_STATUS) Internal exceptions */
+#define PICOP_CMD_STATUS_UPC_RETI_SLEEP_Val 0x3Ful /**< \brief (PICOP_CMD_STATUS) RETI: Clear SLEEPMODE (RETI) */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R0_Val 0x40ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R3..R0 (RETIS) */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R4_Val 0x41ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R7..R4 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R8_Val 0x42ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R11..R8 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R12_Val 0x43ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R15..R12 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R16_Val 0x44ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R19..R16 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R20_Val 0x45ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R23..R20 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R24_Val 0x46ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R27..R24 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R28_Val 0x47ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R31..R28 */
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_SP_Val 0x48ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore CCR..SP */
+#define PICOP_CMD_STATUS_UPC_RETI_EXEC_Val 0x49ul /**< \brief (PICOP_CMD_STATUS) RETI: Return to code execution (PC <- LINK) */
+#define PICOP_CMD_STATUS_UPC_EXEC (PICOP_CMD_STATUS_UPC_EXEC_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_EXEC_NOBRK (PICOP_CMD_STATUS_UPC_EXEC_NOBRK_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_EXEC_NOP (PICOP_CMD_STATUS_UPC_EXEC_NOP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_EXEC_IMM (PICOP_CMD_STATUS_UPC_EXEC_IMM_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_ICACHE_FLUSH (PICOP_CMD_STATUS_UPC_ICACHE_FLUSH_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_HALT (PICOP_CMD_STATUS_UPC_HALT_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_HALTED (PICOP_CMD_STATUS_UPC_HALTED_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_SLEEP (PICOP_CMD_STATUS_UPC_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_SLEEPING (PICOP_CMD_STATUS_UPC_SLEEPING_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_WAKEUP_RST1 (PICOP_CMD_STATUS_UPC_WAKEUP_RST1_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP (PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY (PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_OCD_STATE (PICOP_CMD_STATUS_UPC_OCD_STATE_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_NOP (PICOP_CMD_STATUS_UPC_OCD_STATE_NOP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_IMM (PICOP_CMD_STATUS_UPC_OCD_STATE_IMM_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP (PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT (PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_OCD_BREAKI (PICOP_CMD_STATUS_UPC_OCD_BREAKI_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_CANCEL_EX (PICOP_CMD_STATUS_UPC_CANCEL_EX_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ (PICOP_CMD_STATUS_UPC_IRQ_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_0 (PICOP_CMD_STATUS_UPC_IRQ_CTS_0_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_1 (PICOP_CMD_STATUS_UPC_IRQ_CTS_1_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_2 (PICOP_CMD_STATUS_UPC_IRQ_CTS_2_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_3 (PICOP_CMD_STATUS_UPC_IRQ_CTS_3_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_4 (PICOP_CMD_STATUS_UPC_IRQ_CTS_4_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_5 (PICOP_CMD_STATUS_UPC_IRQ_CTS_5_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_6 (PICOP_CMD_STATUS_UPC_IRQ_CTS_6_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_7 (PICOP_CMD_STATUS_UPC_IRQ_CTS_7_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_CTS_PC (PICOP_CMD_STATUS_UPC_IRQ_CTS_PC_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_IRQ_ACK (PICOP_CMD_STATUS_UPC_IRQ_ACK_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_EXCEPT (PICOP_CMD_STATUS_UPC_EXCEPT_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_SLEEP (PICOP_CMD_STATUS_UPC_RETI_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R0 (PICOP_CMD_STATUS_UPC_RETI_CTR_R0_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R4 (PICOP_CMD_STATUS_UPC_RETI_CTR_R4_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R8 (PICOP_CMD_STATUS_UPC_RETI_CTR_R8_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R12 (PICOP_CMD_STATUS_UPC_RETI_CTR_R12_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R16 (PICOP_CMD_STATUS_UPC_RETI_CTR_R16_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R20 (PICOP_CMD_STATUS_UPC_RETI_CTR_R20_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R24 (PICOP_CMD_STATUS_UPC_RETI_CTR_R24_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_R28 (PICOP_CMD_STATUS_UPC_RETI_CTR_R28_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_CTR_SP (PICOP_CMD_STATUS_UPC_RETI_CTR_SP_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_UPC_RETI_EXEC (PICOP_CMD_STATUS_UPC_RETI_EXEC_Val << PICOP_CMD_STATUS_UPC_Pos)
+#define PICOP_CMD_STATUS_STATE_Pos 27 /**< \brief (PICOP_CMD_STATUS) System State */
+#define PICOP_CMD_STATUS_STATE_Msk (0x1Ful << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE(value) (PICOP_CMD_STATUS_STATE_Msk & ((value) << PICOP_CMD_STATUS_STATE_Pos))
+#define PICOP_CMD_STATUS_STATE_RESET_0_Val 0x0ul /**< \brief (PICOP_CMD_STATUS) Reset step 0 */
+#define PICOP_CMD_STATUS_STATE_RESET_1_Val 0x1ul /**< \brief (PICOP_CMD_STATUS) Reset step 1 */
+#define PICOP_CMD_STATUS_STATE_RESET_2_Val 0x2ul /**< \brief (PICOP_CMD_STATUS) Reset step 2 */
+#define PICOP_CMD_STATUS_STATE_RESET_3_Val 0x3ul /**< \brief (PICOP_CMD_STATUS) Reset step 3 */
+#define PICOP_CMD_STATUS_STATE_FUSE_CHECK_Val 0x4ul /**< \brief (PICOP_CMD_STATUS) Fuse check */
+#define PICOP_CMD_STATUS_STATE_INITIALIZED_Val 0x5ul /**< \brief (PICOP_CMD_STATUS) Initialized */
+#define PICOP_CMD_STATUS_STATE_STANDBY_Val 0x6ul /**< \brief (PICOP_CMD_STATUS) Standby */
+#define PICOP_CMD_STATUS_STATE_RUNNING_LOCKED_Val 0x8ul /**< \brief (PICOP_CMD_STATUS) Running locked */
+#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1_Val 0x9ul /**< \brief (PICOP_CMD_STATUS) Running unlock step 1 */
+#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2_Val 0xAul /**< \brief (PICOP_CMD_STATUS) Running unlock step 2 */
+#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3_Val 0xBul /**< \brief (PICOP_CMD_STATUS) Running unlock step 3 */
+#define PICOP_CMD_STATUS_STATE_RUNNING_Val 0xCul /**< \brief (PICOP_CMD_STATUS) Running */
+#define PICOP_CMD_STATUS_STATE_RUNNING_BOOT_Val 0xDul /**< \brief (PICOP_CMD_STATUS) Running boot */
+#define PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD_Val 0xEul /**< \brief (PICOP_CMD_STATUS) Running hostocd */
+#define PICOP_CMD_STATUS_STATE_RESETTING_Val 0x10ul /**< \brief (PICOP_CMD_STATUS) Resetting */
+#define PICOP_CMD_STATUS_STATE_STOPPING_Val 0x11ul /**< \brief (PICOP_CMD_STATUS) Stopping */
+#define PICOP_CMD_STATUS_STATE_STOPPED_Val 0x12ul /**< \brief (PICOP_CMD_STATUS) Stopped */
+#define PICOP_CMD_STATUS_STATE_RESET_0 (PICOP_CMD_STATUS_STATE_RESET_0_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RESET_1 (PICOP_CMD_STATUS_STATE_RESET_1_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RESET_2 (PICOP_CMD_STATUS_STATE_RESET_2_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RESET_3 (PICOP_CMD_STATUS_STATE_RESET_3_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_FUSE_CHECK (PICOP_CMD_STATUS_STATE_FUSE_CHECK_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_INITIALIZED (PICOP_CMD_STATUS_STATE_INITIALIZED_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_STANDBY (PICOP_CMD_STATUS_STATE_STANDBY_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING_LOCKED (PICOP_CMD_STATUS_STATE_RUNNING_LOCKED_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1 (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2 (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3 (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING (PICOP_CMD_STATUS_STATE_RUNNING_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING_BOOT (PICOP_CMD_STATUS_STATE_RUNNING_BOOT_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD (PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_RESETTING (PICOP_CMD_STATUS_STATE_RESETTING_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_STOPPING (PICOP_CMD_STATUS_STATE_STOPPING_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_STATE_STOPPED (PICOP_CMD_STATUS_STATE_STOPPED_Val << PICOP_CMD_STATUS_STATE_Pos)
+#define PICOP_CMD_STATUS_MASK 0xF8FF077Ful /**< \brief (PICOP_CMD_STATUS) MASK Register */
+
+/* -------- PICOP_PC : (PICOP Offset: 0x02C) (R/W 32) Program Counter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PC:16; /*!< bit: 0..15 Program Counter */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_PC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_PC_OFFSET 0x02C /**< \brief (PICOP_PC offset) Program Counter */
+#define PICOP_PC_RESETVALUE 0x00000000ul /**< \brief (PICOP_PC reset_value) Program Counter */
+
+#define PICOP_PC_PC_Pos 0 /**< \brief (PICOP_PC) Program Counter */
+#define PICOP_PC_PC_Msk (0xFFFFul << PICOP_PC_PC_Pos)
+#define PICOP_PC_PC(value) (PICOP_PC_PC_Msk & ((value) << PICOP_PC_PC_Pos))
+#define PICOP_PC_MASK 0x0000FFFFul /**< \brief (PICOP_PC) MASK Register */
+
+/* -------- PICOP_HF : (PICOP Offset: 0x030) (R/W 32) Host Flags -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HF:32; /*!< bit: 0..31 Host Flags */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_HF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_HF_OFFSET 0x030 /**< \brief (PICOP_HF offset) Host Flags */
+#define PICOP_HF_RESETVALUE 0x00000000ul /**< \brief (PICOP_HF reset_value) Host Flags */
+
+#define PICOP_HF_HF_Pos 0 /**< \brief (PICOP_HF) Host Flags */
+#define PICOP_HF_HF_Msk (0xFFFFFFFFul << PICOP_HF_HF_Pos)
+#define PICOP_HF_HF(value) (PICOP_HF_HF_Msk & ((value) << PICOP_HF_HF_Pos))
+#define PICOP_HF_MASK 0xFFFFFFFFul /**< \brief (PICOP_HF) MASK Register */
+
+/* -------- PICOP_HFCTRL : (PICOP Offset: 0x034) (R/W 32) Host Flag Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t IRQENCLR:4; /*!< bit: 4.. 7 Host Flags IRQ Enable Clear */
+ uint32_t :4; /*!< bit: 8..11 Reserved */
+ uint32_t IRQENSET:4; /*!< bit: 12..15 Host Flags IRQ Enable Set */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_HFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_HFCTRL_OFFSET 0x034 /**< \brief (PICOP_HFCTRL offset) Host Flag Control */
+#define PICOP_HFCTRL_RESETVALUE 0x00000000ul /**< \brief (PICOP_HFCTRL reset_value) Host Flag Control */
+
+#define PICOP_HFCTRL_IRQENCLR_Pos 4 /**< \brief (PICOP_HFCTRL) Host Flags IRQ Enable Clear */
+#define PICOP_HFCTRL_IRQENCLR_Msk (0xFul << PICOP_HFCTRL_IRQENCLR_Pos)
+#define PICOP_HFCTRL_IRQENCLR(value) (PICOP_HFCTRL_IRQENCLR_Msk & ((value) << PICOP_HFCTRL_IRQENCLR_Pos))
+#define PICOP_HFCTRL_IRQENSET_Pos 12 /**< \brief (PICOP_HFCTRL) Host Flags IRQ Enable Set */
+#define PICOP_HFCTRL_IRQENSET_Msk (0xFul << PICOP_HFCTRL_IRQENSET_Pos)
+#define PICOP_HFCTRL_IRQENSET(value) (PICOP_HFCTRL_IRQENSET_Msk & ((value) << PICOP_HFCTRL_IRQENSET_Pos))
+#define PICOP_HFCTRL_MASK 0x0000F0F0ul /**< \brief (PICOP_HFCTRL) MASK Register */
+
+/* -------- PICOP_HFSETCLR0 : (PICOP Offset: 0x038) (R/W 32) Host Flags Set/Clr -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HFCLR0:8; /*!< bit: 0.. 7 Host Flags Clear bits 7:0 */
+ uint32_t HFSET0:8; /*!< bit: 8..15 Host Flags Set bits 7:0 */
+ uint32_t HFCLR1:8; /*!< bit: 16..23 Host Flags Clear bits 15:8 */
+ uint32_t HFSET1:8; /*!< bit: 24..31 Host Flags Set bits 15:8 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_HFSETCLR0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_HFSETCLR0_OFFSET 0x038 /**< \brief (PICOP_HFSETCLR0 offset) Host Flags Set/Clr */
+#define PICOP_HFSETCLR0_RESETVALUE 0x00000000ul /**< \brief (PICOP_HFSETCLR0 reset_value) Host Flags Set/Clr */
+
+#define PICOP_HFSETCLR0_HFCLR0_Pos 0 /**< \brief (PICOP_HFSETCLR0) Host Flags Clear bits 7:0 */
+#define PICOP_HFSETCLR0_HFCLR0_Msk (0xFFul << PICOP_HFSETCLR0_HFCLR0_Pos)
+#define PICOP_HFSETCLR0_HFCLR0(value) (PICOP_HFSETCLR0_HFCLR0_Msk & ((value) << PICOP_HFSETCLR0_HFCLR0_Pos))
+#define PICOP_HFSETCLR0_HFSET0_Pos 8 /**< \brief (PICOP_HFSETCLR0) Host Flags Set bits 7:0 */
+#define PICOP_HFSETCLR0_HFSET0_Msk (0xFFul << PICOP_HFSETCLR0_HFSET0_Pos)
+#define PICOP_HFSETCLR0_HFSET0(value) (PICOP_HFSETCLR0_HFSET0_Msk & ((value) << PICOP_HFSETCLR0_HFSET0_Pos))
+#define PICOP_HFSETCLR0_HFCLR1_Pos 16 /**< \brief (PICOP_HFSETCLR0) Host Flags Clear bits 15:8 */
+#define PICOP_HFSETCLR0_HFCLR1_Msk (0xFFul << PICOP_HFSETCLR0_HFCLR1_Pos)
+#define PICOP_HFSETCLR0_HFCLR1(value) (PICOP_HFSETCLR0_HFCLR1_Msk & ((value) << PICOP_HFSETCLR0_HFCLR1_Pos))
+#define PICOP_HFSETCLR0_HFSET1_Pos 24 /**< \brief (PICOP_HFSETCLR0) Host Flags Set bits 15:8 */
+#define PICOP_HFSETCLR0_HFSET1_Msk (0xFFul << PICOP_HFSETCLR0_HFSET1_Pos)
+#define PICOP_HFSETCLR0_HFSET1(value) (PICOP_HFSETCLR0_HFSET1_Msk & ((value) << PICOP_HFSETCLR0_HFSET1_Pos))
+#define PICOP_HFSETCLR0_MASK 0xFFFFFFFFul /**< \brief (PICOP_HFSETCLR0) MASK Register */
+
+/* -------- PICOP_HFSETCLR1 : (PICOP Offset: 0x03C) (R/W 32) Host Flags Set/Clr -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HFCLR2:8; /*!< bit: 0.. 7 Host Flags Clear bits 23:16 */
+ uint32_t HFSET2:8; /*!< bit: 8..15 Host Flags Set bits 23:16 */
+ uint32_t HFCLR3:8; /*!< bit: 16..23 Host Flags Clear bits 31:24 */
+ uint32_t HFSET3:8; /*!< bit: 24..31 Host Flags Set bits 31:24 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_HFSETCLR1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_HFSETCLR1_OFFSET 0x03C /**< \brief (PICOP_HFSETCLR1 offset) Host Flags Set/Clr */
+#define PICOP_HFSETCLR1_RESETVALUE 0x00000000ul /**< \brief (PICOP_HFSETCLR1 reset_value) Host Flags Set/Clr */
+
+#define PICOP_HFSETCLR1_HFCLR2_Pos 0 /**< \brief (PICOP_HFSETCLR1) Host Flags Clear bits 23:16 */
+#define PICOP_HFSETCLR1_HFCLR2_Msk (0xFFul << PICOP_HFSETCLR1_HFCLR2_Pos)
+#define PICOP_HFSETCLR1_HFCLR2(value) (PICOP_HFSETCLR1_HFCLR2_Msk & ((value) << PICOP_HFSETCLR1_HFCLR2_Pos))
+#define PICOP_HFSETCLR1_HFSET2_Pos 8 /**< \brief (PICOP_HFSETCLR1) Host Flags Set bits 23:16 */
+#define PICOP_HFSETCLR1_HFSET2_Msk (0xFFul << PICOP_HFSETCLR1_HFSET2_Pos)
+#define PICOP_HFSETCLR1_HFSET2(value) (PICOP_HFSETCLR1_HFSET2_Msk & ((value) << PICOP_HFSETCLR1_HFSET2_Pos))
+#define PICOP_HFSETCLR1_HFCLR3_Pos 16 /**< \brief (PICOP_HFSETCLR1) Host Flags Clear bits 31:24 */
+#define PICOP_HFSETCLR1_HFCLR3_Msk (0xFFul << PICOP_HFSETCLR1_HFCLR3_Pos)
+#define PICOP_HFSETCLR1_HFCLR3(value) (PICOP_HFSETCLR1_HFCLR3_Msk & ((value) << PICOP_HFSETCLR1_HFCLR3_Pos))
+#define PICOP_HFSETCLR1_HFSET3_Pos 24 /**< \brief (PICOP_HFSETCLR1) Host Flags Set bits 31:24 */
+#define PICOP_HFSETCLR1_HFSET3_Msk (0xFFul << PICOP_HFSETCLR1_HFSET3_Pos)
+#define PICOP_HFSETCLR1_HFSET3(value) (PICOP_HFSETCLR1_HFSET3_Msk & ((value) << PICOP_HFSETCLR1_HFSET3_Pos))
+#define PICOP_HFSETCLR1_MASK 0xFFFFFFFFul /**< \brief (PICOP_HFSETCLR1) MASK Register */
+
+/* -------- PICOP_OCDCONFIG : (PICOP Offset: 0x050) (R/W 32) OCD Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t CCNTEN:1; /*!< bit: 1 Cycle Counter Enable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDCONFIG_OFFSET 0x050 /**< \brief (PICOP_OCDCONFIG offset) OCD Configuration */
+#define PICOP_OCDCONFIG_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDCONFIG reset_value) OCD Configuration */
+
+#define PICOP_OCDCONFIG_CCNTEN_Pos 1 /**< \brief (PICOP_OCDCONFIG) Cycle Counter Enable */
+#define PICOP_OCDCONFIG_CCNTEN (0x1ul << PICOP_OCDCONFIG_CCNTEN_Pos)
+#define PICOP_OCDCONFIG_MASK 0x00000002ul /**< \brief (PICOP_OCDCONFIG) MASK Register */
+
+/* -------- PICOP_OCDCONTROL : (PICOP Offset: 0x054) (R/W 32) OCD Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OCDEN:1; /*!< bit: 0 OCD Enable */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t BPSSTEP:1; /*!< bit: 2 Single Step Breakpoint */
+ uint32_t BPCOF:1; /*!< bit: 3 Change of Flow Breakpoint */
+ uint32_t BPRST:1; /*!< bit: 4 Reset Breakpoint */
+ uint32_t BPEXCEPTION:1; /*!< bit: 5 Exception Breakpoint */
+ uint32_t BPIRQ:1; /*!< bit: 6 Interrupt Request Breakpoint */
+ uint32_t BPSW:1; /*!< bit: 7 Software Breakpoint */
+ uint32_t BPSLEEP:1; /*!< bit: 8 Sleep Breakpoint */
+ uint32_t BPWDT:1; /*!< bit: 9 Watchdog Timer Breakpoint */
+ uint32_t BPISA:1; /*!< bit: 10 ISA Breakpoint */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t BPCOMP:4; /*!< bit: 12..15 Comparator Breakpoint */
+ uint32_t BPGENMODE:4; /*!< bit: 16..19 Breakpoint Generator n Mode */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDCONTROL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDCONTROL_OFFSET 0x054 /**< \brief (PICOP_OCDCONTROL offset) OCD Control */
+#define PICOP_OCDCONTROL_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDCONTROL reset_value) OCD Control */
+
+#define PICOP_OCDCONTROL_OCDEN_Pos 0 /**< \brief (PICOP_OCDCONTROL) OCD Enable */
+#define PICOP_OCDCONTROL_OCDEN (0x1ul << PICOP_OCDCONTROL_OCDEN_Pos)
+#define PICOP_OCDCONTROL_BPSSTEP_Pos 2 /**< \brief (PICOP_OCDCONTROL) Single Step Breakpoint */
+#define PICOP_OCDCONTROL_BPSSTEP (0x1ul << PICOP_OCDCONTROL_BPSSTEP_Pos)
+#define PICOP_OCDCONTROL_BPCOF_Pos 3 /**< \brief (PICOP_OCDCONTROL) Change of Flow Breakpoint */
+#define PICOP_OCDCONTROL_BPCOF (0x1ul << PICOP_OCDCONTROL_BPCOF_Pos)
+#define PICOP_OCDCONTROL_BPRST_Pos 4 /**< \brief (PICOP_OCDCONTROL) Reset Breakpoint */
+#define PICOP_OCDCONTROL_BPRST (0x1ul << PICOP_OCDCONTROL_BPRST_Pos)
+#define PICOP_OCDCONTROL_BPEXCEPTION_Pos 5 /**< \brief (PICOP_OCDCONTROL) Exception Breakpoint */
+#define PICOP_OCDCONTROL_BPEXCEPTION (0x1ul << PICOP_OCDCONTROL_BPEXCEPTION_Pos)
+#define PICOP_OCDCONTROL_BPIRQ_Pos 6 /**< \brief (PICOP_OCDCONTROL) Interrupt Request Breakpoint */
+#define PICOP_OCDCONTROL_BPIRQ (0x1ul << PICOP_OCDCONTROL_BPIRQ_Pos)
+#define PICOP_OCDCONTROL_BPSW_Pos 7 /**< \brief (PICOP_OCDCONTROL) Software Breakpoint */
+#define PICOP_OCDCONTROL_BPSW (0x1ul << PICOP_OCDCONTROL_BPSW_Pos)
+#define PICOP_OCDCONTROL_BPSLEEP_Pos 8 /**< \brief (PICOP_OCDCONTROL) Sleep Breakpoint */
+#define PICOP_OCDCONTROL_BPSLEEP (0x1ul << PICOP_OCDCONTROL_BPSLEEP_Pos)
+#define PICOP_OCDCONTROL_BPWDT_Pos 9 /**< \brief (PICOP_OCDCONTROL) Watchdog Timer Breakpoint */
+#define PICOP_OCDCONTROL_BPWDT (0x1ul << PICOP_OCDCONTROL_BPWDT_Pos)
+#define PICOP_OCDCONTROL_BPISA_Pos 10 /**< \brief (PICOP_OCDCONTROL) ISA Breakpoint */
+#define PICOP_OCDCONTROL_BPISA (0x1ul << PICOP_OCDCONTROL_BPISA_Pos)
+#define PICOP_OCDCONTROL_BPCOMP_Pos 12 /**< \brief (PICOP_OCDCONTROL) Comparator Breakpoint */
+#define PICOP_OCDCONTROL_BPCOMP_Msk (0xFul << PICOP_OCDCONTROL_BPCOMP_Pos)
+#define PICOP_OCDCONTROL_BPCOMP(value) (PICOP_OCDCONTROL_BPCOMP_Msk & ((value) << PICOP_OCDCONTROL_BPCOMP_Pos))
+#define PICOP_OCDCONTROL_BPGENMODE_Pos 16 /**< \brief (PICOP_OCDCONTROL) Breakpoint Generator n Mode */
+#define PICOP_OCDCONTROL_BPGENMODE_Msk (0xFul << PICOP_OCDCONTROL_BPGENMODE_Pos)
+#define PICOP_OCDCONTROL_BPGENMODE(value) (PICOP_OCDCONTROL_BPGENMODE_Msk & ((value) << PICOP_OCDCONTROL_BPGENMODE_Pos))
+#define PICOP_OCDCONTROL_MASK 0x000FF7FDul /**< \brief (PICOP_OCDCONTROL) MASK Register */
+
+/* -------- PICOP_OCDSTATUS : (PICOP Offset: 0x058) (R/W 32) OCD Status and Command -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // CMD mode
+ uint32_t INST:16; /*!< bit: 0..15 Instruction Override */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } CMD; /*!< Structure used for CMD */
+ struct { // STATUS mode
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t BPEXT:1; /*!< bit: 1 External Breakpoint */
+ uint32_t BPSSTEP:1; /*!< bit: 2 Single Step Breakpoint */
+ uint32_t BPCOF:1; /*!< bit: 3 Change of Flow Breakpoint */
+ uint32_t BPRST:1; /*!< bit: 4 Reset Breakpoint */
+ uint32_t BPEXCEPTION:1; /*!< bit: 5 Exception Breakpoint */
+ uint32_t BPIRQ:1; /*!< bit: 6 Interrupt Request Breakpoint */
+ uint32_t BPSW:1; /*!< bit: 7 Software Breakpoint */
+ uint32_t BPSLEEP:1; /*!< bit: 8 Sleep Breakpoint */
+ uint32_t BPWDT:1; /*!< bit: 9 Watchdog Timer Breakpoint */
+ uint32_t BPISA:1; /*!< bit: 10 ISA Breakpoint */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t BPCOMP:4; /*!< bit: 12..15 Comparator Breakpoint */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } STATUS; /*!< Structure used for STATUS */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDSTATUS_OFFSET 0x058 /**< \brief (PICOP_OCDSTATUS offset) OCD Status and Command */
+#define PICOP_OCDSTATUS_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDSTATUS reset_value) OCD Status and Command */
+
+// CMD mode
+#define PICOP_OCDSTATUS_CMD_INST_Pos 0 /**< \brief (PICOP_OCDSTATUS_CMD) Instruction Override */
+#define PICOP_OCDSTATUS_CMD_INST_Msk (0xFFFFul << PICOP_OCDSTATUS_CMD_INST_Pos)
+#define PICOP_OCDSTATUS_CMD_INST(value) (PICOP_OCDSTATUS_CMD_INST_Msk & ((value) << PICOP_OCDSTATUS_CMD_INST_Pos))
+#define PICOP_OCDSTATUS_CMD_MASK 0x0000FFFFul /**< \brief (PICOP_OCDSTATUS_CMD) MASK Register */
+
+// STATUS mode
+#define PICOP_OCDSTATUS_STATUS_BPEXT_Pos 1 /**< \brief (PICOP_OCDSTATUS_STATUS) External Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPEXT (0x1ul << PICOP_OCDSTATUS_STATUS_BPEXT_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPSSTEP_Pos 2 /**< \brief (PICOP_OCDSTATUS_STATUS) Single Step Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPSSTEP (0x1ul << PICOP_OCDSTATUS_STATUS_BPSSTEP_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPCOF_Pos 3 /**< \brief (PICOP_OCDSTATUS_STATUS) Change of Flow Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPCOF (0x1ul << PICOP_OCDSTATUS_STATUS_BPCOF_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPRST_Pos 4 /**< \brief (PICOP_OCDSTATUS_STATUS) Reset Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPRST (0x1ul << PICOP_OCDSTATUS_STATUS_BPRST_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPEXCEPTION_Pos 5 /**< \brief (PICOP_OCDSTATUS_STATUS) Exception Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPEXCEPTION (0x1ul << PICOP_OCDSTATUS_STATUS_BPEXCEPTION_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPIRQ_Pos 6 /**< \brief (PICOP_OCDSTATUS_STATUS) Interrupt Request Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPIRQ (0x1ul << PICOP_OCDSTATUS_STATUS_BPIRQ_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPSW_Pos 7 /**< \brief (PICOP_OCDSTATUS_STATUS) Software Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPSW (0x1ul << PICOP_OCDSTATUS_STATUS_BPSW_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPSLEEP_Pos 8 /**< \brief (PICOP_OCDSTATUS_STATUS) Sleep Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPSLEEP (0x1ul << PICOP_OCDSTATUS_STATUS_BPSLEEP_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPWDT_Pos 9 /**< \brief (PICOP_OCDSTATUS_STATUS) Watchdog Timer Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPWDT (0x1ul << PICOP_OCDSTATUS_STATUS_BPWDT_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPISA_Pos 10 /**< \brief (PICOP_OCDSTATUS_STATUS) ISA Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPISA (0x1ul << PICOP_OCDSTATUS_STATUS_BPISA_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPCOMP_Pos 12 /**< \brief (PICOP_OCDSTATUS_STATUS) Comparator Breakpoint */
+#define PICOP_OCDSTATUS_STATUS_BPCOMP_Msk (0xFul << PICOP_OCDSTATUS_STATUS_BPCOMP_Pos)
+#define PICOP_OCDSTATUS_STATUS_BPCOMP(value) (PICOP_OCDSTATUS_STATUS_BPCOMP_Msk & ((value) << PICOP_OCDSTATUS_STATUS_BPCOMP_Pos))
+#define PICOP_OCDSTATUS_STATUS_MASK 0x0000F7FEul /**< \brief (PICOP_OCDSTATUS_STATUS) MASK Register */
+
+/* -------- PICOP_OCDPC : (PICOP Offset: 0x05C) (R/W 32) ODC Program Counter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PC:16; /*!< bit: 0..15 Program Counter */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDPC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDPC_OFFSET 0x05C /**< \brief (PICOP_OCDPC offset) ODC Program Counter */
+
+#define PICOP_OCDPC_PC_Pos 0 /**< \brief (PICOP_OCDPC) Program Counter */
+#define PICOP_OCDPC_PC_Msk (0xFFFFul << PICOP_OCDPC_PC_Pos)
+#define PICOP_OCDPC_PC(value) (PICOP_OCDPC_PC_Msk & ((value) << PICOP_OCDPC_PC_Pos))
+#define PICOP_OCDPC_MASK 0x0000FFFFul /**< \brief (PICOP_OCDPC) MASK Register */
+
+/* -------- PICOP_OCDFEAT : (PICOP Offset: 0x060) (R/W 32) OCD Features -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCNT:2; /*!< bit: 0.. 1 Cycle Counter */
+ uint32_t BPGEN:2; /*!< bit: 2.. 3 Breakpoint Generators */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDFEAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDFEAT_OFFSET 0x060 /**< \brief (PICOP_OCDFEAT offset) OCD Features */
+#define PICOP_OCDFEAT_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDFEAT reset_value) OCD Features */
+
+#define PICOP_OCDFEAT_CCNT_Pos 0 /**< \brief (PICOP_OCDFEAT) Cycle Counter */
+#define PICOP_OCDFEAT_CCNT_Msk (0x3ul << PICOP_OCDFEAT_CCNT_Pos)
+#define PICOP_OCDFEAT_CCNT(value) (PICOP_OCDFEAT_CCNT_Msk & ((value) << PICOP_OCDFEAT_CCNT_Pos))
+#define PICOP_OCDFEAT_BPGEN_Pos 2 /**< \brief (PICOP_OCDFEAT) Breakpoint Generators */
+#define PICOP_OCDFEAT_BPGEN_Msk (0x3ul << PICOP_OCDFEAT_BPGEN_Pos)
+#define PICOP_OCDFEAT_BPGEN(value) (PICOP_OCDFEAT_BPGEN_Msk & ((value) << PICOP_OCDFEAT_BPGEN_Pos))
+#define PICOP_OCDFEAT_MASK 0x0000000Ful /**< \brief (PICOP_OCDFEAT) MASK Register */
+
+/* -------- PICOP_OCDCCNT : (PICOP Offset: 0x068) (R/W 32) OCD Cycle Counter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCNT:32; /*!< bit: 0..31 Cycle Count */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDCCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDCCNT_OFFSET 0x068 /**< \brief (PICOP_OCDCCNT offset) OCD Cycle Counter */
+#define PICOP_OCDCCNT_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDCCNT reset_value) OCD Cycle Counter */
+
+#define PICOP_OCDCCNT_CCNT_Pos 0 /**< \brief (PICOP_OCDCCNT) Cycle Count */
+#define PICOP_OCDCCNT_CCNT_Msk (0xFFFFFFFFul << PICOP_OCDCCNT_CCNT_Pos)
+#define PICOP_OCDCCNT_CCNT(value) (PICOP_OCDCCNT_CCNT_Msk & ((value) << PICOP_OCDCCNT_CCNT_Pos))
+#define PICOP_OCDCCNT_MASK 0xFFFFFFFFul /**< \brief (PICOP_OCDCCNT) MASK Register */
+
+/* -------- PICOP_OCDBPGEN : (PICOP Offset: 0x070) (R/W 32) OCD Breakpoint Generator n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BPGEN:16; /*!< bit: 0..15 Breakpoint Generator */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_OCDBPGEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_OCDBPGEN_OFFSET 0x070 /**< \brief (PICOP_OCDBPGEN offset) OCD Breakpoint Generator n */
+#define PICOP_OCDBPGEN_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDBPGEN reset_value) OCD Breakpoint Generator n */
+
+#define PICOP_OCDBPGEN_BPGEN_Pos 0 /**< \brief (PICOP_OCDBPGEN) Breakpoint Generator */
+#define PICOP_OCDBPGEN_BPGEN_Msk (0xFFFFul << PICOP_OCDBPGEN_BPGEN_Pos)
+#define PICOP_OCDBPGEN_BPGEN(value) (PICOP_OCDBPGEN_BPGEN_Msk & ((value) << PICOP_OCDBPGEN_BPGEN_Pos))
+#define PICOP_OCDBPGEN_MASK 0x0000FFFFul /**< \brief (PICOP_OCDBPGEN) MASK Register */
+
+/* -------- PICOP_R3R0 : (PICOP Offset: 0x080) (R/W 32) R3 to 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R3R0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R3R0_OFFSET 0x080 /**< \brief (PICOP_R3R0 offset) R3 to 0 */
+
+#define PICOP_R3R0_R0_Pos 0 /**< \brief (PICOP_R3R0) Register 0 */
+#define PICOP_R3R0_R0_Msk (0xFFul << PICOP_R3R0_R0_Pos)
+#define PICOP_R3R0_R0(value) (PICOP_R3R0_R0_Msk & ((value) << PICOP_R3R0_R0_Pos))
+#define PICOP_R3R0_R1_Pos 8 /**< \brief (PICOP_R3R0) Register 1 */
+#define PICOP_R3R0_R1_Msk (0xFFul << PICOP_R3R0_R1_Pos)
+#define PICOP_R3R0_R1(value) (PICOP_R3R0_R1_Msk & ((value) << PICOP_R3R0_R1_Pos))
+#define PICOP_R3R0_R2_Pos 16 /**< \brief (PICOP_R3R0) Register 2 */
+#define PICOP_R3R0_R2_Msk (0xFFul << PICOP_R3R0_R2_Pos)
+#define PICOP_R3R0_R2(value) (PICOP_R3R0_R2_Msk & ((value) << PICOP_R3R0_R2_Pos))
+#define PICOP_R3R0_R3_Pos 24 /**< \brief (PICOP_R3R0) Register 3 */
+#define PICOP_R3R0_R3_Msk (0xFFul << PICOP_R3R0_R3_Pos)
+#define PICOP_R3R0_R3(value) (PICOP_R3R0_R3_Msk & ((value) << PICOP_R3R0_R3_Pos))
+#define PICOP_R3R0_MASK 0xFFFFFFFFul /**< \brief (PICOP_R3R0) MASK Register */
+
+/* -------- PICOP_R7R4 : (PICOP Offset: 0x084) (R/W 32) R7 to 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R7R4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R7R4_OFFSET 0x084 /**< \brief (PICOP_R7R4 offset) R7 to 4 */
+
+#define PICOP_R7R4_R0_Pos 0 /**< \brief (PICOP_R7R4) Register 0 */
+#define PICOP_R7R4_R0_Msk (0xFFul << PICOP_R7R4_R0_Pos)
+#define PICOP_R7R4_R0(value) (PICOP_R7R4_R0_Msk & ((value) << PICOP_R7R4_R0_Pos))
+#define PICOP_R7R4_R1_Pos 8 /**< \brief (PICOP_R7R4) Register 1 */
+#define PICOP_R7R4_R1_Msk (0xFFul << PICOP_R7R4_R1_Pos)
+#define PICOP_R7R4_R1(value) (PICOP_R7R4_R1_Msk & ((value) << PICOP_R7R4_R1_Pos))
+#define PICOP_R7R4_R2_Pos 16 /**< \brief (PICOP_R7R4) Register 2 */
+#define PICOP_R7R4_R2_Msk (0xFFul << PICOP_R7R4_R2_Pos)
+#define PICOP_R7R4_R2(value) (PICOP_R7R4_R2_Msk & ((value) << PICOP_R7R4_R2_Pos))
+#define PICOP_R7R4_R3_Pos 24 /**< \brief (PICOP_R7R4) Register 3 */
+#define PICOP_R7R4_R3_Msk (0xFFul << PICOP_R7R4_R3_Pos)
+#define PICOP_R7R4_R3(value) (PICOP_R7R4_R3_Msk & ((value) << PICOP_R7R4_R3_Pos))
+#define PICOP_R7R4_MASK 0xFFFFFFFFul /**< \brief (PICOP_R7R4) MASK Register */
+
+/* -------- PICOP_R11R8 : (PICOP Offset: 0x088) (R/W 32) R11 to 8 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R11R8_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R11R8_OFFSET 0x088 /**< \brief (PICOP_R11R8 offset) R11 to 8 */
+
+#define PICOP_R11R8_R0_Pos 0 /**< \brief (PICOP_R11R8) Register 0 */
+#define PICOP_R11R8_R0_Msk (0xFFul << PICOP_R11R8_R0_Pos)
+#define PICOP_R11R8_R0(value) (PICOP_R11R8_R0_Msk & ((value) << PICOP_R11R8_R0_Pos))
+#define PICOP_R11R8_R1_Pos 8 /**< \brief (PICOP_R11R8) Register 1 */
+#define PICOP_R11R8_R1_Msk (0xFFul << PICOP_R11R8_R1_Pos)
+#define PICOP_R11R8_R1(value) (PICOP_R11R8_R1_Msk & ((value) << PICOP_R11R8_R1_Pos))
+#define PICOP_R11R8_R2_Pos 16 /**< \brief (PICOP_R11R8) Register 2 */
+#define PICOP_R11R8_R2_Msk (0xFFul << PICOP_R11R8_R2_Pos)
+#define PICOP_R11R8_R2(value) (PICOP_R11R8_R2_Msk & ((value) << PICOP_R11R8_R2_Pos))
+#define PICOP_R11R8_R3_Pos 24 /**< \brief (PICOP_R11R8) Register 3 */
+#define PICOP_R11R8_R3_Msk (0xFFul << PICOP_R11R8_R3_Pos)
+#define PICOP_R11R8_R3(value) (PICOP_R11R8_R3_Msk & ((value) << PICOP_R11R8_R3_Pos))
+#define PICOP_R11R8_MASK 0xFFFFFFFFul /**< \brief (PICOP_R11R8) MASK Register */
+
+/* -------- PICOP_R15R12 : (PICOP Offset: 0x08C) (R/W 32) R15 to 12 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R15R12_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R15R12_OFFSET 0x08C /**< \brief (PICOP_R15R12 offset) R15 to 12 */
+
+#define PICOP_R15R12_R0_Pos 0 /**< \brief (PICOP_R15R12) Register 0 */
+#define PICOP_R15R12_R0_Msk (0xFFul << PICOP_R15R12_R0_Pos)
+#define PICOP_R15R12_R0(value) (PICOP_R15R12_R0_Msk & ((value) << PICOP_R15R12_R0_Pos))
+#define PICOP_R15R12_R1_Pos 8 /**< \brief (PICOP_R15R12) Register 1 */
+#define PICOP_R15R12_R1_Msk (0xFFul << PICOP_R15R12_R1_Pos)
+#define PICOP_R15R12_R1(value) (PICOP_R15R12_R1_Msk & ((value) << PICOP_R15R12_R1_Pos))
+#define PICOP_R15R12_R2_Pos 16 /**< \brief (PICOP_R15R12) Register 2 */
+#define PICOP_R15R12_R2_Msk (0xFFul << PICOP_R15R12_R2_Pos)
+#define PICOP_R15R12_R2(value) (PICOP_R15R12_R2_Msk & ((value) << PICOP_R15R12_R2_Pos))
+#define PICOP_R15R12_R3_Pos 24 /**< \brief (PICOP_R15R12) Register 3 */
+#define PICOP_R15R12_R3_Msk (0xFFul << PICOP_R15R12_R3_Pos)
+#define PICOP_R15R12_R3(value) (PICOP_R15R12_R3_Msk & ((value) << PICOP_R15R12_R3_Pos))
+#define PICOP_R15R12_MASK 0xFFFFFFFFul /**< \brief (PICOP_R15R12) MASK Register */
+
+/* -------- PICOP_R19R16 : (PICOP Offset: 0x090) (R/W 32) R19 to 16 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R19R16_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R19R16_OFFSET 0x090 /**< \brief (PICOP_R19R16 offset) R19 to 16 */
+
+#define PICOP_R19R16_R0_Pos 0 /**< \brief (PICOP_R19R16) Register 0 */
+#define PICOP_R19R16_R0_Msk (0xFFul << PICOP_R19R16_R0_Pos)
+#define PICOP_R19R16_R0(value) (PICOP_R19R16_R0_Msk & ((value) << PICOP_R19R16_R0_Pos))
+#define PICOP_R19R16_R1_Pos 8 /**< \brief (PICOP_R19R16) Register 1 */
+#define PICOP_R19R16_R1_Msk (0xFFul << PICOP_R19R16_R1_Pos)
+#define PICOP_R19R16_R1(value) (PICOP_R19R16_R1_Msk & ((value) << PICOP_R19R16_R1_Pos))
+#define PICOP_R19R16_R2_Pos 16 /**< \brief (PICOP_R19R16) Register 2 */
+#define PICOP_R19R16_R2_Msk (0xFFul << PICOP_R19R16_R2_Pos)
+#define PICOP_R19R16_R2(value) (PICOP_R19R16_R2_Msk & ((value) << PICOP_R19R16_R2_Pos))
+#define PICOP_R19R16_R3_Pos 24 /**< \brief (PICOP_R19R16) Register 3 */
+#define PICOP_R19R16_R3_Msk (0xFFul << PICOP_R19R16_R3_Pos)
+#define PICOP_R19R16_R3(value) (PICOP_R19R16_R3_Msk & ((value) << PICOP_R19R16_R3_Pos))
+#define PICOP_R19R16_MASK 0xFFFFFFFFul /**< \brief (PICOP_R19R16) MASK Register */
+
+/* -------- PICOP_R23R20 : (PICOP Offset: 0x094) (R/W 32) R23 to 20 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R23R20_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R23R20_OFFSET 0x094 /**< \brief (PICOP_R23R20 offset) R23 to 20 */
+
+#define PICOP_R23R20_R0_Pos 0 /**< \brief (PICOP_R23R20) Register 0 */
+#define PICOP_R23R20_R0_Msk (0xFFul << PICOP_R23R20_R0_Pos)
+#define PICOP_R23R20_R0(value) (PICOP_R23R20_R0_Msk & ((value) << PICOP_R23R20_R0_Pos))
+#define PICOP_R23R20_R1_Pos 8 /**< \brief (PICOP_R23R20) Register 1 */
+#define PICOP_R23R20_R1_Msk (0xFFul << PICOP_R23R20_R1_Pos)
+#define PICOP_R23R20_R1(value) (PICOP_R23R20_R1_Msk & ((value) << PICOP_R23R20_R1_Pos))
+#define PICOP_R23R20_R2_Pos 16 /**< \brief (PICOP_R23R20) Register 2 */
+#define PICOP_R23R20_R2_Msk (0xFFul << PICOP_R23R20_R2_Pos)
+#define PICOP_R23R20_R2(value) (PICOP_R23R20_R2_Msk & ((value) << PICOP_R23R20_R2_Pos))
+#define PICOP_R23R20_R3_Pos 24 /**< \brief (PICOP_R23R20) Register 3 */
+#define PICOP_R23R20_R3_Msk (0xFFul << PICOP_R23R20_R3_Pos)
+#define PICOP_R23R20_R3(value) (PICOP_R23R20_R3_Msk & ((value) << PICOP_R23R20_R3_Pos))
+#define PICOP_R23R20_MASK 0xFFFFFFFFul /**< \brief (PICOP_R23R20) MASK Register */
+
+/* -------- PICOP_R27R24 : (PICOP Offset: 0x098) (R/W 32) R27 to 24: XH, XL, R25, R24 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R27R24_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R27R24_OFFSET 0x098 /**< \brief (PICOP_R27R24 offset) R27 to 24: XH, XL, R25, R24 */
+
+#define PICOP_R27R24_R0_Pos 0 /**< \brief (PICOP_R27R24) Register 0 */
+#define PICOP_R27R24_R0_Msk (0xFFul << PICOP_R27R24_R0_Pos)
+#define PICOP_R27R24_R0(value) (PICOP_R27R24_R0_Msk & ((value) << PICOP_R27R24_R0_Pos))
+#define PICOP_R27R24_R1_Pos 8 /**< \brief (PICOP_R27R24) Register 1 */
+#define PICOP_R27R24_R1_Msk (0xFFul << PICOP_R27R24_R1_Pos)
+#define PICOP_R27R24_R1(value) (PICOP_R27R24_R1_Msk & ((value) << PICOP_R27R24_R1_Pos))
+#define PICOP_R27R24_R2_Pos 16 /**< \brief (PICOP_R27R24) Register 2 */
+#define PICOP_R27R24_R2_Msk (0xFFul << PICOP_R27R24_R2_Pos)
+#define PICOP_R27R24_R2(value) (PICOP_R27R24_R2_Msk & ((value) << PICOP_R27R24_R2_Pos))
+#define PICOP_R27R24_R3_Pos 24 /**< \brief (PICOP_R27R24) Register 3 */
+#define PICOP_R27R24_R3_Msk (0xFFul << PICOP_R27R24_R3_Pos)
+#define PICOP_R27R24_R3(value) (PICOP_R27R24_R3_Msk & ((value) << PICOP_R27R24_R3_Pos))
+#define PICOP_R27R24_MASK 0xFFFFFFFFul /**< \brief (PICOP_R27R24) MASK Register */
+
+/* -------- PICOP_R31R28 : (PICOP Offset: 0x09C) (R/W 32) R31 to 28: ZH, ZL, YH, YL -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_R31R28_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_R31R28_OFFSET 0x09C /**< \brief (PICOP_R31R28 offset) R31 to 28: ZH, ZL, YH, YL */
+
+#define PICOP_R31R28_R0_Pos 0 /**< \brief (PICOP_R31R28) Register 0 */
+#define PICOP_R31R28_R0_Msk (0xFFul << PICOP_R31R28_R0_Pos)
+#define PICOP_R31R28_R0(value) (PICOP_R31R28_R0_Msk & ((value) << PICOP_R31R28_R0_Pos))
+#define PICOP_R31R28_R1_Pos 8 /**< \brief (PICOP_R31R28) Register 1 */
+#define PICOP_R31R28_R1_Msk (0xFFul << PICOP_R31R28_R1_Pos)
+#define PICOP_R31R28_R1(value) (PICOP_R31R28_R1_Msk & ((value) << PICOP_R31R28_R1_Pos))
+#define PICOP_R31R28_R2_Pos 16 /**< \brief (PICOP_R31R28) Register 2 */
+#define PICOP_R31R28_R2_Msk (0xFFul << PICOP_R31R28_R2_Pos)
+#define PICOP_R31R28_R2(value) (PICOP_R31R28_R2_Msk & ((value) << PICOP_R31R28_R2_Pos))
+#define PICOP_R31R28_R3_Pos 24 /**< \brief (PICOP_R31R28) Register 3 */
+#define PICOP_R31R28_R3_Msk (0xFFul << PICOP_R31R28_R3_Pos)
+#define PICOP_R31R28_R3(value) (PICOP_R31R28_R3_Msk & ((value) << PICOP_R31R28_R3_Pos))
+#define PICOP_R31R28_MASK 0xFFFFFFFFul /**< \brief (PICOP_R31R28) MASK Register */
+
+/* -------- PICOP_S1S0 : (PICOP Offset: 0x0A0) (R/W 32) System Regs 1 to 0: SR -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_S1S0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_S1S0_OFFSET 0x0A0 /**< \brief (PICOP_S1S0 offset) System Regs 1 to 0: SR */
+
+#define PICOP_S1S0_R0_Pos 0 /**< \brief (PICOP_S1S0) Register 0 */
+#define PICOP_S1S0_R0_Msk (0xFFul << PICOP_S1S0_R0_Pos)
+#define PICOP_S1S0_R0(value) (PICOP_S1S0_R0_Msk & ((value) << PICOP_S1S0_R0_Pos))
+#define PICOP_S1S0_R1_Pos 8 /**< \brief (PICOP_S1S0) Register 1 */
+#define PICOP_S1S0_R1_Msk (0xFFul << PICOP_S1S0_R1_Pos)
+#define PICOP_S1S0_R1(value) (PICOP_S1S0_R1_Msk & ((value) << PICOP_S1S0_R1_Pos))
+#define PICOP_S1S0_R2_Pos 16 /**< \brief (PICOP_S1S0) Register 2 */
+#define PICOP_S1S0_R2_Msk (0xFFul << PICOP_S1S0_R2_Pos)
+#define PICOP_S1S0_R2(value) (PICOP_S1S0_R2_Msk & ((value) << PICOP_S1S0_R2_Pos))
+#define PICOP_S1S0_R3_Pos 24 /**< \brief (PICOP_S1S0) Register 3 */
+#define PICOP_S1S0_R3_Msk (0xFFul << PICOP_S1S0_R3_Pos)
+#define PICOP_S1S0_R3(value) (PICOP_S1S0_R3_Msk & ((value) << PICOP_S1S0_R3_Pos))
+#define PICOP_S1S0_MASK 0xFFFFFFFFul /**< \brief (PICOP_S1S0) MASK Register */
+
+/* -------- PICOP_S3S2 : (PICOP Offset: 0x0A4) (R/W 32) System Regs 3 to 2: CTRL -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_S3S2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_S3S2_OFFSET 0x0A4 /**< \brief (PICOP_S3S2 offset) System Regs 3 to 2: CTRL */
+
+#define PICOP_S3S2_R0_Pos 0 /**< \brief (PICOP_S3S2) Register 0 */
+#define PICOP_S3S2_R0_Msk (0xFFul << PICOP_S3S2_R0_Pos)
+#define PICOP_S3S2_R0(value) (PICOP_S3S2_R0_Msk & ((value) << PICOP_S3S2_R0_Pos))
+#define PICOP_S3S2_R1_Pos 8 /**< \brief (PICOP_S3S2) Register 1 */
+#define PICOP_S3S2_R1_Msk (0xFFul << PICOP_S3S2_R1_Pos)
+#define PICOP_S3S2_R1(value) (PICOP_S3S2_R1_Msk & ((value) << PICOP_S3S2_R1_Pos))
+#define PICOP_S3S2_R2_Pos 16 /**< \brief (PICOP_S3S2) Register 2 */
+#define PICOP_S3S2_R2_Msk (0xFFul << PICOP_S3S2_R2_Pos)
+#define PICOP_S3S2_R2(value) (PICOP_S3S2_R2_Msk & ((value) << PICOP_S3S2_R2_Pos))
+#define PICOP_S3S2_R3_Pos 24 /**< \brief (PICOP_S3S2) Register 3 */
+#define PICOP_S3S2_R3_Msk (0xFFul << PICOP_S3S2_R3_Pos)
+#define PICOP_S3S2_R3(value) (PICOP_S3S2_R3_Msk & ((value) << PICOP_S3S2_R3_Pos))
+#define PICOP_S3S2_MASK 0xFFFFFFFFul /**< \brief (PICOP_S3S2) MASK Register */
+
+/* -------- PICOP_S5S4 : (PICOP Offset: 0x0A8) (R/W 32) System Regs 5 to 4: SREG, CCR -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_S5S4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_S5S4_OFFSET 0x0A8 /**< \brief (PICOP_S5S4 offset) System Regs 5 to 4: SREG, CCR */
+
+#define PICOP_S5S4_R0_Pos 0 /**< \brief (PICOP_S5S4) Register 0 */
+#define PICOP_S5S4_R0_Msk (0xFFul << PICOP_S5S4_R0_Pos)
+#define PICOP_S5S4_R0(value) (PICOP_S5S4_R0_Msk & ((value) << PICOP_S5S4_R0_Pos))
+#define PICOP_S5S4_R1_Pos 8 /**< \brief (PICOP_S5S4) Register 1 */
+#define PICOP_S5S4_R1_Msk (0xFFul << PICOP_S5S4_R1_Pos)
+#define PICOP_S5S4_R1(value) (PICOP_S5S4_R1_Msk & ((value) << PICOP_S5S4_R1_Pos))
+#define PICOP_S5S4_R2_Pos 16 /**< \brief (PICOP_S5S4) Register 2 */
+#define PICOP_S5S4_R2_Msk (0xFFul << PICOP_S5S4_R2_Pos)
+#define PICOP_S5S4_R2(value) (PICOP_S5S4_R2_Msk & ((value) << PICOP_S5S4_R2_Pos))
+#define PICOP_S5S4_R3_Pos 24 /**< \brief (PICOP_S5S4) Register 3 */
+#define PICOP_S5S4_R3_Msk (0xFFul << PICOP_S5S4_R3_Pos)
+#define PICOP_S5S4_R3(value) (PICOP_S5S4_R3_Msk & ((value) << PICOP_S5S4_R3_Pos))
+#define PICOP_S5S4_MASK 0xFFFFFFFFul /**< \brief (PICOP_S5S4) MASK Register */
+
+/* -------- PICOP_S11S10 : (PICOP Offset: 0x0B4) (R/W 32) System Regs 11 to 10: Immediate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_S11S10_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_S11S10_OFFSET 0x0B4 /**< \brief (PICOP_S11S10 offset) System Regs 11 to 10: Immediate */
+
+#define PICOP_S11S10_R0_Pos 0 /**< \brief (PICOP_S11S10) Register 0 */
+#define PICOP_S11S10_R0_Msk (0xFFul << PICOP_S11S10_R0_Pos)
+#define PICOP_S11S10_R0(value) (PICOP_S11S10_R0_Msk & ((value) << PICOP_S11S10_R0_Pos))
+#define PICOP_S11S10_R1_Pos 8 /**< \brief (PICOP_S11S10) Register 1 */
+#define PICOP_S11S10_R1_Msk (0xFFul << PICOP_S11S10_R1_Pos)
+#define PICOP_S11S10_R1(value) (PICOP_S11S10_R1_Msk & ((value) << PICOP_S11S10_R1_Pos))
+#define PICOP_S11S10_R2_Pos 16 /**< \brief (PICOP_S11S10) Register 2 */
+#define PICOP_S11S10_R2_Msk (0xFFul << PICOP_S11S10_R2_Pos)
+#define PICOP_S11S10_R2(value) (PICOP_S11S10_R2_Msk & ((value) << PICOP_S11S10_R2_Pos))
+#define PICOP_S11S10_R3_Pos 24 /**< \brief (PICOP_S11S10) Register 3 */
+#define PICOP_S11S10_R3_Msk (0xFFul << PICOP_S11S10_R3_Pos)
+#define PICOP_S11S10_R3(value) (PICOP_S11S10_R3_Msk & ((value) << PICOP_S11S10_R3_Pos))
+#define PICOP_S11S10_MASK 0xFFFFFFFFul /**< \brief (PICOP_S11S10) MASK Register */
+
+/* -------- PICOP_LINK : (PICOP Offset: 0x0B8) (R/W 32) Link -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_LINK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_LINK_OFFSET 0x0B8 /**< \brief (PICOP_LINK offset) Link */
+#define PICOP_LINK_MASK 0xFFFFFFFFul /**< \brief (PICOP_LINK) MASK Register */
+
+/* -------- PICOP_SP : (PICOP Offset: 0x0BC) (R/W 32) Stack Pointer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */
+ uint32_t R1:8; /*!< bit: 8..15 Register 1 */
+ uint32_t R2:8; /*!< bit: 16..23 Register 2 */
+ uint32_t R3:8; /*!< bit: 24..31 Register 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_SP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_SP_OFFSET 0x0BC /**< \brief (PICOP_SP offset) Stack Pointer */
+
+#define PICOP_SP_R0_Pos 0 /**< \brief (PICOP_SP) Register 0 */
+#define PICOP_SP_R0_Msk (0xFFul << PICOP_SP_R0_Pos)
+#define PICOP_SP_R0(value) (PICOP_SP_R0_Msk & ((value) << PICOP_SP_R0_Pos))
+#define PICOP_SP_R1_Pos 8 /**< \brief (PICOP_SP) Register 1 */
+#define PICOP_SP_R1_Msk (0xFFul << PICOP_SP_R1_Pos)
+#define PICOP_SP_R1(value) (PICOP_SP_R1_Msk & ((value) << PICOP_SP_R1_Pos))
+#define PICOP_SP_R2_Pos 16 /**< \brief (PICOP_SP) Register 2 */
+#define PICOP_SP_R2_Msk (0xFFul << PICOP_SP_R2_Pos)
+#define PICOP_SP_R2(value) (PICOP_SP_R2_Msk & ((value) << PICOP_SP_R2_Pos))
+#define PICOP_SP_R3_Pos 24 /**< \brief (PICOP_SP) Register 3 */
+#define PICOP_SP_R3_Msk (0xFFul << PICOP_SP_R3_Pos)
+#define PICOP_SP_R3(value) (PICOP_SP_R3_Msk & ((value) << PICOP_SP_R3_Pos))
+#define PICOP_SP_MASK 0xFFFFFFFFul /**< \brief (PICOP_SP) MASK Register */
+
+/* -------- PICOP_MMUFLASH : (PICOP Offset: 0x100) (R/W 32) MMU mapping for flash -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDRESS:4; /*!< bit: 0.. 3 MMU Flash Address */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_MMUFLASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_MMUFLASH_OFFSET 0x100 /**< \brief (PICOP_MMUFLASH offset) MMU mapping for flash */
+#define PICOP_MMUFLASH_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMUFLASH reset_value) MMU mapping for flash */
+
+#define PICOP_MMUFLASH_ADDRESS_Pos 0 /**< \brief (PICOP_MMUFLASH) MMU Flash Address */
+#define PICOP_MMUFLASH_ADDRESS_Msk (0xFul << PICOP_MMUFLASH_ADDRESS_Pos)
+#define PICOP_MMUFLASH_ADDRESS(value) (PICOP_MMUFLASH_ADDRESS_Msk & ((value) << PICOP_MMUFLASH_ADDRESS_Pos))
+#define PICOP_MMUFLASH_MASK 0x0000000Ful /**< \brief (PICOP_MMUFLASH) MASK Register */
+
+/* -------- PICOP_MMU0 : (PICOP Offset: 0x118) (R/W 32) MMU mapping user 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDRESS:32; /*!< bit: 0..31 MMU User 0 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_MMU0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_MMU0_OFFSET 0x118 /**< \brief (PICOP_MMU0 offset) MMU mapping user 0 */
+#define PICOP_MMU0_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMU0 reset_value) MMU mapping user 0 */
+
+#define PICOP_MMU0_ADDRESS_Pos 0 /**< \brief (PICOP_MMU0) MMU User 0 Address */
+#define PICOP_MMU0_ADDRESS_Msk (0xFFFFFFFFul << PICOP_MMU0_ADDRESS_Pos)
+#define PICOP_MMU0_ADDRESS(value) (PICOP_MMU0_ADDRESS_Msk & ((value) << PICOP_MMU0_ADDRESS_Pos))
+#define PICOP_MMU0_MASK 0xFFFFFFFFul /**< \brief (PICOP_MMU0) MASK Register */
+
+/* -------- PICOP_MMU1 : (PICOP Offset: 0x11C) (R/W 32) MMU mapping user 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDRESS:32; /*!< bit: 0..31 MMU User 1 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_MMU1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_MMU1_OFFSET 0x11C /**< \brief (PICOP_MMU1 offset) MMU mapping user 1 */
+#define PICOP_MMU1_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMU1 reset_value) MMU mapping user 1 */
+
+#define PICOP_MMU1_ADDRESS_Pos 0 /**< \brief (PICOP_MMU1) MMU User 1 Address */
+#define PICOP_MMU1_ADDRESS_Msk (0xFFFFFFFFul << PICOP_MMU1_ADDRESS_Pos)
+#define PICOP_MMU1_ADDRESS(value) (PICOP_MMU1_ADDRESS_Msk & ((value) << PICOP_MMU1_ADDRESS_Pos))
+#define PICOP_MMU1_MASK 0xFFFFFFFFul /**< \brief (PICOP_MMU1) MASK Register */
+
+/* -------- PICOP_MMUCTRL : (PICOP Offset: 0x120) (R/W 32) MMU Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IODIS:1; /*!< bit: 0 Peripheral MMU Disable */
+ uint32_t MEMDIS:1; /*!< bit: 1 Memory MMU Disable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_MMUCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_MMUCTRL_OFFSET 0x120 /**< \brief (PICOP_MMUCTRL offset) MMU Control */
+#define PICOP_MMUCTRL_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMUCTRL reset_value) MMU Control */
+
+#define PICOP_MMUCTRL_IODIS_Pos 0 /**< \brief (PICOP_MMUCTRL) Peripheral MMU Disable */
+#define PICOP_MMUCTRL_IODIS (0x1ul << PICOP_MMUCTRL_IODIS_Pos)
+#define PICOP_MMUCTRL_MEMDIS_Pos 1 /**< \brief (PICOP_MMUCTRL) Memory MMU Disable */
+#define PICOP_MMUCTRL_MEMDIS (0x1ul << PICOP_MMUCTRL_MEMDIS_Pos)
+#define PICOP_MMUCTRL_MASK 0x00000003ul /**< \brief (PICOP_MMUCTRL) MASK Register */
+
+/* -------- PICOP_ICACHE : (PICOP Offset: 0x180) (R/W 32) Instruction Cache Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CTRL:2; /*!< bit: 0.. 1 Instruction Cache Control */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_ICACHE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_ICACHE_OFFSET 0x180 /**< \brief (PICOP_ICACHE offset) Instruction Cache Control */
+#define PICOP_ICACHE_RESETVALUE 0x00000000ul /**< \brief (PICOP_ICACHE reset_value) Instruction Cache Control */
+
+#define PICOP_ICACHE_CTRL_Pos 0 /**< \brief (PICOP_ICACHE) Instruction Cache Control */
+#define PICOP_ICACHE_CTRL_Msk (0x3ul << PICOP_ICACHE_CTRL_Pos)
+#define PICOP_ICACHE_CTRL(value) (PICOP_ICACHE_CTRL_Msk & ((value) << PICOP_ICACHE_CTRL_Pos))
+#define PICOP_ICACHE_MASK 0x00000003ul /**< \brief (PICOP_ICACHE) MASK Register */
+
+/* -------- PICOP_ICACHELRU : (PICOP Offset: 0x184) (R/W 32) Instruction Cache LRU -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LRU0:2; /*!< bit: 0.. 1 Instruction Cache LRU 0 */
+ uint32_t LRU1:2; /*!< bit: 2.. 3 Instruction Cache LRU 1 */
+ uint32_t LRU2:2; /*!< bit: 4.. 5 Instruction Cache LRU 2 */
+ uint32_t LRU3:2; /*!< bit: 6.. 7 Instruction Cache LRU 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_ICACHELRU_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_ICACHELRU_OFFSET 0x184 /**< \brief (PICOP_ICACHELRU offset) Instruction Cache LRU */
+#define PICOP_ICACHELRU_RESETVALUE 0x00000000ul /**< \brief (PICOP_ICACHELRU reset_value) Instruction Cache LRU */
+
+#define PICOP_ICACHELRU_LRU0_Pos 0 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 0 */
+#define PICOP_ICACHELRU_LRU0_Msk (0x3ul << PICOP_ICACHELRU_LRU0_Pos)
+#define PICOP_ICACHELRU_LRU0(value) (PICOP_ICACHELRU_LRU0_Msk & ((value) << PICOP_ICACHELRU_LRU0_Pos))
+#define PICOP_ICACHELRU_LRU1_Pos 2 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 1 */
+#define PICOP_ICACHELRU_LRU1_Msk (0x3ul << PICOP_ICACHELRU_LRU1_Pos)
+#define PICOP_ICACHELRU_LRU1(value) (PICOP_ICACHELRU_LRU1_Msk & ((value) << PICOP_ICACHELRU_LRU1_Pos))
+#define PICOP_ICACHELRU_LRU2_Pos 4 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 2 */
+#define PICOP_ICACHELRU_LRU2_Msk (0x3ul << PICOP_ICACHELRU_LRU2_Pos)
+#define PICOP_ICACHELRU_LRU2(value) (PICOP_ICACHELRU_LRU2_Msk & ((value) << PICOP_ICACHELRU_LRU2_Pos))
+#define PICOP_ICACHELRU_LRU3_Pos 6 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 3 */
+#define PICOP_ICACHELRU_LRU3_Msk (0x3ul << PICOP_ICACHELRU_LRU3_Pos)
+#define PICOP_ICACHELRU_LRU3(value) (PICOP_ICACHELRU_LRU3_Msk & ((value) << PICOP_ICACHELRU_LRU3_Pos))
+#define PICOP_ICACHELRU_MASK 0x000000FFul /**< \brief (PICOP_ICACHELRU) MASK Register */
+
+/* -------- PICOP_QOSCTRL : (PICOP Offset: 0x200) (R/W 32) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PICOP_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PICOP_QOSCTRL_OFFSET 0x200 /**< \brief (PICOP_QOSCTRL offset) QOS Control */
+
+#define PICOP_QOSCTRL_QOS_Pos 0 /**< \brief (PICOP_QOSCTRL) Quality of Service */
+#define PICOP_QOSCTRL_QOS_Msk (0x3ul << PICOP_QOSCTRL_QOS_Pos)
+#define PICOP_QOSCTRL_QOS(value) (PICOP_QOSCTRL_QOS_Msk & ((value) << PICOP_QOSCTRL_QOS_Pos))
+#define PICOP_QOSCTRL_MASK 0x00000003ul /**< \brief (PICOP_QOSCTRL) MASK Register */
+
+/** \brief PICOP hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PICOP_ID_Type ID[8]; /**< \brief Offset: 0x000 (R/W 32) ID n */
+ __IO PICOP_CONFIG_Type CONFIG; /**< \brief Offset: 0x020 (R/W 32) Configuration */
+ __IO PICOP_CTRL_Type CTRL; /**< \brief Offset: 0x024 (R/W 32) Control */
+ __IO PICOP_CMD_Type CMD; /**< \brief Offset: 0x028 (R/W 32) Command */
+ __IO PICOP_PC_Type PC; /**< \brief Offset: 0x02C (R/W 32) Program Counter */
+ __IO PICOP_HF_Type HF; /**< \brief Offset: 0x030 (R/W 32) Host Flags */
+ __IO PICOP_HFCTRL_Type HFCTRL; /**< \brief Offset: 0x034 (R/W 32) Host Flag Control */
+ __IO PICOP_HFSETCLR0_Type HFSETCLR0; /**< \brief Offset: 0x038 (R/W 32) Host Flags Set/Clr */
+ __IO PICOP_HFSETCLR1_Type HFSETCLR1; /**< \brief Offset: 0x03C (R/W 32) Host Flags Set/Clr */
+ RoReg8 Reserved1[0x10];
+ __IO PICOP_OCDCONFIG_Type OCDCONFIG; /**< \brief Offset: 0x050 (R/W 32) OCD Configuration */
+ __IO PICOP_OCDCONTROL_Type OCDCONTROL; /**< \brief Offset: 0x054 (R/W 32) OCD Control */
+ __IO PICOP_OCDSTATUS_Type OCDSTATUS; /**< \brief Offset: 0x058 (R/W 32) OCD Status and Command */
+ __IO PICOP_OCDPC_Type OCDPC; /**< \brief Offset: 0x05C (R/W 32) ODC Program Counter */
+ __IO PICOP_OCDFEAT_Type OCDFEAT; /**< \brief Offset: 0x060 (R/W 32) OCD Features */
+ RoReg8 Reserved2[0x4];
+ __IO PICOP_OCDCCNT_Type OCDCCNT; /**< \brief Offset: 0x068 (R/W 32) OCD Cycle Counter */
+ RoReg8 Reserved3[0x4];
+ __IO PICOP_OCDBPGEN_Type OCDBPGEN[4]; /**< \brief Offset: 0x070 (R/W 32) OCD Breakpoint Generator n */
+ __IO PICOP_R3R0_Type R3R0; /**< \brief Offset: 0x080 (R/W 32) R3 to 0 */
+ __IO PICOP_R7R4_Type R7R4; /**< \brief Offset: 0x084 (R/W 32) R7 to 4 */
+ __IO PICOP_R11R8_Type R11R8; /**< \brief Offset: 0x088 (R/W 32) R11 to 8 */
+ __IO PICOP_R15R12_Type R15R12; /**< \brief Offset: 0x08C (R/W 32) R15 to 12 */
+ __IO PICOP_R19R16_Type R19R16; /**< \brief Offset: 0x090 (R/W 32) R19 to 16 */
+ __IO PICOP_R23R20_Type R23R20; /**< \brief Offset: 0x094 (R/W 32) R23 to 20 */
+ __IO PICOP_R27R24_Type R27R24; /**< \brief Offset: 0x098 (R/W 32) R27 to 24: XH, XL, R25, R24 */
+ __IO PICOP_R31R28_Type R31R28; /**< \brief Offset: 0x09C (R/W 32) R31 to 28: ZH, ZL, YH, YL */
+ __IO PICOP_S1S0_Type S1S0; /**< \brief Offset: 0x0A0 (R/W 32) System Regs 1 to 0: SR */
+ __IO PICOP_S3S2_Type S3S2; /**< \brief Offset: 0x0A4 (R/W 32) System Regs 3 to 2: CTRL */
+ __IO PICOP_S5S4_Type S5S4; /**< \brief Offset: 0x0A8 (R/W 32) System Regs 5 to 4: SREG, CCR */
+ RoReg8 Reserved4[0x8];
+ __IO PICOP_S11S10_Type S11S10; /**< \brief Offset: 0x0B4 (R/W 32) System Regs 11 to 10: Immediate */
+ __IO PICOP_LINK_Type LINK; /**< \brief Offset: 0x0B8 (R/W 32) Link */
+ __IO PICOP_SP_Type SP; /**< \brief Offset: 0x0BC (R/W 32) Stack Pointer */
+ RoReg8 Reserved5[0x40];
+ __IO PICOP_MMUFLASH_Type MMUFLASH; /**< \brief Offset: 0x100 (R/W 32) MMU mapping for flash */
+ RoReg8 Reserved6[0x14];
+ __IO PICOP_MMU0_Type MMU0; /**< \brief Offset: 0x118 (R/W 32) MMU mapping user 0 */
+ __IO PICOP_MMU1_Type MMU1; /**< \brief Offset: 0x11C (R/W 32) MMU mapping user 1 */
+ __IO PICOP_MMUCTRL_Type MMUCTRL; /**< \brief Offset: 0x120 (R/W 32) MMU Control */
+ RoReg8 Reserved7[0x5C];
+ __IO PICOP_ICACHE_Type ICACHE; /**< \brief Offset: 0x180 (R/W 32) Instruction Cache Control */
+ __IO PICOP_ICACHELRU_Type ICACHELRU; /**< \brief Offset: 0x184 (R/W 32) Instruction Cache LRU */
+ RoReg8 Reserved8[0x78];
+ __IO PICOP_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x200 (R/W 32) QOS Control */
+} Picop;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PICOP_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/pm.h b/GPIO/ATSAME54/include/component/pm.h
new file mode 100644
index 0000000..01caf80
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/pm.h
@@ -0,0 +1,261 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PM_COMPONENT_
+#define _SAME54_PM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAME54_PM Power Manager */
+/*@{*/
+
+#define PM_U2406
+#define REV_PM 0x100
+
+/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t IORET:1; /*!< bit: 2 I/O Retention */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
+#define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
+
+#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
+#define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
+#define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
+
+/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_SLEEPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
+#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
+
+#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
+#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
+#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
+#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
+#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
+#define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
+#define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
+#define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
+#define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
+#define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
+#define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_STDBYCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
+#define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
+
+#define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */
+#define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
+#define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */
+#define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
+#define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
+#define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */
+#define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
+#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
+#define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */
+
+/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
+ uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_HIBCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
+#define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
+
+#define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */
+#define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
+#define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
+#define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */
+#define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
+#define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
+#define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */
+
+/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_BKUPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */
+#define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
+
+#define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */
+#define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
+#define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
+#define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */
+
+/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */
+ uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_PWSAKDLY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
+#define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
+
+#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */
+#define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
+#define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
+#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
+#define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
+#define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved2[0x1];
+ __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */
+ __IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */
+ __IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */
+ RoReg8 Reserved3[0x7];
+ __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PM_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/port.h b/GPIO/ATSAME54/include/component/port.h
new file mode 100644
index 0000000..486c040
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/port.h
@@ -0,0 +1,414 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PORT_COMPONENT_
+#define _SAME54_PORT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAME54_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT 0x220
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 PORT Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) PORT Data Output Value */
+#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 PORT Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 PORT Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) PORT Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 PORT Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 PORT Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) PORT Data Input Value */
+#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PID0:5; /*!< bit: 0.. 4 PORT Event Pin Identifier 0 */
+ uint32_t EVACT0:2; /*!< bit: 5.. 6 PORT Event Action 0 */
+ uint32_t PORTEI0:1; /*!< bit: 7 PORT Event Input Enable 0 */
+ uint32_t PID1:5; /*!< bit: 8..12 PORT Event Pin Identifier 1 */
+ uint32_t EVACT1:2; /*!< bit: 13..14 PORT Event Action 1 */
+ uint32_t PORTEI1:1; /*!< bit: 15 PORT Event Input Enable 1 */
+ uint32_t PID2:5; /*!< bit: 16..20 PORT Event Pin Identifier 2 */
+ uint32_t EVACT2:2; /*!< bit: 21..22 PORT Event Action 2 */
+ uint32_t PORTEI2:1; /*!< bit: 23 PORT Event Input Enable 2 */
+ uint32_t PID3:5; /*!< bit: 24..28 PORT Event Pin Identifier 3 */
+ uint32_t EVACT3:2; /*!< bit: 29..30 PORT Event Action 3 */
+ uint32_t PORTEI3:1; /*!< bit: 31 PORT Event Input Enable 3 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */
+#define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
+
+#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */
+#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
+#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
+#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) PORT Event Action 0 */
+#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
+#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */
+#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */
+#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
+#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
+#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */
+#define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
+#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */
+#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
+#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
+#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) PORT Event Action 1 */
+#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
+#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
+#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */
+#define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
+#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */
+#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
+#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
+#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) PORT Event Action 2 */
+#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
+#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
+#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */
+#define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
+#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */
+#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
+#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
+#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) PORT Event Action 3 */
+#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
+#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
+#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */
+#define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
+#define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */
+#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */
+
+#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
+#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
+#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration */
+#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration */
+
+#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration */
+ RoReg8 Reserved1[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ PortGroup Group[4]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_PORT_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/qspi.h b/GPIO/ATSAME54/include/component/qspi.h
new file mode 100644
index 0000000..d7ae426
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/qspi.h
@@ -0,0 +1,528 @@
+/**
+ * \file
+ *
+ * \brief Component description for QSPI
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_QSPI_COMPONENT_
+#define _SAME54_QSPI_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR QSPI */
+/* ========================================================================== */
+/** \addtogroup SAME54_QSPI Quad SPI interface */
+/*@{*/
+
+#define QSPI_U2008
+#define REV_QSPI 0x163
+
+/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :22; /*!< bit: 2..23 Reserved */
+ uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_CTRLA_OFFSET 0x00 /**< \brief (QSPI_CTRLA offset) Control A */
+#define QSPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
+
+#define QSPI_CTRLA_SWRST_Pos 0 /**< \brief (QSPI_CTRLA) Software Reset */
+#define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
+#define QSPI_CTRLA_ENABLE_Pos 1 /**< \brief (QSPI_CTRLA) Enable */
+#define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
+#define QSPI_CTRLA_LASTXFER_Pos 24 /**< \brief (QSPI_CTRLA) Last Transfer */
+#define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
+#define QSPI_CTRLA_MASK _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
+
+/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */
+ uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */
+ uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */
+ uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */
+ uint32_t CSMODE:2; /*!< bit: 4.. 5 Chip Select Mode */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t DATALEN:4; /*!< bit: 8..11 Data Length */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DLYBCT:8; /*!< bit: 16..23 Delay Between Consecutive Transfers */
+ uint32_t DLYCS:8; /*!< bit: 24..31 Minimum Inactive CS Delay */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_CTRLB_OFFSET 0x04 /**< \brief (QSPI_CTRLB offset) Control B */
+#define QSPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
+
+#define QSPI_CTRLB_MODE_Pos 0 /**< \brief (QSPI_CTRLB) Serial Memory Mode */
+#define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) /**< \brief (QSPI_CTRLB) SPI operating mode */
+#define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
+#define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_LOOPEN_Pos 1 /**< \brief (QSPI_CTRLB) Local Loopback Enable */
+#define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
+#define QSPI_CTRLB_WDRBT_Pos 2 /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
+#define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
+#define QSPI_CTRLB_SMEMREG_Pos 3 /**< \brief (QSPI_CTRLB) Serial Memory reg */
+#define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
+#define QSPI_CTRLB_CSMODE_Pos 4 /**< \brief (QSPI_CTRLB) Chip Select Mode */
+#define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
+#define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
+#define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
+#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
+#define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_DATALEN_Pos 8 /**< \brief (QSPI_CTRLB) Data Length */
+#define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
+#define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) /**< \brief (QSPI_CTRLB) 8-bits transfer */
+#define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) /**< \brief (QSPI_CTRLB) 9 bits transfer */
+#define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) /**< \brief (QSPI_CTRLB) 10-bits transfer */
+#define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) /**< \brief (QSPI_CTRLB) 11-bits transfer */
+#define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) /**< \brief (QSPI_CTRLB) 12-bits transfer */
+#define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) /**< \brief (QSPI_CTRLB) 13-bits transfer */
+#define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) /**< \brief (QSPI_CTRLB) 14-bits transfer */
+#define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) /**< \brief (QSPI_CTRLB) 15-bits transfer */
+#define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) /**< \brief (QSPI_CTRLB) 16-bits transfer */
+#define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DLYBCT_Pos 16 /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
+#define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
+#define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
+#define QSPI_CTRLB_DLYCS_Pos 24 /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
+#define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
+#define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
+#define QSPI_CTRLB_MASK _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
+
+/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CPOL:1; /*!< bit: 0 Clock Polarity */
+ uint32_t CPHA:1; /*!< bit: 1 Clock Phase */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t BAUD:8; /*!< bit: 8..15 Serial Clock Baud Rate */
+ uint32_t DLYBS:8; /*!< bit: 16..23 Delay Before SCK */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_BAUD_OFFSET 0x08 /**< \brief (QSPI_BAUD offset) Baud Rate */
+#define QSPI_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
+
+#define QSPI_BAUD_CPOL_Pos 0 /**< \brief (QSPI_BAUD) Clock Polarity */
+#define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
+#define QSPI_BAUD_CPHA_Pos 1 /**< \brief (QSPI_BAUD) Clock Phase */
+#define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
+#define QSPI_BAUD_BAUD_Pos 8 /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
+#define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
+#define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
+#define QSPI_BAUD_DLYBS_Pos 16 /**< \brief (QSPI_BAUD) Delay Before SCK */
+#define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
+#define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
+#define QSPI_BAUD_MASK _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
+
+/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:16; /*!< bit: 0..15 Receive Data */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_RXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_RXDATA_OFFSET 0x0C /**< \brief (QSPI_RXDATA offset) Receive Data */
+#define QSPI_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
+
+#define QSPI_RXDATA_DATA_Pos 0 /**< \brief (QSPI_RXDATA) Receive Data */
+#define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
+#define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
+#define QSPI_RXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
+
+/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:16; /*!< bit: 0..15 Transmit Data */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_TXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_TXDATA_OFFSET 0x10 /**< \brief (QSPI_TXDATA offset) Transmit Data */
+#define QSPI_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
+
+#define QSPI_TXDATA_DATA_Pos 0 /**< \brief (QSPI_TXDATA) Transmit Data */
+#define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
+#define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
+#define QSPI_TXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
+
+/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Disable */
+ uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Disable */
+ uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Disable */
+ uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Disable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Disable */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Disable */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTENCLR_OFFSET 0x14 /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
+#define QSPI_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define QSPI_INTENCLR_RXC_Pos 0 /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
+#define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
+#define QSPI_INTENCLR_DRE_Pos 1 /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
+#define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
+#define QSPI_INTENCLR_TXC_Pos 2 /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
+#define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
+#define QSPI_INTENCLR_ERROR_Pos 3 /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
+#define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
+#define QSPI_INTENCLR_CSRISE_Pos 8 /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
+#define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
+#define QSPI_INTENCLR_INSTREND_Pos 10 /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
+#define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
+#define QSPI_INTENCLR_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
+
+/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Enable */
+ uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Enable */
+ uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Enable */
+ uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Enable */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Enable */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Enable */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTENSET_OFFSET 0x18 /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
+#define QSPI_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
+
+#define QSPI_INTENSET_RXC_Pos 0 /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
+#define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
+#define QSPI_INTENSET_DRE_Pos 1 /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
+#define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
+#define QSPI_INTENSET_TXC_Pos 2 /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
+#define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
+#define QSPI_INTENSET_ERROR_Pos 3 /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
+#define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
+#define QSPI_INTENSET_CSRISE_Pos 8 /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
+#define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
+#define QSPI_INTENSET_INSTREND_Pos 10 /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
+#define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
+#define QSPI_INTENSET_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
+
+/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */
+ __I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */
+ __I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */
+ __I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */
+ __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ __I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */
+ __I uint32_t :1; /*!< bit: 9 Reserved */
+ __I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */
+ __I uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTFLAG_OFFSET 0x1C /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
+#define QSPI_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define QSPI_INTFLAG_RXC_Pos 0 /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
+#define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
+#define QSPI_INTFLAG_DRE_Pos 1 /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
+#define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
+#define QSPI_INTFLAG_TXC_Pos 2 /**< \brief (QSPI_INTFLAG) Transmission Complete */
+#define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
+#define QSPI_INTFLAG_ERROR_Pos 3 /**< \brief (QSPI_INTFLAG) Overrun Error */
+#define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
+#define QSPI_INTFLAG_CSRISE_Pos 8 /**< \brief (QSPI_INTFLAG) Chip Select Rise */
+#define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
+#define QSPI_INTFLAG_INSTREND_Pos 10 /**< \brief (QSPI_INTFLAG) Instruction End */
+#define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
+#define QSPI_INTFLAG_MASK _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
+
+/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :7; /*!< bit: 2.. 8 Reserved */
+ uint32_t CSSTATUS:1; /*!< bit: 9 Chip Select */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_STATUS_OFFSET 0x20 /**< \brief (QSPI_STATUS offset) Status Register */
+#define QSPI_STATUS_RESETVALUE _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
+
+#define QSPI_STATUS_ENABLE_Pos 1 /**< \brief (QSPI_STATUS) Enable */
+#define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
+#define QSPI_STATUS_CSSTATUS_Pos 9 /**< \brief (QSPI_STATUS) Chip Select */
+#define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
+#define QSPI_STATUS_MASK _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
+
+/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Instruction Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INSTRADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRADDR_OFFSET 0x30 /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
+#define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
+
+#define QSPI_INSTRADDR_ADDR_Pos 0 /**< \brief (QSPI_INSTRADDR) Instruction Address */
+#define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
+#define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
+#define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
+
+/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t INSTR:8; /*!< bit: 0.. 7 Instruction Code */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t OPTCODE:8; /*!< bit: 16..23 Option Code */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INSTRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRCTRL_OFFSET 0x34 /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
+#define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
+
+#define QSPI_INSTRCTRL_INSTR_Pos 0 /**< \brief (QSPI_INSTRCTRL) Instruction Code */
+#define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
+#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
+#define QSPI_INSTRCTRL_OPTCODE_Pos 16 /**< \brief (QSPI_INSTRCTRL) Option Code */
+#define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
+#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
+#define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
+
+/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WIDTH:3; /*!< bit: 0.. 2 Instruction Code, Address, Option Code and Data Width */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t INSTREN:1; /*!< bit: 4 Instruction Enable */
+ uint32_t ADDREN:1; /*!< bit: 5 Address Enable */
+ uint32_t OPTCODEEN:1; /*!< bit: 6 Option Enable */
+ uint32_t DATAEN:1; /*!< bit: 7 Data Enable */
+ uint32_t OPTCODELEN:2; /*!< bit: 8.. 9 Option Code Length */
+ uint32_t ADDRLEN:1; /*!< bit: 10 Address Length */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TFRTYPE:2; /*!< bit: 12..13 Data Transfer Type */
+ uint32_t CRMODE:1; /*!< bit: 14 Continuous Read Mode */
+ uint32_t DDREN:1; /*!< bit: 15 Double Data Rate Enable */
+ uint32_t DUMMYLEN:5; /*!< bit: 16..20 Dummy Cycles Length */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_INSTRFRAME_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRFRAME_OFFSET 0x38 /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
+#define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
+
+#define QSPI_INSTRFRAME_WIDTH_Pos 0 /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
+#define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
+#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
+#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
+#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_INSTREN_Pos 4 /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
+#define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
+#define QSPI_INSTRFRAME_ADDREN_Pos 5 /**< \brief (QSPI_INSTRFRAME) Address Enable */
+#define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
+#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6 /**< \brief (QSPI_INSTRFRAME) Option Enable */
+#define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
+#define QSPI_INSTRFRAME_DATAEN_Pos 7 /**< \brief (QSPI_INSTRFRAME) Data Enable */
+#define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8 /**< \brief (QSPI_INSTRFRAME) Option Code Length */
+#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
+#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_Pos 10 /**< \brief (QSPI_INSTRFRAME) Address Length */
+#define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
+#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
+#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_Pos 12 /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
+#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
+#define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
+#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
+#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
+#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
+#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_CRMODE_Pos 14 /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
+#define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
+#define QSPI_INSTRFRAME_DDREN_Pos 15 /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
+#define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
+#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16 /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
+#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
+#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
+#define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
+
+/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Scrambling/Unscrambling Enable */
+ uint32_t RANDOMDIS:1; /*!< bit: 1 Scrambling/Unscrambling Random Value Disable */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_SCRAMBCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_SCRAMBCTRL_OFFSET 0x40 /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
+#define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
+
+#define QSPI_SCRAMBCTRL_ENABLE_Pos 0 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
+#define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
+#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
+#define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
+#define QSPI_SCRAMBCTRL_MASK _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
+
+/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t KEY:32; /*!< bit: 0..31 Scrambling User Key */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} QSPI_SCRAMBKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_SCRAMBKEY_OFFSET 0x44 /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
+#define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
+
+#define QSPI_SCRAMBKEY_KEY_Pos 0 /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
+#define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
+#define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
+#define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
+
+/** \brief QSPI APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO QSPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO QSPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO QSPI_BAUD_Type BAUD; /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
+ __I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */
+ __O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
+ __IO QSPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
+ __IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
+ __IO QSPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
+ __I QSPI_STATUS_Type STATUS; /**< \brief Offset: 0x20 (R/ 32) Status Register */
+ RoReg8 Reserved1[0xC];
+ __IO QSPI_INSTRADDR_Type INSTRADDR; /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
+ __IO QSPI_INSTRCTRL_Type INSTRCTRL; /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
+ __IO QSPI_INSTRFRAME_Type INSTRFRAME; /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
+ RoReg8 Reserved2[0x4];
+ __IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL; /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
+ __O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
+} Qspi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_QSPI_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/ramecc.h b/GPIO/ATSAME54/include/component/ramecc.h
new file mode 100644
index 0000000..943683f
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/ramecc.h
@@ -0,0 +1,178 @@
+/**
+ * \file
+ *
+ * \brief Component description for RAMECC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RAMECC_COMPONENT_
+#define _SAME54_RAMECC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RAMECC */
+/* ========================================================================== */
+/** \addtogroup SAME54_RAMECC RAM ECC */
+/*@{*/
+
+#define RAMECC_U2268
+#define REV_RAMECC 0x100
+
+/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */
+ uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
+#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
+#define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
+#define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
+#define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
+#define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */
+
+/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */
+ uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
+#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
+
+#define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
+#define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
+#define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
+#define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
+#define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */
+
+/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
+ __I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
+#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
+
+#define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
+#define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
+#define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
+#define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
+#define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */
+
+/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */
+#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */
+
+#define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */
+#define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
+#define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */
+
+/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RAMECC_ERRADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */
+#define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
+
+#define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */
+#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
+#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
+#define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
+
+/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
+ uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RAMECC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
+#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
+
+#define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */
+#define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
+#define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
+#define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
+#define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */
+
+/** \brief RAMECC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */
+ __IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */
+ __IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */
+ __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
+ __I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
+ RoReg8 Reserved1[0x7];
+ __IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */
+} Ramecc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_RAMECC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/rstc.h b/GPIO/ATSAME54/include/component/rstc.h
new file mode 100644
index 0000000..5dd8d23
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/rstc.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Component description for RSTC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RSTC_COMPONENT_
+#define _SAME54_RSTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RSTC */
+/* ========================================================================== */
+/** \addtogroup SAME54_RSTC Reset Controller */
+/*@{*/
+
+#define RSTC_U2239
+#define REV_RSTC 0x400
+
+/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
+ uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
+ uint8_t NVM:1; /*!< bit: 3 NVM Reset */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RSTC_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
+
+#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
+#define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
+#define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
+#define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
+#define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
+#define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
+#define RSTC_RCAUSE_NVM_Pos 3 /**< \brief (RSTC_RCAUSE) NVM Reset */
+#define RSTC_RCAUSE_NVM (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
+#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
+#define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
+#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
+#define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
+#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
+#define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
+#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */
+#define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
+#define RSTC_RCAUSE_MASK _U_(0xFF) /**< \brief (RSTC_RCAUSE) MASK Register */
+
+/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */
+ uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t HIB:1; /*!< bit: 7 Hibernate */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RSTC_BKUPEXIT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
+#define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
+
+#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
+#define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
+#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
+#define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
+#define RSTC_BKUPEXIT_HIB_Pos 7 /**< \brief (RSTC_BKUPEXIT) Hibernate */
+#define RSTC_BKUPEXIT_HIB (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
+#define RSTC_BKUPEXIT_MASK _U_(0x86) /**< \brief (RSTC_BKUPEXIT) MASK Register */
+
+/** \brief RSTC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
+ RoReg8 Reserved1[0x1];
+ __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_RSTC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/rtc.h b/GPIO/ATSAME54/include/component/rtc.h
new file mode 100644
index 0000000..e5f8ce8
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/rtc.h
@@ -0,0 +1,2098 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RTC_COMPONENT_
+#define _SAME54_RTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAME54_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2250
+#define REV_RTC 0x210
+
+/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
+ uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
+ uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */
+#define RTC_MODE0_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */
+
+#define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */
+#define RTC_MODE0_CTRLA_SWRST (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)
+#define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */
+#define RTC_MODE0_CTRLA_ENABLE (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)
+#define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */
+#define RTC_MODE0_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
+#define RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */
+#define RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */
+#define RTC_MODE0_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */
+#define RTC_MODE0_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */
+#define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
+#define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE0_CTRLA_BKTRST (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)
+#define RTC_MODE0_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE0_CTRLA_GPTRST (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)
+#define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */
+#define RTC_MODE0_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
+#define RTC_MODE0_CTRLA_MASK _U_(0xEF8F) /**< \brief (RTC_MODE0_CTRLA) MASK Register */
+
+/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
+ uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
+ uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */
+#define RTC_MODE1_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */
+
+#define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */
+#define RTC_MODE1_CTRLA_SWRST (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)
+#define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */
+#define RTC_MODE1_CTRLA_ENABLE (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)
+#define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */
+#define RTC_MODE1_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
+#define RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */
+#define RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */
+#define RTC_MODE1_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */
+#define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
+#define RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE1_CTRLA_BKTRST (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)
+#define RTC_MODE1_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE1_CTRLA_GPTRST (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)
+#define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */
+#define RTC_MODE1_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)
+#define RTC_MODE1_CTRLA_MASK _U_(0xEF0F) /**< \brief (RTC_MODE1_CTRLA) MASK Register */
+
+/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :1; /*!< bit: 12 Reserved */
+ uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
+ uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
+ uint16_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */
+#define RTC_MODE2_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */
+
+#define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */
+#define RTC_MODE2_CTRLA_SWRST (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)
+#define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */
+#define RTC_MODE2_CTRLA_ENABLE (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)
+#define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */
+#define RTC_MODE2_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
+#define RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */
+#define RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */
+#define RTC_MODE2_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */
+#define RTC_MODE2_CTRLA_CLKREP (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)
+#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */
+#define RTC_MODE2_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */
+#define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
+#define RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE2_CTRLA_BKTRST (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)
+#define RTC_MODE2_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE2_CTRLA_GPTRST (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)
+#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */
+#define RTC_MODE2_CTRLA_CLOCKSYNC (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)
+#define RTC_MODE2_CTRLA_MASK _U_(0xEFCF) /**< \brief (RTC_MODE2_CTRLA) MASK Register */
+
+/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
+ uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
+ uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
+ uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
+ uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
+ uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE0_CTRLB offset) MODE0 Control B */
+#define RTC_MODE0_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLB reset_value) MODE0 Control B */
+
+#define RTC_MODE0_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE0_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE0_CTRLB_GP0EN (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)
+#define RTC_MODE0_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE0_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE0_CTRLB_GP2EN (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)
+#define RTC_MODE0_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE0_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE0_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE0_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE0_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE0_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE0_CTRLB) RTC Output Enable */
+#define RTC_MODE0_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)
+#define RTC_MODE0_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE0_CTRLB) DMA Enable */
+#define RTC_MODE0_CTRLB_DMAEN (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)
+#define RTC_MODE0_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE0_CTRLB) Debounce Freqnuency */
+#define RTC_MODE0_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
+#define RTC_MODE0_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define RTC_MODE0_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define RTC_MODE0_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define RTC_MODE0_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define RTC_MODE0_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define RTC_MODE0_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE0_CTRLB_DEBF_DIV2 (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV4 (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV8 (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV16 (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV32 (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV64 (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE0_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE0_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
+#define RTC_MODE0_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define RTC_MODE0_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define RTC_MODE0_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define RTC_MODE0_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define RTC_MODE0_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define RTC_MODE0_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE0_CTRLB_ACTF_DIV2 (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV4 (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV8 (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV16 (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV32 (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV64 (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE0_CTRLB) MASK Register */
+
+/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
+ uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
+ uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
+ uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
+ uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
+ uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE1_CTRLB offset) MODE1 Control B */
+#define RTC_MODE1_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLB reset_value) MODE1 Control B */
+
+#define RTC_MODE1_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE1_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE1_CTRLB_GP0EN (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)
+#define RTC_MODE1_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE1_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE1_CTRLB_GP2EN (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)
+#define RTC_MODE1_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE1_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE1_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE1_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE1_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE1_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE1_CTRLB) RTC Output Enable */
+#define RTC_MODE1_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)
+#define RTC_MODE1_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE1_CTRLB) DMA Enable */
+#define RTC_MODE1_CTRLB_DMAEN (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)
+#define RTC_MODE1_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE1_CTRLB) Debounce Freqnuency */
+#define RTC_MODE1_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
+#define RTC_MODE1_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define RTC_MODE1_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define RTC_MODE1_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define RTC_MODE1_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define RTC_MODE1_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define RTC_MODE1_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE1_CTRLB_DEBF_DIV2 (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV4 (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV8 (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV16 (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV32 (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV64 (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE1_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE1_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
+#define RTC_MODE1_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define RTC_MODE1_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define RTC_MODE1_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define RTC_MODE1_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define RTC_MODE1_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define RTC_MODE1_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE1_CTRLB_ACTF_DIV2 (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV4 (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV8 (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV16 (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV32 (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV64 (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE1_CTRLB) MASK Register */
+
+/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
+ uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
+ uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
+ uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
+ uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
+ uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE2_CTRLB offset) MODE2 Control B */
+#define RTC_MODE2_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLB reset_value) MODE2 Control B */
+
+#define RTC_MODE2_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE2_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE2_CTRLB_GP0EN (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)
+#define RTC_MODE2_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE2_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE2_CTRLB_GP2EN (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)
+#define RTC_MODE2_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE2_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE2_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE2_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE2_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE2_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE2_CTRLB) RTC Output Enable */
+#define RTC_MODE2_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)
+#define RTC_MODE2_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE2_CTRLB) DMA Enable */
+#define RTC_MODE2_CTRLB_DMAEN (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)
+#define RTC_MODE2_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE2_CTRLB) Debounce Freqnuency */
+#define RTC_MODE2_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
+#define RTC_MODE2_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define RTC_MODE2_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define RTC_MODE2_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define RTC_MODE2_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define RTC_MODE2_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define RTC_MODE2_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE2_CTRLB_DEBF_DIV2 (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV4 (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV8 (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV16 (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV32 (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV64 (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE2_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE2_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
+#define RTC_MODE2_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define RTC_MODE2_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define RTC_MODE2_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define RTC_MODE2_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define RTC_MODE2_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define RTC_MODE2_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE2_CTRLB_ACTF_DIV2 (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV4 (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV8 (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV16 (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV32 (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV64 (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE2_CTRLB) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint32_t :4; /*!< bit: 10..13 Reserved */
+ uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
+ uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0 (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1 (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2 (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3 (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4 (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5 (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6 (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7 (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE0_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE0_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE0_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint32_t CMPEO2:1; /*!< bit: 10 Compare 2 Event Output Enable */
+ uint32_t CMPEO3:1; /*!< bit: 11 Compare 3 Event Output Enable */
+ uint32_t :2; /*!< bit: 12..13 Reserved */
+ uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
+ uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint32_t CMPEO:4; /*!< bit: 8..11 Compare x Event Output Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0 (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1 (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2 (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3 (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4 (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5 (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6 (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7 (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO2_Pos 10 /**< \brief (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO2 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO3_Pos 11 /**< \brief (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO3 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE1_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE1_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE1_EVCTRL_MASK _U_(0x0001CFFF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint32_t ALARMEO1:1; /*!< bit: 9 Alarm 1 Event Output Enable */
+ uint32_t :4; /*!< bit: 10..13 Reserved */
+ uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
+ uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
+ uint32_t :15; /*!< bit: 17..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint32_t ALARMEO:2; /*!< bit: 8.. 9 Alarm x Event Output Enable */
+ uint32_t :22; /*!< bit: 10..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0 (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1 (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2 (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3 (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4 (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5 (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6 (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7 (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9 /**< \brief (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO1 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE2_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE2_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE2_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER0 (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)
+#define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER1 (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)
+#define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER2 (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)
+#define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER3 (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)
+#define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER4 (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)
+#define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER5 (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)
+#define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER6 (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)
+#define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER7 (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)
+#define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)
+#define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))
+#define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0 (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP1 (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENCLR) Tamper Enable */
+#define RTC_MODE0_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
+ uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER0 (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)
+#define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER1 (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)
+#define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER2 (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)
+#define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER3 (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)
+#define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER4 (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)
+#define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER5 (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)
+#define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER6 (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)
+#define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER7 (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)
+#define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)
+#define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))
+#define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0 (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1 (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP2 (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)
+#define RTC_MODE1_INTENCLR_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP3 (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENCLR) Tamper Enable */
+#define RTC_MODE1_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
+ uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER0 (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)
+#define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER1 (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)
+#define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER2 (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)
+#define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER3 (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)
+#define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER4 (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)
+#define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER5 (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)
+#define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER6 (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)
+#define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER7 (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)
+#define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)
+#define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0 (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM1 (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENCLR) Tamper Enable */
+#define RTC_MODE2_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER0 (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)
+#define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER1 (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)
+#define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER2 (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)
+#define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER3 (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)
+#define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER4 (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)
+#define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER5 (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)
+#define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER6 (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)
+#define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER7 (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)
+#define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)
+#define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))
+#define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0 (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP1 (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENSET) Tamper Enable */
+#define RTC_MODE0_INTENSET_TAMPER (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
+ uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
+ uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
+ uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
+ uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
+ uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER0 (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)
+#define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER1 (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)
+#define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER2 (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)
+#define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER3 (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)
+#define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER4 (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)
+#define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER5 (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)
+#define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER6 (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)
+#define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER7 (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)
+#define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)
+#define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))
+#define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0 (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1 (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP2 (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)
+#define RTC_MODE1_INTENSET_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP3 (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENSET) Tamper Enable */
+#define RTC_MODE1_INTENSET_TAMPER (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */
+ uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */
+ uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */
+ uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */
+ uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */
+ uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */
+ uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */
+ uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */
+ uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
+ uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
+ uint16_t :4; /*!< bit: 10..13 Reserved */
+ uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
+ uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */
+ uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */
+#define RTC_MODE2_INTENSET_PER0 (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)
+#define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */
+#define RTC_MODE2_INTENSET_PER1 (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)
+#define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */
+#define RTC_MODE2_INTENSET_PER2 (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)
+#define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */
+#define RTC_MODE2_INTENSET_PER3 (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)
+#define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */
+#define RTC_MODE2_INTENSET_PER4 (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)
+#define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */
+#define RTC_MODE2_INTENSET_PER5 (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)
+#define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */
+#define RTC_MODE2_INTENSET_PER6 (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)
+#define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */
+#define RTC_MODE2_INTENSET_PER7 (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)
+#define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */
+#define RTC_MODE2_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)
+#define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))
+#define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0 (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM1 (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENSET) Tamper Enable */
+#define RTC_MODE2_INTENSET_TAMPER (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
+ __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
+ __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
+ __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
+ __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
+ __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
+ __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
+ __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
+ __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
+ __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
+ __I uint16_t :4; /*!< bit: 10..13 Reserved */
+ __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
+ __I uint16_t OVF:1; /*!< bit: 15 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
+ __I uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE0_INTFLAG_PER0 (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)
+#define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE0_INTFLAG_PER1 (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)
+#define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE0_INTFLAG_PER2 (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)
+#define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE0_INTFLAG_PER3 (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)
+#define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE0_INTFLAG_PER4 (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)
+#define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE0_INTFLAG_PER5 (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)
+#define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE0_INTFLAG_PER6 (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)
+#define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE0_INTFLAG_PER7 (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)
+#define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */
+#define RTC_MODE0_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)
+#define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))
+#define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0 (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTFLAG) Compare 1 */
+#define RTC_MODE0_INTFLAG_CMP1 (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTFLAG) Tamper */
+#define RTC_MODE0_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
+ __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
+ __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
+ __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
+ __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
+ __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
+ __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
+ __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
+ __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
+ __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
+ __I uint16_t CMP2:1; /*!< bit: 10 Compare 2 */
+ __I uint16_t CMP3:1; /*!< bit: 11 Compare 3 */
+ __I uint16_t :2; /*!< bit: 12..13 Reserved */
+ __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
+ __I uint16_t OVF:1; /*!< bit: 15 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
+ __I uint16_t CMP:4; /*!< bit: 8..11 Compare x */
+ __I uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE1_INTFLAG_PER0 (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)
+#define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE1_INTFLAG_PER1 (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)
+#define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE1_INTFLAG_PER2 (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)
+#define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE1_INTFLAG_PER3 (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)
+#define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE1_INTFLAG_PER4 (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)
+#define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE1_INTFLAG_PER5 (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)
+#define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE1_INTFLAG_PER6 (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)
+#define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE1_INTFLAG_PER7 (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)
+#define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */
+#define RTC_MODE1_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)
+#define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))
+#define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0 (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1 (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTFLAG) Compare 2 */
+#define RTC_MODE1_INTFLAG_CMP2 (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)
+#define RTC_MODE1_INTFLAG_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTFLAG) Compare 3 */
+#define RTC_MODE1_INTFLAG_CMP3 (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTFLAG) Tamper */
+#define RTC_MODE1_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
+ __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
+ __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
+ __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
+ __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
+ __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
+ __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
+ __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
+ __I uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */
+ __I uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 */
+ __I uint16_t :4; /*!< bit: 10..13 Reserved */
+ __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
+ __I uint16_t OVF:1; /*!< bit: 15 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
+ __I uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE2_INTFLAG_PER0 (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)
+#define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE2_INTFLAG_PER1 (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)
+#define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE2_INTFLAG_PER2 (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)
+#define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE2_INTFLAG_PER3 (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)
+#define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE2_INTFLAG_PER4 (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)
+#define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE2_INTFLAG_PER5 (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)
+#define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE2_INTFLAG_PER6 (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)
+#define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE2_INTFLAG_PER7 (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)
+#define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */
+#define RTC_MODE2_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)
+#define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0 (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTFLAG) Alarm 1 */
+#define RTC_MODE2_INTFLAG_ALARM1 (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTFLAG) Tamper */
+#define RTC_MODE2_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK _U_(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
+ uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
+ uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
+ uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
+ uint32_t :8; /*!< bit: 7..14 Reserved */
+ uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
+ uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
+ uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
+ uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
+ uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */
+ uint32_t :9; /*!< bit: 7..15 Reserved */
+ uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */
+#define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */
+
+#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */
+#define RTC_MODE0_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE0_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */
+#define RTC_MODE0_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy */
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)
+#define RTC_MODE0_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP0 (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)
+#define RTC_MODE0_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP1 (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)
+#define RTC_MODE0_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP2 (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)
+#define RTC_MODE0_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP3 (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)
+#define RTC_MODE0_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)
+#define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))
+#define RTC_MODE0_SYNCBUSY_MASK _U_(0x000F806F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */
+
+/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
+ uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
+ uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
+ uint32_t PER:1; /*!< bit: 4 PER Register Busy */
+ uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
+ uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
+ uint32_t COMP2:1; /*!< bit: 7 COMP 2 Register Busy */
+ uint32_t COMP3:1; /*!< bit: 8 COMP 3 Register Busy */
+ uint32_t :6; /*!< bit: 9..14 Reserved */
+ uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
+ uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
+ uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
+ uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
+ uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COMP:4; /*!< bit: 5.. 8 COMP x Register Busy */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE1_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */
+#define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */
+
+#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */
+#define RTC_MODE1_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE1_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */
+#define RTC_MODE1_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)
+#define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */
+#define RTC_MODE1_SYNCBUSY_PER (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP2_Pos 7 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP2 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP3_Pos 8 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP3 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy */
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)
+#define RTC_MODE1_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP0 (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)
+#define RTC_MODE1_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP1 (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)
+#define RTC_MODE1_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP2 (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)
+#define RTC_MODE1_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP3 (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)
+#define RTC_MODE1_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)
+#define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))
+#define RTC_MODE1_SYNCBUSY_MASK _U_(0x000F81FF) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */
+
+/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
+ uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
+ uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */
+ uint32_t ALARM1:1; /*!< bit: 6 ALARM 1 Register Busy */
+ uint32_t :4; /*!< bit: 7..10 Reserved */
+ uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */
+ uint32_t MASK1:1; /*!< bit: 12 MASK 1 Register Busy */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t CLOCKSYNC:1; /*!< bit: 15 Clock Synchronization Enable Bit Busy */
+ uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
+ uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
+ uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
+ uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t ALARM:2; /*!< bit: 5.. 6 ALARM x Register Busy */
+ uint32_t :4; /*!< bit: 7..10 Reserved */
+ uint32_t MASK:2; /*!< bit: 11..12 MASK x Register Busy */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */
+#define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */
+
+#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */
+#define RTC_MODE2_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE2_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */
+#define RTC_MODE2_SYNCBUSY_CLOCK (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM0 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM1 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))
+#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK0 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK1_Pos 12 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK1 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy */
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)
+#define RTC_MODE2_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP0 (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)
+#define RTC_MODE2_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP1 (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)
+#define RTC_MODE2_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP2 (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)
+#define RTC_MODE2_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP3 (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)
+#define RTC_MODE2_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)
+#define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))
+#define RTC_MODE2_SYNCBUSY_MASK_ _U_(0x000F986F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE _U_(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK _U_(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */
+#define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
+#define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GP:32; /*!< bit: 0..31 General Purpose */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_GP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */
+#define RTC_GP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */
+
+#define RTC_GP_GP_Pos 0 /**< \brief (RTC_GP) General Purpose */
+#define RTC_GP_GP_Msk (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)
+#define RTC_GP_GP(value) (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))
+#define RTC_GP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */
+
+/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN0ACT:2; /*!< bit: 0.. 1 Tamper Input 0 Action */
+ uint32_t IN1ACT:2; /*!< bit: 2.. 3 Tamper Input 1 Action */
+ uint32_t IN2ACT:2; /*!< bit: 4.. 5 Tamper Input 2 Action */
+ uint32_t IN3ACT:2; /*!< bit: 6.. 7 Tamper Input 3 Action */
+ uint32_t IN4ACT:2; /*!< bit: 8.. 9 Tamper Input 4 Action */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t TAMLVL0:1; /*!< bit: 16 Tamper Level Select 0 */
+ uint32_t TAMLVL1:1; /*!< bit: 17 Tamper Level Select 1 */
+ uint32_t TAMLVL2:1; /*!< bit: 18 Tamper Level Select 2 */
+ uint32_t TAMLVL3:1; /*!< bit: 19 Tamper Level Select 3 */
+ uint32_t TAMLVL4:1; /*!< bit: 20 Tamper Level Select 4 */
+ uint32_t :3; /*!< bit: 21..23 Reserved */
+ uint32_t DEBNC0:1; /*!< bit: 24 Debouncer Enable 0 */
+ uint32_t DEBNC1:1; /*!< bit: 25 Debouncer Enable 1 */
+ uint32_t DEBNC2:1; /*!< bit: 26 Debouncer Enable 2 */
+ uint32_t DEBNC3:1; /*!< bit: 27 Debouncer Enable 3 */
+ uint32_t DEBNC4:1; /*!< bit: 28 Debouncer Enable 4 */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t TAMLVL:5; /*!< bit: 16..20 Tamper Level Select x */
+ uint32_t :3; /*!< bit: 21..23 Reserved */
+ uint32_t DEBNC:5; /*!< bit: 24..28 Debouncer Enable x */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_TAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_TAMPCTRL_OFFSET 0x60 /**< \brief (RTC_TAMPCTRL offset) Tamper Control */
+#define RTC_TAMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPCTRL reset_value) Tamper Control */
+
+#define RTC_TAMPCTRL_IN0ACT_Pos 0 /**< \brief (RTC_TAMPCTRL) Tamper Input 0 Action */
+#define RTC_TAMPCTRL_IN0ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT(value) (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
+#define RTC_TAMPCTRL_IN0ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN0ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN0ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN0 to OUT */
+#define RTC_TAMPCTRL_IN0ACT_OFF (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_WAKE (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_ACTL (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_Pos 2 /**< \brief (RTC_TAMPCTRL) Tamper Input 1 Action */
+#define RTC_TAMPCTRL_IN1ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT(value) (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
+#define RTC_TAMPCTRL_IN1ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN1ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN1ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN1 to OUT */
+#define RTC_TAMPCTRL_IN1ACT_OFF (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_WAKE (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_ACTL (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_Pos 4 /**< \brief (RTC_TAMPCTRL) Tamper Input 2 Action */
+#define RTC_TAMPCTRL_IN2ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT(value) (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
+#define RTC_TAMPCTRL_IN2ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN2ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN2ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN2 to OUT */
+#define RTC_TAMPCTRL_IN2ACT_OFF (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_WAKE (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_ACTL (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_Pos 6 /**< \brief (RTC_TAMPCTRL) Tamper Input 3 Action */
+#define RTC_TAMPCTRL_IN3ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT(value) (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
+#define RTC_TAMPCTRL_IN3ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN3ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN3ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN3 to OUT */
+#define RTC_TAMPCTRL_IN3ACT_OFF (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_WAKE (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_ACTL (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_Pos 8 /**< \brief (RTC_TAMPCTRL) Tamper Input 4 Action */
+#define RTC_TAMPCTRL_IN4ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT(value) (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))
+#define RTC_TAMPCTRL_IN4ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define RTC_TAMPCTRL_IN4ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define RTC_TAMPCTRL_IN4ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN4 to OUT */
+#define RTC_TAMPCTRL_IN4ACT_OFF (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_WAKE (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_ACTL (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_TAMLVL0_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 0 */
+#define RTC_TAMPCTRL_TAMLVL0 (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)
+#define RTC_TAMPCTRL_TAMLVL1_Pos 17 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 1 */
+#define RTC_TAMPCTRL_TAMLVL1 (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)
+#define RTC_TAMPCTRL_TAMLVL2_Pos 18 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 2 */
+#define RTC_TAMPCTRL_TAMLVL2 (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)
+#define RTC_TAMPCTRL_TAMLVL3_Pos 19 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 3 */
+#define RTC_TAMPCTRL_TAMLVL3 (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)
+#define RTC_TAMPCTRL_TAMLVL4_Pos 20 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 4 */
+#define RTC_TAMPCTRL_TAMLVL4 (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)
+#define RTC_TAMPCTRL_TAMLVL_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select x */
+#define RTC_TAMPCTRL_TAMLVL_Msk (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)
+#define RTC_TAMPCTRL_TAMLVL(value) (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))
+#define RTC_TAMPCTRL_DEBNC0_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 0 */
+#define RTC_TAMPCTRL_DEBNC0 (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)
+#define RTC_TAMPCTRL_DEBNC1_Pos 25 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 1 */
+#define RTC_TAMPCTRL_DEBNC1 (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)
+#define RTC_TAMPCTRL_DEBNC2_Pos 26 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 2 */
+#define RTC_TAMPCTRL_DEBNC2 (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)
+#define RTC_TAMPCTRL_DEBNC3_Pos 27 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 3 */
+#define RTC_TAMPCTRL_DEBNC3 (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)
+#define RTC_TAMPCTRL_DEBNC4_Pos 28 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 4 */
+#define RTC_TAMPCTRL_DEBNC4 (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)
+#define RTC_TAMPCTRL_DEBNC_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable x */
+#define RTC_TAMPCTRL_DEBNC_Msk (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)
+#define RTC_TAMPCTRL_DEBNC(value) (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))
+#define RTC_TAMPCTRL_MASK _U_(0x1F1F03FF) /**< \brief (RTC_TAMPCTRL) MASK Register */
+
+/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE0 MODE0 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Timestamp Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp */
+#define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp */
+
+#define RTC_MODE0_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE0_TIMESTAMP) Count Timestamp Value */
+#define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)
+#define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
+#define RTC_MODE0_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_TIMESTAMP) MASK Register */
+
+/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE1 MODE1 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:16; /*!< bit: 0..15 Count Timestamp Value */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE1_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp */
+#define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp */
+
+#define RTC_MODE1_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE1_TIMESTAMP) Count Timestamp Value */
+#define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)
+#define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
+#define RTC_MODE1_TIMESTAMP_MASK _U_(0x0000FFFF) /**< \brief (RTC_MODE1_TIMESTAMP) MASK Register */
+
+/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE2 MODE2 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second Timestamp Value */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute Timestamp Value */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour Timestamp Value */
+ uint32_t DAY:5; /*!< bit: 17..21 Day Timestamp Value */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month Timestamp Value */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year Timestamp Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp */
+#define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp */
+
+#define RTC_MODE2_TIMESTAMP_SECOND_Pos 0 /**< \brief (RTC_MODE2_TIMESTAMP) Second Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)
+#define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
+#define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6 /**< \brief (RTC_MODE2_TIMESTAMP) Minute Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)
+#define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
+#define RTC_MODE2_TIMESTAMP_HOUR_Pos 12 /**< \brief (RTC_MODE2_TIMESTAMP) Hour Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
+#define RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */
+#define RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */
+#define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_DAY_Pos 17 /**< \brief (RTC_MODE2_TIMESTAMP) Day Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)
+#define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
+#define RTC_MODE2_TIMESTAMP_MONTH_Pos 22 /**< \brief (RTC_MODE2_TIMESTAMP) Month Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)
+#define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
+#define RTC_MODE2_TIMESTAMP_YEAR_Pos 26 /**< \brief (RTC_MODE2_TIMESTAMP) Year Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)
+#define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
+#define RTC_MODE2_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_TIMESTAMP) MASK Register */
+
+/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TAMPID0:1; /*!< bit: 0 Tamper Input 0 Detected */
+ uint32_t TAMPID1:1; /*!< bit: 1 Tamper Input 1 Detected */
+ uint32_t TAMPID2:1; /*!< bit: 2 Tamper Input 2 Detected */
+ uint32_t TAMPID3:1; /*!< bit: 3 Tamper Input 3 Detected */
+ uint32_t TAMPID4:1; /*!< bit: 4 Tamper Input 4 Detected */
+ uint32_t :26; /*!< bit: 5..30 Reserved */
+ uint32_t TAMPEVT:1; /*!< bit: 31 Tamper Event Detected */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t TAMPID:5; /*!< bit: 0.. 4 Tamper Input x Detected */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_TAMPID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_TAMPID_OFFSET 0x68 /**< \brief (RTC_TAMPID offset) Tamper ID */
+#define RTC_TAMPID_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPID reset_value) Tamper ID */
+
+#define RTC_TAMPID_TAMPID0_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input 0 Detected */
+#define RTC_TAMPID_TAMPID0 (_U_(1) << RTC_TAMPID_TAMPID0_Pos)
+#define RTC_TAMPID_TAMPID1_Pos 1 /**< \brief (RTC_TAMPID) Tamper Input 1 Detected */
+#define RTC_TAMPID_TAMPID1 (_U_(1) << RTC_TAMPID_TAMPID1_Pos)
+#define RTC_TAMPID_TAMPID2_Pos 2 /**< \brief (RTC_TAMPID) Tamper Input 2 Detected */
+#define RTC_TAMPID_TAMPID2 (_U_(1) << RTC_TAMPID_TAMPID2_Pos)
+#define RTC_TAMPID_TAMPID3_Pos 3 /**< \brief (RTC_TAMPID) Tamper Input 3 Detected */
+#define RTC_TAMPID_TAMPID3 (_U_(1) << RTC_TAMPID_TAMPID3_Pos)
+#define RTC_TAMPID_TAMPID4_Pos 4 /**< \brief (RTC_TAMPID) Tamper Input 4 Detected */
+#define RTC_TAMPID_TAMPID4 (_U_(1) << RTC_TAMPID_TAMPID4_Pos)
+#define RTC_TAMPID_TAMPID_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input x Detected */
+#define RTC_TAMPID_TAMPID_Msk (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)
+#define RTC_TAMPID_TAMPID(value) (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))
+#define RTC_TAMPID_TAMPEVT_Pos 31 /**< \brief (RTC_TAMPID) Tamper Event Detected */
+#define RTC_TAMPID_TAMPEVT (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)
+#define RTC_TAMPID_MASK _U_(0x8000001F) /**< \brief (RTC_TAMPID) MASK Register */
+
+/* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BKUP:32; /*!< bit: 0..31 Backup */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_BKUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_BKUP_OFFSET 0x80 /**< \brief (RTC_BKUP offset) Backup */
+#define RTC_BKUP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_BKUP reset_value) Backup */
+
+#define RTC_BKUP_BKUP_Pos 0 /**< \brief (RTC_BKUP) Backup */
+#define RTC_BKUP_BKUP_Msk (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)
+#define RTC_BKUP_BKUP(value) (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))
+#define RTC_BKUP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_BKUP) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+ __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
+ __IO RTC_MODE0_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x1];
+ __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */
+ RoReg8 Reserved4[0x18];
+ __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+ RoReg8 Reserved5[0x10];
+ __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+ __I RTC_MODE0_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE0 Timestamp */
+ __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+ RoReg8 Reserved6[0x14];
+ __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+ __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */
+ __IO RTC_MODE1_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x1];
+ __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[4]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */
+ RoReg8 Reserved5[0x18];
+ __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+ RoReg8 Reserved6[0x10];
+ __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+ __I RTC_MODE1_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE1 Timestamp */
+ __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+ RoReg8 Reserved7[0x14];
+ __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+ __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */
+ __IO RTC_MODE2_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x1];
+ __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */
+ RoReg8 Reserved4[0x10];
+ __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+ RoReg8 Reserved5[0x10];
+ __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+ __I RTC_MODE2_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE2 Timestamp */
+ __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+ RoReg8 Reserved6[0x14];
+ __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_RTC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/sdhc.h b/GPIO/ATSAME54/include/component/sdhc.h
new file mode 100644
index 0000000..dcdf2dd
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/sdhc.h
@@ -0,0 +1,2599 @@
+/**
+ * \file
+ *
+ * \brief Component description for SDHC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SDHC_COMPONENT_
+#define _SAME54_SDHC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SDHC */
+/* ========================================================================== */
+/** \addtogroup SAME54_SDHC SD/MMC Host Controller */
+/*@{*/
+
+#define SDHC_U2011
+#define REV_SDHC 0x183
+
+/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // CMD23 mode
+ uint32_t ARG2:32; /*!< bit: 0..31 Argument 2 */
+ } CMD23; /*!< Structure used for CMD23 */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 SDMA System Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_SSAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SSAR_OFFSET 0x000 /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */
+#define SDHC_SSAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */
+
+// CMD23 mode
+#define SDHC_SSAR_CMD23_ARG2_Pos 0 /**< \brief (SDHC_SSAR_CMD23) Argument 2 */
+#define SDHC_SSAR_CMD23_ARG2_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)
+#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))
+#define SDHC_SSAR_CMD23_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */
+
+#define SDHC_SSAR_ADDR_Pos 0 /**< \brief (SDHC_SSAR) SDMA System Address */
+#define SDHC_SSAR_ADDR_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)
+#define SDHC_SSAR_ADDR(value) (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))
+#define SDHC_SSAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */
+
+/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_BSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BSR_OFFSET 0x004 /**< \brief (SDHC_BSR offset) Block Size */
+#define SDHC_BSR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BSR reset_value) Block Size */
+
+#define SDHC_BSR_BLOCKSIZE_Pos 0 /**< \brief (SDHC_BSR) Transfer Block Size */
+#define SDHC_BSR_BLOCKSIZE_Msk (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)
+#define SDHC_BSR_BLOCKSIZE(value) (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))
+#define SDHC_BSR_BOUNDARY_Pos 12 /**< \brief (SDHC_BSR) SDMA Buffer Boundary */
+#define SDHC_BSR_BOUNDARY_Msk (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY(value) (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))
+#define SDHC_BSR_BOUNDARY_4K_Val _U_(0x0) /**< \brief (SDHC_BSR) 4k bytes */
+#define SDHC_BSR_BOUNDARY_8K_Val _U_(0x1) /**< \brief (SDHC_BSR) 8k bytes */
+#define SDHC_BSR_BOUNDARY_16K_Val _U_(0x2) /**< \brief (SDHC_BSR) 16k bytes */
+#define SDHC_BSR_BOUNDARY_32K_Val _U_(0x3) /**< \brief (SDHC_BSR) 32k bytes */
+#define SDHC_BSR_BOUNDARY_64K_Val _U_(0x4) /**< \brief (SDHC_BSR) 64k bytes */
+#define SDHC_BSR_BOUNDARY_128K_Val _U_(0x5) /**< \brief (SDHC_BSR) 128k bytes */
+#define SDHC_BSR_BOUNDARY_256K_Val _U_(0x6) /**< \brief (SDHC_BSR) 256k bytes */
+#define SDHC_BSR_BOUNDARY_512K_Val _U_(0x7) /**< \brief (SDHC_BSR) 512k bytes */
+#define SDHC_BSR_BOUNDARY_4K (SDHC_BSR_BOUNDARY_4K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_8K (SDHC_BSR_BOUNDARY_8K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_16K (SDHC_BSR_BOUNDARY_16K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_32K (SDHC_BSR_BOUNDARY_32K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_64K (SDHC_BSR_BOUNDARY_64K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_128K (SDHC_BSR_BOUNDARY_128K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_256K (SDHC_BSR_BOUNDARY_256K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_512K (SDHC_BSR_BOUNDARY_512K_Val << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_MASK _U_(0x73FF) /**< \brief (SDHC_BSR) MASK Register */
+
+/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_BCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BCR_OFFSET 0x006 /**< \brief (SDHC_BCR offset) Block Count */
+#define SDHC_BCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BCR reset_value) Block Count */
+
+#define SDHC_BCR_BCNT_Pos 0 /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */
+#define SDHC_BCR_BCNT_Msk (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)
+#define SDHC_BCR_BCNT(value) (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))
+#define SDHC_BCR_MASK _U_(0xFFFF) /**< \brief (SDHC_BCR) MASK Register */
+
+/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ARG:32; /*!< bit: 0..31 Argument 1 */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_ARG1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ARG1R_OFFSET 0x008 /**< \brief (SDHC_ARG1R offset) Argument 1 */
+#define SDHC_ARG1R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */
+
+#define SDHC_ARG1R_ARG_Pos 0 /**< \brief (SDHC_ARG1R) Argument 1 */
+#define SDHC_ARG1R_ARG_Msk (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)
+#define SDHC_ARG1R_ARG(value) (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))
+#define SDHC_ARG1R_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */
+
+/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */
+ uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */
+ uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */
+ uint16_t DTDSEL:1; /*!< bit: 4 Data Transfer Direction Selection */
+ uint16_t MSBSEL:1; /*!< bit: 5 Multi/Single Block Selection */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_TMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_TMR_OFFSET 0x00C /**< \brief (SDHC_TMR offset) Transfer Mode */
+#define SDHC_TMR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_TMR reset_value) Transfer Mode */
+
+#define SDHC_TMR_DMAEN_Pos 0 /**< \brief (SDHC_TMR) DMA Enable */
+#define SDHC_TMR_DMAEN (_U_(0x1) << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_DMAEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */
+#define SDHC_TMR_DMAEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) DMA data transfer */
+#define SDHC_TMR_DMAEN_DISABLE (SDHC_TMR_DMAEN_DISABLE_Val << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_DMAEN_ENABLE (SDHC_TMR_DMAEN_ENABLE_Val << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_BCEN_Pos 1 /**< \brief (SDHC_TMR) Block Count Enable */
+#define SDHC_TMR_BCEN (_U_(0x1) << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_BCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Disable */
+#define SDHC_TMR_BCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Enable */
+#define SDHC_TMR_BCEN_DISABLE (SDHC_TMR_BCEN_DISABLE_Val << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_BCEN_ENABLE (SDHC_TMR_BCEN_ENABLE_Val << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_ACMDEN_Pos 2 /**< \brief (SDHC_TMR) Auto Command Enable */
+#define SDHC_TMR_ACMDEN_Msk (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN(value) (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))
+#define SDHC_TMR_ACMDEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_TMR) Auto Command Disabled */
+#define SDHC_TMR_ACMDEN_CMD12_Val _U_(0x1) /**< \brief (SDHC_TMR) Auto CMD12 Enable */
+#define SDHC_TMR_ACMDEN_CMD23_Val _U_(0x2) /**< \brief (SDHC_TMR) Auto CMD23 Enable */
+#define SDHC_TMR_ACMDEN_3_Val _U_(0x3) /**< \brief (SDHC_TMR) Reserved */
+#define SDHC_TMR_ACMDEN_DISABLED (SDHC_TMR_ACMDEN_DISABLED_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_CMD12 (SDHC_TMR_ACMDEN_CMD12_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_CMD23 (SDHC_TMR_ACMDEN_CMD23_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_3 (SDHC_TMR_ACMDEN_3_Val << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_DTDSEL_Pos 4 /**< \brief (SDHC_TMR) Data Transfer Direction Selection */
+#define SDHC_TMR_DTDSEL (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_DTDSEL_WRITE_Val _U_(0x0) /**< \brief (SDHC_TMR) Write (Host to Card) */
+#define SDHC_TMR_DTDSEL_READ_Val _U_(0x1) /**< \brief (SDHC_TMR) Read (Card to Host) */
+#define SDHC_TMR_DTDSEL_WRITE (SDHC_TMR_DTDSEL_WRITE_Val << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_DTDSEL_READ (SDHC_TMR_DTDSEL_READ_Val << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_MSBSEL_Pos 5 /**< \brief (SDHC_TMR) Multi/Single Block Selection */
+#define SDHC_TMR_MSBSEL (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MSBSEL_SINGLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Single Block */
+#define SDHC_TMR_MSBSEL_MULTIPLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Multiple Block */
+#define SDHC_TMR_MSBSEL_SINGLE (SDHC_TMR_MSBSEL_SINGLE_Val << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MSBSEL_MULTIPLE (SDHC_TMR_MSBSEL_MULTIPLE_Val << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MASK _U_(0x003F) /**< \brief (SDHC_TMR) MASK Register */
+
+/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESPTYP:2; /*!< bit: 0.. 1 Response Type */
+ uint16_t :1; /*!< bit: 2 Reserved */
+ uint16_t CMDCCEN:1; /*!< bit: 3 Command CRC Check Enable */
+ uint16_t CMDICEN:1; /*!< bit: 4 Command Index Check Enable */
+ uint16_t DPSEL:1; /*!< bit: 5 Data Present Select */
+ uint16_t CMDTYP:2; /*!< bit: 6.. 7 Command Type */
+ uint16_t CMDIDX:6; /*!< bit: 8..13 Command Index */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_CR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CR_OFFSET 0x00E /**< \brief (SDHC_CR offset) Command */
+#define SDHC_CR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CR reset_value) Command */
+
+#define SDHC_CR_RESPTYP_Pos 0 /**< \brief (SDHC_CR) Response Type */
+#define SDHC_CR_RESPTYP_Msk (_U_(0x3) << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP(value) (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))
+#define SDHC_CR_RESPTYP_NONE_Val _U_(0x0) /**< \brief (SDHC_CR) No response */
+#define SDHC_CR_RESPTYP_136_BIT_Val _U_(0x1) /**< \brief (SDHC_CR) 136-bit response */
+#define SDHC_CR_RESPTYP_48_BIT_Val _U_(0x2) /**< \brief (SDHC_CR) 48-bit response */
+#define SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3) /**< \brief (SDHC_CR) 48-bit response check busy after response */
+#define SDHC_CR_RESPTYP_NONE (SDHC_CR_RESPTYP_NONE_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_136_BIT (SDHC_CR_RESPTYP_136_BIT_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_48_BIT (SDHC_CR_RESPTYP_48_BIT_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_CMDCCEN_Pos 3 /**< \brief (SDHC_CR) Command CRC Check Enable */
+#define SDHC_CR_CMDCCEN (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDCCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */
+#define SDHC_CR_CMDCCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */
+#define SDHC_CR_CMDCCEN_DISABLE (SDHC_CR_CMDCCEN_DISABLE_Val << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDCCEN_ENABLE (SDHC_CR_CMDCCEN_ENABLE_Val << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDICEN_Pos 4 /**< \brief (SDHC_CR) Command Index Check Enable */
+#define SDHC_CR_CMDICEN (_U_(0x1) << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_CMDICEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */
+#define SDHC_CR_CMDICEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */
+#define SDHC_CR_CMDICEN_DISABLE (SDHC_CR_CMDICEN_DISABLE_Val << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_CMDICEN_ENABLE (SDHC_CR_CMDICEN_ENABLE_Val << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_DPSEL_Pos 5 /**< \brief (SDHC_CR) Data Present Select */
+#define SDHC_CR_DPSEL (_U_(0x1) << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_DPSEL_NO_DATA_Val _U_(0x0) /**< \brief (SDHC_CR) No Data Present */
+#define SDHC_CR_DPSEL_DATA_Val _U_(0x1) /**< \brief (SDHC_CR) Data Present */
+#define SDHC_CR_DPSEL_NO_DATA (SDHC_CR_DPSEL_NO_DATA_Val << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_DPSEL_DATA (SDHC_CR_DPSEL_DATA_Val << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_CMDTYP_Pos 6 /**< \brief (SDHC_CR) Command Type */
+#define SDHC_CR_CMDTYP_Msk (_U_(0x3) << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP(value) (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))
+#define SDHC_CR_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_CR) Other commands */
+#define SDHC_CR_CMDTYP_SUSPEND_Val _U_(0x1) /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */
+#define SDHC_CR_CMDTYP_RESUME_Val _U_(0x2) /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */
+#define SDHC_CR_CMDTYP_ABORT_Val _U_(0x3) /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */
+#define SDHC_CR_CMDTYP_NORMAL (SDHC_CR_CMDTYP_NORMAL_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_SUSPEND (SDHC_CR_CMDTYP_SUSPEND_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_RESUME (SDHC_CR_CMDTYP_RESUME_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_ABORT (SDHC_CR_CMDTYP_ABORT_Val << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDIDX_Pos 8 /**< \brief (SDHC_CR) Command Index */
+#define SDHC_CR_CMDIDX_Msk (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)
+#define SDHC_CR_CMDIDX(value) (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))
+#define SDHC_CR_MASK _U_(0x3FFB) /**< \brief (SDHC_CR) MASK Register */
+
+/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/ 32) Response -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CMDRESP:32; /*!< bit: 0..31 Command Response */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_RR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_RR_OFFSET 0x010 /**< \brief (SDHC_RR offset) Response */
+#define SDHC_RR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */
+
+#define SDHC_RR_CMDRESP_Pos 0 /**< \brief (SDHC_RR) Command Response */
+#define SDHC_RR_CMDRESP_Msk (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)
+#define SDHC_RR_CMDRESP(value) (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))
+#define SDHC_RR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */
+
+/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUFDATA:32; /*!< bit: 0..31 Buffer Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_BDPR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BDPR_OFFSET 0x020 /**< \brief (SDHC_BDPR offset) Buffer Data Port */
+#define SDHC_BDPR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */
+
+#define SDHC_BDPR_BUFDATA_Pos 0 /**< \brief (SDHC_BDPR) Buffer Data */
+#define SDHC_BDPR_BUFDATA_Msk (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)
+#define SDHC_BDPR_BUFDATA(value) (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))
+#define SDHC_BDPR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */
+
+/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/ 32) Present State -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CMDINHC:1; /*!< bit: 0 Command Inhibit (CMD) */
+ uint32_t CMDINHD:1; /*!< bit: 1 Command Inhibit (DAT) */
+ uint32_t DLACT:1; /*!< bit: 2 DAT Line Active */
+ uint32_t RTREQ:1; /*!< bit: 3 Re-Tuning Request */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t WTACT:1; /*!< bit: 8 Write Transfer Active */
+ uint32_t RTACT:1; /*!< bit: 9 Read Transfer Active */
+ uint32_t BUFWREN:1; /*!< bit: 10 Buffer Write Enable */
+ uint32_t BUFRDEN:1; /*!< bit: 11 Buffer Read Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t CARDINS:1; /*!< bit: 16 Card Inserted */
+ uint32_t CARDSS:1; /*!< bit: 17 Card State Stable */
+ uint32_t CARDDPL:1; /*!< bit: 18 Card Detect Pin Level */
+ uint32_t WRPPL:1; /*!< bit: 19 Write Protect Pin Level */
+ uint32_t DATLL:4; /*!< bit: 20..23 DAT[3:0] Line Level */
+ uint32_t CMDLL:1; /*!< bit: 24 CMD Line Level */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_PSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PSR_OFFSET 0x024 /**< \brief (SDHC_PSR offset) Present State */
+#define SDHC_PSR_RESETVALUE _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */
+
+#define SDHC_PSR_CMDINHC_Pos 0 /**< \brief (SDHC_PSR) Command Inhibit (CMD) */
+#define SDHC_PSR_CMDINHC (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHC_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command using only CMD line */
+#define SDHC_PSR_CMDINHC_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command */
+#define SDHC_PSR_CMDINHC_CAN (SDHC_PSR_CMDINHC_CAN_Val << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHC_CANNOT (SDHC_PSR_CMDINHC_CANNOT_Val << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHD_Pos 1 /**< \brief (SDHC_PSR) Command Inhibit (DAT) */
+#define SDHC_PSR_CMDINHD (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_CMDINHD_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */
+#define SDHC_PSR_CMDINHD_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */
+#define SDHC_PSR_CMDINHD_CAN (SDHC_PSR_CMDINHD_CAN_Val << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_CMDINHD_CANNOT (SDHC_PSR_CMDINHD_CANNOT_Val << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_DLACT_Pos 2 /**< \brief (SDHC_PSR) DAT Line Active */
+#define SDHC_PSR_DLACT (_U_(0x1) << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_DLACT_INACTIVE_Val _U_(0x0) /**< \brief (SDHC_PSR) DAT Line Inactive */
+#define SDHC_PSR_DLACT_ACTIVE_Val _U_(0x1) /**< \brief (SDHC_PSR) DAT Line Active */
+#define SDHC_PSR_DLACT_INACTIVE (SDHC_PSR_DLACT_INACTIVE_Val << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_DLACT_ACTIVE (SDHC_PSR_DLACT_ACTIVE_Val << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_RTREQ_Pos 3 /**< \brief (SDHC_PSR) Re-Tuning Request */
+#define SDHC_PSR_RTREQ (_U_(0x1) << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_RTREQ_OK_Val _U_(0x0) /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */
+#define SDHC_PSR_RTREQ_REQUIRED_Val _U_(0x1) /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */
+#define SDHC_PSR_RTREQ_OK (SDHC_PSR_RTREQ_OK_Val << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_RTREQ_REQUIRED (SDHC_PSR_RTREQ_REQUIRED_Val << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_WTACT_Pos 8 /**< \brief (SDHC_PSR) Write Transfer Active */
+#define SDHC_PSR_WTACT (_U_(0x1) << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_WTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */
+#define SDHC_PSR_WTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */
+#define SDHC_PSR_WTACT_NO (SDHC_PSR_WTACT_NO_Val << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_WTACT_YES (SDHC_PSR_WTACT_YES_Val << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_RTACT_Pos 9 /**< \brief (SDHC_PSR) Read Transfer Active */
+#define SDHC_PSR_RTACT (_U_(0x1) << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_RTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */
+#define SDHC_PSR_RTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */
+#define SDHC_PSR_RTACT_NO (SDHC_PSR_RTACT_NO_Val << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_RTACT_YES (SDHC_PSR_RTACT_YES_Val << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_BUFWREN_Pos 10 /**< \brief (SDHC_PSR) Buffer Write Enable */
+#define SDHC_PSR_BUFWREN (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFWREN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Write disable */
+#define SDHC_PSR_BUFWREN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enable */
+#define SDHC_PSR_BUFWREN_DISABLE (SDHC_PSR_BUFWREN_DISABLE_Val << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFWREN_ENABLE (SDHC_PSR_BUFWREN_ENABLE_Val << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFRDEN_Pos 11 /**< \brief (SDHC_PSR) Buffer Read Enable */
+#define SDHC_PSR_BUFRDEN (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_BUFRDEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Read disable */
+#define SDHC_PSR_BUFRDEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Read enable */
+#define SDHC_PSR_BUFRDEN_DISABLE (SDHC_PSR_BUFRDEN_DISABLE_Val << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_BUFRDEN_ENABLE (SDHC_PSR_BUFRDEN_ENABLE_Val << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_CARDINS_Pos 16 /**< \brief (SDHC_PSR) Card Inserted */
+#define SDHC_PSR_CARDINS (_U_(0x1) << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDINS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */
+#define SDHC_PSR_CARDINS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card inserted */
+#define SDHC_PSR_CARDINS_NO (SDHC_PSR_CARDINS_NO_Val << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDINS_YES (SDHC_PSR_CARDINS_YES_Val << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDSS_Pos 17 /**< \brief (SDHC_PSR) Card State Stable */
+#define SDHC_PSR_CARDSS (_U_(0x1) << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDSS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing */
+#define SDHC_PSR_CARDSS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) No Card or Insered */
+#define SDHC_PSR_CARDSS_NO (SDHC_PSR_CARDSS_NO_Val << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDSS_YES (SDHC_PSR_CARDSS_YES_Val << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDDPL_Pos 18 /**< \brief (SDHC_PSR) Card Detect Pin Level */
+#define SDHC_PSR_CARDDPL (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_CARDDPL_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No card present (SDCD#=1) */
+#define SDHC_PSR_CARDDPL_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card present (SDCD#=0) */
+#define SDHC_PSR_CARDDPL_NO (SDHC_PSR_CARDDPL_NO_Val << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_CARDDPL_YES (SDHC_PSR_CARDDPL_YES_Val << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_WRPPL_Pos 19 /**< \brief (SDHC_PSR) Write Protect Pin Level */
+#define SDHC_PSR_WRPPL (_U_(0x1) << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_WRPPL_PROTECTED_Val _U_(0x0) /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */
+#define SDHC_PSR_WRPPL_ENABLED_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */
+#define SDHC_PSR_WRPPL_PROTECTED (SDHC_PSR_WRPPL_PROTECTED_Val << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_WRPPL_ENABLED (SDHC_PSR_WRPPL_ENABLED_Val << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_DATLL_Pos 20 /**< \brief (SDHC_PSR) DAT[3:0] Line Level */
+#define SDHC_PSR_DATLL_Msk (_U_(0xF) << SDHC_PSR_DATLL_Pos)
+#define SDHC_PSR_DATLL(value) (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))
+#define SDHC_PSR_CMDLL_Pos 24 /**< \brief (SDHC_PSR) CMD Line Level */
+#define SDHC_PSR_CMDLL (_U_(0x1) << SDHC_PSR_CMDLL_Pos)
+#define SDHC_PSR_MASK _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */
+
+/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W 8) Host Control 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t LEDCTRL:1; /*!< bit: 0 LED Control */
+ uint8_t DW:1; /*!< bit: 1 Data Width */
+ uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */
+ uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t CARDDTL:1; /*!< bit: 6 Card Detect Test Level */
+ uint8_t CARDDSEL:1; /*!< bit: 7 Card Detect Signal Selection */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t DW:1; /*!< bit: 1 Data Width */
+ uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */
+ uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_HC1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HC1R_OFFSET 0x028 /**< \brief (SDHC_HC1R offset) Host Control 1 */
+#define SDHC_HC1R_RESETVALUE _U_(0xE00) /**< \brief (SDHC_HC1R reset_value) Host Control 1 */
+
+#define SDHC_HC1R_LEDCTRL_Pos 0 /**< \brief (SDHC_HC1R) LED Control */
+#define SDHC_HC1R_LEDCTRL (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_LEDCTRL_OFF_Val _U_(0x0) /**< \brief (SDHC_HC1R) LED off */
+#define SDHC_HC1R_LEDCTRL_ON_Val _U_(0x1) /**< \brief (SDHC_HC1R) LED on */
+#define SDHC_HC1R_LEDCTRL_OFF (SDHC_HC1R_LEDCTRL_OFF_Val << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_LEDCTRL_ON (SDHC_HC1R_LEDCTRL_ON_Val << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_DW_Pos 1 /**< \brief (SDHC_HC1R) Data Width */
+#define SDHC_HC1R_DW (_U_(0x1) << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R) 1-bit mode */
+#define SDHC_HC1R_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R) 4-bit mode */
+#define SDHC_HC1R_DW_1BIT (SDHC_HC1R_DW_1BIT_Val << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_DW_4BIT (SDHC_HC1R_DW_4BIT_Val << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_HSEN_Pos 2 /**< \brief (SDHC_HC1R) High Speed Enable */
+#define SDHC_HC1R_HSEN (_U_(0x1) << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) Normal Speed mode */
+#define SDHC_HC1R_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R) High Speed mode */
+#define SDHC_HC1R_HSEN_NORMAL (SDHC_HC1R_HSEN_NORMAL_Val << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_HSEN_HIGH (SDHC_HC1R_HSEN_HIGH_Val << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_DMASEL_Pos 3 /**< \brief (SDHC_HC1R) DMA Select */
+#define SDHC_HC1R_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL(value) (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))
+#define SDHC_HC1R_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDMA is selected */
+#define SDHC_HC1R_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R) Reserved */
+#define SDHC_HC1R_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */
+#define SDHC_HC1R_DMASEL_SDMA (SDHC_HC1R_DMASEL_SDMA_Val << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL_1 (SDHC_HC1R_DMASEL_1_Val << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL_32BIT (SDHC_HC1R_DMASEL_32BIT_Val << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_CARDDTL_Pos 6 /**< \brief (SDHC_HC1R) Card Detect Test Level */
+#define SDHC_HC1R_CARDDTL (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDTL_NO_Val _U_(0x0) /**< \brief (SDHC_HC1R) No Card */
+#define SDHC_HC1R_CARDDTL_YES_Val _U_(0x1) /**< \brief (SDHC_HC1R) Card Inserted */
+#define SDHC_HC1R_CARDDTL_NO (SDHC_HC1R_CARDDTL_NO_Val << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDTL_YES (SDHC_HC1R_CARDDTL_YES_Val << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDSEL_Pos 7 /**< \brief (SDHC_HC1R) Card Detect Signal Selection */
+#define SDHC_HC1R_CARDDSEL (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_CARDDSEL_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */
+#define SDHC_HC1R_CARDDSEL_TEST_Val _U_(0x1) /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */
+#define SDHC_HC1R_CARDDSEL_NORMAL (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_CARDDSEL_TEST (SDHC_HC1R_CARDDSEL_TEST_Val << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_MASK _U_(0xDF) /**< \brief (SDHC_HC1R) MASK Register */
+
+// EMMC mode
+#define SDHC_HC1R_EMMC_DW_Pos 1 /**< \brief (SDHC_HC1R_EMMC) Data Width */
+#define SDHC_HC1R_EMMC_DW (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */
+#define SDHC_HC1R_EMMC_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */
+#define SDHC_HC1R_EMMC_DW_1BIT (SDHC_HC1R_EMMC_DW_1BIT_Val << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_DW_4BIT (SDHC_HC1R_EMMC_DW_4BIT_Val << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_HSEN_Pos 2 /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */
+#define SDHC_HC1R_EMMC_HSEN (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */
+#define SDHC_HC1R_EMMC_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) High Speed mode */
+#define SDHC_HC1R_EMMC_HSEN_NORMAL (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_HSEN_HIGH (SDHC_HC1R_EMMC_HSEN_HIGH_Val << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_Pos 3 /**< \brief (SDHC_HC1R_EMMC) DMA Select */
+#define SDHC_HC1R_EMMC_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))
+#define SDHC_HC1R_EMMC_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */
+#define SDHC_HC1R_EMMC_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) Reserved */
+#define SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */
+#define SDHC_HC1R_EMMC_DMASEL_SDMA (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_1 (SDHC_HC1R_EMMC_DMASEL_1_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_MASK _U_(0x1E) /**< \brief (SDHC_HC1R_EMMC) MASK Register */
+
+/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W 8) Power Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SDBPWR:1; /*!< bit: 0 SD Bus Power */
+ uint8_t SDBVSEL:3; /*!< bit: 1.. 3 SD Bus Voltage Select */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_PCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PCR_OFFSET 0x029 /**< \brief (SDHC_PCR offset) Power Control */
+#define SDHC_PCR_RESETVALUE _U_(0x0E) /**< \brief (SDHC_PCR reset_value) Power Control */
+
+#define SDHC_PCR_SDBPWR_Pos 0 /**< \brief (SDHC_PCR) SD Bus Power */
+#define SDHC_PCR_SDBPWR (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBPWR_OFF_Val _U_(0x0) /**< \brief (SDHC_PCR) Power off */
+#define SDHC_PCR_SDBPWR_ON_Val _U_(0x1) /**< \brief (SDHC_PCR) Power on */
+#define SDHC_PCR_SDBPWR_OFF (SDHC_PCR_SDBPWR_OFF_Val << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBPWR_ON (SDHC_PCR_SDBPWR_ON_Val << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBVSEL_Pos 1 /**< \brief (SDHC_PCR) SD Bus Voltage Select */
+#define SDHC_PCR_SDBVSEL_Msk (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL(value) (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))
+#define SDHC_PCR_SDBVSEL_1V8_Val _U_(0x5) /**< \brief (SDHC_PCR) 1.8V (Typ.) */
+#define SDHC_PCR_SDBVSEL_3V0_Val _U_(0x6) /**< \brief (SDHC_PCR) 3.0V (Typ.) */
+#define SDHC_PCR_SDBVSEL_3V3_Val _U_(0x7) /**< \brief (SDHC_PCR) 3.3V (Typ.) */
+#define SDHC_PCR_SDBVSEL_1V8 (SDHC_PCR_SDBVSEL_1V8_Val << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL_3V0 (SDHC_PCR_SDBVSEL_3V0_Val << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL_3V3 (SDHC_PCR_SDBVSEL_3V3_Val << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_MASK _U_(0x0F) /**< \brief (SDHC_PCR) MASK Register */
+
+/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W 8) Block Gap Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */
+ uint8_t CONTR:1; /*!< bit: 1 Continue Request */
+ uint8_t RWCTRL:1; /*!< bit: 2 Read Wait Control */
+ uint8_t INTBG:1; /*!< bit: 3 Interrupt at Block Gap */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */
+ uint8_t CONTR:1; /*!< bit: 1 Continue Request */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_BGCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BGCR_OFFSET 0x02A /**< \brief (SDHC_BGCR offset) Block Gap Control */
+#define SDHC_BGCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_BGCR reset_value) Block Gap Control */
+
+#define SDHC_BGCR_STPBGR_Pos 0 /**< \brief (SDHC_BGCR) Stop at Block Gap Request */
+#define SDHC_BGCR_STPBGR (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR) Transfer */
+#define SDHC_BGCR_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR) Stop */
+#define SDHC_BGCR_STPBGR_TRANSFER (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_STPBGR_STOP (SDHC_BGCR_STPBGR_STOP_Val << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_CONTR_Pos 1 /**< \brief (SDHC_BGCR) Continue Request */
+#define SDHC_BGCR_CONTR (_U_(0x1) << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR) Not affected */
+#define SDHC_BGCR_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR) Restart */
+#define SDHC_BGCR_CONTR_GO_ON (SDHC_BGCR_CONTR_GO_ON_Val << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_CONTR_RESTART (SDHC_BGCR_CONTR_RESTART_Val << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_RWCTRL_Pos 2 /**< \brief (SDHC_BGCR) Read Wait Control */
+#define SDHC_BGCR_RWCTRL (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_RWCTRL_DISABLE_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disable Read Wait Control */
+#define SDHC_BGCR_RWCTRL_ENABLE_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enable Read Wait Control */
+#define SDHC_BGCR_RWCTRL_DISABLE (SDHC_BGCR_RWCTRL_DISABLE_Val << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_RWCTRL_ENABLE (SDHC_BGCR_RWCTRL_ENABLE_Val << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_INTBG_Pos 3 /**< \brief (SDHC_BGCR) Interrupt at Block Gap */
+#define SDHC_BGCR_INTBG (_U_(0x1) << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_INTBG_DISABLED_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disabled */
+#define SDHC_BGCR_INTBG_ENABLED_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enabled */
+#define SDHC_BGCR_INTBG_DISABLED (SDHC_BGCR_INTBG_DISABLED_Val << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_INTBG_ENABLED (SDHC_BGCR_INTBG_ENABLED_Val << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_MASK _U_(0x0F) /**< \brief (SDHC_BGCR) MASK Register */
+
+// EMMC mode
+#define SDHC_BGCR_EMMC_STPBGR_Pos 0 /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */
+#define SDHC_BGCR_EMMC_STPBGR (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Transfer */
+#define SDHC_BGCR_EMMC_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Stop */
+#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_STPBGR_STOP (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_Pos 1 /**< \brief (SDHC_BGCR_EMMC) Continue Request */
+#define SDHC_BGCR_EMMC_CONTR (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Not affected */
+#define SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Restart */
+#define SDHC_BGCR_EMMC_CONTR_GO_ON (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_MASK _U_(0x03) /**< \brief (SDHC_BGCR_EMMC) MASK Register */
+
+/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W 8) Wakeup Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WKENCINT:1; /*!< bit: 0 Wakeup Event Enable on Card Interrupt */
+ uint8_t WKENCINS:1; /*!< bit: 1 Wakeup Event Enable on Card Insertion */
+ uint8_t WKENCREM:1; /*!< bit: 2 Wakeup Event Enable on Card Removal */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_WCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_WCR_OFFSET 0x02B /**< \brief (SDHC_WCR offset) Wakeup Control */
+#define SDHC_WCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_WCR reset_value) Wakeup Control */
+
+#define SDHC_WCR_WKENCINT_Pos 0 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Interrupt */
+#define SDHC_WCR_WKENCINT (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINT_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
+#define SDHC_WCR_WKENCINT_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCINT_DISABLE (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINT_ENABLE (SDHC_WCR_WKENCINT_ENABLE_Val << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINS_Pos 1 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Insertion */
+#define SDHC_WCR_WKENCINS (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCINS_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
+#define SDHC_WCR_WKENCINS_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCINS_DISABLE (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCINS_ENABLE (SDHC_WCR_WKENCINS_ENABLE_Val << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCREM_Pos 2 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Removal */
+#define SDHC_WCR_WKENCREM (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_WKENCREM_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */
+#define SDHC_WCR_WKENCREM_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCREM_DISABLE (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_WKENCREM_ENABLE (SDHC_WCR_WKENCREM_ENABLE_Val << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_MASK _U_(0x07) /**< \brief (SDHC_WCR) MASK Register */
+
+/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t INTCLKEN:1; /*!< bit: 0 Internal Clock Enable */
+ uint16_t INTCLKS:1; /*!< bit: 1 Internal Clock Stable */
+ uint16_t SDCLKEN:1; /*!< bit: 2 SD Clock Enable */
+ uint16_t :2; /*!< bit: 3.. 4 Reserved */
+ uint16_t CLKGSEL:1; /*!< bit: 5 Clock Generator Select */
+ uint16_t USDCLKFSEL:2; /*!< bit: 6.. 7 Upper Bits of SDCLK Frequency Select */
+ uint16_t SDCLKFSEL:8; /*!< bit: 8..15 SDCLK Frequency Select */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_CCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CCR_OFFSET 0x02C /**< \brief (SDHC_CCR offset) Clock Control */
+#define SDHC_CCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CCR reset_value) Clock Control */
+
+#define SDHC_CCR_INTCLKEN_Pos 0 /**< \brief (SDHC_CCR) Internal Clock Enable */
+#define SDHC_CCR_INTCLKEN (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKEN_OFF_Val _U_(0x0) /**< \brief (SDHC_CCR) Stop */
+#define SDHC_CCR_INTCLKEN_ON_Val _U_(0x1) /**< \brief (SDHC_CCR) Oscillate */
+#define SDHC_CCR_INTCLKEN_OFF (SDHC_CCR_INTCLKEN_OFF_Val << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKEN_ON (SDHC_CCR_INTCLKEN_ON_Val << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKS_Pos 1 /**< \brief (SDHC_CCR) Internal Clock Stable */
+#define SDHC_CCR_INTCLKS (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_INTCLKS_NOT_READY_Val _U_(0x0) /**< \brief (SDHC_CCR) Not Ready */
+#define SDHC_CCR_INTCLKS_READY_Val _U_(0x1) /**< \brief (SDHC_CCR) Ready */
+#define SDHC_CCR_INTCLKS_NOT_READY (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_INTCLKS_READY (SDHC_CCR_INTCLKS_READY_Val << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_SDCLKEN_Pos 2 /**< \brief (SDHC_CCR) SD Clock Enable */
+#define SDHC_CCR_SDCLKEN (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_SDCLKEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CCR) Disable */
+#define SDHC_CCR_SDCLKEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CCR) Enable */
+#define SDHC_CCR_SDCLKEN_DISABLE (SDHC_CCR_SDCLKEN_DISABLE_Val << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_SDCLKEN_ENABLE (SDHC_CCR_SDCLKEN_ENABLE_Val << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_CLKGSEL_Pos 5 /**< \brief (SDHC_CCR) Clock Generator Select */
+#define SDHC_CCR_CLKGSEL (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */
+#define SDHC_CCR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_CCR) Programmable Clock Mode */
+#define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_CLKGSEL_PROG (SDHC_CCR_CLKGSEL_PROG_Val << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_USDCLKFSEL_Pos 6 /**< \brief (SDHC_CCR) Upper Bits of SDCLK Frequency Select */
+#define SDHC_CCR_USDCLKFSEL_Msk (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)
+#define SDHC_CCR_USDCLKFSEL(value) (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))
+#define SDHC_CCR_SDCLKFSEL_Pos 8 /**< \brief (SDHC_CCR) SDCLK Frequency Select */
+#define SDHC_CCR_SDCLKFSEL_Msk (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)
+#define SDHC_CCR_SDCLKFSEL(value) (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))
+#define SDHC_CCR_MASK _U_(0xFFE7) /**< \brief (SDHC_CCR) MASK Register */
+
+/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W 8) Timeout Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTCVAL:4; /*!< bit: 0.. 3 Data Timeout Counter Value */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_TCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_TCR_OFFSET 0x02E /**< \brief (SDHC_TCR offset) Timeout Control */
+#define SDHC_TCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_TCR reset_value) Timeout Control */
+
+#define SDHC_TCR_DTCVAL_Pos 0 /**< \brief (SDHC_TCR) Data Timeout Counter Value */
+#define SDHC_TCR_DTCVAL_Msk (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)
+#define SDHC_TCR_DTCVAL(value) (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))
+#define SDHC_TCR_MASK _U_(0x0F) /**< \brief (SDHC_TCR) MASK Register */
+
+/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W 8) Software Reset -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRSTALL:1; /*!< bit: 0 Software Reset For All */
+ uint8_t SWRSTCMD:1; /*!< bit: 1 Software Reset For CMD Line */
+ uint8_t SWRSTDAT:1; /*!< bit: 2 Software Reset For DAT Line */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_SRR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SRR_OFFSET 0x02F /**< \brief (SDHC_SRR offset) Software Reset */
+#define SDHC_SRR_RESETVALUE _U_(0x00) /**< \brief (SDHC_SRR reset_value) Software Reset */
+
+#define SDHC_SRR_SWRSTALL_Pos 0 /**< \brief (SDHC_SRR) Software Reset For All */
+#define SDHC_SRR_SWRSTALL (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTALL_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
+#define SDHC_SRR_SWRSTALL_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTALL_WORK (SDHC_SRR_SWRSTALL_WORK_Val << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTALL_RESET (SDHC_SRR_SWRSTALL_RESET_Val << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTCMD_Pos 1 /**< \brief (SDHC_SRR) Software Reset For CMD Line */
+#define SDHC_SRR_SWRSTCMD (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTCMD_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
+#define SDHC_SRR_SWRSTCMD_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTCMD_WORK (SDHC_SRR_SWRSTCMD_WORK_Val << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTCMD_RESET (SDHC_SRR_SWRSTCMD_RESET_Val << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTDAT_Pos 2 /**< \brief (SDHC_SRR) Software Reset For DAT Line */
+#define SDHC_SRR_SWRSTDAT (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_SWRSTDAT_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */
+#define SDHC_SRR_SWRSTDAT_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTDAT_WORK (SDHC_SRR_SWRSTDAT_WORK_Val << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_SWRSTDAT_RESET (SDHC_SRR_SWRSTDAT_RESET_Val << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_MASK _U_(0x07) /**< \brief (SDHC_SRR) MASK Register */
+
+/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */
+ uint16_t CINS:1; /*!< bit: 6 Card Insertion */
+ uint16_t CREM:1; /*!< bit: 7 Card Removal */
+ uint16_t CINT:1; /*!< bit: 8 Card Interrupt */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received */
+ uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_NISTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISTR_OFFSET 0x030 /**< \brief (SDHC_NISTR offset) Normal Interrupt Status */
+#define SDHC_NISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTR reset_value) Normal Interrupt Status */
+
+#define SDHC_NISTR_CMDC_Pos 0 /**< \brief (SDHC_NISTR) Command Complete */
+#define SDHC_NISTR_CMDC (_U_(0x1) << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No command complete */
+#define SDHC_NISTR_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command complete */
+#define SDHC_NISTR_CMDC_NO (SDHC_NISTR_CMDC_NO_Val << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_CMDC_YES (SDHC_NISTR_CMDC_YES_Val << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_TRFC_Pos 1 /**< \brief (SDHC_NISTR) Transfer Complete */
+#define SDHC_NISTR_TRFC (_U_(0x1) << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not complete */
+#define SDHC_NISTR_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command execution is completed */
+#define SDHC_NISTR_TRFC_NO (SDHC_NISTR_TRFC_NO_Val << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_TRFC_YES (SDHC_NISTR_TRFC_YES_Val << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_BLKGE_Pos 2 /**< \brief (SDHC_NISTR) Block Gap Event */
+#define SDHC_NISTR_BLKGE (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Block Gap Event */
+#define SDHC_NISTR_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR) Transaction stopped at block gap */
+#define SDHC_NISTR_BLKGE_NO (SDHC_NISTR_BLKGE_NO_Val << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_BLKGE_STOP (SDHC_NISTR_BLKGE_STOP_Val << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_DMAINT_Pos 3 /**< \brief (SDHC_NISTR) DMA Interrupt */
+#define SDHC_NISTR_DMAINT (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No DMA Interrupt */
+#define SDHC_NISTR_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) DMA Interrupt is generated */
+#define SDHC_NISTR_DMAINT_NO (SDHC_NISTR_DMAINT_NO_Val << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_DMAINT_YES (SDHC_NISTR_DMAINT_YES_Val << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR) Buffer Write Ready */
+#define SDHC_NISTR_BWRRDY (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to write buffer */
+#define SDHC_NISTR_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to write buffer */
+#define SDHC_NISTR_BWRRDY_NO (SDHC_NISTR_BWRRDY_NO_Val << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BWRRDY_YES (SDHC_NISTR_BWRRDY_YES_Val << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR) Buffer Read Ready */
+#define SDHC_NISTR_BRDRDY (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to read buffer */
+#define SDHC_NISTR_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to read buffer */
+#define SDHC_NISTR_BRDRDY_NO (SDHC_NISTR_BRDRDY_NO_Val << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_BRDRDY_YES (SDHC_NISTR_BRDRDY_YES_Val << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_CINS_Pos 6 /**< \brief (SDHC_NISTR) Card Insertion */
+#define SDHC_NISTR_CINS (_U_(0x1) << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CINS_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
+#define SDHC_NISTR_CINS_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card inserted */
+#define SDHC_NISTR_CINS_NO (SDHC_NISTR_CINS_NO_Val << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CINS_YES (SDHC_NISTR_CINS_YES_Val << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CREM_Pos 7 /**< \brief (SDHC_NISTR) Card Removal */
+#define SDHC_NISTR_CREM (_U_(0x1) << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CREM_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
+#define SDHC_NISTR_CREM_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card Removed */
+#define SDHC_NISTR_CREM_NO (SDHC_NISTR_CREM_NO_Val << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CREM_YES (SDHC_NISTR_CREM_YES_Val << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CINT_Pos 8 /**< \brief (SDHC_NISTR) Card Interrupt */
+#define SDHC_NISTR_CINT (_U_(0x1) << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_CINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Card Interrupt */
+#define SDHC_NISTR_CINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Generate Card Interrupt */
+#define SDHC_NISTR_CINT_NO (SDHC_NISTR_CINT_NO_Val << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_CINT_YES (SDHC_NISTR_CINT_YES_Val << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_ERRINT_Pos 15 /**< \brief (SDHC_NISTR) Error Interrupt */
+#define SDHC_NISTR_ERRINT (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Error */
+#define SDHC_NISTR_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Error */
+#define SDHC_NISTR_ERRINT_NO (SDHC_NISTR_ERRINT_NO_Val << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_ERRINT_YES (SDHC_NISTR_ERRINT_YES_Val << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_MASK _U_(0x81FF) /**< \brief (SDHC_NISTR) MASK Register */
+
+// EMMC mode
+#define SDHC_NISTR_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTR_EMMC) Command Complete */
+#define SDHC_NISTR_EMMC_CMDC (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No command complete */
+#define SDHC_NISTR_EMMC_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command complete */
+#define SDHC_NISTR_EMMC_CMDC_NO (SDHC_NISTR_EMMC_CMDC_NO_Val << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_CMDC_YES (SDHC_NISTR_EMMC_CMDC_YES_Val << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTR_EMMC) Transfer Complete */
+#define SDHC_NISTR_EMMC_TRFC (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not complete */
+#define SDHC_NISTR_EMMC_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command execution is completed */
+#define SDHC_NISTR_EMMC_TRFC_NO (SDHC_NISTR_EMMC_TRFC_NO_Val << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_YES (SDHC_NISTR_EMMC_TRFC_YES_Val << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTR_EMMC) Block Gap Event */
+#define SDHC_NISTR_EMMC_BLKGE (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Block Gap Event */
+#define SDHC_NISTR_EMMC_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Transaction stopped at block gap */
+#define SDHC_NISTR_EMMC_BLKGE_NO (SDHC_NISTR_EMMC_BLKGE_NO_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_STOP (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt */
+#define SDHC_NISTR_EMMC_DMAINT (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No DMA Interrupt */
+#define SDHC_NISTR_EMMC_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt is generated */
+#define SDHC_NISTR_EMMC_DMAINT_NO (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_YES (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR_EMMC) Buffer Write Ready */
+#define SDHC_NISTR_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to write buffer */
+#define SDHC_NISTR_EMMC_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to write buffer */
+#define SDHC_NISTR_EMMC_BWRRDY_NO (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_YES (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR_EMMC) Buffer Read Ready */
+#define SDHC_NISTR_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to read buffer */
+#define SDHC_NISTR_EMMC_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to read buffer */
+#define SDHC_NISTR_EMMC_BRDRDY_NO (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_YES (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTR_EMMC) Boot Acknowledge Received */
+#define SDHC_NISTR_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_Pos 15 /**< \brief (SDHC_NISTR_EMMC) Error Interrupt */
+#define SDHC_NISTR_EMMC_ERRINT (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Error */
+#define SDHC_NISTR_EMMC_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Error */
+#define SDHC_NISTR_EMMC_ERRINT_NO (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_YES (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_MASK _U_(0xC03F) /**< \brief (SDHC_NISTR_EMMC) MASK Register */
+
+/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_EISTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISTR_OFFSET 0x032 /**< \brief (SDHC_EISTR offset) Error Interrupt Status */
+#define SDHC_EISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTR reset_value) Error Interrupt Status */
+
+#define SDHC_EISTR_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR) Command Timeout Error */
+#define SDHC_EISTR_CMDTEO (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */
+#define SDHC_EISTR_CMDTEO_NO (SDHC_EISTR_CMDTEO_NO_Val << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDTEO_YES (SDHC_EISTR_CMDTEO_YES_Val << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR) Command CRC Error */
+#define SDHC_EISTR_CMDCRC (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) CRC Error Generated */
+#define SDHC_EISTR_CMDCRC_NO (SDHC_EISTR_CMDCRC_NO_Val << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDCRC_YES (SDHC_EISTR_CMDCRC_YES_Val << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDEND_Pos 2 /**< \brief (SDHC_EISTR) Command End Bit Error */
+#define SDHC_EISTR_CMDEND (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No error */
+#define SDHC_EISTR_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) End Bit Error Generated */
+#define SDHC_EISTR_CMDEND_NO (SDHC_EISTR_CMDEND_NO_Val << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDEND_YES (SDHC_EISTR_CMDEND_YES_Val << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR) Command Index Error */
+#define SDHC_EISTR_CMDIDX (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_CMDIDX_NO (SDHC_EISTR_CMDIDX_NO_Val << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_CMDIDX_YES (SDHC_EISTR_CMDIDX_YES_Val << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_DATTEO_Pos 4 /**< \brief (SDHC_EISTR) Data Timeout Error */
+#define SDHC_EISTR_DATTEO (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */
+#define SDHC_EISTR_DATTEO_NO (SDHC_EISTR_DATTEO_NO_Val << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATTEO_YES (SDHC_EISTR_DATTEO_YES_Val << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATCRC_Pos 5 /**< \brief (SDHC_EISTR) Data CRC Error */
+#define SDHC_EISTR_DATCRC (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_DATCRC_NO (SDHC_EISTR_DATCRC_NO_Val << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATCRC_YES (SDHC_EISTR_DATCRC_YES_Val << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATEND_Pos 6 /**< \brief (SDHC_EISTR) Data End Bit Error */
+#define SDHC_EISTR_DATEND (_U_(0x1) << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_DATEND_NO (SDHC_EISTR_DATEND_NO_Val << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_DATEND_YES (SDHC_EISTR_DATEND_YES_Val << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_CURLIM_Pos 7 /**< \brief (SDHC_EISTR) Current Limit Error */
+#define SDHC_EISTR_CURLIM (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Power Fail */
+#define SDHC_EISTR_CURLIM_NO (SDHC_EISTR_CURLIM_NO_Val << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_CURLIM_YES (SDHC_EISTR_CURLIM_YES_Val << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_ACMD_Pos 8 /**< \brief (SDHC_EISTR) Auto CMD Error */
+#define SDHC_EISTR_ACMD (_U_(0x1) << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_ACMD_NO (SDHC_EISTR_ACMD_NO_Val << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ACMD_YES (SDHC_EISTR_ACMD_YES_Val << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ADMA_Pos 9 /**< \brief (SDHC_EISTR) ADMA Error */
+#define SDHC_EISTR_ADMA (_U_(0x1) << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */
+#define SDHC_EISTR_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_ADMA_NO (SDHC_EISTR_ADMA_NO_Val << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_ADMA_YES (SDHC_EISTR_ADMA_YES_Val << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_MASK _U_(0x03FF) /**< \brief (SDHC_EISTR) MASK Register */
+
+// EMMC mode
+#define SDHC_EISTR_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR_EMMC) Command Timeout Error */
+#define SDHC_EISTR_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */
+#define SDHC_EISTR_EMMC_CMDTEO_NO (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDTEO_YES (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR_EMMC) Command CRC Error */
+#define SDHC_EISTR_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) CRC Error Generated */
+#define SDHC_EISTR_EMMC_CMDCRC_NO (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_YES (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTR_EMMC) Command End Bit Error */
+#define SDHC_EISTR_EMMC_CMDEND (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No error */
+#define SDHC_EISTR_EMMC_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) End Bit Error Generated */
+#define SDHC_EISTR_EMMC_CMDEND_NO (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_YES (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR_EMMC) Command Index Error */
+#define SDHC_EISTR_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_CMDIDX_NO (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_YES (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTR_EMMC) Data Timeout Error */
+#define SDHC_EISTR_EMMC_DATTEO (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */
+#define SDHC_EISTR_EMMC_DATTEO_NO (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_YES (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTR_EMMC) Data CRC Error */
+#define SDHC_EISTR_EMMC_DATCRC (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_DATCRC_NO (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_YES (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTR_EMMC) Data End Bit Error */
+#define SDHC_EISTR_EMMC_DATEND (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_DATEND_NO (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_DATEND_YES (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTR_EMMC) Current Limit Error */
+#define SDHC_EISTR_EMMC_CURLIM (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Power Fail */
+#define SDHC_EISTR_EMMC_CURLIM_NO (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_YES (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTR_EMMC) Auto CMD Error */
+#define SDHC_EISTR_EMMC_ACMD (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_ACMD_NO (SDHC_EISTR_EMMC_ACMD_NO_Val << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ACMD_YES (SDHC_EISTR_EMMC_ACMD_YES_Val << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTR_EMMC) ADMA Error */
+#define SDHC_EISTR_EMMC_ADMA (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define SDHC_EISTR_EMMC_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_ADMA_NO (SDHC_EISTR_EMMC_ADMA_NO_Val << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_ADMA_YES (SDHC_EISTR_EMMC_ADMA_YES_Val << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTR_EMMC) Boot Acknowledge Error */
+#define SDHC_EISTR_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_0_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) FIFO contains at least one byte */
+#define SDHC_EISTR_EMMC_BOOTAE_1_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) FIFO is empty */
+#define SDHC_EISTR_EMMC_BOOTAE_0 (SDHC_EISTR_EMMC_BOOTAE_0_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_1 (SDHC_EISTR_EMMC_BOOTAE_1_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTR_EMMC) MASK Register */
+
+/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */
+ uint16_t CINS:1; /*!< bit: 6 Card Insertion Status Enable */
+ uint16_t CREM:1; /*!< bit: 7 Card Removal Status Enable */
+ uint16_t CINT:1; /*!< bit: 8 Card Interrupt Status Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Status Enable */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_NISTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISTER_OFFSET 0x034 /**< \brief (SDHC_NISTER offset) Normal Interrupt Status Enable */
+#define SDHC_NISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTER reset_value) Normal Interrupt Status Enable */
+
+#define SDHC_NISTER_CMDC_Pos 0 /**< \brief (SDHC_NISTER) Command Complete Status Enable */
+#define SDHC_NISTER_CMDC (_U_(0x1) << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CMDC_MASKED (SDHC_NISTER_CMDC_MASKED_Val << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_CMDC_ENABLED (SDHC_NISTER_CMDC_ENABLED_Val << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_TRFC_Pos 1 /**< \brief (SDHC_NISTER) Transfer Complete Status Enable */
+#define SDHC_NISTER_TRFC (_U_(0x1) << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_TRFC_MASKED (SDHC_NISTER_TRFC_MASKED_Val << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_TRFC_ENABLED (SDHC_NISTER_TRFC_ENABLED_Val << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_BLKGE_Pos 2 /**< \brief (SDHC_NISTER) Block Gap Event Status Enable */
+#define SDHC_NISTER_BLKGE (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BLKGE_MASKED (SDHC_NISTER_BLKGE_MASKED_Val << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_BLKGE_ENABLED (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_DMAINT_Pos 3 /**< \brief (SDHC_NISTER) DMA Interrupt Status Enable */
+#define SDHC_NISTER_DMAINT (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_DMAINT_MASKED (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_DMAINT_ENABLED (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER) Buffer Write Ready Status Enable */
+#define SDHC_NISTER_BWRRDY (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BWRRDY_MASKED (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BWRRDY_ENABLED (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER) Buffer Read Ready Status Enable */
+#define SDHC_NISTER_BRDRDY (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BRDRDY_MASKED (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_BRDRDY_ENABLED (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_CINS_Pos 6 /**< \brief (SDHC_NISTER) Card Insertion Status Enable */
+#define SDHC_NISTER_CINS (_U_(0x1) << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CINS_MASKED (SDHC_NISTER_CINS_MASKED_Val << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CINS_ENABLED (SDHC_NISTER_CINS_ENABLED_Val << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CREM_Pos 7 /**< \brief (SDHC_NISTER) Card Removal Status Enable */
+#define SDHC_NISTER_CREM (_U_(0x1) << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CREM_MASKED (SDHC_NISTER_CREM_MASKED_Val << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CREM_ENABLED (SDHC_NISTER_CREM_ENABLED_Val << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CINT_Pos 8 /**< \brief (SDHC_NISTER) Card Interrupt Status Enable */
+#define SDHC_NISTER_CINT (_U_(0x1) << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */
+#define SDHC_NISTER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CINT_MASKED (SDHC_NISTER_CINT_MASKED_Val << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_CINT_ENABLED (SDHC_NISTER_CINT_ENABLED_Val << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_MASK _U_(0x01FF) /**< \brief (SDHC_NISTER) MASK Register */
+
+// EMMC mode
+#define SDHC_NISTER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTER_EMMC) Command Complete Status Enable */
+#define SDHC_NISTER_EMMC_CMDC (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTER_EMMC) Transfer Complete Status Enable */
+#define SDHC_NISTER_EMMC_TRFC (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTER_EMMC) Block Gap Event Status Enable */
+#define SDHC_NISTER_EMMC_BLKGE (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTER_EMMC) DMA Interrupt Status Enable */
+#define SDHC_NISTER_EMMC_DMAINT (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER_EMMC) Buffer Write Ready Status Enable */
+#define SDHC_NISTER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER_EMMC) Buffer Read Ready Status Enable */
+#define SDHC_NISTER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTER_EMMC) Boot Acknowledge Received Status Enable */
+#define SDHC_NISTER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)
+#define SDHC_NISTER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISTER_EMMC) MASK Register */
+
+/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Status Enable */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_EISTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISTER_OFFSET 0x036 /**< \brief (SDHC_EISTER offset) Error Interrupt Status Enable */
+#define SDHC_EISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTER reset_value) Error Interrupt Status Enable */
+
+#define SDHC_EISTER_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER) Command Timeout Error Status Enable */
+#define SDHC_EISTER_CMDTEO (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDTEO_MASKED (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDTEO_ENABLED (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER) Command CRC Error Status Enable */
+#define SDHC_EISTER_CMDCRC (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDCRC_MASKED (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDCRC_ENABLED (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDEND_Pos 2 /**< \brief (SDHC_EISTER) Command End Bit Error Status Enable */
+#define SDHC_EISTER_CMDEND (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDEND_MASKED (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDEND_ENABLED (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER) Command Index Error Status Enable */
+#define SDHC_EISTER_CMDIDX (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDIDX_MASKED (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_CMDIDX_ENABLED (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_DATTEO_Pos 4 /**< \brief (SDHC_EISTER) Data Timeout Error Status Enable */
+#define SDHC_EISTER_DATTEO (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATTEO_MASKED (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATTEO_ENABLED (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATCRC_Pos 5 /**< \brief (SDHC_EISTER) Data CRC Error Status Enable */
+#define SDHC_EISTER_DATCRC (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATCRC_MASKED (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATCRC_ENABLED (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATEND_Pos 6 /**< \brief (SDHC_EISTER) Data End Bit Error Status Enable */
+#define SDHC_EISTER_DATEND (_U_(0x1) << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATEND_MASKED (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_DATEND_ENABLED (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_CURLIM_Pos 7 /**< \brief (SDHC_EISTER) Current Limit Error Status Enable */
+#define SDHC_EISTER_CURLIM (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CURLIM_MASKED (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_CURLIM_ENABLED (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_ACMD_Pos 8 /**< \brief (SDHC_EISTER) Auto CMD Error Status Enable */
+#define SDHC_EISTER_ACMD (_U_(0x1) << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_ACMD_MASKED (SDHC_EISTER_ACMD_MASKED_Val << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ACMD_ENABLED (SDHC_EISTER_ACMD_ENABLED_Val << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ADMA_Pos 9 /**< \brief (SDHC_EISTER) ADMA Error Status Enable */
+#define SDHC_EISTER_ADMA (_U_(0x1) << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */
+#define SDHC_EISTER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_ADMA_MASKED (SDHC_EISTER_ADMA_MASKED_Val << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_ADMA_ENABLED (SDHC_EISTER_ADMA_ENABLED_Val << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_MASK _U_(0x03FF) /**< \brief (SDHC_EISTER) MASK Register */
+
+// EMMC mode
+#define SDHC_EISTER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER_EMMC) Command Timeout Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER_EMMC) Command CRC Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTER_EMMC) Command End Bit Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDEND (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER_EMMC) Command Index Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTER_EMMC) Data Timeout Error Status Enable */
+#define SDHC_EISTER_EMMC_DATTEO (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTER_EMMC) Data CRC Error Status Enable */
+#define SDHC_EISTER_EMMC_DATCRC (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTER_EMMC) Data End Bit Error Status Enable */
+#define SDHC_EISTER_EMMC_DATEND (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTER_EMMC) Current Limit Error Status Enable */
+#define SDHC_EISTER_EMMC_CURLIM (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTER_EMMC) Auto CMD Error Status Enable */
+#define SDHC_EISTER_EMMC_ACMD (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTER_EMMC) ADMA Error Status Enable */
+#define SDHC_EISTER_EMMC_ADMA (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTER_EMMC) Boot Acknowledge Error Status Enable */
+#define SDHC_EISTER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)
+#define SDHC_EISTER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTER_EMMC) MASK Register */
+
+/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */
+ uint16_t CINS:1; /*!< bit: 6 Card Insertion Signal Enable */
+ uint16_t CREM:1; /*!< bit: 7 Card Removal Signal Enable */
+ uint16_t CINT:1; /*!< bit: 8 Card Interrupt Signal Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */
+ uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */
+ uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */
+ uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */
+ uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */
+ uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Signal Enable */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_NISIER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISIER_OFFSET 0x038 /**< \brief (SDHC_NISIER offset) Normal Interrupt Signal Enable */
+#define SDHC_NISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISIER reset_value) Normal Interrupt Signal Enable */
+
+#define SDHC_NISIER_CMDC_Pos 0 /**< \brief (SDHC_NISIER) Command Complete Signal Enable */
+#define SDHC_NISIER_CMDC (_U_(0x1) << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CMDC_MASKED (SDHC_NISIER_CMDC_MASKED_Val << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_CMDC_ENABLED (SDHC_NISIER_CMDC_ENABLED_Val << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_TRFC_Pos 1 /**< \brief (SDHC_NISIER) Transfer Complete Signal Enable */
+#define SDHC_NISIER_TRFC (_U_(0x1) << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_TRFC_MASKED (SDHC_NISIER_TRFC_MASKED_Val << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_TRFC_ENABLED (SDHC_NISIER_TRFC_ENABLED_Val << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_BLKGE_Pos 2 /**< \brief (SDHC_NISIER) Block Gap Event Signal Enable */
+#define SDHC_NISIER_BLKGE (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BLKGE_MASKED (SDHC_NISIER_BLKGE_MASKED_Val << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_BLKGE_ENABLED (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_DMAINT_Pos 3 /**< \brief (SDHC_NISIER) DMA Interrupt Signal Enable */
+#define SDHC_NISIER_DMAINT (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_DMAINT_MASKED (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_DMAINT_ENABLED (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER) Buffer Write Ready Signal Enable */
+#define SDHC_NISIER_BWRRDY (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BWRRDY_MASKED (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BWRRDY_ENABLED (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER) Buffer Read Ready Signal Enable */
+#define SDHC_NISIER_BRDRDY (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BRDRDY_MASKED (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_BRDRDY_ENABLED (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_CINS_Pos 6 /**< \brief (SDHC_NISIER) Card Insertion Signal Enable */
+#define SDHC_NISIER_CINS (_U_(0x1) << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CINS_MASKED (SDHC_NISIER_CINS_MASKED_Val << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CINS_ENABLED (SDHC_NISIER_CINS_ENABLED_Val << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CREM_Pos 7 /**< \brief (SDHC_NISIER) Card Removal Signal Enable */
+#define SDHC_NISIER_CREM (_U_(0x1) << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CREM_MASKED (SDHC_NISIER_CREM_MASKED_Val << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CREM_ENABLED (SDHC_NISIER_CREM_ENABLED_Val << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CINT_Pos 8 /**< \brief (SDHC_NISIER) Card Interrupt Signal Enable */
+#define SDHC_NISIER_CINT (_U_(0x1) << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */
+#define SDHC_NISIER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CINT_MASKED (SDHC_NISIER_CINT_MASKED_Val << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_CINT_ENABLED (SDHC_NISIER_CINT_ENABLED_Val << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_MASK _U_(0x01FF) /**< \brief (SDHC_NISIER) MASK Register */
+
+// EMMC mode
+#define SDHC_NISIER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISIER_EMMC) Command Complete Signal Enable */
+#define SDHC_NISIER_EMMC_CMDC (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISIER_EMMC) Transfer Complete Signal Enable */
+#define SDHC_NISIER_EMMC_TRFC (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISIER_EMMC) Block Gap Event Signal Enable */
+#define SDHC_NISIER_EMMC_BLKGE (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISIER_EMMC) DMA Interrupt Signal Enable */
+#define SDHC_NISIER_EMMC_DMAINT (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER_EMMC) Buffer Write Ready Signal Enable */
+#define SDHC_NISIER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER_EMMC) Buffer Read Ready Signal Enable */
+#define SDHC_NISIER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISIER_EMMC) Boot Acknowledge Received Signal Enable */
+#define SDHC_NISIER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)
+#define SDHC_NISIER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISIER_EMMC) MASK Register */
+
+/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */
+ uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */
+ uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */
+ uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */
+ uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */
+ uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */
+ uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */
+ uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */
+ uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */
+ uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Signal Enable */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_EISIER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISIER_OFFSET 0x03A /**< \brief (SDHC_EISIER offset) Error Interrupt Signal Enable */
+#define SDHC_EISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISIER reset_value) Error Interrupt Signal Enable */
+
+#define SDHC_EISIER_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER) Command Timeout Error Signal Enable */
+#define SDHC_EISIER_CMDTEO (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDTEO_MASKED (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDTEO_ENABLED (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER) Command CRC Error Signal Enable */
+#define SDHC_EISIER_CMDCRC (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDCRC_MASKED (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDCRC_ENABLED (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDEND_Pos 2 /**< \brief (SDHC_EISIER) Command End Bit Error Signal Enable */
+#define SDHC_EISIER_CMDEND (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDEND_MASKED (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDEND_ENABLED (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER) Command Index Error Signal Enable */
+#define SDHC_EISIER_CMDIDX (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDIDX_MASKED (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_CMDIDX_ENABLED (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_DATTEO_Pos 4 /**< \brief (SDHC_EISIER) Data Timeout Error Signal Enable */
+#define SDHC_EISIER_DATTEO (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATTEO_MASKED (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATTEO_ENABLED (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATCRC_Pos 5 /**< \brief (SDHC_EISIER) Data CRC Error Signal Enable */
+#define SDHC_EISIER_DATCRC (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATCRC_MASKED (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATCRC_ENABLED (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATEND_Pos 6 /**< \brief (SDHC_EISIER) Data End Bit Error Signal Enable */
+#define SDHC_EISIER_DATEND (_U_(0x1) << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATEND_MASKED (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_DATEND_ENABLED (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_CURLIM_Pos 7 /**< \brief (SDHC_EISIER) Current Limit Error Signal Enable */
+#define SDHC_EISIER_CURLIM (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CURLIM_MASKED (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_CURLIM_ENABLED (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_ACMD_Pos 8 /**< \brief (SDHC_EISIER) Auto CMD Error Signal Enable */
+#define SDHC_EISIER_ACMD (_U_(0x1) << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_ACMD_MASKED (SDHC_EISIER_ACMD_MASKED_Val << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ACMD_ENABLED (SDHC_EISIER_ACMD_ENABLED_Val << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ADMA_Pos 9 /**< \brief (SDHC_EISIER) ADMA Error Signal Enable */
+#define SDHC_EISIER_ADMA (_U_(0x1) << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */
+#define SDHC_EISIER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_ADMA_MASKED (SDHC_EISIER_ADMA_MASKED_Val << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_ADMA_ENABLED (SDHC_EISIER_ADMA_ENABLED_Val << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_MASK _U_(0x03FF) /**< \brief (SDHC_EISIER) MASK Register */
+
+// EMMC mode
+#define SDHC_EISIER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER_EMMC) Command Timeout Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER_EMMC) Command CRC Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISIER_EMMC) Command End Bit Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDEND (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER_EMMC) Command Index Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISIER_EMMC) Data Timeout Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATTEO (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISIER_EMMC) Data CRC Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATCRC (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISIER_EMMC) Data End Bit Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATEND (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISIER_EMMC) Current Limit Error Signal Enable */
+#define SDHC_EISIER_EMMC_CURLIM (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISIER_EMMC) Auto CMD Error Signal Enable */
+#define SDHC_EISIER_EMMC_ACMD (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISIER_EMMC) ADMA Error Signal Enable */
+#define SDHC_EISIER_EMMC_ADMA (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISIER_EMMC) Boot Acknowledge Error Signal Enable */
+#define SDHC_EISIER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)
+#define SDHC_EISIER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISIER_EMMC) MASK Register */
+
+/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/ 16) Auto CMD Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ACMD12NE:1; /*!< bit: 0 Auto CMD12 Not Executed */
+ uint16_t ACMDTEO:1; /*!< bit: 1 Auto CMD Timeout Error */
+ uint16_t ACMDCRC:1; /*!< bit: 2 Auto CMD CRC Error */
+ uint16_t ACMDEND:1; /*!< bit: 3 Auto CMD End Bit Error */
+ uint16_t ACMDIDX:1; /*!< bit: 4 Auto CMD Index Error */
+ uint16_t :2; /*!< bit: 5.. 6 Reserved */
+ uint16_t CMDNI:1; /*!< bit: 7 Command not Issued By Auto CMD12 Error */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_ACESR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ACESR_OFFSET 0x03C /**< \brief (SDHC_ACESR offset) Auto CMD Error Status */
+#define SDHC_ACESR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_ACESR reset_value) Auto CMD Error Status */
+
+#define SDHC_ACESR_ACMD12NE_Pos 0 /**< \brief (SDHC_ACESR) Auto CMD12 Not Executed */
+#define SDHC_ACESR_ACMD12NE (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMD12NE_EXEC_Val _U_(0x0) /**< \brief (SDHC_ACESR) Executed */
+#define SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not executed */
+#define SDHC_ACESR_ACMD12NE_EXEC (SDHC_ACESR_ACMD12NE_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMDTEO_Pos 1 /**< \brief (SDHC_ACESR) Auto CMD Timeout Error */
+#define SDHC_ACESR_ACMDTEO (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Timeout */
+#define SDHC_ACESR_ACMDTEO_NO (SDHC_ACESR_ACMDTEO_NO_Val << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDTEO_YES (SDHC_ACESR_ACMDTEO_YES_Val << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDCRC_Pos 2 /**< \brief (SDHC_ACESR) Auto CMD CRC Error */
+#define SDHC_ACESR_ACMDCRC (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) CRC Error Generated */
+#define SDHC_ACESR_ACMDCRC_NO (SDHC_ACESR_ACMDCRC_NO_Val << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDCRC_YES (SDHC_ACESR_ACMDCRC_YES_Val << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDEND_Pos 3 /**< \brief (SDHC_ACESR) Auto CMD End Bit Error */
+#define SDHC_ACESR_ACMDEND (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) End Bit Error Generated */
+#define SDHC_ACESR_ACMDEND_NO (SDHC_ACESR_ACMDEND_NO_Val << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDEND_YES (SDHC_ACESR_ACMDEND_YES_Val << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDIDX_Pos 4 /**< \brief (SDHC_ACESR) Auto CMD Index Error */
+#define SDHC_ACESR_ACMDIDX (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Error */
+#define SDHC_ACESR_ACMDIDX_NO (SDHC_ACESR_ACMDIDX_NO_Val << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_ACMDIDX_YES (SDHC_ACESR_ACMDIDX_YES_Val << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_CMDNI_Pos 7 /**< \brief (SDHC_ACESR) Command not Issued By Auto CMD12 Error */
+#define SDHC_ACESR_CMDNI (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_CMDNI_OK_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */
+#define SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not Issued */
+#define SDHC_ACESR_CMDNI_OK (SDHC_ACESR_CMDNI_OK_Val << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_MASK _U_(0x009F) /**< \brief (SDHC_ACESR) MASK Register */
+
+/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t UHSMS:3; /*!< bit: 0.. 2 UHS Mode Select */
+ uint16_t VS18EN:1; /*!< bit: 3 1.8V Signaling Enable */
+ uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */
+ uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */
+ uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */
+ uint16_t :6; /*!< bit: 8..13 Reserved */
+ uint16_t ASINTEN:1; /*!< bit: 14 Asynchronous Interrupt Enable */
+ uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */
+ } bit; /*!< Structure used for bit access */
+ struct { // EMMC mode
+ uint16_t HS200EN:4; /*!< bit: 0.. 3 HS200 Mode Enable */
+ uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */
+ uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */
+ uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */
+ uint16_t :7; /*!< bit: 8..14 Reserved */
+ uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */
+ } EMMC; /*!< Structure used for EMMC */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_HC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HC2R_OFFSET 0x03E /**< \brief (SDHC_HC2R offset) Host Control 2 */
+#define SDHC_HC2R_RESETVALUE _U_(0x0000) /**< \brief (SDHC_HC2R reset_value) Host Control 2 */
+
+#define SDHC_HC2R_UHSMS_Pos 0 /**< \brief (SDHC_HC2R) UHS Mode Select */
+#define SDHC_HC2R_UHSMS_Msk (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS(value) (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))
+#define SDHC_HC2R_UHSMS_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDR12 */
+#define SDHC_HC2R_UHSMS_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R) SDR25 */
+#define SDHC_HC2R_UHSMS_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R) SDR50 */
+#define SDHC_HC2R_UHSMS_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R) SDR104 */
+#define SDHC_HC2R_UHSMS_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R) DDR50 */
+#define SDHC_HC2R_UHSMS_SDR12 (SDHC_HC2R_UHSMS_SDR12_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR25 (SDHC_HC2R_UHSMS_SDR25_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR50 (SDHC_HC2R_UHSMS_SDR50_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR104 (SDHC_HC2R_UHSMS_SDR104_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_DDR50 (SDHC_HC2R_UHSMS_DDR50_Val << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_VS18EN_Pos 3 /**< \brief (SDHC_HC2R) 1.8V Signaling Enable */
+#define SDHC_HC2R_VS18EN (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_VS18EN_S33V_Val _U_(0x0) /**< \brief (SDHC_HC2R) 3.3V Signaling */
+#define SDHC_HC2R_VS18EN_S18V_Val _U_(0x1) /**< \brief (SDHC_HC2R) 1.8V Signaling */
+#define SDHC_HC2R_VS18EN_S33V (SDHC_HC2R_VS18EN_S33V_Val << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_VS18EN_S18V (SDHC_HC2R_VS18EN_S18V_Val << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R) Driver Strength Select */
+#define SDHC_HC2R_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL(value) (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))
+#define SDHC_HC2R_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R) Driver Type B is Selected (Default) */
+#define SDHC_HC2R_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R) Driver Type A is Selected */
+#define SDHC_HC2R_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R) Driver Type C is Selected */
+#define SDHC_HC2R_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R) Driver Type D is Selected */
+#define SDHC_HC2R_DRVSEL_B (SDHC_HC2R_DRVSEL_B_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_A (SDHC_HC2R_DRVSEL_A_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_C (SDHC_HC2R_DRVSEL_C_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_D (SDHC_HC2R_DRVSEL_D_Val << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_EXTUN_Pos 6 /**< \brief (SDHC_HC2R) Execute Tuning */
+#define SDHC_HC2R_EXTUN (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R) Not Tuned or Tuning Completed */
+#define SDHC_HC2R_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Execute Tuning */
+#define SDHC_HC2R_EXTUN_NO (SDHC_HC2R_EXTUN_NO_Val << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_EXTUN_REQUESTED (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R) Sampling Clock Select */
+#define SDHC_HC2R_SLCKSEL (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Fixed clock is used to sample data */
+#define SDHC_HC2R_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Tuned clock is used to sample data */
+#define SDHC_HC2R_SLCKSEL_FIXED (SDHC_HC2R_SLCKSEL_FIXED_Val << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_SLCKSEL_TUNED (SDHC_HC2R_SLCKSEL_TUNED_Val << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_ASINTEN_Pos 14 /**< \brief (SDHC_HC2R) Asynchronous Interrupt Enable */
+#define SDHC_HC2R_ASINTEN (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_ASINTEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Disabled */
+#define SDHC_HC2R_ASINTEN_ENABLED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Enabled */
+#define SDHC_HC2R_ASINTEN_DISABLED (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_ASINTEN_ENABLED (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_PVALEN_Pos 15 /**< \brief (SDHC_HC2R) Preset Value Enable */
+#define SDHC_HC2R_PVALEN (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */
+#define SDHC_HC2R_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */
+#define SDHC_HC2R_PVALEN_HOST (SDHC_HC2R_PVALEN_HOST_Val << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_PVALEN_AUTO (SDHC_HC2R_PVALEN_AUTO_Val << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_MASK _U_(0xC0FF) /**< \brief (SDHC_HC2R) MASK Register */
+
+// EMMC mode
+#define SDHC_HC2R_EMMC_HS200EN_Pos 0 /**< \brief (SDHC_HC2R_EMMC) HS200 Mode Enable */
+#define SDHC_HC2R_EMMC_HS200EN_Msk (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))
+#define SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDR12 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) SDR25 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) SDR50 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) SDR104 */
+#define SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R_EMMC) DDR50 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R_EMMC) Driver Strength Select */
+#define SDHC_HC2R_EMMC_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))
+#define SDHC_HC2R_EMMC_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Driver Type B is Selected (Default) */
+#define SDHC_HC2R_EMMC_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Driver Type A is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) Driver Type C is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) Driver Type D is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_B (SDHC_HC2R_EMMC_DRVSEL_B_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_A (SDHC_HC2R_EMMC_DRVSEL_A_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_C (SDHC_HC2R_EMMC_DRVSEL_C_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_D (SDHC_HC2R_EMMC_DRVSEL_D_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_Pos 6 /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
+#define SDHC_HC2R_EMMC_EXTUN (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Not Tuned or Tuning Completed */
+#define SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
+#define SDHC_HC2R_EMMC_EXTUN_NO (SDHC_HC2R_EMMC_EXTUN_NO_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R_EMMC) Sampling Clock Select */
+#define SDHC_HC2R_EMMC_SLCKSEL (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Fixed clock is used to sample data */
+#define SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Tuned clock is used to sample data */
+#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_Pos 15 /**< \brief (SDHC_HC2R_EMMC) Preset Value Enable */
+#define SDHC_HC2R_EMMC_PVALEN (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDCLK and Driver Strength are controlled by Host Controller */
+#define SDHC_HC2R_EMMC_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Automatic Selection by Preset Value is Enabled */
+#define SDHC_HC2R_EMMC_PVALEN_HOST (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_AUTO (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_MASK _U_(0x80FF) /**< \brief (SDHC_HC2R_EMMC) MASK Register */
+
+/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/ 32) Capabilities 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t TEOCLKF:6; /*!< bit: 0.. 5 Timeout Clock Frequency */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t TEOCLKU:1; /*!< bit: 7 Timeout Clock Unit */
+ uint32_t BASECLKF:8; /*!< bit: 8..15 Base Clock Frequency */
+ uint32_t MAXBLKL:2; /*!< bit: 16..17 Max Block Length */
+ uint32_t ED8SUP:1; /*!< bit: 18 8-bit Support for Embedded Device */
+ uint32_t ADMA2SUP:1; /*!< bit: 19 ADMA2 Support */
+ uint32_t :1; /*!< bit: 20 Reserved */
+ uint32_t HSSUP:1; /*!< bit: 21 High Speed Support */
+ uint32_t SDMASUP:1; /*!< bit: 22 SDMA Support */
+ uint32_t SRSUP:1; /*!< bit: 23 Suspend/Resume Support */
+ uint32_t V33VSUP:1; /*!< bit: 24 Voltage Support 3.3V */
+ uint32_t V30VSUP:1; /*!< bit: 25 Voltage Support 3.0V */
+ uint32_t V18VSUP:1; /*!< bit: 26 Voltage Support 1.8V */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t SB64SUP:1; /*!< bit: 28 64-Bit System Bus Support */
+ uint32_t ASINTSUP:1; /*!< bit: 29 Asynchronous Interrupt Support */
+ uint32_t SLTYPE:2; /*!< bit: 30..31 Slot Type */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CA0R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CA0R_OFFSET 0x040 /**< \brief (SDHC_CA0R offset) Capabilities 0 */
+#define SDHC_CA0R_RESETVALUE _U_(0x27E80080) /**< \brief (SDHC_CA0R reset_value) Capabilities 0 */
+
+#define SDHC_CA0R_TEOCLKF_Pos 0 /**< \brief (SDHC_CA0R) Timeout Clock Frequency */
+#define SDHC_CA0R_TEOCLKF_Msk (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)
+#define SDHC_CA0R_TEOCLKF(value) (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))
+#define SDHC_CA0R_TEOCLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */
+#define SDHC_CA0R_TEOCLKF_OTHER (SDHC_CA0R_TEOCLKF_OTHER_Val << SDHC_CA0R_TEOCLKF_Pos)
+#define SDHC_CA0R_TEOCLKU_Pos 7 /**< \brief (SDHC_CA0R) Timeout Clock Unit */
+#define SDHC_CA0R_TEOCLKU (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_TEOCLKU_KHZ_Val _U_(0x0) /**< \brief (SDHC_CA0R) kHz */
+#define SDHC_CA0R_TEOCLKU_MHZ_Val _U_(0x1) /**< \brief (SDHC_CA0R) MHz */
+#define SDHC_CA0R_TEOCLKU_KHZ (SDHC_CA0R_TEOCLKU_KHZ_Val << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_TEOCLKU_MHZ (SDHC_CA0R_TEOCLKU_MHZ_Val << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_BASECLKF_Pos 8 /**< \brief (SDHC_CA0R) Base Clock Frequency */
+#define SDHC_CA0R_BASECLKF_Msk (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)
+#define SDHC_CA0R_BASECLKF(value) (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))
+#define SDHC_CA0R_BASECLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */
+#define SDHC_CA0R_BASECLKF_OTHER (SDHC_CA0R_BASECLKF_OTHER_Val << SDHC_CA0R_BASECLKF_Pos)
+#define SDHC_CA0R_MAXBLKL_Pos 16 /**< \brief (SDHC_CA0R) Max Block Length */
+#define SDHC_CA0R_MAXBLKL_Msk (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL(value) (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))
+#define SDHC_CA0R_MAXBLKL_512_Val _U_(0x0) /**< \brief (SDHC_CA0R) 512 bytes */
+#define SDHC_CA0R_MAXBLKL_1024_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1024 bytes */
+#define SDHC_CA0R_MAXBLKL_2048_Val _U_(0x2) /**< \brief (SDHC_CA0R) 2048 bytes */
+#define SDHC_CA0R_MAXBLKL_512 (SDHC_CA0R_MAXBLKL_512_Val << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL_1024 (SDHC_CA0R_MAXBLKL_1024_Val << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL_2048 (SDHC_CA0R_MAXBLKL_2048_Val << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_ED8SUP_Pos 18 /**< \brief (SDHC_CA0R) 8-bit Support for Embedded Device */
+#define SDHC_CA0R_ED8SUP (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ED8SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 8-bit Bus Width not Supported */
+#define SDHC_CA0R_ED8SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 8-bit Bus Width Supported */
+#define SDHC_CA0R_ED8SUP_NO (SDHC_CA0R_ED8SUP_NO_Val << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ED8SUP_YES (SDHC_CA0R_ED8SUP_YES_Val << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_Pos 19 /**< \brief (SDHC_CA0R) ADMA2 Support */
+#define SDHC_CA0R_ADMA2SUP (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) ADMA2 not Supported */
+#define SDHC_CA0R_ADMA2SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) ADMA2 Supported */
+#define SDHC_CA0R_ADMA2SUP_NO (SDHC_CA0R_ADMA2SUP_NO_Val << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_YES (SDHC_CA0R_ADMA2SUP_YES_Val << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_HSSUP_Pos 21 /**< \brief (SDHC_CA0R) High Speed Support */
+#define SDHC_CA0R_HSSUP (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_HSSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) High Speed not Supported */
+#define SDHC_CA0R_HSSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) High Speed Supported */
+#define SDHC_CA0R_HSSUP_NO (SDHC_CA0R_HSSUP_NO_Val << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_HSSUP_YES (SDHC_CA0R_HSSUP_YES_Val << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_SDMASUP_Pos 22 /**< \brief (SDHC_CA0R) SDMA Support */
+#define SDHC_CA0R_SDMASUP (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SDMASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) SDMA not Supported */
+#define SDHC_CA0R_SDMASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) SDMA Supported */
+#define SDHC_CA0R_SDMASUP_NO (SDHC_CA0R_SDMASUP_NO_Val << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SDMASUP_YES (SDHC_CA0R_SDMASUP_YES_Val << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SRSUP_Pos 23 /**< \brief (SDHC_CA0R) Suspend/Resume Support */
+#define SDHC_CA0R_SRSUP (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_SRSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Suspend/Resume not Supported */
+#define SDHC_CA0R_SRSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Suspend/Resume Supported */
+#define SDHC_CA0R_SRSUP_NO (SDHC_CA0R_SRSUP_NO_Val << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_SRSUP_YES (SDHC_CA0R_SRSUP_YES_Val << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_V33VSUP_Pos 24 /**< \brief (SDHC_CA0R) Voltage Support 3.3V */
+#define SDHC_CA0R_V33VSUP (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V33VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.3V Not Supported */
+#define SDHC_CA0R_V33VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.3V Supported */
+#define SDHC_CA0R_V33VSUP_NO (SDHC_CA0R_V33VSUP_NO_Val << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V33VSUP_YES (SDHC_CA0R_V33VSUP_YES_Val << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_Pos 25 /**< \brief (SDHC_CA0R) Voltage Support 3.0V */
+#define SDHC_CA0R_V30VSUP (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.0V Not Supported */
+#define SDHC_CA0R_V30VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.0V Supported */
+#define SDHC_CA0R_V30VSUP_NO (SDHC_CA0R_V30VSUP_NO_Val << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_YES (SDHC_CA0R_V30VSUP_YES_Val << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_Pos 26 /**< \brief (SDHC_CA0R) Voltage Support 1.8V */
+#define SDHC_CA0R_V18VSUP (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 1.8V Not Supported */
+#define SDHC_CA0R_V18VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1.8V Supported */
+#define SDHC_CA0R_V18VSUP_NO (SDHC_CA0R_V18VSUP_NO_Val << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_YES (SDHC_CA0R_V18VSUP_YES_Val << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_SB64SUP_Pos 28 /**< \brief (SDHC_CA0R) 64-Bit System Bus Support */
+#define SDHC_CA0R_SB64SUP (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_SB64SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 32-bit Address Descriptors and System Bus */
+#define SDHC_CA0R_SB64SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 64-bit Address Descriptors and System Bus */
+#define SDHC_CA0R_SB64SUP_NO (SDHC_CA0R_SB64SUP_NO_Val << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_SB64SUP_YES (SDHC_CA0R_SB64SUP_YES_Val << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_ASINTSUP_Pos 29 /**< \brief (SDHC_CA0R) Asynchronous Interrupt Support */
+#define SDHC_CA0R_ASINTSUP (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_ASINTSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Asynchronous Interrupt not Supported */
+#define SDHC_CA0R_ASINTSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Asynchronous Interrupt supported */
+#define SDHC_CA0R_ASINTSUP_NO (SDHC_CA0R_ASINTSUP_NO_Val << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_ASINTSUP_YES (SDHC_CA0R_ASINTSUP_YES_Val << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_SLTYPE_Pos 30 /**< \brief (SDHC_CA0R) Slot Type */
+#define SDHC_CA0R_SLTYPE_Msk (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_SLTYPE(value) (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))
+#define SDHC_CA0R_SLTYPE_REMOVABLE_Val _U_(0x0) /**< \brief (SDHC_CA0R) Removable Card Slot */
+#define SDHC_CA0R_SLTYPE_EMBEDDED_Val _U_(0x1) /**< \brief (SDHC_CA0R) Embedded Slot for One Device */
+#define SDHC_CA0R_SLTYPE_REMOVABLE (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_SLTYPE_EMBEDDED (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_MASK _U_(0xF7EFFFBF) /**< \brief (SDHC_CA0R) MASK Register */
+
+/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/ 32) Capabilities 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SDR50SUP:1; /*!< bit: 0 SDR50 Support */
+ uint32_t SDR104SUP:1; /*!< bit: 1 SDR104 Support */
+ uint32_t DDR50SUP:1; /*!< bit: 2 DDR50 Support */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t DRVASUP:1; /*!< bit: 4 Driver Type A Support */
+ uint32_t DRVCSUP:1; /*!< bit: 5 Driver Type C Support */
+ uint32_t DRVDSUP:1; /*!< bit: 6 Driver Type D Support */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TCNTRT:4; /*!< bit: 8..11 Timer Count for Re-Tuning */
+ uint32_t :1; /*!< bit: 12 Reserved */
+ uint32_t TSDR50:1; /*!< bit: 13 Use Tuning for SDR50 */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t CLKMULT:8; /*!< bit: 16..23 Clock Multiplier */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CA1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CA1R_OFFSET 0x044 /**< \brief (SDHC_CA1R offset) Capabilities 1 */
+#define SDHC_CA1R_RESETVALUE _U_(0x00000070) /**< \brief (SDHC_CA1R reset_value) Capabilities 1 */
+
+#define SDHC_CA1R_SDR50SUP_Pos 0 /**< \brief (SDHC_CA1R) SDR50 Support */
+#define SDHC_CA1R_SDR50SUP (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 is Not Supported */
+#define SDHC_CA1R_SDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 is Supported */
+#define SDHC_CA1R_SDR50SUP_NO (SDHC_CA1R_SDR50SUP_NO_Val << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR50SUP_YES (SDHC_CA1R_SDR50SUP_YES_Val << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_Pos 1 /**< \brief (SDHC_CA1R) SDR104 Support */
+#define SDHC_CA1R_SDR104SUP (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR104 is Not Supported */
+#define SDHC_CA1R_SDR104SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR104 is Supported */
+#define SDHC_CA1R_SDR104SUP_NO (SDHC_CA1R_SDR104SUP_NO_Val << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_YES (SDHC_CA1R_SDR104SUP_YES_Val << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_Pos 2 /**< \brief (SDHC_CA1R) DDR50 Support */
+#define SDHC_CA1R_DDR50SUP (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) DDR50 is Not Supported */
+#define SDHC_CA1R_DDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) DDR50 is Supported */
+#define SDHC_CA1R_DDR50SUP_NO (SDHC_CA1R_DDR50SUP_NO_Val << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_YES (SDHC_CA1R_DDR50SUP_YES_Val << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DRVASUP_Pos 4 /**< \brief (SDHC_CA1R) Driver Type A Support */
+#define SDHC_CA1R_DRVASUP (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type A is Not Supported */
+#define SDHC_CA1R_DRVASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type A is Supported */
+#define SDHC_CA1R_DRVASUP_NO (SDHC_CA1R_DRVASUP_NO_Val << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVASUP_YES (SDHC_CA1R_DRVASUP_YES_Val << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVCSUP_Pos 5 /**< \brief (SDHC_CA1R) Driver Type C Support */
+#define SDHC_CA1R_DRVCSUP (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVCSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type C is Not Supported */
+#define SDHC_CA1R_DRVCSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type C is Supported */
+#define SDHC_CA1R_DRVCSUP_NO (SDHC_CA1R_DRVCSUP_NO_Val << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVCSUP_YES (SDHC_CA1R_DRVCSUP_YES_Val << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_Pos 6 /**< \brief (SDHC_CA1R) Driver Type D Support */
+#define SDHC_CA1R_DRVDSUP (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type D is Not Supported */
+#define SDHC_CA1R_DRVDSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type D is Supported */
+#define SDHC_CA1R_DRVDSUP_NO (SDHC_CA1R_DRVDSUP_NO_Val << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_YES (SDHC_CA1R_DRVDSUP_YES_Val << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_TCNTRT_Pos 8 /**< \brief (SDHC_CA1R) Timer Count for Re-Tuning */
+#define SDHC_CA1R_TCNTRT_Msk (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT(value) (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))
+#define SDHC_CA1R_TCNTRT_DISABLED_Val _U_(0x0) /**< \brief (SDHC_CA1R) Re-Tuning Timer disabled */
+#define SDHC_CA1R_TCNTRT_1S_Val _U_(0x1) /**< \brief (SDHC_CA1R) 1 second */
+#define SDHC_CA1R_TCNTRT_2S_Val _U_(0x2) /**< \brief (SDHC_CA1R) 2 seconds */
+#define SDHC_CA1R_TCNTRT_4S_Val _U_(0x3) /**< \brief (SDHC_CA1R) 4 seconds */
+#define SDHC_CA1R_TCNTRT_8S_Val _U_(0x4) /**< \brief (SDHC_CA1R) 8 seconds */
+#define SDHC_CA1R_TCNTRT_16S_Val _U_(0x5) /**< \brief (SDHC_CA1R) 16 seconds */
+#define SDHC_CA1R_TCNTRT_32S_Val _U_(0x6) /**< \brief (SDHC_CA1R) 32 seconds */
+#define SDHC_CA1R_TCNTRT_64S_Val _U_(0x7) /**< \brief (SDHC_CA1R) 64 seconds */
+#define SDHC_CA1R_TCNTRT_128S_Val _U_(0x8) /**< \brief (SDHC_CA1R) 128 seconds */
+#define SDHC_CA1R_TCNTRT_256S_Val _U_(0x9) /**< \brief (SDHC_CA1R) 256 seconds */
+#define SDHC_CA1R_TCNTRT_512S_Val _U_(0xA) /**< \brief (SDHC_CA1R) 512 seconds */
+#define SDHC_CA1R_TCNTRT_1024S_Val _U_(0xB) /**< \brief (SDHC_CA1R) 1024 seconds */
+#define SDHC_CA1R_TCNTRT_OTHER_Val _U_(0xF) /**< \brief (SDHC_CA1R) Get information from other source */
+#define SDHC_CA1R_TCNTRT_DISABLED (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_1S (SDHC_CA1R_TCNTRT_1S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_2S (SDHC_CA1R_TCNTRT_2S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_4S (SDHC_CA1R_TCNTRT_4S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_8S (SDHC_CA1R_TCNTRT_8S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_16S (SDHC_CA1R_TCNTRT_16S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_32S (SDHC_CA1R_TCNTRT_32S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_64S (SDHC_CA1R_TCNTRT_64S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_128S (SDHC_CA1R_TCNTRT_128S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_256S (SDHC_CA1R_TCNTRT_256S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_512S (SDHC_CA1R_TCNTRT_512S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_1024S (SDHC_CA1R_TCNTRT_1024S_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_OTHER (SDHC_CA1R_TCNTRT_OTHER_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TSDR50_Pos 13 /**< \brief (SDHC_CA1R) Use Tuning for SDR50 */
+#define SDHC_CA1R_TSDR50 (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_TSDR50_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 does not require tuning */
+#define SDHC_CA1R_TSDR50_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 requires tuning */
+#define SDHC_CA1R_TSDR50_NO (SDHC_CA1R_TSDR50_NO_Val << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_TSDR50_YES (SDHC_CA1R_TSDR50_YES_Val << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_CLKMULT_Pos 16 /**< \brief (SDHC_CA1R) Clock Multiplier */
+#define SDHC_CA1R_CLKMULT_Msk (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)
+#define SDHC_CA1R_CLKMULT(value) (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))
+#define SDHC_CA1R_CLKMULT_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Clock Multiplier is Not Supported */
+#define SDHC_CA1R_CLKMULT_NO (SDHC_CA1R_CLKMULT_NO_Val << SDHC_CA1R_CLKMULT_Pos)
+#define SDHC_CA1R_MASK _U_(0x00FF2F77) /**< \brief (SDHC_CA1R) MASK Register */
+
+/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/ 32) Maximum Current Capabilities -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MAXCUR33V:8; /*!< bit: 0.. 7 Maximum Current for 3.3V */
+ uint32_t MAXCUR30V:8; /*!< bit: 8..15 Maximum Current for 3.0V */
+ uint32_t MAXCUR18V:8; /*!< bit: 16..23 Maximum Current for 1.8V */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_MCCAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MCCAR_OFFSET 0x048 /**< \brief (SDHC_MCCAR offset) Maximum Current Capabilities */
+#define SDHC_MCCAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_MCCAR reset_value) Maximum Current Capabilities */
+
+#define SDHC_MCCAR_MAXCUR33V_Pos 0 /**< \brief (SDHC_MCCAR) Maximum Current for 3.3V */
+#define SDHC_MCCAR_MAXCUR33V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))
+#define SDHC_MCCAR_MAXCUR33V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
+#define SDHC_MCCAR_MAXCUR33V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
+#define SDHC_MCCAR_MAXCUR33V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
+#define SDHC_MCCAR_MAXCUR33V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR33V_OTHER (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_4MA (SDHC_MCCAR_MAXCUR33V_4MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_8MA (SDHC_MCCAR_MAXCUR33V_8MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_12MA (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_Pos 8 /**< \brief (SDHC_MCCAR) Maximum Current for 3.0V */
+#define SDHC_MCCAR_MAXCUR30V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))
+#define SDHC_MCCAR_MAXCUR30V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
+#define SDHC_MCCAR_MAXCUR30V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
+#define SDHC_MCCAR_MAXCUR30V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
+#define SDHC_MCCAR_MAXCUR30V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR30V_OTHER (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_4MA (SDHC_MCCAR_MAXCUR30V_4MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_8MA (SDHC_MCCAR_MAXCUR30V_8MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_12MA (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_Pos 16 /**< \brief (SDHC_MCCAR) Maximum Current for 1.8V */
+#define SDHC_MCCAR_MAXCUR18V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))
+#define SDHC_MCCAR_MAXCUR18V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */
+#define SDHC_MCCAR_MAXCUR18V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */
+#define SDHC_MCCAR_MAXCUR18V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */
+#define SDHC_MCCAR_MAXCUR18V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR18V_OTHER (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_4MA (SDHC_MCCAR_MAXCUR18V_4MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_8MA (SDHC_MCCAR_MAXCUR18V_8MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_12MA (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MASK _U_(0x00FFFFFF) /**< \brief (SDHC_MCCAR) MASK Register */
+
+/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ACMD12NE:1; /*!< bit: 0 Force Event for Auto CMD12 Not Executed */
+ uint16_t ACMDTEO:1; /*!< bit: 1 Force Event for Auto CMD Timeout Error */
+ uint16_t ACMDCRC:1; /*!< bit: 2 Force Event for Auto CMD CRC Error */
+ uint16_t ACMDEND:1; /*!< bit: 3 Force Event for Auto CMD End Bit Error */
+ uint16_t ACMDIDX:1; /*!< bit: 4 Force Event for Auto CMD Index Error */
+ uint16_t :2; /*!< bit: 5.. 6 Reserved */
+ uint16_t CMDNI:1; /*!< bit: 7 Force Event for Command Not Issued By Auto CMD12 Error */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_FERACES_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_FERACES_OFFSET 0x050 /**< \brief (SDHC_FERACES offset) Force Event for Auto CMD Error Status */
+#define SDHC_FERACES_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FERACES reset_value) Force Event for Auto CMD Error Status */
+
+#define SDHC_FERACES_ACMD12NE_Pos 0 /**< \brief (SDHC_FERACES) Force Event for Auto CMD12 Not Executed */
+#define SDHC_FERACES_ACMD12NE (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMD12NE_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMD12NE_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMD12NE_NO (SDHC_FERACES_ACMD12NE_NO_Val << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMD12NE_YES (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMDTEO_Pos 1 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Timeout Error */
+#define SDHC_FERACES_ACMDTEO (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDTEO_NO (SDHC_FERACES_ACMDTEO_NO_Val << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDTEO_YES (SDHC_FERACES_ACMDTEO_YES_Val << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDCRC_Pos 2 /**< \brief (SDHC_FERACES) Force Event for Auto CMD CRC Error */
+#define SDHC_FERACES_ACMDCRC (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDCRC_NO (SDHC_FERACES_ACMDCRC_NO_Val << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDCRC_YES (SDHC_FERACES_ACMDCRC_YES_Val << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDEND_Pos 3 /**< \brief (SDHC_FERACES) Force Event for Auto CMD End Bit Error */
+#define SDHC_FERACES_ACMDEND (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDEND_NO (SDHC_FERACES_ACMDEND_NO_Val << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDEND_YES (SDHC_FERACES_ACMDEND_YES_Val << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDIDX_Pos 4 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Index Error */
+#define SDHC_FERACES_ACMDIDX (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDIDX_NO (SDHC_FERACES_ACMDIDX_NO_Val << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_ACMDIDX_YES (SDHC_FERACES_ACMDIDX_YES_Val << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_CMDNI_Pos 7 /**< \brief (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error */
+#define SDHC_FERACES_CMDNI (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_CMDNI_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */
+#define SDHC_FERACES_CMDNI_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_CMDNI_NO (SDHC_FERACES_CMDNI_NO_Val << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_CMDNI_YES (SDHC_FERACES_CMDNI_YES_Val << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_MASK _U_(0x009F) /**< \brief (SDHC_FERACES) MASK Register */
+
+/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMDTEO:1; /*!< bit: 0 Force Event for Command Timeout Error */
+ uint16_t CMDCRC:1; /*!< bit: 1 Force Event for Command CRC Error */
+ uint16_t CMDEND:1; /*!< bit: 2 Force Event for Command End Bit Error */
+ uint16_t CMDIDX:1; /*!< bit: 3 Force Event for Command Index Error */
+ uint16_t DATTEO:1; /*!< bit: 4 Force Event for Data Timeout Error */
+ uint16_t DATCRC:1; /*!< bit: 5 Force Event for Data CRC Error */
+ uint16_t DATEND:1; /*!< bit: 6 Force Event for Data End Bit Error */
+ uint16_t CURLIM:1; /*!< bit: 7 Force Event for Current Limit Error */
+ uint16_t ACMD:1; /*!< bit: 8 Force Event for Auto CMD Error */
+ uint16_t ADMA:1; /*!< bit: 9 Force Event for ADMA Error */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t BOOTAE:1; /*!< bit: 12 Force Event for Boot Acknowledge Error */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_FEREIS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_FEREIS_OFFSET 0x052 /**< \brief (SDHC_FEREIS offset) Force Event for Error Interrupt Status */
+#define SDHC_FEREIS_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FEREIS reset_value) Force Event for Error Interrupt Status */
+
+#define SDHC_FEREIS_CMDTEO_Pos 0 /**< \brief (SDHC_FEREIS) Force Event for Command Timeout Error */
+#define SDHC_FEREIS_CMDTEO (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDTEO_NO (SDHC_FEREIS_CMDTEO_NO_Val << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDTEO_YES (SDHC_FEREIS_CMDTEO_YES_Val << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDCRC_Pos 1 /**< \brief (SDHC_FEREIS) Force Event for Command CRC Error */
+#define SDHC_FEREIS_CMDCRC (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDCRC_NO (SDHC_FEREIS_CMDCRC_NO_Val << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDCRC_YES (SDHC_FEREIS_CMDCRC_YES_Val << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDEND_Pos 2 /**< \brief (SDHC_FEREIS) Force Event for Command End Bit Error */
+#define SDHC_FEREIS_CMDEND (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDEND_NO (SDHC_FEREIS_CMDEND_NO_Val << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDEND_YES (SDHC_FEREIS_CMDEND_YES_Val << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDIDX_Pos 3 /**< \brief (SDHC_FEREIS) Force Event for Command Index Error */
+#define SDHC_FEREIS_CMDIDX (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDIDX_NO (SDHC_FEREIS_CMDIDX_NO_Val << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_CMDIDX_YES (SDHC_FEREIS_CMDIDX_YES_Val << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_DATTEO_Pos 4 /**< \brief (SDHC_FEREIS) Force Event for Data Timeout Error */
+#define SDHC_FEREIS_DATTEO (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATTEO_NO (SDHC_FEREIS_DATTEO_NO_Val << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATTEO_YES (SDHC_FEREIS_DATTEO_YES_Val << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATCRC_Pos 5 /**< \brief (SDHC_FEREIS) Force Event for Data CRC Error */
+#define SDHC_FEREIS_DATCRC (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATCRC_NO (SDHC_FEREIS_DATCRC_NO_Val << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATCRC_YES (SDHC_FEREIS_DATCRC_YES_Val << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATEND_Pos 6 /**< \brief (SDHC_FEREIS) Force Event for Data End Bit Error */
+#define SDHC_FEREIS_DATEND (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATEND_NO (SDHC_FEREIS_DATEND_NO_Val << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_DATEND_YES (SDHC_FEREIS_DATEND_YES_Val << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_CURLIM_Pos 7 /**< \brief (SDHC_FEREIS) Force Event for Current Limit Error */
+#define SDHC_FEREIS_CURLIM (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CURLIM_NO (SDHC_FEREIS_CURLIM_NO_Val << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_CURLIM_YES (SDHC_FEREIS_CURLIM_YES_Val << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_ACMD_Pos 8 /**< \brief (SDHC_FEREIS) Force Event for Auto CMD Error */
+#define SDHC_FEREIS_ACMD (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_ACMD_NO (SDHC_FEREIS_ACMD_NO_Val << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ACMD_YES (SDHC_FEREIS_ACMD_YES_Val << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ADMA_Pos 9 /**< \brief (SDHC_FEREIS) Force Event for ADMA Error */
+#define SDHC_FEREIS_ADMA (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_ADMA_NO (SDHC_FEREIS_ADMA_NO_Val << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_ADMA_YES (SDHC_FEREIS_ADMA_YES_Val << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_BOOTAE_Pos 12 /**< \brief (SDHC_FEREIS) Force Event for Boot Acknowledge Error */
+#define SDHC_FEREIS_BOOTAE (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_BOOTAE_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */
+#define SDHC_FEREIS_BOOTAE_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_BOOTAE_NO (SDHC_FEREIS_BOOTAE_NO_Val << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_BOOTAE_YES (SDHC_FEREIS_BOOTAE_YES_Val << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_MASK _U_(0x13FF) /**< \brief (SDHC_FEREIS) MASK Register */
+
+/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/ 8) ADMA Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ERRST:2; /*!< bit: 0.. 1 ADMA Error State */
+ uint8_t LMIS:1; /*!< bit: 2 ADMA Length Mismatch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_AESR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_AESR_OFFSET 0x054 /**< \brief (SDHC_AESR offset) ADMA Error Status */
+#define SDHC_AESR_RESETVALUE _U_(0x00) /**< \brief (SDHC_AESR reset_value) ADMA Error Status */
+
+#define SDHC_AESR_ERRST_Pos 0 /**< \brief (SDHC_AESR) ADMA Error State */
+#define SDHC_AESR_ERRST_Msk (_U_(0x3) << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST(value) (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))
+#define SDHC_AESR_ERRST_STOP_Val _U_(0x0) /**< \brief (SDHC_AESR) ST_STOP (Stop DMA) */
+#define SDHC_AESR_ERRST_FDS_Val _U_(0x1) /**< \brief (SDHC_AESR) ST_FDS (Fetch Descriptor) */
+#define SDHC_AESR_ERRST_2_Val _U_(0x2) /**< \brief (SDHC_AESR) Reserved */
+#define SDHC_AESR_ERRST_TFR_Val _U_(0x3) /**< \brief (SDHC_AESR) ST_TFR (Transfer Data) */
+#define SDHC_AESR_ERRST_STOP (SDHC_AESR_ERRST_STOP_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_FDS (SDHC_AESR_ERRST_FDS_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_2 (SDHC_AESR_ERRST_2_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_TFR (SDHC_AESR_ERRST_TFR_Val << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_LMIS_Pos 2 /**< \brief (SDHC_AESR) ADMA Length Mismatch Error */
+#define SDHC_AESR_LMIS (_U_(0x1) << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_LMIS_NO_Val _U_(0x0) /**< \brief (SDHC_AESR) No Error */
+#define SDHC_AESR_LMIS_YES_Val _U_(0x1) /**< \brief (SDHC_AESR) Error */
+#define SDHC_AESR_LMIS_NO (SDHC_AESR_LMIS_NO_Val << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_LMIS_YES (SDHC_AESR_LMIS_YES_Val << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_MASK _U_(0x07) /**< \brief (SDHC_AESR) MASK Register */
+
+/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADMASA:32; /*!< bit: 0..31 ADMA System Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_ASAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ASAR_OFFSET 0x058 /**< \brief (SDHC_ASAR offset) ADMA System Address n */
+#define SDHC_ASAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ASAR reset_value) ADMA System Address n */
+
+#define SDHC_ASAR_ADMASA_Pos 0 /**< \brief (SDHC_ASAR) ADMA System Address */
+#define SDHC_ASAR_ADMASA_Msk (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)
+#define SDHC_ASAR_ADMASA(value) (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))
+#define SDHC_ASAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ASAR) MASK Register */
+
+/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SDCLKFSEL:10; /*!< bit: 0.. 9 SDCLK Frequency Select Value for Initialization */
+ uint16_t CLKGSEL:1; /*!< bit: 10 Clock Generator Select Value for Initialization */
+ uint16_t :3; /*!< bit: 11..13 Reserved */
+ uint16_t DRVSEL:2; /*!< bit: 14..15 Driver Strength Select Value for Initialization */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_PVR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PVR_OFFSET 0x060 /**< \brief (SDHC_PVR offset) Preset Value n */
+#define SDHC_PVR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_PVR reset_value) Preset Value n */
+
+#define SDHC_PVR_SDCLKFSEL_Pos 0 /**< \brief (SDHC_PVR) SDCLK Frequency Select Value for Initialization */
+#define SDHC_PVR_SDCLKFSEL_Msk (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)
+#define SDHC_PVR_SDCLKFSEL(value) (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))
+#define SDHC_PVR_CLKGSEL_Pos 10 /**< \brief (SDHC_PVR) Clock Generator Select Value for Initialization */
+#define SDHC_PVR_CLKGSEL (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */
+#define SDHC_PVR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_PVR) Programmable Clock Generator */
+#define SDHC_PVR_CLKGSEL_DIV (SDHC_PVR_CLKGSEL_DIV_Val << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_CLKGSEL_PROG (SDHC_PVR_CLKGSEL_PROG_Val << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_DRVSEL_Pos 14 /**< \brief (SDHC_PVR) Driver Strength Select Value for Initialization */
+#define SDHC_PVR_DRVSEL_Msk (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL(value) (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))
+#define SDHC_PVR_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_PVR) Driver Type B is Selected */
+#define SDHC_PVR_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_PVR) Driver Type A is Selected */
+#define SDHC_PVR_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_PVR) Driver Type C is Selected */
+#define SDHC_PVR_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_PVR) Driver Type D is Selected */
+#define SDHC_PVR_DRVSEL_B (SDHC_PVR_DRVSEL_B_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_A (SDHC_PVR_DRVSEL_A_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_C (SDHC_PVR_DRVSEL_C_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_D (SDHC_PVR_DRVSEL_D_Val << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_MASK _U_(0xC7FF) /**< \brief (SDHC_PVR) MASK Register */
+
+/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/ 16) Slot Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t INTSSL:1; /*!< bit: 0 Interrupt Signal for Each Slot */
+ uint16_t :15; /*!< bit: 1..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_SISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SISR_OFFSET 0x0FC /**< \brief (SDHC_SISR offset) Slot Interrupt Status */
+#define SDHC_SISR_RESETVALUE _U_(0x20000) /**< \brief (SDHC_SISR reset_value) Slot Interrupt Status */
+
+#define SDHC_SISR_INTSSL_Pos 0 /**< \brief (SDHC_SISR) Interrupt Signal for Each Slot */
+#define SDHC_SISR_INTSSL_Msk (_U_(0x1) << SDHC_SISR_INTSSL_Pos)
+#define SDHC_SISR_INTSSL(value) (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))
+#define SDHC_SISR_MASK _U_(0x0001) /**< \brief (SDHC_SISR) MASK Register */
+
+/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/ 16) Host Controller Version -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SVER:8; /*!< bit: 0.. 7 Spec Version */
+ uint16_t VVER:8; /*!< bit: 8..15 Vendor Version */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SDHC_HCVR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HCVR_OFFSET 0x0FE /**< \brief (SDHC_HCVR offset) Host Controller Version */
+#define SDHC_HCVR_RESETVALUE _U_(0x1802) /**< \brief (SDHC_HCVR reset_value) Host Controller Version */
+
+#define SDHC_HCVR_SVER_Pos 0 /**< \brief (SDHC_HCVR) Spec Version */
+#define SDHC_HCVR_SVER_Msk (_U_(0xFF) << SDHC_HCVR_SVER_Pos)
+#define SDHC_HCVR_SVER(value) (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))
+#define SDHC_HCVR_VVER_Pos 8 /**< \brief (SDHC_HCVR) Vendor Version */
+#define SDHC_HCVR_VVER_Msk (_U_(0xFF) << SDHC_HCVR_VVER_Pos)
+#define SDHC_HCVR_VVER(value) (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))
+#define SDHC_HCVR_MASK _U_(0xFFFF) /**< \brief (SDHC_HCVR) MASK Register */
+
+/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W 8) MMC Control 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMDTYP:2; /*!< bit: 0.. 1 e.MMC Command Type */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t DDR:1; /*!< bit: 3 e.MMC HSDDR Mode */
+ uint8_t OPD:1; /*!< bit: 4 e.MMC Open Drain Mode */
+ uint8_t BOOTA:1; /*!< bit: 5 e.MMC Boot Acknowledge Enable */
+ uint8_t RSTN:1; /*!< bit: 6 e.MMC Reset Signal */
+ uint8_t FCD:1; /*!< bit: 7 e.MMC Force Card Detect */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_MC1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MC1R_OFFSET 0x204 /**< \brief (SDHC_MC1R offset) MMC Control 1 */
+#define SDHC_MC1R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC1R reset_value) MMC Control 1 */
+
+#define SDHC_MC1R_CMDTYP_Pos 0 /**< \brief (SDHC_MC1R) e.MMC Command Type */
+#define SDHC_MC1R_CMDTYP_Msk (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP(value) (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))
+#define SDHC_MC1R_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_MC1R) Not a MMC specific command */
+#define SDHC_MC1R_CMDTYP_WAITIRQ_Val _U_(0x1) /**< \brief (SDHC_MC1R) Wait IRQ Command */
+#define SDHC_MC1R_CMDTYP_STREAM_Val _U_(0x2) /**< \brief (SDHC_MC1R) Stream Command */
+#define SDHC_MC1R_CMDTYP_BOOT_Val _U_(0x3) /**< \brief (SDHC_MC1R) Boot Command */
+#define SDHC_MC1R_CMDTYP_NORMAL (SDHC_MC1R_CMDTYP_NORMAL_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_WAITIRQ (SDHC_MC1R_CMDTYP_WAITIRQ_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_STREAM (SDHC_MC1R_CMDTYP_STREAM_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_BOOT (SDHC_MC1R_CMDTYP_BOOT_Val << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_DDR_Pos 3 /**< \brief (SDHC_MC1R) e.MMC HSDDR Mode */
+#define SDHC_MC1R_DDR (_U_(0x1) << SDHC_MC1R_DDR_Pos)
+#define SDHC_MC1R_OPD_Pos 4 /**< \brief (SDHC_MC1R) e.MMC Open Drain Mode */
+#define SDHC_MC1R_OPD (_U_(0x1) << SDHC_MC1R_OPD_Pos)
+#define SDHC_MC1R_BOOTA_Pos 5 /**< \brief (SDHC_MC1R) e.MMC Boot Acknowledge Enable */
+#define SDHC_MC1R_BOOTA (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)
+#define SDHC_MC1R_RSTN_Pos 6 /**< \brief (SDHC_MC1R) e.MMC Reset Signal */
+#define SDHC_MC1R_RSTN (_U_(0x1) << SDHC_MC1R_RSTN_Pos)
+#define SDHC_MC1R_FCD_Pos 7 /**< \brief (SDHC_MC1R) e.MMC Force Card Detect */
+#define SDHC_MC1R_FCD (_U_(0x1) << SDHC_MC1R_FCD_Pos)
+#define SDHC_MC1R_MASK _U_(0xFB) /**< \brief (SDHC_MC1R) MASK Register */
+
+/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W 8) MMC Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SRESP:1; /*!< bit: 0 e.MMC Abort Wait IRQ */
+ uint8_t ABOOT:1; /*!< bit: 1 e.MMC Abort Boot */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_MC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MC2R_OFFSET 0x205 /**< \brief (SDHC_MC2R offset) MMC Control 2 */
+#define SDHC_MC2R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC2R reset_value) MMC Control 2 */
+
+#define SDHC_MC2R_SRESP_Pos 0 /**< \brief (SDHC_MC2R) e.MMC Abort Wait IRQ */
+#define SDHC_MC2R_SRESP (_U_(0x1) << SDHC_MC2R_SRESP_Pos)
+#define SDHC_MC2R_ABOOT_Pos 1 /**< \brief (SDHC_MC2R) e.MMC Abort Boot */
+#define SDHC_MC2R_ABOOT (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)
+#define SDHC_MC2R_MASK _U_(0x03) /**< \brief (SDHC_MC2R) MASK Register */
+
+/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BMAX:2; /*!< bit: 0.. 1 AHB Maximum Burst */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_ACR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ACR_OFFSET 0x208 /**< \brief (SDHC_ACR offset) AHB Control */
+#define SDHC_ACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ACR reset_value) AHB Control */
+
+#define SDHC_ACR_BMAX_Pos 0 /**< \brief (SDHC_ACR) AHB Maximum Burst */
+#define SDHC_ACR_BMAX_Msk (_U_(0x3) << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX(value) (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))
+#define SDHC_ACR_BMAX_INCR16_Val _U_(0x0) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_INCR8_Val _U_(0x1) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_INCR4_Val _U_(0x2) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_SINGLE_Val _U_(0x3) /**< \brief (SDHC_ACR) */
+#define SDHC_ACR_BMAX_INCR16 (SDHC_ACR_BMAX_INCR16_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_INCR8 (SDHC_ACR_BMAX_INCR8_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_INCR4 (SDHC_ACR_BMAX_INCR4_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_SINGLE (SDHC_ACR_BMAX_SINGLE_Val << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_MASK _U_(0x00000003) /**< \brief (SDHC_ACR) MASK Register */
+
+/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FSDCLKD:1; /*!< bit: 0 Force SDCK Disabled */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CC2R_OFFSET 0x20C /**< \brief (SDHC_CC2R offset) Clock Control 2 */
+#define SDHC_CC2R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CC2R reset_value) Clock Control 2 */
+
+#define SDHC_CC2R_FSDCLKD_Pos 0 /**< \brief (SDHC_CC2R) Force SDCK Disabled */
+#define SDHC_CC2R_FSDCLKD (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_FSDCLKD_NOEFFECT_Val _U_(0x0) /**< \brief (SDHC_CC2R) No effect */
+#define SDHC_CC2R_FSDCLKD_DISABLE_Val _U_(0x1) /**< \brief (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */
+#define SDHC_CC2R_FSDCLKD_NOEFFECT (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_FSDCLKD_DISABLE (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_MASK _U_(0x00000001) /**< \brief (SDHC_CC2R) MASK Register */
+
+/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CAPWREN:1; /*!< bit: 0 Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t KEY:8; /*!< bit: 8..15 Key (0x46) */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SDHC_CACR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CACR_OFFSET 0x230 /**< \brief (SDHC_CACR offset) Capabilities Control */
+#define SDHC_CACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CACR reset_value) Capabilities Control */
+
+#define SDHC_CACR_CAPWREN_Pos 0 /**< \brief (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
+#define SDHC_CACR_CAPWREN (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)
+#define SDHC_CACR_KEY_Pos 8 /**< \brief (SDHC_CACR) Key (0x46) */
+#define SDHC_CACR_KEY_Msk (_U_(0xFF) << SDHC_CACR_KEY_Pos)
+#define SDHC_CACR_KEY(value) (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))
+#define SDHC_CACR_MASK _U_(0x0000FF01) /**< \brief (SDHC_CACR) MASK Register */
+
+/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W 8) Debug -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NIDBG:1; /*!< bit: 0 Non-intrusive debug enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SDHC_DBGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_DBGR_OFFSET 0x234 /**< \brief (SDHC_DBGR offset) Debug */
+#define SDHC_DBGR_RESETVALUE _U_(0x00) /**< \brief (SDHC_DBGR reset_value) Debug */
+
+#define SDHC_DBGR_NIDBG_Pos 0 /**< \brief (SDHC_DBGR) Non-intrusive debug enable */
+#define SDHC_DBGR_NIDBG (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_NIDBG_IDBG_Val _U_(0x0) /**< \brief (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */
+#define SDHC_DBGR_NIDBG_NIDBG_Val _U_(0x1) /**< \brief (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */
+#define SDHC_DBGR_NIDBG_IDBG (SDHC_DBGR_NIDBG_IDBG_Val << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_NIDBG_NIDBG (SDHC_DBGR_NIDBG_NIDBG_Val << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_MASK _U_(0x01) /**< \brief (SDHC_DBGR) MASK Register */
+
+/** \brief SDHC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO SDHC_SSAR_Type SSAR; /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */
+ __IO SDHC_BSR_Type BSR; /**< \brief Offset: 0x004 (R/W 16) Block Size */
+ __IO SDHC_BCR_Type BCR; /**< \brief Offset: 0x006 (R/W 16) Block Count */
+ __IO SDHC_ARG1R_Type ARG1R; /**< \brief Offset: 0x008 (R/W 32) Argument 1 */
+ __IO SDHC_TMR_Type TMR; /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */
+ __IO SDHC_CR_Type CR; /**< \brief Offset: 0x00E (R/W 16) Command */
+ __I SDHC_RR_Type RR[4]; /**< \brief Offset: 0x010 (R/ 32) Response */
+ __IO SDHC_BDPR_Type BDPR; /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */
+ __I SDHC_PSR_Type PSR; /**< \brief Offset: 0x024 (R/ 32) Present State */
+ __IO SDHC_HC1R_Type HC1R; /**< \brief Offset: 0x028 (R/W 8) Host Control 1 */
+ __IO SDHC_PCR_Type PCR; /**< \brief Offset: 0x029 (R/W 8) Power Control */
+ __IO SDHC_BGCR_Type BGCR; /**< \brief Offset: 0x02A (R/W 8) Block Gap Control */
+ __IO SDHC_WCR_Type WCR; /**< \brief Offset: 0x02B (R/W 8) Wakeup Control */
+ __IO SDHC_CCR_Type CCR; /**< \brief Offset: 0x02C (R/W 16) Clock Control */
+ __IO SDHC_TCR_Type TCR; /**< \brief Offset: 0x02E (R/W 8) Timeout Control */
+ __IO SDHC_SRR_Type SRR; /**< \brief Offset: 0x02F (R/W 8) Software Reset */
+ __IO SDHC_NISTR_Type NISTR; /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */
+ __IO SDHC_EISTR_Type EISTR; /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */
+ __IO SDHC_NISTER_Type NISTER; /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */
+ __IO SDHC_EISTER_Type EISTER; /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */
+ __IO SDHC_NISIER_Type NISIER; /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */
+ __IO SDHC_EISIER_Type EISIER; /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */
+ __I SDHC_ACESR_Type ACESR; /**< \brief Offset: 0x03C (R/ 16) Auto CMD Error Status */
+ __IO SDHC_HC2R_Type HC2R; /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */
+ __I SDHC_CA0R_Type CA0R; /**< \brief Offset: 0x040 (R/ 32) Capabilities 0 */
+ __I SDHC_CA1R_Type CA1R; /**< \brief Offset: 0x044 (R/ 32) Capabilities 1 */
+ __I SDHC_MCCAR_Type MCCAR; /**< \brief Offset: 0x048 (R/ 32) Maximum Current Capabilities */
+ RoReg8 Reserved1[0x4];
+ __O SDHC_FERACES_Type FERACES; /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */
+ __O SDHC_FEREIS_Type FEREIS; /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */
+ __I SDHC_AESR_Type AESR; /**< \brief Offset: 0x054 (R/ 8) ADMA Error Status */
+ RoReg8 Reserved2[0x3];
+ __IO SDHC_ASAR_Type ASAR[1]; /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */
+ RoReg8 Reserved3[0x4];
+ __IO SDHC_PVR_Type PVR[8]; /**< \brief Offset: 0x060 (R/W 16) Preset Value n */
+ RoReg8 Reserved4[0x8C];
+ __I SDHC_SISR_Type SISR; /**< \brief Offset: 0x0FC (R/ 16) Slot Interrupt Status */
+ __I SDHC_HCVR_Type HCVR; /**< \brief Offset: 0x0FE (R/ 16) Host Controller Version */
+ RoReg8 Reserved5[0x104];
+ __IO SDHC_MC1R_Type MC1R; /**< \brief Offset: 0x204 (R/W 8) MMC Control 1 */
+ __O SDHC_MC2R_Type MC2R; /**< \brief Offset: 0x205 ( /W 8) MMC Control 2 */
+ RoReg8 Reserved6[0x2];
+ __IO SDHC_ACR_Type ACR; /**< \brief Offset: 0x208 (R/W 32) AHB Control */
+ __IO SDHC_CC2R_Type CC2R; /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */
+ RoReg8 Reserved7[0x20];
+ __IO SDHC_CACR_Type CACR; /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */
+ __IO SDHC_DBGR_Type DBGR; /**< \brief Offset: 0x234 (R/W 8) Debug */
+} Sdhc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_SDHC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/sercom.h b/GPIO/ATSAME54/include/component/sercom.h
new file mode 100644
index 0000000..f66adc4
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/sercom.h
@@ -0,0 +1,1680 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM_COMPONENT_
+#define _SAME54_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAME54_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM 0x500
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t TXINV:1; /*!< bit: 9 Transmit Data Invert */
+ uint32_t RXINV:1; /*!< bit: 10 Receive Data Invert */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_TXINV_Pos 9 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
+#define SERCOM_USART_CTRLA_TXINV (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
+#define SERCOM_USART_CTRLA_RXINV_Pos 10 /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
+#define SERCOM_USART_CTRLA_RXINV (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :6; /*!< bit: 18..23 Reserved */
+ uint32_t LINCMD:2; /*!< bit: 24..25 LIN Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_LINCMD_Pos 24 /**< \brief (SERCOM_USART_CTRLB) LIN Command */
+#define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
+#define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
+#define SERCOM_USART_CTRLB_MASK _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM I2CM Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CM_CTRLC offset) I2CM Control C */
+#define SERCOM_I2CM_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLC reset_value) I2CM Control C */
+
+#define SERCOM_I2CM_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CM_CTRLC) Data 32 Bit */
+#define SERCOM_I2CM_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)
+#define SERCOM_I2CM_CTRLC_MASK _U_(0x01000000) /**< \brief (SERCOM_I2CM_CTRLC) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS I2CS Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SDASETUP:4; /*!< bit: 0.. 3 SDA Setup Time */
+ uint32_t :20; /*!< bit: 4..23 Reserved */
+ uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CS_CTRLC offset) I2CS Control C */
+#define SERCOM_I2CS_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLC reset_value) I2CS Control C */
+
+#define SERCOM_I2CS_CTRLC_SDASETUP_Pos 0 /**< \brief (SERCOM_I2CS_CTRLC) SDA Setup Time */
+#define SERCOM_I2CS_CTRLC_SDASETUP_Msk (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)
+#define SERCOM_I2CS_CTRLC_SDASETUP(value) (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
+#define SERCOM_I2CS_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CS_CTRLC) Data 32 Bit */
+#define SERCOM_I2CS_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)
+#define SERCOM_I2CS_CTRLC_MASK _U_(0x0100000F) /**< \brief (SERCOM_I2CS_CTRLC) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ICSPACE:6; /*!< bit: 0.. 5 Inter-Character Spacing */
+ uint32_t :18; /*!< bit: 6..23 Reserved */
+ uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
+ uint32_t :7; /*!< bit: 25..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
+#define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
+
+#define SERCOM_SPI_CTRLC_ICSPACE_Pos 0 /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
+#define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
+#define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
+#define SERCOM_SPI_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
+#define SERCOM_SPI_CTRLC_DATA32B (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
+#define SERCOM_SPI_CTRLC_MASK _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
+
+/* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GTIME:3; /*!< bit: 0.. 2 Guard Time */
+ uint32_t :5; /*!< bit: 3.. 7 Reserved */
+ uint32_t BRKLEN:2; /*!< bit: 8.. 9 LIN Master Break Length */
+ uint32_t HDRDLY:2; /*!< bit: 10..11 LIN Master Header Delay */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t INACK:1; /*!< bit: 16 Inhibit Not Acknowledge */
+ uint32_t DSNACK:1; /*!< bit: 17 Disable Successive NACK */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t MAXITER:3; /*!< bit: 20..22 Maximum Iterations */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t DATA32B:2; /*!< bit: 24..25 Data 32 Bit */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
+#define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
+
+#define SERCOM_USART_CTRLC_GTIME_Pos 0 /**< \brief (SERCOM_USART_CTRLC) Guard Time */
+#define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
+#define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
+#define SERCOM_USART_CTRLC_BRKLEN_Pos 8 /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
+#define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
+#define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
+#define SERCOM_USART_CTRLC_HDRDLY_Pos 10 /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
+#define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
+#define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
+#define SERCOM_USART_CTRLC_INACK_Pos 16 /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
+#define SERCOM_USART_CTRLC_INACK (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
+#define SERCOM_USART_CTRLC_DSNACK_Pos 17 /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
+#define SERCOM_USART_CTRLC_DSNACK (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
+#define SERCOM_USART_CTRLC_MAXITER_Pos 20 /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
+#define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
+#define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
+#define SERCOM_USART_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
+#define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
+#define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
+#define SERCOM_USART_CTRLC_MASK _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ __I uint8_t :1; /*!< bit: 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK _U_(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_I2CS_STATUS) Transaction Length Error */
+#define SERCOM_I2CS_STATUS_LENERR (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)
+#define SERCOM_I2CS_STATUS_MASK _U_(0x0EDF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :8; /*!< bit: 3..10 Reserved */
+ uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
+#define SERCOM_SPI_STATUS_LENERR (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
+#define SERCOM_SPI_STATUS_MASK _U_(0x0804) /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t TXE:1; /*!< bit: 6 Transmitter Empty */
+ uint16_t ITER:1; /*!< bit: 7 Maximum Number of Repetitions Reached */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_TXE_Pos 6 /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
+#define SERCOM_USART_STATUS_TXE (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
+#define SERCOM_USART_STATUS_ITER_Pos 7 /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
+#define SERCOM_USART_STATUS_ITER (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
+#define SERCOM_USART_STATUS_MASK _U_(0x00FF) /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :2; /*!< bit: 2.. 3 Reserved */
+ uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK _U_(0x00000013) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t RXERRCNT:1; /*!< bit: 3 RXERRCNT Synchronization Busy */
+ uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3 /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
+#define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/ 8) USART USART Receive Error Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXERRCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXERRCNT_OFFSET 0x20 /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
+#define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
+#define SERCOM_USART_RXERRCNT_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
+
+/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS I2CS Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
+ uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_I2CS_LENGTH offset) I2CS Length */
+#define SERCOM_I2CS_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_LENGTH reset_value) I2CS Length */
+
+#define SERCOM_I2CS_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_I2CS_LENGTH) Data Length */
+#define SERCOM_I2CS_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)
+#define SERCOM_I2CS_LENGTH_LEN(value) (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
+#define SERCOM_I2CS_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_I2CS_LENGTH) Data Length Enable */
+#define SERCOM_I2CS_LENGTH_LENEN (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)
+#define SERCOM_I2CS_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_I2CS_LENGTH) MASK Register */
+
+/* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
+ uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
+#define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
+
+#define SERCOM_SPI_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_SPI_LENGTH) Data Length */
+#define SERCOM_SPI_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
+#define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
+#define SERCOM_SPI_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
+#define SERCOM_SPI_LENGTH_LENEN (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
+#define SERCOM_SPI_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
+
+/* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
+ uint16_t LENEN:2; /*!< bit: 8.. 9 Data Length Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
+#define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
+
+#define SERCOM_USART_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_USART_LENGTH) Data Length */
+#define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
+#define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
+#define SERCOM_USART_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
+#define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
+#define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
+#define SERCOM_USART_LENGTH_MASK _U_(0x03FF) /**< \brief (SERCOM_USART_LENGTH) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
+ RoReg8 Reserved1[0x8];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */
+ RoReg8 Reserved5[0x2];
+ __IO SERCOM_I2CS_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved1[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */
+ RoReg8 Reserved5[0x2];
+ __IO SERCOM_SPI_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) SPI Length */
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved1[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */
+ __I SERCOM_USART_RXERRCNT_Type RXERRCNT; /**< \brief Offset: 0x20 (R/ 8) USART Receive Error Count */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) USART Length */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) USART Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_SERCOM_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/supc.h b/GPIO/ATSAME54/include/component/supc.h
new file mode 100644
index 0000000..e41d74d
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/supc.h
@@ -0,0 +1,554 @@
+/**
+ * \file
+ *
+ * \brief Component description for SUPC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SUPC_COMPONENT_
+#define _SAME54_SUPC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SUPC */
+/* ========================================================================== */
+/** \addtogroup SAME54_SUPC Supply Controller */
+/*@{*/
+
+#define SUPC_U2407
+#define REV_SUPC 0x100
+
+/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
+ uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
+ uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
+ uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */
+#define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */
+#define SUPC_INTENCLR_BOD33RDY (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)
+#define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */
+#define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
+#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
+#define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
+#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */
+#define SUPC_INTENCLR_BOD12RDY (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos)
+#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */
+#define SUPC_INTENCLR_BOD12DET (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos)
+#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */
+#define SUPC_INTENCLR_B12SRDY (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos)
+#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
+#define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
+#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
+#define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
+#define SUPC_INTENCLR_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */
+
+/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
+ uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
+ uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
+ uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */
+#define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */
+
+#define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */
+#define SUPC_INTENSET_BOD33RDY (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)
+#define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */
+#define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
+#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
+#define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
+#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */
+#define SUPC_INTENSET_BOD12RDY (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos)
+#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */
+#define SUPC_INTENSET_BOD12DET (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos)
+#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */
+#define SUPC_INTENSET_B12SRDY (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos)
+#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
+#define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
+#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */
+#define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
+#define SUPC_INTENSET_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */
+
+/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
+ __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
+ __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
+ __I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
+ __I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
+ __I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
+ __I uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
+ __I uint32_t :1; /*!< bit: 9 Reserved */
+ __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
+ __I uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */
+#define SUPC_INTFLAG_BOD33RDY (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)
+#define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */
+#define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
+#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
+#define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
+#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */
+#define SUPC_INTFLAG_BOD12RDY (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos)
+#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */
+#define SUPC_INTFLAG_BOD12DET (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos)
+#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */
+#define SUPC_INTFLAG_B12SRDY (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos)
+#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
+#define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
+#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
+#define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
+#define SUPC_INTFLAG_MASK _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */
+
+/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
+ uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
+ uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
+ uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
+ uint32_t :21; /*!< bit: 11..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */
+#define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */
+
+#define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */
+#define SUPC_STATUS_BOD33RDY (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)
+#define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */
+#define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
+#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
+#define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
+#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */
+#define SUPC_STATUS_BOD12RDY (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos)
+#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */
+#define SUPC_STATUS_BOD12DET (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos)
+#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */
+#define SUPC_STATUS_B12SRDY (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos)
+#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
+#define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
+#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */
+#define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
+#define SUPC_STATUS_MASK _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */
+
+/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t ACTION:2; /*!< bit: 2.. 3 Action when Threshold Crossed */
+ uint32_t STDBYCFG:1; /*!< bit: 4 Configuration in Standby mode */
+ uint32_t RUNSTDBY:1; /*!< bit: 5 Run in Standby mode */
+ uint32_t RUNHIB:1; /*!< bit: 6 Run in Hibernate mode */
+ uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */
+ uint32_t HYST:4; /*!< bit: 8..11 Hysteresis value */
+ uint32_t PSEL:3; /*!< bit: 12..14 Prescaler Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t LEVEL:8; /*!< bit: 16..23 Threshold Level for VDD */
+ uint32_t VBATLEVEL:8; /*!< bit: 24..31 Threshold Level in battery backup sleep mode for VBAT */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */
+#define SUPC_BOD33_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */
+
+#define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */
+#define SUPC_BOD33_ENABLE (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)
+#define SUPC_BOD33_ACTION_Pos 2 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */
+#define SUPC_BOD33_ACTION_Msk (_U_(0x3) << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))
+#define SUPC_BOD33_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD33) No action */
+#define SUPC_BOD33_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD33) The BOD33 generates a reset */
+#define SUPC_BOD33_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */
+#define SUPC_BOD33_ACTION_BKUP_Val _U_(0x3) /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */
+#define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_STDBYCFG_Pos 4 /**< \brief (SUPC_BOD33) Configuration in Standby mode */
+#define SUPC_BOD33_STDBYCFG (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)
+#define SUPC_BOD33_RUNSTDBY_Pos 5 /**< \brief (SUPC_BOD33) Run in Standby mode */
+#define SUPC_BOD33_RUNSTDBY (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)
+#define SUPC_BOD33_RUNHIB_Pos 6 /**< \brief (SUPC_BOD33) Run in Hibernate mode */
+#define SUPC_BOD33_RUNHIB (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)
+#define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Run in Backup mode */
+#define SUPC_BOD33_RUNBKUP (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)
+#define SUPC_BOD33_HYST_Pos 8 /**< \brief (SUPC_BOD33) Hysteresis value */
+#define SUPC_BOD33_HYST_Msk (_U_(0xF) << SUPC_BOD33_HYST_Pos)
+#define SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))
+#define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */
+#define SUPC_BOD33_PSEL_Msk (_U_(0x7) << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))
+#define SUPC_BOD33_PSEL_NODIV_Val _U_(0x0) /**< \brief (SUPC_BOD33) Not divided */
+#define SUPC_BOD33_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD33) Divide clock by 4 */
+#define SUPC_BOD33_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD33) Divide clock by 8 */
+#define SUPC_BOD33_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD33) Divide clock by 16 */
+#define SUPC_BOD33_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD33) Divide clock by 32 */
+#define SUPC_BOD33_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD33) Divide clock by 64 */
+#define SUPC_BOD33_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD33) Divide clock by 128 */
+#define SUPC_BOD33_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD33) Divide clock by 256 */
+#define SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */
+#define SUPC_BOD33_LEVEL_Msk (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)
+#define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))
+#define SUPC_BOD33_VBATLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT */
+#define SUPC_BOD33_VBATLEVEL_Msk (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)
+#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
+#define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
+
+/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
+ uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
+ uint32_t :3; /*!< bit: 9..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_BOD12_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */
+#define SUPC_BOD12_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */
+
+#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */
+#define SUPC_BOD12_ENABLE (_U_(0x1) << SUPC_BOD12_ENABLE_Pos)
+#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */
+#define SUPC_BOD12_HYST (_U_(0x1) << SUPC_BOD12_HYST_Pos)
+#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */
+#define SUPC_BOD12_ACTION_Msk (_U_(0x3) << SUPC_BOD12_ACTION_Pos)
+#define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))
+#define SUPC_BOD12_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD12) No action */
+#define SUPC_BOD12_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */
+#define SUPC_BOD12_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */
+#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos)
+#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos)
+#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos)
+#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */
+#define SUPC_BOD12_STDBYCFG (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos)
+#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */
+#define SUPC_BOD12_RUNSTDBY (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos)
+#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */
+#define SUPC_BOD12_ACTCFG (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos)
+#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */
+#define SUPC_BOD12_PSEL_Msk (_U_(0xF) << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))
+#define SUPC_BOD12_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */
+#define SUPC_BOD12_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */
+#define SUPC_BOD12_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */
+#define SUPC_BOD12_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */
+#define SUPC_BOD12_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */
+#define SUPC_BOD12_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */
+#define SUPC_BOD12_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */
+#define SUPC_BOD12_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */
+#define SUPC_BOD12_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */
+#define SUPC_BOD12_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */
+#define SUPC_BOD12_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */
+#define SUPC_BOD12_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */
+#define SUPC_BOD12_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */
+#define SUPC_BOD12_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */
+#define SUPC_BOD12_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */
+#define SUPC_BOD12_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */
+#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos)
+#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */
+#define SUPC_BOD12_LEVEL_Msk (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos)
+#define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))
+#define SUPC_BOD12_MASK _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */
+
+/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t SEL:1; /*!< bit: 2 Voltage Regulator Selection */
+ uint32_t :4; /*!< bit: 3.. 6 Reserved */
+ uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t VSEN:1; /*!< bit: 16 Voltage Scaling Enable */
+ uint32_t :7; /*!< bit: 17..23 Reserved */
+ uint32_t VSPER:3; /*!< bit: 24..26 Voltage Scaling Period */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */
+#define SUPC_VREG_RESETVALUE _U_(0x00000002) /**< \brief (SUPC_VREG reset_value) VREG Control */
+
+#define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */
+#define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos)
+#define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection */
+#define SUPC_VREG_SEL (_U_(0x1) << SUPC_VREG_SEL_Pos)
+#define SUPC_VREG_SEL_LDO_Val _U_(0x0) /**< \brief (SUPC_VREG) LDO selection */
+#define SUPC_VREG_SEL_BUCK_Val _U_(0x1) /**< \brief (SUPC_VREG) Buck selection */
+#define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos)
+#define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos)
+#define SUPC_VREG_RUNBKUP_Pos 7 /**< \brief (SUPC_VREG) Run in Backup mode */
+#define SUPC_VREG_RUNBKUP (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)
+#define SUPC_VREG_VSEN_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Enable */
+#define SUPC_VREG_VSEN (_U_(0x1) << SUPC_VREG_VSEN_Pos)
+#define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */
+#define SUPC_VREG_VSPER_Msk (_U_(0x7) << SUPC_VREG_VSPER_Pos)
+#define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))
+#define SUPC_VREG_MASK _U_(0x07010086) /**< \brief (SUPC_VREG) MASK Register */
+
+/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */
+ uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */
+ uint32_t TSSEL:1; /*!< bit: 3 Temperature Sensor Selection */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */
+#define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */
+
+#define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */
+#define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos)
+#define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */
+#define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos)
+#define SUPC_VREF_TSSEL_Pos 3 /**< \brief (SUPC_VREF) Temperature Sensor Selection */
+#define SUPC_VREF_TSSEL (_U_(0x1) << SUPC_VREF_TSSEL_Pos)
+#define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */
+#define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)
+#define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */
+#define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)
+#define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */
+#define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
+#define SUPC_VREF_SEL_1V0_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */
+#define SUPC_VREF_SEL_1V1_Val _U_(0x1) /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */
+#define SUPC_VREF_SEL_1V2_Val _U_(0x2) /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */
+#define SUPC_VREF_SEL_1V25_Val _U_(0x3) /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */
+#define SUPC_VREF_SEL_2V0_Val _U_(0x4) /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */
+#define SUPC_VREF_SEL_2V2_Val _U_(0x5) /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */
+#define SUPC_VREF_SEL_2V4_Val _U_(0x6) /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */
+#define SUPC_VREF_SEL_2V5_Val _U_(0x7) /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */
+#define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_MASK _U_(0x000F00CE) /**< \brief (SUPC_VREF) MASK Register */
+
+/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CONF:1; /*!< bit: 0 Battery Backup Configuration */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_BBPS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */
+#define SUPC_BBPS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */
+
+#define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */
+#define SUPC_BBPS_CONF (_U_(0x1) << SUPC_BBPS_CONF_Pos)
+#define SUPC_BBPS_CONF_BOD33_Val _U_(0x0) /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */
+#define SUPC_BBPS_CONF_FORCED_Val _U_(0x1) /**< \brief (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */
+#define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos)
+#define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos)
+#define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */
+#define SUPC_BBPS_WAKEEN (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)
+#define SUPC_BBPS_MASK _U_(0x00000005) /**< \brief (SUPC_BBPS) MASK Register */
+
+/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t SET:2; /*!< bit: 16..17 Set Output */
+ uint32_t :6; /*!< bit: 18..23 Reserved */
+ uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_BKOUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */
+#define SUPC_BKOUT_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */
+
+#define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */
+#define SUPC_BKOUT_EN_Msk (_U_(0x3) << SUPC_BKOUT_EN_Pos)
+#define SUPC_BKOUT_EN(value) (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))
+#define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */
+#define SUPC_BKOUT_CLR_Msk (_U_(0x3) << SUPC_BKOUT_CLR_Pos)
+#define SUPC_BKOUT_CLR(value) (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))
+#define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */
+#define SUPC_BKOUT_SET_Msk (_U_(0x3) << SUPC_BKOUT_SET_Pos)
+#define SUPC_BKOUT_SET(value) (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))
+#define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */
+#define SUPC_BKOUT_RTCTGL_Msk (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)
+#define SUPC_BKOUT_RTCTGL(value) (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))
+#define SUPC_BKOUT_MASK _U_(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */
+
+/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SUPC_BKIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */
+#define SUPC_BKIN_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */
+
+#define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */
+#define SUPC_BKIN_BKIN_Msk (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)
+#define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))
+#define SUPC_BKIN_MASK _U_(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */
+
+/** \brief SUPC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
+ __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */
+ __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */
+ __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */
+ __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */
+ __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */
+ __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_SUPC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/tal.h b/GPIO/ATSAME54/include/component/tal.h
new file mode 100644
index 0000000..4ceb1dc
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/tal.h
@@ -0,0 +1,1842 @@
+/**
+ * \file
+ *
+ * \brief Component description for TAL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TAL_COMPONENT_
+#define _SAME54_TAL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TAL */
+/* ========================================================================== */
+/** \addtogroup SAME54_TAL Trigger Allocator */
+/*@{*/
+
+#define TAL_U2253
+#define REV_TAL 0x200
+
+/* -------- TAL_CTRLA : (TAL Offset: 0x000) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_CTRLA_OFFSET 0x000 /**< \brief (TAL_CTRLA offset) Control A */
+#define TAL_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TAL_CTRLA reset_value) Control A */
+
+#define TAL_CTRLA_SWRST_Pos 0 /**< \brief (TAL_CTRLA) Software Reset */
+#define TAL_CTRLA_SWRST (_U_(0x1) << TAL_CTRLA_SWRST_Pos)
+#define TAL_CTRLA_ENABLE_Pos 1 /**< \brief (TAL_CTRLA) Enable */
+#define TAL_CTRLA_ENABLE (_U_(0x1) << TAL_CTRLA_ENABLE_Pos)
+#define TAL_CTRLA_MASK _U_(0x03) /**< \brief (TAL_CTRLA) MASK Register */
+
+/* -------- TAL_EXTCTRL : (TAL Offset: 0x001) (R/W 8) External Break Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ENABLE:1; /*!< bit: 0 Enable BRK Pin */
+ uint8_t INV:1; /*!< bit: 1 Invert BRK Pin */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_EXTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_EXTCTRL_OFFSET 0x001 /**< \brief (TAL_EXTCTRL offset) External Break Control */
+#define TAL_EXTCTRL_RESETVALUE _U_(0x00) /**< \brief (TAL_EXTCTRL reset_value) External Break Control */
+
+#define TAL_EXTCTRL_ENABLE_Pos 0 /**< \brief (TAL_EXTCTRL) Enable BRK Pin */
+#define TAL_EXTCTRL_ENABLE (_U_(0x1) << TAL_EXTCTRL_ENABLE_Pos)
+#define TAL_EXTCTRL_INV_Pos 1 /**< \brief (TAL_EXTCTRL) Invert BRK Pin */
+#define TAL_EXTCTRL_INV (_U_(0x1) << TAL_EXTCTRL_INV_Pos)
+#define TAL_EXTCTRL_MASK _U_(0x03) /**< \brief (TAL_EXTCTRL) MASK Register */
+
+/* -------- TAL_EVCTRL : (TAL Offset: 0x004) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BRKEI:1; /*!< bit: 0 Break Input Event Enable */
+ uint16_t BRKEO:1; /*!< bit: 1 Break Output Event Enable */
+ uint16_t IRQMONEO0:1; /*!< bit: 2 Interrupt Request Monitor 0 Output Event Enable */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t IRQMONEO:1; /*!< bit: 2 Interrupt Request Monitor x Output Event Enable */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TAL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_EVCTRL_OFFSET 0x004 /**< \brief (TAL_EVCTRL offset) Event Control */
+#define TAL_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TAL_EVCTRL reset_value) Event Control */
+
+#define TAL_EVCTRL_BRKEI_Pos 0 /**< \brief (TAL_EVCTRL) Break Input Event Enable */
+#define TAL_EVCTRL_BRKEI (_U_(0x1) << TAL_EVCTRL_BRKEI_Pos)
+#define TAL_EVCTRL_BRKEO_Pos 1 /**< \brief (TAL_EVCTRL) Break Output Event Enable */
+#define TAL_EVCTRL_BRKEO (_U_(0x1) << TAL_EVCTRL_BRKEO_Pos)
+#define TAL_EVCTRL_IRQMONEO0_Pos 2 /**< \brief (TAL_EVCTRL) Interrupt Request Monitor 0 Output Event Enable */
+#define TAL_EVCTRL_IRQMONEO0 (_U_(1) << TAL_EVCTRL_IRQMONEO0_Pos)
+#define TAL_EVCTRL_IRQMONEO_Pos 2 /**< \brief (TAL_EVCTRL) Interrupt Request Monitor x Output Event Enable */
+#define TAL_EVCTRL_IRQMONEO_Msk (_U_(0x1) << TAL_EVCTRL_IRQMONEO_Pos)
+#define TAL_EVCTRL_IRQMONEO(value) (TAL_EVCTRL_IRQMONEO_Msk & ((value) << TAL_EVCTRL_IRQMONEO_Pos))
+#define TAL_EVCTRL_MASK _U_(0x0007) /**< \brief (TAL_EVCTRL) MASK Register */
+
+/* -------- TAL_INTENCLR : (TAL Offset: 0x008) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */
+ uint8_t IPS0:1; /*!< bit: 1 Inter-Processor Signal Interrupt Enable for CPU 0 */
+ uint8_t IPS1:1; /*!< bit: 2 Inter-Processor Signal Interrupt Enable for CPU 1 */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t IPS:2; /*!< bit: 1.. 2 Inter-Processor Signal Interrupt Enable for CPU x */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTENCLR_OFFSET 0x008 /**< \brief (TAL_INTENCLR offset) Interrupt Enable Clear */
+#define TAL_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TAL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TAL_INTENCLR_BRK_Pos 0 /**< \brief (TAL_INTENCLR) Break Interrupt Enable */
+#define TAL_INTENCLR_BRK (_U_(0x1) << TAL_INTENCLR_BRK_Pos)
+#define TAL_INTENCLR_IPS0_Pos 1 /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU 0 */
+#define TAL_INTENCLR_IPS0 (_U_(1) << TAL_INTENCLR_IPS0_Pos)
+#define TAL_INTENCLR_IPS1_Pos 2 /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU 1 */
+#define TAL_INTENCLR_IPS1 (_U_(1) << TAL_INTENCLR_IPS1_Pos)
+#define TAL_INTENCLR_IPS_Pos 1 /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU x */
+#define TAL_INTENCLR_IPS_Msk (_U_(0x3) << TAL_INTENCLR_IPS_Pos)
+#define TAL_INTENCLR_IPS(value) (TAL_INTENCLR_IPS_Msk & ((value) << TAL_INTENCLR_IPS_Pos))
+#define TAL_INTENCLR_MASK _U_(0x07) /**< \brief (TAL_INTENCLR) MASK Register */
+
+/* -------- TAL_INTENSET : (TAL Offset: 0x009) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */
+ uint8_t IPS0:1; /*!< bit: 1 Inter-Processor Signal Interrupt Enable for CPU 0 */
+ uint8_t IPS1:1; /*!< bit: 2 Inter-Processor Signal Interrupt Enable for CPU 1 */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t IPS:2; /*!< bit: 1.. 2 Inter-Processor Signal Interrupt Enable for CPU x */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTENSET_OFFSET 0x009 /**< \brief (TAL_INTENSET offset) Interrupt Enable Set */
+#define TAL_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TAL_INTENSET reset_value) Interrupt Enable Set */
+
+#define TAL_INTENSET_BRK_Pos 0 /**< \brief (TAL_INTENSET) Break Interrupt Enable */
+#define TAL_INTENSET_BRK (_U_(0x1) << TAL_INTENSET_BRK_Pos)
+#define TAL_INTENSET_IPS0_Pos 1 /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU 0 */
+#define TAL_INTENSET_IPS0 (_U_(1) << TAL_INTENSET_IPS0_Pos)
+#define TAL_INTENSET_IPS1_Pos 2 /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU 1 */
+#define TAL_INTENSET_IPS1 (_U_(1) << TAL_INTENSET_IPS1_Pos)
+#define TAL_INTENSET_IPS_Pos 1 /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU x */
+#define TAL_INTENSET_IPS_Msk (_U_(0x3) << TAL_INTENSET_IPS_Pos)
+#define TAL_INTENSET_IPS(value) (TAL_INTENSET_IPS_Msk & ((value) << TAL_INTENSET_IPS_Pos))
+#define TAL_INTENSET_MASK _U_(0x07) /**< \brief (TAL_INTENSET) MASK Register */
+
+/* -------- TAL_INTFLAG : (TAL Offset: 0x00A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t BRK:1; /*!< bit: 0 Break */
+ __I uint8_t IPS0:1; /*!< bit: 1 Inter-Processor Signal for CPU 0 */
+ __I uint8_t IPS1:1; /*!< bit: 2 Inter-Processor Signal for CPU 1 */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :1; /*!< bit: 0 Reserved */
+ __I uint8_t IPS:2; /*!< bit: 1.. 2 Inter-Processor Signal for CPU x */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTFLAG_OFFSET 0x00A /**< \brief (TAL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TAL_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TAL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TAL_INTFLAG_BRK_Pos 0 /**< \brief (TAL_INTFLAG) Break */
+#define TAL_INTFLAG_BRK (_U_(0x1) << TAL_INTFLAG_BRK_Pos)
+#define TAL_INTFLAG_IPS0_Pos 1 /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU 0 */
+#define TAL_INTFLAG_IPS0 (_U_(1) << TAL_INTFLAG_IPS0_Pos)
+#define TAL_INTFLAG_IPS1_Pos 2 /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU 1 */
+#define TAL_INTFLAG_IPS1 (_U_(1) << TAL_INTFLAG_IPS1_Pos)
+#define TAL_INTFLAG_IPS_Pos 1 /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU x */
+#define TAL_INTFLAG_IPS_Msk (_U_(0x3) << TAL_INTFLAG_IPS_Pos)
+#define TAL_INTFLAG_IPS(value) (TAL_INTFLAG_IPS_Msk & ((value) << TAL_INTFLAG_IPS_Pos))
+#define TAL_INTFLAG_MASK _U_(0x07) /**< \brief (TAL_INTFLAG) MASK Register */
+
+/* -------- TAL_GLOBMASK : (TAL Offset: 0x00B) (R/W 8) Global Break Requests Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */
+ uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */
+ uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_GLOBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_GLOBMASK_OFFSET 0x00B /**< \brief (TAL_GLOBMASK offset) Global Break Requests Mask */
+#define TAL_GLOBMASK_RESETVALUE _U_(0x00) /**< \brief (TAL_GLOBMASK reset_value) Global Break Requests Mask */
+
+#define TAL_GLOBMASK_CPU0_Pos 0 /**< \brief (TAL_GLOBMASK) CPU 0 Break Master */
+#define TAL_GLOBMASK_CPU0 (_U_(1) << TAL_GLOBMASK_CPU0_Pos)
+#define TAL_GLOBMASK_CPU1_Pos 1 /**< \brief (TAL_GLOBMASK) CPU 1 Break Master */
+#define TAL_GLOBMASK_CPU1 (_U_(1) << TAL_GLOBMASK_CPU1_Pos)
+#define TAL_GLOBMASK_CPU_Pos 0 /**< \brief (TAL_GLOBMASK) CPU x Break Master */
+#define TAL_GLOBMASK_CPU_Msk (_U_(0x3) << TAL_GLOBMASK_CPU_Pos)
+#define TAL_GLOBMASK_CPU(value) (TAL_GLOBMASK_CPU_Msk & ((value) << TAL_GLOBMASK_CPU_Pos))
+#define TAL_GLOBMASK_EVBRK_Pos 6 /**< \brief (TAL_GLOBMASK) Event Break Master */
+#define TAL_GLOBMASK_EVBRK (_U_(0x1) << TAL_GLOBMASK_EVBRK_Pos)
+#define TAL_GLOBMASK_EXTBRK_Pos 7 /**< \brief (TAL_GLOBMASK) External Break Master */
+#define TAL_GLOBMASK_EXTBRK (_U_(0x1) << TAL_GLOBMASK_EXTBRK_Pos)
+#define TAL_GLOBMASK_MASK _U_(0xC3) /**< \brief (TAL_GLOBMASK) MASK Register */
+
+/* -------- TAL_HALT : (TAL Offset: 0x00C) ( /W 8) Debug Halt Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */
+ uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */
+ uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_HALT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_HALT_OFFSET 0x00C /**< \brief (TAL_HALT offset) Debug Halt Request */
+#define TAL_HALT_RESETVALUE _U_(0x00) /**< \brief (TAL_HALT reset_value) Debug Halt Request */
+
+#define TAL_HALT_CPU0_Pos 0 /**< \brief (TAL_HALT) CPU 0 Break Master */
+#define TAL_HALT_CPU0 (_U_(1) << TAL_HALT_CPU0_Pos)
+#define TAL_HALT_CPU1_Pos 1 /**< \brief (TAL_HALT) CPU 1 Break Master */
+#define TAL_HALT_CPU1 (_U_(1) << TAL_HALT_CPU1_Pos)
+#define TAL_HALT_CPU_Pos 0 /**< \brief (TAL_HALT) CPU x Break Master */
+#define TAL_HALT_CPU_Msk (_U_(0x3) << TAL_HALT_CPU_Pos)
+#define TAL_HALT_CPU(value) (TAL_HALT_CPU_Msk & ((value) << TAL_HALT_CPU_Pos))
+#define TAL_HALT_EVBRK_Pos 6 /**< \brief (TAL_HALT) Event Break Master */
+#define TAL_HALT_EVBRK (_U_(0x1) << TAL_HALT_EVBRK_Pos)
+#define TAL_HALT_EXTBRK_Pos 7 /**< \brief (TAL_HALT) External Break Master */
+#define TAL_HALT_EXTBRK (_U_(0x1) << TAL_HALT_EXTBRK_Pos)
+#define TAL_HALT_MASK _U_(0xC3) /**< \brief (TAL_HALT) MASK Register */
+
+/* -------- TAL_RESTART : (TAL Offset: 0x00D) ( /W 8) Debug Restart Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */
+ uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_RESTART_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_RESTART_OFFSET 0x00D /**< \brief (TAL_RESTART offset) Debug Restart Request */
+#define TAL_RESTART_RESETVALUE _U_(0x00) /**< \brief (TAL_RESTART reset_value) Debug Restart Request */
+
+#define TAL_RESTART_CPU0_Pos 0 /**< \brief (TAL_RESTART) CPU 0 Break Master */
+#define TAL_RESTART_CPU0 (_U_(1) << TAL_RESTART_CPU0_Pos)
+#define TAL_RESTART_CPU1_Pos 1 /**< \brief (TAL_RESTART) CPU 1 Break Master */
+#define TAL_RESTART_CPU1 (_U_(1) << TAL_RESTART_CPU1_Pos)
+#define TAL_RESTART_CPU_Pos 0 /**< \brief (TAL_RESTART) CPU x Break Master */
+#define TAL_RESTART_CPU_Msk (_U_(0x3) << TAL_RESTART_CPU_Pos)
+#define TAL_RESTART_CPU(value) (TAL_RESTART_CPU_Msk & ((value) << TAL_RESTART_CPU_Pos))
+#define TAL_RESTART_EXTBRK_Pos 7 /**< \brief (TAL_RESTART) External Break Master */
+#define TAL_RESTART_EXTBRK (_U_(0x1) << TAL_RESTART_EXTBRK_Pos)
+#define TAL_RESTART_MASK _U_(0x83) /**< \brief (TAL_RESTART) MASK Register */
+
+/* -------- TAL_BRKSTATUS : (TAL Offset: 0x00E) (R/ 16) Break Request Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CPU0:2; /*!< bit: 0.. 1 CPU 0 Break Request */
+ uint16_t CPU1:2; /*!< bit: 2.. 3 CPU 1 Break Request */
+ uint16_t :8; /*!< bit: 4..11 Reserved */
+ uint16_t EVBRK:2; /*!< bit: 12..13 Event Break Request */
+ uint16_t EXTBRK:2; /*!< bit: 14..15 External Break Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TAL_BRKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_BRKSTATUS_OFFSET 0x00E /**< \brief (TAL_BRKSTATUS offset) Break Request Status */
+#define TAL_BRKSTATUS_RESETVALUE _U_(0x0000) /**< \brief (TAL_BRKSTATUS reset_value) Break Request Status */
+
+#define TAL_BRKSTATUS_CPU0_Pos 0 /**< \brief (TAL_BRKSTATUS) CPU 0 Break Request */
+#define TAL_BRKSTATUS_CPU0_Msk (_U_(0x3) << TAL_BRKSTATUS_CPU0_Pos)
+#define TAL_BRKSTATUS_CPU0(value) (TAL_BRKSTATUS_CPU0_Msk & ((value) << TAL_BRKSTATUS_CPU0_Pos))
+#define TAL_BRKSTATUS_CPU1_Pos 2 /**< \brief (TAL_BRKSTATUS) CPU 1 Break Request */
+#define TAL_BRKSTATUS_CPU1_Msk (_U_(0x3) << TAL_BRKSTATUS_CPU1_Pos)
+#define TAL_BRKSTATUS_CPU1(value) (TAL_BRKSTATUS_CPU1_Msk & ((value) << TAL_BRKSTATUS_CPU1_Pos))
+#define TAL_BRKSTATUS_EVBRK_Pos 12 /**< \brief (TAL_BRKSTATUS) Event Break Request */
+#define TAL_BRKSTATUS_EVBRK_Msk (_U_(0x3) << TAL_BRKSTATUS_EVBRK_Pos)
+#define TAL_BRKSTATUS_EVBRK(value) (TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos))
+#define TAL_BRKSTATUS_EXTBRK_Pos 14 /**< \brief (TAL_BRKSTATUS) External Break Request */
+#define TAL_BRKSTATUS_EXTBRK_Msk (_U_(0x3) << TAL_BRKSTATUS_EXTBRK_Pos)
+#define TAL_BRKSTATUS_EXTBRK(value) (TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Pos))
+#define TAL_BRKSTATUS_MASK _U_(0xF00F) /**< \brief (TAL_BRKSTATUS) MASK Register */
+
+/* -------- TAL_CTICTRLA : (TAL Offset: 0x010) (R/W 8) CTIS Cross-Trigger Interface n Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BRK:2; /*!< bit: 0.. 1 Action when global break issued */
+ uint8_t RESTART:1; /*!< bit: 2 Action when global restart issued */
+ uint8_t IPS:1; /*!< bit: 3 Action when inter-process resource freed */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_CTICTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_CTICTRLA_OFFSET 0x010 /**< \brief (TAL_CTICTRLA offset) Cross-Trigger Interface n Control A */
+#define TAL_CTICTRLA_RESETVALUE _U_(0x00) /**< \brief (TAL_CTICTRLA reset_value) Cross-Trigger Interface n Control A */
+
+#define TAL_CTICTRLA_BRK_Pos 0 /**< \brief (TAL_CTICTRLA) Action when global break issued */
+#define TAL_CTICTRLA_BRK_Msk (_U_(0x3) << TAL_CTICTRLA_BRK_Pos)
+#define TAL_CTICTRLA_BRK(value) (TAL_CTICTRLA_BRK_Msk & ((value) << TAL_CTICTRLA_BRK_Pos))
+#define TAL_CTICTRLA_BRK_BREAK_Val _U_(0x0) /**< \brief (TAL_CTICTRLA) Break when requested */
+#define TAL_CTICTRLA_BRK_INTERRUPT_Val _U_(0x1) /**< \brief (TAL_CTICTRLA) Trigger DBG interrupt instead of break */
+#define TAL_CTICTRLA_BRK_IGNORE_Val _U_(0x2) /**< \brief (TAL_CTICTRLA) Ignore break request */
+#define TAL_CTICTRLA_BRK_BREAK (TAL_CTICTRLA_BRK_BREAK_Val << TAL_CTICTRLA_BRK_Pos)
+#define TAL_CTICTRLA_BRK_INTERRUPT (TAL_CTICTRLA_BRK_INTERRUPT_Val << TAL_CTICTRLA_BRK_Pos)
+#define TAL_CTICTRLA_BRK_IGNORE (TAL_CTICTRLA_BRK_IGNORE_Val << TAL_CTICTRLA_BRK_Pos)
+#define TAL_CTICTRLA_RESTART_Pos 2 /**< \brief (TAL_CTICTRLA) Action when global restart issued */
+#define TAL_CTICTRLA_RESTART (_U_(0x1) << TAL_CTICTRLA_RESTART_Pos)
+#define TAL_CTICTRLA_RESTART_RESTART_Val _U_(0x0) /**< \brief (TAL_CTICTRLA) Restart when requested */
+#define TAL_CTICTRLA_RESTART_IGNORE_Val _U_(0x1) /**< \brief (TAL_CTICTRLA) Ignore restart request */
+#define TAL_CTICTRLA_RESTART_RESTART (TAL_CTICTRLA_RESTART_RESTART_Val << TAL_CTICTRLA_RESTART_Pos)
+#define TAL_CTICTRLA_RESTART_IGNORE (TAL_CTICTRLA_RESTART_IGNORE_Val << TAL_CTICTRLA_RESTART_Pos)
+#define TAL_CTICTRLA_IPS_Pos 3 /**< \brief (TAL_CTICTRLA) Action when inter-process resource freed */
+#define TAL_CTICTRLA_IPS (_U_(0x1) << TAL_CTICTRLA_IPS_Pos)
+#define TAL_CTICTRLA_IPS_EVENT_Val _U_(0x0) /**< \brief (TAL_CTICTRLA) Generate CPU Event when awaited resource is freed. */
+#define TAL_CTICTRLA_IPS_INTERRUPT_Val _U_(0x1) /**< \brief (TAL_CTICTRLA) Generate Interrupt when awaited resource is freed. */
+#define TAL_CTICTRLA_IPS_EVENT (TAL_CTICTRLA_IPS_EVENT_Val << TAL_CTICTRLA_IPS_Pos)
+#define TAL_CTICTRLA_IPS_INTERRUPT (TAL_CTICTRLA_IPS_INTERRUPT_Val << TAL_CTICTRLA_IPS_Pos)
+#define TAL_CTICTRLA_MASK _U_(0x0F) /**< \brief (TAL_CTICTRLA) MASK Register */
+
+/* -------- TAL_CTIMASK : (TAL Offset: 0x011) (R/W 8) CTIS Cross-Trigger Interface n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */
+ uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */
+ uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_CTIMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_CTIMASK_OFFSET 0x011 /**< \brief (TAL_CTIMASK offset) Cross-Trigger Interface n Mask */
+#define TAL_CTIMASK_RESETVALUE _U_(0x00) /**< \brief (TAL_CTIMASK reset_value) Cross-Trigger Interface n Mask */
+
+#define TAL_CTIMASK_CPU0_Pos 0 /**< \brief (TAL_CTIMASK) CPU 0 Break Master */
+#define TAL_CTIMASK_CPU0 (_U_(1) << TAL_CTIMASK_CPU0_Pos)
+#define TAL_CTIMASK_CPU1_Pos 1 /**< \brief (TAL_CTIMASK) CPU 1 Break Master */
+#define TAL_CTIMASK_CPU1 (_U_(1) << TAL_CTIMASK_CPU1_Pos)
+#define TAL_CTIMASK_CPU_Pos 0 /**< \brief (TAL_CTIMASK) CPU x Break Master */
+#define TAL_CTIMASK_CPU_Msk (_U_(0x3) << TAL_CTIMASK_CPU_Pos)
+#define TAL_CTIMASK_CPU(value) (TAL_CTIMASK_CPU_Msk & ((value) << TAL_CTIMASK_CPU_Pos))
+#define TAL_CTIMASK_EVBRK_Pos 6 /**< \brief (TAL_CTIMASK) Event Break Master */
+#define TAL_CTIMASK_EVBRK (_U_(0x1) << TAL_CTIMASK_EVBRK_Pos)
+#define TAL_CTIMASK_EXTBRK_Pos 7 /**< \brief (TAL_CTIMASK) External Break Master */
+#define TAL_CTIMASK_EXTBRK (_U_(0x1) << TAL_CTIMASK_EXTBRK_Pos)
+#define TAL_CTIMASK_MASK _U_(0xC3) /**< \brief (TAL_CTIMASK) MASK Register */
+
+/* -------- TAL_INTSTATUS : (TAL Offset: 0x020) (R/ 8) Interrupt n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t IRQ0:1; /*!< bit: 0 Interrupt Status for Interrupt Request 0 within Interrupt n */
+ uint8_t IRQ1:1; /*!< bit: 1 Interrupt Status for Interrupt Request 1 within Interrupt n */
+ uint8_t IRQ2:1; /*!< bit: 2 Interrupt Status for Interrupt Request 2 within Interrupt n */
+ uint8_t IRQ3:1; /*!< bit: 3 Interrupt Status for Interrupt Request 3 within Interrupt n */
+ uint8_t IRQ4:1; /*!< bit: 4 Interrupt Status for Interrupt Request 4 within Interrupt n */
+ uint8_t IRQ5:1; /*!< bit: 5 Interrupt Status for Interrupt Request 5 within Interrupt n */
+ uint8_t IRQ6:1; /*!< bit: 6 Interrupt Status for Interrupt Request 6 within Interrupt n */
+ uint8_t IRQ7:1; /*!< bit: 7 Interrupt Status for Interrupt Request 7 within Interrupt n */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t IRQ:8; /*!< bit: 0.. 7 Interrupt Status for Interrupt Request x within Interrupt n */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTSTATUS_OFFSET 0x020 /**< \brief (TAL_INTSTATUS offset) Interrupt n Status */
+#define TAL_INTSTATUS_RESETVALUE _U_(0x00) /**< \brief (TAL_INTSTATUS reset_value) Interrupt n Status */
+
+#define TAL_INTSTATUS_IRQ0_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 0 within Interrupt n */
+#define TAL_INTSTATUS_IRQ0 (_U_(1) << TAL_INTSTATUS_IRQ0_Pos)
+#define TAL_INTSTATUS_IRQ1_Pos 1 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 1 within Interrupt n */
+#define TAL_INTSTATUS_IRQ1 (_U_(1) << TAL_INTSTATUS_IRQ1_Pos)
+#define TAL_INTSTATUS_IRQ2_Pos 2 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 2 within Interrupt n */
+#define TAL_INTSTATUS_IRQ2 (_U_(1) << TAL_INTSTATUS_IRQ2_Pos)
+#define TAL_INTSTATUS_IRQ3_Pos 3 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 3 within Interrupt n */
+#define TAL_INTSTATUS_IRQ3 (_U_(1) << TAL_INTSTATUS_IRQ3_Pos)
+#define TAL_INTSTATUS_IRQ4_Pos 4 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 4 within Interrupt n */
+#define TAL_INTSTATUS_IRQ4 (_U_(1) << TAL_INTSTATUS_IRQ4_Pos)
+#define TAL_INTSTATUS_IRQ5_Pos 5 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 5 within Interrupt n */
+#define TAL_INTSTATUS_IRQ5 (_U_(1) << TAL_INTSTATUS_IRQ5_Pos)
+#define TAL_INTSTATUS_IRQ6_Pos 6 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 6 within Interrupt n */
+#define TAL_INTSTATUS_IRQ6 (_U_(1) << TAL_INTSTATUS_IRQ6_Pos)
+#define TAL_INTSTATUS_IRQ7_Pos 7 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 7 within Interrupt n */
+#define TAL_INTSTATUS_IRQ7 (_U_(1) << TAL_INTSTATUS_IRQ7_Pos)
+#define TAL_INTSTATUS_IRQ_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request x within Interrupt n */
+#define TAL_INTSTATUS_IRQ_Msk (_U_(0xFF) << TAL_INTSTATUS_IRQ_Pos)
+#define TAL_INTSTATUS_IRQ(value) (TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos))
+#define TAL_INTSTATUS_MASK _U_(0xFF) /**< \brief (TAL_INTSTATUS) MASK Register */
+
+/* -------- TAL_DMACPUSEL0 : (TAL Offset: 0x110) (R/W 32) DMA Channel Interrupts CPU Select 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CH0:1; /*!< bit: 0 DMA Channel 0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t CH1:1; /*!< bit: 2 DMA Channel 1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t CH2:1; /*!< bit: 4 DMA Channel 2 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t CH3:1; /*!< bit: 6 DMA Channel 3 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t CH4:1; /*!< bit: 8 DMA Channel 4 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t CH5:1; /*!< bit: 10 DMA Channel 5 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t CH6:1; /*!< bit: 12 DMA Channel 6 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 13 Reserved */
+ uint32_t CH7:1; /*!< bit: 14 DMA Channel 7 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t CH8:1; /*!< bit: 16 DMA Channel 8 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t CH9:1; /*!< bit: 18 DMA Channel 9 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t CH10:1; /*!< bit: 20 DMA Channel 10 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t CH11:1; /*!< bit: 22 DMA Channel 11 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t CH12:1; /*!< bit: 24 DMA Channel 12 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 25 Reserved */
+ uint32_t CH13:1; /*!< bit: 26 DMA Channel 13 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t CH14:1; /*!< bit: 28 DMA Channel 14 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t CH15:1; /*!< bit: 30 DMA Channel 15 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_DMACPUSEL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_DMACPUSEL0_OFFSET 0x110 /**< \brief (TAL_DMACPUSEL0 offset) DMA Channel Interrupts CPU Select 0 */
+#define TAL_DMACPUSEL0_RESETVALUE _U_(0x00000000) /**< \brief (TAL_DMACPUSEL0 reset_value) DMA Channel Interrupts CPU Select 0 */
+
+#define TAL_DMACPUSEL0_CH0_Pos 0 /**< \brief (TAL_DMACPUSEL0) DMA Channel 0 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH0_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH0_Pos)
+#define TAL_DMACPUSEL0_CH0(value) (TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos))
+#define TAL_DMACPUSEL0_CH1_Pos 2 /**< \brief (TAL_DMACPUSEL0) DMA Channel 1 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH1_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH1_Pos)
+#define TAL_DMACPUSEL0_CH1(value) (TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos))
+#define TAL_DMACPUSEL0_CH2_Pos 4 /**< \brief (TAL_DMACPUSEL0) DMA Channel 2 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH2_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH2_Pos)
+#define TAL_DMACPUSEL0_CH2(value) (TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos))
+#define TAL_DMACPUSEL0_CH3_Pos 6 /**< \brief (TAL_DMACPUSEL0) DMA Channel 3 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH3_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH3_Pos)
+#define TAL_DMACPUSEL0_CH3(value) (TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos))
+#define TAL_DMACPUSEL0_CH4_Pos 8 /**< \brief (TAL_DMACPUSEL0) DMA Channel 4 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH4_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH4_Pos)
+#define TAL_DMACPUSEL0_CH4(value) (TAL_DMACPUSEL0_CH4_Msk & ((value) << TAL_DMACPUSEL0_CH4_Pos))
+#define TAL_DMACPUSEL0_CH5_Pos 10 /**< \brief (TAL_DMACPUSEL0) DMA Channel 5 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH5_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH5_Pos)
+#define TAL_DMACPUSEL0_CH5(value) (TAL_DMACPUSEL0_CH5_Msk & ((value) << TAL_DMACPUSEL0_CH5_Pos))
+#define TAL_DMACPUSEL0_CH6_Pos 12 /**< \brief (TAL_DMACPUSEL0) DMA Channel 6 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH6_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH6_Pos)
+#define TAL_DMACPUSEL0_CH6(value) (TAL_DMACPUSEL0_CH6_Msk & ((value) << TAL_DMACPUSEL0_CH6_Pos))
+#define TAL_DMACPUSEL0_CH7_Pos 14 /**< \brief (TAL_DMACPUSEL0) DMA Channel 7 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH7_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH7_Pos)
+#define TAL_DMACPUSEL0_CH7(value) (TAL_DMACPUSEL0_CH7_Msk & ((value) << TAL_DMACPUSEL0_CH7_Pos))
+#define TAL_DMACPUSEL0_CH8_Pos 16 /**< \brief (TAL_DMACPUSEL0) DMA Channel 8 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH8_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH8_Pos)
+#define TAL_DMACPUSEL0_CH8(value) (TAL_DMACPUSEL0_CH8_Msk & ((value) << TAL_DMACPUSEL0_CH8_Pos))
+#define TAL_DMACPUSEL0_CH9_Pos 18 /**< \brief (TAL_DMACPUSEL0) DMA Channel 9 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH9_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH9_Pos)
+#define TAL_DMACPUSEL0_CH9(value) (TAL_DMACPUSEL0_CH9_Msk & ((value) << TAL_DMACPUSEL0_CH9_Pos))
+#define TAL_DMACPUSEL0_CH10_Pos 20 /**< \brief (TAL_DMACPUSEL0) DMA Channel 10 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH10_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH10_Pos)
+#define TAL_DMACPUSEL0_CH10(value) (TAL_DMACPUSEL0_CH10_Msk & ((value) << TAL_DMACPUSEL0_CH10_Pos))
+#define TAL_DMACPUSEL0_CH11_Pos 22 /**< \brief (TAL_DMACPUSEL0) DMA Channel 11 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH11_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH11_Pos)
+#define TAL_DMACPUSEL0_CH11(value) (TAL_DMACPUSEL0_CH11_Msk & ((value) << TAL_DMACPUSEL0_CH11_Pos))
+#define TAL_DMACPUSEL0_CH12_Pos 24 /**< \brief (TAL_DMACPUSEL0) DMA Channel 12 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH12_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH12_Pos)
+#define TAL_DMACPUSEL0_CH12(value) (TAL_DMACPUSEL0_CH12_Msk & ((value) << TAL_DMACPUSEL0_CH12_Pos))
+#define TAL_DMACPUSEL0_CH13_Pos 26 /**< \brief (TAL_DMACPUSEL0) DMA Channel 13 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH13_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH13_Pos)
+#define TAL_DMACPUSEL0_CH13(value) (TAL_DMACPUSEL0_CH13_Msk & ((value) << TAL_DMACPUSEL0_CH13_Pos))
+#define TAL_DMACPUSEL0_CH14_Pos 28 /**< \brief (TAL_DMACPUSEL0) DMA Channel 14 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH14_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH14_Pos)
+#define TAL_DMACPUSEL0_CH14(value) (TAL_DMACPUSEL0_CH14_Msk & ((value) << TAL_DMACPUSEL0_CH14_Pos))
+#define TAL_DMACPUSEL0_CH15_Pos 30 /**< \brief (TAL_DMACPUSEL0) DMA Channel 15 Interrupt CPU Select */
+#define TAL_DMACPUSEL0_CH15_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH15_Pos)
+#define TAL_DMACPUSEL0_CH15(value) (TAL_DMACPUSEL0_CH15_Msk & ((value) << TAL_DMACPUSEL0_CH15_Pos))
+#define TAL_DMACPUSEL0_MASK _U_(0x55555555) /**< \brief (TAL_DMACPUSEL0) MASK Register */
+
+/* -------- TAL_DMACPUSEL1 : (TAL Offset: 0x114) (R/W 32) DMA Channel Interrupts CPU Select 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CH16:1; /*!< bit: 0 DMA Channel 16 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t CH17:1; /*!< bit: 2 DMA Channel 17 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t CH18:1; /*!< bit: 4 DMA Channel 18 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t CH19:1; /*!< bit: 6 DMA Channel 19 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t CH20:1; /*!< bit: 8 DMA Channel 20 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t CH21:1; /*!< bit: 10 DMA Channel 21 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t CH22:1; /*!< bit: 12 DMA Channel 22 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 13 Reserved */
+ uint32_t CH23:1; /*!< bit: 14 DMA Channel 23 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t CH24:1; /*!< bit: 16 DMA Channel 24 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t CH25:1; /*!< bit: 18 DMA Channel 25 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t CH26:1; /*!< bit: 20 DMA Channel 26 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t CH27:1; /*!< bit: 22 DMA Channel 27 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t CH28:1; /*!< bit: 24 DMA Channel 28 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 25 Reserved */
+ uint32_t CH29:1; /*!< bit: 26 DMA Channel 29 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t CH30:1; /*!< bit: 28 DMA Channel 30 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t CH31:1; /*!< bit: 30 DMA Channel 31 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_DMACPUSEL1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_DMACPUSEL1_OFFSET 0x114 /**< \brief (TAL_DMACPUSEL1 offset) DMA Channel Interrupts CPU Select 1 */
+#define TAL_DMACPUSEL1_RESETVALUE _U_(0x00000000) /**< \brief (TAL_DMACPUSEL1 reset_value) DMA Channel Interrupts CPU Select 1 */
+
+#define TAL_DMACPUSEL1_CH16_Pos 0 /**< \brief (TAL_DMACPUSEL1) DMA Channel 16 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH16_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH16_Pos)
+#define TAL_DMACPUSEL1_CH16(value) (TAL_DMACPUSEL1_CH16_Msk & ((value) << TAL_DMACPUSEL1_CH16_Pos))
+#define TAL_DMACPUSEL1_CH17_Pos 2 /**< \brief (TAL_DMACPUSEL1) DMA Channel 17 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH17_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH17_Pos)
+#define TAL_DMACPUSEL1_CH17(value) (TAL_DMACPUSEL1_CH17_Msk & ((value) << TAL_DMACPUSEL1_CH17_Pos))
+#define TAL_DMACPUSEL1_CH18_Pos 4 /**< \brief (TAL_DMACPUSEL1) DMA Channel 18 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH18_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH18_Pos)
+#define TAL_DMACPUSEL1_CH18(value) (TAL_DMACPUSEL1_CH18_Msk & ((value) << TAL_DMACPUSEL1_CH18_Pos))
+#define TAL_DMACPUSEL1_CH19_Pos 6 /**< \brief (TAL_DMACPUSEL1) DMA Channel 19 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH19_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH19_Pos)
+#define TAL_DMACPUSEL1_CH19(value) (TAL_DMACPUSEL1_CH19_Msk & ((value) << TAL_DMACPUSEL1_CH19_Pos))
+#define TAL_DMACPUSEL1_CH20_Pos 8 /**< \brief (TAL_DMACPUSEL1) DMA Channel 20 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH20_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH20_Pos)
+#define TAL_DMACPUSEL1_CH20(value) (TAL_DMACPUSEL1_CH20_Msk & ((value) << TAL_DMACPUSEL1_CH20_Pos))
+#define TAL_DMACPUSEL1_CH21_Pos 10 /**< \brief (TAL_DMACPUSEL1) DMA Channel 21 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH21_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH21_Pos)
+#define TAL_DMACPUSEL1_CH21(value) (TAL_DMACPUSEL1_CH21_Msk & ((value) << TAL_DMACPUSEL1_CH21_Pos))
+#define TAL_DMACPUSEL1_CH22_Pos 12 /**< \brief (TAL_DMACPUSEL1) DMA Channel 22 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH22_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH22_Pos)
+#define TAL_DMACPUSEL1_CH22(value) (TAL_DMACPUSEL1_CH22_Msk & ((value) << TAL_DMACPUSEL1_CH22_Pos))
+#define TAL_DMACPUSEL1_CH23_Pos 14 /**< \brief (TAL_DMACPUSEL1) DMA Channel 23 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH23_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH23_Pos)
+#define TAL_DMACPUSEL1_CH23(value) (TAL_DMACPUSEL1_CH23_Msk & ((value) << TAL_DMACPUSEL1_CH23_Pos))
+#define TAL_DMACPUSEL1_CH24_Pos 16 /**< \brief (TAL_DMACPUSEL1) DMA Channel 24 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH24_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH24_Pos)
+#define TAL_DMACPUSEL1_CH24(value) (TAL_DMACPUSEL1_CH24_Msk & ((value) << TAL_DMACPUSEL1_CH24_Pos))
+#define TAL_DMACPUSEL1_CH25_Pos 18 /**< \brief (TAL_DMACPUSEL1) DMA Channel 25 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH25_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH25_Pos)
+#define TAL_DMACPUSEL1_CH25(value) (TAL_DMACPUSEL1_CH25_Msk & ((value) << TAL_DMACPUSEL1_CH25_Pos))
+#define TAL_DMACPUSEL1_CH26_Pos 20 /**< \brief (TAL_DMACPUSEL1) DMA Channel 26 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH26_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH26_Pos)
+#define TAL_DMACPUSEL1_CH26(value) (TAL_DMACPUSEL1_CH26_Msk & ((value) << TAL_DMACPUSEL1_CH26_Pos))
+#define TAL_DMACPUSEL1_CH27_Pos 22 /**< \brief (TAL_DMACPUSEL1) DMA Channel 27 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH27_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH27_Pos)
+#define TAL_DMACPUSEL1_CH27(value) (TAL_DMACPUSEL1_CH27_Msk & ((value) << TAL_DMACPUSEL1_CH27_Pos))
+#define TAL_DMACPUSEL1_CH28_Pos 24 /**< \brief (TAL_DMACPUSEL1) DMA Channel 28 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH28_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH28_Pos)
+#define TAL_DMACPUSEL1_CH28(value) (TAL_DMACPUSEL1_CH28_Msk & ((value) << TAL_DMACPUSEL1_CH28_Pos))
+#define TAL_DMACPUSEL1_CH29_Pos 26 /**< \brief (TAL_DMACPUSEL1) DMA Channel 29 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH29_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH29_Pos)
+#define TAL_DMACPUSEL1_CH29(value) (TAL_DMACPUSEL1_CH29_Msk & ((value) << TAL_DMACPUSEL1_CH29_Pos))
+#define TAL_DMACPUSEL1_CH30_Pos 28 /**< \brief (TAL_DMACPUSEL1) DMA Channel 30 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH30_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH30_Pos)
+#define TAL_DMACPUSEL1_CH30(value) (TAL_DMACPUSEL1_CH30_Msk & ((value) << TAL_DMACPUSEL1_CH30_Pos))
+#define TAL_DMACPUSEL1_CH31_Pos 30 /**< \brief (TAL_DMACPUSEL1) DMA Channel 31 Interrupt CPU Select */
+#define TAL_DMACPUSEL1_CH31_Msk (_U_(0x1) << TAL_DMACPUSEL1_CH31_Pos)
+#define TAL_DMACPUSEL1_CH31(value) (TAL_DMACPUSEL1_CH31_Msk & ((value) << TAL_DMACPUSEL1_CH31_Pos))
+#define TAL_DMACPUSEL1_MASK _U_(0x55555555) /**< \brief (TAL_DMACPUSEL1) MASK Register */
+
+/* -------- TAL_EVCPUSEL0 : (TAL Offset: 0x118) (R/W 32) EVSYS Channel Interrupts CPU Select 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CH0:1; /*!< bit: 0 Event Channel 0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t CH1:1; /*!< bit: 2 Event Channel 1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t CH2:1; /*!< bit: 4 Event Channel 2 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t CH3:1; /*!< bit: 6 Event Channel 3 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t CH4:1; /*!< bit: 8 Event Channel 4 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t CH5:1; /*!< bit: 10 Event Channel 5 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t CH6:1; /*!< bit: 12 Event Channel 6 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 13 Reserved */
+ uint32_t CH7:1; /*!< bit: 14 Event Channel 7 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t CH8:1; /*!< bit: 16 Event Channel 8 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t CH9:1; /*!< bit: 18 Event Channel 9 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t CH10:1; /*!< bit: 20 Event Channel 10 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t CH11:1; /*!< bit: 22 Event Channel 11 Interrupt CPU Select */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_EVCPUSEL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_EVCPUSEL0_OFFSET 0x118 /**< \brief (TAL_EVCPUSEL0 offset) EVSYS Channel Interrupts CPU Select 0 */
+#define TAL_EVCPUSEL0_RESETVALUE _U_(0x00000000) /**< \brief (TAL_EVCPUSEL0 reset_value) EVSYS Channel Interrupts CPU Select 0 */
+
+#define TAL_EVCPUSEL0_CH0_Pos 0 /**< \brief (TAL_EVCPUSEL0) Event Channel 0 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH0_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH0_Pos)
+#define TAL_EVCPUSEL0_CH0(value) (TAL_EVCPUSEL0_CH0_Msk & ((value) << TAL_EVCPUSEL0_CH0_Pos))
+#define TAL_EVCPUSEL0_CH1_Pos 2 /**< \brief (TAL_EVCPUSEL0) Event Channel 1 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH1_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH1_Pos)
+#define TAL_EVCPUSEL0_CH1(value) (TAL_EVCPUSEL0_CH1_Msk & ((value) << TAL_EVCPUSEL0_CH1_Pos))
+#define TAL_EVCPUSEL0_CH2_Pos 4 /**< \brief (TAL_EVCPUSEL0) Event Channel 2 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH2_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH2_Pos)
+#define TAL_EVCPUSEL0_CH2(value) (TAL_EVCPUSEL0_CH2_Msk & ((value) << TAL_EVCPUSEL0_CH2_Pos))
+#define TAL_EVCPUSEL0_CH3_Pos 6 /**< \brief (TAL_EVCPUSEL0) Event Channel 3 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH3_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH3_Pos)
+#define TAL_EVCPUSEL0_CH3(value) (TAL_EVCPUSEL0_CH3_Msk & ((value) << TAL_EVCPUSEL0_CH3_Pos))
+#define TAL_EVCPUSEL0_CH4_Pos 8 /**< \brief (TAL_EVCPUSEL0) Event Channel 4 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH4_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH4_Pos)
+#define TAL_EVCPUSEL0_CH4(value) (TAL_EVCPUSEL0_CH4_Msk & ((value) << TAL_EVCPUSEL0_CH4_Pos))
+#define TAL_EVCPUSEL0_CH5_Pos 10 /**< \brief (TAL_EVCPUSEL0) Event Channel 5 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH5_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH5_Pos)
+#define TAL_EVCPUSEL0_CH5(value) (TAL_EVCPUSEL0_CH5_Msk & ((value) << TAL_EVCPUSEL0_CH5_Pos))
+#define TAL_EVCPUSEL0_CH6_Pos 12 /**< \brief (TAL_EVCPUSEL0) Event Channel 6 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH6_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH6_Pos)
+#define TAL_EVCPUSEL0_CH6(value) (TAL_EVCPUSEL0_CH6_Msk & ((value) << TAL_EVCPUSEL0_CH6_Pos))
+#define TAL_EVCPUSEL0_CH7_Pos 14 /**< \brief (TAL_EVCPUSEL0) Event Channel 7 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH7_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH7_Pos)
+#define TAL_EVCPUSEL0_CH7(value) (TAL_EVCPUSEL0_CH7_Msk & ((value) << TAL_EVCPUSEL0_CH7_Pos))
+#define TAL_EVCPUSEL0_CH8_Pos 16 /**< \brief (TAL_EVCPUSEL0) Event Channel 8 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH8_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH8_Pos)
+#define TAL_EVCPUSEL0_CH8(value) (TAL_EVCPUSEL0_CH8_Msk & ((value) << TAL_EVCPUSEL0_CH8_Pos))
+#define TAL_EVCPUSEL0_CH9_Pos 18 /**< \brief (TAL_EVCPUSEL0) Event Channel 9 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH9_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH9_Pos)
+#define TAL_EVCPUSEL0_CH9(value) (TAL_EVCPUSEL0_CH9_Msk & ((value) << TAL_EVCPUSEL0_CH9_Pos))
+#define TAL_EVCPUSEL0_CH10_Pos 20 /**< \brief (TAL_EVCPUSEL0) Event Channel 10 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH10_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH10_Pos)
+#define TAL_EVCPUSEL0_CH10(value) (TAL_EVCPUSEL0_CH10_Msk & ((value) << TAL_EVCPUSEL0_CH10_Pos))
+#define TAL_EVCPUSEL0_CH11_Pos 22 /**< \brief (TAL_EVCPUSEL0) Event Channel 11 Interrupt CPU Select */
+#define TAL_EVCPUSEL0_CH11_Msk (_U_(0x1) << TAL_EVCPUSEL0_CH11_Pos)
+#define TAL_EVCPUSEL0_CH11(value) (TAL_EVCPUSEL0_CH11_Msk & ((value) << TAL_EVCPUSEL0_CH11_Pos))
+#define TAL_EVCPUSEL0_MASK _U_(0x00555555) /**< \brief (TAL_EVCPUSEL0) MASK Register */
+
+/* -------- TAL_EICCPUSEL0 : (TAL Offset: 0x120) (R/W 32) EIC External Interrupts CPU Select 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t EXTINT1:1; /*!< bit: 2 External Interrupt 1 CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t EXTINT2:1; /*!< bit: 4 External Interrupt 2 CPU Select */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t EXTINT3:1; /*!< bit: 6 External Interrupt 3 CPU Select */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t EXTINT4:1; /*!< bit: 8 External Interrupt 4 CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t EXTINT5:1; /*!< bit: 10 External Interrupt 5 CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t EXTINT6:1; /*!< bit: 12 External Interrupt 6 CPU Select */
+ uint32_t :1; /*!< bit: 13 Reserved */
+ uint32_t EXTINT7:1; /*!< bit: 14 External Interrupt 7 CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t EXTINT8:1; /*!< bit: 16 External Interrupt 8 CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t EXTINT9:1; /*!< bit: 18 External Interrupt 9 CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t EXTINT10:1; /*!< bit: 20 External Interrupt 10 CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t EXTINT11:1; /*!< bit: 22 External Interrupt 11 CPU Select */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t EXTINT12:1; /*!< bit: 24 External Interrupt 12 CPU Select */
+ uint32_t :1; /*!< bit: 25 Reserved */
+ uint32_t EXTINT13:1; /*!< bit: 26 External Interrupt 13 CPU Select */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t EXTINT14:1; /*!< bit: 28 External Interrupt 14 CPU Select */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t EXTINT15:1; /*!< bit: 30 External Interrupt 15 CPU Select */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_EICCPUSEL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_EICCPUSEL0_OFFSET 0x120 /**< \brief (TAL_EICCPUSEL0 offset) EIC External Interrupts CPU Select 0 */
+#define TAL_EICCPUSEL0_RESETVALUE _U_(0x00000000) /**< \brief (TAL_EICCPUSEL0 reset_value) EIC External Interrupts CPU Select 0 */
+
+#define TAL_EICCPUSEL0_EXTINT0_Pos 0 /**< \brief (TAL_EICCPUSEL0) External Interrupt 0 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT0_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT0_Pos)
+#define TAL_EICCPUSEL0_EXTINT0(value) (TAL_EICCPUSEL0_EXTINT0_Msk & ((value) << TAL_EICCPUSEL0_EXTINT0_Pos))
+#define TAL_EICCPUSEL0_EXTINT1_Pos 2 /**< \brief (TAL_EICCPUSEL0) External Interrupt 1 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT1_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT1_Pos)
+#define TAL_EICCPUSEL0_EXTINT1(value) (TAL_EICCPUSEL0_EXTINT1_Msk & ((value) << TAL_EICCPUSEL0_EXTINT1_Pos))
+#define TAL_EICCPUSEL0_EXTINT2_Pos 4 /**< \brief (TAL_EICCPUSEL0) External Interrupt 2 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT2_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT2_Pos)
+#define TAL_EICCPUSEL0_EXTINT2(value) (TAL_EICCPUSEL0_EXTINT2_Msk & ((value) << TAL_EICCPUSEL0_EXTINT2_Pos))
+#define TAL_EICCPUSEL0_EXTINT3_Pos 6 /**< \brief (TAL_EICCPUSEL0) External Interrupt 3 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT3_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT3_Pos)
+#define TAL_EICCPUSEL0_EXTINT3(value) (TAL_EICCPUSEL0_EXTINT3_Msk & ((value) << TAL_EICCPUSEL0_EXTINT3_Pos))
+#define TAL_EICCPUSEL0_EXTINT4_Pos 8 /**< \brief (TAL_EICCPUSEL0) External Interrupt 4 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT4_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT4_Pos)
+#define TAL_EICCPUSEL0_EXTINT4(value) (TAL_EICCPUSEL0_EXTINT4_Msk & ((value) << TAL_EICCPUSEL0_EXTINT4_Pos))
+#define TAL_EICCPUSEL0_EXTINT5_Pos 10 /**< \brief (TAL_EICCPUSEL0) External Interrupt 5 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT5_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT5_Pos)
+#define TAL_EICCPUSEL0_EXTINT5(value) (TAL_EICCPUSEL0_EXTINT5_Msk & ((value) << TAL_EICCPUSEL0_EXTINT5_Pos))
+#define TAL_EICCPUSEL0_EXTINT6_Pos 12 /**< \brief (TAL_EICCPUSEL0) External Interrupt 6 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT6_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT6_Pos)
+#define TAL_EICCPUSEL0_EXTINT6(value) (TAL_EICCPUSEL0_EXTINT6_Msk & ((value) << TAL_EICCPUSEL0_EXTINT6_Pos))
+#define TAL_EICCPUSEL0_EXTINT7_Pos 14 /**< \brief (TAL_EICCPUSEL0) External Interrupt 7 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT7_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT7_Pos)
+#define TAL_EICCPUSEL0_EXTINT7(value) (TAL_EICCPUSEL0_EXTINT7_Msk & ((value) << TAL_EICCPUSEL0_EXTINT7_Pos))
+#define TAL_EICCPUSEL0_EXTINT8_Pos 16 /**< \brief (TAL_EICCPUSEL0) External Interrupt 8 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT8_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT8_Pos)
+#define TAL_EICCPUSEL0_EXTINT8(value) (TAL_EICCPUSEL0_EXTINT8_Msk & ((value) << TAL_EICCPUSEL0_EXTINT8_Pos))
+#define TAL_EICCPUSEL0_EXTINT9_Pos 18 /**< \brief (TAL_EICCPUSEL0) External Interrupt 9 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT9_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT9_Pos)
+#define TAL_EICCPUSEL0_EXTINT9(value) (TAL_EICCPUSEL0_EXTINT9_Msk & ((value) << TAL_EICCPUSEL0_EXTINT9_Pos))
+#define TAL_EICCPUSEL0_EXTINT10_Pos 20 /**< \brief (TAL_EICCPUSEL0) External Interrupt 10 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT10_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT10_Pos)
+#define TAL_EICCPUSEL0_EXTINT10(value) (TAL_EICCPUSEL0_EXTINT10_Msk & ((value) << TAL_EICCPUSEL0_EXTINT10_Pos))
+#define TAL_EICCPUSEL0_EXTINT11_Pos 22 /**< \brief (TAL_EICCPUSEL0) External Interrupt 11 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT11_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT11_Pos)
+#define TAL_EICCPUSEL0_EXTINT11(value) (TAL_EICCPUSEL0_EXTINT11_Msk & ((value) << TAL_EICCPUSEL0_EXTINT11_Pos))
+#define TAL_EICCPUSEL0_EXTINT12_Pos 24 /**< \brief (TAL_EICCPUSEL0) External Interrupt 12 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT12_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT12_Pos)
+#define TAL_EICCPUSEL0_EXTINT12(value) (TAL_EICCPUSEL0_EXTINT12_Msk & ((value) << TAL_EICCPUSEL0_EXTINT12_Pos))
+#define TAL_EICCPUSEL0_EXTINT13_Pos 26 /**< \brief (TAL_EICCPUSEL0) External Interrupt 13 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT13_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT13_Pos)
+#define TAL_EICCPUSEL0_EXTINT13(value) (TAL_EICCPUSEL0_EXTINT13_Msk & ((value) << TAL_EICCPUSEL0_EXTINT13_Pos))
+#define TAL_EICCPUSEL0_EXTINT14_Pos 28 /**< \brief (TAL_EICCPUSEL0) External Interrupt 14 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT14_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT14_Pos)
+#define TAL_EICCPUSEL0_EXTINT14(value) (TAL_EICCPUSEL0_EXTINT14_Msk & ((value) << TAL_EICCPUSEL0_EXTINT14_Pos))
+#define TAL_EICCPUSEL0_EXTINT15_Pos 30 /**< \brief (TAL_EICCPUSEL0) External Interrupt 15 CPU Select */
+#define TAL_EICCPUSEL0_EXTINT15_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT15_Pos)
+#define TAL_EICCPUSEL0_EXTINT15(value) (TAL_EICCPUSEL0_EXTINT15_Msk & ((value) << TAL_EICCPUSEL0_EXTINT15_Pos))
+#define TAL_EICCPUSEL0_MASK _U_(0x55555555) /**< \brief (TAL_EICCPUSEL0) MASK Register */
+
+/* -------- TAL_INTCPUSEL0 : (TAL Offset: 0x128) (R/W 32) Interrupts CPU Select 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC:1; /*!< bit: 0 PAC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t PM:1; /*!< bit: 2 PM Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t MCLK:1; /*!< bit: 4 MCLK Interrupt CPU Select */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t OSCCTRL:1; /*!< bit: 8 OSCCTRL Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t OSC32KCTRL:1; /*!< bit: 10 OSC32KCTRL Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t SUPC:1; /*!< bit: 12 SUPC Interrupt CPU Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t WDT:1; /*!< bit: 16 WDT Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t RTC:1; /*!< bit: 18 RTC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t EIC:1; /*!< bit: 20 EIC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t FREQM:1; /*!< bit: 22 FREQM Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t SERCOM0:1; /*!< bit: 24 SERCOM0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 25 Reserved */
+ uint32_t SERCOM1:1; /*!< bit: 26 SERCOM1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t TC0:1; /*!< bit: 28 TC0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t TC1:1; /*!< bit: 30 TC1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL0_OFFSET 0x128 /**< \brief (TAL_INTCPUSEL0 offset) Interrupts CPU Select 0 */
+#define TAL_INTCPUSEL0_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL0 reset_value) Interrupts CPU Select 0 */
+
+#define TAL_INTCPUSEL0_PAC_Pos 0 /**< \brief (TAL_INTCPUSEL0) PAC Interrupt CPU Select */
+#define TAL_INTCPUSEL0_PAC_Msk (_U_(0x1) << TAL_INTCPUSEL0_PAC_Pos)
+#define TAL_INTCPUSEL0_PAC(value) (TAL_INTCPUSEL0_PAC_Msk & ((value) << TAL_INTCPUSEL0_PAC_Pos))
+#define TAL_INTCPUSEL0_PM_Pos 2 /**< \brief (TAL_INTCPUSEL0) PM Interrupt CPU Select */
+#define TAL_INTCPUSEL0_PM_Msk (_U_(0x1) << TAL_INTCPUSEL0_PM_Pos)
+#define TAL_INTCPUSEL0_PM(value) (TAL_INTCPUSEL0_PM_Msk & ((value) << TAL_INTCPUSEL0_PM_Pos))
+#define TAL_INTCPUSEL0_MCLK_Pos 4 /**< \brief (TAL_INTCPUSEL0) MCLK Interrupt CPU Select */
+#define TAL_INTCPUSEL0_MCLK_Msk (_U_(0x1) << TAL_INTCPUSEL0_MCLK_Pos)
+#define TAL_INTCPUSEL0_MCLK(value) (TAL_INTCPUSEL0_MCLK_Msk & ((value) << TAL_INTCPUSEL0_MCLK_Pos))
+#define TAL_INTCPUSEL0_OSCCTRL_Pos 8 /**< \brief (TAL_INTCPUSEL0) OSCCTRL Interrupt CPU Select */
+#define TAL_INTCPUSEL0_OSCCTRL_Msk (_U_(0x1) << TAL_INTCPUSEL0_OSCCTRL_Pos)
+#define TAL_INTCPUSEL0_OSCCTRL(value) (TAL_INTCPUSEL0_OSCCTRL_Msk & ((value) << TAL_INTCPUSEL0_OSCCTRL_Pos))
+#define TAL_INTCPUSEL0_OSC32KCTRL_Pos 10 /**< \brief (TAL_INTCPUSEL0) OSC32KCTRL Interrupt CPU Select */
+#define TAL_INTCPUSEL0_OSC32KCTRL_Msk (_U_(0x1) << TAL_INTCPUSEL0_OSC32KCTRL_Pos)
+#define TAL_INTCPUSEL0_OSC32KCTRL(value) (TAL_INTCPUSEL0_OSC32KCTRL_Msk & ((value) << TAL_INTCPUSEL0_OSC32KCTRL_Pos))
+#define TAL_INTCPUSEL0_SUPC_Pos 12 /**< \brief (TAL_INTCPUSEL0) SUPC Interrupt CPU Select */
+#define TAL_INTCPUSEL0_SUPC_Msk (_U_(0x1) << TAL_INTCPUSEL0_SUPC_Pos)
+#define TAL_INTCPUSEL0_SUPC(value) (TAL_INTCPUSEL0_SUPC_Msk & ((value) << TAL_INTCPUSEL0_SUPC_Pos))
+#define TAL_INTCPUSEL0_WDT_Pos 16 /**< \brief (TAL_INTCPUSEL0) WDT Interrupt CPU Select */
+#define TAL_INTCPUSEL0_WDT_Msk (_U_(0x1) << TAL_INTCPUSEL0_WDT_Pos)
+#define TAL_INTCPUSEL0_WDT(value) (TAL_INTCPUSEL0_WDT_Msk & ((value) << TAL_INTCPUSEL0_WDT_Pos))
+#define TAL_INTCPUSEL0_RTC_Pos 18 /**< \brief (TAL_INTCPUSEL0) RTC Interrupt CPU Select */
+#define TAL_INTCPUSEL0_RTC_Msk (_U_(0x1) << TAL_INTCPUSEL0_RTC_Pos)
+#define TAL_INTCPUSEL0_RTC(value) (TAL_INTCPUSEL0_RTC_Msk & ((value) << TAL_INTCPUSEL0_RTC_Pos))
+#define TAL_INTCPUSEL0_EIC_Pos 20 /**< \brief (TAL_INTCPUSEL0) EIC Interrupt CPU Select */
+#define TAL_INTCPUSEL0_EIC_Msk (_U_(0x1) << TAL_INTCPUSEL0_EIC_Pos)
+#define TAL_INTCPUSEL0_EIC(value) (TAL_INTCPUSEL0_EIC_Msk & ((value) << TAL_INTCPUSEL0_EIC_Pos))
+#define TAL_INTCPUSEL0_FREQM_Pos 22 /**< \brief (TAL_INTCPUSEL0) FREQM Interrupt CPU Select */
+#define TAL_INTCPUSEL0_FREQM_Msk (_U_(0x1) << TAL_INTCPUSEL0_FREQM_Pos)
+#define TAL_INTCPUSEL0_FREQM(value) (TAL_INTCPUSEL0_FREQM_Msk & ((value) << TAL_INTCPUSEL0_FREQM_Pos))
+#define TAL_INTCPUSEL0_SERCOM0_Pos 24 /**< \brief (TAL_INTCPUSEL0) SERCOM0 Interrupt CPU Select */
+#define TAL_INTCPUSEL0_SERCOM0_Msk (_U_(0x1) << TAL_INTCPUSEL0_SERCOM0_Pos)
+#define TAL_INTCPUSEL0_SERCOM0(value) (TAL_INTCPUSEL0_SERCOM0_Msk & ((value) << TAL_INTCPUSEL0_SERCOM0_Pos))
+#define TAL_INTCPUSEL0_SERCOM1_Pos 26 /**< \brief (TAL_INTCPUSEL0) SERCOM1 Interrupt CPU Select */
+#define TAL_INTCPUSEL0_SERCOM1_Msk (_U_(0x1) << TAL_INTCPUSEL0_SERCOM1_Pos)
+#define TAL_INTCPUSEL0_SERCOM1(value) (TAL_INTCPUSEL0_SERCOM1_Msk & ((value) << TAL_INTCPUSEL0_SERCOM1_Pos))
+#define TAL_INTCPUSEL0_TC0_Pos 28 /**< \brief (TAL_INTCPUSEL0) TC0 Interrupt CPU Select */
+#define TAL_INTCPUSEL0_TC0_Msk (_U_(0x1) << TAL_INTCPUSEL0_TC0_Pos)
+#define TAL_INTCPUSEL0_TC0(value) (TAL_INTCPUSEL0_TC0_Msk & ((value) << TAL_INTCPUSEL0_TC0_Pos))
+#define TAL_INTCPUSEL0_TC1_Pos 30 /**< \brief (TAL_INTCPUSEL0) TC1 Interrupt CPU Select */
+#define TAL_INTCPUSEL0_TC1_Msk (_U_(0x1) << TAL_INTCPUSEL0_TC1_Pos)
+#define TAL_INTCPUSEL0_TC1(value) (TAL_INTCPUSEL0_TC1_Msk & ((value) << TAL_INTCPUSEL0_TC1_Pos))
+#define TAL_INTCPUSEL0_MASK _U_(0x55551515) /**< \brief (TAL_INTCPUSEL0) MASK Register */
+
+/* -------- TAL_INTCPUSEL1 : (TAL Offset: 0x12C) (R/W 32) Interrupts CPU Select 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL1_OFFSET 0x12C /**< \brief (TAL_INTCPUSEL1 offset) Interrupts CPU Select 1 */
+#define TAL_INTCPUSEL1_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL1 reset_value) Interrupts CPU Select 1 */
+#define TAL_INTCPUSEL1_MASK _U_(0x00000000) /**< \brief (TAL_INTCPUSEL1) MASK Register */
+
+/* -------- TAL_INTCPUSEL2 : (TAL Offset: 0x130) (R/W 32) Interrupts CPU Select 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USB:1; /*!< bit: 0 USB Interrupt CPU Select */
+ uint32_t :3; /*!< bit: 1.. 3 Reserved */
+ uint32_t NVMCTRL:1; /*!< bit: 4 NVMCTRL Interrupt CPU Select */
+ uint32_t :5; /*!< bit: 5.. 9 Reserved */
+ uint32_t DMAC:1; /*!< bit: 10 DMAC Interrupt CPU Select */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t EVSYS:1; /*!< bit: 14 EVSYS Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t PICOP:1; /*!< bit: 16 PICOP Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t SERCOM2:1; /*!< bit: 18 SERCOM2 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t SERCOM3:1; /*!< bit: 20 SERCOM3 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t TCC0:1; /*!< bit: 22 TCC0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t TCC1:1; /*!< bit: 24 TCC1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 25 Reserved */
+ uint32_t TC2:1; /*!< bit: 26 TC2 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 27 Reserved */
+ uint32_t TC3:1; /*!< bit: 28 TC3 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t TAL:1; /*!< bit: 30 TAL Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL2_OFFSET 0x130 /**< \brief (TAL_INTCPUSEL2 offset) Interrupts CPU Select 2 */
+#define TAL_INTCPUSEL2_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL2 reset_value) Interrupts CPU Select 2 */
+
+#define TAL_INTCPUSEL2_USB_Pos 0 /**< \brief (TAL_INTCPUSEL2) USB Interrupt CPU Select */
+#define TAL_INTCPUSEL2_USB_Msk (_U_(0x1) << TAL_INTCPUSEL2_USB_Pos)
+#define TAL_INTCPUSEL2_USB(value) (TAL_INTCPUSEL2_USB_Msk & ((value) << TAL_INTCPUSEL2_USB_Pos))
+#define TAL_INTCPUSEL2_NVMCTRL_Pos 4 /**< \brief (TAL_INTCPUSEL2) NVMCTRL Interrupt CPU Select */
+#define TAL_INTCPUSEL2_NVMCTRL_Msk (_U_(0x1) << TAL_INTCPUSEL2_NVMCTRL_Pos)
+#define TAL_INTCPUSEL2_NVMCTRL(value) (TAL_INTCPUSEL2_NVMCTRL_Msk & ((value) << TAL_INTCPUSEL2_NVMCTRL_Pos))
+#define TAL_INTCPUSEL2_DMAC_Pos 10 /**< \brief (TAL_INTCPUSEL2) DMAC Interrupt CPU Select */
+#define TAL_INTCPUSEL2_DMAC_Msk (_U_(0x1) << TAL_INTCPUSEL2_DMAC_Pos)
+#define TAL_INTCPUSEL2_DMAC(value) (TAL_INTCPUSEL2_DMAC_Msk & ((value) << TAL_INTCPUSEL2_DMAC_Pos))
+#define TAL_INTCPUSEL2_EVSYS_Pos 14 /**< \brief (TAL_INTCPUSEL2) EVSYS Interrupt CPU Select */
+#define TAL_INTCPUSEL2_EVSYS_Msk (_U_(0x1) << TAL_INTCPUSEL2_EVSYS_Pos)
+#define TAL_INTCPUSEL2_EVSYS(value) (TAL_INTCPUSEL2_EVSYS_Msk & ((value) << TAL_INTCPUSEL2_EVSYS_Pos))
+#define TAL_INTCPUSEL2_PICOP_Pos 16 /**< \brief (TAL_INTCPUSEL2) PICOP Interrupt CPU Select */
+#define TAL_INTCPUSEL2_PICOP_Msk (_U_(0x1) << TAL_INTCPUSEL2_PICOP_Pos)
+#define TAL_INTCPUSEL2_PICOP(value) (TAL_INTCPUSEL2_PICOP_Msk & ((value) << TAL_INTCPUSEL2_PICOP_Pos))
+#define TAL_INTCPUSEL2_SERCOM2_Pos 18 /**< \brief (TAL_INTCPUSEL2) SERCOM2 Interrupt CPU Select */
+#define TAL_INTCPUSEL2_SERCOM2_Msk (_U_(0x1) << TAL_INTCPUSEL2_SERCOM2_Pos)
+#define TAL_INTCPUSEL2_SERCOM2(value) (TAL_INTCPUSEL2_SERCOM2_Msk & ((value) << TAL_INTCPUSEL2_SERCOM2_Pos))
+#define TAL_INTCPUSEL2_SERCOM3_Pos 20 /**< \brief (TAL_INTCPUSEL2) SERCOM3 Interrupt CPU Select */
+#define TAL_INTCPUSEL2_SERCOM3_Msk (_U_(0x1) << TAL_INTCPUSEL2_SERCOM3_Pos)
+#define TAL_INTCPUSEL2_SERCOM3(value) (TAL_INTCPUSEL2_SERCOM3_Msk & ((value) << TAL_INTCPUSEL2_SERCOM3_Pos))
+#define TAL_INTCPUSEL2_TCC0_Pos 22 /**< \brief (TAL_INTCPUSEL2) TCC0 Interrupt CPU Select */
+#define TAL_INTCPUSEL2_TCC0_Msk (_U_(0x1) << TAL_INTCPUSEL2_TCC0_Pos)
+#define TAL_INTCPUSEL2_TCC0(value) (TAL_INTCPUSEL2_TCC0_Msk & ((value) << TAL_INTCPUSEL2_TCC0_Pos))
+#define TAL_INTCPUSEL2_TCC1_Pos 24 /**< \brief (TAL_INTCPUSEL2) TCC1 Interrupt CPU Select */
+#define TAL_INTCPUSEL2_TCC1_Msk (_U_(0x1) << TAL_INTCPUSEL2_TCC1_Pos)
+#define TAL_INTCPUSEL2_TCC1(value) (TAL_INTCPUSEL2_TCC1_Msk & ((value) << TAL_INTCPUSEL2_TCC1_Pos))
+#define TAL_INTCPUSEL2_TC2_Pos 26 /**< \brief (TAL_INTCPUSEL2) TC2 Interrupt CPU Select */
+#define TAL_INTCPUSEL2_TC2_Msk (_U_(0x1) << TAL_INTCPUSEL2_TC2_Pos)
+#define TAL_INTCPUSEL2_TC2(value) (TAL_INTCPUSEL2_TC2_Msk & ((value) << TAL_INTCPUSEL2_TC2_Pos))
+#define TAL_INTCPUSEL2_TC3_Pos 28 /**< \brief (TAL_INTCPUSEL2) TC3 Interrupt CPU Select */
+#define TAL_INTCPUSEL2_TC3_Msk (_U_(0x1) << TAL_INTCPUSEL2_TC3_Pos)
+#define TAL_INTCPUSEL2_TC3(value) (TAL_INTCPUSEL2_TC3_Msk & ((value) << TAL_INTCPUSEL2_TC3_Pos))
+#define TAL_INTCPUSEL2_TAL_Pos 30 /**< \brief (TAL_INTCPUSEL2) TAL Interrupt CPU Select */
+#define TAL_INTCPUSEL2_TAL_Msk (_U_(0x1) << TAL_INTCPUSEL2_TAL_Pos)
+#define TAL_INTCPUSEL2_TAL(value) (TAL_INTCPUSEL2_TAL_Msk & ((value) << TAL_INTCPUSEL2_TAL_Pos))
+#define TAL_INTCPUSEL2_MASK _U_(0x55554411) /**< \brief (TAL_INTCPUSEL2) MASK Register */
+
+/* -------- TAL_INTCPUSEL3 : (TAL Offset: 0x134) (R/W 32) Interrupts CPU Select 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t RAMECC:1; /*!< bit: 0 RAMECC Interrupt CPU Select */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL3_OFFSET 0x134 /**< \brief (TAL_INTCPUSEL3 offset) Interrupts CPU Select 3 */
+#define TAL_INTCPUSEL3_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL3 reset_value) Interrupts CPU Select 3 */
+
+#define TAL_INTCPUSEL3_RAMECC_Pos 0 /**< \brief (TAL_INTCPUSEL3) RAMECC Interrupt CPU Select */
+#define TAL_INTCPUSEL3_RAMECC_Msk (_U_(0x1) << TAL_INTCPUSEL3_RAMECC_Pos)
+#define TAL_INTCPUSEL3_RAMECC(value) (TAL_INTCPUSEL3_RAMECC_Msk & ((value) << TAL_INTCPUSEL3_RAMECC_Pos))
+#define TAL_INTCPUSEL3_MASK _U_(0x00000001) /**< \brief (TAL_INTCPUSEL3) MASK Register */
+
+/* -------- TAL_INTCPUSEL4 : (TAL Offset: 0x138) (R/W 32) Interrupts CPU Select 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CAN0:1; /*!< bit: 0 CAN0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t CAN1:1; /*!< bit: 2 CAN1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t GMAC:1; /*!< bit: 4 GMAC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t TCC2:1; /*!< bit: 6 TCC2 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TCC3:1; /*!< bit: 8 TCC3 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t TC4:1; /*!< bit: 10 TC4 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TC5:1; /*!< bit: 12 TC5 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 13 Reserved */
+ uint32_t PDEC:1; /*!< bit: 14 PDEC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t AC:1; /*!< bit: 16 AC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t AES:1; /*!< bit: 18 AES Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t TRNG:1; /*!< bit: 20 TRNG Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t ICM:1; /*!< bit: 22 ICM Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PUKCC:1; /*!< bit: 24 PUKCC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 25 Reserved */
+ uint32_t QSPI:1; /*!< bit: 26 QSPI Interrupt CPU Select */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL4_OFFSET 0x138 /**< \brief (TAL_INTCPUSEL4 offset) Interrupts CPU Select 4 */
+#define TAL_INTCPUSEL4_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL4 reset_value) Interrupts CPU Select 4 */
+
+#define TAL_INTCPUSEL4_CAN0_Pos 0 /**< \brief (TAL_INTCPUSEL4) CAN0 Interrupt CPU Select */
+#define TAL_INTCPUSEL4_CAN0_Msk (_U_(0x1) << TAL_INTCPUSEL4_CAN0_Pos)
+#define TAL_INTCPUSEL4_CAN0(value) (TAL_INTCPUSEL4_CAN0_Msk & ((value) << TAL_INTCPUSEL4_CAN0_Pos))
+#define TAL_INTCPUSEL4_CAN1_Pos 2 /**< \brief (TAL_INTCPUSEL4) CAN1 Interrupt CPU Select */
+#define TAL_INTCPUSEL4_CAN1_Msk (_U_(0x1) << TAL_INTCPUSEL4_CAN1_Pos)
+#define TAL_INTCPUSEL4_CAN1(value) (TAL_INTCPUSEL4_CAN1_Msk & ((value) << TAL_INTCPUSEL4_CAN1_Pos))
+#define TAL_INTCPUSEL4_GMAC_Pos 4 /**< \brief (TAL_INTCPUSEL4) GMAC Interrupt CPU Select */
+#define TAL_INTCPUSEL4_GMAC_Msk (_U_(0x1) << TAL_INTCPUSEL4_GMAC_Pos)
+#define TAL_INTCPUSEL4_GMAC(value) (TAL_INTCPUSEL4_GMAC_Msk & ((value) << TAL_INTCPUSEL4_GMAC_Pos))
+#define TAL_INTCPUSEL4_TCC2_Pos 6 /**< \brief (TAL_INTCPUSEL4) TCC2 Interrupt CPU Select */
+#define TAL_INTCPUSEL4_TCC2_Msk (_U_(0x1) << TAL_INTCPUSEL4_TCC2_Pos)
+#define TAL_INTCPUSEL4_TCC2(value) (TAL_INTCPUSEL4_TCC2_Msk & ((value) << TAL_INTCPUSEL4_TCC2_Pos))
+#define TAL_INTCPUSEL4_TCC3_Pos 8 /**< \brief (TAL_INTCPUSEL4) TCC3 Interrupt CPU Select */
+#define TAL_INTCPUSEL4_TCC3_Msk (_U_(0x1) << TAL_INTCPUSEL4_TCC3_Pos)
+#define TAL_INTCPUSEL4_TCC3(value) (TAL_INTCPUSEL4_TCC3_Msk & ((value) << TAL_INTCPUSEL4_TCC3_Pos))
+#define TAL_INTCPUSEL4_TC4_Pos 10 /**< \brief (TAL_INTCPUSEL4) TC4 Interrupt CPU Select */
+#define TAL_INTCPUSEL4_TC4_Msk (_U_(0x1) << TAL_INTCPUSEL4_TC4_Pos)
+#define TAL_INTCPUSEL4_TC4(value) (TAL_INTCPUSEL4_TC4_Msk & ((value) << TAL_INTCPUSEL4_TC4_Pos))
+#define TAL_INTCPUSEL4_TC5_Pos 12 /**< \brief (TAL_INTCPUSEL4) TC5 Interrupt CPU Select */
+#define TAL_INTCPUSEL4_TC5_Msk (_U_(0x1) << TAL_INTCPUSEL4_TC5_Pos)
+#define TAL_INTCPUSEL4_TC5(value) (TAL_INTCPUSEL4_TC5_Msk & ((value) << TAL_INTCPUSEL4_TC5_Pos))
+#define TAL_INTCPUSEL4_PDEC_Pos 14 /**< \brief (TAL_INTCPUSEL4) PDEC Interrupt CPU Select */
+#define TAL_INTCPUSEL4_PDEC_Msk (_U_(0x1) << TAL_INTCPUSEL4_PDEC_Pos)
+#define TAL_INTCPUSEL4_PDEC(value) (TAL_INTCPUSEL4_PDEC_Msk & ((value) << TAL_INTCPUSEL4_PDEC_Pos))
+#define TAL_INTCPUSEL4_AC_Pos 16 /**< \brief (TAL_INTCPUSEL4) AC Interrupt CPU Select */
+#define TAL_INTCPUSEL4_AC_Msk (_U_(0x1) << TAL_INTCPUSEL4_AC_Pos)
+#define TAL_INTCPUSEL4_AC(value) (TAL_INTCPUSEL4_AC_Msk & ((value) << TAL_INTCPUSEL4_AC_Pos))
+#define TAL_INTCPUSEL4_AES_Pos 18 /**< \brief (TAL_INTCPUSEL4) AES Interrupt CPU Select */
+#define TAL_INTCPUSEL4_AES_Msk (_U_(0x1) << TAL_INTCPUSEL4_AES_Pos)
+#define TAL_INTCPUSEL4_AES(value) (TAL_INTCPUSEL4_AES_Msk & ((value) << TAL_INTCPUSEL4_AES_Pos))
+#define TAL_INTCPUSEL4_TRNG_Pos 20 /**< \brief (TAL_INTCPUSEL4) TRNG Interrupt CPU Select */
+#define TAL_INTCPUSEL4_TRNG_Msk (_U_(0x1) << TAL_INTCPUSEL4_TRNG_Pos)
+#define TAL_INTCPUSEL4_TRNG(value) (TAL_INTCPUSEL4_TRNG_Msk & ((value) << TAL_INTCPUSEL4_TRNG_Pos))
+#define TAL_INTCPUSEL4_ICM_Pos 22 /**< \brief (TAL_INTCPUSEL4) ICM Interrupt CPU Select */
+#define TAL_INTCPUSEL4_ICM_Msk (_U_(0x1) << TAL_INTCPUSEL4_ICM_Pos)
+#define TAL_INTCPUSEL4_ICM(value) (TAL_INTCPUSEL4_ICM_Msk & ((value) << TAL_INTCPUSEL4_ICM_Pos))
+#define TAL_INTCPUSEL4_PUKCC_Pos 24 /**< \brief (TAL_INTCPUSEL4) PUKCC Interrupt CPU Select */
+#define TAL_INTCPUSEL4_PUKCC_Msk (_U_(0x1) << TAL_INTCPUSEL4_PUKCC_Pos)
+#define TAL_INTCPUSEL4_PUKCC(value) (TAL_INTCPUSEL4_PUKCC_Msk & ((value) << TAL_INTCPUSEL4_PUKCC_Pos))
+#define TAL_INTCPUSEL4_QSPI_Pos 26 /**< \brief (TAL_INTCPUSEL4) QSPI Interrupt CPU Select */
+#define TAL_INTCPUSEL4_QSPI_Msk (_U_(0x1) << TAL_INTCPUSEL4_QSPI_Pos)
+#define TAL_INTCPUSEL4_QSPI(value) (TAL_INTCPUSEL4_QSPI_Msk & ((value) << TAL_INTCPUSEL4_QSPI_Pos))
+#define TAL_INTCPUSEL4_MASK _U_(0x05555555) /**< \brief (TAL_INTCPUSEL4) MASK Register */
+
+/* -------- TAL_INTCPUSEL5 : (TAL Offset: 0x13C) (R/W 32) Interrupts CPU Select 5 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL5_OFFSET 0x13C /**< \brief (TAL_INTCPUSEL5 offset) Interrupts CPU Select 5 */
+#define TAL_INTCPUSEL5_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL5 reset_value) Interrupts CPU Select 5 */
+#define TAL_INTCPUSEL5_MASK _U_(0x00000000) /**< \brief (TAL_INTCPUSEL5) MASK Register */
+
+/* -------- TAL_INTCPUSEL6 : (TAL Offset: 0x140) (R/W 32) Interrupts CPU Select 6 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERCOM4:1; /*!< bit: 0 SERCOM4 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t SERCOM5:1; /*!< bit: 2 SERCOM5 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t SERCOM6:1; /*!< bit: 4 SERCOM6 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t SERCOM7:1; /*!< bit: 6 SERCOM7 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TCC4:1; /*!< bit: 8 TCC4 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 9 Reserved */
+ uint32_t TC6:1; /*!< bit: 10 TC6 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TC7:1; /*!< bit: 12 TC7 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 13 Reserved */
+ uint32_t ADC0:1; /*!< bit: 14 ADC0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t ADC1:1; /*!< bit: 16 ADC1 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t DAC:1; /*!< bit: 18 DAC Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t I2S:1; /*!< bit: 20 I2S Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 21 Reserved */
+ uint32_t PCC:1; /*!< bit: 22 PCC Interrupt CPU Select */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL6_OFFSET 0x140 /**< \brief (TAL_INTCPUSEL6 offset) Interrupts CPU Select 6 */
+#define TAL_INTCPUSEL6_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL6 reset_value) Interrupts CPU Select 6 */
+
+#define TAL_INTCPUSEL6_SERCOM4_Pos 0 /**< \brief (TAL_INTCPUSEL6) SERCOM4 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_SERCOM4_Msk (_U_(0x1) << TAL_INTCPUSEL6_SERCOM4_Pos)
+#define TAL_INTCPUSEL6_SERCOM4(value) (TAL_INTCPUSEL6_SERCOM4_Msk & ((value) << TAL_INTCPUSEL6_SERCOM4_Pos))
+#define TAL_INTCPUSEL6_SERCOM5_Pos 2 /**< \brief (TAL_INTCPUSEL6) SERCOM5 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_SERCOM5_Msk (_U_(0x1) << TAL_INTCPUSEL6_SERCOM5_Pos)
+#define TAL_INTCPUSEL6_SERCOM5(value) (TAL_INTCPUSEL6_SERCOM5_Msk & ((value) << TAL_INTCPUSEL6_SERCOM5_Pos))
+#define TAL_INTCPUSEL6_SERCOM6_Pos 4 /**< \brief (TAL_INTCPUSEL6) SERCOM6 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_SERCOM6_Msk (_U_(0x1) << TAL_INTCPUSEL6_SERCOM6_Pos)
+#define TAL_INTCPUSEL6_SERCOM6(value) (TAL_INTCPUSEL6_SERCOM6_Msk & ((value) << TAL_INTCPUSEL6_SERCOM6_Pos))
+#define TAL_INTCPUSEL6_SERCOM7_Pos 6 /**< \brief (TAL_INTCPUSEL6) SERCOM7 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_SERCOM7_Msk (_U_(0x1) << TAL_INTCPUSEL6_SERCOM7_Pos)
+#define TAL_INTCPUSEL6_SERCOM7(value) (TAL_INTCPUSEL6_SERCOM7_Msk & ((value) << TAL_INTCPUSEL6_SERCOM7_Pos))
+#define TAL_INTCPUSEL6_TCC4_Pos 8 /**< \brief (TAL_INTCPUSEL6) TCC4 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_TCC4_Msk (_U_(0x1) << TAL_INTCPUSEL6_TCC4_Pos)
+#define TAL_INTCPUSEL6_TCC4(value) (TAL_INTCPUSEL6_TCC4_Msk & ((value) << TAL_INTCPUSEL6_TCC4_Pos))
+#define TAL_INTCPUSEL6_TC6_Pos 10 /**< \brief (TAL_INTCPUSEL6) TC6 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_TC6_Msk (_U_(0x1) << TAL_INTCPUSEL6_TC6_Pos)
+#define TAL_INTCPUSEL6_TC6(value) (TAL_INTCPUSEL6_TC6_Msk & ((value) << TAL_INTCPUSEL6_TC6_Pos))
+#define TAL_INTCPUSEL6_TC7_Pos 12 /**< \brief (TAL_INTCPUSEL6) TC7 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_TC7_Msk (_U_(0x1) << TAL_INTCPUSEL6_TC7_Pos)
+#define TAL_INTCPUSEL6_TC7(value) (TAL_INTCPUSEL6_TC7_Msk & ((value) << TAL_INTCPUSEL6_TC7_Pos))
+#define TAL_INTCPUSEL6_ADC0_Pos 14 /**< \brief (TAL_INTCPUSEL6) ADC0 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_ADC0_Msk (_U_(0x1) << TAL_INTCPUSEL6_ADC0_Pos)
+#define TAL_INTCPUSEL6_ADC0(value) (TAL_INTCPUSEL6_ADC0_Msk & ((value) << TAL_INTCPUSEL6_ADC0_Pos))
+#define TAL_INTCPUSEL6_ADC1_Pos 16 /**< \brief (TAL_INTCPUSEL6) ADC1 Interrupt CPU Select */
+#define TAL_INTCPUSEL6_ADC1_Msk (_U_(0x1) << TAL_INTCPUSEL6_ADC1_Pos)
+#define TAL_INTCPUSEL6_ADC1(value) (TAL_INTCPUSEL6_ADC1_Msk & ((value) << TAL_INTCPUSEL6_ADC1_Pos))
+#define TAL_INTCPUSEL6_DAC_Pos 18 /**< \brief (TAL_INTCPUSEL6) DAC Interrupt CPU Select */
+#define TAL_INTCPUSEL6_DAC_Msk (_U_(0x1) << TAL_INTCPUSEL6_DAC_Pos)
+#define TAL_INTCPUSEL6_DAC(value) (TAL_INTCPUSEL6_DAC_Msk & ((value) << TAL_INTCPUSEL6_DAC_Pos))
+#define TAL_INTCPUSEL6_I2S_Pos 20 /**< \brief (TAL_INTCPUSEL6) I2S Interrupt CPU Select */
+#define TAL_INTCPUSEL6_I2S_Msk (_U_(0x1) << TAL_INTCPUSEL6_I2S_Pos)
+#define TAL_INTCPUSEL6_I2S(value) (TAL_INTCPUSEL6_I2S_Msk & ((value) << TAL_INTCPUSEL6_I2S_Pos))
+#define TAL_INTCPUSEL6_PCC_Pos 22 /**< \brief (TAL_INTCPUSEL6) PCC Interrupt CPU Select */
+#define TAL_INTCPUSEL6_PCC_Msk (_U_(0x1) << TAL_INTCPUSEL6_PCC_Pos)
+#define TAL_INTCPUSEL6_PCC(value) (TAL_INTCPUSEL6_PCC_Msk & ((value) << TAL_INTCPUSEL6_PCC_Pos))
+#define TAL_INTCPUSEL6_MASK _U_(0x00555555) /**< \brief (TAL_INTCPUSEL6) MASK Register */
+
+/* -------- TAL_INTCPUSEL7 : (TAL Offset: 0x144) (R/W 32) Interrupts CPU Select 7 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL7_OFFSET 0x144 /**< \brief (TAL_INTCPUSEL7 offset) Interrupts CPU Select 7 */
+#define TAL_INTCPUSEL7_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL7 reset_value) Interrupts CPU Select 7 */
+#define TAL_INTCPUSEL7_MASK _U_(0x00000000) /**< \brief (TAL_INTCPUSEL7) MASK Register */
+
+/* -------- TAL_INTCPUSEL8 : (TAL Offset: 0x148) (R/W 32) Interrupts CPU Select 8 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SDHC0:1; /*!< bit: 0 SDHC0 Interrupt CPU Select */
+ uint32_t :1; /*!< bit: 1 Reserved */
+ uint32_t SDHC1:1; /*!< bit: 2 SDHC1 Interrupt CPU Select */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_INTCPUSEL8_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_INTCPUSEL8_OFFSET 0x148 /**< \brief (TAL_INTCPUSEL8 offset) Interrupts CPU Select 8 */
+#define TAL_INTCPUSEL8_RESETVALUE _U_(0x00000000) /**< \brief (TAL_INTCPUSEL8 reset_value) Interrupts CPU Select 8 */
+
+#define TAL_INTCPUSEL8_SDHC0_Pos 0 /**< \brief (TAL_INTCPUSEL8) SDHC0 Interrupt CPU Select */
+#define TAL_INTCPUSEL8_SDHC0_Msk (_U_(0x1) << TAL_INTCPUSEL8_SDHC0_Pos)
+#define TAL_INTCPUSEL8_SDHC0(value) (TAL_INTCPUSEL8_SDHC0_Msk & ((value) << TAL_INTCPUSEL8_SDHC0_Pos))
+#define TAL_INTCPUSEL8_SDHC1_Pos 2 /**< \brief (TAL_INTCPUSEL8) SDHC1 Interrupt CPU Select */
+#define TAL_INTCPUSEL8_SDHC1_Msk (_U_(0x1) << TAL_INTCPUSEL8_SDHC1_Pos)
+#define TAL_INTCPUSEL8_SDHC1(value) (TAL_INTCPUSEL8_SDHC1_Msk & ((value) << TAL_INTCPUSEL8_SDHC1_Pos))
+#define TAL_INTCPUSEL8_MASK _U_(0x00000005) /**< \brief (TAL_INTCPUSEL8) MASK Register */
+
+/* -------- TAL_IRQTRIG : (TAL Offset: 0x164) (R/W 32) Interrupt Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Trigger Enable */
+ uint32_t :7; /*!< bit: 1.. 7 Reserved */
+ uint32_t IRQNUM:8; /*!< bit: 8..15 Interrupt Request Number */
+ uint32_t OVERRIDE:8; /*!< bit: 16..23 Interrupt Request Override Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_IRQTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_IRQTRIG_OFFSET 0x164 /**< \brief (TAL_IRQTRIG offset) Interrupt Trigger */
+#define TAL_IRQTRIG_RESETVALUE _U_(0x00000000) /**< \brief (TAL_IRQTRIG reset_value) Interrupt Trigger */
+
+#define TAL_IRQTRIG_ENABLE_Pos 0 /**< \brief (TAL_IRQTRIG) Trigger Enable */
+#define TAL_IRQTRIG_ENABLE (_U_(0x1) << TAL_IRQTRIG_ENABLE_Pos)
+#define TAL_IRQTRIG_IRQNUM_Pos 8 /**< \brief (TAL_IRQTRIG) Interrupt Request Number */
+#define TAL_IRQTRIG_IRQNUM_Msk (_U_(0xFF) << TAL_IRQTRIG_IRQNUM_Pos)
+#define TAL_IRQTRIG_IRQNUM(value) (TAL_IRQTRIG_IRQNUM_Msk & ((value) << TAL_IRQTRIG_IRQNUM_Pos))
+#define TAL_IRQTRIG_OVERRIDE_Pos 16 /**< \brief (TAL_IRQTRIG) Interrupt Request Override Value */
+#define TAL_IRQTRIG_OVERRIDE_Msk (_U_(0xFF) << TAL_IRQTRIG_OVERRIDE_Pos)
+#define TAL_IRQTRIG_OVERRIDE(value) (TAL_IRQTRIG_OVERRIDE_Msk & ((value) << TAL_IRQTRIG_OVERRIDE_Pos))
+#define TAL_IRQTRIG_MASK _U_(0x00FFFF01) /**< \brief (TAL_IRQTRIG) MASK Register */
+
+/* -------- TAL_IRQMON : (TAL Offset: 0x168) (R/W 16) Interrupt Monitor Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EXTEND:1; /*!< bit: 0 Extended Interrupt Request */
+ uint16_t DROP:1; /*!< bit: 1 Drop Shortened Events */
+ uint16_t CPUID:1; /*!< bit: 2 ID of CPU currently servicing this IRQ */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t IRQNUM:8; /*!< bit: 8..15 Interrupt Request Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TAL_IRQMON_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_IRQMON_OFFSET 0x168 /**< \brief (TAL_IRQMON offset) Interrupt Monitor Select */
+#define TAL_IRQMON_RESETVALUE _U_(0x0000) /**< \brief (TAL_IRQMON reset_value) Interrupt Monitor Select */
+
+#define TAL_IRQMON_EXTEND_Pos 0 /**< \brief (TAL_IRQMON) Extended Interrupt Request */
+#define TAL_IRQMON_EXTEND (_U_(0x1) << TAL_IRQMON_EXTEND_Pos)
+#define TAL_IRQMON_EXTEND_NO_Val _U_(0x0) /**< \brief (TAL_IRQMON) Event is Interrupt Request signal */
+#define TAL_IRQMON_EXTEND_YES_Val _U_(0x1) /**< \brief (TAL_IRQMON) Event is Interrupt Request signal extended until end of Interrupt Handler */
+#define TAL_IRQMON_EXTEND_NO (TAL_IRQMON_EXTEND_NO_Val << TAL_IRQMON_EXTEND_Pos)
+#define TAL_IRQMON_EXTEND_YES (TAL_IRQMON_EXTEND_YES_Val << TAL_IRQMON_EXTEND_Pos)
+#define TAL_IRQMON_DROP_Pos 1 /**< \brief (TAL_IRQMON) Drop Shortened Events */
+#define TAL_IRQMON_DROP (_U_(0x1) << TAL_IRQMON_DROP_Pos)
+#define TAL_IRQMON_CPUID_Pos 2 /**< \brief (TAL_IRQMON) ID of CPU currently servicing this IRQ */
+#define TAL_IRQMON_CPUID_Msk (_U_(0x1) << TAL_IRQMON_CPUID_Pos)
+#define TAL_IRQMON_CPUID(value) (TAL_IRQMON_CPUID_Msk & ((value) << TAL_IRQMON_CPUID_Pos))
+#define TAL_IRQMON_IRQNUM_Pos 8 /**< \brief (TAL_IRQMON) Interrupt Request Number */
+#define TAL_IRQMON_IRQNUM_Msk (_U_(0xFF) << TAL_IRQMON_IRQNUM_Pos)
+#define TAL_IRQMON_IRQNUM(value) (TAL_IRQMON_IRQNUM_Msk & ((value) << TAL_IRQMON_IRQNUM_Pos))
+#define TAL_IRQMON_MASK _U_(0xFF07) /**< \brief (TAL_IRQMON) MASK Register */
+
+/* -------- TAL_CPUIRQS : (TAL Offset: 0x180) (R/ 32) CPUIRQS Interrupt Status m for CPU n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CPUIRQS:32; /*!< bit: 0..31 Interrupt Requests for CPU n */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_CPUIRQS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_CPUIRQS_OFFSET 0x180 /**< \brief (TAL_CPUIRQS offset) Interrupt Status m for CPU n */
+#define TAL_CPUIRQS_RESETVALUE _U_(0x00000000) /**< \brief (TAL_CPUIRQS reset_value) Interrupt Status m for CPU n */
+
+#define TAL_CPUIRQS_CPUIRQS_Pos 0 /**< \brief (TAL_CPUIRQS) Interrupt Requests for CPU n */
+#define TAL_CPUIRQS_CPUIRQS_Msk (_U_(0xFFFFFFFF) << TAL_CPUIRQS_CPUIRQS_Pos)
+#define TAL_CPUIRQS_CPUIRQS(value) (TAL_CPUIRQS_CPUIRQS_Msk & ((value) << TAL_CPUIRQS_CPUIRQS_Pos))
+#define TAL_CPUIRQS_MASK _U_(0xFFFFFFFF) /**< \brief (TAL_CPUIRQS) MASK Register */
+
+/* -------- TAL_SMASK : (TAL Offset: 0x200) (R/W 32) SMASKS Inter-Process Signal Mask m for CPU n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IPS0:1; /*!< bit: 0 Inter-Process Signal 0 */
+ uint32_t IPS1:1; /*!< bit: 1 Inter-Process Signal 1 */
+ uint32_t IPS2:1; /*!< bit: 2 Inter-Process Signal 2 */
+ uint32_t IPS3:1; /*!< bit: 3 Inter-Process Signal 3 */
+ uint32_t IPS4:1; /*!< bit: 4 Inter-Process Signal 4 */
+ uint32_t IPS5:1; /*!< bit: 5 Inter-Process Signal 5 */
+ uint32_t IPS6:1; /*!< bit: 6 Inter-Process Signal 6 */
+ uint32_t IPS7:1; /*!< bit: 7 Inter-Process Signal 7 */
+ uint32_t IPS8:1; /*!< bit: 8 Inter-Process Signal 8 */
+ uint32_t IPS9:1; /*!< bit: 9 Inter-Process Signal 9 */
+ uint32_t IPS10:1; /*!< bit: 10 Inter-Process Signal 10 */
+ uint32_t IPS11:1; /*!< bit: 11 Inter-Process Signal 11 */
+ uint32_t IPS12:1; /*!< bit: 12 Inter-Process Signal 12 */
+ uint32_t IPS13:1; /*!< bit: 13 Inter-Process Signal 13 */
+ uint32_t IPS14:1; /*!< bit: 14 Inter-Process Signal 14 */
+ uint32_t IPS15:1; /*!< bit: 15 Inter-Process Signal 15 */
+ uint32_t IPS16:1; /*!< bit: 16 Inter-Process Signal 16 */
+ uint32_t IPS17:1; /*!< bit: 17 Inter-Process Signal 17 */
+ uint32_t IPS18:1; /*!< bit: 18 Inter-Process Signal 18 */
+ uint32_t IPS19:1; /*!< bit: 19 Inter-Process Signal 19 */
+ uint32_t IPS20:1; /*!< bit: 20 Inter-Process Signal 20 */
+ uint32_t IPS21:1; /*!< bit: 21 Inter-Process Signal 21 */
+ uint32_t IPS22:1; /*!< bit: 22 Inter-Process Signal 22 */
+ uint32_t IPS23:1; /*!< bit: 23 Inter-Process Signal 23 */
+ uint32_t IPS24:1; /*!< bit: 24 Inter-Process Signal 24 */
+ uint32_t IPS25:1; /*!< bit: 25 Inter-Process Signal 25 */
+ uint32_t IPS26:1; /*!< bit: 26 Inter-Process Signal 26 */
+ uint32_t IPS27:1; /*!< bit: 27 Inter-Process Signal 27 */
+ uint32_t IPS28:1; /*!< bit: 28 Inter-Process Signal 28 */
+ uint32_t IPS29:1; /*!< bit: 29 Inter-Process Signal 29 */
+ uint32_t IPS30:1; /*!< bit: 30 Inter-Process Signal 30 */
+ uint32_t IPS31:1; /*!< bit: 31 Inter-Process Signal 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t IPS:32; /*!< bit: 0..31 Inter-Process Signal x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_SMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_SMASK_OFFSET 0x200 /**< \brief (TAL_SMASK offset) Inter-Process Signal Mask m for CPU n */
+#define TAL_SMASK_RESETVALUE _U_(0x00000000) /**< \brief (TAL_SMASK reset_value) Inter-Process Signal Mask m for CPU n */
+
+#define TAL_SMASK_IPS0_Pos 0 /**< \brief (TAL_SMASK) Inter-Process Signal 0 */
+#define TAL_SMASK_IPS0 (_U_(1) << TAL_SMASK_IPS0_Pos)
+#define TAL_SMASK_IPS1_Pos 1 /**< \brief (TAL_SMASK) Inter-Process Signal 1 */
+#define TAL_SMASK_IPS1 (_U_(1) << TAL_SMASK_IPS1_Pos)
+#define TAL_SMASK_IPS2_Pos 2 /**< \brief (TAL_SMASK) Inter-Process Signal 2 */
+#define TAL_SMASK_IPS2 (_U_(1) << TAL_SMASK_IPS2_Pos)
+#define TAL_SMASK_IPS3_Pos 3 /**< \brief (TAL_SMASK) Inter-Process Signal 3 */
+#define TAL_SMASK_IPS3 (_U_(1) << TAL_SMASK_IPS3_Pos)
+#define TAL_SMASK_IPS4_Pos 4 /**< \brief (TAL_SMASK) Inter-Process Signal 4 */
+#define TAL_SMASK_IPS4 (_U_(1) << TAL_SMASK_IPS4_Pos)
+#define TAL_SMASK_IPS5_Pos 5 /**< \brief (TAL_SMASK) Inter-Process Signal 5 */
+#define TAL_SMASK_IPS5 (_U_(1) << TAL_SMASK_IPS5_Pos)
+#define TAL_SMASK_IPS6_Pos 6 /**< \brief (TAL_SMASK) Inter-Process Signal 6 */
+#define TAL_SMASK_IPS6 (_U_(1) << TAL_SMASK_IPS6_Pos)
+#define TAL_SMASK_IPS7_Pos 7 /**< \brief (TAL_SMASK) Inter-Process Signal 7 */
+#define TAL_SMASK_IPS7 (_U_(1) << TAL_SMASK_IPS7_Pos)
+#define TAL_SMASK_IPS8_Pos 8 /**< \brief (TAL_SMASK) Inter-Process Signal 8 */
+#define TAL_SMASK_IPS8 (_U_(1) << TAL_SMASK_IPS8_Pos)
+#define TAL_SMASK_IPS9_Pos 9 /**< \brief (TAL_SMASK) Inter-Process Signal 9 */
+#define TAL_SMASK_IPS9 (_U_(1) << TAL_SMASK_IPS9_Pos)
+#define TAL_SMASK_IPS10_Pos 10 /**< \brief (TAL_SMASK) Inter-Process Signal 10 */
+#define TAL_SMASK_IPS10 (_U_(1) << TAL_SMASK_IPS10_Pos)
+#define TAL_SMASK_IPS11_Pos 11 /**< \brief (TAL_SMASK) Inter-Process Signal 11 */
+#define TAL_SMASK_IPS11 (_U_(1) << TAL_SMASK_IPS11_Pos)
+#define TAL_SMASK_IPS12_Pos 12 /**< \brief (TAL_SMASK) Inter-Process Signal 12 */
+#define TAL_SMASK_IPS12 (_U_(1) << TAL_SMASK_IPS12_Pos)
+#define TAL_SMASK_IPS13_Pos 13 /**< \brief (TAL_SMASK) Inter-Process Signal 13 */
+#define TAL_SMASK_IPS13 (_U_(1) << TAL_SMASK_IPS13_Pos)
+#define TAL_SMASK_IPS14_Pos 14 /**< \brief (TAL_SMASK) Inter-Process Signal 14 */
+#define TAL_SMASK_IPS14 (_U_(1) << TAL_SMASK_IPS14_Pos)
+#define TAL_SMASK_IPS15_Pos 15 /**< \brief (TAL_SMASK) Inter-Process Signal 15 */
+#define TAL_SMASK_IPS15 (_U_(1) << TAL_SMASK_IPS15_Pos)
+#define TAL_SMASK_IPS16_Pos 16 /**< \brief (TAL_SMASK) Inter-Process Signal 16 */
+#define TAL_SMASK_IPS16 (_U_(1) << TAL_SMASK_IPS16_Pos)
+#define TAL_SMASK_IPS17_Pos 17 /**< \brief (TAL_SMASK) Inter-Process Signal 17 */
+#define TAL_SMASK_IPS17 (_U_(1) << TAL_SMASK_IPS17_Pos)
+#define TAL_SMASK_IPS18_Pos 18 /**< \brief (TAL_SMASK) Inter-Process Signal 18 */
+#define TAL_SMASK_IPS18 (_U_(1) << TAL_SMASK_IPS18_Pos)
+#define TAL_SMASK_IPS19_Pos 19 /**< \brief (TAL_SMASK) Inter-Process Signal 19 */
+#define TAL_SMASK_IPS19 (_U_(1) << TAL_SMASK_IPS19_Pos)
+#define TAL_SMASK_IPS20_Pos 20 /**< \brief (TAL_SMASK) Inter-Process Signal 20 */
+#define TAL_SMASK_IPS20 (_U_(1) << TAL_SMASK_IPS20_Pos)
+#define TAL_SMASK_IPS21_Pos 21 /**< \brief (TAL_SMASK) Inter-Process Signal 21 */
+#define TAL_SMASK_IPS21 (_U_(1) << TAL_SMASK_IPS21_Pos)
+#define TAL_SMASK_IPS22_Pos 22 /**< \brief (TAL_SMASK) Inter-Process Signal 22 */
+#define TAL_SMASK_IPS22 (_U_(1) << TAL_SMASK_IPS22_Pos)
+#define TAL_SMASK_IPS23_Pos 23 /**< \brief (TAL_SMASK) Inter-Process Signal 23 */
+#define TAL_SMASK_IPS23 (_U_(1) << TAL_SMASK_IPS23_Pos)
+#define TAL_SMASK_IPS24_Pos 24 /**< \brief (TAL_SMASK) Inter-Process Signal 24 */
+#define TAL_SMASK_IPS24 (_U_(1) << TAL_SMASK_IPS24_Pos)
+#define TAL_SMASK_IPS25_Pos 25 /**< \brief (TAL_SMASK) Inter-Process Signal 25 */
+#define TAL_SMASK_IPS25 (_U_(1) << TAL_SMASK_IPS25_Pos)
+#define TAL_SMASK_IPS26_Pos 26 /**< \brief (TAL_SMASK) Inter-Process Signal 26 */
+#define TAL_SMASK_IPS26 (_U_(1) << TAL_SMASK_IPS26_Pos)
+#define TAL_SMASK_IPS27_Pos 27 /**< \brief (TAL_SMASK) Inter-Process Signal 27 */
+#define TAL_SMASK_IPS27 (_U_(1) << TAL_SMASK_IPS27_Pos)
+#define TAL_SMASK_IPS28_Pos 28 /**< \brief (TAL_SMASK) Inter-Process Signal 28 */
+#define TAL_SMASK_IPS28 (_U_(1) << TAL_SMASK_IPS28_Pos)
+#define TAL_SMASK_IPS29_Pos 29 /**< \brief (TAL_SMASK) Inter-Process Signal 29 */
+#define TAL_SMASK_IPS29 (_U_(1) << TAL_SMASK_IPS29_Pos)
+#define TAL_SMASK_IPS30_Pos 30 /**< \brief (TAL_SMASK) Inter-Process Signal 30 */
+#define TAL_SMASK_IPS30 (_U_(1) << TAL_SMASK_IPS30_Pos)
+#define TAL_SMASK_IPS31_Pos 31 /**< \brief (TAL_SMASK) Inter-Process Signal 31 */
+#define TAL_SMASK_IPS31 (_U_(1) << TAL_SMASK_IPS31_Pos)
+#define TAL_SMASK_IPS_Pos 0 /**< \brief (TAL_SMASK) Inter-Process Signal x */
+#define TAL_SMASK_IPS_Msk (_U_(0xFFFFFFFF) << TAL_SMASK_IPS_Pos)
+#define TAL_SMASK_IPS(value) (TAL_SMASK_IPS_Msk & ((value) << TAL_SMASK_IPS_Pos))
+#define TAL_SMASK_MASK _U_(0xFFFFFFFF) /**< \brief (TAL_SMASK) MASK Register */
+
+/* -------- TAL_SFLAGCLR : (TAL Offset: 0x220) ( /W 32) Inter-Process Signal Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IPS0:1; /*!< bit: 0 Inter-Process Signal 0 */
+ uint32_t IPS1:1; /*!< bit: 1 Inter-Process Signal 1 */
+ uint32_t IPS2:1; /*!< bit: 2 Inter-Process Signal 2 */
+ uint32_t IPS3:1; /*!< bit: 3 Inter-Process Signal 3 */
+ uint32_t IPS4:1; /*!< bit: 4 Inter-Process Signal 4 */
+ uint32_t IPS5:1; /*!< bit: 5 Inter-Process Signal 5 */
+ uint32_t IPS6:1; /*!< bit: 6 Inter-Process Signal 6 */
+ uint32_t IPS7:1; /*!< bit: 7 Inter-Process Signal 7 */
+ uint32_t IPS8:1; /*!< bit: 8 Inter-Process Signal 8 */
+ uint32_t IPS9:1; /*!< bit: 9 Inter-Process Signal 9 */
+ uint32_t IPS10:1; /*!< bit: 10 Inter-Process Signal 10 */
+ uint32_t IPS11:1; /*!< bit: 11 Inter-Process Signal 11 */
+ uint32_t IPS12:1; /*!< bit: 12 Inter-Process Signal 12 */
+ uint32_t IPS13:1; /*!< bit: 13 Inter-Process Signal 13 */
+ uint32_t IPS14:1; /*!< bit: 14 Inter-Process Signal 14 */
+ uint32_t IPS15:1; /*!< bit: 15 Inter-Process Signal 15 */
+ uint32_t IPS16:1; /*!< bit: 16 Inter-Process Signal 16 */
+ uint32_t IPS17:1; /*!< bit: 17 Inter-Process Signal 17 */
+ uint32_t IPS18:1; /*!< bit: 18 Inter-Process Signal 18 */
+ uint32_t IPS19:1; /*!< bit: 19 Inter-Process Signal 19 */
+ uint32_t IPS20:1; /*!< bit: 20 Inter-Process Signal 20 */
+ uint32_t IPS21:1; /*!< bit: 21 Inter-Process Signal 21 */
+ uint32_t IPS22:1; /*!< bit: 22 Inter-Process Signal 22 */
+ uint32_t IPS23:1; /*!< bit: 23 Inter-Process Signal 23 */
+ uint32_t IPS24:1; /*!< bit: 24 Inter-Process Signal 24 */
+ uint32_t IPS25:1; /*!< bit: 25 Inter-Process Signal 25 */
+ uint32_t IPS26:1; /*!< bit: 26 Inter-Process Signal 26 */
+ uint32_t IPS27:1; /*!< bit: 27 Inter-Process Signal 27 */
+ uint32_t IPS28:1; /*!< bit: 28 Inter-Process Signal 28 */
+ uint32_t IPS29:1; /*!< bit: 29 Inter-Process Signal 29 */
+ uint32_t IPS30:1; /*!< bit: 30 Inter-Process Signal 30 */
+ uint32_t IPS31:1; /*!< bit: 31 Inter-Process Signal 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t IPS:32; /*!< bit: 0..31 Inter-Process Signal x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_SFLAGCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_SFLAGCLR_OFFSET 0x220 /**< \brief (TAL_SFLAGCLR offset) Inter-Process Signal Flag Clear */
+#define TAL_SFLAGCLR_RESETVALUE _U_(0x00000000) /**< \brief (TAL_SFLAGCLR reset_value) Inter-Process Signal Flag Clear */
+
+#define TAL_SFLAGCLR_IPS0_Pos 0 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 0 */
+#define TAL_SFLAGCLR_IPS0 (_U_(1) << TAL_SFLAGCLR_IPS0_Pos)
+#define TAL_SFLAGCLR_IPS1_Pos 1 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 1 */
+#define TAL_SFLAGCLR_IPS1 (_U_(1) << TAL_SFLAGCLR_IPS1_Pos)
+#define TAL_SFLAGCLR_IPS2_Pos 2 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 2 */
+#define TAL_SFLAGCLR_IPS2 (_U_(1) << TAL_SFLAGCLR_IPS2_Pos)
+#define TAL_SFLAGCLR_IPS3_Pos 3 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 3 */
+#define TAL_SFLAGCLR_IPS3 (_U_(1) << TAL_SFLAGCLR_IPS3_Pos)
+#define TAL_SFLAGCLR_IPS4_Pos 4 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 4 */
+#define TAL_SFLAGCLR_IPS4 (_U_(1) << TAL_SFLAGCLR_IPS4_Pos)
+#define TAL_SFLAGCLR_IPS5_Pos 5 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 5 */
+#define TAL_SFLAGCLR_IPS5 (_U_(1) << TAL_SFLAGCLR_IPS5_Pos)
+#define TAL_SFLAGCLR_IPS6_Pos 6 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 6 */
+#define TAL_SFLAGCLR_IPS6 (_U_(1) << TAL_SFLAGCLR_IPS6_Pos)
+#define TAL_SFLAGCLR_IPS7_Pos 7 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 7 */
+#define TAL_SFLAGCLR_IPS7 (_U_(1) << TAL_SFLAGCLR_IPS7_Pos)
+#define TAL_SFLAGCLR_IPS8_Pos 8 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 8 */
+#define TAL_SFLAGCLR_IPS8 (_U_(1) << TAL_SFLAGCLR_IPS8_Pos)
+#define TAL_SFLAGCLR_IPS9_Pos 9 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 9 */
+#define TAL_SFLAGCLR_IPS9 (_U_(1) << TAL_SFLAGCLR_IPS9_Pos)
+#define TAL_SFLAGCLR_IPS10_Pos 10 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 10 */
+#define TAL_SFLAGCLR_IPS10 (_U_(1) << TAL_SFLAGCLR_IPS10_Pos)
+#define TAL_SFLAGCLR_IPS11_Pos 11 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 11 */
+#define TAL_SFLAGCLR_IPS11 (_U_(1) << TAL_SFLAGCLR_IPS11_Pos)
+#define TAL_SFLAGCLR_IPS12_Pos 12 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 12 */
+#define TAL_SFLAGCLR_IPS12 (_U_(1) << TAL_SFLAGCLR_IPS12_Pos)
+#define TAL_SFLAGCLR_IPS13_Pos 13 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 13 */
+#define TAL_SFLAGCLR_IPS13 (_U_(1) << TAL_SFLAGCLR_IPS13_Pos)
+#define TAL_SFLAGCLR_IPS14_Pos 14 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 14 */
+#define TAL_SFLAGCLR_IPS14 (_U_(1) << TAL_SFLAGCLR_IPS14_Pos)
+#define TAL_SFLAGCLR_IPS15_Pos 15 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 15 */
+#define TAL_SFLAGCLR_IPS15 (_U_(1) << TAL_SFLAGCLR_IPS15_Pos)
+#define TAL_SFLAGCLR_IPS16_Pos 16 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 16 */
+#define TAL_SFLAGCLR_IPS16 (_U_(1) << TAL_SFLAGCLR_IPS16_Pos)
+#define TAL_SFLAGCLR_IPS17_Pos 17 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 17 */
+#define TAL_SFLAGCLR_IPS17 (_U_(1) << TAL_SFLAGCLR_IPS17_Pos)
+#define TAL_SFLAGCLR_IPS18_Pos 18 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 18 */
+#define TAL_SFLAGCLR_IPS18 (_U_(1) << TAL_SFLAGCLR_IPS18_Pos)
+#define TAL_SFLAGCLR_IPS19_Pos 19 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 19 */
+#define TAL_SFLAGCLR_IPS19 (_U_(1) << TAL_SFLAGCLR_IPS19_Pos)
+#define TAL_SFLAGCLR_IPS20_Pos 20 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 20 */
+#define TAL_SFLAGCLR_IPS20 (_U_(1) << TAL_SFLAGCLR_IPS20_Pos)
+#define TAL_SFLAGCLR_IPS21_Pos 21 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 21 */
+#define TAL_SFLAGCLR_IPS21 (_U_(1) << TAL_SFLAGCLR_IPS21_Pos)
+#define TAL_SFLAGCLR_IPS22_Pos 22 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 22 */
+#define TAL_SFLAGCLR_IPS22 (_U_(1) << TAL_SFLAGCLR_IPS22_Pos)
+#define TAL_SFLAGCLR_IPS23_Pos 23 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 23 */
+#define TAL_SFLAGCLR_IPS23 (_U_(1) << TAL_SFLAGCLR_IPS23_Pos)
+#define TAL_SFLAGCLR_IPS24_Pos 24 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 24 */
+#define TAL_SFLAGCLR_IPS24 (_U_(1) << TAL_SFLAGCLR_IPS24_Pos)
+#define TAL_SFLAGCLR_IPS25_Pos 25 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 25 */
+#define TAL_SFLAGCLR_IPS25 (_U_(1) << TAL_SFLAGCLR_IPS25_Pos)
+#define TAL_SFLAGCLR_IPS26_Pos 26 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 26 */
+#define TAL_SFLAGCLR_IPS26 (_U_(1) << TAL_SFLAGCLR_IPS26_Pos)
+#define TAL_SFLAGCLR_IPS27_Pos 27 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 27 */
+#define TAL_SFLAGCLR_IPS27 (_U_(1) << TAL_SFLAGCLR_IPS27_Pos)
+#define TAL_SFLAGCLR_IPS28_Pos 28 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 28 */
+#define TAL_SFLAGCLR_IPS28 (_U_(1) << TAL_SFLAGCLR_IPS28_Pos)
+#define TAL_SFLAGCLR_IPS29_Pos 29 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 29 */
+#define TAL_SFLAGCLR_IPS29 (_U_(1) << TAL_SFLAGCLR_IPS29_Pos)
+#define TAL_SFLAGCLR_IPS30_Pos 30 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 30 */
+#define TAL_SFLAGCLR_IPS30 (_U_(1) << TAL_SFLAGCLR_IPS30_Pos)
+#define TAL_SFLAGCLR_IPS31_Pos 31 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 31 */
+#define TAL_SFLAGCLR_IPS31 (_U_(1) << TAL_SFLAGCLR_IPS31_Pos)
+#define TAL_SFLAGCLR_IPS_Pos 0 /**< \brief (TAL_SFLAGCLR) Inter-Process Signal x */
+#define TAL_SFLAGCLR_IPS_Msk (_U_(0xFFFFFFFF) << TAL_SFLAGCLR_IPS_Pos)
+#define TAL_SFLAGCLR_IPS(value) (TAL_SFLAGCLR_IPS_Msk & ((value) << TAL_SFLAGCLR_IPS_Pos))
+#define TAL_SFLAGCLR_MASK _U_(0xFFFFFFFF) /**< \brief (TAL_SFLAGCLR) MASK Register */
+
+/* -------- TAL_SFLAGSET : (TAL Offset: 0x228) ( /W 32) Inter-Process Signal Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IPS0:1; /*!< bit: 0 Inter-Process Signal 0 */
+ uint32_t IPS1:1; /*!< bit: 1 Inter-Process Signal 1 */
+ uint32_t IPS2:1; /*!< bit: 2 Inter-Process Signal 2 */
+ uint32_t IPS3:1; /*!< bit: 3 Inter-Process Signal 3 */
+ uint32_t IPS4:1; /*!< bit: 4 Inter-Process Signal 4 */
+ uint32_t IPS5:1; /*!< bit: 5 Inter-Process Signal 5 */
+ uint32_t IPS6:1; /*!< bit: 6 Inter-Process Signal 6 */
+ uint32_t IPS7:1; /*!< bit: 7 Inter-Process Signal 7 */
+ uint32_t IPS8:1; /*!< bit: 8 Inter-Process Signal 8 */
+ uint32_t IPS9:1; /*!< bit: 9 Inter-Process Signal 9 */
+ uint32_t IPS10:1; /*!< bit: 10 Inter-Process Signal 10 */
+ uint32_t IPS11:1; /*!< bit: 11 Inter-Process Signal 11 */
+ uint32_t IPS12:1; /*!< bit: 12 Inter-Process Signal 12 */
+ uint32_t IPS13:1; /*!< bit: 13 Inter-Process Signal 13 */
+ uint32_t IPS14:1; /*!< bit: 14 Inter-Process Signal 14 */
+ uint32_t IPS15:1; /*!< bit: 15 Inter-Process Signal 15 */
+ uint32_t IPS16:1; /*!< bit: 16 Inter-Process Signal 16 */
+ uint32_t IPS17:1; /*!< bit: 17 Inter-Process Signal 17 */
+ uint32_t IPS18:1; /*!< bit: 18 Inter-Process Signal 18 */
+ uint32_t IPS19:1; /*!< bit: 19 Inter-Process Signal 19 */
+ uint32_t IPS20:1; /*!< bit: 20 Inter-Process Signal 20 */
+ uint32_t IPS21:1; /*!< bit: 21 Inter-Process Signal 21 */
+ uint32_t IPS22:1; /*!< bit: 22 Inter-Process Signal 22 */
+ uint32_t IPS23:1; /*!< bit: 23 Inter-Process Signal 23 */
+ uint32_t IPS24:1; /*!< bit: 24 Inter-Process Signal 24 */
+ uint32_t IPS25:1; /*!< bit: 25 Inter-Process Signal 25 */
+ uint32_t IPS26:1; /*!< bit: 26 Inter-Process Signal 26 */
+ uint32_t IPS27:1; /*!< bit: 27 Inter-Process Signal 27 */
+ uint32_t IPS28:1; /*!< bit: 28 Inter-Process Signal 28 */
+ uint32_t IPS29:1; /*!< bit: 29 Inter-Process Signal 29 */
+ uint32_t IPS30:1; /*!< bit: 30 Inter-Process Signal 30 */
+ uint32_t IPS31:1; /*!< bit: 31 Inter-Process Signal 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t IPS:32; /*!< bit: 0..31 Inter-Process Signal x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_SFLAGSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_SFLAGSET_OFFSET 0x228 /**< \brief (TAL_SFLAGSET offset) Inter-Process Signal Flag Set */
+#define TAL_SFLAGSET_RESETVALUE _U_(0x00000000) /**< \brief (TAL_SFLAGSET reset_value) Inter-Process Signal Flag Set */
+
+#define TAL_SFLAGSET_IPS0_Pos 0 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 0 */
+#define TAL_SFLAGSET_IPS0 (_U_(1) << TAL_SFLAGSET_IPS0_Pos)
+#define TAL_SFLAGSET_IPS1_Pos 1 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 1 */
+#define TAL_SFLAGSET_IPS1 (_U_(1) << TAL_SFLAGSET_IPS1_Pos)
+#define TAL_SFLAGSET_IPS2_Pos 2 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 2 */
+#define TAL_SFLAGSET_IPS2 (_U_(1) << TAL_SFLAGSET_IPS2_Pos)
+#define TAL_SFLAGSET_IPS3_Pos 3 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 3 */
+#define TAL_SFLAGSET_IPS3 (_U_(1) << TAL_SFLAGSET_IPS3_Pos)
+#define TAL_SFLAGSET_IPS4_Pos 4 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 4 */
+#define TAL_SFLAGSET_IPS4 (_U_(1) << TAL_SFLAGSET_IPS4_Pos)
+#define TAL_SFLAGSET_IPS5_Pos 5 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 5 */
+#define TAL_SFLAGSET_IPS5 (_U_(1) << TAL_SFLAGSET_IPS5_Pos)
+#define TAL_SFLAGSET_IPS6_Pos 6 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 6 */
+#define TAL_SFLAGSET_IPS6 (_U_(1) << TAL_SFLAGSET_IPS6_Pos)
+#define TAL_SFLAGSET_IPS7_Pos 7 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 7 */
+#define TAL_SFLAGSET_IPS7 (_U_(1) << TAL_SFLAGSET_IPS7_Pos)
+#define TAL_SFLAGSET_IPS8_Pos 8 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 8 */
+#define TAL_SFLAGSET_IPS8 (_U_(1) << TAL_SFLAGSET_IPS8_Pos)
+#define TAL_SFLAGSET_IPS9_Pos 9 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 9 */
+#define TAL_SFLAGSET_IPS9 (_U_(1) << TAL_SFLAGSET_IPS9_Pos)
+#define TAL_SFLAGSET_IPS10_Pos 10 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 10 */
+#define TAL_SFLAGSET_IPS10 (_U_(1) << TAL_SFLAGSET_IPS10_Pos)
+#define TAL_SFLAGSET_IPS11_Pos 11 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 11 */
+#define TAL_SFLAGSET_IPS11 (_U_(1) << TAL_SFLAGSET_IPS11_Pos)
+#define TAL_SFLAGSET_IPS12_Pos 12 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 12 */
+#define TAL_SFLAGSET_IPS12 (_U_(1) << TAL_SFLAGSET_IPS12_Pos)
+#define TAL_SFLAGSET_IPS13_Pos 13 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 13 */
+#define TAL_SFLAGSET_IPS13 (_U_(1) << TAL_SFLAGSET_IPS13_Pos)
+#define TAL_SFLAGSET_IPS14_Pos 14 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 14 */
+#define TAL_SFLAGSET_IPS14 (_U_(1) << TAL_SFLAGSET_IPS14_Pos)
+#define TAL_SFLAGSET_IPS15_Pos 15 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 15 */
+#define TAL_SFLAGSET_IPS15 (_U_(1) << TAL_SFLAGSET_IPS15_Pos)
+#define TAL_SFLAGSET_IPS16_Pos 16 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 16 */
+#define TAL_SFLAGSET_IPS16 (_U_(1) << TAL_SFLAGSET_IPS16_Pos)
+#define TAL_SFLAGSET_IPS17_Pos 17 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 17 */
+#define TAL_SFLAGSET_IPS17 (_U_(1) << TAL_SFLAGSET_IPS17_Pos)
+#define TAL_SFLAGSET_IPS18_Pos 18 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 18 */
+#define TAL_SFLAGSET_IPS18 (_U_(1) << TAL_SFLAGSET_IPS18_Pos)
+#define TAL_SFLAGSET_IPS19_Pos 19 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 19 */
+#define TAL_SFLAGSET_IPS19 (_U_(1) << TAL_SFLAGSET_IPS19_Pos)
+#define TAL_SFLAGSET_IPS20_Pos 20 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 20 */
+#define TAL_SFLAGSET_IPS20 (_U_(1) << TAL_SFLAGSET_IPS20_Pos)
+#define TAL_SFLAGSET_IPS21_Pos 21 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 21 */
+#define TAL_SFLAGSET_IPS21 (_U_(1) << TAL_SFLAGSET_IPS21_Pos)
+#define TAL_SFLAGSET_IPS22_Pos 22 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 22 */
+#define TAL_SFLAGSET_IPS22 (_U_(1) << TAL_SFLAGSET_IPS22_Pos)
+#define TAL_SFLAGSET_IPS23_Pos 23 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 23 */
+#define TAL_SFLAGSET_IPS23 (_U_(1) << TAL_SFLAGSET_IPS23_Pos)
+#define TAL_SFLAGSET_IPS24_Pos 24 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 24 */
+#define TAL_SFLAGSET_IPS24 (_U_(1) << TAL_SFLAGSET_IPS24_Pos)
+#define TAL_SFLAGSET_IPS25_Pos 25 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 25 */
+#define TAL_SFLAGSET_IPS25 (_U_(1) << TAL_SFLAGSET_IPS25_Pos)
+#define TAL_SFLAGSET_IPS26_Pos 26 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 26 */
+#define TAL_SFLAGSET_IPS26 (_U_(1) << TAL_SFLAGSET_IPS26_Pos)
+#define TAL_SFLAGSET_IPS27_Pos 27 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 27 */
+#define TAL_SFLAGSET_IPS27 (_U_(1) << TAL_SFLAGSET_IPS27_Pos)
+#define TAL_SFLAGSET_IPS28_Pos 28 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 28 */
+#define TAL_SFLAGSET_IPS28 (_U_(1) << TAL_SFLAGSET_IPS28_Pos)
+#define TAL_SFLAGSET_IPS29_Pos 29 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 29 */
+#define TAL_SFLAGSET_IPS29 (_U_(1) << TAL_SFLAGSET_IPS29_Pos)
+#define TAL_SFLAGSET_IPS30_Pos 30 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 30 */
+#define TAL_SFLAGSET_IPS30 (_U_(1) << TAL_SFLAGSET_IPS30_Pos)
+#define TAL_SFLAGSET_IPS31_Pos 31 /**< \brief (TAL_SFLAGSET) Inter-Process Signal 31 */
+#define TAL_SFLAGSET_IPS31 (_U_(1) << TAL_SFLAGSET_IPS31_Pos)
+#define TAL_SFLAGSET_IPS_Pos 0 /**< \brief (TAL_SFLAGSET) Inter-Process Signal x */
+#define TAL_SFLAGSET_IPS_Msk (_U_(0xFFFFFFFF) << TAL_SFLAGSET_IPS_Pos)
+#define TAL_SFLAGSET_IPS(value) (TAL_SFLAGSET_IPS_Msk & ((value) << TAL_SFLAGSET_IPS_Pos))
+#define TAL_SFLAGSET_MASK _U_(0xFFFFFFFF) /**< \brief (TAL_SFLAGSET) MASK Register */
+
+/* -------- TAL_SFLAG : (TAL Offset: 0x230) (R/ 32) Inter-Process Signal Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IPS0:1; /*!< bit: 0 Inter-Process Signal 0 */
+ uint32_t IPS1:1; /*!< bit: 1 Inter-Process Signal 1 */
+ uint32_t IPS2:1; /*!< bit: 2 Inter-Process Signal 2 */
+ uint32_t IPS3:1; /*!< bit: 3 Inter-Process Signal 3 */
+ uint32_t IPS4:1; /*!< bit: 4 Inter-Process Signal 4 */
+ uint32_t IPS5:1; /*!< bit: 5 Inter-Process Signal 5 */
+ uint32_t IPS6:1; /*!< bit: 6 Inter-Process Signal 6 */
+ uint32_t IPS7:1; /*!< bit: 7 Inter-Process Signal 7 */
+ uint32_t IPS8:1; /*!< bit: 8 Inter-Process Signal 8 */
+ uint32_t IPS9:1; /*!< bit: 9 Inter-Process Signal 9 */
+ uint32_t IPS10:1; /*!< bit: 10 Inter-Process Signal 10 */
+ uint32_t IPS11:1; /*!< bit: 11 Inter-Process Signal 11 */
+ uint32_t IPS12:1; /*!< bit: 12 Inter-Process Signal 12 */
+ uint32_t IPS13:1; /*!< bit: 13 Inter-Process Signal 13 */
+ uint32_t IPS14:1; /*!< bit: 14 Inter-Process Signal 14 */
+ uint32_t IPS15:1; /*!< bit: 15 Inter-Process Signal 15 */
+ uint32_t IPS16:1; /*!< bit: 16 Inter-Process Signal 16 */
+ uint32_t IPS17:1; /*!< bit: 17 Inter-Process Signal 17 */
+ uint32_t IPS18:1; /*!< bit: 18 Inter-Process Signal 18 */
+ uint32_t IPS19:1; /*!< bit: 19 Inter-Process Signal 19 */
+ uint32_t IPS20:1; /*!< bit: 20 Inter-Process Signal 20 */
+ uint32_t IPS21:1; /*!< bit: 21 Inter-Process Signal 21 */
+ uint32_t IPS22:1; /*!< bit: 22 Inter-Process Signal 22 */
+ uint32_t IPS23:1; /*!< bit: 23 Inter-Process Signal 23 */
+ uint32_t IPS24:1; /*!< bit: 24 Inter-Process Signal 24 */
+ uint32_t IPS25:1; /*!< bit: 25 Inter-Process Signal 25 */
+ uint32_t IPS26:1; /*!< bit: 26 Inter-Process Signal 26 */
+ uint32_t IPS27:1; /*!< bit: 27 Inter-Process Signal 27 */
+ uint32_t IPS28:1; /*!< bit: 28 Inter-Process Signal 28 */
+ uint32_t IPS29:1; /*!< bit: 29 Inter-Process Signal 29 */
+ uint32_t IPS30:1; /*!< bit: 30 Inter-Process Signal 30 */
+ uint32_t IPS31:1; /*!< bit: 31 Inter-Process Signal 31 */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t IPS:32; /*!< bit: 0..31 Inter-Process Signal x */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TAL_SFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_SFLAG_OFFSET 0x230 /**< \brief (TAL_SFLAG offset) Inter-Process Signal Flag */
+#define TAL_SFLAG_RESETVALUE _U_(0x00000000) /**< \brief (TAL_SFLAG reset_value) Inter-Process Signal Flag */
+
+#define TAL_SFLAG_IPS0_Pos 0 /**< \brief (TAL_SFLAG) Inter-Process Signal 0 */
+#define TAL_SFLAG_IPS0 (_U_(1) << TAL_SFLAG_IPS0_Pos)
+#define TAL_SFLAG_IPS1_Pos 1 /**< \brief (TAL_SFLAG) Inter-Process Signal 1 */
+#define TAL_SFLAG_IPS1 (_U_(1) << TAL_SFLAG_IPS1_Pos)
+#define TAL_SFLAG_IPS2_Pos 2 /**< \brief (TAL_SFLAG) Inter-Process Signal 2 */
+#define TAL_SFLAG_IPS2 (_U_(1) << TAL_SFLAG_IPS2_Pos)
+#define TAL_SFLAG_IPS3_Pos 3 /**< \brief (TAL_SFLAG) Inter-Process Signal 3 */
+#define TAL_SFLAG_IPS3 (_U_(1) << TAL_SFLAG_IPS3_Pos)
+#define TAL_SFLAG_IPS4_Pos 4 /**< \brief (TAL_SFLAG) Inter-Process Signal 4 */
+#define TAL_SFLAG_IPS4 (_U_(1) << TAL_SFLAG_IPS4_Pos)
+#define TAL_SFLAG_IPS5_Pos 5 /**< \brief (TAL_SFLAG) Inter-Process Signal 5 */
+#define TAL_SFLAG_IPS5 (_U_(1) << TAL_SFLAG_IPS5_Pos)
+#define TAL_SFLAG_IPS6_Pos 6 /**< \brief (TAL_SFLAG) Inter-Process Signal 6 */
+#define TAL_SFLAG_IPS6 (_U_(1) << TAL_SFLAG_IPS6_Pos)
+#define TAL_SFLAG_IPS7_Pos 7 /**< \brief (TAL_SFLAG) Inter-Process Signal 7 */
+#define TAL_SFLAG_IPS7 (_U_(1) << TAL_SFLAG_IPS7_Pos)
+#define TAL_SFLAG_IPS8_Pos 8 /**< \brief (TAL_SFLAG) Inter-Process Signal 8 */
+#define TAL_SFLAG_IPS8 (_U_(1) << TAL_SFLAG_IPS8_Pos)
+#define TAL_SFLAG_IPS9_Pos 9 /**< \brief (TAL_SFLAG) Inter-Process Signal 9 */
+#define TAL_SFLAG_IPS9 (_U_(1) << TAL_SFLAG_IPS9_Pos)
+#define TAL_SFLAG_IPS10_Pos 10 /**< \brief (TAL_SFLAG) Inter-Process Signal 10 */
+#define TAL_SFLAG_IPS10 (_U_(1) << TAL_SFLAG_IPS10_Pos)
+#define TAL_SFLAG_IPS11_Pos 11 /**< \brief (TAL_SFLAG) Inter-Process Signal 11 */
+#define TAL_SFLAG_IPS11 (_U_(1) << TAL_SFLAG_IPS11_Pos)
+#define TAL_SFLAG_IPS12_Pos 12 /**< \brief (TAL_SFLAG) Inter-Process Signal 12 */
+#define TAL_SFLAG_IPS12 (_U_(1) << TAL_SFLAG_IPS12_Pos)
+#define TAL_SFLAG_IPS13_Pos 13 /**< \brief (TAL_SFLAG) Inter-Process Signal 13 */
+#define TAL_SFLAG_IPS13 (_U_(1) << TAL_SFLAG_IPS13_Pos)
+#define TAL_SFLAG_IPS14_Pos 14 /**< \brief (TAL_SFLAG) Inter-Process Signal 14 */
+#define TAL_SFLAG_IPS14 (_U_(1) << TAL_SFLAG_IPS14_Pos)
+#define TAL_SFLAG_IPS15_Pos 15 /**< \brief (TAL_SFLAG) Inter-Process Signal 15 */
+#define TAL_SFLAG_IPS15 (_U_(1) << TAL_SFLAG_IPS15_Pos)
+#define TAL_SFLAG_IPS16_Pos 16 /**< \brief (TAL_SFLAG) Inter-Process Signal 16 */
+#define TAL_SFLAG_IPS16 (_U_(1) << TAL_SFLAG_IPS16_Pos)
+#define TAL_SFLAG_IPS17_Pos 17 /**< \brief (TAL_SFLAG) Inter-Process Signal 17 */
+#define TAL_SFLAG_IPS17 (_U_(1) << TAL_SFLAG_IPS17_Pos)
+#define TAL_SFLAG_IPS18_Pos 18 /**< \brief (TAL_SFLAG) Inter-Process Signal 18 */
+#define TAL_SFLAG_IPS18 (_U_(1) << TAL_SFLAG_IPS18_Pos)
+#define TAL_SFLAG_IPS19_Pos 19 /**< \brief (TAL_SFLAG) Inter-Process Signal 19 */
+#define TAL_SFLAG_IPS19 (_U_(1) << TAL_SFLAG_IPS19_Pos)
+#define TAL_SFLAG_IPS20_Pos 20 /**< \brief (TAL_SFLAG) Inter-Process Signal 20 */
+#define TAL_SFLAG_IPS20 (_U_(1) << TAL_SFLAG_IPS20_Pos)
+#define TAL_SFLAG_IPS21_Pos 21 /**< \brief (TAL_SFLAG) Inter-Process Signal 21 */
+#define TAL_SFLAG_IPS21 (_U_(1) << TAL_SFLAG_IPS21_Pos)
+#define TAL_SFLAG_IPS22_Pos 22 /**< \brief (TAL_SFLAG) Inter-Process Signal 22 */
+#define TAL_SFLAG_IPS22 (_U_(1) << TAL_SFLAG_IPS22_Pos)
+#define TAL_SFLAG_IPS23_Pos 23 /**< \brief (TAL_SFLAG) Inter-Process Signal 23 */
+#define TAL_SFLAG_IPS23 (_U_(1) << TAL_SFLAG_IPS23_Pos)
+#define TAL_SFLAG_IPS24_Pos 24 /**< \brief (TAL_SFLAG) Inter-Process Signal 24 */
+#define TAL_SFLAG_IPS24 (_U_(1) << TAL_SFLAG_IPS24_Pos)
+#define TAL_SFLAG_IPS25_Pos 25 /**< \brief (TAL_SFLAG) Inter-Process Signal 25 */
+#define TAL_SFLAG_IPS25 (_U_(1) << TAL_SFLAG_IPS25_Pos)
+#define TAL_SFLAG_IPS26_Pos 26 /**< \brief (TAL_SFLAG) Inter-Process Signal 26 */
+#define TAL_SFLAG_IPS26 (_U_(1) << TAL_SFLAG_IPS26_Pos)
+#define TAL_SFLAG_IPS27_Pos 27 /**< \brief (TAL_SFLAG) Inter-Process Signal 27 */
+#define TAL_SFLAG_IPS27 (_U_(1) << TAL_SFLAG_IPS27_Pos)
+#define TAL_SFLAG_IPS28_Pos 28 /**< \brief (TAL_SFLAG) Inter-Process Signal 28 */
+#define TAL_SFLAG_IPS28 (_U_(1) << TAL_SFLAG_IPS28_Pos)
+#define TAL_SFLAG_IPS29_Pos 29 /**< \brief (TAL_SFLAG) Inter-Process Signal 29 */
+#define TAL_SFLAG_IPS29 (_U_(1) << TAL_SFLAG_IPS29_Pos)
+#define TAL_SFLAG_IPS30_Pos 30 /**< \brief (TAL_SFLAG) Inter-Process Signal 30 */
+#define TAL_SFLAG_IPS30 (_U_(1) << TAL_SFLAG_IPS30_Pos)
+#define TAL_SFLAG_IPS31_Pos 31 /**< \brief (TAL_SFLAG) Inter-Process Signal 31 */
+#define TAL_SFLAG_IPS31 (_U_(1) << TAL_SFLAG_IPS31_Pos)
+#define TAL_SFLAG_IPS_Pos 0 /**< \brief (TAL_SFLAG) Inter-Process Signal x */
+#define TAL_SFLAG_IPS_Msk (_U_(0xFFFFFFFF) << TAL_SFLAG_IPS_Pos)
+#define TAL_SFLAG_IPS(value) (TAL_SFLAG_IPS_Msk & ((value) << TAL_SFLAG_IPS_Pos))
+#define TAL_SFLAG_MASK _U_(0xFFFFFFFF) /**< \brief (TAL_SFLAG) MASK Register */
+
+/* -------- TAL_SFLAGCLRR : (TAL Offset: 0x300) (R/W 8) Inter-Process Signal Flag Bit n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t IPS:1; /*!< bit: 0 Inter-Process Signal n */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TAL_SFLAGCLRR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TAL_SFLAGCLRR_OFFSET 0x300 /**< \brief (TAL_SFLAGCLRR offset) Inter-Process Signal Flag Bit n */
+#define TAL_SFLAGCLRR_RESETVALUE _U_(0x00) /**< \brief (TAL_SFLAGCLRR reset_value) Inter-Process Signal Flag Bit n */
+
+#define TAL_SFLAGCLRR_IPS_Pos 0 /**< \brief (TAL_SFLAGCLRR) Inter-Process Signal n */
+#define TAL_SFLAGCLRR_IPS (_U_(0x1) << TAL_SFLAGCLRR_IPS_Pos)
+#define TAL_SFLAGCLRR_MASK _U_(0x01) /**< \brief (TAL_SFLAGCLRR) MASK Register */
+
+/** \brief TalCpuirqs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __I TAL_CPUIRQS_Type CPUIRQS[5]; /**< \brief Offset: 0x000 (R/ 32) Interrupt Status m for CPU n */
+ RoReg8 Reserved1[0xC];
+} TalCpuirqs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TalCtis hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TAL_CTICTRLA_Type CTICTRLA; /**< \brief Offset: 0x000 (R/W 8) Cross-Trigger Interface n Control A */
+ __IO TAL_CTIMASK_Type CTIMASK; /**< \brief Offset: 0x001 (R/W 8) Cross-Trigger Interface n Mask */
+} TalCtis;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TalSmasks hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TAL_SMASK_Type SMASK[2]; /**< \brief Offset: 0x000 (R/W 32) Inter-Process Signal Mask m for CPU n */
+} TalSmasks;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TAL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TAL_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ __IO TAL_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x001 (R/W 8) External Break Control */
+ RoReg8 Reserved1[0x2];
+ __IO TAL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x004 (R/W 16) Event Control */
+ RoReg8 Reserved2[0x2];
+ __IO TAL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x008 (R/W 8) Interrupt Enable Clear */
+ __IO TAL_INTENSET_Type INTENSET; /**< \brief Offset: 0x009 (R/W 8) Interrupt Enable Set */
+ __IO TAL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x00A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TAL_GLOBMASK_Type GLOBMASK; /**< \brief Offset: 0x00B (R/W 8) Global Break Requests Mask */
+ __O TAL_HALT_Type HALT; /**< \brief Offset: 0x00C ( /W 8) Debug Halt Request */
+ __O TAL_RESTART_Type RESTART; /**< \brief Offset: 0x00D ( /W 8) Debug Restart Request */
+ __I TAL_BRKSTATUS_Type BRKSTATUS; /**< \brief Offset: 0x00E (R/ 16) Break Request Status */
+ TalCtis Ctis[4]; /**< \brief Offset: 0x010 TalCtis groups [CTI_NUM] */
+ RoReg8 Reserved3[0x8];
+ __I TAL_INTSTATUS_Type INTSTATUS[137]; /**< \brief Offset: 0x020 (R/ 8) Interrupt n Status */
+ RoReg8 Reserved4[0x67];
+ __IO TAL_DMACPUSEL0_Type DMACPUSEL0; /**< \brief Offset: 0x110 (R/W 32) DMA Channel Interrupts CPU Select 0 */
+ __IO TAL_DMACPUSEL1_Type DMACPUSEL1; /**< \brief Offset: 0x114 (R/W 32) DMA Channel Interrupts CPU Select 1 */
+ __IO TAL_EVCPUSEL0_Type EVCPUSEL0; /**< \brief Offset: 0x118 (R/W 32) EVSYS Channel Interrupts CPU Select 0 */
+ RoReg8 Reserved5[0x4];
+ __IO TAL_EICCPUSEL0_Type EICCPUSEL0; /**< \brief Offset: 0x120 (R/W 32) EIC External Interrupts CPU Select 0 */
+ RoReg8 Reserved6[0x4];
+ __IO TAL_INTCPUSEL0_Type INTCPUSEL0; /**< \brief Offset: 0x128 (R/W 32) Interrupts CPU Select 0 */
+ __IO TAL_INTCPUSEL1_Type INTCPUSEL1; /**< \brief Offset: 0x12C (R/W 32) Interrupts CPU Select 1 */
+ __IO TAL_INTCPUSEL2_Type INTCPUSEL2; /**< \brief Offset: 0x130 (R/W 32) Interrupts CPU Select 2 */
+ __IO TAL_INTCPUSEL3_Type INTCPUSEL3; /**< \brief Offset: 0x134 (R/W 32) Interrupts CPU Select 3 */
+ __IO TAL_INTCPUSEL4_Type INTCPUSEL4; /**< \brief Offset: 0x138 (R/W 32) Interrupts CPU Select 4 */
+ __IO TAL_INTCPUSEL5_Type INTCPUSEL5; /**< \brief Offset: 0x13C (R/W 32) Interrupts CPU Select 5 */
+ __IO TAL_INTCPUSEL6_Type INTCPUSEL6; /**< \brief Offset: 0x140 (R/W 32) Interrupts CPU Select 6 */
+ __IO TAL_INTCPUSEL7_Type INTCPUSEL7; /**< \brief Offset: 0x144 (R/W 32) Interrupts CPU Select 7 */
+ __IO TAL_INTCPUSEL8_Type INTCPUSEL8; /**< \brief Offset: 0x148 (R/W 32) Interrupts CPU Select 8 */
+ RoReg8 Reserved7[0x18];
+ __IO TAL_IRQTRIG_Type IRQTRIG; /**< \brief Offset: 0x164 (R/W 32) Interrupt Trigger */
+ __IO TAL_IRQMON_Type IRQMON[1]; /**< \brief Offset: 0x168 (R/W 16) Interrupt Monitor Select */
+ RoReg8 Reserved8[0x16];
+ TalCpuirqs Cpuirqs[2]; /**< \brief Offset: 0x180 TalCpuirqs groups [CPU_NUM] */
+ RoReg8 Reserved9[0x40];
+ TalSmasks Smasks[2]; /**< \brief Offset: 0x200 TalSmasks groups [CPU_NUM] */
+ RoReg8 Reserved10[0x10];
+ __O TAL_SFLAGCLR_Type SFLAGCLR[2]; /**< \brief Offset: 0x220 ( /W 32) Inter-Process Signal Flag Clear */
+ __O TAL_SFLAGSET_Type SFLAGSET[2]; /**< \brief Offset: 0x228 ( /W 32) Inter-Process Signal Flag Set */
+ __I TAL_SFLAG_Type SFLAG[2]; /**< \brief Offset: 0x230 (R/ 32) Inter-Process Signal Flag */
+ RoReg8 Reserved11[0xC8];
+ __IO TAL_SFLAGCLRR_Type SFLAGCLRR[64]; /**< \brief Offset: 0x300 (R/W 8) Inter-Process Signal Flag Bit n */
+} Tal;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TAL_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/tc.h b/GPIO/ATSAME54/include/component/tc.h
new file mode 100644
index 0000000..9a56142
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/tc.h
@@ -0,0 +1,851 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC_COMPONENT_
+#define _SAME54_TC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAME54_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2249
+#define REV_TC 0x300
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */
+ uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */
+ uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */
+ uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t CAPTMODE0:2; /*!< bit: 24..25 Capture Mode Channel 0 */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t CAPTMODE1:2; /*!< bit: 27..28 Capture mode Channel 1 */
+ uint32_t :3; /*!< bit: 29..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */
+#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */
+#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */
+#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
+#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */
+#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
+#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
+#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
+#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
+#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
+#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */
+#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
+#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
+#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
+#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
+#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
+#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
+#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */
+#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
+#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
+#define TC_CTRLA_CAPTMODE0_Pos 24 /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
+#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
+#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
+#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
+#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
+#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE1_Pos 27 /**< \brief (TC_CTRLA) Capture mode Channel 1 */
+#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
+#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
+#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
+#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
+#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_MASK _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
+ uint8_t :2; /*!< bit: 3.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */
+#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
+#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */
+#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
+#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
+#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
+#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
+ uint8_t :2; /*!< bit: 3.. 4 Reserved */
+ uint8_t CMD:3; /*!< bit: 5.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */
+#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */
+#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */
+#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
+#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
+#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
+#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */
+ uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */
+#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */
+#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */
+#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */
+#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
+#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */
+#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */
+#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */
+#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */
+#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
+#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
+#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */
+#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */
+ uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
+#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
+#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
+#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
+#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
+#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */
+ uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */
+#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */
+#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
+#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
+#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */
+#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
+ __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
+ __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
+#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
+#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
+#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
+#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
+#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */
+ uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */
+ uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */
+ uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */
+#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */
+#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */
+#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
+#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
+#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
+#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
+#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
+#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */
+#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
+#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
+#define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */
+#define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
+
+#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */
+#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
+#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */
+#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */
+#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */
+#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */
+#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */
+
+/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */
+#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */
+
+#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
+#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
+#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
+#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
+#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
+#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
+#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
+#define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */
+#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 swrst */
+ uint32_t ENABLE:1; /*!< bit: 1 enable */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB */
+ uint32_t STATUS:1; /*!< bit: 3 STATUS */
+ uint32_t COUNT:1; /*!< bit: 4 Counter */
+ uint32_t PER:1; /*!< bit: 5 Period */
+ uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */
+ uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
+#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
+
+#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */
+#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
+#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */
+#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
+#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */
+#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
+#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */
+#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
+#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */
+#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
+#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */
+#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
+#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
+#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
+#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
+#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
+#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */
+#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
+#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
+#define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
+#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
+
+#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */
+#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
+#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
+
+#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */
+#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
+#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
+
+#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
+#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
+
+#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
+#define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
+
+#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
+#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
+#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
+
+#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
+#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
+#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
+
+#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
+#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
+#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
+
+#define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
+#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
+#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
+#define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */
+
+/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
+#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
+
+#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
+#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
+#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */
+
+/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
+#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
+
+#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
+#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
+#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
+
+/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
+#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
+
+#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
+#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
+#define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
+ __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
+ __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */
+ RoReg8 Reserved2[0x6];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
+ RoReg8 Reserved3[0x11];
+ __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
+ __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
+ __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
+ __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
+ RoReg8 Reserved2[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
+ RoReg8 Reserved3[0x10];
+ __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
+ __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
+ __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
+ __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
+ RoReg8 Reserved2[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
+ RoReg8 Reserved3[0xC];
+ __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/tcc.h b/GPIO/ATSAME54/include/component/tcc.h
new file mode 100644
index 0000000..c97ba8b
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/tcc.h
@@ -0,0 +1,1762 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC_COMPONENT_
+#define _SAME54_TCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAME54_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC 0x310
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */
+ uint32_t :7; /*!< bit: 16..22 Reserved */
+ uint32_t DMAOS:1; /*!< bit: 23 DMA One-shot Trigger Mode */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t CPTEN4:1; /*!< bit: 28 Capture Channel 4 Enable */
+ uint32_t CPTEN5:1; /*!< bit: 29 Capture Channel 5 Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:6; /*!< bit: 24..29 Capture Channel x Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1) /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2) /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3) /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TCC_CTRLA) No division */
+#define TCC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TCC_CTRLA) Divide by 2 */
+#define TCC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TCC_CTRLA) Divide by 4 */
+#define TCC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TCC_CTRLA) Divide by 8 */
+#define TCC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TCC_CTRLA) Divide by 16 */
+#define TCC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TCC_CTRLA) Divide by 64 */
+#define TCC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TCC_CTRLA) Divide by 256 */
+#define TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define TCC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define TCC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define TCC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK (_U_(0x1) << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_MSYNC_Pos 15 /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */
+#define TCC_CTRLA_MSYNC (_U_(0x1) << TCC_CTRLA_MSYNC_Pos)
+#define TCC_CTRLA_DMAOS_Pos 23 /**< \brief (TCC_CTRLA) DMA One-shot Trigger Mode */
+#define TCC_CTRLA_DMAOS (_U_(0x1) << TCC_CTRLA_DMAOS_Pos)
+#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0 (_U_(1) << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1 (_U_(1) << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2 (_U_(1) << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3 (_U_(1) << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN4_Pos 28 /**< \brief (TCC_CTRLA) Capture Channel 4 Enable */
+#define TCC_CTRLA_CPTEN4 (_U_(1) << TCC_CTRLA_CPTEN4_Pos)
+#define TCC_CTRLA_CPTEN5_Pos 29 /**< \brief (TCC_CTRLA) Capture Channel 5 Enable */
+#define TCC_CTRLA_CPTEN5 (_U_(1) << TCC_CTRLA_CPTEN5_Pos)
+#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK _U_(0x3F80FF63) /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBCLR_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define TCC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) No action */
+#define TCC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define TCC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Force stop */
+#define TCC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */
+#define TCC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBCLR) One-shot DMA trigger */
+#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_DMAOS (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK _U_(0xFF) /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR (_U_(0x1) << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBSET_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk (_U_(0x7) << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define TCC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) No action */
+#define TCC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define TCC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Force stop */
+#define TCC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */
+#define TCC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBSET) One-shot DMA trigger */
+#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_DMAOS (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK _U_(0xFF) /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period Busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t CC4:1; /*!< bit: 12 Compare Channel 4 Busy */
+ uint32_t CC5:1; /*!< bit: 13 Compare Channel 5 Busy */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:6; /*!< bit: 8..13 Compare Channel x Busy */
+ uint32_t :18; /*!< bit: 14..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period Busy */
+#define TCC_SYNCBUSY_PER (_U_(0x1) << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0 (_U_(1) << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1 (_U_(1) << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2 (_U_(1) << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3 (_U_(1) << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC4_Pos 12 /**< \brief (TCC_SYNCBUSY) Compare Channel 4 Busy */
+#define TCC_SYNCBUSY_CC4 (_U_(1) << TCC_SYNCBUSY_CC4_Pos)
+#define TCC_SYNCBUSY_CC5_Pos 13 /**< \brief (TCC_SYNCBUSY) Compare Channel 5 Busy */
+#define TCC_SYNCBUSY_CC5 (_U_(1) << TCC_SYNCBUSY_CC5_Pos)
+#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_MASK _U_(0x00003FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk (_U_(0x3) << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define TCC_FCTRLA_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define TCC_FCTRLA_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP (_U_(0x1) << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL (_U_(0x1) << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk (_U_(0x3) << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define TCC_FCTRLA_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */
+#define TCC_FCTRLA_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLA_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLA_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART (_U_(0x1) << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk (_U_(0x3) << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define TCC_FCTRLA_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define TCC_FCTRLA_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define TCC_FCTRLA_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Software halt action */
+#define TCC_FCTRLA_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define TCC_FCTRLA_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define TCC_FCTRLA_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define TCC_FCTRLA_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define TCC_FCTRLA_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define TCC_FCTRLA_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) No capture */
+#define TCC_FCTRLA_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture on fault */
+#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Minimum capture */
+#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Maximum capture */
+#define TCC_FCTRLA_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define TCC_FCTRLA_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */
+#define TCC_FCTRLA_BLANKPRESC (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk (_U_(0x3) << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define TCC_FCTRLB_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define TCC_FCTRLB_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP (_U_(0x1) << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL (_U_(0x1) << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk (_U_(0x3) << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define TCC_FCTRLB_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */
+#define TCC_FCTRLB_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLB_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLB_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART (_U_(0x1) << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk (_U_(0x3) << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define TCC_FCTRLB_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define TCC_FCTRLB_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define TCC_FCTRLB_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Software halt action */
+#define TCC_FCTRLB_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define TCC_FCTRLB_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define TCC_FCTRLB_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define TCC_FCTRLB_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define TCC_FCTRLB_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define TCC_FCTRLB_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) No capture */
+#define TCC_FCTRLB_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture on fault */
+#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Minimum capture */
+#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Maximum capture */
+#define TCC_FCTRLB_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define TCC_FCTRLB_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */
+#define TCC_FCTRLB_BLANKPRESC (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0 (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1 (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2 (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3 (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0 (_U_(1) << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1 (_U_(1) << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2 (_U_(1) << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3 (_U_(1) << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4 (_U_(1) << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5 (_U_(1) << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6 (_U_(1) << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7 (_U_(1) << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0 (_U_(1) << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1 (_U_(1) << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2 (_U_(1) << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3 (_U_(1) << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4 (_U_(1) << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5 (_U_(1) << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6 (_U_(1) << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7 (_U_(1) << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0 (_U_(1) << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1 (_U_(1) << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2 (_U_(1) << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3 (_U_(1) << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4 (_U_(1) << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5 (_U_(1) << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6 (_U_(1) << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7 (_U_(1) << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK _U_(0x05) /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t MCEI4:1; /*!< bit: 20 Match or Capture Channel 4 Event Input Enable */
+ uint32_t MCEI5:1; /*!< bit: 21 Match or Capture Channel 5 Event Input Enable */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t MCEO4:1; /*!< bit: 28 Match or Capture Channel 4 Event Output Enable */
+ uint32_t MCEO5:1; /*!< bit: 29 Match or Capture Channel 5 Event Output Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:6; /*!< bit: 16..21 Match or Capture Channel x Event Input Enable */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t MCEO:6; /*!< bit: 24..29 Match or Capture Channel x Event Output Enable */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define TCC_EVCTRL_EVACT0_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define TCC_EVCTRL_EVACT0_COUNTEV_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Count on event */
+#define TCC_EVCTRL_EVACT0_START_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Start counter on event */
+#define TCC_EVCTRL_EVACT0_INC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define TCC_EVCTRL_EVACT0_COUNT_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define TCC_EVCTRL_EVACT0_STAMP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Stamp capture */
+#define TCC_EVCTRL_EVACT0_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define TCC_EVCTRL_EVACT1_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define TCC_EVCTRL_EVACT1_DIR_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Direction control */
+#define TCC_EVCTRL_EVACT1_STOP_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define TCC_EVCTRL_EVACT1_DEC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define TCC_EVCTRL_EVACT1_PPW_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define TCC_EVCTRL_EVACT1_PWP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define TCC_EVCTRL_EVACT1_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define TCC_EVCTRL_CNTSEL_START_Val _U_(0x0) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define TCC_EVCTRL_CNTSEL_END_Val _U_(0x1) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_BETWEEN_Val _U_(0x2) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val _U_(0x3) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0 (_U_(1) << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1 (_U_(1) << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk (_U_(0x3) << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0 (_U_(1) << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1 (_U_(1) << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk (_U_(0x3) << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0 (_U_(1) << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1 (_U_(1) << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2 (_U_(1) << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3 (_U_(1) << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI4_Pos 20 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable */
+#define TCC_EVCTRL_MCEI4 (_U_(1) << TCC_EVCTRL_MCEI4_Pos)
+#define TCC_EVCTRL_MCEI5_Pos 21 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable */
+#define TCC_EVCTRL_MCEI5 (_U_(1) << TCC_EVCTRL_MCEI5_Pos)
+#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0 (_U_(1) << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1 (_U_(1) << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2 (_U_(1) << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3 (_U_(1) << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO4_Pos 28 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable */
+#define TCC_EVCTRL_MCEO4 (_U_(1) << TCC_EVCTRL_MCEO4_Pos)
+#define TCC_EVCTRL_MCEO5_Pos 29 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable */
+#define TCC_EVCTRL_MCEO5 (_U_(1) << TCC_EVCTRL_MCEO5_Pos)
+#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK _U_(0x3F3FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */
+ uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF (_U_(0x1) << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG (_U_(0x1) << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT (_U_(0x1) << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR (_U_(0x1) << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS (_U_(0x1) << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS (_U_(0x1) << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0 (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1 (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0 (_U_(1) << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1 (_U_(1) << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2 (_U_(1) << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3 (_U_(1) << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC4_Pos 20 /**< \brief (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable */
+#define TCC_INTENCLR_MC4 (_U_(1) << TCC_INTENCLR_MC4_Pos)
+#define TCC_INTENCLR_MC5_Pos 21 /**< \brief (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable */
+#define TCC_INTENCLR_MC5 (_U_(1) << TCC_INTENCLR_MC5_Pos)
+#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk (_U_(0x3F) << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */
+ uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF (_U_(0x1) << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG (_U_(0x1) << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT (_U_(0x1) << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR (_U_(0x1) << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS (_U_(0x1) << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS (_U_(0x1) << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA (_U_(0x1) << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB (_U_(0x1) << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0 (_U_(0x1) << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1 (_U_(0x1) << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0 (_U_(1) << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1 (_U_(1) << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2 (_U_(1) << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3 (_U_(1) << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC4_Pos 20 /**< \brief (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable */
+#define TCC_INTENSET_MC4 (_U_(1) << TCC_INTENSET_MC4_Pos)
+#define TCC_INTENSET_MC5_Pos 21 /**< \brief (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable */
+#define TCC_INTENSET_MC5 (_U_(1) << TCC_INTENSET_MC5_Pos)
+#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk (_U_(0x3F) << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ __I uint32_t CNT:1; /*!< bit: 2 Counter */
+ __I uint32_t ERR:1; /*!< bit: 3 Error */
+ __I uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
+ __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ __I uint32_t MC4:1; /*!< bit: 20 Match or Capture 4 */
+ __I uint32_t MC5:1; /*!< bit: 21 Match or Capture 5 */
+ __I uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t :16; /*!< bit: 0..15 Reserved */
+ __I uint32_t MC:6; /*!< bit: 16..21 Match or Capture x */
+ __I uint32_t :10; /*!< bit: 22..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF (_U_(0x1) << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG (_U_(0x1) << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT (_U_(0x1) << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR (_U_(0x1) << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS (_U_(0x1) << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS (_U_(0x1) << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0 (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1 (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0 (_U_(1) << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1 (_U_(1) << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2 (_U_(1) << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3 (_U_(1) << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC4_Pos 20 /**< \brief (TCC_INTFLAG) Match or Capture 4 */
+#define TCC_INTFLAG_MC4 (_U_(1) << TCC_INTFLAG_MC4_Pos)
+#define TCC_INTFLAG_MC5_Pos 21 /**< \brief (TCC_INTFLAG) Match or Capture 5 */
+#define TCC_INTFLAG_MC5 (_U_(1) << TCC_INTFLAG_MC5_Pos)
+#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk (_U_(0x3F) << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t CCBUFV4:1; /*!< bit: 20 Compare Channel 4 Buffer Valid */
+ uint32_t CCBUFV5:1; /*!< bit: 21 Compare Channel 5 Buffer Valid */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t CMP4:1; /*!< bit: 28 Compare Channel 4 Value */
+ uint32_t CMP5:1; /*!< bit: 29 Compare Channel 5 Value */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBUFV:6; /*!< bit: 16..21 Compare Channel x Buffer Valid */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t CMP:6; /*!< bit: 24..29 Compare Channel x Value */
+ uint32_t :2; /*!< bit: 30..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP (_U_(0x1) << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX (_U_(0x1) << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */
+#define TCC_STATUS_UFS (_U_(0x1) << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS (_U_(0x1) << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE (_U_(0x1) << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBUFV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBUFV (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos)
+#define TCC_STATUS_PERBUFV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBUFV (_U_(0x1) << TCC_STATUS_PERBUFV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA (_U_(0x1) << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB (_U_(0x1) << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0 (_U_(0x1) << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1 (_U_(0x1) << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBUFV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBUFV0 (_U_(1) << TCC_STATUS_CCBUFV0_Pos)
+#define TCC_STATUS_CCBUFV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBUFV1 (_U_(1) << TCC_STATUS_CCBUFV1_Pos)
+#define TCC_STATUS_CCBUFV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBUFV2 (_U_(1) << TCC_STATUS_CCBUFV2_Pos)
+#define TCC_STATUS_CCBUFV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBUFV3 (_U_(1) << TCC_STATUS_CCBUFV3_Pos)
+#define TCC_STATUS_CCBUFV4_Pos 20 /**< \brief (TCC_STATUS) Compare Channel 4 Buffer Valid */
+#define TCC_STATUS_CCBUFV4 (_U_(1) << TCC_STATUS_CCBUFV4_Pos)
+#define TCC_STATUS_CCBUFV5_Pos 21 /**< \brief (TCC_STATUS) Compare Channel 5 Buffer Valid */
+#define TCC_STATUS_CCBUFV5 (_U_(1) << TCC_STATUS_CCBUFV5_Pos)
+#define TCC_STATUS_CCBUFV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBUFV_Msk (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos)
+#define TCC_STATUS_CCBUFV(value) (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))
+#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0 (_U_(1) << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1 (_U_(1) << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2 (_U_(1) << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3 (_U_(1) << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP4_Pos 28 /**< \brief (TCC_STATUS) Compare Channel 4 Value */
+#define TCC_STATUS_CMP4 (_U_(1) << TCC_STATUS_CMP4_Pos)
+#define TCC_STATUS_CMP5_Pos 29 /**< \brief (TCC_STATUS) Compare Channel 5 Value */
+#define TCC_STATUS_CMP5 (_U_(1) << TCC_STATUS_CMP5_Pos)
+#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk (_U_(0x3F) << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK _U_(0x3F3FFFBF) /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0 (_U_(1) << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1 (_U_(1) << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2 (_U_(1) << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3 (_U_(1) << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4 (_U_(1) << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5 (_U_(1) << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6 (_U_(1) << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7 (_U_(1) << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk (_U_(0xFF) << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0 (_U_(1) << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1 (_U_(1) << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2 (_U_(1) << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3 (_U_(1) << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4 (_U_(1) << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5 (_U_(1) << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6 (_U_(1) << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7 (_U_(1) << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk (_U_(0xFF) << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK _U_(0xFFFF) /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t POL4:1; /*!< bit: 20 Channel 4 Polarity */
+ uint32_t POL5:1; /*!< bit: 21 Channel 5 Polarity */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:6; /*!< bit: 16..21 Channel x Polarity */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define TCC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TCC_WAVE) Normal frequency */
+#define TCC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TCC_WAVE) Match frequency */
+#define TCC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TCC_WAVE) Normal PWM */
+#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4) /**< \brief (TCC_WAVE) Dual-slope critical */
+#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val _U_(0x5) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define TCC_WAVE_WAVEGEN_DSBOTH_Val _U_(0x6) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define TCC_WAVE_WAVEGEN_DSTOP_Val _U_(0x7) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk (_U_(0x3) << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define TCC_WAVE_RAMP_RAMP1_Val _U_(0x0) /**< \brief (TCC_WAVE) RAMP1 operation */
+#define TCC_WAVE_RAMP_RAMP2A_Val _U_(0x1) /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP2_Val _U_(0x2) /**< \brief (TCC_WAVE) RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP2C_Val _U_(0x3) /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN (_U_(0x1) << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0 (_U_(1) << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1 (_U_(1) << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2 (_U_(1) << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3 (_U_(1) << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk (_U_(0xF) << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0 (_U_(1) << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1 (_U_(1) << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2 (_U_(1) << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3 (_U_(1) << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL4_Pos 20 /**< \brief (TCC_WAVE) Channel 4 Polarity */
+#define TCC_WAVE_POL4 (_U_(1) << TCC_WAVE_POL4_Pos)
+#define TCC_WAVE_POL5_Pos 21 /**< \brief (TCC_WAVE) Channel 5 Polarity */
+#define TCC_WAVE_POL5 (_U_(1) << TCC_WAVE_POL5_Pos)
+#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk (_U_(0x3F) << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0 (_U_(1) << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1 (_U_(1) << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2 (_U_(1) << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3 (_U_(1) << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk (_U_(0xF) << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK _U_(0x0F3F0FB7) /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHER_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHER_Msk (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos)
+#define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))
+#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHER_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHER_Msk (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos)
+#define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))
+#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHER_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHER_Msk (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos)
+#define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))
+#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk (_U_(0xFFFFFF) << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHER_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHER_Msk (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos)
+#define TCC_CC_DITH4_DITHER(value) (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))
+#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHER_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHER_Msk (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos)
+#define TCC_CC_DITH5_DITHER(value) (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))
+#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHER_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHER_Msk (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos)
+#define TCC_CC_DITH6_DITHER(value) (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))
+#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk (_U_(0xFFFFFF) << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATTBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTBUF_OFFSET 0x64 /**< \brief (TCC_PATTBUF offset) Pattern Buffer */
+#define TCC_PATTBUF_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */
+
+#define TCC_PATTBUF_PGEB0_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB0 (_U_(1) << TCC_PATTBUF_PGEB0_Pos)
+#define TCC_PATTBUF_PGEB1_Pos 1 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB1 (_U_(1) << TCC_PATTBUF_PGEB1_Pos)
+#define TCC_PATTBUF_PGEB2_Pos 2 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB2 (_U_(1) << TCC_PATTBUF_PGEB2_Pos)
+#define TCC_PATTBUF_PGEB3_Pos 3 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB3 (_U_(1) << TCC_PATTBUF_PGEB3_Pos)
+#define TCC_PATTBUF_PGEB4_Pos 4 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB4 (_U_(1) << TCC_PATTBUF_PGEB4_Pos)
+#define TCC_PATTBUF_PGEB5_Pos 5 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB5 (_U_(1) << TCC_PATTBUF_PGEB5_Pos)
+#define TCC_PATTBUF_PGEB6_Pos 6 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB6 (_U_(1) << TCC_PATTBUF_PGEB6_Pos)
+#define TCC_PATTBUF_PGEB7_Pos 7 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB7 (_U_(1) << TCC_PATTBUF_PGEB7_Pos)
+#define TCC_PATTBUF_PGEB_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTBUF_PGEB_Msk (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos)
+#define TCC_PATTBUF_PGEB(value) (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))
+#define TCC_PATTBUF_PGVB0_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */
+#define TCC_PATTBUF_PGVB0 (_U_(1) << TCC_PATTBUF_PGVB0_Pos)
+#define TCC_PATTBUF_PGVB1_Pos 9 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */
+#define TCC_PATTBUF_PGVB1 (_U_(1) << TCC_PATTBUF_PGVB1_Pos)
+#define TCC_PATTBUF_PGVB2_Pos 10 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */
+#define TCC_PATTBUF_PGVB2 (_U_(1) << TCC_PATTBUF_PGVB2_Pos)
+#define TCC_PATTBUF_PGVB3_Pos 11 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */
+#define TCC_PATTBUF_PGVB3 (_U_(1) << TCC_PATTBUF_PGVB3_Pos)
+#define TCC_PATTBUF_PGVB4_Pos 12 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */
+#define TCC_PATTBUF_PGVB4 (_U_(1) << TCC_PATTBUF_PGVB4_Pos)
+#define TCC_PATTBUF_PGVB5_Pos 13 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */
+#define TCC_PATTBUF_PGVB5 (_U_(1) << TCC_PATTBUF_PGVB5_Pos)
+#define TCC_PATTBUF_PGVB6_Pos 14 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */
+#define TCC_PATTBUF_PGVB6 (_U_(1) << TCC_PATTBUF_PGVB6_Pos)
+#define TCC_PATTBUF_PGVB7_Pos 15 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */
+#define TCC_PATTBUF_PGVB7 (_U_(1) << TCC_PATTBUF_PGVB7_Pos)
+#define TCC_PATTBUF_PGVB_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */
+#define TCC_PATTBUF_PGVB_Msk (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos)
+#define TCC_PATTBUF_PGVB(value) (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))
+#define TCC_PATTBUF_MASK _U_(0xFFFF) /**< \brief (TCC_PATTBUF) MASK Register */
+
+/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERBUF_OFFSET 0x6C /**< \brief (TCC_PERBUF offset) Period Buffer */
+#define TCC_PERBUF_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PERBUF reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH4_PERBUF_Pos 4 /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */
+#define TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)
+#define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))
+#define TCC_PERBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH5_PERBUF_Pos 5 /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */
+#define TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos)
+#define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))
+#define TCC_PERBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH6_PERBUF_Pos 6 /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */
+#define TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos)
+#define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))
+#define TCC_PERBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH6) MASK Register */
+
+#define TCC_PERBUF_PERBUF_Pos 0 /**< \brief (TCC_PERBUF) Period Buffer Value */
+#define TCC_PERBUF_PERBUF_Msk (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos)
+#define TCC_PERBUF_PERBUF(value) (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))
+#define TCC_PERBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF) MASK Register */
+
+/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */
+ uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCBUF_OFFSET 0x70 /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */
+#define TCC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCBUF_DITH4_CCBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH4_CCBUF_Msk (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos)
+#define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))
+#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4 /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH5_CCBUF_Pos 5 /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH5_CCBUF_Msk (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos)
+#define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))
+#define TCC_CCBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH6_CCBUF_Pos 6 /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH6_CCBUF_Msk (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos)
+#define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))
+#define TCC_CCBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH6) MASK Register */
+
+#define TCC_CCBUF_CCBUF_Pos 0 /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_CCBUF_Msk (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos)
+#define TCC_CCBUF_CCBUF(value) (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))
+#define TCC_CCBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[6]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x8];
+ __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x6];
+ __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCBUF_Type CCBUF[6]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TCC_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/trng.h b/GPIO/ATSAME54/include/component/trng.h
new file mode 100644
index 0000000..cf7f36b
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/trng.h
@@ -0,0 +1,172 @@
+/**
+ * \file
+ *
+ * \brief Component description for TRNG
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TRNG_COMPONENT_
+#define _SAME54_TRNG_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TRNG */
+/* ========================================================================== */
+/** \addtogroup SAME54_TRNG True Random Generator */
+/*@{*/
+
+#define TRNG_U2242
+#define REV_TRNG 0x110
+
+/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */
+#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */
+
+#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */
+#define TRNG_CTRLA_ENABLE (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
+#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */
+#define TRNG_CTRLA_RUNSTDBY (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
+#define TRNG_CTRLA_MASK _U_(0x42) /**< \brief (TRNG_CTRLA) MASK Register */
+
+/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */
+#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */
+
+#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
+#define TRNG_EVCTRL_DATARDYEO (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
+#define TRNG_EVCTRL_MASK _U_(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */
+
+/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
+#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
+#define TRNG_INTENCLR_DATARDY (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
+#define TRNG_INTENCLR_MASK _U_(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */
+
+/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
+#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
+
+#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
+#define TRNG_INTENSET_DATARDY (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
+#define TRNG_INTENSET_MASK _U_(0x01) /**< \brief (TRNG_INTENSET) MASK Register */
+
+/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TRNG_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
+#define TRNG_INTFLAG_DATARDY (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
+#define TRNG_INTFLAG_MASK _U_(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */
+
+/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Output Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TRNG_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */
+#define TRNG_DATA_RESETVALUE _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
+
+#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */
+#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
+#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
+#define TRNG_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
+
+/** \brief TRNG hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
+ RoReg8 Reserved2[0x3];
+ __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
+ __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
+ __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved3[0x15];
+ __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
+} Trng;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_TRNG_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/usb.h b/GPIO/ATSAME54/include/component/usb.h
new file mode 100644
index 0000000..dfdf11c
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/usb.h
@@ -0,0 +1,1777 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_USB_COMPONENT_
+#define _SAME54_USB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAME54_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB 0x120
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE _U_(0x00) /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST (_U_(0x1) << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE (_U_(0x1) << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_DEVICE_Val _U_(0x0) /**< \brief (USB_CTRLA) Device Mode */
+#define USB_CTRLA_MODE_HOST_Val _U_(0x1) /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK _U_(0x87) /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK _U_(0x03) /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE _U_(0x0F) /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define USB_QOSCTRL_MASK _U_(0x0F) /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001) /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2 (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK _U_(0x0FFF) /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0) /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define USB_HOST_CTRLB_SPDCONF_FS_Val _U_(0x3) /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */
+#define USB_HOST_CTRLB_AUTORESUME (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK _U_(0x0F7E) /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK _U_(0xFF) /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK _U_(0x8F) /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE _U_(0x40) /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define USB_DEVICE_STATUS_SPEED_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define USB_DEVICE_STATUS_SPEED_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK _U_(0xCC) /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK _U_(0xCC) /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE _U_(0x01) /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define USB_FSMSTATUS_FSMSTATE_OFF_Val _U_(0x1) /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define USB_FSMSTATUS_FSMSTATE_ON_Val _U_(0x2) /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4) /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8) /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10) /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20) /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40) /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK _U_(0x7F) /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK _U_(0xBFFF) /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK _U_(0x3FFF) /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK _U_(0xFF) /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0 (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1 (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2 (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3 (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4 (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5 (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6 (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7 (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE _U_(0x0000) /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk (_U_(0x7) << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK _U_(0x77DF) /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK _U_(0x3F) /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK _U_(0xFF) /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ __I uint8_t :1; /*!< bit: 4 Reserved */
+ __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0 (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1 (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0 (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1 (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0 (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1 (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK _U_(0xFF7F) /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK _U_(0x00FF) /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_USB_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/component/wdt.h b/GPIO/ATSAME54/include/component/wdt.h
new file mode 100644
index 0000000..b14e7ad
--- /dev/null
+++ b/GPIO/ATSAME54/include/component/wdt.h
@@ -0,0 +1,300 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_WDT_COMPONENT_
+#define _SAME54_WDT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAME54_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2251
+#define REV_WDT 0x110
+
+/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */
+#define WDT_CTRLA_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRLA reset_value) Control */
+
+#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */
+#define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
+#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
+#define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
+#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */
+#define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
+#define WDT_CTRLA_MASK _U_(0x86) /**< \brief (WDT_CTRLA) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t EW:1; /*!< bit: 0 Early Warning */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint32_t WEN:1; /*!< bit: 2 Window Enable Synchronization Busy */
+ uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Synchronization Busy */
+ uint32_t CLEAR:1; /*!< bit: 4 Clear Synchronization Busy */
+ uint32_t :27; /*!< bit: 5..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} WDT_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
+#define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
+
+#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
+#define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
+#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
+#define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
+#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
+#define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
+#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
+#define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
+#define WDT_SYNCBUSY_MASK _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved2[0x1];
+ __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME54_WDT_COMPONENT_ */
diff --git a/GPIO/ATSAME54/include/core_cm4.h b/GPIO/ATSAME54/include/core_cm4.h
new file mode 100644
index 0000000..827dc38
--- /dev/null
+++ b/GPIO/ATSAME54/include/core_cm4.h
@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/GPIO/ATSAME54/include/core_cmFunc.h b/GPIO/ATSAME54/include/core_cmFunc.h
new file mode 100644
index 0000000..a1bd88c
--- /dev/null
+++ b/GPIO/ATSAME54/include/core_cmFunc.h
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.00
+ * @date 28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/GPIO/ATSAME54/include/core_cmInstr.h b/GPIO/ATSAME54/include/core_cmInstr.h
new file mode 100644
index 0000000..cabf4a0
--- /dev/null
+++ b/GPIO/ATSAME54/include/core_cmInstr.h
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.00
+ * @date 28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function executes a exclusive LDR instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function executes a exclusive LDR instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function executes a exclusive LDR instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function executes a exclusive STR instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function executes a exclusive STR instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function executes a exclusive STR instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+/** \brief Rotate Right with Extend (32 bit)
+
+ This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function executes a exclusive LDR instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function executes a exclusive LDR instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function executes a exclusive LDR instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function executes a exclusive STR instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function executes a exclusive STR instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function executes a exclusive STR instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief Rotate Right with Extend (32 bit)
+
+ This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/GPIO/ATSAME54/include/core_cmSimd.h b/GPIO/ATSAME54/include/core_cmSimd.h
new file mode 100644
index 0000000..0466561
--- /dev/null
+++ b/GPIO/ATSAME54/include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/GPIO/ATSAME54/include/instance/ac.h b/GPIO/ATSAME54/include/instance/ac.h
new file mode 100644
index 0000000..fa85532
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/ac.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_AC_INSTANCE_
+#define _SAME54_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA (0x42002000) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (0x42002001) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (0x42002002) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (0x42002004) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (0x42002005) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (0x42002006) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (0x42002007) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (0x42002008) /**< \brief (AC) Status B */
+#define REG_AC_DBGCTRL (0x42002009) /**< \brief (AC) Debug Control */
+#define REG_AC_WINCTRL (0x4200200A) /**< \brief (AC) Window Control */
+#define REG_AC_SCALER0 (0x4200200C) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (0x4200200D) /**< \brief (AC) Scaler 1 */
+#define REG_AC_COMPCTRL0 (0x42002010) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (0x42002014) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SYNCBUSY (0x42002020) /**< \brief (AC) Synchronization Busy */
+#define REG_AC_CALIB (0x42002024) /**< \brief (AC) Calibration */
+#else
+#define REG_AC_CTRLA (*(RwReg8 *)0x42002000UL) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (*(WoReg8 *)0x42002001UL) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (*(RwReg16*)0x42002002UL) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (*(RwReg8 *)0x42002004UL) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (*(RwReg8 *)0x42002005UL) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (*(RwReg8 *)0x42002006UL) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (*(RoReg8 *)0x42002007UL) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (*(RoReg8 *)0x42002008UL) /**< \brief (AC) Status B */
+#define REG_AC_DBGCTRL (*(RwReg8 *)0x42002009UL) /**< \brief (AC) Debug Control */
+#define REG_AC_WINCTRL (*(RwReg8 *)0x4200200AUL) /**< \brief (AC) Window Control */
+#define REG_AC_SCALER0 (*(RwReg8 *)0x4200200CUL) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (*(RwReg8 *)0x4200200DUL) /**< \brief (AC) Scaler 1 */
+#define REG_AC_COMPCTRL0 (*(RwReg *)0x42002010UL) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (*(RwReg *)0x42002014UL) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SYNCBUSY (*(RoReg *)0x42002020UL) /**< \brief (AC) Synchronization Busy */
+#define REG_AC_CALIB (*(RwReg16*)0x42002024UL) /**< \brief (AC) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG
+#define AC_FUSES_BIAS1 // PAIR1 Bias Calibration
+#define AC_GCLK_ID 32 // Index of Generic Clock
+#define AC_IMPLEMENTS_VDBLR 0 // VDoubler implemented ?
+#define AC_NUM_CMP 2 // Number of comparators
+#define AC_PAIRS 1 // Number of pairs of comparators
+#define AC_SPEED_LEVELS 2 // Number of speed values
+
+#endif /* _SAME54_AC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/adc0.h b/GPIO/ATSAME54/include/instance/adc0.h
new file mode 100644
index 0000000..f99c5f9
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/adc0.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC0
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ADC0_INSTANCE_
+#define _SAME54_ADC0_INSTANCE_
+
+/* ========== Register definition for ADC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC0_CTRLA (0x43001C00) /**< \brief (ADC0) Control A */
+#define REG_ADC0_EVCTRL (0x43001C02) /**< \brief (ADC0) Event Control */
+#define REG_ADC0_DBGCTRL (0x43001C03) /**< \brief (ADC0) Debug Control */
+#define REG_ADC0_INPUTCTRL (0x43001C04) /**< \brief (ADC0) Input Control */
+#define REG_ADC0_CTRLB (0x43001C06) /**< \brief (ADC0) Control B */
+#define REG_ADC0_REFCTRL (0x43001C08) /**< \brief (ADC0) Reference Control */
+#define REG_ADC0_AVGCTRL (0x43001C0A) /**< \brief (ADC0) Average Control */
+#define REG_ADC0_SAMPCTRL (0x43001C0B) /**< \brief (ADC0) Sample Time Control */
+#define REG_ADC0_WINLT (0x43001C0C) /**< \brief (ADC0) Window Monitor Lower Threshold */
+#define REG_ADC0_WINUT (0x43001C0E) /**< \brief (ADC0) Window Monitor Upper Threshold */
+#define REG_ADC0_GAINCORR (0x43001C10) /**< \brief (ADC0) Gain Correction */
+#define REG_ADC0_OFFSETCORR (0x43001C12) /**< \brief (ADC0) Offset Correction */
+#define REG_ADC0_SWTRIG (0x43001C14) /**< \brief (ADC0) Software Trigger */
+#define REG_ADC0_INTENCLR (0x43001C2C) /**< \brief (ADC0) Interrupt Enable Clear */
+#define REG_ADC0_INTENSET (0x43001C2D) /**< \brief (ADC0) Interrupt Enable Set */
+#define REG_ADC0_INTFLAG (0x43001C2E) /**< \brief (ADC0) Interrupt Flag Status and Clear */
+#define REG_ADC0_STATUS (0x43001C2F) /**< \brief (ADC0) Status */
+#define REG_ADC0_SYNCBUSY (0x43001C30) /**< \brief (ADC0) Synchronization Busy */
+#define REG_ADC0_DSEQDATA (0x43001C34) /**< \brief (ADC0) DMA Sequencial Data */
+#define REG_ADC0_DSEQCTRL (0x43001C38) /**< \brief (ADC0) DMA Sequential Control */
+#define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */
+#define REG_ADC0_RESULT (0x43001C40) /**< \brief (ADC0) Result Conversion Value */
+#define REG_ADC0_RESS (0x43001C44) /**< \brief (ADC0) Last Sample Result */
+#define REG_ADC0_CALIB (0x43001C48) /**< \brief (ADC0) Calibration */
+#else
+#define REG_ADC0_CTRLA (*(RwReg16*)0x43001C00UL) /**< \brief (ADC0) Control A */
+#define REG_ADC0_EVCTRL (*(RwReg8 *)0x43001C02UL) /**< \brief (ADC0) Event Control */
+#define REG_ADC0_DBGCTRL (*(RwReg8 *)0x43001C03UL) /**< \brief (ADC0) Debug Control */
+#define REG_ADC0_INPUTCTRL (*(RwReg16*)0x43001C04UL) /**< \brief (ADC0) Input Control */
+#define REG_ADC0_CTRLB (*(RwReg16*)0x43001C06UL) /**< \brief (ADC0) Control B */
+#define REG_ADC0_REFCTRL (*(RwReg8 *)0x43001C08UL) /**< \brief (ADC0) Reference Control */
+#define REG_ADC0_AVGCTRL (*(RwReg8 *)0x43001C0AUL) /**< \brief (ADC0) Average Control */
+#define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x43001C0BUL) /**< \brief (ADC0) Sample Time Control */
+#define REG_ADC0_WINLT (*(RwReg16*)0x43001C0CUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
+#define REG_ADC0_WINUT (*(RwReg16*)0x43001C0EUL) /**< \brief (ADC0) Window Monitor Upper Threshold */
+#define REG_ADC0_GAINCORR (*(RwReg16*)0x43001C10UL) /**< \brief (ADC0) Gain Correction */
+#define REG_ADC0_OFFSETCORR (*(RwReg16*)0x43001C12UL) /**< \brief (ADC0) Offset Correction */
+#define REG_ADC0_SWTRIG (*(RwReg8 *)0x43001C14UL) /**< \brief (ADC0) Software Trigger */
+#define REG_ADC0_INTENCLR (*(RwReg8 *)0x43001C2CUL) /**< \brief (ADC0) Interrupt Enable Clear */
+#define REG_ADC0_INTENSET (*(RwReg8 *)0x43001C2DUL) /**< \brief (ADC0) Interrupt Enable Set */
+#define REG_ADC0_INTFLAG (*(RwReg8 *)0x43001C2EUL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
+#define REG_ADC0_STATUS (*(RoReg8 *)0x43001C2FUL) /**< \brief (ADC0) Status */
+#define REG_ADC0_SYNCBUSY (*(RoReg *)0x43001C30UL) /**< \brief (ADC0) Synchronization Busy */
+#define REG_ADC0_DSEQDATA (*(WoReg *)0x43001C34UL) /**< \brief (ADC0) DMA Sequencial Data */
+#define REG_ADC0_DSEQCTRL (*(RwReg *)0x43001C38UL) /**< \brief (ADC0) DMA Sequential Control */
+#define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Status */
+#define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion Value */
+#define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result */
+#define REG_ADC0_CALIB (*(RwReg16*)0x43001C48UL) /**< \brief (ADC0) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC0 peripheral ========== */
+#define ADC0_BANDGAP 27 // MUXPOS value to select BANDGAP
+#define ADC0_CTAT 29 // MUXPOS value to select CTAT
+#define ADC0_DMAC_ID_RESRDY 68 // index of DMA RESRDY trigger
+#define ADC0_DMAC_ID_SEQ 69 // Index of DMA SEQ trigger
+#define ADC0_EXTCHANNEL_MSB 15 // Number of external channels
+#define ADC0_GCLK_ID 40 // index of Generic Clock
+#define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode
+#define ADC0_OPAMP2 0 // MUXPOS value to select OPAMP2
+#define ADC0_OPAMP01 0 // MUXPOS value to select OPAMP01
+#define ADC0_PTAT 28 // MUXPOS value to select PTAT
+#define ADC0_TOUCH_IMPLEMENTED 1 // TOUCH implemented or not
+
+#endif /* _SAME54_ADC0_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/adc1.h b/GPIO/ATSAME54/include/instance/adc1.h
new file mode 100644
index 0000000..9056ec2
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/adc1.h
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC1
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ADC1_INSTANCE_
+#define _SAME54_ADC1_INSTANCE_
+
+/* ========== Register definition for ADC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC1_CTRLA (0x43002000) /**< \brief (ADC1) Control A */
+#define REG_ADC1_EVCTRL (0x43002002) /**< \brief (ADC1) Event Control */
+#define REG_ADC1_DBGCTRL (0x43002003) /**< \brief (ADC1) Debug Control */
+#define REG_ADC1_INPUTCTRL (0x43002004) /**< \brief (ADC1) Input Control */
+#define REG_ADC1_CTRLB (0x43002006) /**< \brief (ADC1) Control B */
+#define REG_ADC1_REFCTRL (0x43002008) /**< \brief (ADC1) Reference Control */
+#define REG_ADC1_AVGCTRL (0x4300200A) /**< \brief (ADC1) Average Control */
+#define REG_ADC1_SAMPCTRL (0x4300200B) /**< \brief (ADC1) Sample Time Control */
+#define REG_ADC1_WINLT (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */
+#define REG_ADC1_WINUT (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */
+#define REG_ADC1_GAINCORR (0x43002010) /**< \brief (ADC1) Gain Correction */
+#define REG_ADC1_OFFSETCORR (0x43002012) /**< \brief (ADC1) Offset Correction */
+#define REG_ADC1_SWTRIG (0x43002014) /**< \brief (ADC1) Software Trigger */
+#define REG_ADC1_INTENCLR (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */
+#define REG_ADC1_INTENSET (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */
+#define REG_ADC1_INTFLAG (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */
+#define REG_ADC1_STATUS (0x4300202F) /**< \brief (ADC1) Status */
+#define REG_ADC1_SYNCBUSY (0x43002030) /**< \brief (ADC1) Synchronization Busy */
+#define REG_ADC1_DSEQDATA (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */
+#define REG_ADC1_DSEQCTRL (0x43002038) /**< \brief (ADC1) DMA Sequential Control */
+#define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */
+#define REG_ADC1_RESULT (0x43002040) /**< \brief (ADC1) Result Conversion Value */
+#define REG_ADC1_RESS (0x43002044) /**< \brief (ADC1) Last Sample Result */
+#define REG_ADC1_CALIB (0x43002048) /**< \brief (ADC1) Calibration */
+#else
+#define REG_ADC1_CTRLA (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */
+#define REG_ADC1_EVCTRL (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */
+#define REG_ADC1_DBGCTRL (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */
+#define REG_ADC1_INPUTCTRL (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */
+#define REG_ADC1_CTRLB (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */
+#define REG_ADC1_REFCTRL (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */
+#define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */
+#define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */
+#define REG_ADC1_WINLT (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
+#define REG_ADC1_WINUT (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */
+#define REG_ADC1_GAINCORR (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */
+#define REG_ADC1_OFFSETCORR (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */
+#define REG_ADC1_SWTRIG (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */
+#define REG_ADC1_INTENCLR (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */
+#define REG_ADC1_INTENSET (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */
+#define REG_ADC1_INTFLAG (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
+#define REG_ADC1_STATUS (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */
+#define REG_ADC1_SYNCBUSY (*(RoReg *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */
+#define REG_ADC1_DSEQDATA (*(WoReg *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */
+#define REG_ADC1_DSEQCTRL (*(RwReg *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */
+#define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */
+#define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */
+#define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */
+#define REG_ADC1_CALIB (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC1 peripheral ========== */
+#define ADC1_BANDGAP 27 // MUXPOS value to select BANDGAP
+#define ADC1_CTAT 29 // MUXPOS value to select CTAT
+#define ADC1_DMAC_ID_RESRDY 70 // Index of DMA RESRDY trigger
+#define ADC1_DMAC_ID_SEQ 71 // Index of DMA SEQ trigger
+#define ADC1_EXTCHANNEL_MSB 15 // Number of external channels
+#define ADC1_GCLK_ID 41 // Index of Generic Clock
+#define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode
+#define ADC1_OPAMP2 0 // MUXPOS value to select OPAMP2
+#define ADC1_OPAMP01 0 // MUXPOS value to select OPAMP01
+#define ADC1_PTAT 28 // MUXPOS value to select PTAT
+#define ADC1_TOUCH_IMPLEMENTED 0 // TOUCH implemented or not
+#define ADC1_TOUCH_LINES_NUM 1 // Number of touch lines
+
+#endif /* _SAME54_ADC1_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/aes.h b/GPIO/ATSAME54/include/instance/aes.h
new file mode 100644
index 0000000..3a60163
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/aes.h
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AES
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_AES_INSTANCE_
+#define _SAME54_AES_INSTANCE_
+
+/* ========== Register definition for AES peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AES_CTRLA (0x42002400) /**< \brief (AES) Control A */
+#define REG_AES_CTRLB (0x42002404) /**< \brief (AES) Control B */
+#define REG_AES_INTENCLR (0x42002405) /**< \brief (AES) Interrupt Enable Clear */
+#define REG_AES_INTENSET (0x42002406) /**< \brief (AES) Interrupt Enable Set */
+#define REG_AES_INTFLAG (0x42002407) /**< \brief (AES) Interrupt Flag Status */
+#define REG_AES_DATABUFPTR (0x42002408) /**< \brief (AES) Data buffer pointer */
+#define REG_AES_DBGCTRL (0x42002409) /**< \brief (AES) Debug control */
+#define REG_AES_KEYWORD0 (0x4200240C) /**< \brief (AES) Keyword 0 */
+#define REG_AES_KEYWORD1 (0x42002410) /**< \brief (AES) Keyword 1 */
+#define REG_AES_KEYWORD2 (0x42002414) /**< \brief (AES) Keyword 2 */
+#define REG_AES_KEYWORD3 (0x42002418) /**< \brief (AES) Keyword 3 */
+#define REG_AES_KEYWORD4 (0x4200241C) /**< \brief (AES) Keyword 4 */
+#define REG_AES_KEYWORD5 (0x42002420) /**< \brief (AES) Keyword 5 */
+#define REG_AES_KEYWORD6 (0x42002424) /**< \brief (AES) Keyword 6 */
+#define REG_AES_KEYWORD7 (0x42002428) /**< \brief (AES) Keyword 7 */
+#define REG_AES_INDATA (0x42002438) /**< \brief (AES) Indata */
+#define REG_AES_INTVECTV0 (0x4200243C) /**< \brief (AES) Initialisation Vector 0 */
+#define REG_AES_INTVECTV1 (0x42002440) /**< \brief (AES) Initialisation Vector 1 */
+#define REG_AES_INTVECTV2 (0x42002444) /**< \brief (AES) Initialisation Vector 2 */
+#define REG_AES_INTVECTV3 (0x42002448) /**< \brief (AES) Initialisation Vector 3 */
+#define REG_AES_HASHKEY0 (0x4200245C) /**< \brief (AES) Hash key 0 */
+#define REG_AES_HASHKEY1 (0x42002460) /**< \brief (AES) Hash key 1 */
+#define REG_AES_HASHKEY2 (0x42002464) /**< \brief (AES) Hash key 2 */
+#define REG_AES_HASHKEY3 (0x42002468) /**< \brief (AES) Hash key 3 */
+#define REG_AES_GHASH0 (0x4200246C) /**< \brief (AES) Galois Hash 0 */
+#define REG_AES_GHASH1 (0x42002470) /**< \brief (AES) Galois Hash 1 */
+#define REG_AES_GHASH2 (0x42002474) /**< \brief (AES) Galois Hash 2 */
+#define REG_AES_GHASH3 (0x42002478) /**< \brief (AES) Galois Hash 3 */
+#define REG_AES_CIPLEN (0x42002480) /**< \brief (AES) Cipher Length */
+#define REG_AES_RANDSEED (0x42002484) /**< \brief (AES) Random Seed */
+#else
+#define REG_AES_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (AES) Control A */
+#define REG_AES_CTRLB (*(RwReg8 *)0x42002404UL) /**< \brief (AES) Control B */
+#define REG_AES_INTENCLR (*(RwReg8 *)0x42002405UL) /**< \brief (AES) Interrupt Enable Clear */
+#define REG_AES_INTENSET (*(RwReg8 *)0x42002406UL) /**< \brief (AES) Interrupt Enable Set */
+#define REG_AES_INTFLAG (*(RwReg8 *)0x42002407UL) /**< \brief (AES) Interrupt Flag Status */
+#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42002408UL) /**< \brief (AES) Data buffer pointer */
+#define REG_AES_DBGCTRL (*(RwReg8 *)0x42002409UL) /**< \brief (AES) Debug control */
+#define REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) /**< \brief (AES) Keyword 0 */
+#define REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) /**< \brief (AES) Keyword 1 */
+#define REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) /**< \brief (AES) Keyword 2 */
+#define REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) /**< \brief (AES) Keyword 3 */
+#define REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) /**< \brief (AES) Keyword 4 */
+#define REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) /**< \brief (AES) Keyword 5 */
+#define REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) /**< \brief (AES) Keyword 6 */
+#define REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) /**< \brief (AES) Keyword 7 */
+#define REG_AES_INDATA (*(RwReg *)0x42002438UL) /**< \brief (AES) Indata */
+#define REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) /**< \brief (AES) Initialisation Vector 0 */
+#define REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) /**< \brief (AES) Initialisation Vector 1 */
+#define REG_AES_INTVECTV2 (*(WoReg *)0x42002444UL) /**< \brief (AES) Initialisation Vector 2 */
+#define REG_AES_INTVECTV3 (*(WoReg *)0x42002448UL) /**< \brief (AES) Initialisation Vector 3 */
+#define REG_AES_HASHKEY0 (*(RwReg *)0x4200245CUL) /**< \brief (AES) Hash key 0 */
+#define REG_AES_HASHKEY1 (*(RwReg *)0x42002460UL) /**< \brief (AES) Hash key 1 */
+#define REG_AES_HASHKEY2 (*(RwReg *)0x42002464UL) /**< \brief (AES) Hash key 2 */
+#define REG_AES_HASHKEY3 (*(RwReg *)0x42002468UL) /**< \brief (AES) Hash key 3 */
+#define REG_AES_GHASH0 (*(RwReg *)0x4200246CUL) /**< \brief (AES) Galois Hash 0 */
+#define REG_AES_GHASH1 (*(RwReg *)0x42002470UL) /**< \brief (AES) Galois Hash 1 */
+#define REG_AES_GHASH2 (*(RwReg *)0x42002474UL) /**< \brief (AES) Galois Hash 2 */
+#define REG_AES_GHASH3 (*(RwReg *)0x42002478UL) /**< \brief (AES) Galois Hash 3 */
+#define REG_AES_CIPLEN (*(RwReg *)0x42002480UL) /**< \brief (AES) Cipher Length */
+#define REG_AES_RANDSEED (*(RwReg *)0x42002484UL) /**< \brief (AES) Random Seed */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AES peripheral ========== */
+#define AES_DMAC_ID_RD 82 // DMA DATA Read trigger
+#define AES_DMAC_ID_WR 81 // DMA DATA Write trigger
+#define AES_FOUR_BYTE_OPERATION 1 // Byte Operation
+#define AES_GCM 1 // GCM
+#define AES_KEYLEN 2 // Key Length
+
+#endif /* _SAME54_AES_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/can0.h b/GPIO/ATSAME54/include/instance/can0.h
new file mode 100644
index 0000000..8643bc4
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/can0.h
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Instance description for CAN0
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CAN0_INSTANCE_
+#define _SAME54_CAN0_INSTANCE_
+
+/* ========== Register definition for CAN0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CAN0_CREL (0x42000000) /**< \brief (CAN0) Core Release */
+#define REG_CAN0_ENDN (0x42000004) /**< \brief (CAN0) Endian */
+#define REG_CAN0_MRCFG (0x42000008) /**< \brief (CAN0) Message RAM Configuration */
+#define REG_CAN0_DBTP (0x4200000C) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
+#define REG_CAN0_TEST (0x42000010) /**< \brief (CAN0) Test */
+#define REG_CAN0_RWD (0x42000014) /**< \brief (CAN0) RAM Watchdog */
+#define REG_CAN0_CCCR (0x42000018) /**< \brief (CAN0) CC Control */
+#define REG_CAN0_NBTP (0x4200001C) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
+#define REG_CAN0_TSCC (0x42000020) /**< \brief (CAN0) Timestamp Counter Configuration */
+#define REG_CAN0_TSCV (0x42000024) /**< \brief (CAN0) Timestamp Counter Value */
+#define REG_CAN0_TOCC (0x42000028) /**< \brief (CAN0) Timeout Counter Configuration */
+#define REG_CAN0_TOCV (0x4200002C) /**< \brief (CAN0) Timeout Counter Value */
+#define REG_CAN0_ECR (0x42000040) /**< \brief (CAN0) Error Counter */
+#define REG_CAN0_PSR (0x42000044) /**< \brief (CAN0) Protocol Status */
+#define REG_CAN0_TDCR (0x42000048) /**< \brief (CAN0) Extended ID Filter Configuration */
+#define REG_CAN0_IR (0x42000050) /**< \brief (CAN0) Interrupt */
+#define REG_CAN0_IE (0x42000054) /**< \brief (CAN0) Interrupt Enable */
+#define REG_CAN0_ILS (0x42000058) /**< \brief (CAN0) Interrupt Line Select */
+#define REG_CAN0_ILE (0x4200005C) /**< \brief (CAN0) Interrupt Line Enable */
+#define REG_CAN0_GFC (0x42000080) /**< \brief (CAN0) Global Filter Configuration */
+#define REG_CAN0_SIDFC (0x42000084) /**< \brief (CAN0) Standard ID Filter Configuration */
+#define REG_CAN0_XIDFC (0x42000088) /**< \brief (CAN0) Extended ID Filter Configuration */
+#define REG_CAN0_XIDAM (0x42000090) /**< \brief (CAN0) Extended ID AND Mask */
+#define REG_CAN0_HPMS (0x42000094) /**< \brief (CAN0) High Priority Message Status */
+#define REG_CAN0_NDAT1 (0x42000098) /**< \brief (CAN0) New Data 1 */
+#define REG_CAN0_NDAT2 (0x4200009C) /**< \brief (CAN0) New Data 2 */
+#define REG_CAN0_RXF0C (0x420000A0) /**< \brief (CAN0) Rx FIFO 0 Configuration */
+#define REG_CAN0_RXF0S (0x420000A4) /**< \brief (CAN0) Rx FIFO 0 Status */
+#define REG_CAN0_RXF0A (0x420000A8) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
+#define REG_CAN0_RXBC (0x420000AC) /**< \brief (CAN0) Rx Buffer Configuration */
+#define REG_CAN0_RXF1C (0x420000B0) /**< \brief (CAN0) Rx FIFO 1 Configuration */
+#define REG_CAN0_RXF1S (0x420000B4) /**< \brief (CAN0) Rx FIFO 1 Status */
+#define REG_CAN0_RXF1A (0x420000B8) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
+#define REG_CAN0_RXESC (0x420000BC) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
+#define REG_CAN0_TXBC (0x420000C0) /**< \brief (CAN0) Tx Buffer Configuration */
+#define REG_CAN0_TXFQS (0x420000C4) /**< \brief (CAN0) Tx FIFO / Queue Status */
+#define REG_CAN0_TXESC (0x420000C8) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
+#define REG_CAN0_TXBRP (0x420000CC) /**< \brief (CAN0) Tx Buffer Request Pending */
+#define REG_CAN0_TXBAR (0x420000D0) /**< \brief (CAN0) Tx Buffer Add Request */
+#define REG_CAN0_TXBCR (0x420000D4) /**< \brief (CAN0) Tx Buffer Cancellation Request */
+#define REG_CAN0_TXBTO (0x420000D8) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
+#define REG_CAN0_TXBCF (0x420000DC) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
+#define REG_CAN0_TXBTIE (0x420000E0) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
+#define REG_CAN0_TXBCIE (0x420000E4) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
+#define REG_CAN0_TXEFC (0x420000F0) /**< \brief (CAN0) Tx Event FIFO Configuration */
+#define REG_CAN0_TXEFS (0x420000F4) /**< \brief (CAN0) Tx Event FIFO Status */
+#define REG_CAN0_TXEFA (0x420000F8) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
+#else
+#define REG_CAN0_CREL (*(RoReg *)0x42000000UL) /**< \brief (CAN0) Core Release */
+#define REG_CAN0_ENDN (*(RoReg *)0x42000004UL) /**< \brief (CAN0) Endian */
+#define REG_CAN0_MRCFG (*(RwReg *)0x42000008UL) /**< \brief (CAN0) Message RAM Configuration */
+#define REG_CAN0_DBTP (*(RwReg *)0x4200000CUL) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
+#define REG_CAN0_TEST (*(RwReg *)0x42000010UL) /**< \brief (CAN0) Test */
+#define REG_CAN0_RWD (*(RwReg *)0x42000014UL) /**< \brief (CAN0) RAM Watchdog */
+#define REG_CAN0_CCCR (*(RwReg *)0x42000018UL) /**< \brief (CAN0) CC Control */
+#define REG_CAN0_NBTP (*(RwReg *)0x4200001CUL) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
+#define REG_CAN0_TSCC (*(RwReg *)0x42000020UL) /**< \brief (CAN0) Timestamp Counter Configuration */
+#define REG_CAN0_TSCV (*(RoReg *)0x42000024UL) /**< \brief (CAN0) Timestamp Counter Value */
+#define REG_CAN0_TOCC (*(RwReg *)0x42000028UL) /**< \brief (CAN0) Timeout Counter Configuration */
+#define REG_CAN0_TOCV (*(RwReg *)0x4200002CUL) /**< \brief (CAN0) Timeout Counter Value */
+#define REG_CAN0_ECR (*(RoReg *)0x42000040UL) /**< \brief (CAN0) Error Counter */
+#define REG_CAN0_PSR (*(RoReg *)0x42000044UL) /**< \brief (CAN0) Protocol Status */
+#define REG_CAN0_TDCR (*(RwReg *)0x42000048UL) /**< \brief (CAN0) Extended ID Filter Configuration */
+#define REG_CAN0_IR (*(RwReg *)0x42000050UL) /**< \brief (CAN0) Interrupt */
+#define REG_CAN0_IE (*(RwReg *)0x42000054UL) /**< \brief (CAN0) Interrupt Enable */
+#define REG_CAN0_ILS (*(RwReg *)0x42000058UL) /**< \brief (CAN0) Interrupt Line Select */
+#define REG_CAN0_ILE (*(RwReg *)0x4200005CUL) /**< \brief (CAN0) Interrupt Line Enable */
+#define REG_CAN0_GFC (*(RwReg *)0x42000080UL) /**< \brief (CAN0) Global Filter Configuration */
+#define REG_CAN0_SIDFC (*(RwReg *)0x42000084UL) /**< \brief (CAN0) Standard ID Filter Configuration */
+#define REG_CAN0_XIDFC (*(RwReg *)0x42000088UL) /**< \brief (CAN0) Extended ID Filter Configuration */
+#define REG_CAN0_XIDAM (*(RwReg *)0x42000090UL) /**< \brief (CAN0) Extended ID AND Mask */
+#define REG_CAN0_HPMS (*(RoReg *)0x42000094UL) /**< \brief (CAN0) High Priority Message Status */
+#define REG_CAN0_NDAT1 (*(RwReg *)0x42000098UL) /**< \brief (CAN0) New Data 1 */
+#define REG_CAN0_NDAT2 (*(RwReg *)0x4200009CUL) /**< \brief (CAN0) New Data 2 */
+#define REG_CAN0_RXF0C (*(RwReg *)0x420000A0UL) /**< \brief (CAN0) Rx FIFO 0 Configuration */
+#define REG_CAN0_RXF0S (*(RoReg *)0x420000A4UL) /**< \brief (CAN0) Rx FIFO 0 Status */
+#define REG_CAN0_RXF0A (*(RwReg *)0x420000A8UL) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
+#define REG_CAN0_RXBC (*(RwReg *)0x420000ACUL) /**< \brief (CAN0) Rx Buffer Configuration */
+#define REG_CAN0_RXF1C (*(RwReg *)0x420000B0UL) /**< \brief (CAN0) Rx FIFO 1 Configuration */
+#define REG_CAN0_RXF1S (*(RoReg *)0x420000B4UL) /**< \brief (CAN0) Rx FIFO 1 Status */
+#define REG_CAN0_RXF1A (*(RwReg *)0x420000B8UL) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
+#define REG_CAN0_RXESC (*(RwReg *)0x420000BCUL) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
+#define REG_CAN0_TXBC (*(RwReg *)0x420000C0UL) /**< \brief (CAN0) Tx Buffer Configuration */
+#define REG_CAN0_TXFQS (*(RoReg *)0x420000C4UL) /**< \brief (CAN0) Tx FIFO / Queue Status */
+#define REG_CAN0_TXESC (*(RwReg *)0x420000C8UL) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
+#define REG_CAN0_TXBRP (*(RoReg *)0x420000CCUL) /**< \brief (CAN0) Tx Buffer Request Pending */
+#define REG_CAN0_TXBAR (*(RwReg *)0x420000D0UL) /**< \brief (CAN0) Tx Buffer Add Request */
+#define REG_CAN0_TXBCR (*(RwReg *)0x420000D4UL) /**< \brief (CAN0) Tx Buffer Cancellation Request */
+#define REG_CAN0_TXBTO (*(RoReg *)0x420000D8UL) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
+#define REG_CAN0_TXBCF (*(RoReg *)0x420000DCUL) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
+#define REG_CAN0_TXBTIE (*(RwReg *)0x420000E0UL) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
+#define REG_CAN0_TXBCIE (*(RwReg *)0x420000E4UL) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
+#define REG_CAN0_TXEFC (*(RwReg *)0x420000F0UL) /**< \brief (CAN0) Tx Event FIFO Configuration */
+#define REG_CAN0_TXEFS (*(RoReg *)0x420000F4UL) /**< \brief (CAN0) Tx Event FIFO Status */
+#define REG_CAN0_TXEFA (*(RwReg *)0x420000F8UL) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for CAN0 peripheral ========== */
+#define CAN0_CLK_AHB_ID 17 // Index of AHB clock
+#define CAN0_DMAC_ID_DEBUG 20 // DMA CAN Debug Req
+#define CAN0_GCLK_ID 27 // Index of Generic Clock
+#define CAN0_MSG_RAM_ADDR 0x20000000
+#define CAN0_QOS_RESET_VAL 1 // QOS reset value
+
+#endif /* _SAME54_CAN0_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/can1.h b/GPIO/ATSAME54/include/instance/can1.h
new file mode 100644
index 0000000..06d7026
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/can1.h
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Instance description for CAN1
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CAN1_INSTANCE_
+#define _SAME54_CAN1_INSTANCE_
+
+/* ========== Register definition for CAN1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CAN1_CREL (0x42000400) /**< \brief (CAN1) Core Release */
+#define REG_CAN1_ENDN (0x42000404) /**< \brief (CAN1) Endian */
+#define REG_CAN1_MRCFG (0x42000408) /**< \brief (CAN1) Message RAM Configuration */
+#define REG_CAN1_DBTP (0x4200040C) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
+#define REG_CAN1_TEST (0x42000410) /**< \brief (CAN1) Test */
+#define REG_CAN1_RWD (0x42000414) /**< \brief (CAN1) RAM Watchdog */
+#define REG_CAN1_CCCR (0x42000418) /**< \brief (CAN1) CC Control */
+#define REG_CAN1_NBTP (0x4200041C) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
+#define REG_CAN1_TSCC (0x42000420) /**< \brief (CAN1) Timestamp Counter Configuration */
+#define REG_CAN1_TSCV (0x42000424) /**< \brief (CAN1) Timestamp Counter Value */
+#define REG_CAN1_TOCC (0x42000428) /**< \brief (CAN1) Timeout Counter Configuration */
+#define REG_CAN1_TOCV (0x4200042C) /**< \brief (CAN1) Timeout Counter Value */
+#define REG_CAN1_ECR (0x42000440) /**< \brief (CAN1) Error Counter */
+#define REG_CAN1_PSR (0x42000444) /**< \brief (CAN1) Protocol Status */
+#define REG_CAN1_TDCR (0x42000448) /**< \brief (CAN1) Extended ID Filter Configuration */
+#define REG_CAN1_IR (0x42000450) /**< \brief (CAN1) Interrupt */
+#define REG_CAN1_IE (0x42000454) /**< \brief (CAN1) Interrupt Enable */
+#define REG_CAN1_ILS (0x42000458) /**< \brief (CAN1) Interrupt Line Select */
+#define REG_CAN1_ILE (0x4200045C) /**< \brief (CAN1) Interrupt Line Enable */
+#define REG_CAN1_GFC (0x42000480) /**< \brief (CAN1) Global Filter Configuration */
+#define REG_CAN1_SIDFC (0x42000484) /**< \brief (CAN1) Standard ID Filter Configuration */
+#define REG_CAN1_XIDFC (0x42000488) /**< \brief (CAN1) Extended ID Filter Configuration */
+#define REG_CAN1_XIDAM (0x42000490) /**< \brief (CAN1) Extended ID AND Mask */
+#define REG_CAN1_HPMS (0x42000494) /**< \brief (CAN1) High Priority Message Status */
+#define REG_CAN1_NDAT1 (0x42000498) /**< \brief (CAN1) New Data 1 */
+#define REG_CAN1_NDAT2 (0x4200049C) /**< \brief (CAN1) New Data 2 */
+#define REG_CAN1_RXF0C (0x420004A0) /**< \brief (CAN1) Rx FIFO 0 Configuration */
+#define REG_CAN1_RXF0S (0x420004A4) /**< \brief (CAN1) Rx FIFO 0 Status */
+#define REG_CAN1_RXF0A (0x420004A8) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
+#define REG_CAN1_RXBC (0x420004AC) /**< \brief (CAN1) Rx Buffer Configuration */
+#define REG_CAN1_RXF1C (0x420004B0) /**< \brief (CAN1) Rx FIFO 1 Configuration */
+#define REG_CAN1_RXF1S (0x420004B4) /**< \brief (CAN1) Rx FIFO 1 Status */
+#define REG_CAN1_RXF1A (0x420004B8) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
+#define REG_CAN1_RXESC (0x420004BC) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
+#define REG_CAN1_TXBC (0x420004C0) /**< \brief (CAN1) Tx Buffer Configuration */
+#define REG_CAN1_TXFQS (0x420004C4) /**< \brief (CAN1) Tx FIFO / Queue Status */
+#define REG_CAN1_TXESC (0x420004C8) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
+#define REG_CAN1_TXBRP (0x420004CC) /**< \brief (CAN1) Tx Buffer Request Pending */
+#define REG_CAN1_TXBAR (0x420004D0) /**< \brief (CAN1) Tx Buffer Add Request */
+#define REG_CAN1_TXBCR (0x420004D4) /**< \brief (CAN1) Tx Buffer Cancellation Request */
+#define REG_CAN1_TXBTO (0x420004D8) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
+#define REG_CAN1_TXBCF (0x420004DC) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
+#define REG_CAN1_TXBTIE (0x420004E0) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
+#define REG_CAN1_TXBCIE (0x420004E4) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
+#define REG_CAN1_TXEFC (0x420004F0) /**< \brief (CAN1) Tx Event FIFO Configuration */
+#define REG_CAN1_TXEFS (0x420004F4) /**< \brief (CAN1) Tx Event FIFO Status */
+#define REG_CAN1_TXEFA (0x420004F8) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
+#else
+#define REG_CAN1_CREL (*(RoReg *)0x42000400UL) /**< \brief (CAN1) Core Release */
+#define REG_CAN1_ENDN (*(RoReg *)0x42000404UL) /**< \brief (CAN1) Endian */
+#define REG_CAN1_MRCFG (*(RwReg *)0x42000408UL) /**< \brief (CAN1) Message RAM Configuration */
+#define REG_CAN1_DBTP (*(RwReg *)0x4200040CUL) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
+#define REG_CAN1_TEST (*(RwReg *)0x42000410UL) /**< \brief (CAN1) Test */
+#define REG_CAN1_RWD (*(RwReg *)0x42000414UL) /**< \brief (CAN1) RAM Watchdog */
+#define REG_CAN1_CCCR (*(RwReg *)0x42000418UL) /**< \brief (CAN1) CC Control */
+#define REG_CAN1_NBTP (*(RwReg *)0x4200041CUL) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
+#define REG_CAN1_TSCC (*(RwReg *)0x42000420UL) /**< \brief (CAN1) Timestamp Counter Configuration */
+#define REG_CAN1_TSCV (*(RoReg *)0x42000424UL) /**< \brief (CAN1) Timestamp Counter Value */
+#define REG_CAN1_TOCC (*(RwReg *)0x42000428UL) /**< \brief (CAN1) Timeout Counter Configuration */
+#define REG_CAN1_TOCV (*(RwReg *)0x4200042CUL) /**< \brief (CAN1) Timeout Counter Value */
+#define REG_CAN1_ECR (*(RoReg *)0x42000440UL) /**< \brief (CAN1) Error Counter */
+#define REG_CAN1_PSR (*(RoReg *)0x42000444UL) /**< \brief (CAN1) Protocol Status */
+#define REG_CAN1_TDCR (*(RwReg *)0x42000448UL) /**< \brief (CAN1) Extended ID Filter Configuration */
+#define REG_CAN1_IR (*(RwReg *)0x42000450UL) /**< \brief (CAN1) Interrupt */
+#define REG_CAN1_IE (*(RwReg *)0x42000454UL) /**< \brief (CAN1) Interrupt Enable */
+#define REG_CAN1_ILS (*(RwReg *)0x42000458UL) /**< \brief (CAN1) Interrupt Line Select */
+#define REG_CAN1_ILE (*(RwReg *)0x4200045CUL) /**< \brief (CAN1) Interrupt Line Enable */
+#define REG_CAN1_GFC (*(RwReg *)0x42000480UL) /**< \brief (CAN1) Global Filter Configuration */
+#define REG_CAN1_SIDFC (*(RwReg *)0x42000484UL) /**< \brief (CAN1) Standard ID Filter Configuration */
+#define REG_CAN1_XIDFC (*(RwReg *)0x42000488UL) /**< \brief (CAN1) Extended ID Filter Configuration */
+#define REG_CAN1_XIDAM (*(RwReg *)0x42000490UL) /**< \brief (CAN1) Extended ID AND Mask */
+#define REG_CAN1_HPMS (*(RoReg *)0x42000494UL) /**< \brief (CAN1) High Priority Message Status */
+#define REG_CAN1_NDAT1 (*(RwReg *)0x42000498UL) /**< \brief (CAN1) New Data 1 */
+#define REG_CAN1_NDAT2 (*(RwReg *)0x4200049CUL) /**< \brief (CAN1) New Data 2 */
+#define REG_CAN1_RXF0C (*(RwReg *)0x420004A0UL) /**< \brief (CAN1) Rx FIFO 0 Configuration */
+#define REG_CAN1_RXF0S (*(RoReg *)0x420004A4UL) /**< \brief (CAN1) Rx FIFO 0 Status */
+#define REG_CAN1_RXF0A (*(RwReg *)0x420004A8UL) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
+#define REG_CAN1_RXBC (*(RwReg *)0x420004ACUL) /**< \brief (CAN1) Rx Buffer Configuration */
+#define REG_CAN1_RXF1C (*(RwReg *)0x420004B0UL) /**< \brief (CAN1) Rx FIFO 1 Configuration */
+#define REG_CAN1_RXF1S (*(RoReg *)0x420004B4UL) /**< \brief (CAN1) Rx FIFO 1 Status */
+#define REG_CAN1_RXF1A (*(RwReg *)0x420004B8UL) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
+#define REG_CAN1_RXESC (*(RwReg *)0x420004BCUL) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
+#define REG_CAN1_TXBC (*(RwReg *)0x420004C0UL) /**< \brief (CAN1) Tx Buffer Configuration */
+#define REG_CAN1_TXFQS (*(RoReg *)0x420004C4UL) /**< \brief (CAN1) Tx FIFO / Queue Status */
+#define REG_CAN1_TXESC (*(RwReg *)0x420004C8UL) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
+#define REG_CAN1_TXBRP (*(RoReg *)0x420004CCUL) /**< \brief (CAN1) Tx Buffer Request Pending */
+#define REG_CAN1_TXBAR (*(RwReg *)0x420004D0UL) /**< \brief (CAN1) Tx Buffer Add Request */
+#define REG_CAN1_TXBCR (*(RwReg *)0x420004D4UL) /**< \brief (CAN1) Tx Buffer Cancellation Request */
+#define REG_CAN1_TXBTO (*(RoReg *)0x420004D8UL) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
+#define REG_CAN1_TXBCF (*(RoReg *)0x420004DCUL) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
+#define REG_CAN1_TXBTIE (*(RwReg *)0x420004E0UL) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
+#define REG_CAN1_TXBCIE (*(RwReg *)0x420004E4UL) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
+#define REG_CAN1_TXEFC (*(RwReg *)0x420004F0UL) /**< \brief (CAN1) Tx Event FIFO Configuration */
+#define REG_CAN1_TXEFS (*(RoReg *)0x420004F4UL) /**< \brief (CAN1) Tx Event FIFO Status */
+#define REG_CAN1_TXEFA (*(RwReg *)0x420004F8UL) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for CAN1 peripheral ========== */
+#define CAN1_CLK_AHB_ID 18 // Index of AHB clock
+#define CAN1_DMAC_ID_DEBUG 21 // DMA CAN Debug Req
+#define CAN1_GCLK_ID 28 // Index of Generic Clock
+#define CAN1_MSG_RAM_ADDR 0x20000000
+#define CAN1_QOS_RESET_VAL 1 // QOS reset value
+
+#endif /* _SAME54_CAN1_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/ccl.h b/GPIO/ATSAME54/include/instance/ccl.h
new file mode 100644
index 0000000..f94416c
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/ccl.h
@@ -0,0 +1,57 @@
+/**
+ * \file
+ *
+ * \brief Instance description for CCL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CCL_INSTANCE_
+#define _SAME54_CCL_INSTANCE_
+
+/* ========== Register definition for CCL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CCL_CTRL (0x42003800) /**< \brief (CCL) Control */
+#define REG_CCL_SEQCTRL0 (0x42003804) /**< \brief (CCL) SEQ Control x 0 */
+#define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */
+#define REG_CCL_LUTCTRL0 (0x42003808) /**< \brief (CCL) LUT Control x 0 */
+#define REG_CCL_LUTCTRL1 (0x4200380C) /**< \brief (CCL) LUT Control x 1 */
+#define REG_CCL_LUTCTRL2 (0x42003810) /**< \brief (CCL) LUT Control x 2 */
+#define REG_CCL_LUTCTRL3 (0x42003814) /**< \brief (CCL) LUT Control x 3 */
+#else
+#define REG_CCL_CTRL (*(RwReg8 *)0x42003800UL) /**< \brief (CCL) Control */
+#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42003804UL) /**< \brief (CCL) SEQ Control x 0 */
+#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */
+#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42003808UL) /**< \brief (CCL) LUT Control x 0 */
+#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200380CUL) /**< \brief (CCL) LUT Control x 1 */
+#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42003810UL) /**< \brief (CCL) LUT Control x 2 */
+#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42003814UL) /**< \brief (CCL) LUT Control x 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for CCL peripheral ========== */
+#define CCL_GCLK_ID 33 // GCLK index for CCL
+#define CCL_LUT_NUM 4 // Number of LUT in a CCL
+#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
+
+#endif /* _SAME54_CCL_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/cmcc.h b/GPIO/ATSAME54/include/instance/cmcc.h
new file mode 100644
index 0000000..18b26ba
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/cmcc.h
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Instance description for CMCC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_CMCC_INSTANCE_
+#define _SAME54_CMCC_INSTANCE_
+
+/* ========== Register definition for CMCC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CMCC_TYPE (0x41006000) /**< \brief (CMCC) Cache Type Register */
+#define REG_CMCC_CFG (0x41006004) /**< \brief (CMCC) Cache Configuration Register */
+#define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */
+#define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */
+#define REG_CMCC_LCKWAY (0x41006010) /**< \brief (CMCC) Cache Lock per Way Register */
+#define REG_CMCC_MAINT0 (0x41006020) /**< \brief (CMCC) Cache Maintenance Register 0 */
+#define REG_CMCC_MAINT1 (0x41006024) /**< \brief (CMCC) Cache Maintenance Register 1 */
+#define REG_CMCC_MCFG (0x41006028) /**< \brief (CMCC) Cache Monitor Configuration Register */
+#define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */
+#define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */
+#define REG_CMCC_MSR (0x41006034) /**< \brief (CMCC) Cache Monitor Status Register */
+#else
+#define REG_CMCC_TYPE (*(RoReg *)0x41006000UL) /**< \brief (CMCC) Cache Type Register */
+#define REG_CMCC_CFG (*(RwReg *)0x41006004UL) /**< \brief (CMCC) Cache Configuration Register */
+#define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Register */
+#define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Register */
+#define REG_CMCC_LCKWAY (*(RwReg *)0x41006010UL) /**< \brief (CMCC) Cache Lock per Way Register */
+#define REG_CMCC_MAINT0 (*(WoReg *)0x41006020UL) /**< \brief (CMCC) Cache Maintenance Register 0 */
+#define REG_CMCC_MAINT1 (*(WoReg *)0x41006024UL) /**< \brief (CMCC) Cache Maintenance Register 1 */
+#define REG_CMCC_MCFG (*(RwReg *)0x41006028UL) /**< \brief (CMCC) Cache Monitor Configuration Register */
+#define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enable Register */
+#define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Control Register */
+#define REG_CMCC_MSR (*(RoReg *)0x41006034UL) /**< \brief (CMCC) Cache Monitor Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME54_CMCC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/dac.h b/GPIO/ATSAME54/include/instance/dac.h
new file mode 100644
index 0000000..926a26a
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/dac.h
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DAC_INSTANCE_
+#define _SAME54_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA (0x43002400) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB (0x43002401) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL (0x43002402) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS (0x43002407) /**< \brief (DAC) Status */
+#define REG_DAC_SYNCBUSY (0x43002408) /**< \brief (DAC) Synchronization Busy */
+#define REG_DAC_DACCTRL0 (0x4300240C) /**< \brief (DAC) DAC 0 Control */
+#define REG_DAC_DACCTRL1 (0x4300240E) /**< \brief (DAC) DAC 1 Control */
+#define REG_DAC_DATA0 (0x43002410) /**< \brief (DAC) DAC 0 Data */
+#define REG_DAC_DATA1 (0x43002412) /**< \brief (DAC) DAC 1 Data */
+#define REG_DAC_DATABUF0 (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
+#define REG_DAC_DATABUF1 (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
+#define REG_DAC_DBGCTRL (0x43002418) /**< \brief (DAC) Debug Control */
+#define REG_DAC_RESULT0 (0x4300241C) /**< \brief (DAC) Filter Result 0 */
+#define REG_DAC_RESULT1 (0x4300241E) /**< \brief (DAC) Filter Result 1 */
+#else
+#define REG_DAC_CTRLA (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
+#define REG_DAC_SYNCBUSY (*(RoReg *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
+#define REG_DAC_DACCTRL0 (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
+#define REG_DAC_DACCTRL1 (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
+#define REG_DAC_DATA0 (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
+#define REG_DAC_DATA1 (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
+#define REG_DAC_DATABUF0 (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
+#define REG_DAC_DATABUF1 (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
+#define REG_DAC_DBGCTRL (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
+#define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
+#define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_CHANNEL_SIZE 2 // Number of DACs
+#define DAC_DATA_SIZE 12 // Number of bits in data
+#define DAC_DMAC_ID_EMPTY_0 72
+#define DAC_DMAC_ID_EMPTY_1 73
+#define DAC_DMAC_ID_EMPTY_LSB 72
+#define DAC_DMAC_ID_EMPTY_MSB 73
+#define DAC_DMAC_ID_EMPTY_SIZE 2
+#define DAC_DMAC_ID_RESRDY_0 74
+#define DAC_DMAC_ID_RESRDY_1 75
+#define DAC_DMAC_ID_RESRDY_LSB 74
+#define DAC_DMAC_ID_RESRDY_MSB 75
+#define DAC_DMAC_ID_RESRDY_SIZE 2
+#define DAC_GCLK_ID 42 // Index of Generic Clock
+#define DAC_STEP 7 // Number of steps to reach full scale
+
+#endif /* _SAME54_DAC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/dmac.h b/GPIO/ATSAME54/include/instance/dmac.h
new file mode 100644
index 0000000..a6642b2
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/dmac.h
@@ -0,0 +1,596 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DMAC_INSTANCE_
+#define _SAME54_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL (0x4100A000) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (0x4100A002) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (0x4100A004) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (0x4100A008) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (0x4100A00C) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (0x4100A00D) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL (0x4100A010) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (0x4100A014) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (0x4100A020) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (0x4100A024) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (0x4100A028) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (0x4100A02C) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (0x4100A030) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (0x4100A034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (0x4100A038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHCTRLA0 (0x4100A040) /**< \brief (DMAC) Channel 0 Control A */
+#define REG_DMAC_CHCTRLB0 (0x4100A044) /**< \brief (DMAC) Channel 0 Control B */
+#define REG_DMAC_CHPRILVL0 (0x4100A045) /**< \brief (DMAC) Channel 0 Priority Level */
+#define REG_DMAC_CHEVCTRL0 (0x4100A046) /**< \brief (DMAC) Channel 0 Event Control */
+#define REG_DMAC_CHINTENCLR0 (0x4100A04C) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET0 (0x4100A04D) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG0 (0x4100A04E) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS0 (0x4100A04F) /**< \brief (DMAC) Channel 0 Status */
+#define REG_DMAC_CHCTRLA1 (0x4100A050) /**< \brief (DMAC) Channel 1 Control A */
+#define REG_DMAC_CHCTRLB1 (0x4100A054) /**< \brief (DMAC) Channel 1 Control B */
+#define REG_DMAC_CHPRILVL1 (0x4100A055) /**< \brief (DMAC) Channel 1 Priority Level */
+#define REG_DMAC_CHEVCTRL1 (0x4100A056) /**< \brief (DMAC) Channel 1 Event Control */
+#define REG_DMAC_CHINTENCLR1 (0x4100A05C) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET1 (0x4100A05D) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG1 (0x4100A05E) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS1 (0x4100A05F) /**< \brief (DMAC) Channel 1 Status */
+#define REG_DMAC_CHCTRLA2 (0x4100A060) /**< \brief (DMAC) Channel 2 Control A */
+#define REG_DMAC_CHCTRLB2 (0x4100A064) /**< \brief (DMAC) Channel 2 Control B */
+#define REG_DMAC_CHPRILVL2 (0x4100A065) /**< \brief (DMAC) Channel 2 Priority Level */
+#define REG_DMAC_CHEVCTRL2 (0x4100A066) /**< \brief (DMAC) Channel 2 Event Control */
+#define REG_DMAC_CHINTENCLR2 (0x4100A06C) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET2 (0x4100A06D) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG2 (0x4100A06E) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS2 (0x4100A06F) /**< \brief (DMAC) Channel 2 Status */
+#define REG_DMAC_CHCTRLA3 (0x4100A070) /**< \brief (DMAC) Channel 3 Control A */
+#define REG_DMAC_CHCTRLB3 (0x4100A074) /**< \brief (DMAC) Channel 3 Control B */
+#define REG_DMAC_CHPRILVL3 (0x4100A075) /**< \brief (DMAC) Channel 3 Priority Level */
+#define REG_DMAC_CHEVCTRL3 (0x4100A076) /**< \brief (DMAC) Channel 3 Event Control */
+#define REG_DMAC_CHINTENCLR3 (0x4100A07C) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET3 (0x4100A07D) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG3 (0x4100A07E) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS3 (0x4100A07F) /**< \brief (DMAC) Channel 3 Status */
+#define REG_DMAC_CHCTRLA4 (0x4100A080) /**< \brief (DMAC) Channel 4 Control A */
+#define REG_DMAC_CHCTRLB4 (0x4100A084) /**< \brief (DMAC) Channel 4 Control B */
+#define REG_DMAC_CHPRILVL4 (0x4100A085) /**< \brief (DMAC) Channel 4 Priority Level */
+#define REG_DMAC_CHEVCTRL4 (0x4100A086) /**< \brief (DMAC) Channel 4 Event Control */
+#define REG_DMAC_CHINTENCLR4 (0x4100A08C) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET4 (0x4100A08D) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG4 (0x4100A08E) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS4 (0x4100A08F) /**< \brief (DMAC) Channel 4 Status */
+#define REG_DMAC_CHCTRLA5 (0x4100A090) /**< \brief (DMAC) Channel 5 Control A */
+#define REG_DMAC_CHCTRLB5 (0x4100A094) /**< \brief (DMAC) Channel 5 Control B */
+#define REG_DMAC_CHPRILVL5 (0x4100A095) /**< \brief (DMAC) Channel 5 Priority Level */
+#define REG_DMAC_CHEVCTRL5 (0x4100A096) /**< \brief (DMAC) Channel 5 Event Control */
+#define REG_DMAC_CHINTENCLR5 (0x4100A09C) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET5 (0x4100A09D) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG5 (0x4100A09E) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS5 (0x4100A09F) /**< \brief (DMAC) Channel 5 Status */
+#define REG_DMAC_CHCTRLA6 (0x4100A0A0) /**< \brief (DMAC) Channel 6 Control A */
+#define REG_DMAC_CHCTRLB6 (0x4100A0A4) /**< \brief (DMAC) Channel 6 Control B */
+#define REG_DMAC_CHPRILVL6 (0x4100A0A5) /**< \brief (DMAC) Channel 6 Priority Level */
+#define REG_DMAC_CHEVCTRL6 (0x4100A0A6) /**< \brief (DMAC) Channel 6 Event Control */
+#define REG_DMAC_CHINTENCLR6 (0x4100A0AC) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET6 (0x4100A0AD) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG6 (0x4100A0AE) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS6 (0x4100A0AF) /**< \brief (DMAC) Channel 6 Status */
+#define REG_DMAC_CHCTRLA7 (0x4100A0B0) /**< \brief (DMAC) Channel 7 Control A */
+#define REG_DMAC_CHCTRLB7 (0x4100A0B4) /**< \brief (DMAC) Channel 7 Control B */
+#define REG_DMAC_CHPRILVL7 (0x4100A0B5) /**< \brief (DMAC) Channel 7 Priority Level */
+#define REG_DMAC_CHEVCTRL7 (0x4100A0B6) /**< \brief (DMAC) Channel 7 Event Control */
+#define REG_DMAC_CHINTENCLR7 (0x4100A0BC) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET7 (0x4100A0BD) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG7 (0x4100A0BE) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS7 (0x4100A0BF) /**< \brief (DMAC) Channel 7 Status */
+#define REG_DMAC_CHCTRLA8 (0x4100A0C0) /**< \brief (DMAC) Channel 8 Control A */
+#define REG_DMAC_CHCTRLB8 (0x4100A0C4) /**< \brief (DMAC) Channel 8 Control B */
+#define REG_DMAC_CHPRILVL8 (0x4100A0C5) /**< \brief (DMAC) Channel 8 Priority Level */
+#define REG_DMAC_CHEVCTRL8 (0x4100A0C6) /**< \brief (DMAC) Channel 8 Event Control */
+#define REG_DMAC_CHINTENCLR8 (0x4100A0CC) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET8 (0x4100A0CD) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG8 (0x4100A0CE) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS8 (0x4100A0CF) /**< \brief (DMAC) Channel 8 Status */
+#define REG_DMAC_CHCTRLA9 (0x4100A0D0) /**< \brief (DMAC) Channel 9 Control A */
+#define REG_DMAC_CHCTRLB9 (0x4100A0D4) /**< \brief (DMAC) Channel 9 Control B */
+#define REG_DMAC_CHPRILVL9 (0x4100A0D5) /**< \brief (DMAC) Channel 9 Priority Level */
+#define REG_DMAC_CHEVCTRL9 (0x4100A0D6) /**< \brief (DMAC) Channel 9 Event Control */
+#define REG_DMAC_CHINTENCLR9 (0x4100A0DC) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET9 (0x4100A0DD) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG9 (0x4100A0DE) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS9 (0x4100A0DF) /**< \brief (DMAC) Channel 9 Status */
+#define REG_DMAC_CHCTRLA10 (0x4100A0E0) /**< \brief (DMAC) Channel 10 Control A */
+#define REG_DMAC_CHCTRLB10 (0x4100A0E4) /**< \brief (DMAC) Channel 10 Control B */
+#define REG_DMAC_CHPRILVL10 (0x4100A0E5) /**< \brief (DMAC) Channel 10 Priority Level */
+#define REG_DMAC_CHEVCTRL10 (0x4100A0E6) /**< \brief (DMAC) Channel 10 Event Control */
+#define REG_DMAC_CHINTENCLR10 (0x4100A0EC) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET10 (0x4100A0ED) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG10 (0x4100A0EE) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS10 (0x4100A0EF) /**< \brief (DMAC) Channel 10 Status */
+#define REG_DMAC_CHCTRLA11 (0x4100A0F0) /**< \brief (DMAC) Channel 11 Control A */
+#define REG_DMAC_CHCTRLB11 (0x4100A0F4) /**< \brief (DMAC) Channel 11 Control B */
+#define REG_DMAC_CHPRILVL11 (0x4100A0F5) /**< \brief (DMAC) Channel 11 Priority Level */
+#define REG_DMAC_CHEVCTRL11 (0x4100A0F6) /**< \brief (DMAC) Channel 11 Event Control */
+#define REG_DMAC_CHINTENCLR11 (0x4100A0FC) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET11 (0x4100A0FD) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG11 (0x4100A0FE) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS11 (0x4100A0FF) /**< \brief (DMAC) Channel 11 Status */
+#define REG_DMAC_CHCTRLA12 (0x4100A100) /**< \brief (DMAC) Channel 12 Control A */
+#define REG_DMAC_CHCTRLB12 (0x4100A104) /**< \brief (DMAC) Channel 12 Control B */
+#define REG_DMAC_CHPRILVL12 (0x4100A105) /**< \brief (DMAC) Channel 12 Priority Level */
+#define REG_DMAC_CHEVCTRL12 (0x4100A106) /**< \brief (DMAC) Channel 12 Event Control */
+#define REG_DMAC_CHINTENCLR12 (0x4100A10C) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET12 (0x4100A10D) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG12 (0x4100A10E) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS12 (0x4100A10F) /**< \brief (DMAC) Channel 12 Status */
+#define REG_DMAC_CHCTRLA13 (0x4100A110) /**< \brief (DMAC) Channel 13 Control A */
+#define REG_DMAC_CHCTRLB13 (0x4100A114) /**< \brief (DMAC) Channel 13 Control B */
+#define REG_DMAC_CHPRILVL13 (0x4100A115) /**< \brief (DMAC) Channel 13 Priority Level */
+#define REG_DMAC_CHEVCTRL13 (0x4100A116) /**< \brief (DMAC) Channel 13 Event Control */
+#define REG_DMAC_CHINTENCLR13 (0x4100A11C) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET13 (0x4100A11D) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG13 (0x4100A11E) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS13 (0x4100A11F) /**< \brief (DMAC) Channel 13 Status */
+#define REG_DMAC_CHCTRLA14 (0x4100A120) /**< \brief (DMAC) Channel 14 Control A */
+#define REG_DMAC_CHCTRLB14 (0x4100A124) /**< \brief (DMAC) Channel 14 Control B */
+#define REG_DMAC_CHPRILVL14 (0x4100A125) /**< \brief (DMAC) Channel 14 Priority Level */
+#define REG_DMAC_CHEVCTRL14 (0x4100A126) /**< \brief (DMAC) Channel 14 Event Control */
+#define REG_DMAC_CHINTENCLR14 (0x4100A12C) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET14 (0x4100A12D) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG14 (0x4100A12E) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS14 (0x4100A12F) /**< \brief (DMAC) Channel 14 Status */
+#define REG_DMAC_CHCTRLA15 (0x4100A130) /**< \brief (DMAC) Channel 15 Control A */
+#define REG_DMAC_CHCTRLB15 (0x4100A134) /**< \brief (DMAC) Channel 15 Control B */
+#define REG_DMAC_CHPRILVL15 (0x4100A135) /**< \brief (DMAC) Channel 15 Priority Level */
+#define REG_DMAC_CHEVCTRL15 (0x4100A136) /**< \brief (DMAC) Channel 15 Event Control */
+#define REG_DMAC_CHINTENCLR15 (0x4100A13C) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET15 (0x4100A13D) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG15 (0x4100A13E) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS15 (0x4100A13F) /**< \brief (DMAC) Channel 15 Status */
+#define REG_DMAC_CHCTRLA16 (0x4100A140) /**< \brief (DMAC) Channel 16 Control A */
+#define REG_DMAC_CHCTRLB16 (0x4100A144) /**< \brief (DMAC) Channel 16 Control B */
+#define REG_DMAC_CHPRILVL16 (0x4100A145) /**< \brief (DMAC) Channel 16 Priority Level */
+#define REG_DMAC_CHEVCTRL16 (0x4100A146) /**< \brief (DMAC) Channel 16 Event Control */
+#define REG_DMAC_CHINTENCLR16 (0x4100A14C) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET16 (0x4100A14D) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG16 (0x4100A14E) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS16 (0x4100A14F) /**< \brief (DMAC) Channel 16 Status */
+#define REG_DMAC_CHCTRLA17 (0x4100A150) /**< \brief (DMAC) Channel 17 Control A */
+#define REG_DMAC_CHCTRLB17 (0x4100A154) /**< \brief (DMAC) Channel 17 Control B */
+#define REG_DMAC_CHPRILVL17 (0x4100A155) /**< \brief (DMAC) Channel 17 Priority Level */
+#define REG_DMAC_CHEVCTRL17 (0x4100A156) /**< \brief (DMAC) Channel 17 Event Control */
+#define REG_DMAC_CHINTENCLR17 (0x4100A15C) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET17 (0x4100A15D) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG17 (0x4100A15E) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS17 (0x4100A15F) /**< \brief (DMAC) Channel 17 Status */
+#define REG_DMAC_CHCTRLA18 (0x4100A160) /**< \brief (DMAC) Channel 18 Control A */
+#define REG_DMAC_CHCTRLB18 (0x4100A164) /**< \brief (DMAC) Channel 18 Control B */
+#define REG_DMAC_CHPRILVL18 (0x4100A165) /**< \brief (DMAC) Channel 18 Priority Level */
+#define REG_DMAC_CHEVCTRL18 (0x4100A166) /**< \brief (DMAC) Channel 18 Event Control */
+#define REG_DMAC_CHINTENCLR18 (0x4100A16C) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET18 (0x4100A16D) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG18 (0x4100A16E) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS18 (0x4100A16F) /**< \brief (DMAC) Channel 18 Status */
+#define REG_DMAC_CHCTRLA19 (0x4100A170) /**< \brief (DMAC) Channel 19 Control A */
+#define REG_DMAC_CHCTRLB19 (0x4100A174) /**< \brief (DMAC) Channel 19 Control B */
+#define REG_DMAC_CHPRILVL19 (0x4100A175) /**< \brief (DMAC) Channel 19 Priority Level */
+#define REG_DMAC_CHEVCTRL19 (0x4100A176) /**< \brief (DMAC) Channel 19 Event Control */
+#define REG_DMAC_CHINTENCLR19 (0x4100A17C) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET19 (0x4100A17D) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG19 (0x4100A17E) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS19 (0x4100A17F) /**< \brief (DMAC) Channel 19 Status */
+#define REG_DMAC_CHCTRLA20 (0x4100A180) /**< \brief (DMAC) Channel 20 Control A */
+#define REG_DMAC_CHCTRLB20 (0x4100A184) /**< \brief (DMAC) Channel 20 Control B */
+#define REG_DMAC_CHPRILVL20 (0x4100A185) /**< \brief (DMAC) Channel 20 Priority Level */
+#define REG_DMAC_CHEVCTRL20 (0x4100A186) /**< \brief (DMAC) Channel 20 Event Control */
+#define REG_DMAC_CHINTENCLR20 (0x4100A18C) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET20 (0x4100A18D) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG20 (0x4100A18E) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS20 (0x4100A18F) /**< \brief (DMAC) Channel 20 Status */
+#define REG_DMAC_CHCTRLA21 (0x4100A190) /**< \brief (DMAC) Channel 21 Control A */
+#define REG_DMAC_CHCTRLB21 (0x4100A194) /**< \brief (DMAC) Channel 21 Control B */
+#define REG_DMAC_CHPRILVL21 (0x4100A195) /**< \brief (DMAC) Channel 21 Priority Level */
+#define REG_DMAC_CHEVCTRL21 (0x4100A196) /**< \brief (DMAC) Channel 21 Event Control */
+#define REG_DMAC_CHINTENCLR21 (0x4100A19C) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET21 (0x4100A19D) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG21 (0x4100A19E) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS21 (0x4100A19F) /**< \brief (DMAC) Channel 21 Status */
+#define REG_DMAC_CHCTRLA22 (0x4100A1A0) /**< \brief (DMAC) Channel 22 Control A */
+#define REG_DMAC_CHCTRLB22 (0x4100A1A4) /**< \brief (DMAC) Channel 22 Control B */
+#define REG_DMAC_CHPRILVL22 (0x4100A1A5) /**< \brief (DMAC) Channel 22 Priority Level */
+#define REG_DMAC_CHEVCTRL22 (0x4100A1A6) /**< \brief (DMAC) Channel 22 Event Control */
+#define REG_DMAC_CHINTENCLR22 (0x4100A1AC) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET22 (0x4100A1AD) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG22 (0x4100A1AE) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS22 (0x4100A1AF) /**< \brief (DMAC) Channel 22 Status */
+#define REG_DMAC_CHCTRLA23 (0x4100A1B0) /**< \brief (DMAC) Channel 23 Control A */
+#define REG_DMAC_CHCTRLB23 (0x4100A1B4) /**< \brief (DMAC) Channel 23 Control B */
+#define REG_DMAC_CHPRILVL23 (0x4100A1B5) /**< \brief (DMAC) Channel 23 Priority Level */
+#define REG_DMAC_CHEVCTRL23 (0x4100A1B6) /**< \brief (DMAC) Channel 23 Event Control */
+#define REG_DMAC_CHINTENCLR23 (0x4100A1BC) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET23 (0x4100A1BD) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG23 (0x4100A1BE) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS23 (0x4100A1BF) /**< \brief (DMAC) Channel 23 Status */
+#define REG_DMAC_CHCTRLA24 (0x4100A1C0) /**< \brief (DMAC) Channel 24 Control A */
+#define REG_DMAC_CHCTRLB24 (0x4100A1C4) /**< \brief (DMAC) Channel 24 Control B */
+#define REG_DMAC_CHPRILVL24 (0x4100A1C5) /**< \brief (DMAC) Channel 24 Priority Level */
+#define REG_DMAC_CHEVCTRL24 (0x4100A1C6) /**< \brief (DMAC) Channel 24 Event Control */
+#define REG_DMAC_CHINTENCLR24 (0x4100A1CC) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET24 (0x4100A1CD) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG24 (0x4100A1CE) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS24 (0x4100A1CF) /**< \brief (DMAC) Channel 24 Status */
+#define REG_DMAC_CHCTRLA25 (0x4100A1D0) /**< \brief (DMAC) Channel 25 Control A */
+#define REG_DMAC_CHCTRLB25 (0x4100A1D4) /**< \brief (DMAC) Channel 25 Control B */
+#define REG_DMAC_CHPRILVL25 (0x4100A1D5) /**< \brief (DMAC) Channel 25 Priority Level */
+#define REG_DMAC_CHEVCTRL25 (0x4100A1D6) /**< \brief (DMAC) Channel 25 Event Control */
+#define REG_DMAC_CHINTENCLR25 (0x4100A1DC) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET25 (0x4100A1DD) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG25 (0x4100A1DE) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS25 (0x4100A1DF) /**< \brief (DMAC) Channel 25 Status */
+#define REG_DMAC_CHCTRLA26 (0x4100A1E0) /**< \brief (DMAC) Channel 26 Control A */
+#define REG_DMAC_CHCTRLB26 (0x4100A1E4) /**< \brief (DMAC) Channel 26 Control B */
+#define REG_DMAC_CHPRILVL26 (0x4100A1E5) /**< \brief (DMAC) Channel 26 Priority Level */
+#define REG_DMAC_CHEVCTRL26 (0x4100A1E6) /**< \brief (DMAC) Channel 26 Event Control */
+#define REG_DMAC_CHINTENCLR26 (0x4100A1EC) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET26 (0x4100A1ED) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG26 (0x4100A1EE) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS26 (0x4100A1EF) /**< \brief (DMAC) Channel 26 Status */
+#define REG_DMAC_CHCTRLA27 (0x4100A1F0) /**< \brief (DMAC) Channel 27 Control A */
+#define REG_DMAC_CHCTRLB27 (0x4100A1F4) /**< \brief (DMAC) Channel 27 Control B */
+#define REG_DMAC_CHPRILVL27 (0x4100A1F5) /**< \brief (DMAC) Channel 27 Priority Level */
+#define REG_DMAC_CHEVCTRL27 (0x4100A1F6) /**< \brief (DMAC) Channel 27 Event Control */
+#define REG_DMAC_CHINTENCLR27 (0x4100A1FC) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET27 (0x4100A1FD) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG27 (0x4100A1FE) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS27 (0x4100A1FF) /**< \brief (DMAC) Channel 27 Status */
+#define REG_DMAC_CHCTRLA28 (0x4100A200) /**< \brief (DMAC) Channel 28 Control A */
+#define REG_DMAC_CHCTRLB28 (0x4100A204) /**< \brief (DMAC) Channel 28 Control B */
+#define REG_DMAC_CHPRILVL28 (0x4100A205) /**< \brief (DMAC) Channel 28 Priority Level */
+#define REG_DMAC_CHEVCTRL28 (0x4100A206) /**< \brief (DMAC) Channel 28 Event Control */
+#define REG_DMAC_CHINTENCLR28 (0x4100A20C) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET28 (0x4100A20D) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG28 (0x4100A20E) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS28 (0x4100A20F) /**< \brief (DMAC) Channel 28 Status */
+#define REG_DMAC_CHCTRLA29 (0x4100A210) /**< \brief (DMAC) Channel 29 Control A */
+#define REG_DMAC_CHCTRLB29 (0x4100A214) /**< \brief (DMAC) Channel 29 Control B */
+#define REG_DMAC_CHPRILVL29 (0x4100A215) /**< \brief (DMAC) Channel 29 Priority Level */
+#define REG_DMAC_CHEVCTRL29 (0x4100A216) /**< \brief (DMAC) Channel 29 Event Control */
+#define REG_DMAC_CHINTENCLR29 (0x4100A21C) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET29 (0x4100A21D) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG29 (0x4100A21E) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS29 (0x4100A21F) /**< \brief (DMAC) Channel 29 Status */
+#define REG_DMAC_CHCTRLA30 (0x4100A220) /**< \brief (DMAC) Channel 30 Control A */
+#define REG_DMAC_CHCTRLB30 (0x4100A224) /**< \brief (DMAC) Channel 30 Control B */
+#define REG_DMAC_CHPRILVL30 (0x4100A225) /**< \brief (DMAC) Channel 30 Priority Level */
+#define REG_DMAC_CHEVCTRL30 (0x4100A226) /**< \brief (DMAC) Channel 30 Event Control */
+#define REG_DMAC_CHINTENCLR30 (0x4100A22C) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET30 (0x4100A22D) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG30 (0x4100A22E) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS30 (0x4100A22F) /**< \brief (DMAC) Channel 30 Status */
+#define REG_DMAC_CHCTRLA31 (0x4100A230) /**< \brief (DMAC) Channel 31 Control A */
+#define REG_DMAC_CHCTRLB31 (0x4100A234) /**< \brief (DMAC) Channel 31 Control B */
+#define REG_DMAC_CHPRILVL31 (0x4100A235) /**< \brief (DMAC) Channel 31 Priority Level */
+#define REG_DMAC_CHEVCTRL31 (0x4100A236) /**< \brief (DMAC) Channel 31 Event Control */
+#define REG_DMAC_CHINTENCLR31 (0x4100A23C) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET31 (0x4100A23D) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG31 (0x4100A23E) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS31 (0x4100A23F) /**< \brief (DMAC) Channel 31 Status */
+#else
+#define REG_DMAC_CTRL (*(RwReg16*)0x4100A000UL) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (*(RwReg16*)0x4100A002UL) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (*(RwReg *)0x4100A004UL) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x4100A008UL) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100A00CUL) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100A00DUL) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x4100A010UL) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (*(RwReg *)0x4100A014UL) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (*(RwReg16*)0x4100A020UL) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (*(RoReg *)0x4100A024UL) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (*(RoReg *)0x4100A028UL) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (*(RoReg *)0x4100A02CUL) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (*(RoReg *)0x4100A030UL) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (*(RwReg *)0x4100A034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (*(RwReg *)0x4100A038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHCTRLA0 (*(RwReg *)0x4100A040UL) /**< \brief (DMAC) Channel 0 Control A */
+#define REG_DMAC_CHCTRLB0 (*(RwReg *)0x4100A044UL) /**< \brief (DMAC) Channel 0 Control B */
+#define REG_DMAC_CHPRILVL0 (*(RwReg *)0x4100A045UL) /**< \brief (DMAC) Channel 0 Priority Level */
+#define REG_DMAC_CHEVCTRL0 (*(RwReg *)0x4100A046UL) /**< \brief (DMAC) Channel 0 Event Control */
+#define REG_DMAC_CHINTENCLR0 (*(RwReg *)0x4100A04CUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET0 (*(RwReg *)0x4100A04DUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG0 (*(RwReg *)0x4100A04EUL) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS0 (*(RwReg *)0x4100A04FUL) /**< \brief (DMAC) Channel 0 Status */
+#define REG_DMAC_CHCTRLA1 (*(RwReg *)0x4100A050UL) /**< \brief (DMAC) Channel 1 Control A */
+#define REG_DMAC_CHCTRLB1 (*(RwReg *)0x4100A054UL) /**< \brief (DMAC) Channel 1 Control B */
+#define REG_DMAC_CHPRILVL1 (*(RwReg *)0x4100A055UL) /**< \brief (DMAC) Channel 1 Priority Level */
+#define REG_DMAC_CHEVCTRL1 (*(RwReg *)0x4100A056UL) /**< \brief (DMAC) Channel 1 Event Control */
+#define REG_DMAC_CHINTENCLR1 (*(RwReg *)0x4100A05CUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET1 (*(RwReg *)0x4100A05DUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG1 (*(RwReg *)0x4100A05EUL) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS1 (*(RwReg *)0x4100A05FUL) /**< \brief (DMAC) Channel 1 Status */
+#define REG_DMAC_CHCTRLA2 (*(RwReg *)0x4100A060UL) /**< \brief (DMAC) Channel 2 Control A */
+#define REG_DMAC_CHCTRLB2 (*(RwReg *)0x4100A064UL) /**< \brief (DMAC) Channel 2 Control B */
+#define REG_DMAC_CHPRILVL2 (*(RwReg *)0x4100A065UL) /**< \brief (DMAC) Channel 2 Priority Level */
+#define REG_DMAC_CHEVCTRL2 (*(RwReg *)0x4100A066UL) /**< \brief (DMAC) Channel 2 Event Control */
+#define REG_DMAC_CHINTENCLR2 (*(RwReg *)0x4100A06CUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET2 (*(RwReg *)0x4100A06DUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG2 (*(RwReg *)0x4100A06EUL) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS2 (*(RwReg *)0x4100A06FUL) /**< \brief (DMAC) Channel 2 Status */
+#define REG_DMAC_CHCTRLA3 (*(RwReg *)0x4100A070UL) /**< \brief (DMAC) Channel 3 Control A */
+#define REG_DMAC_CHCTRLB3 (*(RwReg *)0x4100A074UL) /**< \brief (DMAC) Channel 3 Control B */
+#define REG_DMAC_CHPRILVL3 (*(RwReg *)0x4100A075UL) /**< \brief (DMAC) Channel 3 Priority Level */
+#define REG_DMAC_CHEVCTRL3 (*(RwReg *)0x4100A076UL) /**< \brief (DMAC) Channel 3 Event Control */
+#define REG_DMAC_CHINTENCLR3 (*(RwReg *)0x4100A07CUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET3 (*(RwReg *)0x4100A07DUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG3 (*(RwReg *)0x4100A07EUL) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS3 (*(RwReg *)0x4100A07FUL) /**< \brief (DMAC) Channel 3 Status */
+#define REG_DMAC_CHCTRLA4 (*(RwReg *)0x4100A080UL) /**< \brief (DMAC) Channel 4 Control A */
+#define REG_DMAC_CHCTRLB4 (*(RwReg *)0x4100A084UL) /**< \brief (DMAC) Channel 4 Control B */
+#define REG_DMAC_CHPRILVL4 (*(RwReg *)0x4100A085UL) /**< \brief (DMAC) Channel 4 Priority Level */
+#define REG_DMAC_CHEVCTRL4 (*(RwReg *)0x4100A086UL) /**< \brief (DMAC) Channel 4 Event Control */
+#define REG_DMAC_CHINTENCLR4 (*(RwReg *)0x4100A08CUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET4 (*(RwReg *)0x4100A08DUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG4 (*(RwReg *)0x4100A08EUL) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS4 (*(RwReg *)0x4100A08FUL) /**< \brief (DMAC) Channel 4 Status */
+#define REG_DMAC_CHCTRLA5 (*(RwReg *)0x4100A090UL) /**< \brief (DMAC) Channel 5 Control A */
+#define REG_DMAC_CHCTRLB5 (*(RwReg *)0x4100A094UL) /**< \brief (DMAC) Channel 5 Control B */
+#define REG_DMAC_CHPRILVL5 (*(RwReg *)0x4100A095UL) /**< \brief (DMAC) Channel 5 Priority Level */
+#define REG_DMAC_CHEVCTRL5 (*(RwReg *)0x4100A096UL) /**< \brief (DMAC) Channel 5 Event Control */
+#define REG_DMAC_CHINTENCLR5 (*(RwReg *)0x4100A09CUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET5 (*(RwReg *)0x4100A09DUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG5 (*(RwReg *)0x4100A09EUL) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS5 (*(RwReg *)0x4100A09FUL) /**< \brief (DMAC) Channel 5 Status */
+#define REG_DMAC_CHCTRLA6 (*(RwReg *)0x4100A0A0UL) /**< \brief (DMAC) Channel 6 Control A */
+#define REG_DMAC_CHCTRLB6 (*(RwReg *)0x4100A0A4UL) /**< \brief (DMAC) Channel 6 Control B */
+#define REG_DMAC_CHPRILVL6 (*(RwReg *)0x4100A0A5UL) /**< \brief (DMAC) Channel 6 Priority Level */
+#define REG_DMAC_CHEVCTRL6 (*(RwReg *)0x4100A0A6UL) /**< \brief (DMAC) Channel 6 Event Control */
+#define REG_DMAC_CHINTENCLR6 (*(RwReg *)0x4100A0ACUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET6 (*(RwReg *)0x4100A0ADUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG6 (*(RwReg *)0x4100A0AEUL) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS6 (*(RwReg *)0x4100A0AFUL) /**< \brief (DMAC) Channel 6 Status */
+#define REG_DMAC_CHCTRLA7 (*(RwReg *)0x4100A0B0UL) /**< \brief (DMAC) Channel 7 Control A */
+#define REG_DMAC_CHCTRLB7 (*(RwReg *)0x4100A0B4UL) /**< \brief (DMAC) Channel 7 Control B */
+#define REG_DMAC_CHPRILVL7 (*(RwReg *)0x4100A0B5UL) /**< \brief (DMAC) Channel 7 Priority Level */
+#define REG_DMAC_CHEVCTRL7 (*(RwReg *)0x4100A0B6UL) /**< \brief (DMAC) Channel 7 Event Control */
+#define REG_DMAC_CHINTENCLR7 (*(RwReg *)0x4100A0BCUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET7 (*(RwReg *)0x4100A0BDUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG7 (*(RwReg *)0x4100A0BEUL) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS7 (*(RwReg *)0x4100A0BFUL) /**< \brief (DMAC) Channel 7 Status */
+#define REG_DMAC_CHCTRLA8 (*(RwReg *)0x4100A0C0UL) /**< \brief (DMAC) Channel 8 Control A */
+#define REG_DMAC_CHCTRLB8 (*(RwReg *)0x4100A0C4UL) /**< \brief (DMAC) Channel 8 Control B */
+#define REG_DMAC_CHPRILVL8 (*(RwReg *)0x4100A0C5UL) /**< \brief (DMAC) Channel 8 Priority Level */
+#define REG_DMAC_CHEVCTRL8 (*(RwReg *)0x4100A0C6UL) /**< \brief (DMAC) Channel 8 Event Control */
+#define REG_DMAC_CHINTENCLR8 (*(RwReg *)0x4100A0CCUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET8 (*(RwReg *)0x4100A0CDUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG8 (*(RwReg *)0x4100A0CEUL) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS8 (*(RwReg *)0x4100A0CFUL) /**< \brief (DMAC) Channel 8 Status */
+#define REG_DMAC_CHCTRLA9 (*(RwReg *)0x4100A0D0UL) /**< \brief (DMAC) Channel 9 Control A */
+#define REG_DMAC_CHCTRLB9 (*(RwReg *)0x4100A0D4UL) /**< \brief (DMAC) Channel 9 Control B */
+#define REG_DMAC_CHPRILVL9 (*(RwReg *)0x4100A0D5UL) /**< \brief (DMAC) Channel 9 Priority Level */
+#define REG_DMAC_CHEVCTRL9 (*(RwReg *)0x4100A0D6UL) /**< \brief (DMAC) Channel 9 Event Control */
+#define REG_DMAC_CHINTENCLR9 (*(RwReg *)0x4100A0DCUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET9 (*(RwReg *)0x4100A0DDUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG9 (*(RwReg *)0x4100A0DEUL) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS9 (*(RwReg *)0x4100A0DFUL) /**< \brief (DMAC) Channel 9 Status */
+#define REG_DMAC_CHCTRLA10 (*(RwReg *)0x4100A0E0UL) /**< \brief (DMAC) Channel 10 Control A */
+#define REG_DMAC_CHCTRLB10 (*(RwReg *)0x4100A0E4UL) /**< \brief (DMAC) Channel 10 Control B */
+#define REG_DMAC_CHPRILVL10 (*(RwReg *)0x4100A0E5UL) /**< \brief (DMAC) Channel 10 Priority Level */
+#define REG_DMAC_CHEVCTRL10 (*(RwReg *)0x4100A0E6UL) /**< \brief (DMAC) Channel 10 Event Control */
+#define REG_DMAC_CHINTENCLR10 (*(RwReg *)0x4100A0ECUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET10 (*(RwReg *)0x4100A0EDUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG10 (*(RwReg *)0x4100A0EEUL) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS10 (*(RwReg *)0x4100A0EFUL) /**< \brief (DMAC) Channel 10 Status */
+#define REG_DMAC_CHCTRLA11 (*(RwReg *)0x4100A0F0UL) /**< \brief (DMAC) Channel 11 Control A */
+#define REG_DMAC_CHCTRLB11 (*(RwReg *)0x4100A0F4UL) /**< \brief (DMAC) Channel 11 Control B */
+#define REG_DMAC_CHPRILVL11 (*(RwReg *)0x4100A0F5UL) /**< \brief (DMAC) Channel 11 Priority Level */
+#define REG_DMAC_CHEVCTRL11 (*(RwReg *)0x4100A0F6UL) /**< \brief (DMAC) Channel 11 Event Control */
+#define REG_DMAC_CHINTENCLR11 (*(RwReg *)0x4100A0FCUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET11 (*(RwReg *)0x4100A0FDUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG11 (*(RwReg *)0x4100A0FEUL) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS11 (*(RwReg *)0x4100A0FFUL) /**< \brief (DMAC) Channel 11 Status */
+#define REG_DMAC_CHCTRLA12 (*(RwReg *)0x4100A100UL) /**< \brief (DMAC) Channel 12 Control A */
+#define REG_DMAC_CHCTRLB12 (*(RwReg *)0x4100A104UL) /**< \brief (DMAC) Channel 12 Control B */
+#define REG_DMAC_CHPRILVL12 (*(RwReg *)0x4100A105UL) /**< \brief (DMAC) Channel 12 Priority Level */
+#define REG_DMAC_CHEVCTRL12 (*(RwReg *)0x4100A106UL) /**< \brief (DMAC) Channel 12 Event Control */
+#define REG_DMAC_CHINTENCLR12 (*(RwReg *)0x4100A10CUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET12 (*(RwReg *)0x4100A10DUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG12 (*(RwReg *)0x4100A10EUL) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS12 (*(RwReg *)0x4100A10FUL) /**< \brief (DMAC) Channel 12 Status */
+#define REG_DMAC_CHCTRLA13 (*(RwReg *)0x4100A110UL) /**< \brief (DMAC) Channel 13 Control A */
+#define REG_DMAC_CHCTRLB13 (*(RwReg *)0x4100A114UL) /**< \brief (DMAC) Channel 13 Control B */
+#define REG_DMAC_CHPRILVL13 (*(RwReg *)0x4100A115UL) /**< \brief (DMAC) Channel 13 Priority Level */
+#define REG_DMAC_CHEVCTRL13 (*(RwReg *)0x4100A116UL) /**< \brief (DMAC) Channel 13 Event Control */
+#define REG_DMAC_CHINTENCLR13 (*(RwReg *)0x4100A11CUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET13 (*(RwReg *)0x4100A11DUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG13 (*(RwReg *)0x4100A11EUL) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS13 (*(RwReg *)0x4100A11FUL) /**< \brief (DMAC) Channel 13 Status */
+#define REG_DMAC_CHCTRLA14 (*(RwReg *)0x4100A120UL) /**< \brief (DMAC) Channel 14 Control A */
+#define REG_DMAC_CHCTRLB14 (*(RwReg *)0x4100A124UL) /**< \brief (DMAC) Channel 14 Control B */
+#define REG_DMAC_CHPRILVL14 (*(RwReg *)0x4100A125UL) /**< \brief (DMAC) Channel 14 Priority Level */
+#define REG_DMAC_CHEVCTRL14 (*(RwReg *)0x4100A126UL) /**< \brief (DMAC) Channel 14 Event Control */
+#define REG_DMAC_CHINTENCLR14 (*(RwReg *)0x4100A12CUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET14 (*(RwReg *)0x4100A12DUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG14 (*(RwReg *)0x4100A12EUL) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS14 (*(RwReg *)0x4100A12FUL) /**< \brief (DMAC) Channel 14 Status */
+#define REG_DMAC_CHCTRLA15 (*(RwReg *)0x4100A130UL) /**< \brief (DMAC) Channel 15 Control A */
+#define REG_DMAC_CHCTRLB15 (*(RwReg *)0x4100A134UL) /**< \brief (DMAC) Channel 15 Control B */
+#define REG_DMAC_CHPRILVL15 (*(RwReg *)0x4100A135UL) /**< \brief (DMAC) Channel 15 Priority Level */
+#define REG_DMAC_CHEVCTRL15 (*(RwReg *)0x4100A136UL) /**< \brief (DMAC) Channel 15 Event Control */
+#define REG_DMAC_CHINTENCLR15 (*(RwReg *)0x4100A13CUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET15 (*(RwReg *)0x4100A13DUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG15 (*(RwReg *)0x4100A13EUL) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS15 (*(RwReg *)0x4100A13FUL) /**< \brief (DMAC) Channel 15 Status */
+#define REG_DMAC_CHCTRLA16 (*(RwReg *)0x4100A140UL) /**< \brief (DMAC) Channel 16 Control A */
+#define REG_DMAC_CHCTRLB16 (*(RwReg *)0x4100A144UL) /**< \brief (DMAC) Channel 16 Control B */
+#define REG_DMAC_CHPRILVL16 (*(RwReg *)0x4100A145UL) /**< \brief (DMAC) Channel 16 Priority Level */
+#define REG_DMAC_CHEVCTRL16 (*(RwReg *)0x4100A146UL) /**< \brief (DMAC) Channel 16 Event Control */
+#define REG_DMAC_CHINTENCLR16 (*(RwReg *)0x4100A14CUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET16 (*(RwReg *)0x4100A14DUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG16 (*(RwReg *)0x4100A14EUL) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS16 (*(RwReg *)0x4100A14FUL) /**< \brief (DMAC) Channel 16 Status */
+#define REG_DMAC_CHCTRLA17 (*(RwReg *)0x4100A150UL) /**< \brief (DMAC) Channel 17 Control A */
+#define REG_DMAC_CHCTRLB17 (*(RwReg *)0x4100A154UL) /**< \brief (DMAC) Channel 17 Control B */
+#define REG_DMAC_CHPRILVL17 (*(RwReg *)0x4100A155UL) /**< \brief (DMAC) Channel 17 Priority Level */
+#define REG_DMAC_CHEVCTRL17 (*(RwReg *)0x4100A156UL) /**< \brief (DMAC) Channel 17 Event Control */
+#define REG_DMAC_CHINTENCLR17 (*(RwReg *)0x4100A15CUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET17 (*(RwReg *)0x4100A15DUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG17 (*(RwReg *)0x4100A15EUL) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS17 (*(RwReg *)0x4100A15FUL) /**< \brief (DMAC) Channel 17 Status */
+#define REG_DMAC_CHCTRLA18 (*(RwReg *)0x4100A160UL) /**< \brief (DMAC) Channel 18 Control A */
+#define REG_DMAC_CHCTRLB18 (*(RwReg *)0x4100A164UL) /**< \brief (DMAC) Channel 18 Control B */
+#define REG_DMAC_CHPRILVL18 (*(RwReg *)0x4100A165UL) /**< \brief (DMAC) Channel 18 Priority Level */
+#define REG_DMAC_CHEVCTRL18 (*(RwReg *)0x4100A166UL) /**< \brief (DMAC) Channel 18 Event Control */
+#define REG_DMAC_CHINTENCLR18 (*(RwReg *)0x4100A16CUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET18 (*(RwReg *)0x4100A16DUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG18 (*(RwReg *)0x4100A16EUL) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS18 (*(RwReg *)0x4100A16FUL) /**< \brief (DMAC) Channel 18 Status */
+#define REG_DMAC_CHCTRLA19 (*(RwReg *)0x4100A170UL) /**< \brief (DMAC) Channel 19 Control A */
+#define REG_DMAC_CHCTRLB19 (*(RwReg *)0x4100A174UL) /**< \brief (DMAC) Channel 19 Control B */
+#define REG_DMAC_CHPRILVL19 (*(RwReg *)0x4100A175UL) /**< \brief (DMAC) Channel 19 Priority Level */
+#define REG_DMAC_CHEVCTRL19 (*(RwReg *)0x4100A176UL) /**< \brief (DMAC) Channel 19 Event Control */
+#define REG_DMAC_CHINTENCLR19 (*(RwReg *)0x4100A17CUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET19 (*(RwReg *)0x4100A17DUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG19 (*(RwReg *)0x4100A17EUL) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS19 (*(RwReg *)0x4100A17FUL) /**< \brief (DMAC) Channel 19 Status */
+#define REG_DMAC_CHCTRLA20 (*(RwReg *)0x4100A180UL) /**< \brief (DMAC) Channel 20 Control A */
+#define REG_DMAC_CHCTRLB20 (*(RwReg *)0x4100A184UL) /**< \brief (DMAC) Channel 20 Control B */
+#define REG_DMAC_CHPRILVL20 (*(RwReg *)0x4100A185UL) /**< \brief (DMAC) Channel 20 Priority Level */
+#define REG_DMAC_CHEVCTRL20 (*(RwReg *)0x4100A186UL) /**< \brief (DMAC) Channel 20 Event Control */
+#define REG_DMAC_CHINTENCLR20 (*(RwReg *)0x4100A18CUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET20 (*(RwReg *)0x4100A18DUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG20 (*(RwReg *)0x4100A18EUL) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS20 (*(RwReg *)0x4100A18FUL) /**< \brief (DMAC) Channel 20 Status */
+#define REG_DMAC_CHCTRLA21 (*(RwReg *)0x4100A190UL) /**< \brief (DMAC) Channel 21 Control A */
+#define REG_DMAC_CHCTRLB21 (*(RwReg *)0x4100A194UL) /**< \brief (DMAC) Channel 21 Control B */
+#define REG_DMAC_CHPRILVL21 (*(RwReg *)0x4100A195UL) /**< \brief (DMAC) Channel 21 Priority Level */
+#define REG_DMAC_CHEVCTRL21 (*(RwReg *)0x4100A196UL) /**< \brief (DMAC) Channel 21 Event Control */
+#define REG_DMAC_CHINTENCLR21 (*(RwReg *)0x4100A19CUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET21 (*(RwReg *)0x4100A19DUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG21 (*(RwReg *)0x4100A19EUL) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS21 (*(RwReg *)0x4100A19FUL) /**< \brief (DMAC) Channel 21 Status */
+#define REG_DMAC_CHCTRLA22 (*(RwReg *)0x4100A1A0UL) /**< \brief (DMAC) Channel 22 Control A */
+#define REG_DMAC_CHCTRLB22 (*(RwReg *)0x4100A1A4UL) /**< \brief (DMAC) Channel 22 Control B */
+#define REG_DMAC_CHPRILVL22 (*(RwReg *)0x4100A1A5UL) /**< \brief (DMAC) Channel 22 Priority Level */
+#define REG_DMAC_CHEVCTRL22 (*(RwReg *)0x4100A1A6UL) /**< \brief (DMAC) Channel 22 Event Control */
+#define REG_DMAC_CHINTENCLR22 (*(RwReg *)0x4100A1ACUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET22 (*(RwReg *)0x4100A1ADUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG22 (*(RwReg *)0x4100A1AEUL) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS22 (*(RwReg *)0x4100A1AFUL) /**< \brief (DMAC) Channel 22 Status */
+#define REG_DMAC_CHCTRLA23 (*(RwReg *)0x4100A1B0UL) /**< \brief (DMAC) Channel 23 Control A */
+#define REG_DMAC_CHCTRLB23 (*(RwReg *)0x4100A1B4UL) /**< \brief (DMAC) Channel 23 Control B */
+#define REG_DMAC_CHPRILVL23 (*(RwReg *)0x4100A1B5UL) /**< \brief (DMAC) Channel 23 Priority Level */
+#define REG_DMAC_CHEVCTRL23 (*(RwReg *)0x4100A1B6UL) /**< \brief (DMAC) Channel 23 Event Control */
+#define REG_DMAC_CHINTENCLR23 (*(RwReg *)0x4100A1BCUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET23 (*(RwReg *)0x4100A1BDUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG23 (*(RwReg *)0x4100A1BEUL) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS23 (*(RwReg *)0x4100A1BFUL) /**< \brief (DMAC) Channel 23 Status */
+#define REG_DMAC_CHCTRLA24 (*(RwReg *)0x4100A1C0UL) /**< \brief (DMAC) Channel 24 Control A */
+#define REG_DMAC_CHCTRLB24 (*(RwReg *)0x4100A1C4UL) /**< \brief (DMAC) Channel 24 Control B */
+#define REG_DMAC_CHPRILVL24 (*(RwReg *)0x4100A1C5UL) /**< \brief (DMAC) Channel 24 Priority Level */
+#define REG_DMAC_CHEVCTRL24 (*(RwReg *)0x4100A1C6UL) /**< \brief (DMAC) Channel 24 Event Control */
+#define REG_DMAC_CHINTENCLR24 (*(RwReg *)0x4100A1CCUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET24 (*(RwReg *)0x4100A1CDUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG24 (*(RwReg *)0x4100A1CEUL) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS24 (*(RwReg *)0x4100A1CFUL) /**< \brief (DMAC) Channel 24 Status */
+#define REG_DMAC_CHCTRLA25 (*(RwReg *)0x4100A1D0UL) /**< \brief (DMAC) Channel 25 Control A */
+#define REG_DMAC_CHCTRLB25 (*(RwReg *)0x4100A1D4UL) /**< \brief (DMAC) Channel 25 Control B */
+#define REG_DMAC_CHPRILVL25 (*(RwReg *)0x4100A1D5UL) /**< \brief (DMAC) Channel 25 Priority Level */
+#define REG_DMAC_CHEVCTRL25 (*(RwReg *)0x4100A1D6UL) /**< \brief (DMAC) Channel 25 Event Control */
+#define REG_DMAC_CHINTENCLR25 (*(RwReg *)0x4100A1DCUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET25 (*(RwReg *)0x4100A1DDUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG25 (*(RwReg *)0x4100A1DEUL) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS25 (*(RwReg *)0x4100A1DFUL) /**< \brief (DMAC) Channel 25 Status */
+#define REG_DMAC_CHCTRLA26 (*(RwReg *)0x4100A1E0UL) /**< \brief (DMAC) Channel 26 Control A */
+#define REG_DMAC_CHCTRLB26 (*(RwReg *)0x4100A1E4UL) /**< \brief (DMAC) Channel 26 Control B */
+#define REG_DMAC_CHPRILVL26 (*(RwReg *)0x4100A1E5UL) /**< \brief (DMAC) Channel 26 Priority Level */
+#define REG_DMAC_CHEVCTRL26 (*(RwReg *)0x4100A1E6UL) /**< \brief (DMAC) Channel 26 Event Control */
+#define REG_DMAC_CHINTENCLR26 (*(RwReg *)0x4100A1ECUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET26 (*(RwReg *)0x4100A1EDUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG26 (*(RwReg *)0x4100A1EEUL) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS26 (*(RwReg *)0x4100A1EFUL) /**< \brief (DMAC) Channel 26 Status */
+#define REG_DMAC_CHCTRLA27 (*(RwReg *)0x4100A1F0UL) /**< \brief (DMAC) Channel 27 Control A */
+#define REG_DMAC_CHCTRLB27 (*(RwReg *)0x4100A1F4UL) /**< \brief (DMAC) Channel 27 Control B */
+#define REG_DMAC_CHPRILVL27 (*(RwReg *)0x4100A1F5UL) /**< \brief (DMAC) Channel 27 Priority Level */
+#define REG_DMAC_CHEVCTRL27 (*(RwReg *)0x4100A1F6UL) /**< \brief (DMAC) Channel 27 Event Control */
+#define REG_DMAC_CHINTENCLR27 (*(RwReg *)0x4100A1FCUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET27 (*(RwReg *)0x4100A1FDUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG27 (*(RwReg *)0x4100A1FEUL) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS27 (*(RwReg *)0x4100A1FFUL) /**< \brief (DMAC) Channel 27 Status */
+#define REG_DMAC_CHCTRLA28 (*(RwReg *)0x4100A200UL) /**< \brief (DMAC) Channel 28 Control A */
+#define REG_DMAC_CHCTRLB28 (*(RwReg *)0x4100A204UL) /**< \brief (DMAC) Channel 28 Control B */
+#define REG_DMAC_CHPRILVL28 (*(RwReg *)0x4100A205UL) /**< \brief (DMAC) Channel 28 Priority Level */
+#define REG_DMAC_CHEVCTRL28 (*(RwReg *)0x4100A206UL) /**< \brief (DMAC) Channel 28 Event Control */
+#define REG_DMAC_CHINTENCLR28 (*(RwReg *)0x4100A20CUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET28 (*(RwReg *)0x4100A20DUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG28 (*(RwReg *)0x4100A20EUL) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS28 (*(RwReg *)0x4100A20FUL) /**< \brief (DMAC) Channel 28 Status */
+#define REG_DMAC_CHCTRLA29 (*(RwReg *)0x4100A210UL) /**< \brief (DMAC) Channel 29 Control A */
+#define REG_DMAC_CHCTRLB29 (*(RwReg *)0x4100A214UL) /**< \brief (DMAC) Channel 29 Control B */
+#define REG_DMAC_CHPRILVL29 (*(RwReg *)0x4100A215UL) /**< \brief (DMAC) Channel 29 Priority Level */
+#define REG_DMAC_CHEVCTRL29 (*(RwReg *)0x4100A216UL) /**< \brief (DMAC) Channel 29 Event Control */
+#define REG_DMAC_CHINTENCLR29 (*(RwReg *)0x4100A21CUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET29 (*(RwReg *)0x4100A21DUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG29 (*(RwReg *)0x4100A21EUL) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS29 (*(RwReg *)0x4100A21FUL) /**< \brief (DMAC) Channel 29 Status */
+#define REG_DMAC_CHCTRLA30 (*(RwReg *)0x4100A220UL) /**< \brief (DMAC) Channel 30 Control A */
+#define REG_DMAC_CHCTRLB30 (*(RwReg *)0x4100A224UL) /**< \brief (DMAC) Channel 30 Control B */
+#define REG_DMAC_CHPRILVL30 (*(RwReg *)0x4100A225UL) /**< \brief (DMAC) Channel 30 Priority Level */
+#define REG_DMAC_CHEVCTRL30 (*(RwReg *)0x4100A226UL) /**< \brief (DMAC) Channel 30 Event Control */
+#define REG_DMAC_CHINTENCLR30 (*(RwReg *)0x4100A22CUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET30 (*(RwReg *)0x4100A22DUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG30 (*(RwReg *)0x4100A22EUL) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS30 (*(RwReg *)0x4100A22FUL) /**< \brief (DMAC) Channel 30 Status */
+#define REG_DMAC_CHCTRLA31 (*(RwReg *)0x4100A230UL) /**< \brief (DMAC) Channel 31 Control A */
+#define REG_DMAC_CHCTRLB31 (*(RwReg *)0x4100A234UL) /**< \brief (DMAC) Channel 31 Control B */
+#define REG_DMAC_CHPRILVL31 (*(RwReg *)0x4100A235UL) /**< \brief (DMAC) Channel 31 Priority Level */
+#define REG_DMAC_CHEVCTRL31 (*(RwReg *)0x4100A236UL) /**< \brief (DMAC) Channel 31 Event Control */
+#define REG_DMAC_CHINTENCLR31 (*(RwReg *)0x4100A23CUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET31 (*(RwReg *)0x4100A23DUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG31 (*(RwReg *)0x4100A23EUL) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS31 (*(RwReg *)0x4100A23FUL) /**< \brief (DMAC) Channel 31 Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_BURST 1 // 0: no burst support; 1: burst support
+#define DMAC_CH_BITS 5 // Number of bits to select channel
+#define DMAC_CH_NUM 32 // Number of channels
+#define DMAC_CLK_AHB_ID 9 // AHB clock index
+#define DMAC_EVIN_NUM 8 // Number of input events
+#define DMAC_EVOUT_NUM 4 // Number of output events
+#define DMAC_FIFO_SIZE 16 // FIFO size for burst mode.
+#define DMAC_LVL_BITS 2 // Number of bits to select level priority
+#define DMAC_LVL_NUM 4 // Enable priority level number
+#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
+#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
+#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
+#define DMAC_TRIG_BITS 7 // Number of bits to select trigger source
+#define DMAC_TRIG_NUM 85 // Number of peripheral triggers
+
+#endif /* _SAME54_DMAC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/dsu.h b/GPIO/ATSAME54/include/instance/dsu.h
new file mode 100644
index 0000000..ccf23a1
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/dsu.h
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_DSU_INSTANCE_
+#define _SAME54_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
+#define REG_DSU_CFG (0x4100201C) /**< \brief (DSU) Configuration */
+#define REG_DSU_MBCTRL (0x41002040) /**< \brief (DSU) MBIST Control */
+#define REG_DSU_MBCONFIG (0x41002044) /**< \brief (DSU) MBIST Configuration */
+#define REG_DSU_MBWORD (0x41002048) /**< \brief (DSU) MBIST Background Word */
+#define REG_DSU_MBGSTAT (0x4100204C) /**< \brief (DSU) MBIST Global Status */
+#define REG_DSU_MBDFAIL (0x41002050) /**< \brief (DSU) MBIST Fail Data */
+#define REG_DSU_MBDEXP (0x41002054) /**< \brief (DSU) MBIST Expected Data */
+#define REG_DSU_MBAFAIL (0x41002058) /**< \brief (DSU) MBIST Fail Address */
+#define REG_DSU_MBCONTEXT (0x4100205C) /**< \brief (DSU) MBIST Fail Context */
+#define REG_DSU_MBENABLE0 (0x41002060) /**< \brief (DSU) MBIST Memory Enable 0 */
+#define REG_DSU_MBBUSY0 (0x41002068) /**< \brief (DSU) MBIST Memory Busy 0 */
+#define REG_DSU_MBSTATUS0 (0x41002070) /**< \brief (DSU) MBIST Memory Status 0 */
+#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
+#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
+#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
+#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
+#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
+#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
+#define REG_DSU_CFG (*(RwReg *)0x4100201CUL) /**< \brief (DSU) Configuration */
+#define REG_DSU_MBCTRL (*(RwReg *)0x41002040UL) /**< \brief (DSU) MBIST Control */
+#define REG_DSU_MBCONFIG (*(RwReg *)0x41002044UL) /**< \brief (DSU) MBIST Configuration */
+#define REG_DSU_MBWORD (*(RwReg *)0x41002048UL) /**< \brief (DSU) MBIST Background Word */
+#define REG_DSU_MBGSTAT (*(RwReg *)0x4100204CUL) /**< \brief (DSU) MBIST Global Status */
+#define REG_DSU_MBDFAIL (*(RoReg *)0x41002050UL) /**< \brief (DSU) MBIST Fail Data */
+#define REG_DSU_MBDEXP (*(RoReg *)0x41002054UL) /**< \brief (DSU) MBIST Expected Data */
+#define REG_DSU_MBAFAIL (*(RoReg *)0x41002058UL) /**< \brief (DSU) MBIST Fail Address */
+#define REG_DSU_MBCONTEXT (*(RoReg *)0x4100205CUL) /**< \brief (DSU) MBIST Fail Context */
+#define REG_DSU_MBENABLE0 (*(RwReg *)0x41002060UL) /**< \brief (DSU) MBIST Memory Enable 0 */
+#define REG_DSU_MBBUSY0 (*(RoReg *)0x41002068UL) /**< \brief (DSU) MBIST Memory Busy 0 */
+#define REG_DSU_MBSTATUS0 (*(RwReg *)0x41002070UL) /**< \brief (DSU) MBIST Memory Status 0 */
+#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
+#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
+#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
+#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
+#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
+#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_AHB_ID 4
+#define DSU_DMAC_ID_DCC0 2 // DMAC ID for DCC0 register
+#define DSU_DMAC_ID_DCC1 3 // DMAC ID for DCC1 register
+
+#endif /* _SAME54_DSU_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/eic.h b/GPIO/ATSAME54/include/instance/eic.h
new file mode 100644
index 0000000..7eedf69
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/eic.h
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_EIC_INSTANCE_
+#define _SAME54_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control A */
+#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Synchronization Busy */
+#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */
+#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
+#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
+#define REG_EIC_DEBOUNCEN (0x40002830) /**< \brief (EIC) Debouncer Enable */
+#define REG_EIC_DPRESCALER (0x40002834) /**< \brief (EIC) Debouncer Prescaler */
+#define REG_EIC_PINSTATE (0x40002838) /**< \brief (EIC) Pin State */
+#else
+#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */
+#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */
+#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */
+#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
+#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
+#define REG_EIC_DEBOUNCEN (*(RwReg *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */
+#define REG_EIC_DPRESCALER (*(RwReg *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */
+#define REG_EIC_PINSTATE (*(RoReg *)0x40002838UL) /**< \brief (EIC) Pin State */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_EXTINT_NUM 16 // Number of external interrupts
+#define EIC_GCLK_ID 4 // Generic Clock index
+#define EIC_NUMBER_OF_CONFIG_REGS 2 // Number of CONFIG registers
+#define EIC_NUMBER_OF_DPRESCALER_REGS 2 // Number of DPRESCALER pin groups
+#define EIC_NUMBER_OF_INTERRUPTS 16 // Number of external interrupts (obsolete)
+
+#endif /* _SAME54_EIC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/evsys.h b/GPIO/ATSAME54/include/instance/evsys.h
new file mode 100644
index 0000000..5b30fb2
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/evsys.h
@@ -0,0 +1,723 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_EVSYS_INSTANCE_
+#define _SAME54_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRLA (0x4100E000) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_SWEVT (0x4100E004) /**< \brief (EVSYS) Software Event */
+#define REG_EVSYS_PRICTRL (0x4100E008) /**< \brief (EVSYS) Priority Control */
+#define REG_EVSYS_INTPEND (0x4100E010) /**< \brief (EVSYS) Channel Pending Interrupt */
+#define REG_EVSYS_INTSTATUS (0x4100E014) /**< \brief (EVSYS) Interrupt Status */
+#define REG_EVSYS_BUSYCH (0x4100E018) /**< \brief (EVSYS) Busy Channels */
+#define REG_EVSYS_READYUSR (0x4100E01C) /**< \brief (EVSYS) Ready Users */
+#define REG_EVSYS_CHANNEL0 (0x4100E020) /**< \brief (EVSYS) Channel 0 Control */
+#define REG_EVSYS_CHINTENCLR0 (0x4100E024) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET0 (0x4100E025) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG0 (0x4100E026) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS0 (0x4100E027) /**< \brief (EVSYS) Channel 0 Status */
+#define REG_EVSYS_CHANNEL1 (0x4100E028) /**< \brief (EVSYS) Channel 1 Control */
+#define REG_EVSYS_CHINTENCLR1 (0x4100E02C) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET1 (0x4100E02D) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG1 (0x4100E02E) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS1 (0x4100E02F) /**< \brief (EVSYS) Channel 1 Status */
+#define REG_EVSYS_CHANNEL2 (0x4100E030) /**< \brief (EVSYS) Channel 2 Control */
+#define REG_EVSYS_CHINTENCLR2 (0x4100E034) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET2 (0x4100E035) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG2 (0x4100E036) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS2 (0x4100E037) /**< \brief (EVSYS) Channel 2 Status */
+#define REG_EVSYS_CHANNEL3 (0x4100E038) /**< \brief (EVSYS) Channel 3 Control */
+#define REG_EVSYS_CHINTENCLR3 (0x4100E03C) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET3 (0x4100E03D) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG3 (0x4100E03E) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS3 (0x4100E03F) /**< \brief (EVSYS) Channel 3 Status */
+#define REG_EVSYS_CHANNEL4 (0x4100E040) /**< \brief (EVSYS) Channel 4 Control */
+#define REG_EVSYS_CHINTENCLR4 (0x4100E044) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET4 (0x4100E045) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG4 (0x4100E046) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS4 (0x4100E047) /**< \brief (EVSYS) Channel 4 Status */
+#define REG_EVSYS_CHANNEL5 (0x4100E048) /**< \brief (EVSYS) Channel 5 Control */
+#define REG_EVSYS_CHINTENCLR5 (0x4100E04C) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET5 (0x4100E04D) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG5 (0x4100E04E) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS5 (0x4100E04F) /**< \brief (EVSYS) Channel 5 Status */
+#define REG_EVSYS_CHANNEL6 (0x4100E050) /**< \brief (EVSYS) Channel 6 Control */
+#define REG_EVSYS_CHINTENCLR6 (0x4100E054) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET6 (0x4100E055) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG6 (0x4100E056) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS6 (0x4100E057) /**< \brief (EVSYS) Channel 6 Status */
+#define REG_EVSYS_CHANNEL7 (0x4100E058) /**< \brief (EVSYS) Channel 7 Control */
+#define REG_EVSYS_CHINTENCLR7 (0x4100E05C) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET7 (0x4100E05D) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG7 (0x4100E05E) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS7 (0x4100E05F) /**< \brief (EVSYS) Channel 7 Status */
+#define REG_EVSYS_CHANNEL8 (0x4100E060) /**< \brief (EVSYS) Channel 8 Control */
+#define REG_EVSYS_CHINTENCLR8 (0x4100E064) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET8 (0x4100E065) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG8 (0x4100E066) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS8 (0x4100E067) /**< \brief (EVSYS) Channel 8 Status */
+#define REG_EVSYS_CHANNEL9 (0x4100E068) /**< \brief (EVSYS) Channel 9 Control */
+#define REG_EVSYS_CHINTENCLR9 (0x4100E06C) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET9 (0x4100E06D) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG9 (0x4100E06E) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS9 (0x4100E06F) /**< \brief (EVSYS) Channel 9 Status */
+#define REG_EVSYS_CHANNEL10 (0x4100E070) /**< \brief (EVSYS) Channel 10 Control */
+#define REG_EVSYS_CHINTENCLR10 (0x4100E074) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET10 (0x4100E075) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG10 (0x4100E076) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS10 (0x4100E077) /**< \brief (EVSYS) Channel 10 Status */
+#define REG_EVSYS_CHANNEL11 (0x4100E078) /**< \brief (EVSYS) Channel 11 Control */
+#define REG_EVSYS_CHINTENCLR11 (0x4100E07C) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET11 (0x4100E07D) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG11 (0x4100E07E) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS11 (0x4100E07F) /**< \brief (EVSYS) Channel 11 Status */
+#define REG_EVSYS_CHANNEL12 (0x4100E080) /**< \brief (EVSYS) Channel 12 Control */
+#define REG_EVSYS_CHINTENCLR12 (0x4100E084) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET12 (0x4100E085) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG12 (0x4100E086) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS12 (0x4100E087) /**< \brief (EVSYS) Channel 12 Status */
+#define REG_EVSYS_CHANNEL13 (0x4100E088) /**< \brief (EVSYS) Channel 13 Control */
+#define REG_EVSYS_CHINTENCLR13 (0x4100E08C) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET13 (0x4100E08D) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG13 (0x4100E08E) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS13 (0x4100E08F) /**< \brief (EVSYS) Channel 13 Status */
+#define REG_EVSYS_CHANNEL14 (0x4100E090) /**< \brief (EVSYS) Channel 14 Control */
+#define REG_EVSYS_CHINTENCLR14 (0x4100E094) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET14 (0x4100E095) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG14 (0x4100E096) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS14 (0x4100E097) /**< \brief (EVSYS) Channel 14 Status */
+#define REG_EVSYS_CHANNEL15 (0x4100E098) /**< \brief (EVSYS) Channel 15 Control */
+#define REG_EVSYS_CHINTENCLR15 (0x4100E09C) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET15 (0x4100E09D) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG15 (0x4100E09E) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS15 (0x4100E09F) /**< \brief (EVSYS) Channel 15 Status */
+#define REG_EVSYS_CHANNEL16 (0x4100E0A0) /**< \brief (EVSYS) Channel 16 Control */
+#define REG_EVSYS_CHINTENCLR16 (0x4100E0A4) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET16 (0x4100E0A5) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG16 (0x4100E0A6) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS16 (0x4100E0A7) /**< \brief (EVSYS) Channel 16 Status */
+#define REG_EVSYS_CHANNEL17 (0x4100E0A8) /**< \brief (EVSYS) Channel 17 Control */
+#define REG_EVSYS_CHINTENCLR17 (0x4100E0AC) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET17 (0x4100E0AD) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG17 (0x4100E0AE) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS17 (0x4100E0AF) /**< \brief (EVSYS) Channel 17 Status */
+#define REG_EVSYS_CHANNEL18 (0x4100E0B0) /**< \brief (EVSYS) Channel 18 Control */
+#define REG_EVSYS_CHINTENCLR18 (0x4100E0B4) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET18 (0x4100E0B5) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG18 (0x4100E0B6) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS18 (0x4100E0B7) /**< \brief (EVSYS) Channel 18 Status */
+#define REG_EVSYS_CHANNEL19 (0x4100E0B8) /**< \brief (EVSYS) Channel 19 Control */
+#define REG_EVSYS_CHINTENCLR19 (0x4100E0BC) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET19 (0x4100E0BD) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG19 (0x4100E0BE) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS19 (0x4100E0BF) /**< \brief (EVSYS) Channel 19 Status */
+#define REG_EVSYS_CHANNEL20 (0x4100E0C0) /**< \brief (EVSYS) Channel 20 Control */
+#define REG_EVSYS_CHINTENCLR20 (0x4100E0C4) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET20 (0x4100E0C5) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG20 (0x4100E0C6) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS20 (0x4100E0C7) /**< \brief (EVSYS) Channel 20 Status */
+#define REG_EVSYS_CHANNEL21 (0x4100E0C8) /**< \brief (EVSYS) Channel 21 Control */
+#define REG_EVSYS_CHINTENCLR21 (0x4100E0CC) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET21 (0x4100E0CD) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG21 (0x4100E0CE) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS21 (0x4100E0CF) /**< \brief (EVSYS) Channel 21 Status */
+#define REG_EVSYS_CHANNEL22 (0x4100E0D0) /**< \brief (EVSYS) Channel 22 Control */
+#define REG_EVSYS_CHINTENCLR22 (0x4100E0D4) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET22 (0x4100E0D5) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG22 (0x4100E0D6) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS22 (0x4100E0D7) /**< \brief (EVSYS) Channel 22 Status */
+#define REG_EVSYS_CHANNEL23 (0x4100E0D8) /**< \brief (EVSYS) Channel 23 Control */
+#define REG_EVSYS_CHINTENCLR23 (0x4100E0DC) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET23 (0x4100E0DD) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG23 (0x4100E0DE) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS23 (0x4100E0DF) /**< \brief (EVSYS) Channel 23 Status */
+#define REG_EVSYS_CHANNEL24 (0x4100E0E0) /**< \brief (EVSYS) Channel 24 Control */
+#define REG_EVSYS_CHINTENCLR24 (0x4100E0E4) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET24 (0x4100E0E5) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG24 (0x4100E0E6) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS24 (0x4100E0E7) /**< \brief (EVSYS) Channel 24 Status */
+#define REG_EVSYS_CHANNEL25 (0x4100E0E8) /**< \brief (EVSYS) Channel 25 Control */
+#define REG_EVSYS_CHINTENCLR25 (0x4100E0EC) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET25 (0x4100E0ED) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG25 (0x4100E0EE) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS25 (0x4100E0EF) /**< \brief (EVSYS) Channel 25 Status */
+#define REG_EVSYS_CHANNEL26 (0x4100E0F0) /**< \brief (EVSYS) Channel 26 Control */
+#define REG_EVSYS_CHINTENCLR26 (0x4100E0F4) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET26 (0x4100E0F5) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG26 (0x4100E0F6) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS26 (0x4100E0F7) /**< \brief (EVSYS) Channel 26 Status */
+#define REG_EVSYS_CHANNEL27 (0x4100E0F8) /**< \brief (EVSYS) Channel 27 Control */
+#define REG_EVSYS_CHINTENCLR27 (0x4100E0FC) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET27 (0x4100E0FD) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG27 (0x4100E0FE) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS27 (0x4100E0FF) /**< \brief (EVSYS) Channel 27 Status */
+#define REG_EVSYS_CHANNEL28 (0x4100E100) /**< \brief (EVSYS) Channel 28 Control */
+#define REG_EVSYS_CHINTENCLR28 (0x4100E104) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET28 (0x4100E105) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG28 (0x4100E106) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS28 (0x4100E107) /**< \brief (EVSYS) Channel 28 Status */
+#define REG_EVSYS_CHANNEL29 (0x4100E108) /**< \brief (EVSYS) Channel 29 Control */
+#define REG_EVSYS_CHINTENCLR29 (0x4100E10C) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET29 (0x4100E10D) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG29 (0x4100E10E) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS29 (0x4100E10F) /**< \brief (EVSYS) Channel 29 Status */
+#define REG_EVSYS_CHANNEL30 (0x4100E110) /**< \brief (EVSYS) Channel 30 Control */
+#define REG_EVSYS_CHINTENCLR30 (0x4100E114) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET30 (0x4100E115) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG30 (0x4100E116) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS30 (0x4100E117) /**< \brief (EVSYS) Channel 30 Status */
+#define REG_EVSYS_CHANNEL31 (0x4100E118) /**< \brief (EVSYS) Channel 31 Control */
+#define REG_EVSYS_CHINTENCLR31 (0x4100E11C) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET31 (0x4100E11D) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG31 (0x4100E11E) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS31 (0x4100E11F) /**< \brief (EVSYS) Channel 31 Status */
+#define REG_EVSYS_USER0 (0x4100E120) /**< \brief (EVSYS) User Multiplexer 0 */
+#define REG_EVSYS_USER1 (0x4100E124) /**< \brief (EVSYS) User Multiplexer 1 */
+#define REG_EVSYS_USER2 (0x4100E128) /**< \brief (EVSYS) User Multiplexer 2 */
+#define REG_EVSYS_USER3 (0x4100E12C) /**< \brief (EVSYS) User Multiplexer 3 */
+#define REG_EVSYS_USER4 (0x4100E130) /**< \brief (EVSYS) User Multiplexer 4 */
+#define REG_EVSYS_USER5 (0x4100E134) /**< \brief (EVSYS) User Multiplexer 5 */
+#define REG_EVSYS_USER6 (0x4100E138) /**< \brief (EVSYS) User Multiplexer 6 */
+#define REG_EVSYS_USER7 (0x4100E13C) /**< \brief (EVSYS) User Multiplexer 7 */
+#define REG_EVSYS_USER8 (0x4100E140) /**< \brief (EVSYS) User Multiplexer 8 */
+#define REG_EVSYS_USER9 (0x4100E144) /**< \brief (EVSYS) User Multiplexer 9 */
+#define REG_EVSYS_USER10 (0x4100E148) /**< \brief (EVSYS) User Multiplexer 10 */
+#define REG_EVSYS_USER11 (0x4100E14C) /**< \brief (EVSYS) User Multiplexer 11 */
+#define REG_EVSYS_USER12 (0x4100E150) /**< \brief (EVSYS) User Multiplexer 12 */
+#define REG_EVSYS_USER13 (0x4100E154) /**< \brief (EVSYS) User Multiplexer 13 */
+#define REG_EVSYS_USER14 (0x4100E158) /**< \brief (EVSYS) User Multiplexer 14 */
+#define REG_EVSYS_USER15 (0x4100E15C) /**< \brief (EVSYS) User Multiplexer 15 */
+#define REG_EVSYS_USER16 (0x4100E160) /**< \brief (EVSYS) User Multiplexer 16 */
+#define REG_EVSYS_USER17 (0x4100E164) /**< \brief (EVSYS) User Multiplexer 17 */
+#define REG_EVSYS_USER18 (0x4100E168) /**< \brief (EVSYS) User Multiplexer 18 */
+#define REG_EVSYS_USER19 (0x4100E16C) /**< \brief (EVSYS) User Multiplexer 19 */
+#define REG_EVSYS_USER20 (0x4100E170) /**< \brief (EVSYS) User Multiplexer 20 */
+#define REG_EVSYS_USER21 (0x4100E174) /**< \brief (EVSYS) User Multiplexer 21 */
+#define REG_EVSYS_USER22 (0x4100E178) /**< \brief (EVSYS) User Multiplexer 22 */
+#define REG_EVSYS_USER23 (0x4100E17C) /**< \brief (EVSYS) User Multiplexer 23 */
+#define REG_EVSYS_USER24 (0x4100E180) /**< \brief (EVSYS) User Multiplexer 24 */
+#define REG_EVSYS_USER25 (0x4100E184) /**< \brief (EVSYS) User Multiplexer 25 */
+#define REG_EVSYS_USER26 (0x4100E188) /**< \brief (EVSYS) User Multiplexer 26 */
+#define REG_EVSYS_USER27 (0x4100E18C) /**< \brief (EVSYS) User Multiplexer 27 */
+#define REG_EVSYS_USER28 (0x4100E190) /**< \brief (EVSYS) User Multiplexer 28 */
+#define REG_EVSYS_USER29 (0x4100E194) /**< \brief (EVSYS) User Multiplexer 29 */
+#define REG_EVSYS_USER30 (0x4100E198) /**< \brief (EVSYS) User Multiplexer 30 */
+#define REG_EVSYS_USER31 (0x4100E19C) /**< \brief (EVSYS) User Multiplexer 31 */
+#define REG_EVSYS_USER32 (0x4100E1A0) /**< \brief (EVSYS) User Multiplexer 32 */
+#define REG_EVSYS_USER33 (0x4100E1A4) /**< \brief (EVSYS) User Multiplexer 33 */
+#define REG_EVSYS_USER34 (0x4100E1A8) /**< \brief (EVSYS) User Multiplexer 34 */
+#define REG_EVSYS_USER35 (0x4100E1AC) /**< \brief (EVSYS) User Multiplexer 35 */
+#define REG_EVSYS_USER36 (0x4100E1B0) /**< \brief (EVSYS) User Multiplexer 36 */
+#define REG_EVSYS_USER37 (0x4100E1B4) /**< \brief (EVSYS) User Multiplexer 37 */
+#define REG_EVSYS_USER38 (0x4100E1B8) /**< \brief (EVSYS) User Multiplexer 38 */
+#define REG_EVSYS_USER39 (0x4100E1BC) /**< \brief (EVSYS) User Multiplexer 39 */
+#define REG_EVSYS_USER40 (0x4100E1C0) /**< \brief (EVSYS) User Multiplexer 40 */
+#define REG_EVSYS_USER41 (0x4100E1C4) /**< \brief (EVSYS) User Multiplexer 41 */
+#define REG_EVSYS_USER42 (0x4100E1C8) /**< \brief (EVSYS) User Multiplexer 42 */
+#define REG_EVSYS_USER43 (0x4100E1CC) /**< \brief (EVSYS) User Multiplexer 43 */
+#define REG_EVSYS_USER44 (0x4100E1D0) /**< \brief (EVSYS) User Multiplexer 44 */
+#define REG_EVSYS_USER45 (0x4100E1D4) /**< \brief (EVSYS) User Multiplexer 45 */
+#define REG_EVSYS_USER46 (0x4100E1D8) /**< \brief (EVSYS) User Multiplexer 46 */
+#define REG_EVSYS_USER47 (0x4100E1DC) /**< \brief (EVSYS) User Multiplexer 47 */
+#define REG_EVSYS_USER48 (0x4100E1E0) /**< \brief (EVSYS) User Multiplexer 48 */
+#define REG_EVSYS_USER49 (0x4100E1E4) /**< \brief (EVSYS) User Multiplexer 49 */
+#define REG_EVSYS_USER50 (0x4100E1E8) /**< \brief (EVSYS) User Multiplexer 50 */
+#define REG_EVSYS_USER51 (0x4100E1EC) /**< \brief (EVSYS) User Multiplexer 51 */
+#define REG_EVSYS_USER52 (0x4100E1F0) /**< \brief (EVSYS) User Multiplexer 52 */
+#define REG_EVSYS_USER53 (0x4100E1F4) /**< \brief (EVSYS) User Multiplexer 53 */
+#define REG_EVSYS_USER54 (0x4100E1F8) /**< \brief (EVSYS) User Multiplexer 54 */
+#define REG_EVSYS_USER55 (0x4100E1FC) /**< \brief (EVSYS) User Multiplexer 55 */
+#define REG_EVSYS_USER56 (0x4100E200) /**< \brief (EVSYS) User Multiplexer 56 */
+#define REG_EVSYS_USER57 (0x4100E204) /**< \brief (EVSYS) User Multiplexer 57 */
+#define REG_EVSYS_USER58 (0x4100E208) /**< \brief (EVSYS) User Multiplexer 58 */
+#define REG_EVSYS_USER59 (0x4100E20C) /**< \brief (EVSYS) User Multiplexer 59 */
+#define REG_EVSYS_USER60 (0x4100E210) /**< \brief (EVSYS) User Multiplexer 60 */
+#define REG_EVSYS_USER61 (0x4100E214) /**< \brief (EVSYS) User Multiplexer 61 */
+#define REG_EVSYS_USER62 (0x4100E218) /**< \brief (EVSYS) User Multiplexer 62 */
+#define REG_EVSYS_USER63 (0x4100E21C) /**< \brief (EVSYS) User Multiplexer 63 */
+#define REG_EVSYS_USER64 (0x4100E220) /**< \brief (EVSYS) User Multiplexer 64 */
+#define REG_EVSYS_USER65 (0x4100E224) /**< \brief (EVSYS) User Multiplexer 65 */
+#define REG_EVSYS_USER66 (0x4100E228) /**< \brief (EVSYS) User Multiplexer 66 */
+#else
+#define REG_EVSYS_CTRLA (*(RwReg8 *)0x4100E000UL) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_SWEVT (*(WoReg *)0x4100E004UL) /**< \brief (EVSYS) Software Event */
+#define REG_EVSYS_PRICTRL (*(RwReg8 *)0x4100E008UL) /**< \brief (EVSYS) Priority Control */
+#define REG_EVSYS_INTPEND (*(RwReg16*)0x4100E010UL) /**< \brief (EVSYS) Channel Pending Interrupt */
+#define REG_EVSYS_INTSTATUS (*(RoReg *)0x4100E014UL) /**< \brief (EVSYS) Interrupt Status */
+#define REG_EVSYS_BUSYCH (*(RoReg *)0x4100E018UL) /**< \brief (EVSYS) Busy Channels */
+#define REG_EVSYS_READYUSR (*(RoReg *)0x4100E01CUL) /**< \brief (EVSYS) Ready Users */
+#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x4100E020UL) /**< \brief (EVSYS) Channel 0 Control */
+#define REG_EVSYS_CHINTENCLR0 (*(RwReg *)0x4100E024UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET0 (*(RwReg *)0x4100E025UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG0 (*(RwReg *)0x4100E026UL) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS0 (*(RoReg *)0x4100E027UL) /**< \brief (EVSYS) Channel 0 Status */
+#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x4100E028UL) /**< \brief (EVSYS) Channel 1 Control */
+#define REG_EVSYS_CHINTENCLR1 (*(RwReg *)0x4100E02CUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET1 (*(RwReg *)0x4100E02DUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG1 (*(RwReg *)0x4100E02EUL) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS1 (*(RoReg *)0x4100E02FUL) /**< \brief (EVSYS) Channel 1 Status */
+#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x4100E030UL) /**< \brief (EVSYS) Channel 2 Control */
+#define REG_EVSYS_CHINTENCLR2 (*(RwReg *)0x4100E034UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET2 (*(RwReg *)0x4100E035UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG2 (*(RwReg *)0x4100E036UL) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS2 (*(RoReg *)0x4100E037UL) /**< \brief (EVSYS) Channel 2 Status */
+#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4100E038UL) /**< \brief (EVSYS) Channel 3 Control */
+#define REG_EVSYS_CHINTENCLR3 (*(RwReg *)0x4100E03CUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET3 (*(RwReg *)0x4100E03DUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG3 (*(RwReg *)0x4100E03EUL) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS3 (*(RoReg *)0x4100E03FUL) /**< \brief (EVSYS) Channel 3 Status */
+#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x4100E040UL) /**< \brief (EVSYS) Channel 4 Control */
+#define REG_EVSYS_CHINTENCLR4 (*(RwReg *)0x4100E044UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET4 (*(RwReg *)0x4100E045UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG4 (*(RwReg *)0x4100E046UL) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS4 (*(RoReg *)0x4100E047UL) /**< \brief (EVSYS) Channel 4 Status */
+#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x4100E048UL) /**< \brief (EVSYS) Channel 5 Control */
+#define REG_EVSYS_CHINTENCLR5 (*(RwReg *)0x4100E04CUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET5 (*(RwReg *)0x4100E04DUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG5 (*(RwReg *)0x4100E04EUL) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS5 (*(RoReg *)0x4100E04FUL) /**< \brief (EVSYS) Channel 5 Status */
+#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x4100E050UL) /**< \brief (EVSYS) Channel 6 Control */
+#define REG_EVSYS_CHINTENCLR6 (*(RwReg *)0x4100E054UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET6 (*(RwReg *)0x4100E055UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG6 (*(RwReg *)0x4100E056UL) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS6 (*(RoReg *)0x4100E057UL) /**< \brief (EVSYS) Channel 6 Status */
+#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4100E058UL) /**< \brief (EVSYS) Channel 7 Control */
+#define REG_EVSYS_CHINTENCLR7 (*(RwReg *)0x4100E05CUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET7 (*(RwReg *)0x4100E05DUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG7 (*(RwReg *)0x4100E05EUL) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS7 (*(RoReg *)0x4100E05FUL) /**< \brief (EVSYS) Channel 7 Status */
+#define REG_EVSYS_CHANNEL8 (*(RwReg *)0x4100E060UL) /**< \brief (EVSYS) Channel 8 Control */
+#define REG_EVSYS_CHINTENCLR8 (*(RwReg *)0x4100E064UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET8 (*(RwReg *)0x4100E065UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG8 (*(RwReg *)0x4100E066UL) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS8 (*(RoReg *)0x4100E067UL) /**< \brief (EVSYS) Channel 8 Status */
+#define REG_EVSYS_CHANNEL9 (*(RwReg *)0x4100E068UL) /**< \brief (EVSYS) Channel 9 Control */
+#define REG_EVSYS_CHINTENCLR9 (*(RwReg *)0x4100E06CUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET9 (*(RwReg *)0x4100E06DUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG9 (*(RwReg *)0x4100E06EUL) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS9 (*(RoReg *)0x4100E06FUL) /**< \brief (EVSYS) Channel 9 Status */
+#define REG_EVSYS_CHANNEL10 (*(RwReg *)0x4100E070UL) /**< \brief (EVSYS) Channel 10 Control */
+#define REG_EVSYS_CHINTENCLR10 (*(RwReg *)0x4100E074UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET10 (*(RwReg *)0x4100E075UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG10 (*(RwReg *)0x4100E076UL) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS10 (*(RoReg *)0x4100E077UL) /**< \brief (EVSYS) Channel 10 Status */
+#define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4100E078UL) /**< \brief (EVSYS) Channel 11 Control */
+#define REG_EVSYS_CHINTENCLR11 (*(RwReg *)0x4100E07CUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET11 (*(RwReg *)0x4100E07DUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG11 (*(RwReg *)0x4100E07EUL) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS11 (*(RoReg *)0x4100E07FUL) /**< \brief (EVSYS) Channel 11 Status */
+#define REG_EVSYS_CHANNEL12 (*(RwReg *)0x4100E080UL) /**< \brief (EVSYS) Channel 12 Control */
+#define REG_EVSYS_CHINTENCLR12 (*(RwReg *)0x4100E084UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET12 (*(RwReg *)0x4100E085UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG12 (*(RwReg *)0x4100E086UL) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS12 (*(RoReg *)0x4100E087UL) /**< \brief (EVSYS) Channel 12 Status */
+#define REG_EVSYS_CHANNEL13 (*(RwReg *)0x4100E088UL) /**< \brief (EVSYS) Channel 13 Control */
+#define REG_EVSYS_CHINTENCLR13 (*(RwReg *)0x4100E08CUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET13 (*(RwReg *)0x4100E08DUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG13 (*(RwReg *)0x4100E08EUL) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS13 (*(RoReg *)0x4100E08FUL) /**< \brief (EVSYS) Channel 13 Status */
+#define REG_EVSYS_CHANNEL14 (*(RwReg *)0x4100E090UL) /**< \brief (EVSYS) Channel 14 Control */
+#define REG_EVSYS_CHINTENCLR14 (*(RwReg *)0x4100E094UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET14 (*(RwReg *)0x4100E095UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG14 (*(RwReg *)0x4100E096UL) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS14 (*(RoReg *)0x4100E097UL) /**< \brief (EVSYS) Channel 14 Status */
+#define REG_EVSYS_CHANNEL15 (*(RwReg *)0x4100E098UL) /**< \brief (EVSYS) Channel 15 Control */
+#define REG_EVSYS_CHINTENCLR15 (*(RwReg *)0x4100E09CUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET15 (*(RwReg *)0x4100E09DUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG15 (*(RwReg *)0x4100E09EUL) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS15 (*(RoReg *)0x4100E09FUL) /**< \brief (EVSYS) Channel 15 Status */
+#define REG_EVSYS_CHANNEL16 (*(RwReg *)0x4100E0A0UL) /**< \brief (EVSYS) Channel 16 Control */
+#define REG_EVSYS_CHINTENCLR16 (*(RwReg *)0x4100E0A4UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET16 (*(RwReg *)0x4100E0A5UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG16 (*(RwReg *)0x4100E0A6UL) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS16 (*(RoReg *)0x4100E0A7UL) /**< \brief (EVSYS) Channel 16 Status */
+#define REG_EVSYS_CHANNEL17 (*(RwReg *)0x4100E0A8UL) /**< \brief (EVSYS) Channel 17 Control */
+#define REG_EVSYS_CHINTENCLR17 (*(RwReg *)0x4100E0ACUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET17 (*(RwReg *)0x4100E0ADUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG17 (*(RwReg *)0x4100E0AEUL) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS17 (*(RoReg *)0x4100E0AFUL) /**< \brief (EVSYS) Channel 17 Status */
+#define REG_EVSYS_CHANNEL18 (*(RwReg *)0x4100E0B0UL) /**< \brief (EVSYS) Channel 18 Control */
+#define REG_EVSYS_CHINTENCLR18 (*(RwReg *)0x4100E0B4UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET18 (*(RwReg *)0x4100E0B5UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG18 (*(RwReg *)0x4100E0B6UL) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS18 (*(RoReg *)0x4100E0B7UL) /**< \brief (EVSYS) Channel 18 Status */
+#define REG_EVSYS_CHANNEL19 (*(RwReg *)0x4100E0B8UL) /**< \brief (EVSYS) Channel 19 Control */
+#define REG_EVSYS_CHINTENCLR19 (*(RwReg *)0x4100E0BCUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET19 (*(RwReg *)0x4100E0BDUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG19 (*(RwReg *)0x4100E0BEUL) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS19 (*(RoReg *)0x4100E0BFUL) /**< \brief (EVSYS) Channel 19 Status */
+#define REG_EVSYS_CHANNEL20 (*(RwReg *)0x4100E0C0UL) /**< \brief (EVSYS) Channel 20 Control */
+#define REG_EVSYS_CHINTENCLR20 (*(RwReg *)0x4100E0C4UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET20 (*(RwReg *)0x4100E0C5UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG20 (*(RwReg *)0x4100E0C6UL) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS20 (*(RoReg *)0x4100E0C7UL) /**< \brief (EVSYS) Channel 20 Status */
+#define REG_EVSYS_CHANNEL21 (*(RwReg *)0x4100E0C8UL) /**< \brief (EVSYS) Channel 21 Control */
+#define REG_EVSYS_CHINTENCLR21 (*(RwReg *)0x4100E0CCUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET21 (*(RwReg *)0x4100E0CDUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG21 (*(RwReg *)0x4100E0CEUL) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS21 (*(RoReg *)0x4100E0CFUL) /**< \brief (EVSYS) Channel 21 Status */
+#define REG_EVSYS_CHANNEL22 (*(RwReg *)0x4100E0D0UL) /**< \brief (EVSYS) Channel 22 Control */
+#define REG_EVSYS_CHINTENCLR22 (*(RwReg *)0x4100E0D4UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET22 (*(RwReg *)0x4100E0D5UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG22 (*(RwReg *)0x4100E0D6UL) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS22 (*(RoReg *)0x4100E0D7UL) /**< \brief (EVSYS) Channel 22 Status */
+#define REG_EVSYS_CHANNEL23 (*(RwReg *)0x4100E0D8UL) /**< \brief (EVSYS) Channel 23 Control */
+#define REG_EVSYS_CHINTENCLR23 (*(RwReg *)0x4100E0DCUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET23 (*(RwReg *)0x4100E0DDUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG23 (*(RwReg *)0x4100E0DEUL) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS23 (*(RoReg *)0x4100E0DFUL) /**< \brief (EVSYS) Channel 23 Status */
+#define REG_EVSYS_CHANNEL24 (*(RwReg *)0x4100E0E0UL) /**< \brief (EVSYS) Channel 24 Control */
+#define REG_EVSYS_CHINTENCLR24 (*(RwReg *)0x4100E0E4UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET24 (*(RwReg *)0x4100E0E5UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG24 (*(RwReg *)0x4100E0E6UL) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS24 (*(RoReg *)0x4100E0E7UL) /**< \brief (EVSYS) Channel 24 Status */
+#define REG_EVSYS_CHANNEL25 (*(RwReg *)0x4100E0E8UL) /**< \brief (EVSYS) Channel 25 Control */
+#define REG_EVSYS_CHINTENCLR25 (*(RwReg *)0x4100E0ECUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET25 (*(RwReg *)0x4100E0EDUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG25 (*(RwReg *)0x4100E0EEUL) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS25 (*(RoReg *)0x4100E0EFUL) /**< \brief (EVSYS) Channel 25 Status */
+#define REG_EVSYS_CHANNEL26 (*(RwReg *)0x4100E0F0UL) /**< \brief (EVSYS) Channel 26 Control */
+#define REG_EVSYS_CHINTENCLR26 (*(RwReg *)0x4100E0F4UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET26 (*(RwReg *)0x4100E0F5UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG26 (*(RwReg *)0x4100E0F6UL) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS26 (*(RoReg *)0x4100E0F7UL) /**< \brief (EVSYS) Channel 26 Status */
+#define REG_EVSYS_CHANNEL27 (*(RwReg *)0x4100E0F8UL) /**< \brief (EVSYS) Channel 27 Control */
+#define REG_EVSYS_CHINTENCLR27 (*(RwReg *)0x4100E0FCUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET27 (*(RwReg *)0x4100E0FDUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG27 (*(RwReg *)0x4100E0FEUL) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS27 (*(RoReg *)0x4100E0FFUL) /**< \brief (EVSYS) Channel 27 Status */
+#define REG_EVSYS_CHANNEL28 (*(RwReg *)0x4100E100UL) /**< \brief (EVSYS) Channel 28 Control */
+#define REG_EVSYS_CHINTENCLR28 (*(RwReg *)0x4100E104UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET28 (*(RwReg *)0x4100E105UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG28 (*(RwReg *)0x4100E106UL) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS28 (*(RoReg *)0x4100E107UL) /**< \brief (EVSYS) Channel 28 Status */
+#define REG_EVSYS_CHANNEL29 (*(RwReg *)0x4100E108UL) /**< \brief (EVSYS) Channel 29 Control */
+#define REG_EVSYS_CHINTENCLR29 (*(RwReg *)0x4100E10CUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET29 (*(RwReg *)0x4100E10DUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG29 (*(RwReg *)0x4100E10EUL) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS29 (*(RoReg *)0x4100E10FUL) /**< \brief (EVSYS) Channel 29 Status */
+#define REG_EVSYS_CHANNEL30 (*(RwReg *)0x4100E110UL) /**< \brief (EVSYS) Channel 30 Control */
+#define REG_EVSYS_CHINTENCLR30 (*(RwReg *)0x4100E114UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET30 (*(RwReg *)0x4100E115UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG30 (*(RwReg *)0x4100E116UL) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS30 (*(RoReg *)0x4100E117UL) /**< \brief (EVSYS) Channel 30 Status */
+#define REG_EVSYS_CHANNEL31 (*(RwReg *)0x4100E118UL) /**< \brief (EVSYS) Channel 31 Control */
+#define REG_EVSYS_CHINTENCLR31 (*(RwReg *)0x4100E11CUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET31 (*(RwReg *)0x4100E11DUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG31 (*(RwReg *)0x4100E11EUL) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS31 (*(RoReg *)0x4100E11FUL) /**< \brief (EVSYS) Channel 31 Status */
+#define REG_EVSYS_USER0 (*(RwReg *)0x4100E120UL) /**< \brief (EVSYS) User Multiplexer 0 */
+#define REG_EVSYS_USER1 (*(RwReg *)0x4100E124UL) /**< \brief (EVSYS) User Multiplexer 1 */
+#define REG_EVSYS_USER2 (*(RwReg *)0x4100E128UL) /**< \brief (EVSYS) User Multiplexer 2 */
+#define REG_EVSYS_USER3 (*(RwReg *)0x4100E12CUL) /**< \brief (EVSYS) User Multiplexer 3 */
+#define REG_EVSYS_USER4 (*(RwReg *)0x4100E130UL) /**< \brief (EVSYS) User Multiplexer 4 */
+#define REG_EVSYS_USER5 (*(RwReg *)0x4100E134UL) /**< \brief (EVSYS) User Multiplexer 5 */
+#define REG_EVSYS_USER6 (*(RwReg *)0x4100E138UL) /**< \brief (EVSYS) User Multiplexer 6 */
+#define REG_EVSYS_USER7 (*(RwReg *)0x4100E13CUL) /**< \brief (EVSYS) User Multiplexer 7 */
+#define REG_EVSYS_USER8 (*(RwReg *)0x4100E140UL) /**< \brief (EVSYS) User Multiplexer 8 */
+#define REG_EVSYS_USER9 (*(RwReg *)0x4100E144UL) /**< \brief (EVSYS) User Multiplexer 9 */
+#define REG_EVSYS_USER10 (*(RwReg *)0x4100E148UL) /**< \brief (EVSYS) User Multiplexer 10 */
+#define REG_EVSYS_USER11 (*(RwReg *)0x4100E14CUL) /**< \brief (EVSYS) User Multiplexer 11 */
+#define REG_EVSYS_USER12 (*(RwReg *)0x4100E150UL) /**< \brief (EVSYS) User Multiplexer 12 */
+#define REG_EVSYS_USER13 (*(RwReg *)0x4100E154UL) /**< \brief (EVSYS) User Multiplexer 13 */
+#define REG_EVSYS_USER14 (*(RwReg *)0x4100E158UL) /**< \brief (EVSYS) User Multiplexer 14 */
+#define REG_EVSYS_USER15 (*(RwReg *)0x4100E15CUL) /**< \brief (EVSYS) User Multiplexer 15 */
+#define REG_EVSYS_USER16 (*(RwReg *)0x4100E160UL) /**< \brief (EVSYS) User Multiplexer 16 */
+#define REG_EVSYS_USER17 (*(RwReg *)0x4100E164UL) /**< \brief (EVSYS) User Multiplexer 17 */
+#define REG_EVSYS_USER18 (*(RwReg *)0x4100E168UL) /**< \brief (EVSYS) User Multiplexer 18 */
+#define REG_EVSYS_USER19 (*(RwReg *)0x4100E16CUL) /**< \brief (EVSYS) User Multiplexer 19 */
+#define REG_EVSYS_USER20 (*(RwReg *)0x4100E170UL) /**< \brief (EVSYS) User Multiplexer 20 */
+#define REG_EVSYS_USER21 (*(RwReg *)0x4100E174UL) /**< \brief (EVSYS) User Multiplexer 21 */
+#define REG_EVSYS_USER22 (*(RwReg *)0x4100E178UL) /**< \brief (EVSYS) User Multiplexer 22 */
+#define REG_EVSYS_USER23 (*(RwReg *)0x4100E17CUL) /**< \brief (EVSYS) User Multiplexer 23 */
+#define REG_EVSYS_USER24 (*(RwReg *)0x4100E180UL) /**< \brief (EVSYS) User Multiplexer 24 */
+#define REG_EVSYS_USER25 (*(RwReg *)0x4100E184UL) /**< \brief (EVSYS) User Multiplexer 25 */
+#define REG_EVSYS_USER26 (*(RwReg *)0x4100E188UL) /**< \brief (EVSYS) User Multiplexer 26 */
+#define REG_EVSYS_USER27 (*(RwReg *)0x4100E18CUL) /**< \brief (EVSYS) User Multiplexer 27 */
+#define REG_EVSYS_USER28 (*(RwReg *)0x4100E190UL) /**< \brief (EVSYS) User Multiplexer 28 */
+#define REG_EVSYS_USER29 (*(RwReg *)0x4100E194UL) /**< \brief (EVSYS) User Multiplexer 29 */
+#define REG_EVSYS_USER30 (*(RwReg *)0x4100E198UL) /**< \brief (EVSYS) User Multiplexer 30 */
+#define REG_EVSYS_USER31 (*(RwReg *)0x4100E19CUL) /**< \brief (EVSYS) User Multiplexer 31 */
+#define REG_EVSYS_USER32 (*(RwReg *)0x4100E1A0UL) /**< \brief (EVSYS) User Multiplexer 32 */
+#define REG_EVSYS_USER33 (*(RwReg *)0x4100E1A4UL) /**< \brief (EVSYS) User Multiplexer 33 */
+#define REG_EVSYS_USER34 (*(RwReg *)0x4100E1A8UL) /**< \brief (EVSYS) User Multiplexer 34 */
+#define REG_EVSYS_USER35 (*(RwReg *)0x4100E1ACUL) /**< \brief (EVSYS) User Multiplexer 35 */
+#define REG_EVSYS_USER36 (*(RwReg *)0x4100E1B0UL) /**< \brief (EVSYS) User Multiplexer 36 */
+#define REG_EVSYS_USER37 (*(RwReg *)0x4100E1B4UL) /**< \brief (EVSYS) User Multiplexer 37 */
+#define REG_EVSYS_USER38 (*(RwReg *)0x4100E1B8UL) /**< \brief (EVSYS) User Multiplexer 38 */
+#define REG_EVSYS_USER39 (*(RwReg *)0x4100E1BCUL) /**< \brief (EVSYS) User Multiplexer 39 */
+#define REG_EVSYS_USER40 (*(RwReg *)0x4100E1C0UL) /**< \brief (EVSYS) User Multiplexer 40 */
+#define REG_EVSYS_USER41 (*(RwReg *)0x4100E1C4UL) /**< \brief (EVSYS) User Multiplexer 41 */
+#define REG_EVSYS_USER42 (*(RwReg *)0x4100E1C8UL) /**< \brief (EVSYS) User Multiplexer 42 */
+#define REG_EVSYS_USER43 (*(RwReg *)0x4100E1CCUL) /**< \brief (EVSYS) User Multiplexer 43 */
+#define REG_EVSYS_USER44 (*(RwReg *)0x4100E1D0UL) /**< \brief (EVSYS) User Multiplexer 44 */
+#define REG_EVSYS_USER45 (*(RwReg *)0x4100E1D4UL) /**< \brief (EVSYS) User Multiplexer 45 */
+#define REG_EVSYS_USER46 (*(RwReg *)0x4100E1D8UL) /**< \brief (EVSYS) User Multiplexer 46 */
+#define REG_EVSYS_USER47 (*(RwReg *)0x4100E1DCUL) /**< \brief (EVSYS) User Multiplexer 47 */
+#define REG_EVSYS_USER48 (*(RwReg *)0x4100E1E0UL) /**< \brief (EVSYS) User Multiplexer 48 */
+#define REG_EVSYS_USER49 (*(RwReg *)0x4100E1E4UL) /**< \brief (EVSYS) User Multiplexer 49 */
+#define REG_EVSYS_USER50 (*(RwReg *)0x4100E1E8UL) /**< \brief (EVSYS) User Multiplexer 50 */
+#define REG_EVSYS_USER51 (*(RwReg *)0x4100E1ECUL) /**< \brief (EVSYS) User Multiplexer 51 */
+#define REG_EVSYS_USER52 (*(RwReg *)0x4100E1F0UL) /**< \brief (EVSYS) User Multiplexer 52 */
+#define REG_EVSYS_USER53 (*(RwReg *)0x4100E1F4UL) /**< \brief (EVSYS) User Multiplexer 53 */
+#define REG_EVSYS_USER54 (*(RwReg *)0x4100E1F8UL) /**< \brief (EVSYS) User Multiplexer 54 */
+#define REG_EVSYS_USER55 (*(RwReg *)0x4100E1FCUL) /**< \brief (EVSYS) User Multiplexer 55 */
+#define REG_EVSYS_USER56 (*(RwReg *)0x4100E200UL) /**< \brief (EVSYS) User Multiplexer 56 */
+#define REG_EVSYS_USER57 (*(RwReg *)0x4100E204UL) /**< \brief (EVSYS) User Multiplexer 57 */
+#define REG_EVSYS_USER58 (*(RwReg *)0x4100E208UL) /**< \brief (EVSYS) User Multiplexer 58 */
+#define REG_EVSYS_USER59 (*(RwReg *)0x4100E20CUL) /**< \brief (EVSYS) User Multiplexer 59 */
+#define REG_EVSYS_USER60 (*(RwReg *)0x4100E210UL) /**< \brief (EVSYS) User Multiplexer 60 */
+#define REG_EVSYS_USER61 (*(RwReg *)0x4100E214UL) /**< \brief (EVSYS) User Multiplexer 61 */
+#define REG_EVSYS_USER62 (*(RwReg *)0x4100E218UL) /**< \brief (EVSYS) User Multiplexer 62 */
+#define REG_EVSYS_USER63 (*(RwReg *)0x4100E21CUL) /**< \brief (EVSYS) User Multiplexer 63 */
+#define REG_EVSYS_USER64 (*(RwReg *)0x4100E220UL) /**< \brief (EVSYS) User Multiplexer 64 */
+#define REG_EVSYS_USER65 (*(RwReg *)0x4100E224UL) /**< \brief (EVSYS) User Multiplexer 65 */
+#define REG_EVSYS_USER66 (*(RwReg *)0x4100E228UL) /**< \brief (EVSYS) User Multiplexer 66 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_ASYNCHRONOUS_CHANNELS 0xFFFFF000 // Mask of Only Asynchronous Channels
+#define EVSYS_CHANNELS 32 // Total Number of Channels
+#define EVSYS_CHANNELS_BITS 5 // Number of bits to select Channel
+#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
+#define EVSYS_GCLK_ID_0 11
+#define EVSYS_GCLK_ID_1 12
+#define EVSYS_GCLK_ID_2 13
+#define EVSYS_GCLK_ID_3 14
+#define EVSYS_GCLK_ID_4 15
+#define EVSYS_GCLK_ID_5 16
+#define EVSYS_GCLK_ID_6 17
+#define EVSYS_GCLK_ID_7 18
+#define EVSYS_GCLK_ID_8 19
+#define EVSYS_GCLK_ID_9 20
+#define EVSYS_GCLK_ID_10 21
+#define EVSYS_GCLK_ID_11 22
+#define EVSYS_GCLK_ID_LSB 11
+#define EVSYS_GCLK_ID_MSB 22
+#define EVSYS_GCLK_ID_SIZE 12
+#define EVSYS_GENERATORS 119 // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
+#define EVSYS_SYNCH_NUM 12 // Number of Synchronous Channels
+#define EVSYS_SYNCH_NUM_BITS 4 // Number of bits to select Synchronous Channels
+#define EVSYS_USERS 67 // Total Number of Event Users
+#define EVSYS_USERS_BITS 7 // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_0 1
+#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_1 2
+#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3
+#define EVSYS_ID_GEN_RTC_PER_0 4
+#define EVSYS_ID_GEN_RTC_PER_1 5
+#define EVSYS_ID_GEN_RTC_PER_2 6
+#define EVSYS_ID_GEN_RTC_PER_3 7
+#define EVSYS_ID_GEN_RTC_PER_4 8
+#define EVSYS_ID_GEN_RTC_PER_5 9
+#define EVSYS_ID_GEN_RTC_PER_6 10
+#define EVSYS_ID_GEN_RTC_PER_7 11
+#define EVSYS_ID_GEN_RTC_CMP_0 12
+#define EVSYS_ID_GEN_RTC_CMP_1 13
+#define EVSYS_ID_GEN_RTC_CMP_2 14
+#define EVSYS_ID_GEN_RTC_CMP_3 15
+#define EVSYS_ID_GEN_RTC_TAMPER 16
+#define EVSYS_ID_GEN_RTC_OVF 17
+#define EVSYS_ID_GEN_EIC_EXTINT_0 18
+#define EVSYS_ID_GEN_EIC_EXTINT_1 19
+#define EVSYS_ID_GEN_EIC_EXTINT_2 20
+#define EVSYS_ID_GEN_EIC_EXTINT_3 21
+#define EVSYS_ID_GEN_EIC_EXTINT_4 22
+#define EVSYS_ID_GEN_EIC_EXTINT_5 23
+#define EVSYS_ID_GEN_EIC_EXTINT_6 24
+#define EVSYS_ID_GEN_EIC_EXTINT_7 25
+#define EVSYS_ID_GEN_EIC_EXTINT_8 26
+#define EVSYS_ID_GEN_EIC_EXTINT_9 27
+#define EVSYS_ID_GEN_EIC_EXTINT_10 28
+#define EVSYS_ID_GEN_EIC_EXTINT_11 29
+#define EVSYS_ID_GEN_EIC_EXTINT_12 30
+#define EVSYS_ID_GEN_EIC_EXTINT_13 31
+#define EVSYS_ID_GEN_EIC_EXTINT_14 32
+#define EVSYS_ID_GEN_EIC_EXTINT_15 33
+#define EVSYS_ID_GEN_DMAC_CH_0 34
+#define EVSYS_ID_GEN_DMAC_CH_1 35
+#define EVSYS_ID_GEN_DMAC_CH_2 36
+#define EVSYS_ID_GEN_DMAC_CH_3 37
+#define EVSYS_ID_GEN_PAC_ACCERR 38
+#define EVSYS_ID_GEN_TAL_BRK 39
+#define EVSYS_ID_GEN_TAL_IRQMON_0 40
+#define EVSYS_ID_GEN_TCC0_OVF 41
+#define EVSYS_ID_GEN_TCC0_TRG 42
+#define EVSYS_ID_GEN_TCC0_CNT 43
+#define EVSYS_ID_GEN_TCC0_MCX_0 44
+#define EVSYS_ID_GEN_TCC0_MCX_1 45
+#define EVSYS_ID_GEN_TCC0_MCX_2 46
+#define EVSYS_ID_GEN_TCC0_MCX_3 47
+#define EVSYS_ID_GEN_TCC0_MCX_4 48
+#define EVSYS_ID_GEN_TCC0_MCX_5 49
+#define EVSYS_ID_GEN_TCC1_OVF 50
+#define EVSYS_ID_GEN_TCC1_TRG 51
+#define EVSYS_ID_GEN_TCC1_CNT 52
+#define EVSYS_ID_GEN_TCC1_MCX_0 53
+#define EVSYS_ID_GEN_TCC1_MCX_1 54
+#define EVSYS_ID_GEN_TCC1_MCX_2 55
+#define EVSYS_ID_GEN_TCC1_MCX_3 56
+#define EVSYS_ID_GEN_TCC2_OVF 57
+#define EVSYS_ID_GEN_TCC2_TRG 58
+#define EVSYS_ID_GEN_TCC2_CNT 59
+#define EVSYS_ID_GEN_TCC2_MCX_0 60
+#define EVSYS_ID_GEN_TCC2_MCX_1 61
+#define EVSYS_ID_GEN_TCC2_MCX_2 62
+#define EVSYS_ID_GEN_TCC3_OVF 63
+#define EVSYS_ID_GEN_TCC3_TRG 64
+#define EVSYS_ID_GEN_TCC3_CNT 65
+#define EVSYS_ID_GEN_TCC3_MCX_0 66
+#define EVSYS_ID_GEN_TCC3_MCX_1 67
+#define EVSYS_ID_GEN_TCC4_OVF 68
+#define EVSYS_ID_GEN_TCC4_TRG 69
+#define EVSYS_ID_GEN_TCC4_CNT 70
+#define EVSYS_ID_GEN_TCC4_MCX_0 71
+#define EVSYS_ID_GEN_TCC4_MCX_1 72
+#define EVSYS_ID_GEN_TC0_OVF 73
+#define EVSYS_ID_GEN_TC0_MCX_0 74
+#define EVSYS_ID_GEN_TC0_MCX_1 75
+#define EVSYS_ID_GEN_TC1_OVF 76
+#define EVSYS_ID_GEN_TC1_MCX_0 77
+#define EVSYS_ID_GEN_TC1_MCX_1 78
+#define EVSYS_ID_GEN_TC2_OVF 79
+#define EVSYS_ID_GEN_TC2_MCX_0 80
+#define EVSYS_ID_GEN_TC2_MCX_1 81
+#define EVSYS_ID_GEN_TC3_OVF 82
+#define EVSYS_ID_GEN_TC3_MCX_0 83
+#define EVSYS_ID_GEN_TC3_MCX_1 84
+#define EVSYS_ID_GEN_TC4_OVF 85
+#define EVSYS_ID_GEN_TC4_MCX_0 86
+#define EVSYS_ID_GEN_TC4_MCX_1 87
+#define EVSYS_ID_GEN_TC5_OVF 88
+#define EVSYS_ID_GEN_TC5_MCX_0 89
+#define EVSYS_ID_GEN_TC5_MCX_1 90
+#define EVSYS_ID_GEN_TC6_OVF 91
+#define EVSYS_ID_GEN_TC6_MCX_0 92
+#define EVSYS_ID_GEN_TC6_MCX_1 93
+#define EVSYS_ID_GEN_TC7_OVF 94
+#define EVSYS_ID_GEN_TC7_MCX_0 95
+#define EVSYS_ID_GEN_TC7_MCX_1 96
+#define EVSYS_ID_GEN_PDEC_OVF 97
+#define EVSYS_ID_GEN_PDEC_ERR 98
+#define EVSYS_ID_GEN_PDEC_DIR 99
+#define EVSYS_ID_GEN_PDEC_VLC 100
+#define EVSYS_ID_GEN_PDEC_MCX_0 101
+#define EVSYS_ID_GEN_PDEC_MCX_1 102
+#define EVSYS_ID_GEN_ADC0_RESRDY 103
+#define EVSYS_ID_GEN_ADC0_WINMON 104
+#define EVSYS_ID_GEN_ADC1_RESRDY 105
+#define EVSYS_ID_GEN_ADC1_WINMON 106
+#define EVSYS_ID_GEN_AC_COMP_0 107
+#define EVSYS_ID_GEN_AC_COMP_1 108
+#define EVSYS_ID_GEN_AC_WIN_0 109
+#define EVSYS_ID_GEN_DAC_EMPTY_0 110
+#define EVSYS_ID_GEN_DAC_EMPTY_1 111
+#define EVSYS_ID_GEN_DAC_RESRDY_0 112
+#define EVSYS_ID_GEN_DAC_RESRDY_1 113
+#define EVSYS_ID_GEN_GMAC_TSU_CMP 114
+#define EVSYS_ID_GEN_TRNG_READY 115
+#define EVSYS_ID_GEN_CCL_LUTOUT_0 116
+#define EVSYS_ID_GEN_CCL_LUTOUT_1 117
+#define EVSYS_ID_GEN_CCL_LUTOUT_2 118
+#define EVSYS_ID_GEN_CCL_LUTOUT_3 119
+
+// USERS
+#define EVSYS_ID_USER_RTC_TAMPER 0
+#define EVSYS_ID_USER_PORT_EV_0 1
+#define EVSYS_ID_USER_PORT_EV_1 2
+#define EVSYS_ID_USER_PORT_EV_2 3
+#define EVSYS_ID_USER_PORT_EV_3 4
+#define EVSYS_ID_USER_DMAC_CH_0 5
+#define EVSYS_ID_USER_DMAC_CH_1 6
+#define EVSYS_ID_USER_DMAC_CH_2 7
+#define EVSYS_ID_USER_DMAC_CH_3 8
+#define EVSYS_ID_USER_DMAC_CH_4 9
+#define EVSYS_ID_USER_DMAC_CH_5 10
+#define EVSYS_ID_USER_DMAC_CH_6 11
+#define EVSYS_ID_USER_DMAC_CH_7 12
+#define EVSYS_ID_USER_TAL_BRK 13
+#define EVSYS_ID_USER_CM4_TRACE_START 14
+#define EVSYS_ID_USER_CM4_TRACE_STOP 15
+#define EVSYS_ID_USER_CM4_TRACE_TRIG 16
+#define EVSYS_ID_USER_TCC0_EV_0 17
+#define EVSYS_ID_USER_TCC0_EV_1 18
+#define EVSYS_ID_USER_TCC0_MC_0 19
+#define EVSYS_ID_USER_TCC0_MC_1 20
+#define EVSYS_ID_USER_TCC0_MC_2 21
+#define EVSYS_ID_USER_TCC0_MC_3 22
+#define EVSYS_ID_USER_TCC0_MC_4 23
+#define EVSYS_ID_USER_TCC0_MC_5 24
+#define EVSYS_ID_USER_TCC1_EV_0 25
+#define EVSYS_ID_USER_TCC1_EV_1 26
+#define EVSYS_ID_USER_TCC1_MC_0 27
+#define EVSYS_ID_USER_TCC1_MC_1 28
+#define EVSYS_ID_USER_TCC1_MC_2 29
+#define EVSYS_ID_USER_TCC1_MC_3 30
+#define EVSYS_ID_USER_TCC2_EV_0 31
+#define EVSYS_ID_USER_TCC2_EV_1 32
+#define EVSYS_ID_USER_TCC2_MC_0 33
+#define EVSYS_ID_USER_TCC2_MC_1 34
+#define EVSYS_ID_USER_TCC2_MC_2 35
+#define EVSYS_ID_USER_TCC3_EV_0 36
+#define EVSYS_ID_USER_TCC3_EV_1 37
+#define EVSYS_ID_USER_TCC3_MC_0 38
+#define EVSYS_ID_USER_TCC3_MC_1 39
+#define EVSYS_ID_USER_TCC4_EV_0 40
+#define EVSYS_ID_USER_TCC4_EV_1 41
+#define EVSYS_ID_USER_TCC4_MC_0 42
+#define EVSYS_ID_USER_TCC4_MC_1 43
+#define EVSYS_ID_USER_TC0_EVU 44
+#define EVSYS_ID_USER_TC1_EVU 45
+#define EVSYS_ID_USER_TC2_EVU 46
+#define EVSYS_ID_USER_TC3_EVU 47
+#define EVSYS_ID_USER_TC4_EVU 48
+#define EVSYS_ID_USER_TC5_EVU 49
+#define EVSYS_ID_USER_TC6_EVU 50
+#define EVSYS_ID_USER_TC7_EVU 51
+#define EVSYS_ID_USER_PDEC_EVU_0 52
+#define EVSYS_ID_USER_PDEC_EVU_1 53
+#define EVSYS_ID_USER_PDEC_EVU_2 54
+#define EVSYS_ID_USER_ADC0_START 55
+#define EVSYS_ID_USER_ADC0_SYNC 56
+#define EVSYS_ID_USER_ADC1_START 57
+#define EVSYS_ID_USER_ADC1_SYNC 58
+#define EVSYS_ID_USER_AC_SOC_0 59
+#define EVSYS_ID_USER_AC_SOC_1 60
+#define EVSYS_ID_USER_DAC_START_0 61
+#define EVSYS_ID_USER_DAC_START_1 62
+#define EVSYS_ID_USER_CCL_LUTIN_0 63
+#define EVSYS_ID_USER_CCL_LUTIN_1 64
+#define EVSYS_ID_USER_CCL_LUTIN_2 65
+#define EVSYS_ID_USER_CCL_LUTIN_3 66
+
+#endif /* _SAME54_EVSYS_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/freqm.h b/GPIO/ATSAME54/include/instance/freqm.h
new file mode 100644
index 0000000..379b401
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/freqm.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for FREQM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_FREQM_INSTANCE_
+#define _SAME54_FREQM_INSTANCE_
+
+/* ========== Register definition for FREQM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */
+#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */
+#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */
+#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */
+#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */
+#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */
+#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */
+#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */
+#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */
+#else
+#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */
+#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */
+#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */
+#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */
+#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */
+#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */
+#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */
+#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */
+#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for FREQM peripheral ========== */
+#define FREQM_GCLK_ID_MSR 5 // Index of measure generic clock
+
+#endif /* _SAME54_FREQM_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/gclk.h b/GPIO/ATSAME54/include/instance/gclk.h
new file mode 100644
index 0000000..bb1fa1f
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/gclk.h
@@ -0,0 +1,191 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_GCLK_INSTANCE_
+#define _SAME54_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */
+#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */
+#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */
+#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */
+#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */
+#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */
+#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */
+#define REG_GCLK_GENCTRL5 (0x40001C34) /**< \brief (GCLK) Generic Clock Generator Control 5 */
+#define REG_GCLK_GENCTRL6 (0x40001C38) /**< \brief (GCLK) Generic Clock Generator Control 6 */
+#define REG_GCLK_GENCTRL7 (0x40001C3C) /**< \brief (GCLK) Generic Clock Generator Control 7 */
+#define REG_GCLK_GENCTRL8 (0x40001C40) /**< \brief (GCLK) Generic Clock Generator Control 8 */
+#define REG_GCLK_GENCTRL9 (0x40001C44) /**< \brief (GCLK) Generic Clock Generator Control 9 */
+#define REG_GCLK_GENCTRL10 (0x40001C48) /**< \brief (GCLK) Generic Clock Generator Control 10 */
+#define REG_GCLK_GENCTRL11 (0x40001C4C) /**< \brief (GCLK) Generic Clock Generator Control 11 */
+#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */
+#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */
+#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */
+#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */
+#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */
+#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */
+#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */
+#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */
+#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */
+#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */
+#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */
+#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */
+#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */
+#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */
+#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */
+#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */
+#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */
+#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */
+#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */
+#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */
+#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */
+#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */
+#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */
+#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */
+#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */
+#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */
+#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */
+#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */
+#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */
+#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */
+#define REG_GCLK_PCHCTRL30 (0x40001CF8) /**< \brief (GCLK) Peripheral Clock Control 30 */
+#define REG_GCLK_PCHCTRL31 (0x40001CFC) /**< \brief (GCLK) Peripheral Clock Control 31 */
+#define REG_GCLK_PCHCTRL32 (0x40001D00) /**< \brief (GCLK) Peripheral Clock Control 32 */
+#define REG_GCLK_PCHCTRL33 (0x40001D04) /**< \brief (GCLK) Peripheral Clock Control 33 */
+#define REG_GCLK_PCHCTRL34 (0x40001D08) /**< \brief (GCLK) Peripheral Clock Control 34 */
+#define REG_GCLK_PCHCTRL35 (0x40001D0C) /**< \brief (GCLK) Peripheral Clock Control 35 */
+#define REG_GCLK_PCHCTRL36 (0x40001D10) /**< \brief (GCLK) Peripheral Clock Control 36 */
+#define REG_GCLK_PCHCTRL37 (0x40001D14) /**< \brief (GCLK) Peripheral Clock Control 37 */
+#define REG_GCLK_PCHCTRL38 (0x40001D18) /**< \brief (GCLK) Peripheral Clock Control 38 */
+#define REG_GCLK_PCHCTRL39 (0x40001D1C) /**< \brief (GCLK) Peripheral Clock Control 39 */
+#define REG_GCLK_PCHCTRL40 (0x40001D20) /**< \brief (GCLK) Peripheral Clock Control 40 */
+#define REG_GCLK_PCHCTRL41 (0x40001D24) /**< \brief (GCLK) Peripheral Clock Control 41 */
+#define REG_GCLK_PCHCTRL42 (0x40001D28) /**< \brief (GCLK) Peripheral Clock Control 42 */
+#define REG_GCLK_PCHCTRL43 (0x40001D2C) /**< \brief (GCLK) Peripheral Clock Control 43 */
+#define REG_GCLK_PCHCTRL44 (0x40001D30) /**< \brief (GCLK) Peripheral Clock Control 44 */
+#define REG_GCLK_PCHCTRL45 (0x40001D34) /**< \brief (GCLK) Peripheral Clock Control 45 */
+#define REG_GCLK_PCHCTRL46 (0x40001D38) /**< \brief (GCLK) Peripheral Clock Control 46 */
+#define REG_GCLK_PCHCTRL47 (0x40001D3C) /**< \brief (GCLK) Peripheral Clock Control 47 */
+#else
+#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */
+#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */
+#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */
+#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */
+#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */
+#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */
+#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */
+#define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001C34UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */
+#define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001C38UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */
+#define REG_GCLK_GENCTRL7 (*(RwReg *)0x40001C3CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */
+#define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001C40UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */
+#define REG_GCLK_GENCTRL9 (*(RwReg *)0x40001C44UL) /**< \brief (GCLK) Generic Clock Generator Control 9 */
+#define REG_GCLK_GENCTRL10 (*(RwReg *)0x40001C48UL) /**< \brief (GCLK) Generic Clock Generator Control 10 */
+#define REG_GCLK_GENCTRL11 (*(RwReg *)0x40001C4CUL) /**< \brief (GCLK) Generic Clock Generator Control 11 */
+#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */
+#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */
+#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */
+#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */
+#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */
+#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */
+#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */
+#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */
+#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */
+#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */
+#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */
+#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */
+#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */
+#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */
+#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */
+#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */
+#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */
+#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */
+#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */
+#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */
+#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */
+#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */
+#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */
+#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */
+#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */
+#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */
+#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */
+#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */
+#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */
+#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */
+#define REG_GCLK_PCHCTRL30 (*(RwReg *)0x40001CF8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */
+#define REG_GCLK_PCHCTRL31 (*(RwReg *)0x40001CFCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */
+#define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001D00UL) /**< \brief (GCLK) Peripheral Clock Control 32 */
+#define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001D04UL) /**< \brief (GCLK) Peripheral Clock Control 33 */
+#define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001D08UL) /**< \brief (GCLK) Peripheral Clock Control 34 */
+#define REG_GCLK_PCHCTRL35 (*(RwReg *)0x40001D0CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */
+#define REG_GCLK_PCHCTRL36 (*(RwReg *)0x40001D10UL) /**< \brief (GCLK) Peripheral Clock Control 36 */
+#define REG_GCLK_PCHCTRL37 (*(RwReg *)0x40001D14UL) /**< \brief (GCLK) Peripheral Clock Control 37 */
+#define REG_GCLK_PCHCTRL38 (*(RwReg *)0x40001D18UL) /**< \brief (GCLK) Peripheral Clock Control 38 */
+#define REG_GCLK_PCHCTRL39 (*(RwReg *)0x40001D1CUL) /**< \brief (GCLK) Peripheral Clock Control 39 */
+#define REG_GCLK_PCHCTRL40 (*(RwReg *)0x40001D20UL) /**< \brief (GCLK) Peripheral Clock Control 40 */
+#define REG_GCLK_PCHCTRL41 (*(RwReg *)0x40001D24UL) /**< \brief (GCLK) Peripheral Clock Control 41 */
+#define REG_GCLK_PCHCTRL42 (*(RwReg *)0x40001D28UL) /**< \brief (GCLK) Peripheral Clock Control 42 */
+#define REG_GCLK_PCHCTRL43 (*(RwReg *)0x40001D2CUL) /**< \brief (GCLK) Peripheral Clock Control 43 */
+#define REG_GCLK_PCHCTRL44 (*(RwReg *)0x40001D30UL) /**< \brief (GCLK) Peripheral Clock Control 44 */
+#define REG_GCLK_PCHCTRL45 (*(RwReg *)0x40001D34UL) /**< \brief (GCLK) Peripheral Clock Control 45 */
+#define REG_GCLK_PCHCTRL46 (*(RwReg *)0x40001D38UL) /**< \brief (GCLK) Peripheral Clock Control 46 */
+#define REG_GCLK_PCHCTRL47 (*(RwReg *)0x40001D3CUL) /**< \brief (GCLK) Peripheral Clock Control 47 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENCTRL0_RESETVALUE 106 // Default specific reset value for generator 0
+#define GCLK_GENDIV_BITS 16
+#define GCLK_GEN_BITS 4
+#define GCLK_GEN_NUM 12 // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB 11 // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
+#define GCLK_IO_NUM 8 // Number of Generic Clock I/Os
+#define GCLK_NUM 48 // Number of Generic Clock Users
+#define GCLK_SOURCE_BITS 4
+#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
+#define GCLK_SOURCE_XOSC0 0 // Crystal Oscillator 0
+#define GCLK_SOURCE_XOSC 0 // Alias to GCLK_SOURCE_XOSC0
+#define GCLK_SOURCE_XOSC1 1 // Crystal Oscillator 1
+#define GCLK_SOURCE_GCLKIN 2 // Input Pin of Corresponding GCLK Generator
+#define GCLK_SOURCE_GCLKGEN1 3 // GCLK Generator 1 output
+#define GCLK_SOURCE_OSCULP32K 4 // Ultra-low-power 32kHz Oscillator
+#define GCLK_SOURCE_XOSC32K 5 // 32kHz Crystal Oscillator
+#define GCLK_SOURCE_DFLL 6 // Digital FLL
+#define GCLK_SOURCE_DFLL48M 6 // Alias to GCLK_SOURCE_DFLL
+#define GCLK_SOURCE_OSC16M 6 // Alias to GCLK_SOURCE_DFLL
+#define GCLK_SOURCE_OSC48M 6 // Alias to GCLK_SOURCE_DFLL
+#define GCLK_SOURCE_DPLL0 7 // Digital PLL 0
+#define GCLK_SOURCE_FDPLL 7 // Alias to GCLK_SOURCE_DPLL0
+#define GCLK_SOURCE_FDPLL0 7 // Alias to GCLK_SOURCE_DPLL0
+#define GCLK_SOURCE_DPLL1 8 // Digital PLL 1
+#define GCLK_SOURCE_FDPLL1 8 // Alias to GCLK_SOURCE_DPLL1
+#define GCLK_GEN_DIV_BITS { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }
+
+#endif /* _SAME54_GCLK_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/gmac.h b/GPIO/ATSAME54/include/instance/gmac.h
new file mode 100644
index 0000000..8e72493
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/gmac.h
@@ -0,0 +1,263 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GMAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_GMAC_INSTANCE_
+#define _SAME54_GMAC_INSTANCE_
+
+/* ========== Register definition for GMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GMAC_NCR (0x42000800) /**< \brief (GMAC) Network Control Register */
+#define REG_GMAC_NCFGR (0x42000804) /**< \brief (GMAC) Network Configuration Register */
+#define REG_GMAC_NSR (0x42000808) /**< \brief (GMAC) Network Status Register */
+#define REG_GMAC_UR (0x4200080C) /**< \brief (GMAC) User Register */
+#define REG_GMAC_DCFGR (0x42000810) /**< \brief (GMAC) DMA Configuration Register */
+#define REG_GMAC_TSR (0x42000814) /**< \brief (GMAC) Transmit Status Register */
+#define REG_GMAC_RBQB (0x42000818) /**< \brief (GMAC) Receive Buffer Queue Base Address */
+#define REG_GMAC_TBQB (0x4200081C) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
+#define REG_GMAC_RSR (0x42000820) /**< \brief (GMAC) Receive Status Register */
+#define REG_GMAC_ISR (0x42000824) /**< \brief (GMAC) Interrupt Status Register */
+#define REG_GMAC_IER (0x42000828) /**< \brief (GMAC) Interrupt Enable Register */
+#define REG_GMAC_IDR (0x4200082C) /**< \brief (GMAC) Interrupt Disable Register */
+#define REG_GMAC_IMR (0x42000830) /**< \brief (GMAC) Interrupt Mask Register */
+#define REG_GMAC_MAN (0x42000834) /**< \brief (GMAC) PHY Maintenance Register */
+#define REG_GMAC_RPQ (0x42000838) /**< \brief (GMAC) Received Pause Quantum Register */
+#define REG_GMAC_TPQ (0x4200083C) /**< \brief (GMAC) Transmit Pause Quantum Register */
+#define REG_GMAC_TPSF (0x42000840) /**< \brief (GMAC) TX partial store and forward Register */
+#define REG_GMAC_RPSF (0x42000844) /**< \brief (GMAC) RX partial store and forward Register */
+#define REG_GMAC_RJFML (0x42000848) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
+#define REG_GMAC_HRB (0x42000880) /**< \brief (GMAC) Hash Register Bottom [31:0] */
+#define REG_GMAC_HRT (0x42000884) /**< \brief (GMAC) Hash Register Top [63:32] */
+#define REG_GMAC_SAB0 (0x42000888) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 0 */
+#define REG_GMAC_SAT0 (0x4200088C) /**< \brief (GMAC) Specific Address Top [47:32] Register 0 */
+#define REG_GMAC_SAB1 (0x42000890) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 1 */
+#define REG_GMAC_SAT1 (0x42000894) /**< \brief (GMAC) Specific Address Top [47:32] Register 1 */
+#define REG_GMAC_SAB2 (0x42000898) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 2 */
+#define REG_GMAC_SAT2 (0x4200089C) /**< \brief (GMAC) Specific Address Top [47:32] Register 2 */
+#define REG_GMAC_SAB3 (0x420008A0) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 3 */
+#define REG_GMAC_SAT3 (0x420008A4) /**< \brief (GMAC) Specific Address Top [47:32] Register 3 */
+#define REG_GMAC_TIDM0 (0x420008A8) /**< \brief (GMAC) Type ID Match Register 0 */
+#define REG_GMAC_TIDM1 (0x420008AC) /**< \brief (GMAC) Type ID Match Register 1 */
+#define REG_GMAC_TIDM2 (0x420008B0) /**< \brief (GMAC) Type ID Match Register 2 */
+#define REG_GMAC_TIDM3 (0x420008B4) /**< \brief (GMAC) Type ID Match Register 3 */
+#define REG_GMAC_WOL (0x420008B8) /**< \brief (GMAC) Wake on LAN */
+#define REG_GMAC_IPGS (0x420008BC) /**< \brief (GMAC) IPG Stretch Register */
+#define REG_GMAC_SVLAN (0x420008C0) /**< \brief (GMAC) Stacked VLAN Register */
+#define REG_GMAC_TPFCP (0x420008C4) /**< \brief (GMAC) Transmit PFC Pause Register */
+#define REG_GMAC_SAMB1 (0x420008C8) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
+#define REG_GMAC_SAMT1 (0x420008CC) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
+#define REG_GMAC_NSC (0x420008DC) /**< \brief (GMAC) Tsu timer comparison nanoseconds Register */
+#define REG_GMAC_SCL (0x420008E0) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_SCH (0x420008E4) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_EFTSH (0x420008E8) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_EFRSH (0x420008EC) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
+#define REG_GMAC_PEFTSH (0x420008F0) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_PEFRSH (0x420008F4) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
+#define REG_GMAC_OTLO (0x42000900) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
+#define REG_GMAC_OTHI (0x42000904) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
+#define REG_GMAC_FT (0x42000908) /**< \brief (GMAC) Frames Transmitted Register */
+#define REG_GMAC_BCFT (0x4200090C) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
+#define REG_GMAC_MFT (0x42000910) /**< \brief (GMAC) Multicast Frames Transmitted Register */
+#define REG_GMAC_PFT (0x42000914) /**< \brief (GMAC) Pause Frames Transmitted Register */
+#define REG_GMAC_BFT64 (0x42000918) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT127 (0x4200091C) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT255 (0x42000920) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT511 (0x42000924) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1023 (0x42000928) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1518 (0x4200092C) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_GTBFT1518 (0x42000930) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_TUR (0x42000934) /**< \brief (GMAC) Transmit Underruns Register */
+#define REG_GMAC_SCF (0x42000938) /**< \brief (GMAC) Single Collision Frames Register */
+#define REG_GMAC_MCF (0x4200093C) /**< \brief (GMAC) Multiple Collision Frames Register */
+#define REG_GMAC_EC (0x42000940) /**< \brief (GMAC) Excessive Collisions Register */
+#define REG_GMAC_LC (0x42000944) /**< \brief (GMAC) Late Collisions Register */
+#define REG_GMAC_DTF (0x42000948) /**< \brief (GMAC) Deferred Transmission Frames Register */
+#define REG_GMAC_CSE (0x4200094C) /**< \brief (GMAC) Carrier Sense Errors Register */
+#define REG_GMAC_ORLO (0x42000950) /**< \brief (GMAC) Octets Received [31:0] Received */
+#define REG_GMAC_ORHI (0x42000954) /**< \brief (GMAC) Octets Received [47:32] Received */
+#define REG_GMAC_FR (0x42000958) /**< \brief (GMAC) Frames Received Register */
+#define REG_GMAC_BCFR (0x4200095C) /**< \brief (GMAC) Broadcast Frames Received Register */
+#define REG_GMAC_MFR (0x42000960) /**< \brief (GMAC) Multicast Frames Received Register */
+#define REG_GMAC_PFR (0x42000964) /**< \brief (GMAC) Pause Frames Received Register */
+#define REG_GMAC_BFR64 (0x42000968) /**< \brief (GMAC) 64 Byte Frames Received Register */
+#define REG_GMAC_TBFR127 (0x4200096C) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
+#define REG_GMAC_TBFR255 (0x42000970) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
+#define REG_GMAC_TBFR511 (0x42000974) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
+#define REG_GMAC_TBFR1023 (0x42000978) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
+#define REG_GMAC_TBFR1518 (0x4200097C) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
+#define REG_GMAC_TMXBFR (0x42000980) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
+#define REG_GMAC_UFR (0x42000984) /**< \brief (GMAC) Undersize Frames Received Register */
+#define REG_GMAC_OFR (0x42000988) /**< \brief (GMAC) Oversize Frames Received Register */
+#define REG_GMAC_JR (0x4200098C) /**< \brief (GMAC) Jabbers Received Register */
+#define REG_GMAC_FCSE (0x42000990) /**< \brief (GMAC) Frame Check Sequence Errors Register */
+#define REG_GMAC_LFFE (0x42000994) /**< \brief (GMAC) Length Field Frame Errors Register */
+#define REG_GMAC_RSE (0x42000998) /**< \brief (GMAC) Receive Symbol Errors Register */
+#define REG_GMAC_AE (0x4200099C) /**< \brief (GMAC) Alignment Errors Register */
+#define REG_GMAC_RRE (0x420009A0) /**< \brief (GMAC) Receive Resource Errors Register */
+#define REG_GMAC_ROE (0x420009A4) /**< \brief (GMAC) Receive Overrun Register */
+#define REG_GMAC_IHCE (0x420009A8) /**< \brief (GMAC) IP Header Checksum Errors Register */
+#define REG_GMAC_TCE (0x420009AC) /**< \brief (GMAC) TCP Checksum Errors Register */
+#define REG_GMAC_UCE (0x420009B0) /**< \brief (GMAC) UDP Checksum Errors Register */
+#define REG_GMAC_TISUBN (0x420009BC) /**< \brief (GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define REG_GMAC_TSH (0x420009C0) /**< \brief (GMAC) 1588 Timer Seconds High [15:0] Register */
+#define REG_GMAC_TSSSL (0x420009C8) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define REG_GMAC_TSSN (0x420009CC) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
+#define REG_GMAC_TSL (0x420009D0) /**< \brief (GMAC) 1588 Timer Seconds [31:0] Register */
+#define REG_GMAC_TN (0x420009D4) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
+#define REG_GMAC_TA (0x420009D8) /**< \brief (GMAC) 1588 Timer Adjust Register */
+#define REG_GMAC_TI (0x420009DC) /**< \brief (GMAC) 1588 Timer Increment Register */
+#define REG_GMAC_EFTSL (0x420009E0) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_EFTN (0x420009E4) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_EFRSL (0x420009E8) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
+#define REG_GMAC_EFRN (0x420009EC) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
+#define REG_GMAC_PEFTSL (0x420009F0) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_PEFTN (0x420009F4) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_PEFRSL (0x420009F8) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
+#define REG_GMAC_PEFRN (0x420009FC) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
+#define REG_GMAC_RLPITR (0x42000A70) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_RLPITI (0x42000A74) /**< \brief (GMAC) Receive LPI Time Register */
+#define REG_GMAC_TLPITR (0x42000A78) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_TLPITI (0x42000A7C) /**< \brief (GMAC) Receive LPI Time Register */
+#else
+#define REG_GMAC_NCR (*(RwReg *)0x42000800UL) /**< \brief (GMAC) Network Control Register */
+#define REG_GMAC_NCFGR (*(RwReg *)0x42000804UL) /**< \brief (GMAC) Network Configuration Register */
+#define REG_GMAC_NSR (*(RoReg *)0x42000808UL) /**< \brief (GMAC) Network Status Register */
+#define REG_GMAC_UR (*(RwReg *)0x4200080CUL) /**< \brief (GMAC) User Register */
+#define REG_GMAC_DCFGR (*(RwReg *)0x42000810UL) /**< \brief (GMAC) DMA Configuration Register */
+#define REG_GMAC_TSR (*(RwReg *)0x42000814UL) /**< \brief (GMAC) Transmit Status Register */
+#define REG_GMAC_RBQB (*(RwReg *)0x42000818UL) /**< \brief (GMAC) Receive Buffer Queue Base Address */
+#define REG_GMAC_TBQB (*(RwReg *)0x4200081CUL) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
+#define REG_GMAC_RSR (*(RwReg *)0x42000820UL) /**< \brief (GMAC) Receive Status Register */
+#define REG_GMAC_ISR (*(RwReg *)0x42000824UL) /**< \brief (GMAC) Interrupt Status Register */
+#define REG_GMAC_IER (*(WoReg *)0x42000828UL) /**< \brief (GMAC) Interrupt Enable Register */
+#define REG_GMAC_IDR (*(WoReg *)0x4200082CUL) /**< \brief (GMAC) Interrupt Disable Register */
+#define REG_GMAC_IMR (*(RoReg *)0x42000830UL) /**< \brief (GMAC) Interrupt Mask Register */
+#define REG_GMAC_MAN (*(RwReg *)0x42000834UL) /**< \brief (GMAC) PHY Maintenance Register */
+#define REG_GMAC_RPQ (*(RoReg *)0x42000838UL) /**< \brief (GMAC) Received Pause Quantum Register */
+#define REG_GMAC_TPQ (*(RwReg *)0x4200083CUL) /**< \brief (GMAC) Transmit Pause Quantum Register */
+#define REG_GMAC_TPSF (*(RwReg *)0x42000840UL) /**< \brief (GMAC) TX partial store and forward Register */
+#define REG_GMAC_RPSF (*(RwReg *)0x42000844UL) /**< \brief (GMAC) RX partial store and forward Register */
+#define REG_GMAC_RJFML (*(RwReg *)0x42000848UL) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
+#define REG_GMAC_HRB (*(RwReg *)0x42000880UL) /**< \brief (GMAC) Hash Register Bottom [31:0] */
+#define REG_GMAC_HRT (*(RwReg *)0x42000884UL) /**< \brief (GMAC) Hash Register Top [63:32] */
+#define REG_GMAC_SAB0 (*(RwReg *)0x42000888UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 0 */
+#define REG_GMAC_SAT0 (*(RwReg *)0x4200088CUL) /**< \brief (GMAC) Specific Address Top [47:32] Register 0 */
+#define REG_GMAC_SAB1 (*(RwReg *)0x42000890UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 1 */
+#define REG_GMAC_SAT1 (*(RwReg *)0x42000894UL) /**< \brief (GMAC) Specific Address Top [47:32] Register 1 */
+#define REG_GMAC_SAB2 (*(RwReg *)0x42000898UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 2 */
+#define REG_GMAC_SAT2 (*(RwReg *)0x4200089CUL) /**< \brief (GMAC) Specific Address Top [47:32] Register 2 */
+#define REG_GMAC_SAB3 (*(RwReg *)0x420008A0UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 3 */
+#define REG_GMAC_SAT3 (*(RwReg *)0x420008A4UL) /**< \brief (GMAC) Specific Address Top [47:32] Register 3 */
+#define REG_GMAC_TIDM0 (*(RwReg *)0x420008A8UL) /**< \brief (GMAC) Type ID Match Register 0 */
+#define REG_GMAC_TIDM1 (*(RwReg *)0x420008ACUL) /**< \brief (GMAC) Type ID Match Register 1 */
+#define REG_GMAC_TIDM2 (*(RwReg *)0x420008B0UL) /**< \brief (GMAC) Type ID Match Register 2 */
+#define REG_GMAC_TIDM3 (*(RwReg *)0x420008B4UL) /**< \brief (GMAC) Type ID Match Register 3 */
+#define REG_GMAC_WOL (*(RwReg *)0x420008B8UL) /**< \brief (GMAC) Wake on LAN */
+#define REG_GMAC_IPGS (*(RwReg *)0x420008BCUL) /**< \brief (GMAC) IPG Stretch Register */
+#define REG_GMAC_SVLAN (*(RwReg *)0x420008C0UL) /**< \brief (GMAC) Stacked VLAN Register */
+#define REG_GMAC_TPFCP (*(RwReg *)0x420008C4UL) /**< \brief (GMAC) Transmit PFC Pause Register */
+#define REG_GMAC_SAMB1 (*(RwReg *)0x420008C8UL) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
+#define REG_GMAC_SAMT1 (*(RwReg *)0x420008CCUL) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
+#define REG_GMAC_NSC (*(RwReg *)0x420008DCUL) /**< \brief (GMAC) Tsu timer comparison nanoseconds Register */
+#define REG_GMAC_SCL (*(RwReg *)0x420008E0UL) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_SCH (*(RwReg *)0x420008E4UL) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_EFTSH (*(RoReg *)0x420008E8UL) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_EFRSH (*(RoReg *)0x420008ECUL) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
+#define REG_GMAC_PEFTSH (*(RoReg *)0x420008F0UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_PEFRSH (*(RoReg *)0x420008F4UL) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
+#define REG_GMAC_OTLO (*(RoReg *)0x42000900UL) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
+#define REG_GMAC_OTHI (*(RoReg *)0x42000904UL) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
+#define REG_GMAC_FT (*(RoReg *)0x42000908UL) /**< \brief (GMAC) Frames Transmitted Register */
+#define REG_GMAC_BCFT (*(RoReg *)0x4200090CUL) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
+#define REG_GMAC_MFT (*(RoReg *)0x42000910UL) /**< \brief (GMAC) Multicast Frames Transmitted Register */
+#define REG_GMAC_PFT (*(RoReg *)0x42000914UL) /**< \brief (GMAC) Pause Frames Transmitted Register */
+#define REG_GMAC_BFT64 (*(RoReg *)0x42000918UL) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT127 (*(RoReg *)0x4200091CUL) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT255 (*(RoReg *)0x42000920UL) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT511 (*(RoReg *)0x42000924UL) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1023 (*(RoReg *)0x42000928UL) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1518 (*(RoReg *)0x4200092CUL) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_GTBFT1518 (*(RoReg *)0x42000930UL) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_TUR (*(RoReg *)0x42000934UL) /**< \brief (GMAC) Transmit Underruns Register */
+#define REG_GMAC_SCF (*(RoReg *)0x42000938UL) /**< \brief (GMAC) Single Collision Frames Register */
+#define REG_GMAC_MCF (*(RoReg *)0x4200093CUL) /**< \brief (GMAC) Multiple Collision Frames Register */
+#define REG_GMAC_EC (*(RoReg *)0x42000940UL) /**< \brief (GMAC) Excessive Collisions Register */
+#define REG_GMAC_LC (*(RoReg *)0x42000944UL) /**< \brief (GMAC) Late Collisions Register */
+#define REG_GMAC_DTF (*(RoReg *)0x42000948UL) /**< \brief (GMAC) Deferred Transmission Frames Register */
+#define REG_GMAC_CSE (*(RoReg *)0x4200094CUL) /**< \brief (GMAC) Carrier Sense Errors Register */
+#define REG_GMAC_ORLO (*(RoReg *)0x42000950UL) /**< \brief (GMAC) Octets Received [31:0] Received */
+#define REG_GMAC_ORHI (*(RoReg *)0x42000954UL) /**< \brief (GMAC) Octets Received [47:32] Received */
+#define REG_GMAC_FR (*(RoReg *)0x42000958UL) /**< \brief (GMAC) Frames Received Register */
+#define REG_GMAC_BCFR (*(RoReg *)0x4200095CUL) /**< \brief (GMAC) Broadcast Frames Received Register */
+#define REG_GMAC_MFR (*(RoReg *)0x42000960UL) /**< \brief (GMAC) Multicast Frames Received Register */
+#define REG_GMAC_PFR (*(RoReg *)0x42000964UL) /**< \brief (GMAC) Pause Frames Received Register */
+#define REG_GMAC_BFR64 (*(RoReg *)0x42000968UL) /**< \brief (GMAC) 64 Byte Frames Received Register */
+#define REG_GMAC_TBFR127 (*(RoReg *)0x4200096CUL) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
+#define REG_GMAC_TBFR255 (*(RoReg *)0x42000970UL) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
+#define REG_GMAC_TBFR511 (*(RoReg *)0x42000974UL) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
+#define REG_GMAC_TBFR1023 (*(RoReg *)0x42000978UL) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
+#define REG_GMAC_TBFR1518 (*(RoReg *)0x4200097CUL) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
+#define REG_GMAC_TMXBFR (*(RoReg *)0x42000980UL) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
+#define REG_GMAC_UFR (*(RoReg *)0x42000984UL) /**< \brief (GMAC) Undersize Frames Received Register */
+#define REG_GMAC_OFR (*(RoReg *)0x42000988UL) /**< \brief (GMAC) Oversize Frames Received Register */
+#define REG_GMAC_JR (*(RoReg *)0x4200098CUL) /**< \brief (GMAC) Jabbers Received Register */
+#define REG_GMAC_FCSE (*(RoReg *)0x42000990UL) /**< \brief (GMAC) Frame Check Sequence Errors Register */
+#define REG_GMAC_LFFE (*(RoReg *)0x42000994UL) /**< \brief (GMAC) Length Field Frame Errors Register */
+#define REG_GMAC_RSE (*(RoReg *)0x42000998UL) /**< \brief (GMAC) Receive Symbol Errors Register */
+#define REG_GMAC_AE (*(RoReg *)0x4200099CUL) /**< \brief (GMAC) Alignment Errors Register */
+#define REG_GMAC_RRE (*(RoReg *)0x420009A0UL) /**< \brief (GMAC) Receive Resource Errors Register */
+#define REG_GMAC_ROE (*(RoReg *)0x420009A4UL) /**< \brief (GMAC) Receive Overrun Register */
+#define REG_GMAC_IHCE (*(RoReg *)0x420009A8UL) /**< \brief (GMAC) IP Header Checksum Errors Register */
+#define REG_GMAC_TCE (*(RoReg *)0x420009ACUL) /**< \brief (GMAC) TCP Checksum Errors Register */
+#define REG_GMAC_UCE (*(RoReg *)0x420009B0UL) /**< \brief (GMAC) UDP Checksum Errors Register */
+#define REG_GMAC_TISUBN (*(RwReg *)0x420009BCUL) /**< \brief (GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define REG_GMAC_TSH (*(RwReg *)0x420009C0UL) /**< \brief (GMAC) 1588 Timer Seconds High [15:0] Register */
+#define REG_GMAC_TSSSL (*(RwReg *)0x420009C8UL) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define REG_GMAC_TSSN (*(RwReg *)0x420009CCUL) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
+#define REG_GMAC_TSL (*(RwReg *)0x420009D0UL) /**< \brief (GMAC) 1588 Timer Seconds [31:0] Register */
+#define REG_GMAC_TN (*(RwReg *)0x420009D4UL) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
+#define REG_GMAC_TA (*(WoReg *)0x420009D8UL) /**< \brief (GMAC) 1588 Timer Adjust Register */
+#define REG_GMAC_TI (*(RwReg *)0x420009DCUL) /**< \brief (GMAC) 1588 Timer Increment Register */
+#define REG_GMAC_EFTSL (*(RoReg *)0x420009E0UL) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_EFTN (*(RoReg *)0x420009E4UL) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_EFRSL (*(RoReg *)0x420009E8UL) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
+#define REG_GMAC_EFRN (*(RoReg *)0x420009ECUL) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
+#define REG_GMAC_PEFTSL (*(RoReg *)0x420009F0UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_PEFTN (*(RoReg *)0x420009F4UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_PEFRSL (*(RoReg *)0x420009F8UL) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
+#define REG_GMAC_PEFRN (*(RoReg *)0x420009FCUL) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
+#define REG_GMAC_RLPITR (*(RoReg *)0x42000A70UL) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_RLPITI (*(RoReg *)0x42000A74UL) /**< \brief (GMAC) Receive LPI Time Register */
+#define REG_GMAC_TLPITR (*(RoReg *)0x42000A78UL) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_TLPITI (*(RoReg *)0x42000A7CUL) /**< \brief (GMAC) Receive LPI Time Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GMAC peripheral ========== */
+#define GMAC_CLK_AHB_ID 14 // Index of AHB clock
+
+#endif /* _SAME54_GMAC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/hmatrix.h b/GPIO/ATSAME54/include/instance/hmatrix.h
new file mode 100644
index 0000000..e97599c
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/hmatrix.h
@@ -0,0 +1,133 @@
+/**
+ * \file
+ *
+ * \brief Instance description for HMATRIX
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_HMATRIX_INSTANCE_
+#define _SAME54_HMATRIX_INSTANCE_
+
+/* ========== Register definition for HMATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HMATRIX_PRAS0 (0x4100C080) /**< \brief (HMATRIX) Priority A for Slave 0 */
+#define REG_HMATRIX_PRBS0 (0x4100C084) /**< \brief (HMATRIX) Priority B for Slave 0 */
+#define REG_HMATRIX_PRAS1 (0x4100C088) /**< \brief (HMATRIX) Priority A for Slave 1 */
+#define REG_HMATRIX_PRBS1 (0x4100C08C) /**< \brief (HMATRIX) Priority B for Slave 1 */
+#define REG_HMATRIX_PRAS2 (0x4100C090) /**< \brief (HMATRIX) Priority A for Slave 2 */
+#define REG_HMATRIX_PRBS2 (0x4100C094) /**< \brief (HMATRIX) Priority B for Slave 2 */
+#define REG_HMATRIX_PRAS3 (0x4100C098) /**< \brief (HMATRIX) Priority A for Slave 3 */
+#define REG_HMATRIX_PRBS3 (0x4100C09C) /**< \brief (HMATRIX) Priority B for Slave 3 */
+#define REG_HMATRIX_PRAS4 (0x4100C0A0) /**< \brief (HMATRIX) Priority A for Slave 4 */
+#define REG_HMATRIX_PRBS4 (0x4100C0A4) /**< \brief (HMATRIX) Priority B for Slave 4 */
+#define REG_HMATRIX_PRAS5 (0x4100C0A8) /**< \brief (HMATRIX) Priority A for Slave 5 */
+#define REG_HMATRIX_PRBS5 (0x4100C0AC) /**< \brief (HMATRIX) Priority B for Slave 5 */
+#define REG_HMATRIX_PRAS6 (0x4100C0B0) /**< \brief (HMATRIX) Priority A for Slave 6 */
+#define REG_HMATRIX_PRBS6 (0x4100C0B4) /**< \brief (HMATRIX) Priority B for Slave 6 */
+#define REG_HMATRIX_PRAS7 (0x4100C0B8) /**< \brief (HMATRIX) Priority A for Slave 7 */
+#define REG_HMATRIX_PRBS7 (0x4100C0BC) /**< \brief (HMATRIX) Priority B for Slave 7 */
+#define REG_HMATRIX_PRAS8 (0x4100C0C0) /**< \brief (HMATRIX) Priority A for Slave 8 */
+#define REG_HMATRIX_PRBS8 (0x4100C0C4) /**< \brief (HMATRIX) Priority B for Slave 8 */
+#define REG_HMATRIX_PRAS9 (0x4100C0C8) /**< \brief (HMATRIX) Priority A for Slave 9 */
+#define REG_HMATRIX_PRBS9 (0x4100C0CC) /**< \brief (HMATRIX) Priority B for Slave 9 */
+#define REG_HMATRIX_PRAS10 (0x4100C0D0) /**< \brief (HMATRIX) Priority A for Slave 10 */
+#define REG_HMATRIX_PRBS10 (0x4100C0D4) /**< \brief (HMATRIX) Priority B for Slave 10 */
+#define REG_HMATRIX_PRAS11 (0x4100C0D8) /**< \brief (HMATRIX) Priority A for Slave 11 */
+#define REG_HMATRIX_PRBS11 (0x4100C0DC) /**< \brief (HMATRIX) Priority B for Slave 11 */
+#define REG_HMATRIX_PRAS12 (0x4100C0E0) /**< \brief (HMATRIX) Priority A for Slave 12 */
+#define REG_HMATRIX_PRBS12 (0x4100C0E4) /**< \brief (HMATRIX) Priority B for Slave 12 */
+#define REG_HMATRIX_PRAS13 (0x4100C0E8) /**< \brief (HMATRIX) Priority A for Slave 13 */
+#define REG_HMATRIX_PRBS13 (0x4100C0EC) /**< \brief (HMATRIX) Priority B for Slave 13 */
+#define REG_HMATRIX_PRAS14 (0x4100C0F0) /**< \brief (HMATRIX) Priority A for Slave 14 */
+#define REG_HMATRIX_PRBS14 (0x4100C0F4) /**< \brief (HMATRIX) Priority B for Slave 14 */
+#define REG_HMATRIX_PRAS15 (0x4100C0F8) /**< \brief (HMATRIX) Priority A for Slave 15 */
+#define REG_HMATRIX_PRBS15 (0x4100C0FC) /**< \brief (HMATRIX) Priority B for Slave 15 */
+#else
+#define REG_HMATRIX_PRAS0 (*(RwReg *)0x4100C080UL) /**< \brief (HMATRIX) Priority A for Slave 0 */
+#define REG_HMATRIX_PRBS0 (*(RwReg *)0x4100C084UL) /**< \brief (HMATRIX) Priority B for Slave 0 */
+#define REG_HMATRIX_PRAS1 (*(RwReg *)0x4100C088UL) /**< \brief (HMATRIX) Priority A for Slave 1 */
+#define REG_HMATRIX_PRBS1 (*(RwReg *)0x4100C08CUL) /**< \brief (HMATRIX) Priority B for Slave 1 */
+#define REG_HMATRIX_PRAS2 (*(RwReg *)0x4100C090UL) /**< \brief (HMATRIX) Priority A for Slave 2 */
+#define REG_HMATRIX_PRBS2 (*(RwReg *)0x4100C094UL) /**< \brief (HMATRIX) Priority B for Slave 2 */
+#define REG_HMATRIX_PRAS3 (*(RwReg *)0x4100C098UL) /**< \brief (HMATRIX) Priority A for Slave 3 */
+#define REG_HMATRIX_PRBS3 (*(RwReg *)0x4100C09CUL) /**< \brief (HMATRIX) Priority B for Slave 3 */
+#define REG_HMATRIX_PRAS4 (*(RwReg *)0x4100C0A0UL) /**< \brief (HMATRIX) Priority A for Slave 4 */
+#define REG_HMATRIX_PRBS4 (*(RwReg *)0x4100C0A4UL) /**< \brief (HMATRIX) Priority B for Slave 4 */
+#define REG_HMATRIX_PRAS5 (*(RwReg *)0x4100C0A8UL) /**< \brief (HMATRIX) Priority A for Slave 5 */
+#define REG_HMATRIX_PRBS5 (*(RwReg *)0x4100C0ACUL) /**< \brief (HMATRIX) Priority B for Slave 5 */
+#define REG_HMATRIX_PRAS6 (*(RwReg *)0x4100C0B0UL) /**< \brief (HMATRIX) Priority A for Slave 6 */
+#define REG_HMATRIX_PRBS6 (*(RwReg *)0x4100C0B4UL) /**< \brief (HMATRIX) Priority B for Slave 6 */
+#define REG_HMATRIX_PRAS7 (*(RwReg *)0x4100C0B8UL) /**< \brief (HMATRIX) Priority A for Slave 7 */
+#define REG_HMATRIX_PRBS7 (*(RwReg *)0x4100C0BCUL) /**< \brief (HMATRIX) Priority B for Slave 7 */
+#define REG_HMATRIX_PRAS8 (*(RwReg *)0x4100C0C0UL) /**< \brief (HMATRIX) Priority A for Slave 8 */
+#define REG_HMATRIX_PRBS8 (*(RwReg *)0x4100C0C4UL) /**< \brief (HMATRIX) Priority B for Slave 8 */
+#define REG_HMATRIX_PRAS9 (*(RwReg *)0x4100C0C8UL) /**< \brief (HMATRIX) Priority A for Slave 9 */
+#define REG_HMATRIX_PRBS9 (*(RwReg *)0x4100C0CCUL) /**< \brief (HMATRIX) Priority B for Slave 9 */
+#define REG_HMATRIX_PRAS10 (*(RwReg *)0x4100C0D0UL) /**< \brief (HMATRIX) Priority A for Slave 10 */
+#define REG_HMATRIX_PRBS10 (*(RwReg *)0x4100C0D4UL) /**< \brief (HMATRIX) Priority B for Slave 10 */
+#define REG_HMATRIX_PRAS11 (*(RwReg *)0x4100C0D8UL) /**< \brief (HMATRIX) Priority A for Slave 11 */
+#define REG_HMATRIX_PRBS11 (*(RwReg *)0x4100C0DCUL) /**< \brief (HMATRIX) Priority B for Slave 11 */
+#define REG_HMATRIX_PRAS12 (*(RwReg *)0x4100C0E0UL) /**< \brief (HMATRIX) Priority A for Slave 12 */
+#define REG_HMATRIX_PRBS12 (*(RwReg *)0x4100C0E4UL) /**< \brief (HMATRIX) Priority B for Slave 12 */
+#define REG_HMATRIX_PRAS13 (*(RwReg *)0x4100C0E8UL) /**< \brief (HMATRIX) Priority A for Slave 13 */
+#define REG_HMATRIX_PRBS13 (*(RwReg *)0x4100C0ECUL) /**< \brief (HMATRIX) Priority B for Slave 13 */
+#define REG_HMATRIX_PRAS14 (*(RwReg *)0x4100C0F0UL) /**< \brief (HMATRIX) Priority A for Slave 14 */
+#define REG_HMATRIX_PRBS14 (*(RwReg *)0x4100C0F4UL) /**< \brief (HMATRIX) Priority B for Slave 14 */
+#define REG_HMATRIX_PRAS15 (*(RwReg *)0x4100C0F8UL) /**< \brief (HMATRIX) Priority A for Slave 15 */
+#define REG_HMATRIX_PRBS15 (*(RwReg *)0x4100C0FCUL) /**< \brief (HMATRIX) Priority B for Slave 15 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for HMATRIX peripheral ========== */
+#define HMATRIX_CLK_AHB_ID 5 // Index of AHB Clock in MCLK.AHBMASK register (MASK may be tied to 1 depending on chip integration)
+#define HMATRIX_DEFINED
+/* ========== Instance parameters for HMATRIX ========== */
+#define HMATRIX_SLAVE_FLASH 0
+#define HMATRIX_SLAVE_FLASH_ALT 1
+#define HMATRIX_SLAVE_SEEPROM 2
+#define HMATRIX_SLAVE_RAMCM4S 3
+#define HMATRIX_SLAVE_RAMPPPDSU 4
+#define HMATRIX_SLAVE_RAMDMAWR 5
+#define HMATRIX_SLAVE_RAMDMACICM 6
+#define HMATRIX_SLAVE_HPB0 7
+#define HMATRIX_SLAVE_HPB1 8
+#define HMATRIX_SLAVE_HPB2 9
+#define HMATRIX_SLAVE_HPB3 10
+#define HMATRIX_SLAVE_SDHC0 12
+#define HMATRIX_SLAVE_SDHC1 13
+#define HMATRIX_SLAVE_QSPI 14
+#define HMATRIX_SLAVE_BKUPRAM 15
+#define HMATRIX_SLAVE_NUM 16
+
+#define HMATRIX_MASTER_CM4_S 0
+#define HMATRIX_MASTER_CMCC 1
+#define HMATRIX_MASTER_PICOP_MEM 2
+#define HMATRIX_MASTER_PICOP_IO 3
+#define HMATRIX_MASTER_DMAC_DTWR 4
+#define HMATRIX_MASTER_DMAC_DTRD 5
+#define HMATRIX_MASTER_ICM 6
+#define HMATRIX_MASTER_DSU 7
+#define HMATRIX_MASTER_NUM 8
+
+#endif /* _SAME54_HMATRIX_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/i2s.h b/GPIO/ATSAME54/include/instance/i2s.h
new file mode 100644
index 0000000..f7b987a
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/i2s.h
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_I2S_INSTANCE_
+#define _SAME54_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA (0x43002800) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0 (0x43002804) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1 (0x43002808) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR (0x4300280C) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET (0x43002810) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG (0x43002814) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY (0x43002818) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_TXCTRL (0x43002820) /**< \brief (I2S) Tx Serializer Control */
+#define REG_I2S_RXCTRL (0x43002824) /**< \brief (I2S) Rx Serializer Control */
+#define REG_I2S_TXDATA (0x43002830) /**< \brief (I2S) Tx Data */
+#define REG_I2S_RXDATA (0x43002834) /**< \brief (I2S) Rx Data */
+#else
+#define REG_I2S_CTRLA (*(RwReg8 *)0x43002800UL) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0 (*(RwReg *)0x43002804UL) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1 (*(RwReg *)0x43002808UL) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR (*(RwReg16*)0x4300280CUL) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET (*(RwReg16*)0x43002810UL) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG (*(RwReg16*)0x43002814UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY (*(RoReg16*)0x43002818UL) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_TXCTRL (*(RwReg *)0x43002820UL) /**< \brief (I2S) Tx Serializer Control */
+#define REG_I2S_RXCTRL (*(RwReg *)0x43002824UL) /**< \brief (I2S) Rx Serializer Control */
+#define REG_I2S_TXDATA (*(WoReg *)0x43002830UL) /**< \brief (I2S) Tx Data */
+#define REG_I2S_RXDATA (*(RoReg *)0x43002834UL) /**< \brief (I2S) Rx Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM 2 // Number of clock units
+#define I2S_DMAC_ID_RX_0 76
+#define I2S_DMAC_ID_RX_1 77
+#define I2S_DMAC_ID_RX_LSB 76
+#define I2S_DMAC_ID_RX_MSB 77
+#define I2S_DMAC_ID_RX_SIZE 2
+#define I2S_DMAC_ID_TX_0 78
+#define I2S_DMAC_ID_TX_1 79
+#define I2S_DMAC_ID_TX_LSB 78
+#define I2S_DMAC_ID_TX_MSB 79
+#define I2S_DMAC_ID_TX_SIZE 2
+#define I2S_GCLK_ID_0 43
+#define I2S_GCLK_ID_1 44
+#define I2S_GCLK_ID_LSB 43
+#define I2S_GCLK_ID_MSB 44
+#define I2S_GCLK_ID_SIZE 2
+#define I2S_MAX_SLOTS 8 // Max number of data slots in frame
+#define I2S_MAX_WL_BITS 32 // Max number of bits in data samples
+#define I2S_SER_NUM 2 // Number of serializers
+
+#endif /* _SAME54_I2S_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/icm.h b/GPIO/ATSAME54/include/instance/icm.h
new file mode 100644
index 0000000..26bbc6d
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/icm.h
@@ -0,0 +1,77 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ICM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_ICM_INSTANCE_
+#define _SAME54_ICM_INSTANCE_
+
+/* ========== Register definition for ICM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ICM_CFG (0x42002C00) /**< \brief (ICM) Configuration */
+#define REG_ICM_CTRL (0x42002C04) /**< \brief (ICM) Control */
+#define REG_ICM_SR (0x42002C08) /**< \brief (ICM) Status */
+#define REG_ICM_IER (0x42002C10) /**< \brief (ICM) Interrupt Enable */
+#define REG_ICM_IDR (0x42002C14) /**< \brief (ICM) Interrupt Disable */
+#define REG_ICM_IMR (0x42002C18) /**< \brief (ICM) Interrupt Mask */
+#define REG_ICM_ISR (0x42002C1C) /**< \brief (ICM) Interrupt Status */
+#define REG_ICM_UASR (0x42002C20) /**< \brief (ICM) Undefined Access Status */
+#define REG_ICM_DSCR (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */
+#define REG_ICM_HASH (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */
+#define REG_ICM_UIHVAL0 (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */
+#define REG_ICM_UIHVAL1 (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */
+#define REG_ICM_UIHVAL2 (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */
+#define REG_ICM_UIHVAL3 (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */
+#define REG_ICM_UIHVAL4 (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */
+#define REG_ICM_UIHVAL5 (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */
+#define REG_ICM_UIHVAL6 (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */
+#define REG_ICM_UIHVAL7 (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */
+#else
+#define REG_ICM_CFG (*(RwReg *)0x42002C00UL) /**< \brief (ICM) Configuration */
+#define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */
+#define REG_ICM_SR (*(RoReg *)0x42002C08UL) /**< \brief (ICM) Status */
+#define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */
+#define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */
+#define REG_ICM_IMR (*(RoReg *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */
+#define REG_ICM_ISR (*(RoReg *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */
+#define REG_ICM_UASR (*(RoReg *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */
+#define REG_ICM_DSCR (*(RwReg *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */
+#define REG_ICM_HASH (*(RwReg *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */
+#define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */
+#define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */
+#define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */
+#define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */
+#define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */
+#define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */
+#define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */
+#define REG_ICM_UIHVAL7 (*(WoReg *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ICM peripheral ========== */
+#define ICM_CLK_AHB_ID 19
+
+#endif /* _SAME54_ICM_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/mclk.h b/GPIO/ATSAME54/include/instance/mclk.h
new file mode 100644
index 0000000..7b3c5c7
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/mclk.h
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Instance description for MCLK
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_MCLK_INSTANCE_
+#define _SAME54_MCLK_INSTANCE_
+
+/* ========== Register definition for MCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
+#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
+#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
+#define REG_MCLK_HSDIV (0x40000804) /**< \brief (MCLK) HS Clock Division */
+#define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */
+#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */
+#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */
+#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */
+#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */
+#define REG_MCLK_APBDMASK (0x40000820) /**< \brief (MCLK) APBD Mask */
+#else
+#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
+#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
+#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
+#define REG_MCLK_HSDIV (*(RoReg8 *)0x40000804UL) /**< \brief (MCLK) HS Clock Division */
+#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division */
+#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
+#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
+#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
+#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
+#define REG_MCLK_APBDMASK (*(RwReg *)0x40000820UL) /**< \brief (MCLK) APBD Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for MCLK peripheral ========== */
+#define MCLK_SYSTEM_CLOCK 48000000 // System Clock Frequency at Reset
+
+#endif /* _SAME54_MCLK_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/nvmctrl.h b/GPIO/ATSAME54/include/instance/nvmctrl.h
new file mode 100644
index 0000000..e74d41c
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/nvmctrl.h
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_NVMCTRL_INSTANCE_
+#define _SAME54_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (0x4100400E) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (0x41004010) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (0x41004012) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (0x41004014) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_RUNLOCK (0x41004018) /**< \brief (NVMCTRL) Lock Section */
+#define REG_NVMCTRL_PBLDATA0 (0x4100401C) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
+#define REG_NVMCTRL_PBLDATA1 (0x41004020) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
+#define REG_NVMCTRL_ECCERR (0x41004024) /**< \brief (NVMCTRL) ECC Error Status Register */
+#define REG_NVMCTRL_DBGCTRL (0x41004028) /**< \brief (NVMCTRL) Debug Control */
+#define REG_NVMCTRL_SEECFG (0x4100402A) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
+#define REG_NVMCTRL_SEESTAT (0x4100402C) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
+#else
+#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (*(WoReg16*)0x41004004UL) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (*(RoReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (*(RwReg16*)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (*(RwReg16*)0x4100400EUL) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (*(RwReg16*)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (*(RoReg16*)0x41004012UL) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (*(RwReg *)0x41004014UL) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_RUNLOCK (*(RoReg *)0x41004018UL) /**< \brief (NVMCTRL) Lock Section */
+#define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x4100401CUL) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
+#define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x41004020UL) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
+#define REG_NVMCTRL_ECCERR (*(RoReg *)0x41004024UL) /**< \brief (NVMCTRL) ECC Error Status Register */
+#define REG_NVMCTRL_DBGCTRL (*(RwReg8 *)0x41004028UL) /**< \brief (NVMCTRL) Debug Control */
+#define REG_NVMCTRL_SEECFG (*(RwReg8 *)0x4100402AUL) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
+#define REG_NVMCTRL_SEESTAT (*(RoReg *)0x4100402CUL) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_BLOCK_SIZE 8192 // Size Of Block (Bytes, Smallest Granularity for Erase Operation)
+#define NVMCTRL_CLK_AHB_ID 6 // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_CLK_AHB_ID_CACHE 23 // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines
+#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22 // Index of AHB Clock in PM.AHBMASK register for SMEE submodule
+#define NVMCTRL_PAGE_SIZE 512 // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)
+
+#endif /* _SAME54_NVMCTRL_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/osc32kctrl.h b/GPIO/ATSAME54/include/instance/osc32kctrl.h
new file mode 100644
index 0000000..b5a89ad
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/osc32kctrl.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for OSC32KCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_OSC32KCTRL_INSTANCE_
+#define _SAME54_OSC32KCTRL_INSTANCE_
+
+/* ========== Register definition for OSC32KCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
+#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
+#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
+#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
+#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */
+#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
+#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
+#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#else
+#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
+#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
+#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
+#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
+#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */
+#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
+#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
+#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
+#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0 // OSC32K coarse calibration size
+
+#endif /* _SAME54_OSC32KCTRL_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/oscctrl.h b/GPIO/ATSAME54/include/instance/oscctrl.h
new file mode 100644
index 0000000..8e18844
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/oscctrl.h
@@ -0,0 +1,130 @@
+/**
+ * \file
+ *
+ * \brief Instance description for OSCCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_OSCCTRL_INSTANCE_
+#define _SAME54_OSCCTRL_INSTANCE_
+
+/* ========== Register definition for OSCCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_OSCCTRL_EVCTRL (0x40001000) /**< \brief (OSCCTRL) Event Control */
+#define REG_OSCCTRL_INTENCLR (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Clear */
+#define REG_OSCCTRL_INTENSET (0x40001008) /**< \brief (OSCCTRL) Interrupt Enable Set */
+#define REG_OSCCTRL_INTFLAG (0x4000100C) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
+#define REG_OSCCTRL_STATUS (0x40001010) /**< \brief (OSCCTRL) Status */
+#define REG_OSCCTRL_XOSCCTRL0 (0x40001014) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
+#define REG_OSCCTRL_XOSCCTRL1 (0x40001018) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
+#define REG_OSCCTRL_DFLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Control A */
+#define REG_OSCCTRL_DFLLCTRLB (0x40001020) /**< \brief (OSCCTRL) DFLL48M Control B */
+#define REG_OSCCTRL_DFLLVAL (0x40001024) /**< \brief (OSCCTRL) DFLL48M Value */
+#define REG_OSCCTRL_DFLLMUL (0x40001028) /**< \brief (OSCCTRL) DFLL48M Multiplier */
+#define REG_OSCCTRL_DFLLSYNC (0x4000102C) /**< \brief (OSCCTRL) DFLL48M Synchronization */
+#define REG_OSCCTRL_DPLLCTRLA0 (0x40001030) /**< \brief (OSCCTRL) DPLL Control A 0 */
+#define REG_OSCCTRL_DPLLRATIO0 (0x40001034) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
+#define REG_OSCCTRL_DPLLCTRLB0 (0x40001038) /**< \brief (OSCCTRL) DPLL Control B 0 */
+#define REG_OSCCTRL_DPLLSYNCBUSY0 (0x4000103C) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
+#define REG_OSCCTRL_DPLLSTATUS0 (0x40001040) /**< \brief (OSCCTRL) DPLL Status 0 */
+#define REG_OSCCTRL_DPLLCTRLA1 (0x40001044) /**< \brief (OSCCTRL) DPLL Control A 1 */
+#define REG_OSCCTRL_DPLLRATIO1 (0x40001048) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
+#define REG_OSCCTRL_DPLLCTRLB1 (0x4000104C) /**< \brief (OSCCTRL) DPLL Control B 1 */
+#define REG_OSCCTRL_DPLLSYNCBUSY1 (0x40001050) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
+#define REG_OSCCTRL_DPLLSTATUS1 (0x40001054) /**< \brief (OSCCTRL) DPLL Status 1 */
+#else
+#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001000UL) /**< \brief (OSCCTRL) Event Control */
+#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
+#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
+#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x4000100CUL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
+#define REG_OSCCTRL_STATUS (*(RoReg *)0x40001010UL) /**< \brief (OSCCTRL) Status */
+#define REG_OSCCTRL_XOSCCTRL0 (*(RwReg *)0x40001014UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
+#define REG_OSCCTRL_XOSCCTRL1 (*(RwReg *)0x40001018UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
+#define REG_OSCCTRL_DFLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Control A */
+#define REG_OSCCTRL_DFLLCTRLB (*(RwReg8 *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Control B */
+#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Value */
+#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001028UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
+#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
+#define REG_OSCCTRL_DPLLCTRLA0 (*(RwReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Control A 0 */
+#define REG_OSCCTRL_DPLLRATIO0 (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
+#define REG_OSCCTRL_DPLLCTRLB0 (*(RwReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Control B 0 */
+#define REG_OSCCTRL_DPLLSYNCBUSY0 (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
+#define REG_OSCCTRL_DPLLSTATUS0 (*(RoReg8 *)0x40001040UL) /**< \brief (OSCCTRL) DPLL Status 0 */
+#define REG_OSCCTRL_DPLLCTRLA1 (*(RwReg8 *)0x40001044UL) /**< \brief (OSCCTRL) DPLL Control A 1 */
+#define REG_OSCCTRL_DPLLRATIO1 (*(RwReg8 *)0x40001048UL) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
+#define REG_OSCCTRL_DPLLCTRLB1 (*(RwReg8 *)0x4000104CUL) /**< \brief (OSCCTRL) DPLL Control B 1 */
+#define REG_OSCCTRL_DPLLSYNCBUSY1 (*(RoReg8 *)0x40001050UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
+#define REG_OSCCTRL_DPLLSTATUS1 (*(RoReg8 *)0x40001054UL) /**< \brief (OSCCTRL) DPLL Status 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for OSCCTRL peripheral ========== */
+#define OSCCTRL_DFLLS_NUM 1 // Number of DFLLs
+#define OSCCTRL_DFLL_IMPLEMENTED 1 // DFLL implemented
+#define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0 // DFLL48M bias test mode implemented
+#define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2 // Size COARSE DAC STEP
+#define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32 // DFLL48M Frequency Coarse Reset Value (Before Calibration)
+#define OSCCTRL_DFLL48M_COARSE_SIZE 6 // Size COARSE CALIBRATION
+#define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1 // Run oscillator at reset
+#define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2 // Size FINE DAC STEP
+#define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128 // DFLL48M Frequency Fine Reset Value (Before Calibration)
+#define OSCCTRL_DFLL48M_FINE_SIZE 8 // Size FINE CALIBRATION
+#define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
+#define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
+#define OSCCTRL_DFLL48M_TCAL_SIZE 4 // Size TEMP CALIBRATION
+#define OSCCTRL_DFLL48M_TCBIAS_SIZE 2 // Size TC BIAS CALIBRATION
+#define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3 // Size TEST POINT SELECTOR
+#define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1 // Enable Wait Lock Feature
+#define OSCCTRL_DPLLS_NUM 2 // Number of DPLLs
+#define OSCCTRL_DPLL0_IMPLEMENTED 1 // DPLL0 implemented
+#define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
+#define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1 // DPLL0 OCC Implemented
+#define OSCCTRL_DPLL1_IMPLEMENTED 1 // DPLL1 implemented
+#define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
+#define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0 // DPLL1 OCC Implemented
+#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
+#define OSCCTRL_GCLK_ID_FDPLL0 1 // Index of Generic Clock for DPLL0
+#define OSCCTRL_GCLK_ID_FDPLL1 2 // Index of Generic Clock for DPLL1
+#define OSCCTRL_GCLK_ID_FDPLL032K 3 // Index of Generic Clock for DPLL0 32K
+#define OSCCTRL_GCLK_ID_FDPLL132K 3 // Index of Generic Clock for DPLL1 32K
+#define OSCCTRL_OSC16M_IMPLEMENTED 0 // OSC16M implemented
+#define OSCCTRL_OSC48M_IMPLEMENTED 0 // OSC48M implemented
+#define OSCCTRL_OSC48M_NUM 1
+#define OSCCTRL_RCOSCS_NUM 1 // Number of RCOSCs (min 1)
+#define OSCCTRL_XOSCS_NUM 2 // Number of XOSCs
+#define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
+#define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
+#define OSCCTRL_XOSC0_IMPLEMENTED 1 // XOSC0 implemented
+#define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
+#define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
+#define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
+#define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
+#define OSCCTRL_XOSC1_IMPLEMENTED 1 // XOSC1 implemented
+#define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
+#define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
+#define OSCCTRL_DFLL48M_VERSION 0x100
+#define OSCCTRL_FDPLL_VERSION 0x100
+#define OSCCTRL_XOSC_VERSION 0x100
+
+#endif /* _SAME54_OSCCTRL_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/pac.h b/GPIO/ATSAME54/include/instance/pac.h
new file mode 100644
index 0000000..81f0aca
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/pac.h
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PAC_INSTANCE_
+#define _SAME54_PAC_INSTANCE_
+
+/* ========== Register definition for PAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */
+#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */
+#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */
+#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */
+#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
+#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
+#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
+#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
+#define REG_PAC_INTFLAGD (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
+#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
+#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
+#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
+#define REG_PAC_STATUSD (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */
+#else
+#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */
+#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
+#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
+#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
+#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
+#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
+#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
+#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
+#define REG_PAC_INTFLAGD (*(RwReg *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
+#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
+#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
+#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
+#define REG_PAC_STATUSD (*(RoReg *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC peripheral ========== */
+#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
+#define PAC_CLK_AHB_ID 12 // AHB clock index
+#define PAC_HPB_NUM 4 // Number of bridges AHB/APB
+
+#endif /* _SAME54_PAC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/pcc.h b/GPIO/ATSAME54/include/instance/pcc.h
new file mode 100644
index 0000000..46fd50a
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/pcc.h
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PCC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PCC_INSTANCE_
+#define _SAME54_PCC_INSTANCE_
+
+/* ========== Register definition for PCC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PCC_MR (0x43002C00) /**< \brief (PCC) Mode Register */
+#define REG_PCC_IER (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */
+#define REG_PCC_IDR (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */
+#define REG_PCC_IMR (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */
+#define REG_PCC_ISR (0x43002C10) /**< \brief (PCC) Interrupt Status Register */
+#define REG_PCC_RHR (0x43002C14) /**< \brief (PCC) Reception Holding Register */
+#define REG_PCC_WPMR (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */
+#define REG_PCC_WPSR (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */
+#else
+#define REG_PCC_MR (*(RwReg *)0x43002C00UL) /**< \brief (PCC) Mode Register */
+#define REG_PCC_IER (*(WoReg *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */
+#define REG_PCC_IDR (*(WoReg *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */
+#define REG_PCC_IMR (*(RoReg *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */
+#define REG_PCC_ISR (*(RoReg *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */
+#define REG_PCC_RHR (*(RoReg *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */
+#define REG_PCC_WPMR (*(RwReg *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */
+#define REG_PCC_WPSR (*(RoReg *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PCC peripheral ========== */
+#define PCC_DATA_SIZE 14
+#define PCC_DMAC_ID_RX 80
+
+#endif /* _SAME54_PCC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/pdec.h b/GPIO/ATSAME54/include/instance/pdec.h
new file mode 100644
index 0000000..73c3284
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/pdec.h
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PDEC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PDEC_INSTANCE_
+#define _SAME54_PDEC_INSTANCE_
+
+/* ========== Register definition for PDEC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PDEC_CTRLA (0x42001C00) /**< \brief (PDEC) Control A */
+#define REG_PDEC_CTRLBCLR (0x42001C04) /**< \brief (PDEC) Control B Clear */
+#define REG_PDEC_CTRLBSET (0x42001C05) /**< \brief (PDEC) Control B Set */
+#define REG_PDEC_EVCTRL (0x42001C06) /**< \brief (PDEC) Event Control */
+#define REG_PDEC_INTENCLR (0x42001C08) /**< \brief (PDEC) Interrupt Enable Clear */
+#define REG_PDEC_INTENSET (0x42001C09) /**< \brief (PDEC) Interrupt Enable Set */
+#define REG_PDEC_INTFLAG (0x42001C0A) /**< \brief (PDEC) Interrupt Flag Status and Clear */
+#define REG_PDEC_STATUS (0x42001C0C) /**< \brief (PDEC) Status */
+#define REG_PDEC_DBGCTRL (0x42001C0F) /**< \brief (PDEC) Debug Control */
+#define REG_PDEC_SYNCBUSY (0x42001C10) /**< \brief (PDEC) Synchronization Status */
+#define REG_PDEC_PRESC (0x42001C14) /**< \brief (PDEC) Prescaler Value */
+#define REG_PDEC_FILTER (0x42001C15) /**< \brief (PDEC) Filter Value */
+#define REG_PDEC_PRESCBUF (0x42001C18) /**< \brief (PDEC) Prescaler Buffer Value */
+#define REG_PDEC_FILTERBUF (0x42001C19) /**< \brief (PDEC) Filter Buffer Value */
+#define REG_PDEC_COUNT (0x42001C1C) /**< \brief (PDEC) Counter Value */
+#define REG_PDEC_CC0 (0x42001C20) /**< \brief (PDEC) Channel 0 Compare Value */
+#define REG_PDEC_CC1 (0x42001C24) /**< \brief (PDEC) Channel 1 Compare Value */
+#define REG_PDEC_CCBUF0 (0x42001C30) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
+#define REG_PDEC_CCBUF1 (0x42001C34) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
+#else
+#define REG_PDEC_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (PDEC) Control A */
+#define REG_PDEC_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (PDEC) Control B Clear */
+#define REG_PDEC_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (PDEC) Control B Set */
+#define REG_PDEC_EVCTRL (*(RwReg16*)0x42001C06UL) /**< \brief (PDEC) Event Control */
+#define REG_PDEC_INTENCLR (*(RwReg8 *)0x42001C08UL) /**< \brief (PDEC) Interrupt Enable Clear */
+#define REG_PDEC_INTENSET (*(RwReg8 *)0x42001C09UL) /**< \brief (PDEC) Interrupt Enable Set */
+#define REG_PDEC_INTFLAG (*(RwReg8 *)0x42001C0AUL) /**< \brief (PDEC) Interrupt Flag Status and Clear */
+#define REG_PDEC_STATUS (*(RwReg16*)0x42001C0CUL) /**< \brief (PDEC) Status */
+#define REG_PDEC_DBGCTRL (*(RwReg8 *)0x42001C0FUL) /**< \brief (PDEC) Debug Control */
+#define REG_PDEC_SYNCBUSY (*(RoReg *)0x42001C10UL) /**< \brief (PDEC) Synchronization Status */
+#define REG_PDEC_PRESC (*(RwReg8 *)0x42001C14UL) /**< \brief (PDEC) Prescaler Value */
+#define REG_PDEC_FILTER (*(RwReg8 *)0x42001C15UL) /**< \brief (PDEC) Filter Value */
+#define REG_PDEC_PRESCBUF (*(RwReg8 *)0x42001C18UL) /**< \brief (PDEC) Prescaler Buffer Value */
+#define REG_PDEC_FILTERBUF (*(RwReg8 *)0x42001C19UL) /**< \brief (PDEC) Filter Buffer Value */
+#define REG_PDEC_COUNT (*(RwReg *)0x42001C1CUL) /**< \brief (PDEC) Counter Value */
+#define REG_PDEC_CC0 (*(RwReg *)0x42001C20UL) /**< \brief (PDEC) Channel 0 Compare Value */
+#define REG_PDEC_CC1 (*(RwReg *)0x42001C24UL) /**< \brief (PDEC) Channel 1 Compare Value */
+#define REG_PDEC_CCBUF0 (*(RwReg *)0x42001C30UL) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
+#define REG_PDEC_CCBUF1 (*(RwReg *)0x42001C34UL) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PDEC peripheral ========== */
+#define PDEC_CC_NUM 2 // Number of Compare Channels units
+#define PDEC_GCLK_ID 31
+
+#endif /* _SAME54_PDEC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/picop.h b/GPIO/ATSAME54/include/instance/picop.h
new file mode 100644
index 0000000..3c58fc0
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/picop.h
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PICOP
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PICOP_INSTANCE_
+#define _SAME54_PICOP_INSTANCE_
+
+/* ========== Register definition for PICOP peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PICOP_ID0 (0x4100E000U) /**< \brief (PICOP) ID 0 */
+#define REG_PICOP_ID1 (0x4100E004U) /**< \brief (PICOP) ID 1 */
+#define REG_PICOP_ID2 (0x4100E008U) /**< \brief (PICOP) ID 2 */
+#define REG_PICOP_ID3 (0x4100E00CU) /**< \brief (PICOP) ID 3 */
+#define REG_PICOP_ID4 (0x4100E010U) /**< \brief (PICOP) ID 4 */
+#define REG_PICOP_ID5 (0x4100E014U) /**< \brief (PICOP) ID 5 */
+#define REG_PICOP_ID6 (0x4100E018U) /**< \brief (PICOP) ID 6 */
+#define REG_PICOP_ID7 (0x4100E01CU) /**< \brief (PICOP) ID 7 */
+#define REG_PICOP_CONFIG (0x4100E020U) /**< \brief (PICOP) Configuration */
+#define REG_PICOP_CTRL (0x4100E024U) /**< \brief (PICOP) Control */
+#define REG_PICOP_CMD (0x4100E028U) /**< \brief (PICOP) Command */
+#define REG_PICOP_PC (0x4100E02CU) /**< \brief (PICOP) Program Counter */
+#define REG_PICOP_HF (0x4100E030U) /**< \brief (PICOP) Host Flags */
+#define REG_PICOP_HFCTRL (0x4100E034U) /**< \brief (PICOP) Host Flag Control */
+#define REG_PICOP_HFSETCLR0 (0x4100E038U) /**< \brief (PICOP) Host Flags Set/Clr */
+#define REG_PICOP_HFSETCLR1 (0x4100E03CU) /**< \brief (PICOP) Host Flags Set/Clr */
+#define REG_PICOP_OCDCONFIG (0x4100E050U) /**< \brief (PICOP) OCD Configuration */
+#define REG_PICOP_OCDCONTROL (0x4100E054U) /**< \brief (PICOP) OCD Control */
+#define REG_PICOP_OCDSTATUS (0x4100E058U) /**< \brief (PICOP) OCD Status and Command */
+#define REG_PICOP_OCDPC (0x4100E05CU) /**< \brief (PICOP) ODC Program Counter */
+#define REG_PICOP_OCDFEAT (0x4100E060U) /**< \brief (PICOP) OCD Features */
+#define REG_PICOP_OCDCCNT (0x4100E068U) /**< \brief (PICOP) OCD Cycle Counter */
+#define REG_PICOP_OCDBPGEN0 (0x4100E070U) /**< \brief (PICOP) OCD Breakpoint Generator 0 */
+#define REG_PICOP_OCDBPGEN1 (0x4100E074U) /**< \brief (PICOP) OCD Breakpoint Generator 1 */
+#define REG_PICOP_OCDBPGEN2 (0x4100E078U) /**< \brief (PICOP) OCD Breakpoint Generator 2 */
+#define REG_PICOP_OCDBPGEN3 (0x4100E07CU) /**< \brief (PICOP) OCD Breakpoint Generator 3 */
+#define REG_PICOP_R3R0 (0x4100E080U) /**< \brief (PICOP) R3 to 0 */
+#define REG_PICOP_R7R4 (0x4100E084U) /**< \brief (PICOP) R7 to 4 */
+#define REG_PICOP_R11R8 (0x4100E088U) /**< \brief (PICOP) R11 to 8 */
+#define REG_PICOP_R15R12 (0x4100E08CU) /**< \brief (PICOP) R15 to 12 */
+#define REG_PICOP_R19R16 (0x4100E090U) /**< \brief (PICOP) R19 to 16 */
+#define REG_PICOP_R23R20 (0x4100E094U) /**< \brief (PICOP) R23 to 20 */
+#define REG_PICOP_R27R24 (0x4100E098U) /**< \brief (PICOP) R27 to 24: XH, XL, R25, R24 */
+#define REG_PICOP_R31R28 (0x4100E09CU) /**< \brief (PICOP) R31 to 28: ZH, ZL, YH, YL */
+#define REG_PICOP_S1S0 (0x4100E0A0U) /**< \brief (PICOP) System Regs 1 to 0: SR */
+#define REG_PICOP_S3S2 (0x4100E0A4U) /**< \brief (PICOP) System Regs 3 to 2: CTRL */
+#define REG_PICOP_S5S4 (0x4100E0A8U) /**< \brief (PICOP) System Regs 5 to 4: SREG, CCR */
+#define REG_PICOP_S11S10 (0x4100E0B4U) /**< \brief (PICOP) System Regs 11 to 10: Immediate */
+#define REG_PICOP_LINK (0x4100E0B8U) /**< \brief (PICOP) Link */
+#define REG_PICOP_SP (0x4100E0BCU) /**< \brief (PICOP) Stack Pointer */
+#define REG_PICOP_MMUFLASH (0x4100E100U) /**< \brief (PICOP) MMU mapping for flash */
+#define REG_PICOP_MMU0 (0x4100E118U) /**< \brief (PICOP) MMU mapping user 0 */
+#define REG_PICOP_MMU1 (0x4100E11CU) /**< \brief (PICOP) MMU mapping user 1 */
+#define REG_PICOP_MMUCTRL (0x4100E120U) /**< \brief (PICOP) MMU Control */
+#define REG_PICOP_ICACHE (0x4100E180U) /**< \brief (PICOP) Instruction Cache Control */
+#define REG_PICOP_ICACHELRU (0x4100E184U) /**< \brief (PICOP) Instruction Cache LRU */
+#define REG_PICOP_QOSCTRL (0x4100E200U) /**< \brief (PICOP) QOS Control */
+#else
+#define REG_PICOP_ID0 (*(RwReg *)0x4100E000U) /**< \brief (PICOP) ID 0 */
+#define REG_PICOP_ID1 (*(RwReg *)0x4100E004U) /**< \brief (PICOP) ID 1 */
+#define REG_PICOP_ID2 (*(RwReg *)0x4100E008U) /**< \brief (PICOP) ID 2 */
+#define REG_PICOP_ID3 (*(RwReg *)0x4100E00CU) /**< \brief (PICOP) ID 3 */
+#define REG_PICOP_ID4 (*(RwReg *)0x4100E010U) /**< \brief (PICOP) ID 4 */
+#define REG_PICOP_ID5 (*(RwReg *)0x4100E014U) /**< \brief (PICOP) ID 5 */
+#define REG_PICOP_ID6 (*(RwReg *)0x4100E018U) /**< \brief (PICOP) ID 6 */
+#define REG_PICOP_ID7 (*(RwReg *)0x4100E01CU) /**< \brief (PICOP) ID 7 */
+#define REG_PICOP_CONFIG (*(RwReg *)0x4100E020U) /**< \brief (PICOP) Configuration */
+#define REG_PICOP_CTRL (*(RwReg *)0x4100E024U) /**< \brief (PICOP) Control */
+#define REG_PICOP_CMD (*(RwReg *)0x4100E028U) /**< \brief (PICOP) Command */
+#define REG_PICOP_PC (*(RwReg *)0x4100E02CU) /**< \brief (PICOP) Program Counter */
+#define REG_PICOP_HF (*(RwReg *)0x4100E030U) /**< \brief (PICOP) Host Flags */
+#define REG_PICOP_HFCTRL (*(RwReg *)0x4100E034U) /**< \brief (PICOP) Host Flag Control */
+#define REG_PICOP_HFSETCLR0 (*(RwReg *)0x4100E038U) /**< \brief (PICOP) Host Flags Set/Clr */
+#define REG_PICOP_HFSETCLR1 (*(RwReg *)0x4100E03CU) /**< \brief (PICOP) Host Flags Set/Clr */
+#define REG_PICOP_OCDCONFIG (*(RwReg *)0x4100E050U) /**< \brief (PICOP) OCD Configuration */
+#define REG_PICOP_OCDCONTROL (*(RwReg *)0x4100E054U) /**< \brief (PICOP) OCD Control */
+#define REG_PICOP_OCDSTATUS (*(RwReg *)0x4100E058U) /**< \brief (PICOP) OCD Status and Command */
+#define REG_PICOP_OCDPC (*(RwReg *)0x4100E05CU) /**< \brief (PICOP) ODC Program Counter */
+#define REG_PICOP_OCDFEAT (*(RwReg *)0x4100E060U) /**< \brief (PICOP) OCD Features */
+#define REG_PICOP_OCDCCNT (*(RwReg *)0x4100E068U) /**< \brief (PICOP) OCD Cycle Counter */
+#define REG_PICOP_OCDBPGEN0 (*(RwReg *)0x4100E070U) /**< \brief (PICOP) OCD Breakpoint Generator 0 */
+#define REG_PICOP_OCDBPGEN1 (*(RwReg *)0x4100E074U) /**< \brief (PICOP) OCD Breakpoint Generator 1 */
+#define REG_PICOP_OCDBPGEN2 (*(RwReg *)0x4100E078U) /**< \brief (PICOP) OCD Breakpoint Generator 2 */
+#define REG_PICOP_OCDBPGEN3 (*(RwReg *)0x4100E07CU) /**< \brief (PICOP) OCD Breakpoint Generator 3 */
+#define REG_PICOP_R3R0 (*(RwReg *)0x4100E080U) /**< \brief (PICOP) R3 to 0 */
+#define REG_PICOP_R7R4 (*(RwReg *)0x4100E084U) /**< \brief (PICOP) R7 to 4 */
+#define REG_PICOP_R11R8 (*(RwReg *)0x4100E088U) /**< \brief (PICOP) R11 to 8 */
+#define REG_PICOP_R15R12 (*(RwReg *)0x4100E08CU) /**< \brief (PICOP) R15 to 12 */
+#define REG_PICOP_R19R16 (*(RwReg *)0x4100E090U) /**< \brief (PICOP) R19 to 16 */
+#define REG_PICOP_R23R20 (*(RwReg *)0x4100E094U) /**< \brief (PICOP) R23 to 20 */
+#define REG_PICOP_R27R24 (*(RwReg *)0x4100E098U) /**< \brief (PICOP) R27 to 24: XH, XL, R25, R24 */
+#define REG_PICOP_R31R28 (*(RwReg *)0x4100E09CU) /**< \brief (PICOP) R31 to 28: ZH, ZL, YH, YL */
+#define REG_PICOP_S1S0 (*(RwReg *)0x4100E0A0U) /**< \brief (PICOP) System Regs 1 to 0: SR */
+#define REG_PICOP_S3S2 (*(RwReg *)0x4100E0A4U) /**< \brief (PICOP) System Regs 3 to 2: CTRL */
+#define REG_PICOP_S5S4 (*(RwReg *)0x4100E0A8U) /**< \brief (PICOP) System Regs 5 to 4: SREG, CCR */
+#define REG_PICOP_S11S10 (*(RwReg *)0x4100E0B4U) /**< \brief (PICOP) System Regs 11 to 10: Immediate */
+#define REG_PICOP_LINK (*(RwReg *)0x4100E0B8U) /**< \brief (PICOP) Link */
+#define REG_PICOP_SP (*(RwReg *)0x4100E0BCU) /**< \brief (PICOP) Stack Pointer */
+#define REG_PICOP_MMUFLASH (*(RwReg *)0x4100E100U) /**< \brief (PICOP) MMU mapping for flash */
+#define REG_PICOP_MMU0 (*(RwReg *)0x4100E118U) /**< \brief (PICOP) MMU mapping user 0 */
+#define REG_PICOP_MMU1 (*(RwReg *)0x4100E11CU) /**< \brief (PICOP) MMU mapping user 1 */
+#define REG_PICOP_MMUCTRL (*(RwReg *)0x4100E120U) /**< \brief (PICOP) MMU Control */
+#define REG_PICOP_ICACHE (*(RwReg *)0x4100E180U) /**< \brief (PICOP) Instruction Cache Control */
+#define REG_PICOP_ICACHELRU (*(RwReg *)0x4100E184U) /**< \brief (PICOP) Instruction Cache LRU */
+#define REG_PICOP_QOSCTRL (*(RwReg *)0x4100E200U) /**< \brief (PICOP) QOS Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME54_PICOP_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/pm.h b/GPIO/ATSAME54/include/instance/pm.h
new file mode 100644
index 0000000..f139964
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/pm.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PM_INSTANCE_
+#define _SAME54_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRLA (0x40000400) /**< \brief (PM) Control A */
+#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */
+#define REG_PM_INTENCLR (0x40000404) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (0x40000405) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */
+#define REG_PM_HIBCFG (0x40000409) /**< \brief (PM) Hibernate Configuration */
+#define REG_PM_BKUPCFG (0x4000040A) /**< \brief (PM) Backup Configuration */
+#define REG_PM_PWSAKDLY (0x40000412) /**< \brief (PM) Power Switch Acknowledge Delay */
+#else
+#define REG_PM_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */
+#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
+#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_STDBYCFG (*(RwReg8 *)0x40000408UL) /**< \brief (PM) Standby Configuration */
+#define REG_PM_HIBCFG (*(RwReg8 *)0x40000409UL) /**< \brief (PM) Hibernate Configuration */
+#define REG_PM_BKUPCFG (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) Backup Configuration */
+#define REG_PM_PWSAKDLY (*(RwReg8 *)0x40000412UL) /**< \brief (PM) Power Switch Acknowledge Delay */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_PD_NUM 0 // Number of switchable Power Domains
+
+#endif /* _SAME54_PM_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/port.h b/GPIO/ATSAME54/include/instance/port.h
new file mode 100644
index 0000000..a8a6385
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/port.h
@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PORT_INSTANCE_
+#define _SAME54_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0 (0x41008000) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (0x41008004) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (0x41008008) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (0x4100800C) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (0x41008010) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (0x41008014) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (0x41008018) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (0x4100801C) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (0x41008020) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (0x41008024) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (0x41008028) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_EVCTRL0 (0x4100802C) /**< \brief (PORT) Event Input Control 0 */
+#define REG_PORT_PMUX0 (0x41008030) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (0x41008040) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (0x41008080) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (0x41008084) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (0x41008088) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (0x4100808C) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (0x41008090) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (0x41008094) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (0x41008098) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (0x4100809C) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (0x410080A0) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (0x410080A4) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (0x410080A8) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_EVCTRL1 (0x410080AC) /**< \brief (PORT) Event Input Control 1 */
+#define REG_PORT_PMUX1 (0x410080B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (0x410080C0) /**< \brief (PORT) Pin Configuration 1 */
+#define REG_PORT_DIR2 (0x41008100) /**< \brief (PORT) Data Direction 2 */
+#define REG_PORT_DIRCLR2 (0x41008104) /**< \brief (PORT) Data Direction Clear 2 */
+#define REG_PORT_DIRSET2 (0x41008108) /**< \brief (PORT) Data Direction Set 2 */
+#define REG_PORT_DIRTGL2 (0x4100810C) /**< \brief (PORT) Data Direction Toggle 2 */
+#define REG_PORT_OUT2 (0x41008110) /**< \brief (PORT) Data Output Value 2 */
+#define REG_PORT_OUTCLR2 (0x41008114) /**< \brief (PORT) Data Output Value Clear 2 */
+#define REG_PORT_OUTSET2 (0x41008118) /**< \brief (PORT) Data Output Value Set 2 */
+#define REG_PORT_OUTTGL2 (0x4100811C) /**< \brief (PORT) Data Output Value Toggle 2 */
+#define REG_PORT_IN2 (0x41008120) /**< \brief (PORT) Data Input Value 2 */
+#define REG_PORT_CTRL2 (0x41008124) /**< \brief (PORT) Control 2 */
+#define REG_PORT_WRCONFIG2 (0x41008128) /**< \brief (PORT) Write Configuration 2 */
+#define REG_PORT_EVCTRL2 (0x4100812C) /**< \brief (PORT) Event Input Control 2 */
+#define REG_PORT_PMUX2 (0x41008130) /**< \brief (PORT) Peripheral Multiplexing 2 */
+#define REG_PORT_PINCFG2 (0x41008140) /**< \brief (PORT) Pin Configuration 2 */
+#define REG_PORT_DIR3 (0x41008180) /**< \brief (PORT) Data Direction 3 */
+#define REG_PORT_DIRCLR3 (0x41008184) /**< \brief (PORT) Data Direction Clear 3 */
+#define REG_PORT_DIRSET3 (0x41008188) /**< \brief (PORT) Data Direction Set 3 */
+#define REG_PORT_DIRTGL3 (0x4100818C) /**< \brief (PORT) Data Direction Toggle 3 */
+#define REG_PORT_OUT3 (0x41008190) /**< \brief (PORT) Data Output Value 3 */
+#define REG_PORT_OUTCLR3 (0x41008194) /**< \brief (PORT) Data Output Value Clear 3 */
+#define REG_PORT_OUTSET3 (0x41008198) /**< \brief (PORT) Data Output Value Set 3 */
+#define REG_PORT_OUTTGL3 (0x4100819C) /**< \brief (PORT) Data Output Value Toggle 3 */
+#define REG_PORT_IN3 (0x410081A0) /**< \brief (PORT) Data Input Value 3 */
+#define REG_PORT_CTRL3 (0x410081A4) /**< \brief (PORT) Control 3 */
+#define REG_PORT_WRCONFIG3 (0x410081A8) /**< \brief (PORT) Write Configuration 3 */
+#define REG_PORT_EVCTRL3 (0x410081AC) /**< \brief (PORT) Event Input Control 3 */
+#define REG_PORT_PMUX3 (0x410081B0) /**< \brief (PORT) Peripheral Multiplexing 3 */
+#define REG_PORT_PINCFG3 (0x410081C0) /**< \brief (PORT) Pin Configuration 3 */
+#else
+#define REG_PORT_DIR0 (*(RwReg *)0x41008000UL) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (*(RwReg *)0x41008004UL) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (*(RwReg *)0x41008008UL) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100800CUL) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (*(RwReg *)0x41008010UL) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (*(RwReg *)0x41008014UL) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (*(RwReg *)0x41008018UL) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100801CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (*(RoReg *)0x41008020UL) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (*(RwReg *)0x41008024UL) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41008028UL) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100802CUL) /**< \brief (PORT) Event Input Control 0 */
+#define REG_PORT_PMUX0 (*(RwReg *)0x41008030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (*(RwReg *)0x41008040UL) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (*(RwReg *)0x41008080UL) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (*(RwReg *)0x41008084UL) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (*(RwReg *)0x41008088UL) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100808CUL) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (*(RwReg *)0x41008090UL) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (*(RwReg *)0x41008094UL) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (*(RwReg *)0x41008098UL) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100809CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (*(RoReg *)0x410080A0UL) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (*(RwReg *)0x410080A4UL) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410080A8UL) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_EVCTRL1 (*(RwReg *)0x410080ACUL) /**< \brief (PORT) Event Input Control 1 */
+#define REG_PORT_PMUX1 (*(RwReg *)0x410080B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (*(RwReg *)0x410080C0UL) /**< \brief (PORT) Pin Configuration 1 */
+#define REG_PORT_DIR2 (*(RwReg *)0x41008100UL) /**< \brief (PORT) Data Direction 2 */
+#define REG_PORT_DIRCLR2 (*(RwReg *)0x41008104UL) /**< \brief (PORT) Data Direction Clear 2 */
+#define REG_PORT_DIRSET2 (*(RwReg *)0x41008108UL) /**< \brief (PORT) Data Direction Set 2 */
+#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100810CUL) /**< \brief (PORT) Data Direction Toggle 2 */
+#define REG_PORT_OUT2 (*(RwReg *)0x41008110UL) /**< \brief (PORT) Data Output Value 2 */
+#define REG_PORT_OUTCLR2 (*(RwReg *)0x41008114UL) /**< \brief (PORT) Data Output Value Clear 2 */
+#define REG_PORT_OUTSET2 (*(RwReg *)0x41008118UL) /**< \brief (PORT) Data Output Value Set 2 */
+#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100811CUL) /**< \brief (PORT) Data Output Value Toggle 2 */
+#define REG_PORT_IN2 (*(RoReg *)0x41008120UL) /**< \brief (PORT) Data Input Value 2 */
+#define REG_PORT_CTRL2 (*(RwReg *)0x41008124UL) /**< \brief (PORT) Control 2 */
+#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41008128UL) /**< \brief (PORT) Write Configuration 2 */
+#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100812CUL) /**< \brief (PORT) Event Input Control 2 */
+#define REG_PORT_PMUX2 (*(RwReg *)0x41008130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */
+#define REG_PORT_PINCFG2 (*(RwReg *)0x41008140UL) /**< \brief (PORT) Pin Configuration 2 */
+#define REG_PORT_DIR3 (*(RwReg *)0x41008180UL) /**< \brief (PORT) Data Direction 3 */
+#define REG_PORT_DIRCLR3 (*(RwReg *)0x41008184UL) /**< \brief (PORT) Data Direction Clear 3 */
+#define REG_PORT_DIRSET3 (*(RwReg *)0x41008188UL) /**< \brief (PORT) Data Direction Set 3 */
+#define REG_PORT_DIRTGL3 (*(RwReg *)0x4100818CUL) /**< \brief (PORT) Data Direction Toggle 3 */
+#define REG_PORT_OUT3 (*(RwReg *)0x41008190UL) /**< \brief (PORT) Data Output Value 3 */
+#define REG_PORT_OUTCLR3 (*(RwReg *)0x41008194UL) /**< \brief (PORT) Data Output Value Clear 3 */
+#define REG_PORT_OUTSET3 (*(RwReg *)0x41008198UL) /**< \brief (PORT) Data Output Value Set 3 */
+#define REG_PORT_OUTTGL3 (*(RwReg *)0x4100819CUL) /**< \brief (PORT) Data Output Value Toggle 3 */
+#define REG_PORT_IN3 (*(RoReg *)0x410081A0UL) /**< \brief (PORT) Data Input Value 3 */
+#define REG_PORT_CTRL3 (*(RwReg *)0x410081A4UL) /**< \brief (PORT) Control 3 */
+#define REG_PORT_WRCONFIG3 (*(WoReg *)0x410081A8UL) /**< \brief (PORT) Write Configuration 3 */
+#define REG_PORT_EVCTRL3 (*(RwReg *)0x410081ACUL) /**< \brief (PORT) Event Input Control 3 */
+#define REG_PORT_PMUX3 (*(RwReg *)0x410081B0UL) /**< \brief (PORT) Peripheral Multiplexing 3 */
+#define REG_PORT_PINCFG3 (*(RwReg *)0x410081C0UL) /**< \brief (PORT) Pin Configuration 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS 118
+#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_DRVSTR 1 // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_EV_NUM 4
+#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_ODRAIN 0 // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_PMUXBIT0_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }
+#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }
+#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT2_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }
+#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT3_IMPLEMENTED { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }
+#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_PPP_IMPLEMENTED { 0x00000001 } // IOBUS2 implemented?
+#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_SLEWLIM 0 // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+
+#endif /* _SAME54_PORT_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/pukcc.h b/GPIO/ATSAME54/include/instance/pukcc.h
new file mode 100644
index 0000000..1ce3860
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/pukcc.h
@@ -0,0 +1,57 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PUKCC
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_PUKCC_INSTANCE_
+#define _SAME54_PUKCC_INSTANCE_
+
+/* ========== Register definition for PUKCC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#else
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PUKCC peripheral ========== */
+#define PUKCC_CLK_AHB_ID 20
+#define PUKCC_RAM_ADDR_SIZE 12
+#define PUKCC_ROM_ADDR_SIZE 16
+
+#endif /* _SAME54_PUKCC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/qspi.h b/GPIO/ATSAME54/include/instance/qspi.h
new file mode 100644
index 0000000..bc7a0ab
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/qspi.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief Instance description for QSPI
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_QSPI_INSTANCE_
+#define _SAME54_QSPI_INSTANCE_
+
+/* ========== Register definition for QSPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_QSPI_CTRLA (0x42003400) /**< \brief (QSPI) Control A */
+#define REG_QSPI_CTRLB (0x42003404) /**< \brief (QSPI) Control B */
+#define REG_QSPI_BAUD (0x42003408) /**< \brief (QSPI) Baud Rate */
+#define REG_QSPI_RXDATA (0x4200340C) /**< \brief (QSPI) Receive Data */
+#define REG_QSPI_TXDATA (0x42003410) /**< \brief (QSPI) Transmit Data */
+#define REG_QSPI_INTENCLR (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */
+#define REG_QSPI_INTENSET (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */
+#define REG_QSPI_INTFLAG (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */
+#define REG_QSPI_STATUS (0x42003420) /**< \brief (QSPI) Status Register */
+#define REG_QSPI_INSTRADDR (0x42003430) /**< \brief (QSPI) Instruction Address */
+#define REG_QSPI_INSTRCTRL (0x42003434) /**< \brief (QSPI) Instruction Code */
+#define REG_QSPI_INSTRFRAME (0x42003438) /**< \brief (QSPI) Instruction Frame */
+#define REG_QSPI_SCRAMBCTRL (0x42003440) /**< \brief (QSPI) Scrambling Mode */
+#define REG_QSPI_SCRAMBKEY (0x42003444) /**< \brief (QSPI) Scrambling Key */
+#else
+#define REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (QSPI) Control A */
+#define REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) /**< \brief (QSPI) Control B */
+#define REG_QSPI_BAUD (*(RwReg *)0x42003408UL) /**< \brief (QSPI) Baud Rate */
+#define REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) /**< \brief (QSPI) Receive Data */
+#define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */
+#define REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */
+#define REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */
+#define REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */
+#define REG_QSPI_STATUS (*(RoReg *)0x42003420UL) /**< \brief (QSPI) Status Register */
+#define REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) /**< \brief (QSPI) Instruction Address */
+#define REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) /**< \brief (QSPI) Instruction Code */
+#define REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */
+#define REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */
+#define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for QSPI peripheral ========== */
+#define QSPI_DMAC_ID_RX 83
+#define QSPI_DMAC_ID_TX 84
+#define QSPI_HADDR_MSB 23
+#define QSPI_OCMS 1
+
+#endif /* _SAME54_QSPI_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/ramecc.h b/GPIO/ATSAME54/include/instance/ramecc.h
new file mode 100644
index 0000000..9fd9ae4
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/ramecc.h
@@ -0,0 +1,54 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RAMECC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RAMECC_INSTANCE_
+#define _SAME54_RAMECC_INSTANCE_
+
+/* ========== Register definition for RAMECC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RAMECC_INTENCLR (0x41020000) /**< \brief (RAMECC) Interrupt Enable Clear */
+#define REG_RAMECC_INTENSET (0x41020001) /**< \brief (RAMECC) Interrupt Enable Set */
+#define REG_RAMECC_INTFLAG (0x41020002) /**< \brief (RAMECC) Interrupt Flag */
+#define REG_RAMECC_STATUS (0x41020003) /**< \brief (RAMECC) Status */
+#define REG_RAMECC_ERRADDR (0x41020004) /**< \brief (RAMECC) Error Address */
+#define REG_RAMECC_DBGCTRL (0x4102000F) /**< \brief (RAMECC) Debug Control */
+#else
+#define REG_RAMECC_INTENCLR (*(RwReg8 *)0x41020000UL) /**< \brief (RAMECC) Interrupt Enable Clear */
+#define REG_RAMECC_INTENSET (*(RwReg8 *)0x41020001UL) /**< \brief (RAMECC) Interrupt Enable Set */
+#define REG_RAMECC_INTFLAG (*(RwReg8 *)0x41020002UL) /**< \brief (RAMECC) Interrupt Flag */
+#define REG_RAMECC_STATUS (*(RoReg8 *)0x41020003UL) /**< \brief (RAMECC) Status */
+#define REG_RAMECC_ERRADDR (*(RoReg *)0x41020004UL) /**< \brief (RAMECC) Error Address */
+#define REG_RAMECC_DBGCTRL (*(RwReg8 *)0x4102000FUL) /**< \brief (RAMECC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RAMECC peripheral ========== */
+#define RAMECC_RAMADDR_BITS 13 // Number of RAM address bits
+#define RAMECC_RAMBANK_NUM 4 // Number of RAM banks
+
+#endif /* _SAME54_RAMECC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/rstc.h b/GPIO/ATSAME54/include/instance/rstc.h
new file mode 100644
index 0000000..5e4299e
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/rstc.h
@@ -0,0 +1,48 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RSTC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RSTC_INSTANCE_
+#define _SAME54_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */
+#define REG_RSTC_BKUPEXIT (0x40000C02) /**< \brief (RSTC) Backup Exit Source */
+#else
+#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */
+#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RSTC peripheral ========== */
+#define RSTC_BACKUP_IMPLEMENTED 1
+#define RSTC_HIB_IMPLEMENTED 1
+#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line
+#define RSTC_NVMRST_IMPLEMENTED 1
+
+#endif /* _SAME54_RSTC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/rtc.h b/GPIO/ATSAME54/include/instance/rtc.h
new file mode 100644
index 0000000..96f3bbf
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/rtc.h
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_RTC_INSTANCE_
+#define _SAME54_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */
+#define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */
+#define REG_RTC_GP2 (0x40002448) /**< \brief (RTC) General Purpose 2 */
+#define REG_RTC_GP3 (0x4000244C) /**< \brief (RTC) General Purpose 3 */
+#define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */
+#define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */
+#define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */
+#define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */
+#define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */
+#define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */
+#define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */
+#define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */
+#define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */
+#define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */
+#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */
+#define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */
+#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
+#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE0_COMP1 (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */
+#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */
+#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */
+#define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */
+#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
+#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE1_COMP2 (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */
+#define REG_RTC_MODE1_COMP3 (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */
+#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */
+#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */
+#define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */
+#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
+#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
+#define REG_RTC_MODE2_ALARM_MASK1 (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
+#else
+#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */
+#define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */
+#define REG_RTC_GP2 (*(RwReg *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */
+#define REG_RTC_GP3 (*(RwReg *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */
+#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */
+#define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */
+#define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */
+#define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */
+#define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */
+#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */
+#define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */
+#define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */
+#define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */
+#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */
+#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
+#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */
+#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
+#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE0_COMP1 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */
+#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */
+#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
+#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */
+#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
+#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE1_COMP2 (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */
+#define REG_RTC_MODE1_COMP3 (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */
+#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */
+#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
+#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */
+#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
+#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
+#define REG_RTC_MODE2_ALARM_MASK1 (*(RwReg *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger
+#define RTC_GPR_NUM 4 // Number of General-Purpose Registers
+#define RTC_NUM_OF_ALARMS 2 // Number of Alarms
+#define RTC_NUM_OF_BKREGS 8 // Number of Backup Registers
+#define RTC_NUM_OF_COMP16 4 // Number of 16-bit Comparators
+#define RTC_NUM_OF_COMP32 2 // Number of 32-bit Comparators
+#define RTC_NUM_OF_TAMPERS 5 // Number of Tamper Inputs
+#define RTC_PER_NUM 8 // Number of Periodic Intervals
+
+#endif /* _SAME54_RTC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sdhc0.h b/GPIO/ATSAME54/include/instance/sdhc0.h
new file mode 100644
index 0000000..1921d38
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sdhc0.h
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SDHC0
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SDHC0_INSTANCE_
+#define _SAME54_SDHC0_INSTANCE_
+
+/* ========== Register definition for SDHC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SDHC0_SSAR (0x45000000) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
+#define REG_SDHC0_BSR (0x45000004) /**< \brief (SDHC0) Block Size */
+#define REG_SDHC0_BCR (0x45000006) /**< \brief (SDHC0) Block Count */
+#define REG_SDHC0_ARG1R (0x45000008) /**< \brief (SDHC0) Argument 1 */
+#define REG_SDHC0_TMR (0x4500000C) /**< \brief (SDHC0) Transfer Mode */
+#define REG_SDHC0_CR (0x4500000E) /**< \brief (SDHC0) Command */
+#define REG_SDHC0_RR0 (0x45000010) /**< \brief (SDHC0) Response 0 */
+#define REG_SDHC0_RR1 (0x45000014) /**< \brief (SDHC0) Response 1 */
+#define REG_SDHC0_RR2 (0x45000018) /**< \brief (SDHC0) Response 2 */
+#define REG_SDHC0_RR3 (0x4500001C) /**< \brief (SDHC0) Response 3 */
+#define REG_SDHC0_BDPR (0x45000020) /**< \brief (SDHC0) Buffer Data Port */
+#define REG_SDHC0_PSR (0x45000024) /**< \brief (SDHC0) Present State */
+#define REG_SDHC0_HC1R (0x45000028) /**< \brief (SDHC0) Host Control 1 */
+#define REG_SDHC0_PCR (0x45000029) /**< \brief (SDHC0) Power Control */
+#define REG_SDHC0_BGCR (0x4500002A) /**< \brief (SDHC0) Block Gap Control */
+#define REG_SDHC0_WCR (0x4500002B) /**< \brief (SDHC0) Wakeup Control */
+#define REG_SDHC0_CCR (0x4500002C) /**< \brief (SDHC0) Clock Control */
+#define REG_SDHC0_TCR (0x4500002E) /**< \brief (SDHC0) Timeout Control */
+#define REG_SDHC0_SRR (0x4500002F) /**< \brief (SDHC0) Software Reset */
+#define REG_SDHC0_NISTR (0x45000030) /**< \brief (SDHC0) Normal Interrupt Status */
+#define REG_SDHC0_EISTR (0x45000032) /**< \brief (SDHC0) Error Interrupt Status */
+#define REG_SDHC0_NISTER (0x45000034) /**< \brief (SDHC0) Normal Interrupt Status Enable */
+#define REG_SDHC0_EISTER (0x45000036) /**< \brief (SDHC0) Error Interrupt Status Enable */
+#define REG_SDHC0_NISIER (0x45000038) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
+#define REG_SDHC0_EISIER (0x4500003A) /**< \brief (SDHC0) Error Interrupt Signal Enable */
+#define REG_SDHC0_ACESR (0x4500003C) /**< \brief (SDHC0) Auto CMD Error Status */
+#define REG_SDHC0_HC2R (0x4500003E) /**< \brief (SDHC0) Host Control 2 */
+#define REG_SDHC0_CA0R (0x45000040) /**< \brief (SDHC0) Capabilities 0 */
+#define REG_SDHC0_CA1R (0x45000044) /**< \brief (SDHC0) Capabilities 1 */
+#define REG_SDHC0_MCCAR (0x45000048) /**< \brief (SDHC0) Maximum Current Capabilities */
+#define REG_SDHC0_FERACES (0x45000050) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
+#define REG_SDHC0_FEREIS (0x45000052) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
+#define REG_SDHC0_AESR (0x45000054) /**< \brief (SDHC0) ADMA Error Status */
+#define REG_SDHC0_ASAR0 (0x45000058) /**< \brief (SDHC0) ADMA System Address 0 */
+#define REG_SDHC0_PVR0 (0x45000060) /**< \brief (SDHC0) Preset Value 0 */
+#define REG_SDHC0_PVR1 (0x45000062) /**< \brief (SDHC0) Preset Value 1 */
+#define REG_SDHC0_PVR2 (0x45000064) /**< \brief (SDHC0) Preset Value 2 */
+#define REG_SDHC0_PVR3 (0x45000066) /**< \brief (SDHC0) Preset Value 3 */
+#define REG_SDHC0_PVR4 (0x45000068) /**< \brief (SDHC0) Preset Value 4 */
+#define REG_SDHC0_PVR5 (0x4500006A) /**< \brief (SDHC0) Preset Value 5 */
+#define REG_SDHC0_PVR6 (0x4500006C) /**< \brief (SDHC0) Preset Value 6 */
+#define REG_SDHC0_PVR7 (0x4500006E) /**< \brief (SDHC0) Preset Value 7 */
+#define REG_SDHC0_SISR (0x450000FC) /**< \brief (SDHC0) Slot Interrupt Status */
+#define REG_SDHC0_HCVR (0x450000FE) /**< \brief (SDHC0) Host Controller Version */
+#define REG_SDHC0_MC1R (0x45000204) /**< \brief (SDHC0) MMC Control 1 */
+#define REG_SDHC0_MC2R (0x45000205) /**< \brief (SDHC0) MMC Control 2 */
+#define REG_SDHC0_ACR (0x45000208) /**< \brief (SDHC0) AHB Control */
+#define REG_SDHC0_CC2R (0x4500020C) /**< \brief (SDHC0) Clock Control 2 */
+#define REG_SDHC0_CACR (0x45000230) /**< \brief (SDHC0) Capabilities Control */
+#define REG_SDHC0_DBGR (0x45000234) /**< \brief (SDHC0) Debug */
+#else
+#define REG_SDHC0_SSAR (*(RwReg *)0x45000000UL) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
+#define REG_SDHC0_BSR (*(RwReg16*)0x45000004UL) /**< \brief (SDHC0) Block Size */
+#define REG_SDHC0_BCR (*(RwReg16*)0x45000006UL) /**< \brief (SDHC0) Block Count */
+#define REG_SDHC0_ARG1R (*(RwReg *)0x45000008UL) /**< \brief (SDHC0) Argument 1 */
+#define REG_SDHC0_TMR (*(RwReg16*)0x4500000CUL) /**< \brief (SDHC0) Transfer Mode */
+#define REG_SDHC0_CR (*(RwReg16*)0x4500000EUL) /**< \brief (SDHC0) Command */
+#define REG_SDHC0_RR0 (*(RoReg *)0x45000010UL) /**< \brief (SDHC0) Response 0 */
+#define REG_SDHC0_RR1 (*(RoReg *)0x45000014UL) /**< \brief (SDHC0) Response 1 */
+#define REG_SDHC0_RR2 (*(RoReg *)0x45000018UL) /**< \brief (SDHC0) Response 2 */
+#define REG_SDHC0_RR3 (*(RoReg *)0x4500001CUL) /**< \brief (SDHC0) Response 3 */
+#define REG_SDHC0_BDPR (*(RwReg *)0x45000020UL) /**< \brief (SDHC0) Buffer Data Port */
+#define REG_SDHC0_PSR (*(RoReg *)0x45000024UL) /**< \brief (SDHC0) Present State */
+#define REG_SDHC0_HC1R (*(RwReg8 *)0x45000028UL) /**< \brief (SDHC0) Host Control 1 */
+#define REG_SDHC0_PCR (*(RwReg8 *)0x45000029UL) /**< \brief (SDHC0) Power Control */
+#define REG_SDHC0_BGCR (*(RwReg8 *)0x4500002AUL) /**< \brief (SDHC0) Block Gap Control */
+#define REG_SDHC0_WCR (*(RwReg8 *)0x4500002BUL) /**< \brief (SDHC0) Wakeup Control */
+#define REG_SDHC0_CCR (*(RwReg16*)0x4500002CUL) /**< \brief (SDHC0) Clock Control */
+#define REG_SDHC0_TCR (*(RwReg8 *)0x4500002EUL) /**< \brief (SDHC0) Timeout Control */
+#define REG_SDHC0_SRR (*(RwReg8 *)0x4500002FUL) /**< \brief (SDHC0) Software Reset */
+#define REG_SDHC0_NISTR (*(RwReg16*)0x45000030UL) /**< \brief (SDHC0) Normal Interrupt Status */
+#define REG_SDHC0_EISTR (*(RwReg16*)0x45000032UL) /**< \brief (SDHC0) Error Interrupt Status */
+#define REG_SDHC0_NISTER (*(RwReg16*)0x45000034UL) /**< \brief (SDHC0) Normal Interrupt Status Enable */
+#define REG_SDHC0_EISTER (*(RwReg16*)0x45000036UL) /**< \brief (SDHC0) Error Interrupt Status Enable */
+#define REG_SDHC0_NISIER (*(RwReg16*)0x45000038UL) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
+#define REG_SDHC0_EISIER (*(RwReg16*)0x4500003AUL) /**< \brief (SDHC0) Error Interrupt Signal Enable */
+#define REG_SDHC0_ACESR (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Status */
+#define REG_SDHC0_HC2R (*(RwReg16*)0x4500003EUL) /**< \brief (SDHC0) Host Control 2 */
+#define REG_SDHC0_CA0R (*(RoReg *)0x45000040UL) /**< \brief (SDHC0) Capabilities 0 */
+#define REG_SDHC0_CA1R (*(RoReg *)0x45000044UL) /**< \brief (SDHC0) Capabilities 1 */
+#define REG_SDHC0_MCCAR (*(RoReg *)0x45000048UL) /**< \brief (SDHC0) Maximum Current Capabilities */
+#define REG_SDHC0_FERACES (*(WoReg16*)0x45000050UL) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
+#define REG_SDHC0_FEREIS (*(WoReg16*)0x45000052UL) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
+#define REG_SDHC0_AESR (*(RoReg8 *)0x45000054UL) /**< \brief (SDHC0) ADMA Error Status */
+#define REG_SDHC0_ASAR0 (*(RwReg *)0x45000058UL) /**< \brief (SDHC0) ADMA System Address 0 */
+#define REG_SDHC0_PVR0 (*(RwReg16*)0x45000060UL) /**< \brief (SDHC0) Preset Value 0 */
+#define REG_SDHC0_PVR1 (*(RwReg16*)0x45000062UL) /**< \brief (SDHC0) Preset Value 1 */
+#define REG_SDHC0_PVR2 (*(RwReg16*)0x45000064UL) /**< \brief (SDHC0) Preset Value 2 */
+#define REG_SDHC0_PVR3 (*(RwReg16*)0x45000066UL) /**< \brief (SDHC0) Preset Value 3 */
+#define REG_SDHC0_PVR4 (*(RwReg16*)0x45000068UL) /**< \brief (SDHC0) Preset Value 4 */
+#define REG_SDHC0_PVR5 (*(RwReg16*)0x4500006AUL) /**< \brief (SDHC0) Preset Value 5 */
+#define REG_SDHC0_PVR6 (*(RwReg16*)0x4500006CUL) /**< \brief (SDHC0) Preset Value 6 */
+#define REG_SDHC0_PVR7 (*(RwReg16*)0x4500006EUL) /**< \brief (SDHC0) Preset Value 7 */
+#define REG_SDHC0_SISR (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Status */
+#define REG_SDHC0_HCVR (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Version */
+#define REG_SDHC0_MC1R (*(RwReg8 *)0x45000204UL) /**< \brief (SDHC0) MMC Control 1 */
+#define REG_SDHC0_MC2R (*(WoReg8 *)0x45000205UL) /**< \brief (SDHC0) MMC Control 2 */
+#define REG_SDHC0_ACR (*(RwReg *)0x45000208UL) /**< \brief (SDHC0) AHB Control */
+#define REG_SDHC0_CC2R (*(RwReg *)0x4500020CUL) /**< \brief (SDHC0) Clock Control 2 */
+#define REG_SDHC0_CACR (*(RwReg *)0x45000230UL) /**< \brief (SDHC0) Capabilities Control */
+#define REG_SDHC0_DBGR (*(RwReg8 *)0x45000234UL) /**< \brief (SDHC0) Debug */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SDHC0 peripheral ========== */
+#define SDHC0_CARD_DATA_SIZE 4
+#define SDHC0_CLK_AHB_ID 15
+#define SDHC0_GCLK_ID 45
+#define SDHC0_GCLK_ID_SLOW 3
+#define SDHC0_NB_OF_DEVICES 1
+#define SDHC0_NB_REG_PVR 8
+#define SDHC0_NB_REG_RR 4
+
+#endif /* _SAME54_SDHC0_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sdhc1.h b/GPIO/ATSAME54/include/instance/sdhc1.h
new file mode 100644
index 0000000..2cec92a
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sdhc1.h
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SDHC1
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SDHC1_INSTANCE_
+#define _SAME54_SDHC1_INSTANCE_
+
+/* ========== Register definition for SDHC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SDHC1_SSAR (0x46000000) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
+#define REG_SDHC1_BSR (0x46000004) /**< \brief (SDHC1) Block Size */
+#define REG_SDHC1_BCR (0x46000006) /**< \brief (SDHC1) Block Count */
+#define REG_SDHC1_ARG1R (0x46000008) /**< \brief (SDHC1) Argument 1 */
+#define REG_SDHC1_TMR (0x4600000C) /**< \brief (SDHC1) Transfer Mode */
+#define REG_SDHC1_CR (0x4600000E) /**< \brief (SDHC1) Command */
+#define REG_SDHC1_RR0 (0x46000010) /**< \brief (SDHC1) Response 0 */
+#define REG_SDHC1_RR1 (0x46000014) /**< \brief (SDHC1) Response 1 */
+#define REG_SDHC1_RR2 (0x46000018) /**< \brief (SDHC1) Response 2 */
+#define REG_SDHC1_RR3 (0x4600001C) /**< \brief (SDHC1) Response 3 */
+#define REG_SDHC1_BDPR (0x46000020) /**< \brief (SDHC1) Buffer Data Port */
+#define REG_SDHC1_PSR (0x46000024) /**< \brief (SDHC1) Present State */
+#define REG_SDHC1_HC1R (0x46000028) /**< \brief (SDHC1) Host Control 1 */
+#define REG_SDHC1_PCR (0x46000029) /**< \brief (SDHC1) Power Control */
+#define REG_SDHC1_BGCR (0x4600002A) /**< \brief (SDHC1) Block Gap Control */
+#define REG_SDHC1_WCR (0x4600002B) /**< \brief (SDHC1) Wakeup Control */
+#define REG_SDHC1_CCR (0x4600002C) /**< \brief (SDHC1) Clock Control */
+#define REG_SDHC1_TCR (0x4600002E) /**< \brief (SDHC1) Timeout Control */
+#define REG_SDHC1_SRR (0x4600002F) /**< \brief (SDHC1) Software Reset */
+#define REG_SDHC1_NISTR (0x46000030) /**< \brief (SDHC1) Normal Interrupt Status */
+#define REG_SDHC1_EISTR (0x46000032) /**< \brief (SDHC1) Error Interrupt Status */
+#define REG_SDHC1_NISTER (0x46000034) /**< \brief (SDHC1) Normal Interrupt Status Enable */
+#define REG_SDHC1_EISTER (0x46000036) /**< \brief (SDHC1) Error Interrupt Status Enable */
+#define REG_SDHC1_NISIER (0x46000038) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
+#define REG_SDHC1_EISIER (0x4600003A) /**< \brief (SDHC1) Error Interrupt Signal Enable */
+#define REG_SDHC1_ACESR (0x4600003C) /**< \brief (SDHC1) Auto CMD Error Status */
+#define REG_SDHC1_HC2R (0x4600003E) /**< \brief (SDHC1) Host Control 2 */
+#define REG_SDHC1_CA0R (0x46000040) /**< \brief (SDHC1) Capabilities 0 */
+#define REG_SDHC1_CA1R (0x46000044) /**< \brief (SDHC1) Capabilities 1 */
+#define REG_SDHC1_MCCAR (0x46000048) /**< \brief (SDHC1) Maximum Current Capabilities */
+#define REG_SDHC1_FERACES (0x46000050) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
+#define REG_SDHC1_FEREIS (0x46000052) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
+#define REG_SDHC1_AESR (0x46000054) /**< \brief (SDHC1) ADMA Error Status */
+#define REG_SDHC1_ASAR0 (0x46000058) /**< \brief (SDHC1) ADMA System Address 0 */
+#define REG_SDHC1_PVR0 (0x46000060) /**< \brief (SDHC1) Preset Value 0 */
+#define REG_SDHC1_PVR1 (0x46000062) /**< \brief (SDHC1) Preset Value 1 */
+#define REG_SDHC1_PVR2 (0x46000064) /**< \brief (SDHC1) Preset Value 2 */
+#define REG_SDHC1_PVR3 (0x46000066) /**< \brief (SDHC1) Preset Value 3 */
+#define REG_SDHC1_PVR4 (0x46000068) /**< \brief (SDHC1) Preset Value 4 */
+#define REG_SDHC1_PVR5 (0x4600006A) /**< \brief (SDHC1) Preset Value 5 */
+#define REG_SDHC1_PVR6 (0x4600006C) /**< \brief (SDHC1) Preset Value 6 */
+#define REG_SDHC1_PVR7 (0x4600006E) /**< \brief (SDHC1) Preset Value 7 */
+#define REG_SDHC1_SISR (0x460000FC) /**< \brief (SDHC1) Slot Interrupt Status */
+#define REG_SDHC1_HCVR (0x460000FE) /**< \brief (SDHC1) Host Controller Version */
+#define REG_SDHC1_MC1R (0x46000204) /**< \brief (SDHC1) MMC Control 1 */
+#define REG_SDHC1_MC2R (0x46000205) /**< \brief (SDHC1) MMC Control 2 */
+#define REG_SDHC1_ACR (0x46000208) /**< \brief (SDHC1) AHB Control */
+#define REG_SDHC1_CC2R (0x4600020C) /**< \brief (SDHC1) Clock Control 2 */
+#define REG_SDHC1_CACR (0x46000230) /**< \brief (SDHC1) Capabilities Control */
+#define REG_SDHC1_DBGR (0x46000234) /**< \brief (SDHC1) Debug */
+#else
+#define REG_SDHC1_SSAR (*(RwReg *)0x46000000UL) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
+#define REG_SDHC1_BSR (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */
+#define REG_SDHC1_BCR (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */
+#define REG_SDHC1_ARG1R (*(RwReg *)0x46000008UL) /**< \brief (SDHC1) Argument 1 */
+#define REG_SDHC1_TMR (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */
+#define REG_SDHC1_CR (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */
+#define REG_SDHC1_RR0 (*(RoReg *)0x46000010UL) /**< \brief (SDHC1) Response 0 */
+#define REG_SDHC1_RR1 (*(RoReg *)0x46000014UL) /**< \brief (SDHC1) Response 1 */
+#define REG_SDHC1_RR2 (*(RoReg *)0x46000018UL) /**< \brief (SDHC1) Response 2 */
+#define REG_SDHC1_RR3 (*(RoReg *)0x4600001CUL) /**< \brief (SDHC1) Response 3 */
+#define REG_SDHC1_BDPR (*(RwReg *)0x46000020UL) /**< \brief (SDHC1) Buffer Data Port */
+#define REG_SDHC1_PSR (*(RoReg *)0x46000024UL) /**< \brief (SDHC1) Present State */
+#define REG_SDHC1_HC1R (*(RwReg8 *)0x46000028UL) /**< \brief (SDHC1) Host Control 1 */
+#define REG_SDHC1_PCR (*(RwReg8 *)0x46000029UL) /**< \brief (SDHC1) Power Control */
+#define REG_SDHC1_BGCR (*(RwReg8 *)0x4600002AUL) /**< \brief (SDHC1) Block Gap Control */
+#define REG_SDHC1_WCR (*(RwReg8 *)0x4600002BUL) /**< \brief (SDHC1) Wakeup Control */
+#define REG_SDHC1_CCR (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */
+#define REG_SDHC1_TCR (*(RwReg8 *)0x4600002EUL) /**< \brief (SDHC1) Timeout Control */
+#define REG_SDHC1_SRR (*(RwReg8 *)0x4600002FUL) /**< \brief (SDHC1) Software Reset */
+#define REG_SDHC1_NISTR (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt Status */
+#define REG_SDHC1_EISTR (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt Status */
+#define REG_SDHC1_NISTER (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt Status Enable */
+#define REG_SDHC1_EISTER (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt Status Enable */
+#define REG_SDHC1_NISIER (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
+#define REG_SDHC1_EISIER (*(RwReg16*)0x4600003AUL) /**< \brief (SDHC1) Error Interrupt Signal Enable */
+#define REG_SDHC1_ACESR (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Status */
+#define REG_SDHC1_HC2R (*(RwReg16*)0x4600003EUL) /**< \brief (SDHC1) Host Control 2 */
+#define REG_SDHC1_CA0R (*(RoReg *)0x46000040UL) /**< \brief (SDHC1) Capabilities 0 */
+#define REG_SDHC1_CA1R (*(RoReg *)0x46000044UL) /**< \brief (SDHC1) Capabilities 1 */
+#define REG_SDHC1_MCCAR (*(RoReg *)0x46000048UL) /**< \brief (SDHC1) Maximum Current Capabilities */
+#define REG_SDHC1_FERACES (*(WoReg16*)0x46000050UL) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
+#define REG_SDHC1_FEREIS (*(WoReg16*)0x46000052UL) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
+#define REG_SDHC1_AESR (*(RoReg8 *)0x46000054UL) /**< \brief (SDHC1) ADMA Error Status */
+#define REG_SDHC1_ASAR0 (*(RwReg *)0x46000058UL) /**< \brief (SDHC1) ADMA System Address 0 */
+#define REG_SDHC1_PVR0 (*(RwReg16*)0x46000060UL) /**< \brief (SDHC1) Preset Value 0 */
+#define REG_SDHC1_PVR1 (*(RwReg16*)0x46000062UL) /**< \brief (SDHC1) Preset Value 1 */
+#define REG_SDHC1_PVR2 (*(RwReg16*)0x46000064UL) /**< \brief (SDHC1) Preset Value 2 */
+#define REG_SDHC1_PVR3 (*(RwReg16*)0x46000066UL) /**< \brief (SDHC1) Preset Value 3 */
+#define REG_SDHC1_PVR4 (*(RwReg16*)0x46000068UL) /**< \brief (SDHC1) Preset Value 4 */
+#define REG_SDHC1_PVR5 (*(RwReg16*)0x4600006AUL) /**< \brief (SDHC1) Preset Value 5 */
+#define REG_SDHC1_PVR6 (*(RwReg16*)0x4600006CUL) /**< \brief (SDHC1) Preset Value 6 */
+#define REG_SDHC1_PVR7 (*(RwReg16*)0x4600006EUL) /**< \brief (SDHC1) Preset Value 7 */
+#define REG_SDHC1_SISR (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Status */
+#define REG_SDHC1_HCVR (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Version */
+#define REG_SDHC1_MC1R (*(RwReg8 *)0x46000204UL) /**< \brief (SDHC1) MMC Control 1 */
+#define REG_SDHC1_MC2R (*(WoReg8 *)0x46000205UL) /**< \brief (SDHC1) MMC Control 2 */
+#define REG_SDHC1_ACR (*(RwReg *)0x46000208UL) /**< \brief (SDHC1) AHB Control */
+#define REG_SDHC1_CC2R (*(RwReg *)0x4600020CUL) /**< \brief (SDHC1) Clock Control 2 */
+#define REG_SDHC1_CACR (*(RwReg *)0x46000230UL) /**< \brief (SDHC1) Capabilities Control */
+#define REG_SDHC1_DBGR (*(RwReg8 *)0x46000234UL) /**< \brief (SDHC1) Debug */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SDHC1 peripheral ========== */
+#define SDHC1_CARD_DATA_SIZE 4
+#define SDHC1_CLK_AHB_ID 16
+#define SDHC1_GCLK_ID 46
+#define SDHC1_GCLK_ID_SLOW 3
+#define SDHC1_NB_OF_DEVICES 1
+#define SDHC1_NB_REG_PVR 8
+#define SDHC1_NB_REG_RR 4
+
+#endif /* _SAME54_SDHC1_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom0.h b/GPIO/ATSAME54/include/instance/sercom0.h
new file mode 100644
index 0000000..ecf84d4
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom0.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM0_INSTANCE_
+#define _SAME54_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA (0x40003000) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (0x40003004) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_CTRLC (0x40003008) /**< \brief (SERCOM0) I2CM Control C */
+#define REG_SERCOM0_I2CM_BAUD (0x4000300C) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (0x40003014) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (0x40003016) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (0x40003018) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (0x4000301A) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR (0x40003024) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (0x40003028) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (0x40003030) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (0x40003000) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (0x40003004) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_CTRLC (0x40003008) /**< \brief (SERCOM0) I2CS Control C */
+#define REG_SERCOM0_I2CS_INTENCLR (0x40003014) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (0x40003016) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (0x40003018) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (0x4000301A) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_LENGTH (0x40003022) /**< \brief (SERCOM0) I2CS Length */
+#define REG_SERCOM0_I2CS_ADDR (0x40003024) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (0x40003028) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (0x40003000) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (0x40003004) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_CTRLC (0x40003008) /**< \brief (SERCOM0) SPI Control C */
+#define REG_SERCOM0_SPI_BAUD (0x4000300C) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (0x40003014) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (0x40003016) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (0x40003018) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (0x4000301A) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_LENGTH (0x40003022) /**< \brief (SERCOM0) SPI Length */
+#define REG_SERCOM0_SPI_ADDR (0x40003024) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (0x40003028) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (0x40003030) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (0x40003000) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (0x40003004) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_CTRLC (0x40003008) /**< \brief (SERCOM0) USART Control C */
+#define REG_SERCOM0_USART_BAUD (0x4000300C) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (0x4000300E) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x40003014) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x40003016) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (0x40003018) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (0x4000301A) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_RXERRCNT (0x40003020) /**< \brief (SERCOM0) USART Receive Error Count */
+#define REG_SERCOM0_USART_LENGTH (0x40003022) /**< \brief (SERCOM0) USART Length */
+#define REG_SERCOM0_USART_DATA (0x40003028) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (0x40003030) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) I2CM Control C */
+#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4000300CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) I2CS Control C */
+#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) I2CS Length */
+#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) SPI Control C */
+#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4000300CUL) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) SPI Length */
+#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) USART Control C */
+#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4000300CUL) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4000300EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x40003020UL) /**< \brief (SERCOM0) USART Receive Error Count */
+#define REG_SERCOM0_USART_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) USART Length */
+#define REG_SERCOM0_USART_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM0_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM0_DMA 1 // DMA support implemented?
+#define SERCOM0_DMAC_ID_RX 4 // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX 5 // Index of DMA TX trigger
+#define SERCOM0_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM0_GCLK_ID_CORE 7
+#define SERCOM0_GCLK_ID_SLOW 3
+#define SERCOM0_INT_MSB 6
+#define SERCOM0_PMSB 3
+#define SERCOM0_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM0_SE_CNT 1 // SE counter included?
+#define SERCOM0_SPI 1 // SPI mode implemented?
+#define SERCOM0_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM0_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM0_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM0_TWIM 1 // TWI Master mode implemented?
+#define SERCOM0_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM0_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM0_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM0_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM0_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM0_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM0_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM0_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM0_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM0_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM0_USART 1 // USART mode implemented?
+#define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM0_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM0_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM0_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM0_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM0_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM0_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM0_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM0_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom1.h b/GPIO/ATSAME54/include/instance/sercom1.h
new file mode 100644
index 0000000..960e585
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom1.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM1_INSTANCE_
+#define _SAME54_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CM Control C */
+#define REG_SERCOM1_I2CM_BAUD (0x4000340C) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR (0x40003424) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (0x40003428) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (0x40003430) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CS Control C */
+#define REG_SERCOM1_I2CS_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_LENGTH (0x40003422) /**< \brief (SERCOM1) I2CS Length */
+#define REG_SERCOM1_I2CS_ADDR (0x40003424) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (0x40003428) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (0x40003400) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (0x40003404) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_CTRLC (0x40003408) /**< \brief (SERCOM1) SPI Control C */
+#define REG_SERCOM1_SPI_BAUD (0x4000340C) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (0x40003414) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (0x40003416) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (0x40003418) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (0x4000341A) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_LENGTH (0x40003422) /**< \brief (SERCOM1) SPI Length */
+#define REG_SERCOM1_SPI_ADDR (0x40003424) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (0x40003428) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (0x40003430) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (0x40003400) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (0x40003404) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_CTRLC (0x40003408) /**< \brief (SERCOM1) USART Control C */
+#define REG_SERCOM1_USART_BAUD (0x4000340C) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (0x4000340E) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x40003414) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x40003416) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (0x40003418) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (0x4000341A) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_RXERRCNT (0x40003420) /**< \brief (SERCOM1) USART Receive Error Count */
+#define REG_SERCOM1_USART_LENGTH (0x40003422) /**< \brief (SERCOM1) USART Length */
+#define REG_SERCOM1_USART_DATA (0x40003428) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (0x40003430) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CM Control C */
+#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4000340CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CS Control C */
+#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) I2CS Length */
+#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) SPI Control C */
+#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4000340CUL) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) SPI Length */
+#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) USART Control C */
+#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4000340CUL) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4000340EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL) /**< \brief (SERCOM1) USART Receive Error Count */
+#define REG_SERCOM1_USART_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) USART Length */
+#define REG_SERCOM1_USART_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM1_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM1_DMA 1 // DMA support implemented?
+#define SERCOM1_DMAC_ID_RX 6 // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX 7 // Index of DMA TX trigger
+#define SERCOM1_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM1_GCLK_ID_CORE 8
+#define SERCOM1_GCLK_ID_SLOW 3
+#define SERCOM1_INT_MSB 6
+#define SERCOM1_PMSB 3
+#define SERCOM1_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM1_SE_CNT 1 // SE counter included?
+#define SERCOM1_SPI 1 // SPI mode implemented?
+#define SERCOM1_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM1_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM1_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM1_TWIM 1 // TWI Master mode implemented?
+#define SERCOM1_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM1_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM1_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM1_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM1_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM1_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM1_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM1_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM1_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM1_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM1_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM1_USART 1 // USART mode implemented?
+#define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM1_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM1_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM1_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM1_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM1_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM1_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM1_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM1_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom2.h b/GPIO/ATSAME54/include/instance/sercom2.h
new file mode 100644
index 0000000..38efd63
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom2.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM2_INSTANCE_
+#define _SAME54_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA (0x41012000) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (0x41012004) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_CTRLC (0x41012008) /**< \brief (SERCOM2) I2CM Control C */
+#define REG_SERCOM2_I2CM_BAUD (0x4101200C) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (0x41012014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (0x41012016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (0x41012018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (0x4101201A) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (0x4101201C) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR (0x41012024) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (0x41012028) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (0x41012030) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (0x41012000) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (0x41012004) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_CTRLC (0x41012008) /**< \brief (SERCOM2) I2CS Control C */
+#define REG_SERCOM2_I2CS_INTENCLR (0x41012014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (0x41012016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (0x41012018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (0x4101201A) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (0x4101201C) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_LENGTH (0x41012022) /**< \brief (SERCOM2) I2CS Length */
+#define REG_SERCOM2_I2CS_ADDR (0x41012024) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (0x41012028) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (0x41012000) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (0x41012004) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_CTRLC (0x41012008) /**< \brief (SERCOM2) SPI Control C */
+#define REG_SERCOM2_SPI_BAUD (0x4101200C) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (0x41012014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (0x41012016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (0x41012018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (0x4101201A) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (0x4101201C) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_LENGTH (0x41012022) /**< \brief (SERCOM2) SPI Length */
+#define REG_SERCOM2_SPI_ADDR (0x41012024) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (0x41012028) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (0x41012030) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (0x41012000) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (0x41012004) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_CTRLC (0x41012008) /**< \brief (SERCOM2) USART Control C */
+#define REG_SERCOM2_USART_BAUD (0x4101200C) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (0x4101200E) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x41012014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x41012016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (0x41012018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (0x4101201A) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4101201C) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_RXERRCNT (0x41012020) /**< \brief (SERCOM2) USART Receive Error Count */
+#define REG_SERCOM2_USART_LENGTH (0x41012022) /**< \brief (SERCOM2) USART Length */
+#define REG_SERCOM2_USART_DATA (0x41012028) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (0x41012030) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x41012000UL) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x41012004UL) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_CTRLC (*(RwReg *)0x41012008UL) /**< \brief (SERCOM2) I2CM Control C */
+#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4101200CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4101201CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x41012024UL) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (*(RwReg *)0x41012028UL) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x41012000UL) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x41012004UL) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_CTRLC (*(RwReg *)0x41012008UL) /**< \brief (SERCOM2) I2CS Control C */
+#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4101201CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_LENGTH (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) I2CS Length */
+#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x41012024UL) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (*(RwReg *)0x41012028UL) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x41012000UL) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x41012004UL) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_CTRLC (*(RwReg *)0x41012008UL) /**< \brief (SERCOM2) SPI Control C */
+#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4101200CUL) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4101201CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_LENGTH (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) SPI Length */
+#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x41012024UL) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x41012028UL) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x41012000UL) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x41012004UL) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x41012008UL) /**< \brief (SERCOM2) USART Control C */
+#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4101200CUL) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4101200EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4101201CUL) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x41012020UL) /**< \brief (SERCOM2) USART Receive Error Count */
+#define REG_SERCOM2_USART_LENGTH (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) USART Length */
+#define REG_SERCOM2_USART_DATA (*(RwReg *)0x41012028UL) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM2_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM2_DMA 1 // DMA support implemented?
+#define SERCOM2_DMAC_ID_RX 8 // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX 9 // Index of DMA TX trigger
+#define SERCOM2_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM2_GCLK_ID_CORE 23
+#define SERCOM2_GCLK_ID_SLOW 3
+#define SERCOM2_INT_MSB 6
+#define SERCOM2_PMSB 3
+#define SERCOM2_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM2_SE_CNT 1 // SE counter included?
+#define SERCOM2_SPI 1 // SPI mode implemented?
+#define SERCOM2_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM2_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM2_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM2_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM2_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM2_TWIM 1 // TWI Master mode implemented?
+#define SERCOM2_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM2_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM2_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM2_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM2_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM2_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM2_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM2_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM2_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM2_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM2_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM2_USART 1 // USART mode implemented?
+#define SERCOM2_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM2_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM2_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM2_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM2_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM2_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM2_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM2_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM2_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM2_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM2_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom3.h b/GPIO/ATSAME54/include/instance/sercom3.h
new file mode 100644
index 0000000..f6e8626
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom3.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM3_INSTANCE_
+#define _SAME54_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA (0x41014000) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (0x41014004) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_CTRLC (0x41014008) /**< \brief (SERCOM3) I2CM Control C */
+#define REG_SERCOM3_I2CM_BAUD (0x4101400C) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (0x41014014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (0x41014016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (0x41014018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (0x4101401A) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (0x4101401C) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR (0x41014024) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (0x41014028) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (0x41014030) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (0x41014000) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (0x41014004) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_CTRLC (0x41014008) /**< \brief (SERCOM3) I2CS Control C */
+#define REG_SERCOM3_I2CS_INTENCLR (0x41014014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (0x41014016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (0x41014018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (0x4101401A) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (0x4101401C) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_LENGTH (0x41014022) /**< \brief (SERCOM3) I2CS Length */
+#define REG_SERCOM3_I2CS_ADDR (0x41014024) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (0x41014028) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (0x41014000) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (0x41014004) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_CTRLC (0x41014008) /**< \brief (SERCOM3) SPI Control C */
+#define REG_SERCOM3_SPI_BAUD (0x4101400C) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (0x41014014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (0x41014016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (0x41014018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (0x4101401A) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (0x4101401C) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_LENGTH (0x41014022) /**< \brief (SERCOM3) SPI Length */
+#define REG_SERCOM3_SPI_ADDR (0x41014024) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (0x41014028) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (0x41014030) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (0x41014000) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (0x41014004) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_CTRLC (0x41014008) /**< \brief (SERCOM3) USART Control C */
+#define REG_SERCOM3_USART_BAUD (0x4101400C) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (0x4101400E) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x41014014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x41014016) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (0x41014018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (0x4101401A) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4101401C) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_RXERRCNT (0x41014020) /**< \brief (SERCOM3) USART Receive Error Count */
+#define REG_SERCOM3_USART_LENGTH (0x41014022) /**< \brief (SERCOM3) USART Length */
+#define REG_SERCOM3_USART_DATA (0x41014028) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (0x41014030) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x41014000UL) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x41014004UL) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_CTRLC (*(RwReg *)0x41014008UL) /**< \brief (SERCOM3) I2CM Control C */
+#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4101400CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4101401CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x41014024UL) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (*(RwReg *)0x41014028UL) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x41014000UL) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x41014004UL) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_CTRLC (*(RwReg *)0x41014008UL) /**< \brief (SERCOM3) I2CS Control C */
+#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4101401CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_LENGTH (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) I2CS Length */
+#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x41014024UL) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (*(RwReg *)0x41014028UL) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x41014000UL) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x41014004UL) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_CTRLC (*(RwReg *)0x41014008UL) /**< \brief (SERCOM3) SPI Control C */
+#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4101400CUL) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4101401CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_LENGTH (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) SPI Length */
+#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x41014024UL) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x41014028UL) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x41014000UL) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x41014004UL) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x41014008UL) /**< \brief (SERCOM3) USART Control C */
+#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4101400CUL) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4101400EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4101401CUL) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x41014020UL) /**< \brief (SERCOM3) USART Receive Error Count */
+#define REG_SERCOM3_USART_LENGTH (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) USART Length */
+#define REG_SERCOM3_USART_DATA (*(RwReg *)0x41014028UL) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM3_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM3_DMA 1 // DMA support implemented?
+#define SERCOM3_DMAC_ID_RX 10 // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX 11 // Index of DMA TX trigger
+#define SERCOM3_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM3_GCLK_ID_CORE 24
+#define SERCOM3_GCLK_ID_SLOW 3
+#define SERCOM3_INT_MSB 6
+#define SERCOM3_PMSB 3
+#define SERCOM3_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM3_SE_CNT 1 // SE counter included?
+#define SERCOM3_SPI 1 // SPI mode implemented?
+#define SERCOM3_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM3_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM3_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM3_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM3_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM3_TWIM 1 // TWI Master mode implemented?
+#define SERCOM3_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM3_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM3_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM3_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM3_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM3_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM3_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM3_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM3_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM3_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM3_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM3_USART 1 // USART mode implemented?
+#define SERCOM3_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM3_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM3_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM3_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM3_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM3_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM3_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM3_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM3_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom4.h b/GPIO/ATSAME54/include/instance/sercom4.h
new file mode 100644
index 0000000..295474c
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom4.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM4_INSTANCE_
+#define _SAME54_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA (0x43000000) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (0x43000004) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_CTRLC (0x43000008) /**< \brief (SERCOM4) I2CM Control C */
+#define REG_SERCOM4_I2CM_BAUD (0x4300000C) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (0x43000014) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (0x43000016) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (0x43000018) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (0x4300001A) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (0x4300001C) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR (0x43000024) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (0x43000028) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (0x43000030) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (0x43000000) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (0x43000004) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_CTRLC (0x43000008) /**< \brief (SERCOM4) I2CS Control C */
+#define REG_SERCOM4_I2CS_INTENCLR (0x43000014) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (0x43000016) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (0x43000018) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (0x4300001A) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (0x4300001C) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_LENGTH (0x43000022) /**< \brief (SERCOM4) I2CS Length */
+#define REG_SERCOM4_I2CS_ADDR (0x43000024) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (0x43000028) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (0x43000000) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (0x43000004) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_CTRLC (0x43000008) /**< \brief (SERCOM4) SPI Control C */
+#define REG_SERCOM4_SPI_BAUD (0x4300000C) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (0x43000014) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (0x43000018) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (0x4300001A) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (0x4300001C) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_LENGTH (0x43000022) /**< \brief (SERCOM4) SPI Length */
+#define REG_SERCOM4_SPI_ADDR (0x43000024) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (0x43000028) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (0x43000030) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (0x43000000) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (0x43000004) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_CTRLC (0x43000008) /**< \brief (SERCOM4) USART Control C */
+#define REG_SERCOM4_USART_BAUD (0x4300000C) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (0x4300000E) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x43000014) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x43000016) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (0x43000018) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (0x4300001A) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4300001C) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_RXERRCNT (0x43000020) /**< \brief (SERCOM4) USART Receive Error Count */
+#define REG_SERCOM4_USART_LENGTH (0x43000022) /**< \brief (SERCOM4) USART Length */
+#define REG_SERCOM4_USART_DATA (0x43000028) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (0x43000030) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x43000000UL) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x43000004UL) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_CTRLC (*(RwReg *)0x43000008UL) /**< \brief (SERCOM4) I2CM Control C */
+#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4300000CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4300001CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x43000024UL) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (*(RwReg *)0x43000028UL) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x43000000UL) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x43000004UL) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_CTRLC (*(RwReg *)0x43000008UL) /**< \brief (SERCOM4) I2CS Control C */
+#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4300001CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_LENGTH (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) I2CS Length */
+#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x43000024UL) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (*(RwReg *)0x43000028UL) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x43000000UL) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x43000004UL) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_CTRLC (*(RwReg *)0x43000008UL) /**< \brief (SERCOM4) SPI Control C */
+#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4300000CUL) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4300001CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_LENGTH (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) SPI Length */
+#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x43000024UL) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x43000028UL) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x43000000UL) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x43000004UL) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x43000008UL) /**< \brief (SERCOM4) USART Control C */
+#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4300000CUL) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4300000EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4300001CUL) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x43000020UL) /**< \brief (SERCOM4) USART Receive Error Count */
+#define REG_SERCOM4_USART_LENGTH (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) USART Length */
+#define REG_SERCOM4_USART_DATA (*(RwReg *)0x43000028UL) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM4_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM4_DMA 1 // DMA support implemented?
+#define SERCOM4_DMAC_ID_RX 12 // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX 13 // Index of DMA TX trigger
+#define SERCOM4_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM4_GCLK_ID_CORE 34
+#define SERCOM4_GCLK_ID_SLOW 3
+#define SERCOM4_INT_MSB 6
+#define SERCOM4_PMSB 3
+#define SERCOM4_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM4_SE_CNT 1 // SE counter included?
+#define SERCOM4_SPI 1 // SPI mode implemented?
+#define SERCOM4_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM4_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM4_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM4_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM4_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM4_TWIM 1 // TWI Master mode implemented?
+#define SERCOM4_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM4_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM4_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM4_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM4_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM4_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM4_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM4_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM4_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM4_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM4_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM4_USART 1 // USART mode implemented?
+#define SERCOM4_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM4_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM4_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM4_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM4_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM4_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM4_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM4_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM4_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM4_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom5.h b/GPIO/ATSAME54/include/instance/sercom5.h
new file mode 100644
index 0000000..b3ea424
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom5.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM5_INSTANCE_
+#define _SAME54_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA (0x43000400) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (0x43000404) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_CTRLC (0x43000408) /**< \brief (SERCOM5) I2CM Control C */
+#define REG_SERCOM5_I2CM_BAUD (0x4300040C) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (0x43000414) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (0x43000416) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (0x43000418) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (0x4300041A) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR (0x43000424) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (0x43000428) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (0x43000430) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (0x43000400) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (0x43000404) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_CTRLC (0x43000408) /**< \brief (SERCOM5) I2CS Control C */
+#define REG_SERCOM5_I2CS_INTENCLR (0x43000414) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (0x43000416) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (0x43000418) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (0x4300041A) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_LENGTH (0x43000422) /**< \brief (SERCOM5) I2CS Length */
+#define REG_SERCOM5_I2CS_ADDR (0x43000424) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (0x43000428) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (0x43000400) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (0x43000404) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_CTRLC (0x43000408) /**< \brief (SERCOM5) SPI Control C */
+#define REG_SERCOM5_SPI_BAUD (0x4300040C) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (0x43000414) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (0x43000416) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (0x43000418) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (0x4300041A) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_LENGTH (0x43000422) /**< \brief (SERCOM5) SPI Length */
+#define REG_SERCOM5_SPI_ADDR (0x43000424) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (0x43000428) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (0x43000430) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (0x43000400) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (0x43000404) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_CTRLC (0x43000408) /**< \brief (SERCOM5) USART Control C */
+#define REG_SERCOM5_USART_BAUD (0x4300040C) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (0x4300040E) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x43000414) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x43000416) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (0x43000418) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (0x4300041A) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_RXERRCNT (0x43000420) /**< \brief (SERCOM5) USART Receive Error Count */
+#define REG_SERCOM5_USART_LENGTH (0x43000422) /**< \brief (SERCOM5) USART Length */
+#define REG_SERCOM5_USART_DATA (0x43000428) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (0x43000430) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_CTRLC (*(RwReg *)0x43000408UL) /**< \brief (SERCOM5) I2CM Control C */
+#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4300040CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (*(RwReg *)0x43000428UL) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_CTRLC (*(RwReg *)0x43000408UL) /**< \brief (SERCOM5) I2CS Control C */
+#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_LENGTH (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) I2CS Length */
+#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (*(RwReg *)0x43000428UL) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_CTRLC (*(RwReg *)0x43000408UL) /**< \brief (SERCOM5) SPI Control C */
+#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4300040CUL) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_LENGTH (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) SPI Length */
+#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x43000428UL) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x43000408UL) /**< \brief (SERCOM5) USART Control C */
+#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4300040CUL) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4300040EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x43000420UL) /**< \brief (SERCOM5) USART Receive Error Count */
+#define REG_SERCOM5_USART_LENGTH (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) USART Length */
+#define REG_SERCOM5_USART_DATA (*(RwReg *)0x43000428UL) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM5_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM5_DMA 1 // DMA support implemented?
+#define SERCOM5_DMAC_ID_RX 14 // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX 15 // Index of DMA TX trigger
+#define SERCOM5_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM5_GCLK_ID_CORE 35
+#define SERCOM5_GCLK_ID_SLOW 3
+#define SERCOM5_INT_MSB 6
+#define SERCOM5_PMSB 3
+#define SERCOM5_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM5_SE_CNT 1 // SE counter included?
+#define SERCOM5_SPI 1 // SPI mode implemented?
+#define SERCOM5_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM5_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM5_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM5_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM5_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM5_TWIM 1 // TWI Master mode implemented?
+#define SERCOM5_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM5_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM5_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM5_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM5_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM5_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM5_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM5_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM5_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM5_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM5_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM5_USART 1 // USART mode implemented?
+#define SERCOM5_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM5_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM5_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM5_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM5_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM5_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM5_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM5_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM5_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom6.h b/GPIO/ATSAME54/include/instance/sercom6.h
new file mode 100644
index 0000000..914dd32
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom6.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM6
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM6_INSTANCE_
+#define _SAME54_SERCOM6_INSTANCE_
+
+/* ========== Register definition for SERCOM6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM6_I2CM_CTRLA (0x43000800) /**< \brief (SERCOM6) I2CM Control A */
+#define REG_SERCOM6_I2CM_CTRLB (0x43000804) /**< \brief (SERCOM6) I2CM Control B */
+#define REG_SERCOM6_I2CM_CTRLC (0x43000808) /**< \brief (SERCOM6) I2CM Control C */
+#define REG_SERCOM6_I2CM_BAUD (0x4300080C) /**< \brief (SERCOM6) I2CM Baud Rate */
+#define REG_SERCOM6_I2CM_INTENCLR (0x43000814) /**< \brief (SERCOM6) I2CM Interrupt Enable Clear */
+#define REG_SERCOM6_I2CM_INTENSET (0x43000816) /**< \brief (SERCOM6) I2CM Interrupt Enable Set */
+#define REG_SERCOM6_I2CM_INTFLAG (0x43000818) /**< \brief (SERCOM6) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CM_STATUS (0x4300081A) /**< \brief (SERCOM6) I2CM Status */
+#define REG_SERCOM6_I2CM_SYNCBUSY (0x4300081C) /**< \brief (SERCOM6) I2CM Synchronization Busy */
+#define REG_SERCOM6_I2CM_ADDR (0x43000824) /**< \brief (SERCOM6) I2CM Address */
+#define REG_SERCOM6_I2CM_DATA (0x43000828) /**< \brief (SERCOM6) I2CM Data */
+#define REG_SERCOM6_I2CM_DBGCTRL (0x43000830) /**< \brief (SERCOM6) I2CM Debug Control */
+#define REG_SERCOM6_I2CS_CTRLA (0x43000800) /**< \brief (SERCOM6) I2CS Control A */
+#define REG_SERCOM6_I2CS_CTRLB (0x43000804) /**< \brief (SERCOM6) I2CS Control B */
+#define REG_SERCOM6_I2CS_CTRLC (0x43000808) /**< \brief (SERCOM6) I2CS Control C */
+#define REG_SERCOM6_I2CS_INTENCLR (0x43000814) /**< \brief (SERCOM6) I2CS Interrupt Enable Clear */
+#define REG_SERCOM6_I2CS_INTENSET (0x43000816) /**< \brief (SERCOM6) I2CS Interrupt Enable Set */
+#define REG_SERCOM6_I2CS_INTFLAG (0x43000818) /**< \brief (SERCOM6) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CS_STATUS (0x4300081A) /**< \brief (SERCOM6) I2CS Status */
+#define REG_SERCOM6_I2CS_SYNCBUSY (0x4300081C) /**< \brief (SERCOM6) I2CS Synchronization Busy */
+#define REG_SERCOM6_I2CS_LENGTH (0x43000822) /**< \brief (SERCOM6) I2CS Length */
+#define REG_SERCOM6_I2CS_ADDR (0x43000824) /**< \brief (SERCOM6) I2CS Address */
+#define REG_SERCOM6_I2CS_DATA (0x43000828) /**< \brief (SERCOM6) I2CS Data */
+#define REG_SERCOM6_SPI_CTRLA (0x43000800) /**< \brief (SERCOM6) SPI Control A */
+#define REG_SERCOM6_SPI_CTRLB (0x43000804) /**< \brief (SERCOM6) SPI Control B */
+#define REG_SERCOM6_SPI_CTRLC (0x43000808) /**< \brief (SERCOM6) SPI Control C */
+#define REG_SERCOM6_SPI_BAUD (0x4300080C) /**< \brief (SERCOM6) SPI Baud Rate */
+#define REG_SERCOM6_SPI_INTENCLR (0x43000814) /**< \brief (SERCOM6) SPI Interrupt Enable Clear */
+#define REG_SERCOM6_SPI_INTENSET (0x43000816) /**< \brief (SERCOM6) SPI Interrupt Enable Set */
+#define REG_SERCOM6_SPI_INTFLAG (0x43000818) /**< \brief (SERCOM6) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM6_SPI_STATUS (0x4300081A) /**< \brief (SERCOM6) SPI Status */
+#define REG_SERCOM6_SPI_SYNCBUSY (0x4300081C) /**< \brief (SERCOM6) SPI Synchronization Busy */
+#define REG_SERCOM6_SPI_LENGTH (0x43000822) /**< \brief (SERCOM6) SPI Length */
+#define REG_SERCOM6_SPI_ADDR (0x43000824) /**< \brief (SERCOM6) SPI Address */
+#define REG_SERCOM6_SPI_DATA (0x43000828) /**< \brief (SERCOM6) SPI Data */
+#define REG_SERCOM6_SPI_DBGCTRL (0x43000830) /**< \brief (SERCOM6) SPI Debug Control */
+#define REG_SERCOM6_USART_CTRLA (0x43000800) /**< \brief (SERCOM6) USART Control A */
+#define REG_SERCOM6_USART_CTRLB (0x43000804) /**< \brief (SERCOM6) USART Control B */
+#define REG_SERCOM6_USART_CTRLC (0x43000808) /**< \brief (SERCOM6) USART Control C */
+#define REG_SERCOM6_USART_BAUD (0x4300080C) /**< \brief (SERCOM6) USART Baud Rate */
+#define REG_SERCOM6_USART_RXPL (0x4300080E) /**< \brief (SERCOM6) USART Receive Pulse Length */
+#define REG_SERCOM6_USART_INTENCLR (0x43000814) /**< \brief (SERCOM6) USART Interrupt Enable Clear */
+#define REG_SERCOM6_USART_INTENSET (0x43000816) /**< \brief (SERCOM6) USART Interrupt Enable Set */
+#define REG_SERCOM6_USART_INTFLAG (0x43000818) /**< \brief (SERCOM6) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM6_USART_STATUS (0x4300081A) /**< \brief (SERCOM6) USART Status */
+#define REG_SERCOM6_USART_SYNCBUSY (0x4300081C) /**< \brief (SERCOM6) USART Synchronization Busy */
+#define REG_SERCOM6_USART_RXERRCNT (0x43000820) /**< \brief (SERCOM6) USART Receive Error Count */
+#define REG_SERCOM6_USART_LENGTH (0x43000822) /**< \brief (SERCOM6) USART Length */
+#define REG_SERCOM6_USART_DATA (0x43000828) /**< \brief (SERCOM6) USART Data */
+#define REG_SERCOM6_USART_DBGCTRL (0x43000830) /**< \brief (SERCOM6) USART Debug Control */
+#else
+#define REG_SERCOM6_I2CM_CTRLA (*(RwReg *)0x43000800UL) /**< \brief (SERCOM6) I2CM Control A */
+#define REG_SERCOM6_I2CM_CTRLB (*(RwReg *)0x43000804UL) /**< \brief (SERCOM6) I2CM Control B */
+#define REG_SERCOM6_I2CM_CTRLC (*(RwReg *)0x43000808UL) /**< \brief (SERCOM6) I2CM Control C */
+#define REG_SERCOM6_I2CM_BAUD (*(RwReg *)0x4300080CUL) /**< \brief (SERCOM6) I2CM Baud Rate */
+#define REG_SERCOM6_I2CM_INTENCLR (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) I2CM Interrupt Enable Clear */
+#define REG_SERCOM6_I2CM_INTENSET (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) I2CM Interrupt Enable Set */
+#define REG_SERCOM6_I2CM_INTFLAG (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CM_STATUS (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) I2CM Status */
+#define REG_SERCOM6_I2CM_SYNCBUSY (*(RoReg *)0x4300081CUL) /**< \brief (SERCOM6) I2CM Synchronization Busy */
+#define REG_SERCOM6_I2CM_ADDR (*(RwReg *)0x43000824UL) /**< \brief (SERCOM6) I2CM Address */
+#define REG_SERCOM6_I2CM_DATA (*(RwReg *)0x43000828UL) /**< \brief (SERCOM6) I2CM Data */
+#define REG_SERCOM6_I2CM_DBGCTRL (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) I2CM Debug Control */
+#define REG_SERCOM6_I2CS_CTRLA (*(RwReg *)0x43000800UL) /**< \brief (SERCOM6) I2CS Control A */
+#define REG_SERCOM6_I2CS_CTRLB (*(RwReg *)0x43000804UL) /**< \brief (SERCOM6) I2CS Control B */
+#define REG_SERCOM6_I2CS_CTRLC (*(RwReg *)0x43000808UL) /**< \brief (SERCOM6) I2CS Control C */
+#define REG_SERCOM6_I2CS_INTENCLR (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) I2CS Interrupt Enable Clear */
+#define REG_SERCOM6_I2CS_INTENSET (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) I2CS Interrupt Enable Set */
+#define REG_SERCOM6_I2CS_INTFLAG (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CS_STATUS (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) I2CS Status */
+#define REG_SERCOM6_I2CS_SYNCBUSY (*(RoReg *)0x4300081CUL) /**< \brief (SERCOM6) I2CS Synchronization Busy */
+#define REG_SERCOM6_I2CS_LENGTH (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) I2CS Length */
+#define REG_SERCOM6_I2CS_ADDR (*(RwReg *)0x43000824UL) /**< \brief (SERCOM6) I2CS Address */
+#define REG_SERCOM6_I2CS_DATA (*(RwReg *)0x43000828UL) /**< \brief (SERCOM6) I2CS Data */
+#define REG_SERCOM6_SPI_CTRLA (*(RwReg *)0x43000800UL) /**< \brief (SERCOM6) SPI Control A */
+#define REG_SERCOM6_SPI_CTRLB (*(RwReg *)0x43000804UL) /**< \brief (SERCOM6) SPI Control B */
+#define REG_SERCOM6_SPI_CTRLC (*(RwReg *)0x43000808UL) /**< \brief (SERCOM6) SPI Control C */
+#define REG_SERCOM6_SPI_BAUD (*(RwReg8 *)0x4300080CUL) /**< \brief (SERCOM6) SPI Baud Rate */
+#define REG_SERCOM6_SPI_INTENCLR (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) SPI Interrupt Enable Clear */
+#define REG_SERCOM6_SPI_INTENSET (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) SPI Interrupt Enable Set */
+#define REG_SERCOM6_SPI_INTFLAG (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM6_SPI_STATUS (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) SPI Status */
+#define REG_SERCOM6_SPI_SYNCBUSY (*(RoReg *)0x4300081CUL) /**< \brief (SERCOM6) SPI Synchronization Busy */
+#define REG_SERCOM6_SPI_LENGTH (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) SPI Length */
+#define REG_SERCOM6_SPI_ADDR (*(RwReg *)0x43000824UL) /**< \brief (SERCOM6) SPI Address */
+#define REG_SERCOM6_SPI_DATA (*(RwReg *)0x43000828UL) /**< \brief (SERCOM6) SPI Data */
+#define REG_SERCOM6_SPI_DBGCTRL (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) SPI Debug Control */
+#define REG_SERCOM6_USART_CTRLA (*(RwReg *)0x43000800UL) /**< \brief (SERCOM6) USART Control A */
+#define REG_SERCOM6_USART_CTRLB (*(RwReg *)0x43000804UL) /**< \brief (SERCOM6) USART Control B */
+#define REG_SERCOM6_USART_CTRLC (*(RwReg *)0x43000808UL) /**< \brief (SERCOM6) USART Control C */
+#define REG_SERCOM6_USART_BAUD (*(RwReg16*)0x4300080CUL) /**< \brief (SERCOM6) USART Baud Rate */
+#define REG_SERCOM6_USART_RXPL (*(RwReg8 *)0x4300080EUL) /**< \brief (SERCOM6) USART Receive Pulse Length */
+#define REG_SERCOM6_USART_INTENCLR (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) USART Interrupt Enable Clear */
+#define REG_SERCOM6_USART_INTENSET (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) USART Interrupt Enable Set */
+#define REG_SERCOM6_USART_INTFLAG (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM6_USART_STATUS (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) USART Status */
+#define REG_SERCOM6_USART_SYNCBUSY (*(RoReg *)0x4300081CUL) /**< \brief (SERCOM6) USART Synchronization Busy */
+#define REG_SERCOM6_USART_RXERRCNT (*(RoReg8 *)0x43000820UL) /**< \brief (SERCOM6) USART Receive Error Count */
+#define REG_SERCOM6_USART_LENGTH (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) USART Length */
+#define REG_SERCOM6_USART_DATA (*(RwReg *)0x43000828UL) /**< \brief (SERCOM6) USART Data */
+#define REG_SERCOM6_USART_DBGCTRL (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM6 peripheral ========== */
+#define SERCOM6_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM6_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM6_DMA 1 // DMA support implemented?
+#define SERCOM6_DMAC_ID_RX 16 // Index of DMA RX trigger
+#define SERCOM6_DMAC_ID_TX 17 // Index of DMA TX trigger
+#define SERCOM6_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM6_GCLK_ID_CORE 36
+#define SERCOM6_GCLK_ID_SLOW 3
+#define SERCOM6_INT_MSB 6
+#define SERCOM6_PMSB 3
+#define SERCOM6_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM6_SE_CNT 1 // SE counter included?
+#define SERCOM6_SPI 1 // SPI mode implemented?
+#define SERCOM6_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM6_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM6_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM6_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM6_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM6_TWIM 1 // TWI Master mode implemented?
+#define SERCOM6_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM6_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM6_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM6_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM6_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM6_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM6_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM6_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM6_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM6_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM6_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM6_USART 1 // USART mode implemented?
+#define SERCOM6_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM6_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM6_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM6_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM6_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM6_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM6_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM6_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM6_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM6_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM6_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/sercom7.h b/GPIO/ATSAME54/include/instance/sercom7.h
new file mode 100644
index 0000000..5f2dc6c
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/sercom7.h
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM7
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SERCOM7_INSTANCE_
+#define _SAME54_SERCOM7_INSTANCE_
+
+/* ========== Register definition for SERCOM7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM7_I2CM_CTRLA (0x43000C00) /**< \brief (SERCOM7) I2CM Control A */
+#define REG_SERCOM7_I2CM_CTRLB (0x43000C04) /**< \brief (SERCOM7) I2CM Control B */
+#define REG_SERCOM7_I2CM_CTRLC (0x43000C08) /**< \brief (SERCOM7) I2CM Control C */
+#define REG_SERCOM7_I2CM_BAUD (0x43000C0C) /**< \brief (SERCOM7) I2CM Baud Rate */
+#define REG_SERCOM7_I2CM_INTENCLR (0x43000C14) /**< \brief (SERCOM7) I2CM Interrupt Enable Clear */
+#define REG_SERCOM7_I2CM_INTENSET (0x43000C16) /**< \brief (SERCOM7) I2CM Interrupt Enable Set */
+#define REG_SERCOM7_I2CM_INTFLAG (0x43000C18) /**< \brief (SERCOM7) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CM_STATUS (0x43000C1A) /**< \brief (SERCOM7) I2CM Status */
+#define REG_SERCOM7_I2CM_SYNCBUSY (0x43000C1C) /**< \brief (SERCOM7) I2CM Synchronization Busy */
+#define REG_SERCOM7_I2CM_ADDR (0x43000C24) /**< \brief (SERCOM7) I2CM Address */
+#define REG_SERCOM7_I2CM_DATA (0x43000C28) /**< \brief (SERCOM7) I2CM Data */
+#define REG_SERCOM7_I2CM_DBGCTRL (0x43000C30) /**< \brief (SERCOM7) I2CM Debug Control */
+#define REG_SERCOM7_I2CS_CTRLA (0x43000C00) /**< \brief (SERCOM7) I2CS Control A */
+#define REG_SERCOM7_I2CS_CTRLB (0x43000C04) /**< \brief (SERCOM7) I2CS Control B */
+#define REG_SERCOM7_I2CS_CTRLC (0x43000C08) /**< \brief (SERCOM7) I2CS Control C */
+#define REG_SERCOM7_I2CS_INTENCLR (0x43000C14) /**< \brief (SERCOM7) I2CS Interrupt Enable Clear */
+#define REG_SERCOM7_I2CS_INTENSET (0x43000C16) /**< \brief (SERCOM7) I2CS Interrupt Enable Set */
+#define REG_SERCOM7_I2CS_INTFLAG (0x43000C18) /**< \brief (SERCOM7) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CS_STATUS (0x43000C1A) /**< \brief (SERCOM7) I2CS Status */
+#define REG_SERCOM7_I2CS_SYNCBUSY (0x43000C1C) /**< \brief (SERCOM7) I2CS Synchronization Busy */
+#define REG_SERCOM7_I2CS_LENGTH (0x43000C22) /**< \brief (SERCOM7) I2CS Length */
+#define REG_SERCOM7_I2CS_ADDR (0x43000C24) /**< \brief (SERCOM7) I2CS Address */
+#define REG_SERCOM7_I2CS_DATA (0x43000C28) /**< \brief (SERCOM7) I2CS Data */
+#define REG_SERCOM7_SPI_CTRLA (0x43000C00) /**< \brief (SERCOM7) SPI Control A */
+#define REG_SERCOM7_SPI_CTRLB (0x43000C04) /**< \brief (SERCOM7) SPI Control B */
+#define REG_SERCOM7_SPI_CTRLC (0x43000C08) /**< \brief (SERCOM7) SPI Control C */
+#define REG_SERCOM7_SPI_BAUD (0x43000C0C) /**< \brief (SERCOM7) SPI Baud Rate */
+#define REG_SERCOM7_SPI_INTENCLR (0x43000C14) /**< \brief (SERCOM7) SPI Interrupt Enable Clear */
+#define REG_SERCOM7_SPI_INTENSET (0x43000C16) /**< \brief (SERCOM7) SPI Interrupt Enable Set */
+#define REG_SERCOM7_SPI_INTFLAG (0x43000C18) /**< \brief (SERCOM7) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM7_SPI_STATUS (0x43000C1A) /**< \brief (SERCOM7) SPI Status */
+#define REG_SERCOM7_SPI_SYNCBUSY (0x43000C1C) /**< \brief (SERCOM7) SPI Synchronization Busy */
+#define REG_SERCOM7_SPI_LENGTH (0x43000C22) /**< \brief (SERCOM7) SPI Length */
+#define REG_SERCOM7_SPI_ADDR (0x43000C24) /**< \brief (SERCOM7) SPI Address */
+#define REG_SERCOM7_SPI_DATA (0x43000C28) /**< \brief (SERCOM7) SPI Data */
+#define REG_SERCOM7_SPI_DBGCTRL (0x43000C30) /**< \brief (SERCOM7) SPI Debug Control */
+#define REG_SERCOM7_USART_CTRLA (0x43000C00) /**< \brief (SERCOM7) USART Control A */
+#define REG_SERCOM7_USART_CTRLB (0x43000C04) /**< \brief (SERCOM7) USART Control B */
+#define REG_SERCOM7_USART_CTRLC (0x43000C08) /**< \brief (SERCOM7) USART Control C */
+#define REG_SERCOM7_USART_BAUD (0x43000C0C) /**< \brief (SERCOM7) USART Baud Rate */
+#define REG_SERCOM7_USART_RXPL (0x43000C0E) /**< \brief (SERCOM7) USART Receive Pulse Length */
+#define REG_SERCOM7_USART_INTENCLR (0x43000C14) /**< \brief (SERCOM7) USART Interrupt Enable Clear */
+#define REG_SERCOM7_USART_INTENSET (0x43000C16) /**< \brief (SERCOM7) USART Interrupt Enable Set */
+#define REG_SERCOM7_USART_INTFLAG (0x43000C18) /**< \brief (SERCOM7) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM7_USART_STATUS (0x43000C1A) /**< \brief (SERCOM7) USART Status */
+#define REG_SERCOM7_USART_SYNCBUSY (0x43000C1C) /**< \brief (SERCOM7) USART Synchronization Busy */
+#define REG_SERCOM7_USART_RXERRCNT (0x43000C20) /**< \brief (SERCOM7) USART Receive Error Count */
+#define REG_SERCOM7_USART_LENGTH (0x43000C22) /**< \brief (SERCOM7) USART Length */
+#define REG_SERCOM7_USART_DATA (0x43000C28) /**< \brief (SERCOM7) USART Data */
+#define REG_SERCOM7_USART_DBGCTRL (0x43000C30) /**< \brief (SERCOM7) USART Debug Control */
+#else
+#define REG_SERCOM7_I2CM_CTRLA (*(RwReg *)0x43000C00UL) /**< \brief (SERCOM7) I2CM Control A */
+#define REG_SERCOM7_I2CM_CTRLB (*(RwReg *)0x43000C04UL) /**< \brief (SERCOM7) I2CM Control B */
+#define REG_SERCOM7_I2CM_CTRLC (*(RwReg *)0x43000C08UL) /**< \brief (SERCOM7) I2CM Control C */
+#define REG_SERCOM7_I2CM_BAUD (*(RwReg *)0x43000C0CUL) /**< \brief (SERCOM7) I2CM Baud Rate */
+#define REG_SERCOM7_I2CM_INTENCLR (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) I2CM Interrupt Enable Clear */
+#define REG_SERCOM7_I2CM_INTENSET (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) I2CM Interrupt Enable Set */
+#define REG_SERCOM7_I2CM_INTFLAG (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CM_STATUS (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) I2CM Status */
+#define REG_SERCOM7_I2CM_SYNCBUSY (*(RoReg *)0x43000C1CUL) /**< \brief (SERCOM7) I2CM Synchronization Busy */
+#define REG_SERCOM7_I2CM_ADDR (*(RwReg *)0x43000C24UL) /**< \brief (SERCOM7) I2CM Address */
+#define REG_SERCOM7_I2CM_DATA (*(RwReg *)0x43000C28UL) /**< \brief (SERCOM7) I2CM Data */
+#define REG_SERCOM7_I2CM_DBGCTRL (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) I2CM Debug Control */
+#define REG_SERCOM7_I2CS_CTRLA (*(RwReg *)0x43000C00UL) /**< \brief (SERCOM7) I2CS Control A */
+#define REG_SERCOM7_I2CS_CTRLB (*(RwReg *)0x43000C04UL) /**< \brief (SERCOM7) I2CS Control B */
+#define REG_SERCOM7_I2CS_CTRLC (*(RwReg *)0x43000C08UL) /**< \brief (SERCOM7) I2CS Control C */
+#define REG_SERCOM7_I2CS_INTENCLR (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) I2CS Interrupt Enable Clear */
+#define REG_SERCOM7_I2CS_INTENSET (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) I2CS Interrupt Enable Set */
+#define REG_SERCOM7_I2CS_INTFLAG (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CS_STATUS (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) I2CS Status */
+#define REG_SERCOM7_I2CS_SYNCBUSY (*(RoReg *)0x43000C1CUL) /**< \brief (SERCOM7) I2CS Synchronization Busy */
+#define REG_SERCOM7_I2CS_LENGTH (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) I2CS Length */
+#define REG_SERCOM7_I2CS_ADDR (*(RwReg *)0x43000C24UL) /**< \brief (SERCOM7) I2CS Address */
+#define REG_SERCOM7_I2CS_DATA (*(RwReg *)0x43000C28UL) /**< \brief (SERCOM7) I2CS Data */
+#define REG_SERCOM7_SPI_CTRLA (*(RwReg *)0x43000C00UL) /**< \brief (SERCOM7) SPI Control A */
+#define REG_SERCOM7_SPI_CTRLB (*(RwReg *)0x43000C04UL) /**< \brief (SERCOM7) SPI Control B */
+#define REG_SERCOM7_SPI_CTRLC (*(RwReg *)0x43000C08UL) /**< \brief (SERCOM7) SPI Control C */
+#define REG_SERCOM7_SPI_BAUD (*(RwReg8 *)0x43000C0CUL) /**< \brief (SERCOM7) SPI Baud Rate */
+#define REG_SERCOM7_SPI_INTENCLR (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) SPI Interrupt Enable Clear */
+#define REG_SERCOM7_SPI_INTENSET (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) SPI Interrupt Enable Set */
+#define REG_SERCOM7_SPI_INTFLAG (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM7_SPI_STATUS (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) SPI Status */
+#define REG_SERCOM7_SPI_SYNCBUSY (*(RoReg *)0x43000C1CUL) /**< \brief (SERCOM7) SPI Synchronization Busy */
+#define REG_SERCOM7_SPI_LENGTH (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) SPI Length */
+#define REG_SERCOM7_SPI_ADDR (*(RwReg *)0x43000C24UL) /**< \brief (SERCOM7) SPI Address */
+#define REG_SERCOM7_SPI_DATA (*(RwReg *)0x43000C28UL) /**< \brief (SERCOM7) SPI Data */
+#define REG_SERCOM7_SPI_DBGCTRL (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) SPI Debug Control */
+#define REG_SERCOM7_USART_CTRLA (*(RwReg *)0x43000C00UL) /**< \brief (SERCOM7) USART Control A */
+#define REG_SERCOM7_USART_CTRLB (*(RwReg *)0x43000C04UL) /**< \brief (SERCOM7) USART Control B */
+#define REG_SERCOM7_USART_CTRLC (*(RwReg *)0x43000C08UL) /**< \brief (SERCOM7) USART Control C */
+#define REG_SERCOM7_USART_BAUD (*(RwReg16*)0x43000C0CUL) /**< \brief (SERCOM7) USART Baud Rate */
+#define REG_SERCOM7_USART_RXPL (*(RwReg8 *)0x43000C0EUL) /**< \brief (SERCOM7) USART Receive Pulse Length */
+#define REG_SERCOM7_USART_INTENCLR (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) USART Interrupt Enable Clear */
+#define REG_SERCOM7_USART_INTENSET (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) USART Interrupt Enable Set */
+#define REG_SERCOM7_USART_INTFLAG (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM7_USART_STATUS (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) USART Status */
+#define REG_SERCOM7_USART_SYNCBUSY (*(RoReg *)0x43000C1CUL) /**< \brief (SERCOM7) USART Synchronization Busy */
+#define REG_SERCOM7_USART_RXERRCNT (*(RoReg8 *)0x43000C20UL) /**< \brief (SERCOM7) USART Receive Error Count */
+#define REG_SERCOM7_USART_LENGTH (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) USART Length */
+#define REG_SERCOM7_USART_DATA (*(RwReg *)0x43000C28UL) /**< \brief (SERCOM7) USART Data */
+#define REG_SERCOM7_USART_DBGCTRL (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM7 peripheral ========== */
+#define SERCOM7_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM7_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM7_DMA 1 // DMA support implemented?
+#define SERCOM7_DMAC_ID_RX 18 // Index of DMA RX trigger
+#define SERCOM7_DMAC_ID_TX 19 // Index of DMA TX trigger
+#define SERCOM7_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM7_GCLK_ID_CORE 37
+#define SERCOM7_GCLK_ID_SLOW 3
+#define SERCOM7_INT_MSB 6
+#define SERCOM7_PMSB 3
+#define SERCOM7_RETENTION_SUPPORT 0 // Retention supported?
+#define SERCOM7_SE_CNT 1 // SE counter included?
+#define SERCOM7_SPI 1 // SPI mode implemented?
+#define SERCOM7_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
+#define SERCOM7_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
+#define SERCOM7_SPI_OZMO 0 // OZMO features implemented?
+#define SERCOM7_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
+#define SERCOM7_TTBIT_EXTENSION 1 // 32-bit extension implemented?
+#define SERCOM7_TWIM 1 // TWI Master mode implemented?
+#define SERCOM7_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM7_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
+#define SERCOM7_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
+#define SERCOM7_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
+#define SERCOM7_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
+#define SERCOM7_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
+#define SERCOM7_TWI_FASTMP 1 // TWI fast mode plus implemented?
+#define SERCOM7_TWI_HSMODE 1 // USART mode implemented?
+#define SERCOM7_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
+#define SERCOM7_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
+#define SERCOM7_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
+#define SERCOM7_USART 1 // USART mode implemented?
+#define SERCOM7_USART_AUTOBAUD 1 // USART autobaud implemented?
+#define SERCOM7_USART_COLDET 1 // USART collision detection implemented?
+#define SERCOM7_USART_FLOW_CTRL 1 // USART flow control implemented?
+#define SERCOM7_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
+#define SERCOM7_USART_IRDA 1 // USART IrDA implemented?
+#define SERCOM7_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM7_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
+#define SERCOM7_USART_RS485 1 // USART RS485 mode implemented?
+#define SERCOM7_USART_SAMPA_EXT 1 // USART sample adjust implemented?
+#define SERCOM7_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
+
+#endif /* _SAME54_SERCOM7_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/supc.h b/GPIO/ATSAME54/include/instance/supc.h
new file mode 100644
index 0000000..d4c8728
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/supc.h
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SUPC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_SUPC_INSTANCE_
+#define _SAME54_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */
+#define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */
+#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */
+#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */
+#define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */
+#define REG_SUPC_BOD12 (0x40001814) /**< \brief (SUPC) BOD12 Control */
+#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */
+#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */
+#define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */
+#define REG_SUPC_BKOUT (0x40001824) /**< \brief (SUPC) Backup Output Control */
+#define REG_SUPC_BKIN (0x40001828) /**< \brief (SUPC) Backup Input Control */
+#else
+#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */
+#define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */
+#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */
+#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */
+#define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */
+#define REG_SUPC_BOD12 (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */
+#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */
+#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */
+#define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */
+#define REG_SUPC_BKOUT (*(RwReg *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */
+#define REG_SUPC_BKIN (*(RoReg *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SUPC peripheral ========== */
+#define SUPC_BOD12_CALIB_MSB 5
+#define SUPC_BOD33_CALIB_MSB 5
+
+#endif /* _SAME54_SUPC_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tal.h b/GPIO/ATSAME54/include/instance/tal.h
new file mode 100644
index 0000000..7c104da
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tal.h
@@ -0,0 +1,541 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TAL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TAL_INSTANCE_
+#define _SAME54_TAL_INSTANCE_
+
+/* ========== Register definition for TAL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TAL_CTRLA (0x4101E000) /**< \brief (TAL) Control A */
+#define REG_TAL_EXTCTRL (0x4101E001) /**< \brief (TAL) External Break Control */
+#define REG_TAL_EVCTRL (0x4101E004) /**< \brief (TAL) Event Control */
+#define REG_TAL_INTENCLR (0x4101E008) /**< \brief (TAL) Interrupt Enable Clear */
+#define REG_TAL_INTENSET (0x4101E009) /**< \brief (TAL) Interrupt Enable Set */
+#define REG_TAL_INTFLAG (0x4101E00A) /**< \brief (TAL) Interrupt Flag Status and Clear */
+#define REG_TAL_GLOBMASK (0x4101E00B) /**< \brief (TAL) Global Break Requests Mask */
+#define REG_TAL_HALT (0x4101E00C) /**< \brief (TAL) Debug Halt Request */
+#define REG_TAL_RESTART (0x4101E00D) /**< \brief (TAL) Debug Restart Request */
+#define REG_TAL_BRKSTATUS (0x4101E00E) /**< \brief (TAL) Break Request Status */
+#define REG_TAL_CTICTRLA0 (0x4101E010) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
+#define REG_TAL_CTIMASK0 (0x4101E011) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
+#define REG_TAL_CTICTRLA1 (0x4101E012) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
+#define REG_TAL_CTIMASK1 (0x4101E013) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
+#define REG_TAL_CTICTRLA2 (0x4101E014) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
+#define REG_TAL_CTIMASK2 (0x4101E015) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
+#define REG_TAL_CTICTRLA3 (0x4101E016) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */
+#define REG_TAL_CTIMASK3 (0x4101E017) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */
+#define REG_TAL_INTSTATUS0 (0x4101E020) /**< \brief (TAL) Interrupt 0 Status */
+#define REG_TAL_INTSTATUS1 (0x4101E021) /**< \brief (TAL) Interrupt 1 Status */
+#define REG_TAL_INTSTATUS2 (0x4101E022) /**< \brief (TAL) Interrupt 2 Status */
+#define REG_TAL_INTSTATUS3 (0x4101E023) /**< \brief (TAL) Interrupt 3 Status */
+#define REG_TAL_INTSTATUS4 (0x4101E024) /**< \brief (TAL) Interrupt 4 Status */
+#define REG_TAL_INTSTATUS5 (0x4101E025) /**< \brief (TAL) Interrupt 5 Status */
+#define REG_TAL_INTSTATUS6 (0x4101E026) /**< \brief (TAL) Interrupt 6 Status */
+#define REG_TAL_INTSTATUS7 (0x4101E027) /**< \brief (TAL) Interrupt 7 Status */
+#define REG_TAL_INTSTATUS8 (0x4101E028) /**< \brief (TAL) Interrupt 8 Status */
+#define REG_TAL_INTSTATUS9 (0x4101E029) /**< \brief (TAL) Interrupt 9 Status */
+#define REG_TAL_INTSTATUS10 (0x4101E02A) /**< \brief (TAL) Interrupt 10 Status */
+#define REG_TAL_INTSTATUS11 (0x4101E02B) /**< \brief (TAL) Interrupt 11 Status */
+#define REG_TAL_INTSTATUS12 (0x4101E02C) /**< \brief (TAL) Interrupt 12 Status */
+#define REG_TAL_INTSTATUS13 (0x4101E02D) /**< \brief (TAL) Interrupt 13 Status */
+#define REG_TAL_INTSTATUS14 (0x4101E02E) /**< \brief (TAL) Interrupt 14 Status */
+#define REG_TAL_INTSTATUS15 (0x4101E02F) /**< \brief (TAL) Interrupt 15 Status */
+#define REG_TAL_INTSTATUS16 (0x4101E030) /**< \brief (TAL) Interrupt 16 Status */
+#define REG_TAL_INTSTATUS17 (0x4101E031) /**< \brief (TAL) Interrupt 17 Status */
+#define REG_TAL_INTSTATUS18 (0x4101E032) /**< \brief (TAL) Interrupt 18 Status */
+#define REG_TAL_INTSTATUS19 (0x4101E033) /**< \brief (TAL) Interrupt 19 Status */
+#define REG_TAL_INTSTATUS20 (0x4101E034) /**< \brief (TAL) Interrupt 20 Status */
+#define REG_TAL_INTSTATUS21 (0x4101E035) /**< \brief (TAL) Interrupt 21 Status */
+#define REG_TAL_INTSTATUS22 (0x4101E036) /**< \brief (TAL) Interrupt 22 Status */
+#define REG_TAL_INTSTATUS23 (0x4101E037) /**< \brief (TAL) Interrupt 23 Status */
+#define REG_TAL_INTSTATUS24 (0x4101E038) /**< \brief (TAL) Interrupt 24 Status */
+#define REG_TAL_INTSTATUS25 (0x4101E039) /**< \brief (TAL) Interrupt 25 Status */
+#define REG_TAL_INTSTATUS26 (0x4101E03A) /**< \brief (TAL) Interrupt 26 Status */
+#define REG_TAL_INTSTATUS27 (0x4101E03B) /**< \brief (TAL) Interrupt 27 Status */
+#define REG_TAL_INTSTATUS28 (0x4101E03C) /**< \brief (TAL) Interrupt 28 Status */
+#define REG_TAL_INTSTATUS29 (0x4101E03D) /**< \brief (TAL) Interrupt 29 Status */
+#define REG_TAL_INTSTATUS30 (0x4101E03E) /**< \brief (TAL) Interrupt 30 Status */
+#define REG_TAL_INTSTATUS31 (0x4101E03F) /**< \brief (TAL) Interrupt 31 Status */
+#define REG_TAL_INTSTATUS32 (0x4101E040) /**< \brief (TAL) Interrupt 32 Status */
+#define REG_TAL_INTSTATUS33 (0x4101E041) /**< \brief (TAL) Interrupt 33 Status */
+#define REG_TAL_INTSTATUS34 (0x4101E042) /**< \brief (TAL) Interrupt 34 Status */
+#define REG_TAL_INTSTATUS35 (0x4101E043) /**< \brief (TAL) Interrupt 35 Status */
+#define REG_TAL_INTSTATUS36 (0x4101E044) /**< \brief (TAL) Interrupt 36 Status */
+#define REG_TAL_INTSTATUS37 (0x4101E045) /**< \brief (TAL) Interrupt 37 Status */
+#define REG_TAL_INTSTATUS38 (0x4101E046) /**< \brief (TAL) Interrupt 38 Status */
+#define REG_TAL_INTSTATUS39 (0x4101E047) /**< \brief (TAL) Interrupt 39 Status */
+#define REG_TAL_INTSTATUS40 (0x4101E048) /**< \brief (TAL) Interrupt 40 Status */
+#define REG_TAL_INTSTATUS41 (0x4101E049) /**< \brief (TAL) Interrupt 41 Status */
+#define REG_TAL_INTSTATUS42 (0x4101E04A) /**< \brief (TAL) Interrupt 42 Status */
+#define REG_TAL_INTSTATUS43 (0x4101E04B) /**< \brief (TAL) Interrupt 43 Status */
+#define REG_TAL_INTSTATUS44 (0x4101E04C) /**< \brief (TAL) Interrupt 44 Status */
+#define REG_TAL_INTSTATUS45 (0x4101E04D) /**< \brief (TAL) Interrupt 45 Status */
+#define REG_TAL_INTSTATUS46 (0x4101E04E) /**< \brief (TAL) Interrupt 46 Status */
+#define REG_TAL_INTSTATUS47 (0x4101E04F) /**< \brief (TAL) Interrupt 47 Status */
+#define REG_TAL_INTSTATUS48 (0x4101E050) /**< \brief (TAL) Interrupt 48 Status */
+#define REG_TAL_INTSTATUS49 (0x4101E051) /**< \brief (TAL) Interrupt 49 Status */
+#define REG_TAL_INTSTATUS50 (0x4101E052) /**< \brief (TAL) Interrupt 50 Status */
+#define REG_TAL_INTSTATUS51 (0x4101E053) /**< \brief (TAL) Interrupt 51 Status */
+#define REG_TAL_INTSTATUS52 (0x4101E054) /**< \brief (TAL) Interrupt 52 Status */
+#define REG_TAL_INTSTATUS53 (0x4101E055) /**< \brief (TAL) Interrupt 53 Status */
+#define REG_TAL_INTSTATUS54 (0x4101E056) /**< \brief (TAL) Interrupt 54 Status */
+#define REG_TAL_INTSTATUS55 (0x4101E057) /**< \brief (TAL) Interrupt 55 Status */
+#define REG_TAL_INTSTATUS56 (0x4101E058) /**< \brief (TAL) Interrupt 56 Status */
+#define REG_TAL_INTSTATUS57 (0x4101E059) /**< \brief (TAL) Interrupt 57 Status */
+#define REG_TAL_INTSTATUS58 (0x4101E05A) /**< \brief (TAL) Interrupt 58 Status */
+#define REG_TAL_INTSTATUS59 (0x4101E05B) /**< \brief (TAL) Interrupt 59 Status */
+#define REG_TAL_INTSTATUS60 (0x4101E05C) /**< \brief (TAL) Interrupt 60 Status */
+#define REG_TAL_INTSTATUS61 (0x4101E05D) /**< \brief (TAL) Interrupt 61 Status */
+#define REG_TAL_INTSTATUS62 (0x4101E05E) /**< \brief (TAL) Interrupt 62 Status */
+#define REG_TAL_INTSTATUS63 (0x4101E05F) /**< \brief (TAL) Interrupt 63 Status */
+#define REG_TAL_INTSTATUS64 (0x4101E060) /**< \brief (TAL) Interrupt 64 Status */
+#define REG_TAL_INTSTATUS65 (0x4101E061) /**< \brief (TAL) Interrupt 65 Status */
+#define REG_TAL_INTSTATUS66 (0x4101E062) /**< \brief (TAL) Interrupt 66 Status */
+#define REG_TAL_INTSTATUS67 (0x4101E063) /**< \brief (TAL) Interrupt 67 Status */
+#define REG_TAL_INTSTATUS68 (0x4101E064) /**< \brief (TAL) Interrupt 68 Status */
+#define REG_TAL_INTSTATUS69 (0x4101E065) /**< \brief (TAL) Interrupt 69 Status */
+#define REG_TAL_INTSTATUS70 (0x4101E066) /**< \brief (TAL) Interrupt 70 Status */
+#define REG_TAL_INTSTATUS71 (0x4101E067) /**< \brief (TAL) Interrupt 71 Status */
+#define REG_TAL_INTSTATUS72 (0x4101E068) /**< \brief (TAL) Interrupt 72 Status */
+#define REG_TAL_INTSTATUS73 (0x4101E069) /**< \brief (TAL) Interrupt 73 Status */
+#define REG_TAL_INTSTATUS74 (0x4101E06A) /**< \brief (TAL) Interrupt 74 Status */
+#define REG_TAL_INTSTATUS75 (0x4101E06B) /**< \brief (TAL) Interrupt 75 Status */
+#define REG_TAL_INTSTATUS76 (0x4101E06C) /**< \brief (TAL) Interrupt 76 Status */
+#define REG_TAL_INTSTATUS77 (0x4101E06D) /**< \brief (TAL) Interrupt 77 Status */
+#define REG_TAL_INTSTATUS78 (0x4101E06E) /**< \brief (TAL) Interrupt 78 Status */
+#define REG_TAL_INTSTATUS79 (0x4101E06F) /**< \brief (TAL) Interrupt 79 Status */
+#define REG_TAL_INTSTATUS80 (0x4101E070) /**< \brief (TAL) Interrupt 80 Status */
+#define REG_TAL_INTSTATUS81 (0x4101E071) /**< \brief (TAL) Interrupt 81 Status */
+#define REG_TAL_INTSTATUS82 (0x4101E072) /**< \brief (TAL) Interrupt 82 Status */
+#define REG_TAL_INTSTATUS83 (0x4101E073) /**< \brief (TAL) Interrupt 83 Status */
+#define REG_TAL_INTSTATUS84 (0x4101E074) /**< \brief (TAL) Interrupt 84 Status */
+#define REG_TAL_INTSTATUS85 (0x4101E075) /**< \brief (TAL) Interrupt 85 Status */
+#define REG_TAL_INTSTATUS86 (0x4101E076) /**< \brief (TAL) Interrupt 86 Status */
+#define REG_TAL_INTSTATUS87 (0x4101E077) /**< \brief (TAL) Interrupt 87 Status */
+#define REG_TAL_INTSTATUS88 (0x4101E078) /**< \brief (TAL) Interrupt 88 Status */
+#define REG_TAL_INTSTATUS89 (0x4101E079) /**< \brief (TAL) Interrupt 89 Status */
+#define REG_TAL_INTSTATUS90 (0x4101E07A) /**< \brief (TAL) Interrupt 90 Status */
+#define REG_TAL_INTSTATUS91 (0x4101E07B) /**< \brief (TAL) Interrupt 91 Status */
+#define REG_TAL_INTSTATUS92 (0x4101E07C) /**< \brief (TAL) Interrupt 92 Status */
+#define REG_TAL_INTSTATUS93 (0x4101E07D) /**< \brief (TAL) Interrupt 93 Status */
+#define REG_TAL_INTSTATUS94 (0x4101E07E) /**< \brief (TAL) Interrupt 94 Status */
+#define REG_TAL_INTSTATUS95 (0x4101E07F) /**< \brief (TAL) Interrupt 95 Status */
+#define REG_TAL_INTSTATUS96 (0x4101E080) /**< \brief (TAL) Interrupt 96 Status */
+#define REG_TAL_INTSTATUS97 (0x4101E081) /**< \brief (TAL) Interrupt 97 Status */
+#define REG_TAL_INTSTATUS98 (0x4101E082) /**< \brief (TAL) Interrupt 98 Status */
+#define REG_TAL_INTSTATUS99 (0x4101E083) /**< \brief (TAL) Interrupt 99 Status */
+#define REG_TAL_INTSTATUS100 (0x4101E084) /**< \brief (TAL) Interrupt 100 Status */
+#define REG_TAL_INTSTATUS101 (0x4101E085) /**< \brief (TAL) Interrupt 101 Status */
+#define REG_TAL_INTSTATUS102 (0x4101E086) /**< \brief (TAL) Interrupt 102 Status */
+#define REG_TAL_INTSTATUS103 (0x4101E087) /**< \brief (TAL) Interrupt 103 Status */
+#define REG_TAL_INTSTATUS104 (0x4101E088) /**< \brief (TAL) Interrupt 104 Status */
+#define REG_TAL_INTSTATUS105 (0x4101E089) /**< \brief (TAL) Interrupt 105 Status */
+#define REG_TAL_INTSTATUS106 (0x4101E08A) /**< \brief (TAL) Interrupt 106 Status */
+#define REG_TAL_INTSTATUS107 (0x4101E08B) /**< \brief (TAL) Interrupt 107 Status */
+#define REG_TAL_INTSTATUS108 (0x4101E08C) /**< \brief (TAL) Interrupt 108 Status */
+#define REG_TAL_INTSTATUS109 (0x4101E08D) /**< \brief (TAL) Interrupt 109 Status */
+#define REG_TAL_INTSTATUS110 (0x4101E08E) /**< \brief (TAL) Interrupt 110 Status */
+#define REG_TAL_INTSTATUS111 (0x4101E08F) /**< \brief (TAL) Interrupt 111 Status */
+#define REG_TAL_INTSTATUS112 (0x4101E090) /**< \brief (TAL) Interrupt 112 Status */
+#define REG_TAL_INTSTATUS113 (0x4101E091) /**< \brief (TAL) Interrupt 113 Status */
+#define REG_TAL_INTSTATUS114 (0x4101E092) /**< \brief (TAL) Interrupt 114 Status */
+#define REG_TAL_INTSTATUS115 (0x4101E093) /**< \brief (TAL) Interrupt 115 Status */
+#define REG_TAL_INTSTATUS116 (0x4101E094) /**< \brief (TAL) Interrupt 116 Status */
+#define REG_TAL_INTSTATUS117 (0x4101E095) /**< \brief (TAL) Interrupt 117 Status */
+#define REG_TAL_INTSTATUS118 (0x4101E096) /**< \brief (TAL) Interrupt 118 Status */
+#define REG_TAL_INTSTATUS119 (0x4101E097) /**< \brief (TAL) Interrupt 119 Status */
+#define REG_TAL_INTSTATUS120 (0x4101E098) /**< \brief (TAL) Interrupt 120 Status */
+#define REG_TAL_INTSTATUS121 (0x4101E099) /**< \brief (TAL) Interrupt 121 Status */
+#define REG_TAL_INTSTATUS122 (0x4101E09A) /**< \brief (TAL) Interrupt 122 Status */
+#define REG_TAL_INTSTATUS123 (0x4101E09B) /**< \brief (TAL) Interrupt 123 Status */
+#define REG_TAL_INTSTATUS124 (0x4101E09C) /**< \brief (TAL) Interrupt 124 Status */
+#define REG_TAL_INTSTATUS125 (0x4101E09D) /**< \brief (TAL) Interrupt 125 Status */
+#define REG_TAL_INTSTATUS126 (0x4101E09E) /**< \brief (TAL) Interrupt 126 Status */
+#define REG_TAL_INTSTATUS127 (0x4101E09F) /**< \brief (TAL) Interrupt 127 Status */
+#define REG_TAL_INTSTATUS128 (0x4101E0A0) /**< \brief (TAL) Interrupt 128 Status */
+#define REG_TAL_INTSTATUS129 (0x4101E0A1) /**< \brief (TAL) Interrupt 129 Status */
+#define REG_TAL_INTSTATUS130 (0x4101E0A2) /**< \brief (TAL) Interrupt 130 Status */
+#define REG_TAL_INTSTATUS131 (0x4101E0A3) /**< \brief (TAL) Interrupt 131 Status */
+#define REG_TAL_INTSTATUS132 (0x4101E0A4) /**< \brief (TAL) Interrupt 132 Status */
+#define REG_TAL_INTSTATUS133 (0x4101E0A5) /**< \brief (TAL) Interrupt 133 Status */
+#define REG_TAL_INTSTATUS134 (0x4101E0A6) /**< \brief (TAL) Interrupt 134 Status */
+#define REG_TAL_INTSTATUS135 (0x4101E0A7) /**< \brief (TAL) Interrupt 135 Status */
+#define REG_TAL_INTSTATUS136 (0x4101E0A8) /**< \brief (TAL) Interrupt 136 Status */
+#define REG_TAL_DMACPUSEL0 (0x4101E110) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
+#define REG_TAL_DMACPUSEL1 (0x4101E114) /**< \brief (TAL) DMA Channel Interrupts CPU Select 1 */
+#define REG_TAL_EVCPUSEL0 (0x4101E118) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
+#define REG_TAL_EICCPUSEL0 (0x4101E120) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL0 (0x4101E128) /**< \brief (TAL) Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL1 (0x4101E12C) /**< \brief (TAL) Interrupts CPU Select 1 */
+#define REG_TAL_INTCPUSEL2 (0x4101E130) /**< \brief (TAL) Interrupts CPU Select 2 */
+#define REG_TAL_INTCPUSEL3 (0x4101E134) /**< \brief (TAL) Interrupts CPU Select 3 */
+#define REG_TAL_INTCPUSEL4 (0x4101E138) /**< \brief (TAL) Interrupts CPU Select 4 */
+#define REG_TAL_INTCPUSEL5 (0x4101E13C) /**< \brief (TAL) Interrupts CPU Select 5 */
+#define REG_TAL_INTCPUSEL6 (0x4101E140) /**< \brief (TAL) Interrupts CPU Select 6 */
+#define REG_TAL_INTCPUSEL7 (0x4101E144) /**< \brief (TAL) Interrupts CPU Select 7 */
+#define REG_TAL_INTCPUSEL8 (0x4101E148) /**< \brief (TAL) Interrupts CPU Select 8 */
+#define REG_TAL_IRQTRIG (0x4101E164) /**< \brief (TAL) Interrupt Trigger */
+#define REG_TAL_IRQMON0 (0x4101E168) /**< \brief (TAL) Interrupt Monitor Select 0 */
+#define REG_TAL_CPUIRQS0 (0x4101E180) /**< \brief (TAL) Interrupt Status m for CPU 0 */
+#define REG_TAL_CPUIRQS1 (0x4101E1A0) /**< \brief (TAL) Interrupt Status m for CPU 1 */
+#define REG_TAL_SMASK0 (0x4101E200) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 0 */
+#define REG_TAL_SMASK1 (0x4101E208) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 1 */
+#define REG_TAL_SFLAGCLR0 (0x4101E220) /**< \brief (TAL) Inter-Process Signal Flag Clear 0 */
+#define REG_TAL_SFLAGCLR1 (0x4101E224) /**< \brief (TAL) Inter-Process Signal Flag Clear 1 */
+#define REG_TAL_SFLAGSET0 (0x4101E228) /**< \brief (TAL) Inter-Process Signal Flag Set 0 */
+#define REG_TAL_SFLAGSET1 (0x4101E22C) /**< \brief (TAL) Inter-Process Signal Flag Set 1 */
+#define REG_TAL_SFLAG0 (0x4101E230) /**< \brief (TAL) Inter-Process Signal Flag 0 */
+#define REG_TAL_SFLAG1 (0x4101E234) /**< \brief (TAL) Inter-Process Signal Flag 1 */
+#define REG_TAL_SFLAGCLRR0 (0x4101E300) /**< \brief (TAL) Inter-Process Signal Flag Bit 0 */
+#define REG_TAL_SFLAGCLRR1 (0x4101E301) /**< \brief (TAL) Inter-Process Signal Flag Bit 1 */
+#define REG_TAL_SFLAGCLRR2 (0x4101E302) /**< \brief (TAL) Inter-Process Signal Flag Bit 2 */
+#define REG_TAL_SFLAGCLRR3 (0x4101E303) /**< \brief (TAL) Inter-Process Signal Flag Bit 3 */
+#define REG_TAL_SFLAGCLRR4 (0x4101E304) /**< \brief (TAL) Inter-Process Signal Flag Bit 4 */
+#define REG_TAL_SFLAGCLRR5 (0x4101E305) /**< \brief (TAL) Inter-Process Signal Flag Bit 5 */
+#define REG_TAL_SFLAGCLRR6 (0x4101E306) /**< \brief (TAL) Inter-Process Signal Flag Bit 6 */
+#define REG_TAL_SFLAGCLRR7 (0x4101E307) /**< \brief (TAL) Inter-Process Signal Flag Bit 7 */
+#define REG_TAL_SFLAGCLRR8 (0x4101E308) /**< \brief (TAL) Inter-Process Signal Flag Bit 8 */
+#define REG_TAL_SFLAGCLRR9 (0x4101E309) /**< \brief (TAL) Inter-Process Signal Flag Bit 9 */
+#define REG_TAL_SFLAGCLRR10 (0x4101E30A) /**< \brief (TAL) Inter-Process Signal Flag Bit 10 */
+#define REG_TAL_SFLAGCLRR11 (0x4101E30B) /**< \brief (TAL) Inter-Process Signal Flag Bit 11 */
+#define REG_TAL_SFLAGCLRR12 (0x4101E30C) /**< \brief (TAL) Inter-Process Signal Flag Bit 12 */
+#define REG_TAL_SFLAGCLRR13 (0x4101E30D) /**< \brief (TAL) Inter-Process Signal Flag Bit 13 */
+#define REG_TAL_SFLAGCLRR14 (0x4101E30E) /**< \brief (TAL) Inter-Process Signal Flag Bit 14 */
+#define REG_TAL_SFLAGCLRR15 (0x4101E30F) /**< \brief (TAL) Inter-Process Signal Flag Bit 15 */
+#define REG_TAL_SFLAGCLRR16 (0x4101E310) /**< \brief (TAL) Inter-Process Signal Flag Bit 16 */
+#define REG_TAL_SFLAGCLRR17 (0x4101E311) /**< \brief (TAL) Inter-Process Signal Flag Bit 17 */
+#define REG_TAL_SFLAGCLRR18 (0x4101E312) /**< \brief (TAL) Inter-Process Signal Flag Bit 18 */
+#define REG_TAL_SFLAGCLRR19 (0x4101E313) /**< \brief (TAL) Inter-Process Signal Flag Bit 19 */
+#define REG_TAL_SFLAGCLRR20 (0x4101E314) /**< \brief (TAL) Inter-Process Signal Flag Bit 20 */
+#define REG_TAL_SFLAGCLRR21 (0x4101E315) /**< \brief (TAL) Inter-Process Signal Flag Bit 21 */
+#define REG_TAL_SFLAGCLRR22 (0x4101E316) /**< \brief (TAL) Inter-Process Signal Flag Bit 22 */
+#define REG_TAL_SFLAGCLRR23 (0x4101E317) /**< \brief (TAL) Inter-Process Signal Flag Bit 23 */
+#define REG_TAL_SFLAGCLRR24 (0x4101E318) /**< \brief (TAL) Inter-Process Signal Flag Bit 24 */
+#define REG_TAL_SFLAGCLRR25 (0x4101E319) /**< \brief (TAL) Inter-Process Signal Flag Bit 25 */
+#define REG_TAL_SFLAGCLRR26 (0x4101E31A) /**< \brief (TAL) Inter-Process Signal Flag Bit 26 */
+#define REG_TAL_SFLAGCLRR27 (0x4101E31B) /**< \brief (TAL) Inter-Process Signal Flag Bit 27 */
+#define REG_TAL_SFLAGCLRR28 (0x4101E31C) /**< \brief (TAL) Inter-Process Signal Flag Bit 28 */
+#define REG_TAL_SFLAGCLRR29 (0x4101E31D) /**< \brief (TAL) Inter-Process Signal Flag Bit 29 */
+#define REG_TAL_SFLAGCLRR30 (0x4101E31E) /**< \brief (TAL) Inter-Process Signal Flag Bit 30 */
+#define REG_TAL_SFLAGCLRR31 (0x4101E31F) /**< \brief (TAL) Inter-Process Signal Flag Bit 31 */
+#define REG_TAL_SFLAGCLRR32 (0x4101E320) /**< \brief (TAL) Inter-Process Signal Flag Bit 32 */
+#define REG_TAL_SFLAGCLRR33 (0x4101E321) /**< \brief (TAL) Inter-Process Signal Flag Bit 33 */
+#define REG_TAL_SFLAGCLRR34 (0x4101E322) /**< \brief (TAL) Inter-Process Signal Flag Bit 34 */
+#define REG_TAL_SFLAGCLRR35 (0x4101E323) /**< \brief (TAL) Inter-Process Signal Flag Bit 35 */
+#define REG_TAL_SFLAGCLRR36 (0x4101E324) /**< \brief (TAL) Inter-Process Signal Flag Bit 36 */
+#define REG_TAL_SFLAGCLRR37 (0x4101E325) /**< \brief (TAL) Inter-Process Signal Flag Bit 37 */
+#define REG_TAL_SFLAGCLRR38 (0x4101E326) /**< \brief (TAL) Inter-Process Signal Flag Bit 38 */
+#define REG_TAL_SFLAGCLRR39 (0x4101E327) /**< \brief (TAL) Inter-Process Signal Flag Bit 39 */
+#define REG_TAL_SFLAGCLRR40 (0x4101E328) /**< \brief (TAL) Inter-Process Signal Flag Bit 40 */
+#define REG_TAL_SFLAGCLRR41 (0x4101E329) /**< \brief (TAL) Inter-Process Signal Flag Bit 41 */
+#define REG_TAL_SFLAGCLRR42 (0x4101E32A) /**< \brief (TAL) Inter-Process Signal Flag Bit 42 */
+#define REG_TAL_SFLAGCLRR43 (0x4101E32B) /**< \brief (TAL) Inter-Process Signal Flag Bit 43 */
+#define REG_TAL_SFLAGCLRR44 (0x4101E32C) /**< \brief (TAL) Inter-Process Signal Flag Bit 44 */
+#define REG_TAL_SFLAGCLRR45 (0x4101E32D) /**< \brief (TAL) Inter-Process Signal Flag Bit 45 */
+#define REG_TAL_SFLAGCLRR46 (0x4101E32E) /**< \brief (TAL) Inter-Process Signal Flag Bit 46 */
+#define REG_TAL_SFLAGCLRR47 (0x4101E32F) /**< \brief (TAL) Inter-Process Signal Flag Bit 47 */
+#define REG_TAL_SFLAGCLRR48 (0x4101E330) /**< \brief (TAL) Inter-Process Signal Flag Bit 48 */
+#define REG_TAL_SFLAGCLRR49 (0x4101E331) /**< \brief (TAL) Inter-Process Signal Flag Bit 49 */
+#define REG_TAL_SFLAGCLRR50 (0x4101E332) /**< \brief (TAL) Inter-Process Signal Flag Bit 50 */
+#define REG_TAL_SFLAGCLRR51 (0x4101E333) /**< \brief (TAL) Inter-Process Signal Flag Bit 51 */
+#define REG_TAL_SFLAGCLRR52 (0x4101E334) /**< \brief (TAL) Inter-Process Signal Flag Bit 52 */
+#define REG_TAL_SFLAGCLRR53 (0x4101E335) /**< \brief (TAL) Inter-Process Signal Flag Bit 53 */
+#define REG_TAL_SFLAGCLRR54 (0x4101E336) /**< \brief (TAL) Inter-Process Signal Flag Bit 54 */
+#define REG_TAL_SFLAGCLRR55 (0x4101E337) /**< \brief (TAL) Inter-Process Signal Flag Bit 55 */
+#define REG_TAL_SFLAGCLRR56 (0x4101E338) /**< \brief (TAL) Inter-Process Signal Flag Bit 56 */
+#define REG_TAL_SFLAGCLRR57 (0x4101E339) /**< \brief (TAL) Inter-Process Signal Flag Bit 57 */
+#define REG_TAL_SFLAGCLRR58 (0x4101E33A) /**< \brief (TAL) Inter-Process Signal Flag Bit 58 */
+#define REG_TAL_SFLAGCLRR59 (0x4101E33B) /**< \brief (TAL) Inter-Process Signal Flag Bit 59 */
+#define REG_TAL_SFLAGCLRR60 (0x4101E33C) /**< \brief (TAL) Inter-Process Signal Flag Bit 60 */
+#define REG_TAL_SFLAGCLRR61 (0x4101E33D) /**< \brief (TAL) Inter-Process Signal Flag Bit 61 */
+#define REG_TAL_SFLAGCLRR62 (0x4101E33E) /**< \brief (TAL) Inter-Process Signal Flag Bit 62 */
+#define REG_TAL_SFLAGCLRR63 (0x4101E33F) /**< \brief (TAL) Inter-Process Signal Flag Bit 63 */
+#else
+#define REG_TAL_CTRLA (*(RwReg8 *)0x4101E000UL) /**< \brief (TAL) Control A */
+#define REG_TAL_EXTCTRL (*(RwReg8 *)0x4101E001UL) /**< \brief (TAL) External Break Control */
+#define REG_TAL_EVCTRL (*(RwReg16*)0x4101E004UL) /**< \brief (TAL) Event Control */
+#define REG_TAL_INTENCLR (*(RwReg8 *)0x4101E008UL) /**< \brief (TAL) Interrupt Enable Clear */
+#define REG_TAL_INTENSET (*(RwReg8 *)0x4101E009UL) /**< \brief (TAL) Interrupt Enable Set */
+#define REG_TAL_INTFLAG (*(RwReg8 *)0x4101E00AUL) /**< \brief (TAL) Interrupt Flag Status and Clear */
+#define REG_TAL_GLOBMASK (*(RwReg8 *)0x4101E00BUL) /**< \brief (TAL) Global Break Requests Mask */
+#define REG_TAL_HALT (*(WoReg8 *)0x4101E00CUL) /**< \brief (TAL) Debug Halt Request */
+#define REG_TAL_RESTART (*(WoReg8 *)0x4101E00DUL) /**< \brief (TAL) Debug Restart Request */
+#define REG_TAL_BRKSTATUS (*(RoReg16*)0x4101E00EUL) /**< \brief (TAL) Break Request Status */
+#define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x4101E010UL) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
+#define REG_TAL_CTIMASK0 (*(RwReg8 *)0x4101E011UL) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
+#define REG_TAL_CTICTRLA1 (*(RwReg8 *)0x4101E012UL) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
+#define REG_TAL_CTIMASK1 (*(RwReg8 *)0x4101E013UL) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
+#define REG_TAL_CTICTRLA2 (*(RwReg8 *)0x4101E014UL) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
+#define REG_TAL_CTIMASK2 (*(RwReg8 *)0x4101E015UL) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
+#define REG_TAL_CTICTRLA3 (*(RwReg8 *)0x4101E016UL) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */
+#define REG_TAL_CTIMASK3 (*(RwReg8 *)0x4101E017UL) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */
+#define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x4101E020UL) /**< \brief (TAL) Interrupt 0 Status */
+#define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x4101E021UL) /**< \brief (TAL) Interrupt 1 Status */
+#define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x4101E022UL) /**< \brief (TAL) Interrupt 2 Status */
+#define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x4101E023UL) /**< \brief (TAL) Interrupt 3 Status */
+#define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x4101E024UL) /**< \brief (TAL) Interrupt 4 Status */
+#define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x4101E025UL) /**< \brief (TAL) Interrupt 5 Status */
+#define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x4101E026UL) /**< \brief (TAL) Interrupt 6 Status */
+#define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x4101E027UL) /**< \brief (TAL) Interrupt 7 Status */
+#define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x4101E028UL) /**< \brief (TAL) Interrupt 8 Status */
+#define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x4101E029UL) /**< \brief (TAL) Interrupt 9 Status */
+#define REG_TAL_INTSTATUS10 (*(RoReg8 *)0x4101E02AUL) /**< \brief (TAL) Interrupt 10 Status */
+#define REG_TAL_INTSTATUS11 (*(RoReg8 *)0x4101E02BUL) /**< \brief (TAL) Interrupt 11 Status */
+#define REG_TAL_INTSTATUS12 (*(RoReg8 *)0x4101E02CUL) /**< \brief (TAL) Interrupt 12 Status */
+#define REG_TAL_INTSTATUS13 (*(RoReg8 *)0x4101E02DUL) /**< \brief (TAL) Interrupt 13 Status */
+#define REG_TAL_INTSTATUS14 (*(RoReg8 *)0x4101E02EUL) /**< \brief (TAL) Interrupt 14 Status */
+#define REG_TAL_INTSTATUS15 (*(RoReg8 *)0x4101E02FUL) /**< \brief (TAL) Interrupt 15 Status */
+#define REG_TAL_INTSTATUS16 (*(RoReg8 *)0x4101E030UL) /**< \brief (TAL) Interrupt 16 Status */
+#define REG_TAL_INTSTATUS17 (*(RoReg8 *)0x4101E031UL) /**< \brief (TAL) Interrupt 17 Status */
+#define REG_TAL_INTSTATUS18 (*(RoReg8 *)0x4101E032UL) /**< \brief (TAL) Interrupt 18 Status */
+#define REG_TAL_INTSTATUS19 (*(RoReg8 *)0x4101E033UL) /**< \brief (TAL) Interrupt 19 Status */
+#define REG_TAL_INTSTATUS20 (*(RoReg8 *)0x4101E034UL) /**< \brief (TAL) Interrupt 20 Status */
+#define REG_TAL_INTSTATUS21 (*(RoReg8 *)0x4101E035UL) /**< \brief (TAL) Interrupt 21 Status */
+#define REG_TAL_INTSTATUS22 (*(RoReg8 *)0x4101E036UL) /**< \brief (TAL) Interrupt 22 Status */
+#define REG_TAL_INTSTATUS23 (*(RoReg8 *)0x4101E037UL) /**< \brief (TAL) Interrupt 23 Status */
+#define REG_TAL_INTSTATUS24 (*(RoReg8 *)0x4101E038UL) /**< \brief (TAL) Interrupt 24 Status */
+#define REG_TAL_INTSTATUS25 (*(RoReg8 *)0x4101E039UL) /**< \brief (TAL) Interrupt 25 Status */
+#define REG_TAL_INTSTATUS26 (*(RoReg8 *)0x4101E03AUL) /**< \brief (TAL) Interrupt 26 Status */
+#define REG_TAL_INTSTATUS27 (*(RoReg8 *)0x4101E03BUL) /**< \brief (TAL) Interrupt 27 Status */
+#define REG_TAL_INTSTATUS28 (*(RoReg8 *)0x4101E03CUL) /**< \brief (TAL) Interrupt 28 Status */
+#define REG_TAL_INTSTATUS29 (*(RoReg8 *)0x4101E03DUL) /**< \brief (TAL) Interrupt 29 Status */
+#define REG_TAL_INTSTATUS30 (*(RoReg8 *)0x4101E03EUL) /**< \brief (TAL) Interrupt 30 Status */
+#define REG_TAL_INTSTATUS31 (*(RoReg8 *)0x4101E03FUL) /**< \brief (TAL) Interrupt 31 Status */
+#define REG_TAL_INTSTATUS32 (*(RoReg8 *)0x4101E040UL) /**< \brief (TAL) Interrupt 32 Status */
+#define REG_TAL_INTSTATUS33 (*(RoReg8 *)0x4101E041UL) /**< \brief (TAL) Interrupt 33 Status */
+#define REG_TAL_INTSTATUS34 (*(RoReg8 *)0x4101E042UL) /**< \brief (TAL) Interrupt 34 Status */
+#define REG_TAL_INTSTATUS35 (*(RoReg8 *)0x4101E043UL) /**< \brief (TAL) Interrupt 35 Status */
+#define REG_TAL_INTSTATUS36 (*(RoReg8 *)0x4101E044UL) /**< \brief (TAL) Interrupt 36 Status */
+#define REG_TAL_INTSTATUS37 (*(RoReg8 *)0x4101E045UL) /**< \brief (TAL) Interrupt 37 Status */
+#define REG_TAL_INTSTATUS38 (*(RoReg8 *)0x4101E046UL) /**< \brief (TAL) Interrupt 38 Status */
+#define REG_TAL_INTSTATUS39 (*(RoReg8 *)0x4101E047UL) /**< \brief (TAL) Interrupt 39 Status */
+#define REG_TAL_INTSTATUS40 (*(RoReg8 *)0x4101E048UL) /**< \brief (TAL) Interrupt 40 Status */
+#define REG_TAL_INTSTATUS41 (*(RoReg8 *)0x4101E049UL) /**< \brief (TAL) Interrupt 41 Status */
+#define REG_TAL_INTSTATUS42 (*(RoReg8 *)0x4101E04AUL) /**< \brief (TAL) Interrupt 42 Status */
+#define REG_TAL_INTSTATUS43 (*(RoReg8 *)0x4101E04BUL) /**< \brief (TAL) Interrupt 43 Status */
+#define REG_TAL_INTSTATUS44 (*(RoReg8 *)0x4101E04CUL) /**< \brief (TAL) Interrupt 44 Status */
+#define REG_TAL_INTSTATUS45 (*(RoReg8 *)0x4101E04DUL) /**< \brief (TAL) Interrupt 45 Status */
+#define REG_TAL_INTSTATUS46 (*(RoReg8 *)0x4101E04EUL) /**< \brief (TAL) Interrupt 46 Status */
+#define REG_TAL_INTSTATUS47 (*(RoReg8 *)0x4101E04FUL) /**< \brief (TAL) Interrupt 47 Status */
+#define REG_TAL_INTSTATUS48 (*(RoReg8 *)0x4101E050UL) /**< \brief (TAL) Interrupt 48 Status */
+#define REG_TAL_INTSTATUS49 (*(RoReg8 *)0x4101E051UL) /**< \brief (TAL) Interrupt 49 Status */
+#define REG_TAL_INTSTATUS50 (*(RoReg8 *)0x4101E052UL) /**< \brief (TAL) Interrupt 50 Status */
+#define REG_TAL_INTSTATUS51 (*(RoReg8 *)0x4101E053UL) /**< \brief (TAL) Interrupt 51 Status */
+#define REG_TAL_INTSTATUS52 (*(RoReg8 *)0x4101E054UL) /**< \brief (TAL) Interrupt 52 Status */
+#define REG_TAL_INTSTATUS53 (*(RoReg8 *)0x4101E055UL) /**< \brief (TAL) Interrupt 53 Status */
+#define REG_TAL_INTSTATUS54 (*(RoReg8 *)0x4101E056UL) /**< \brief (TAL) Interrupt 54 Status */
+#define REG_TAL_INTSTATUS55 (*(RoReg8 *)0x4101E057UL) /**< \brief (TAL) Interrupt 55 Status */
+#define REG_TAL_INTSTATUS56 (*(RoReg8 *)0x4101E058UL) /**< \brief (TAL) Interrupt 56 Status */
+#define REG_TAL_INTSTATUS57 (*(RoReg8 *)0x4101E059UL) /**< \brief (TAL) Interrupt 57 Status */
+#define REG_TAL_INTSTATUS58 (*(RoReg8 *)0x4101E05AUL) /**< \brief (TAL) Interrupt 58 Status */
+#define REG_TAL_INTSTATUS59 (*(RoReg8 *)0x4101E05BUL) /**< \brief (TAL) Interrupt 59 Status */
+#define REG_TAL_INTSTATUS60 (*(RoReg8 *)0x4101E05CUL) /**< \brief (TAL) Interrupt 60 Status */
+#define REG_TAL_INTSTATUS61 (*(RoReg8 *)0x4101E05DUL) /**< \brief (TAL) Interrupt 61 Status */
+#define REG_TAL_INTSTATUS62 (*(RoReg8 *)0x4101E05EUL) /**< \brief (TAL) Interrupt 62 Status */
+#define REG_TAL_INTSTATUS63 (*(RoReg8 *)0x4101E05FUL) /**< \brief (TAL) Interrupt 63 Status */
+#define REG_TAL_INTSTATUS64 (*(RoReg8 *)0x4101E060UL) /**< \brief (TAL) Interrupt 64 Status */
+#define REG_TAL_INTSTATUS65 (*(RoReg8 *)0x4101E061UL) /**< \brief (TAL) Interrupt 65 Status */
+#define REG_TAL_INTSTATUS66 (*(RoReg8 *)0x4101E062UL) /**< \brief (TAL) Interrupt 66 Status */
+#define REG_TAL_INTSTATUS67 (*(RoReg8 *)0x4101E063UL) /**< \brief (TAL) Interrupt 67 Status */
+#define REG_TAL_INTSTATUS68 (*(RoReg8 *)0x4101E064UL) /**< \brief (TAL) Interrupt 68 Status */
+#define REG_TAL_INTSTATUS69 (*(RoReg8 *)0x4101E065UL) /**< \brief (TAL) Interrupt 69 Status */
+#define REG_TAL_INTSTATUS70 (*(RoReg8 *)0x4101E066UL) /**< \brief (TAL) Interrupt 70 Status */
+#define REG_TAL_INTSTATUS71 (*(RoReg8 *)0x4101E067UL) /**< \brief (TAL) Interrupt 71 Status */
+#define REG_TAL_INTSTATUS72 (*(RoReg8 *)0x4101E068UL) /**< \brief (TAL) Interrupt 72 Status */
+#define REG_TAL_INTSTATUS73 (*(RoReg8 *)0x4101E069UL) /**< \brief (TAL) Interrupt 73 Status */
+#define REG_TAL_INTSTATUS74 (*(RoReg8 *)0x4101E06AUL) /**< \brief (TAL) Interrupt 74 Status */
+#define REG_TAL_INTSTATUS75 (*(RoReg8 *)0x4101E06BUL) /**< \brief (TAL) Interrupt 75 Status */
+#define REG_TAL_INTSTATUS76 (*(RoReg8 *)0x4101E06CUL) /**< \brief (TAL) Interrupt 76 Status */
+#define REG_TAL_INTSTATUS77 (*(RoReg8 *)0x4101E06DUL) /**< \brief (TAL) Interrupt 77 Status */
+#define REG_TAL_INTSTATUS78 (*(RoReg8 *)0x4101E06EUL) /**< \brief (TAL) Interrupt 78 Status */
+#define REG_TAL_INTSTATUS79 (*(RoReg8 *)0x4101E06FUL) /**< \brief (TAL) Interrupt 79 Status */
+#define REG_TAL_INTSTATUS80 (*(RoReg8 *)0x4101E070UL) /**< \brief (TAL) Interrupt 80 Status */
+#define REG_TAL_INTSTATUS81 (*(RoReg8 *)0x4101E071UL) /**< \brief (TAL) Interrupt 81 Status */
+#define REG_TAL_INTSTATUS82 (*(RoReg8 *)0x4101E072UL) /**< \brief (TAL) Interrupt 82 Status */
+#define REG_TAL_INTSTATUS83 (*(RoReg8 *)0x4101E073UL) /**< \brief (TAL) Interrupt 83 Status */
+#define REG_TAL_INTSTATUS84 (*(RoReg8 *)0x4101E074UL) /**< \brief (TAL) Interrupt 84 Status */
+#define REG_TAL_INTSTATUS85 (*(RoReg8 *)0x4101E075UL) /**< \brief (TAL) Interrupt 85 Status */
+#define REG_TAL_INTSTATUS86 (*(RoReg8 *)0x4101E076UL) /**< \brief (TAL) Interrupt 86 Status */
+#define REG_TAL_INTSTATUS87 (*(RoReg8 *)0x4101E077UL) /**< \brief (TAL) Interrupt 87 Status */
+#define REG_TAL_INTSTATUS88 (*(RoReg8 *)0x4101E078UL) /**< \brief (TAL) Interrupt 88 Status */
+#define REG_TAL_INTSTATUS89 (*(RoReg8 *)0x4101E079UL) /**< \brief (TAL) Interrupt 89 Status */
+#define REG_TAL_INTSTATUS90 (*(RoReg8 *)0x4101E07AUL) /**< \brief (TAL) Interrupt 90 Status */
+#define REG_TAL_INTSTATUS91 (*(RoReg8 *)0x4101E07BUL) /**< \brief (TAL) Interrupt 91 Status */
+#define REG_TAL_INTSTATUS92 (*(RoReg8 *)0x4101E07CUL) /**< \brief (TAL) Interrupt 92 Status */
+#define REG_TAL_INTSTATUS93 (*(RoReg8 *)0x4101E07DUL) /**< \brief (TAL) Interrupt 93 Status */
+#define REG_TAL_INTSTATUS94 (*(RoReg8 *)0x4101E07EUL) /**< \brief (TAL) Interrupt 94 Status */
+#define REG_TAL_INTSTATUS95 (*(RoReg8 *)0x4101E07FUL) /**< \brief (TAL) Interrupt 95 Status */
+#define REG_TAL_INTSTATUS96 (*(RoReg8 *)0x4101E080UL) /**< \brief (TAL) Interrupt 96 Status */
+#define REG_TAL_INTSTATUS97 (*(RoReg8 *)0x4101E081UL) /**< \brief (TAL) Interrupt 97 Status */
+#define REG_TAL_INTSTATUS98 (*(RoReg8 *)0x4101E082UL) /**< \brief (TAL) Interrupt 98 Status */
+#define REG_TAL_INTSTATUS99 (*(RoReg8 *)0x4101E083UL) /**< \brief (TAL) Interrupt 99 Status */
+#define REG_TAL_INTSTATUS100 (*(RoReg8 *)0x4101E084UL) /**< \brief (TAL) Interrupt 100 Status */
+#define REG_TAL_INTSTATUS101 (*(RoReg8 *)0x4101E085UL) /**< \brief (TAL) Interrupt 101 Status */
+#define REG_TAL_INTSTATUS102 (*(RoReg8 *)0x4101E086UL) /**< \brief (TAL) Interrupt 102 Status */
+#define REG_TAL_INTSTATUS103 (*(RoReg8 *)0x4101E087UL) /**< \brief (TAL) Interrupt 103 Status */
+#define REG_TAL_INTSTATUS104 (*(RoReg8 *)0x4101E088UL) /**< \brief (TAL) Interrupt 104 Status */
+#define REG_TAL_INTSTATUS105 (*(RoReg8 *)0x4101E089UL) /**< \brief (TAL) Interrupt 105 Status */
+#define REG_TAL_INTSTATUS106 (*(RoReg8 *)0x4101E08AUL) /**< \brief (TAL) Interrupt 106 Status */
+#define REG_TAL_INTSTATUS107 (*(RoReg8 *)0x4101E08BUL) /**< \brief (TAL) Interrupt 107 Status */
+#define REG_TAL_INTSTATUS108 (*(RoReg8 *)0x4101E08CUL) /**< \brief (TAL) Interrupt 108 Status */
+#define REG_TAL_INTSTATUS109 (*(RoReg8 *)0x4101E08DUL) /**< \brief (TAL) Interrupt 109 Status */
+#define REG_TAL_INTSTATUS110 (*(RoReg8 *)0x4101E08EUL) /**< \brief (TAL) Interrupt 110 Status */
+#define REG_TAL_INTSTATUS111 (*(RoReg8 *)0x4101E08FUL) /**< \brief (TAL) Interrupt 111 Status */
+#define REG_TAL_INTSTATUS112 (*(RoReg8 *)0x4101E090UL) /**< \brief (TAL) Interrupt 112 Status */
+#define REG_TAL_INTSTATUS113 (*(RoReg8 *)0x4101E091UL) /**< \brief (TAL) Interrupt 113 Status */
+#define REG_TAL_INTSTATUS114 (*(RoReg8 *)0x4101E092UL) /**< \brief (TAL) Interrupt 114 Status */
+#define REG_TAL_INTSTATUS115 (*(RoReg8 *)0x4101E093UL) /**< \brief (TAL) Interrupt 115 Status */
+#define REG_TAL_INTSTATUS116 (*(RoReg8 *)0x4101E094UL) /**< \brief (TAL) Interrupt 116 Status */
+#define REG_TAL_INTSTATUS117 (*(RoReg8 *)0x4101E095UL) /**< \brief (TAL) Interrupt 117 Status */
+#define REG_TAL_INTSTATUS118 (*(RoReg8 *)0x4101E096UL) /**< \brief (TAL) Interrupt 118 Status */
+#define REG_TAL_INTSTATUS119 (*(RoReg8 *)0x4101E097UL) /**< \brief (TAL) Interrupt 119 Status */
+#define REG_TAL_INTSTATUS120 (*(RoReg8 *)0x4101E098UL) /**< \brief (TAL) Interrupt 120 Status */
+#define REG_TAL_INTSTATUS121 (*(RoReg8 *)0x4101E099UL) /**< \brief (TAL) Interrupt 121 Status */
+#define REG_TAL_INTSTATUS122 (*(RoReg8 *)0x4101E09AUL) /**< \brief (TAL) Interrupt 122 Status */
+#define REG_TAL_INTSTATUS123 (*(RoReg8 *)0x4101E09BUL) /**< \brief (TAL) Interrupt 123 Status */
+#define REG_TAL_INTSTATUS124 (*(RoReg8 *)0x4101E09CUL) /**< \brief (TAL) Interrupt 124 Status */
+#define REG_TAL_INTSTATUS125 (*(RoReg8 *)0x4101E09DUL) /**< \brief (TAL) Interrupt 125 Status */
+#define REG_TAL_INTSTATUS126 (*(RoReg8 *)0x4101E09EUL) /**< \brief (TAL) Interrupt 126 Status */
+#define REG_TAL_INTSTATUS127 (*(RoReg8 *)0x4101E09FUL) /**< \brief (TAL) Interrupt 127 Status */
+#define REG_TAL_INTSTATUS128 (*(RoReg8 *)0x4101E0A0UL) /**< \brief (TAL) Interrupt 128 Status */
+#define REG_TAL_INTSTATUS129 (*(RoReg8 *)0x4101E0A1UL) /**< \brief (TAL) Interrupt 129 Status */
+#define REG_TAL_INTSTATUS130 (*(RoReg8 *)0x4101E0A2UL) /**< \brief (TAL) Interrupt 130 Status */
+#define REG_TAL_INTSTATUS131 (*(RoReg8 *)0x4101E0A3UL) /**< \brief (TAL) Interrupt 131 Status */
+#define REG_TAL_INTSTATUS132 (*(RoReg8 *)0x4101E0A4UL) /**< \brief (TAL) Interrupt 132 Status */
+#define REG_TAL_INTSTATUS133 (*(RoReg8 *)0x4101E0A5UL) /**< \brief (TAL) Interrupt 133 Status */
+#define REG_TAL_INTSTATUS134 (*(RoReg8 *)0x4101E0A6UL) /**< \brief (TAL) Interrupt 134 Status */
+#define REG_TAL_INTSTATUS135 (*(RoReg8 *)0x4101E0A7UL) /**< \brief (TAL) Interrupt 135 Status */
+#define REG_TAL_INTSTATUS136 (*(RoReg8 *)0x4101E0A8UL) /**< \brief (TAL) Interrupt 136 Status */
+#define REG_TAL_DMACPUSEL0 (*(RwReg *)0x4101E110UL) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
+#define REG_TAL_DMACPUSEL1 (*(RwReg *)0x4101E114UL) /**< \brief (TAL) DMA Channel Interrupts CPU Select 1 */
+#define REG_TAL_EVCPUSEL0 (*(RwReg *)0x4101E118UL) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
+#define REG_TAL_EICCPUSEL0 (*(RwReg *)0x4101E120UL) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL0 (*(RwReg *)0x4101E128UL) /**< \brief (TAL) Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL1 (*(RwReg *)0x4101E12CUL) /**< \brief (TAL) Interrupts CPU Select 1 */
+#define REG_TAL_INTCPUSEL2 (*(RwReg *)0x4101E130UL) /**< \brief (TAL) Interrupts CPU Select 2 */
+#define REG_TAL_INTCPUSEL3 (*(RwReg *)0x4101E134UL) /**< \brief (TAL) Interrupts CPU Select 3 */
+#define REG_TAL_INTCPUSEL4 (*(RwReg *)0x4101E138UL) /**< \brief (TAL) Interrupts CPU Select 4 */
+#define REG_TAL_INTCPUSEL5 (*(RwReg *)0x4101E13CUL) /**< \brief (TAL) Interrupts CPU Select 5 */
+#define REG_TAL_INTCPUSEL6 (*(RwReg *)0x4101E140UL) /**< \brief (TAL) Interrupts CPU Select 6 */
+#define REG_TAL_INTCPUSEL7 (*(RwReg *)0x4101E144UL) /**< \brief (TAL) Interrupts CPU Select 7 */
+#define REG_TAL_INTCPUSEL8 (*(RwReg *)0x4101E148UL) /**< \brief (TAL) Interrupts CPU Select 8 */
+#define REG_TAL_IRQTRIG (*(RwReg *)0x4101E164UL) /**< \brief (TAL) Interrupt Trigger */
+#define REG_TAL_IRQMON0 (*(RwReg16*)0x4101E168UL) /**< \brief (TAL) Interrupt Monitor Select 0 */
+#define REG_TAL_CPUIRQS0 (*(RoReg *)0x4101E180UL) /**< \brief (TAL) Interrupt Status m for CPU 0 */
+#define REG_TAL_CPUIRQS1 (*(RoReg *)0x4101E1A0UL) /**< \brief (TAL) Interrupt Status m for CPU 1 */
+#define REG_TAL_SMASK0 (*(RwReg *)0x4101E200UL) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 0 */
+#define REG_TAL_SMASK1 (*(RwReg *)0x4101E208UL) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 1 */
+#define REG_TAL_SFLAGCLR0 (*(WoReg *)0x4101E220UL) /**< \brief (TAL) Inter-Process Signal Flag Clear 0 */
+#define REG_TAL_SFLAGCLR1 (*(WoReg *)0x4101E224UL) /**< \brief (TAL) Inter-Process Signal Flag Clear 1 */
+#define REG_TAL_SFLAGSET0 (*(WoReg *)0x4101E228UL) /**< \brief (TAL) Inter-Process Signal Flag Set 0 */
+#define REG_TAL_SFLAGSET1 (*(WoReg *)0x4101E22CUL) /**< \brief (TAL) Inter-Process Signal Flag Set 1 */
+#define REG_TAL_SFLAG0 (*(RoReg *)0x4101E230UL) /**< \brief (TAL) Inter-Process Signal Flag 0 */
+#define REG_TAL_SFLAG1 (*(RoReg *)0x4101E234UL) /**< \brief (TAL) Inter-Process Signal Flag 1 */
+#define REG_TAL_SFLAGCLRR0 (*(RwReg8 *)0x4101E300UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 0 */
+#define REG_TAL_SFLAGCLRR1 (*(RwReg8 *)0x4101E301UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 1 */
+#define REG_TAL_SFLAGCLRR2 (*(RwReg8 *)0x4101E302UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 2 */
+#define REG_TAL_SFLAGCLRR3 (*(RwReg8 *)0x4101E303UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 3 */
+#define REG_TAL_SFLAGCLRR4 (*(RwReg8 *)0x4101E304UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 4 */
+#define REG_TAL_SFLAGCLRR5 (*(RwReg8 *)0x4101E305UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 5 */
+#define REG_TAL_SFLAGCLRR6 (*(RwReg8 *)0x4101E306UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 6 */
+#define REG_TAL_SFLAGCLRR7 (*(RwReg8 *)0x4101E307UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 7 */
+#define REG_TAL_SFLAGCLRR8 (*(RwReg8 *)0x4101E308UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 8 */
+#define REG_TAL_SFLAGCLRR9 (*(RwReg8 *)0x4101E309UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 9 */
+#define REG_TAL_SFLAGCLRR10 (*(RwReg8 *)0x4101E30AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 10 */
+#define REG_TAL_SFLAGCLRR11 (*(RwReg8 *)0x4101E30BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 11 */
+#define REG_TAL_SFLAGCLRR12 (*(RwReg8 *)0x4101E30CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 12 */
+#define REG_TAL_SFLAGCLRR13 (*(RwReg8 *)0x4101E30DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 13 */
+#define REG_TAL_SFLAGCLRR14 (*(RwReg8 *)0x4101E30EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 14 */
+#define REG_TAL_SFLAGCLRR15 (*(RwReg8 *)0x4101E30FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 15 */
+#define REG_TAL_SFLAGCLRR16 (*(RwReg8 *)0x4101E310UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 16 */
+#define REG_TAL_SFLAGCLRR17 (*(RwReg8 *)0x4101E311UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 17 */
+#define REG_TAL_SFLAGCLRR18 (*(RwReg8 *)0x4101E312UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 18 */
+#define REG_TAL_SFLAGCLRR19 (*(RwReg8 *)0x4101E313UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 19 */
+#define REG_TAL_SFLAGCLRR20 (*(RwReg8 *)0x4101E314UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 20 */
+#define REG_TAL_SFLAGCLRR21 (*(RwReg8 *)0x4101E315UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 21 */
+#define REG_TAL_SFLAGCLRR22 (*(RwReg8 *)0x4101E316UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 22 */
+#define REG_TAL_SFLAGCLRR23 (*(RwReg8 *)0x4101E317UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 23 */
+#define REG_TAL_SFLAGCLRR24 (*(RwReg8 *)0x4101E318UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 24 */
+#define REG_TAL_SFLAGCLRR25 (*(RwReg8 *)0x4101E319UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 25 */
+#define REG_TAL_SFLAGCLRR26 (*(RwReg8 *)0x4101E31AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 26 */
+#define REG_TAL_SFLAGCLRR27 (*(RwReg8 *)0x4101E31BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 27 */
+#define REG_TAL_SFLAGCLRR28 (*(RwReg8 *)0x4101E31CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 28 */
+#define REG_TAL_SFLAGCLRR29 (*(RwReg8 *)0x4101E31DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 29 */
+#define REG_TAL_SFLAGCLRR30 (*(RwReg8 *)0x4101E31EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 30 */
+#define REG_TAL_SFLAGCLRR31 (*(RwReg8 *)0x4101E31FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 31 */
+#define REG_TAL_SFLAGCLRR32 (*(RwReg8 *)0x4101E320UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 32 */
+#define REG_TAL_SFLAGCLRR33 (*(RwReg8 *)0x4101E321UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 33 */
+#define REG_TAL_SFLAGCLRR34 (*(RwReg8 *)0x4101E322UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 34 */
+#define REG_TAL_SFLAGCLRR35 (*(RwReg8 *)0x4101E323UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 35 */
+#define REG_TAL_SFLAGCLRR36 (*(RwReg8 *)0x4101E324UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 36 */
+#define REG_TAL_SFLAGCLRR37 (*(RwReg8 *)0x4101E325UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 37 */
+#define REG_TAL_SFLAGCLRR38 (*(RwReg8 *)0x4101E326UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 38 */
+#define REG_TAL_SFLAGCLRR39 (*(RwReg8 *)0x4101E327UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 39 */
+#define REG_TAL_SFLAGCLRR40 (*(RwReg8 *)0x4101E328UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 40 */
+#define REG_TAL_SFLAGCLRR41 (*(RwReg8 *)0x4101E329UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 41 */
+#define REG_TAL_SFLAGCLRR42 (*(RwReg8 *)0x4101E32AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 42 */
+#define REG_TAL_SFLAGCLRR43 (*(RwReg8 *)0x4101E32BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 43 */
+#define REG_TAL_SFLAGCLRR44 (*(RwReg8 *)0x4101E32CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 44 */
+#define REG_TAL_SFLAGCLRR45 (*(RwReg8 *)0x4101E32DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 45 */
+#define REG_TAL_SFLAGCLRR46 (*(RwReg8 *)0x4101E32EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 46 */
+#define REG_TAL_SFLAGCLRR47 (*(RwReg8 *)0x4101E32FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 47 */
+#define REG_TAL_SFLAGCLRR48 (*(RwReg8 *)0x4101E330UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 48 */
+#define REG_TAL_SFLAGCLRR49 (*(RwReg8 *)0x4101E331UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 49 */
+#define REG_TAL_SFLAGCLRR50 (*(RwReg8 *)0x4101E332UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 50 */
+#define REG_TAL_SFLAGCLRR51 (*(RwReg8 *)0x4101E333UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 51 */
+#define REG_TAL_SFLAGCLRR52 (*(RwReg8 *)0x4101E334UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 52 */
+#define REG_TAL_SFLAGCLRR53 (*(RwReg8 *)0x4101E335UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 53 */
+#define REG_TAL_SFLAGCLRR54 (*(RwReg8 *)0x4101E336UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 54 */
+#define REG_TAL_SFLAGCLRR55 (*(RwReg8 *)0x4101E337UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 55 */
+#define REG_TAL_SFLAGCLRR56 (*(RwReg8 *)0x4101E338UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 56 */
+#define REG_TAL_SFLAGCLRR57 (*(RwReg8 *)0x4101E339UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 57 */
+#define REG_TAL_SFLAGCLRR58 (*(RwReg8 *)0x4101E33AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 58 */
+#define REG_TAL_SFLAGCLRR59 (*(RwReg8 *)0x4101E33BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 59 */
+#define REG_TAL_SFLAGCLRR60 (*(RwReg8 *)0x4101E33CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 60 */
+#define REG_TAL_SFLAGCLRR61 (*(RwReg8 *)0x4101E33DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 61 */
+#define REG_TAL_SFLAGCLRR62 (*(RwReg8 *)0x4101E33EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 62 */
+#define REG_TAL_SFLAGCLRR63 (*(RwReg8 *)0x4101E33FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 63 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TAL peripheral ========== */
+#define TAL_CPU_NUM 2 // Number of CPUs
+#define TAL_CTI_NUM 4 // Number of Cross-Trigger Interfaces
+#define TAL_DMA_CH_NUM 32 // Number of DMAC Channels
+#define TAL_EV_CH_NUM 12 // Number of EVSYS Channels
+#define TAL_EXTINT_NUM 16 // Number of EIC External Interrrupts
+#define TAL_ID_IN_INTCPUSEL 1 // Use ID of IP instances in INTCPUSEL registers
+#define TAL_ID_NUM 130 // Number of IDs for IP instance numbers
+#define TAL_INT_GRP_NUM 5 // Number of 32-IRQ Groups
+#define TAL_INT_NUM 137 // Number of Interrupt Requests
+#define TAL_INT_NUM_BITS 8 // Number of bits for INT_NUM
+#define TAL_IPS_GRP_NUM 2 // Number of 32-IPS Groups
+#define TAL_IPS_NUM 64 // Number of Inter-Process Signals
+#define TAL_IRQMON_NUM 1 // Number of IRQ Monitors
+
+#endif /* _SAME54_TAL_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc0.h b/GPIO/ATSAME54/include/instance/tc0.h
new file mode 100644
index 0000000..08a0500
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc0.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC0
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC0_INSTANCE_
+#define _SAME54_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CTRLA (0x40003800) /**< \brief (TC0) Control A */
+#define REG_TC0_CTRLBCLR (0x40003804) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET (0x40003805) /**< \brief (TC0) Control B Set */
+#define REG_TC0_EVCTRL (0x40003806) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET (0x40003809) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS (0x4000380B) /**< \brief (TC0) Status */
+#define REG_TC0_WAVE (0x4000380C) /**< \brief (TC0) Waveform Generation Control */
+#define REG_TC0_DRVCTRL (0x4000380D) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL (0x4000380F) /**< \brief (TC0) Debug Control */
+#define REG_TC0_SYNCBUSY (0x40003810) /**< \brief (TC0) Synchronization Status */
+#define REG_TC0_COUNT16_COUNT (0x40003814) /**< \brief (TC0) COUNT16 Count */
+#define REG_TC0_COUNT16_CC0 (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
+#define REG_TC0_COUNT16_CC1 (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
+#define REG_TC0_COUNT16_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT16_CCBUF1 (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT32_COUNT (0x40003814) /**< \brief (TC0) COUNT32 Count */
+#define REG_TC0_COUNT32_CC0 (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
+#define REG_TC0_COUNT32_CC1 (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
+#define REG_TC0_COUNT32_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT32_CCBUF1 (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT8_COUNT (0x40003814) /**< \brief (TC0) COUNT8 Count */
+#define REG_TC0_COUNT8_PER (0x4000381B) /**< \brief (TC0) COUNT8 Period */
+#define REG_TC0_COUNT8_CC0 (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
+#define REG_TC0_COUNT8_CC1 (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
+#define REG_TC0_COUNT8_PERBUF (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */
+#define REG_TC0_COUNT8_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT8_CCBUF1 (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC0_CTRLA (*(RwReg *)0x40003800UL) /**< \brief (TC0) Control A */
+#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */
+#define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */
+#define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */
+#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */
+#define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL) /**< \brief (TC0) Synchronization Status */
+#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */
+#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
+#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
+#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */
+#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
+#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
+#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */
+#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */
+#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
+#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
+#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */
+#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC0 peripheral ========== */
+#define TC0_CC_NUM 2
+#define TC0_DMAC_ID_MC_0 45
+#define TC0_DMAC_ID_MC_1 46
+#define TC0_DMAC_ID_MC_LSB 45
+#define TC0_DMAC_ID_MC_MSB 46
+#define TC0_DMAC_ID_MC_SIZE 2
+#define TC0_DMAC_ID_OVF 44 // Indexes of DMA Overflow trigger
+#define TC0_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC0_GCLK_ID 9 // Index of Generic Clock
+#define TC0_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC0_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC0_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc1.h b/GPIO/ATSAME54/include/instance/tc1.h
new file mode 100644
index 0000000..7344222
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc1.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC1
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC1_INSTANCE_
+#define _SAME54_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CTRLA (0x40003C00) /**< \brief (TC1) Control A */
+#define REG_TC1_CTRLBCLR (0x40003C04) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET (0x40003C05) /**< \brief (TC1) Control B Set */
+#define REG_TC1_EVCTRL (0x40003C06) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR (0x40003C08) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG (0x40003C0A) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS (0x40003C0B) /**< \brief (TC1) Status */
+#define REG_TC1_WAVE (0x40003C0C) /**< \brief (TC1) Waveform Generation Control */
+#define REG_TC1_DRVCTRL (0x40003C0D) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL (0x40003C0F) /**< \brief (TC1) Debug Control */
+#define REG_TC1_SYNCBUSY (0x40003C10) /**< \brief (TC1) Synchronization Status */
+#define REG_TC1_COUNT16_COUNT (0x40003C14) /**< \brief (TC1) COUNT16 Count */
+#define REG_TC1_COUNT16_CC0 (0x40003C1C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
+#define REG_TC1_COUNT16_CC1 (0x40003C1E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
+#define REG_TC1_COUNT16_CCBUF0 (0x40003C30) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT16_CCBUF1 (0x40003C32) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT32_COUNT (0x40003C14) /**< \brief (TC1) COUNT32 Count */
+#define REG_TC1_COUNT32_CC0 (0x40003C1C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
+#define REG_TC1_COUNT32_CC1 (0x40003C20) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
+#define REG_TC1_COUNT32_CCBUF0 (0x40003C30) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT32_CCBUF1 (0x40003C34) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT8_COUNT (0x40003C14) /**< \brief (TC1) COUNT8 Count */
+#define REG_TC1_COUNT8_PER (0x40003C1B) /**< \brief (TC1) COUNT8 Period */
+#define REG_TC1_COUNT8_CC0 (0x40003C1C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
+#define REG_TC1_COUNT8_CC1 (0x40003C1D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
+#define REG_TC1_COUNT8_PERBUF (0x40003C2F) /**< \brief (TC1) COUNT8 Period Buffer */
+#define REG_TC1_COUNT8_CCBUF0 (0x40003C30) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT8_CCBUF1 (0x40003C31) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC1_CTRLA (*(RwReg *)0x40003C00UL) /**< \brief (TC1) Control A */
+#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x40003C04UL) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET (*(RwReg8 *)0x40003C05UL) /**< \brief (TC1) Control B Set */
+#define REG_TC1_EVCTRL (*(RwReg16*)0x40003C06UL) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR (*(RwReg8 *)0x40003C08UL) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG (*(RwReg8 *)0x40003C0AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS (*(RwReg8 *)0x40003C0BUL) /**< \brief (TC1) Status */
+#define REG_TC1_WAVE (*(RwReg8 *)0x40003C0CUL) /**< \brief (TC1) Waveform Generation Control */
+#define REG_TC1_DRVCTRL (*(RwReg8 *)0x40003C0DUL) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL (*(RwReg8 *)0x40003C0FUL) /**< \brief (TC1) Debug Control */
+#define REG_TC1_SYNCBUSY (*(RoReg *)0x40003C10UL) /**< \brief (TC1) Synchronization Status */
+#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x40003C14UL) /**< \brief (TC1) COUNT16 Count */
+#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x40003C1CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
+#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x40003C1EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
+#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x40003C30UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x40003C32UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x40003C14UL) /**< \brief (TC1) COUNT32 Count */
+#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x40003C1CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
+#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x40003C20UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
+#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x40003C30UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x40003C34UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x40003C14UL) /**< \brief (TC1) COUNT8 Count */
+#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x40003C1BUL) /**< \brief (TC1) COUNT8 Period */
+#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x40003C1CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
+#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x40003C1DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
+#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x40003C2FUL) /**< \brief (TC1) COUNT8 Period Buffer */
+#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x40003C30UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x40003C31UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC1 peripheral ========== */
+#define TC1_CC_NUM 2
+#define TC1_DMAC_ID_MC_0 48
+#define TC1_DMAC_ID_MC_1 49
+#define TC1_DMAC_ID_MC_LSB 48
+#define TC1_DMAC_ID_MC_MSB 49
+#define TC1_DMAC_ID_MC_SIZE 2
+#define TC1_DMAC_ID_OVF 47 // Indexes of DMA Overflow trigger
+#define TC1_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC1_GCLK_ID 9 // Index of Generic Clock
+#define TC1_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC1_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC1_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc2.h b/GPIO/ATSAME54/include/instance/tc2.h
new file mode 100644
index 0000000..6026918
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc2.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC2
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC2_INSTANCE_
+#define _SAME54_TC2_INSTANCE_
+
+/* ========== Register definition for TC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC2_CTRLA (0x4101A000) /**< \brief (TC2) Control A */
+#define REG_TC2_CTRLBCLR (0x4101A004) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET (0x4101A005) /**< \brief (TC2) Control B Set */
+#define REG_TC2_EVCTRL (0x4101A006) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR (0x4101A008) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG (0x4101A00A) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS (0x4101A00B) /**< \brief (TC2) Status */
+#define REG_TC2_WAVE (0x4101A00C) /**< \brief (TC2) Waveform Generation Control */
+#define REG_TC2_DRVCTRL (0x4101A00D) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL (0x4101A00F) /**< \brief (TC2) Debug Control */
+#define REG_TC2_SYNCBUSY (0x4101A010) /**< \brief (TC2) Synchronization Status */
+#define REG_TC2_COUNT16_COUNT (0x4101A014) /**< \brief (TC2) COUNT16 Count */
+#define REG_TC2_COUNT16_CC0 (0x4101A01C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
+#define REG_TC2_COUNT16_CC1 (0x4101A01E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
+#define REG_TC2_COUNT16_CCBUF0 (0x4101A030) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT16_CCBUF1 (0x4101A032) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT32_COUNT (0x4101A014) /**< \brief (TC2) COUNT32 Count */
+#define REG_TC2_COUNT32_CC0 (0x4101A01C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
+#define REG_TC2_COUNT32_CC1 (0x4101A020) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
+#define REG_TC2_COUNT32_CCBUF0 (0x4101A030) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT32_CCBUF1 (0x4101A034) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT8_COUNT (0x4101A014) /**< \brief (TC2) COUNT8 Count */
+#define REG_TC2_COUNT8_PER (0x4101A01B) /**< \brief (TC2) COUNT8 Period */
+#define REG_TC2_COUNT8_CC0 (0x4101A01C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
+#define REG_TC2_COUNT8_CC1 (0x4101A01D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
+#define REG_TC2_COUNT8_PERBUF (0x4101A02F) /**< \brief (TC2) COUNT8 Period Buffer */
+#define REG_TC2_COUNT8_CCBUF0 (0x4101A030) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT8_CCBUF1 (0x4101A031) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC2_CTRLA (*(RwReg *)0x4101A000UL) /**< \brief (TC2) Control A */
+#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x4101A004UL) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET (*(RwReg8 *)0x4101A005UL) /**< \brief (TC2) Control B Set */
+#define REG_TC2_EVCTRL (*(RwReg16*)0x4101A006UL) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR (*(RwReg8 *)0x4101A008UL) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG (*(RwReg8 *)0x4101A00AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS (*(RwReg8 *)0x4101A00BUL) /**< \brief (TC2) Status */
+#define REG_TC2_WAVE (*(RwReg8 *)0x4101A00CUL) /**< \brief (TC2) Waveform Generation Control */
+#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4101A00DUL) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4101A00FUL) /**< \brief (TC2) Debug Control */
+#define REG_TC2_SYNCBUSY (*(RoReg *)0x4101A010UL) /**< \brief (TC2) Synchronization Status */
+#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x4101A014UL) /**< \brief (TC2) COUNT16 Count */
+#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4101A01CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
+#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4101A01EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
+#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x4101A030UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x4101A032UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x4101A014UL) /**< \brief (TC2) COUNT32 Count */
+#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4101A01CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
+#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x4101A020UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
+#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x4101A030UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x4101A034UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x4101A014UL) /**< \brief (TC2) COUNT8 Count */
+#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4101A01BUL) /**< \brief (TC2) COUNT8 Period */
+#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4101A01CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
+#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4101A01DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
+#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4101A02FUL) /**< \brief (TC2) COUNT8 Period Buffer */
+#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x4101A030UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x4101A031UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC2 peripheral ========== */
+#define TC2_CC_NUM 2
+#define TC2_DMAC_ID_MC_0 51
+#define TC2_DMAC_ID_MC_1 52
+#define TC2_DMAC_ID_MC_LSB 51
+#define TC2_DMAC_ID_MC_MSB 52
+#define TC2_DMAC_ID_MC_SIZE 2
+#define TC2_DMAC_ID_OVF 50 // Indexes of DMA Overflow trigger
+#define TC2_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC2_GCLK_ID 26 // Index of Generic Clock
+#define TC2_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC2_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC2_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc3.h b/GPIO/ATSAME54/include/instance/tc3.h
new file mode 100644
index 0000000..507e7f4
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc3.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC3_INSTANCE_
+#define _SAME54_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA (0x4101C000) /**< \brief (TC3) Control A */
+#define REG_TC3_CTRLBCLR (0x4101C004) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (0x4101C005) /**< \brief (TC3) Control B Set */
+#define REG_TC3_EVCTRL (0x4101C006) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (0x4101C008) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (0x4101C009) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (0x4101C00A) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (0x4101C00B) /**< \brief (TC3) Status */
+#define REG_TC3_WAVE (0x4101C00C) /**< \brief (TC3) Waveform Generation Control */
+#define REG_TC3_DRVCTRL (0x4101C00D) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (0x4101C00F) /**< \brief (TC3) Debug Control */
+#define REG_TC3_SYNCBUSY (0x4101C010) /**< \brief (TC3) Synchronization Status */
+#define REG_TC3_COUNT16_COUNT (0x4101C014) /**< \brief (TC3) COUNT16 Count */
+#define REG_TC3_COUNT16_CC0 (0x4101C01C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
+#define REG_TC3_COUNT16_CC1 (0x4101C01E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
+#define REG_TC3_COUNT16_CCBUF0 (0x4101C030) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT16_CCBUF1 (0x4101C032) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT32_COUNT (0x4101C014) /**< \brief (TC3) COUNT32 Count */
+#define REG_TC3_COUNT32_CC0 (0x4101C01C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
+#define REG_TC3_COUNT32_CC1 (0x4101C020) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
+#define REG_TC3_COUNT32_CCBUF0 (0x4101C030) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT32_CCBUF1 (0x4101C034) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT8_COUNT (0x4101C014) /**< \brief (TC3) COUNT8 Count */
+#define REG_TC3_COUNT8_PER (0x4101C01B) /**< \brief (TC3) COUNT8 Period */
+#define REG_TC3_COUNT8_CC0 (0x4101C01C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
+#define REG_TC3_COUNT8_CC1 (0x4101C01D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
+#define REG_TC3_COUNT8_PERBUF (0x4101C02F) /**< \brief (TC3) COUNT8 Period Buffer */
+#define REG_TC3_COUNT8_CCBUF0 (0x4101C030) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT8_CCBUF1 (0x4101C031) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC3_CTRLA (*(RwReg *)0x4101C000UL) /**< \brief (TC3) Control A */
+#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x4101C004UL) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (*(RwReg8 *)0x4101C005UL) /**< \brief (TC3) Control B Set */
+#define REG_TC3_EVCTRL (*(RwReg16*)0x4101C006UL) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (*(RwReg8 *)0x4101C008UL) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (*(RwReg8 *)0x4101C009UL) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (*(RwReg8 *)0x4101C00AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (*(RwReg8 *)0x4101C00BUL) /**< \brief (TC3) Status */
+#define REG_TC3_WAVE (*(RwReg8 *)0x4101C00CUL) /**< \brief (TC3) Waveform Generation Control */
+#define REG_TC3_DRVCTRL (*(RwReg8 *)0x4101C00DUL) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (*(RwReg8 *)0x4101C00FUL) /**< \brief (TC3) Debug Control */
+#define REG_TC3_SYNCBUSY (*(RoReg *)0x4101C010UL) /**< \brief (TC3) Synchronization Status */
+#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x4101C014UL) /**< \brief (TC3) COUNT16 Count */
+#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x4101C01CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
+#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x4101C01EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
+#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x4101C030UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x4101C032UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x4101C014UL) /**< \brief (TC3) COUNT32 Count */
+#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x4101C01CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
+#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x4101C020UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
+#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x4101C030UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x4101C034UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x4101C014UL) /**< \brief (TC3) COUNT8 Count */
+#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x4101C01BUL) /**< \brief (TC3) COUNT8 Period */
+#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x4101C01CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
+#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x4101C01DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
+#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x4101C02FUL) /**< \brief (TC3) COUNT8 Period Buffer */
+#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x4101C030UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x4101C031UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC_NUM 2
+#define TC3_DMAC_ID_MC_0 54
+#define TC3_DMAC_ID_MC_1 55
+#define TC3_DMAC_ID_MC_LSB 54
+#define TC3_DMAC_ID_MC_MSB 55
+#define TC3_DMAC_ID_MC_SIZE 2
+#define TC3_DMAC_ID_OVF 53 // Indexes of DMA Overflow trigger
+#define TC3_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC3_GCLK_ID 26 // Index of Generic Clock
+#define TC3_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC3_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC3_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc4.h b/GPIO/ATSAME54/include/instance/tc4.h
new file mode 100644
index 0000000..70c6eb5
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc4.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC4_INSTANCE_
+#define _SAME54_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA (0x42001400) /**< \brief (TC4) Control A */
+#define REG_TC4_CTRLBCLR (0x42001404) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET (0x42001405) /**< \brief (TC4) Control B Set */
+#define REG_TC4_EVCTRL (0x42001406) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR (0x42001408) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET (0x42001409) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG (0x4200140A) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS (0x4200140B) /**< \brief (TC4) Status */
+#define REG_TC4_WAVE (0x4200140C) /**< \brief (TC4) Waveform Generation Control */
+#define REG_TC4_DRVCTRL (0x4200140D) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL (0x4200140F) /**< \brief (TC4) Debug Control */
+#define REG_TC4_SYNCBUSY (0x42001410) /**< \brief (TC4) Synchronization Status */
+#define REG_TC4_COUNT16_COUNT (0x42001414) /**< \brief (TC4) COUNT16 Count */
+#define REG_TC4_COUNT16_CC0 (0x4200141C) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
+#define REG_TC4_COUNT16_CC1 (0x4200141E) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
+#define REG_TC4_COUNT16_CCBUF0 (0x42001430) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT16_CCBUF1 (0x42001432) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT32_COUNT (0x42001414) /**< \brief (TC4) COUNT32 Count */
+#define REG_TC4_COUNT32_CC0 (0x4200141C) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
+#define REG_TC4_COUNT32_CC1 (0x42001420) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
+#define REG_TC4_COUNT32_CCBUF0 (0x42001430) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT32_CCBUF1 (0x42001434) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT8_COUNT (0x42001414) /**< \brief (TC4) COUNT8 Count */
+#define REG_TC4_COUNT8_PER (0x4200141B) /**< \brief (TC4) COUNT8 Period */
+#define REG_TC4_COUNT8_CC0 (0x4200141C) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
+#define REG_TC4_COUNT8_CC1 (0x4200141D) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
+#define REG_TC4_COUNT8_PERBUF (0x4200142F) /**< \brief (TC4) COUNT8 Period Buffer */
+#define REG_TC4_COUNT8_CCBUF0 (0x42001430) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT8_CCBUF1 (0x42001431) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC4_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (TC4) Control A */
+#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42001404UL) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42001405UL) /**< \brief (TC4) Control B Set */
+#define REG_TC4_EVCTRL (*(RwReg16*)0x42001406UL) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR (*(RwReg8 *)0x42001408UL) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200140AUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS (*(RwReg8 *)0x4200140BUL) /**< \brief (TC4) Status */
+#define REG_TC4_WAVE (*(RwReg8 *)0x4200140CUL) /**< \brief (TC4) Waveform Generation Control */
+#define REG_TC4_DRVCTRL (*(RwReg8 *)0x4200140DUL) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL (*(RwReg8 *)0x4200140FUL) /**< \brief (TC4) Debug Control */
+#define REG_TC4_SYNCBUSY (*(RoReg *)0x42001410UL) /**< \brief (TC4) Synchronization Status */
+#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42001414UL) /**< \brief (TC4) COUNT16 Count */
+#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4200141CUL) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
+#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200141EUL) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
+#define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x42001430UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x42001432UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42001414UL) /**< \brief (TC4) COUNT32 Count */
+#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4200141CUL) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
+#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x42001420UL) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
+#define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x42001430UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x42001434UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42001414UL) /**< \brief (TC4) COUNT8 Count */
+#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4200141BUL) /**< \brief (TC4) COUNT8 Period */
+#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4200141CUL) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
+#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4200141DUL) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
+#define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4200142FUL) /**< \brief (TC4) COUNT8 Period Buffer */
+#define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x42001430UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x42001431UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC_NUM 2
+#define TC4_DMAC_ID_MC_0 57
+#define TC4_DMAC_ID_MC_1 58
+#define TC4_DMAC_ID_MC_LSB 57
+#define TC4_DMAC_ID_MC_MSB 58
+#define TC4_DMAC_ID_MC_SIZE 2
+#define TC4_DMAC_ID_OVF 56 // Indexes of DMA Overflow trigger
+#define TC4_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC4_GCLK_ID 30 // Index of Generic Clock
+#define TC4_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC4_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC4_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc5.h b/GPIO/ATSAME54/include/instance/tc5.h
new file mode 100644
index 0000000..d6dbd7f
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc5.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC5_INSTANCE_
+#define _SAME54_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA (0x42001800) /**< \brief (TC5) Control A */
+#define REG_TC5_CTRLBCLR (0x42001804) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET (0x42001805) /**< \brief (TC5) Control B Set */
+#define REG_TC5_EVCTRL (0x42001806) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR (0x42001808) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET (0x42001809) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG (0x4200180A) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS (0x4200180B) /**< \brief (TC5) Status */
+#define REG_TC5_WAVE (0x4200180C) /**< \brief (TC5) Waveform Generation Control */
+#define REG_TC5_DRVCTRL (0x4200180D) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL (0x4200180F) /**< \brief (TC5) Debug Control */
+#define REG_TC5_SYNCBUSY (0x42001810) /**< \brief (TC5) Synchronization Status */
+#define REG_TC5_COUNT16_COUNT (0x42001814) /**< \brief (TC5) COUNT16 Count */
+#define REG_TC5_COUNT16_CC0 (0x4200181C) /**< \brief (TC5) COUNT16 Compare and Capture 0 */
+#define REG_TC5_COUNT16_CC1 (0x4200181E) /**< \brief (TC5) COUNT16 Compare and Capture 1 */
+#define REG_TC5_COUNT16_CCBUF0 (0x42001830) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT16_CCBUF1 (0x42001832) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT32_COUNT (0x42001814) /**< \brief (TC5) COUNT32 Count */
+#define REG_TC5_COUNT32_CC0 (0x4200181C) /**< \brief (TC5) COUNT32 Compare and Capture 0 */
+#define REG_TC5_COUNT32_CC1 (0x42001820) /**< \brief (TC5) COUNT32 Compare and Capture 1 */
+#define REG_TC5_COUNT32_CCBUF0 (0x42001830) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT32_CCBUF1 (0x42001834) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT8_COUNT (0x42001814) /**< \brief (TC5) COUNT8 Count */
+#define REG_TC5_COUNT8_PER (0x4200181B) /**< \brief (TC5) COUNT8 Period */
+#define REG_TC5_COUNT8_CC0 (0x4200181C) /**< \brief (TC5) COUNT8 Compare and Capture 0 */
+#define REG_TC5_COUNT8_CC1 (0x4200181D) /**< \brief (TC5) COUNT8 Compare and Capture 1 */
+#define REG_TC5_COUNT8_PERBUF (0x4200182F) /**< \brief (TC5) COUNT8 Period Buffer */
+#define REG_TC5_COUNT8_CCBUF0 (0x42001830) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT8_CCBUF1 (0x42001831) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC5_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (TC5) Control A */
+#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42001804UL) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42001805UL) /**< \brief (TC5) Control B Set */
+#define REG_TC5_EVCTRL (*(RwReg16*)0x42001806UL) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR (*(RwReg8 *)0x42001808UL) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET (*(RwReg8 *)0x42001809UL) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200180AUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS (*(RwReg8 *)0x4200180BUL) /**< \brief (TC5) Status */
+#define REG_TC5_WAVE (*(RwReg8 *)0x4200180CUL) /**< \brief (TC5) Waveform Generation Control */
+#define REG_TC5_DRVCTRL (*(RwReg8 *)0x4200180DUL) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL (*(RwReg8 *)0x4200180FUL) /**< \brief (TC5) Debug Control */
+#define REG_TC5_SYNCBUSY (*(RoReg *)0x42001810UL) /**< \brief (TC5) Synchronization Status */
+#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42001814UL) /**< \brief (TC5) COUNT16 Count */
+#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x4200181CUL) /**< \brief (TC5) COUNT16 Compare and Capture 0 */
+#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200181EUL) /**< \brief (TC5) COUNT16 Compare and Capture 1 */
+#define REG_TC5_COUNT16_CCBUF0 (*(RwReg16*)0x42001830UL) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT16_CCBUF1 (*(RwReg16*)0x42001832UL) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42001814UL) /**< \brief (TC5) COUNT32 Count */
+#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x4200181CUL) /**< \brief (TC5) COUNT32 Compare and Capture 0 */
+#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x42001820UL) /**< \brief (TC5) COUNT32 Compare and Capture 1 */
+#define REG_TC5_COUNT32_CCBUF0 (*(RwReg *)0x42001830UL) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT32_CCBUF1 (*(RwReg *)0x42001834UL) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42001814UL) /**< \brief (TC5) COUNT8 Count */
+#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x4200181BUL) /**< \brief (TC5) COUNT8 Period */
+#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x4200181CUL) /**< \brief (TC5) COUNT8 Compare and Capture 0 */
+#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x4200181DUL) /**< \brief (TC5) COUNT8 Compare and Capture 1 */
+#define REG_TC5_COUNT8_PERBUF (*(RwReg8 *)0x4200182FUL) /**< \brief (TC5) COUNT8 Period Buffer */
+#define REG_TC5_COUNT8_CCBUF0 (*(RwReg8 *)0x42001830UL) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT8_CCBUF1 (*(RwReg8 *)0x42001831UL) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC_NUM 2
+#define TC5_DMAC_ID_MC_0 60
+#define TC5_DMAC_ID_MC_1 61
+#define TC5_DMAC_ID_MC_LSB 60
+#define TC5_DMAC_ID_MC_MSB 61
+#define TC5_DMAC_ID_MC_SIZE 2
+#define TC5_DMAC_ID_OVF 59 // Indexes of DMA Overflow trigger
+#define TC5_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC5_GCLK_ID 30 // Index of Generic Clock
+#define TC5_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC5_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC5_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc6.h b/GPIO/ATSAME54/include/instance/tc6.h
new file mode 100644
index 0000000..13f5c70
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc6.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC6_INSTANCE_
+#define _SAME54_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA (0x43001400) /**< \brief (TC6) Control A */
+#define REG_TC6_CTRLBCLR (0x43001404) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET (0x43001405) /**< \brief (TC6) Control B Set */
+#define REG_TC6_EVCTRL (0x43001406) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR (0x43001408) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET (0x43001409) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG (0x4300140A) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS (0x4300140B) /**< \brief (TC6) Status */
+#define REG_TC6_WAVE (0x4300140C) /**< \brief (TC6) Waveform Generation Control */
+#define REG_TC6_DRVCTRL (0x4300140D) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL (0x4300140F) /**< \brief (TC6) Debug Control */
+#define REG_TC6_SYNCBUSY (0x43001410) /**< \brief (TC6) Synchronization Status */
+#define REG_TC6_COUNT16_COUNT (0x43001414) /**< \brief (TC6) COUNT16 Count */
+#define REG_TC6_COUNT16_CC0 (0x4300141C) /**< \brief (TC6) COUNT16 Compare and Capture 0 */
+#define REG_TC6_COUNT16_CC1 (0x4300141E) /**< \brief (TC6) COUNT16 Compare and Capture 1 */
+#define REG_TC6_COUNT16_CCBUF0 (0x43001430) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT16_CCBUF1 (0x43001432) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT32_COUNT (0x43001414) /**< \brief (TC6) COUNT32 Count */
+#define REG_TC6_COUNT32_CC0 (0x4300141C) /**< \brief (TC6) COUNT32 Compare and Capture 0 */
+#define REG_TC6_COUNT32_CC1 (0x43001420) /**< \brief (TC6) COUNT32 Compare and Capture 1 */
+#define REG_TC6_COUNT32_CCBUF0 (0x43001430) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT32_CCBUF1 (0x43001434) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT8_COUNT (0x43001414) /**< \brief (TC6) COUNT8 Count */
+#define REG_TC6_COUNT8_PER (0x4300141B) /**< \brief (TC6) COUNT8 Period */
+#define REG_TC6_COUNT8_CC0 (0x4300141C) /**< \brief (TC6) COUNT8 Compare and Capture 0 */
+#define REG_TC6_COUNT8_CC1 (0x4300141D) /**< \brief (TC6) COUNT8 Compare and Capture 1 */
+#define REG_TC6_COUNT8_PERBUF (0x4300142F) /**< \brief (TC6) COUNT8 Period Buffer */
+#define REG_TC6_COUNT8_CCBUF0 (0x43001430) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT8_CCBUF1 (0x43001431) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC6_CTRLA (*(RwReg *)0x43001400UL) /**< \brief (TC6) Control A */
+#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x43001404UL) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET (*(RwReg8 *)0x43001405UL) /**< \brief (TC6) Control B Set */
+#define REG_TC6_EVCTRL (*(RwReg16*)0x43001406UL) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR (*(RwReg8 *)0x43001408UL) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET (*(RwReg8 *)0x43001409UL) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG (*(RwReg8 *)0x4300140AUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS (*(RwReg8 *)0x4300140BUL) /**< \brief (TC6) Status */
+#define REG_TC6_WAVE (*(RwReg8 *)0x4300140CUL) /**< \brief (TC6) Waveform Generation Control */
+#define REG_TC6_DRVCTRL (*(RwReg8 *)0x4300140DUL) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL (*(RwReg8 *)0x4300140FUL) /**< \brief (TC6) Debug Control */
+#define REG_TC6_SYNCBUSY (*(RoReg *)0x43001410UL) /**< \brief (TC6) Synchronization Status */
+#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x43001414UL) /**< \brief (TC6) COUNT16 Count */
+#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x4300141CUL) /**< \brief (TC6) COUNT16 Compare and Capture 0 */
+#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4300141EUL) /**< \brief (TC6) COUNT16 Compare and Capture 1 */
+#define REG_TC6_COUNT16_CCBUF0 (*(RwReg16*)0x43001430UL) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT16_CCBUF1 (*(RwReg16*)0x43001432UL) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x43001414UL) /**< \brief (TC6) COUNT32 Count */
+#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x4300141CUL) /**< \brief (TC6) COUNT32 Compare and Capture 0 */
+#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x43001420UL) /**< \brief (TC6) COUNT32 Compare and Capture 1 */
+#define REG_TC6_COUNT32_CCBUF0 (*(RwReg *)0x43001430UL) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT32_CCBUF1 (*(RwReg *)0x43001434UL) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x43001414UL) /**< \brief (TC6) COUNT8 Count */
+#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x4300141BUL) /**< \brief (TC6) COUNT8 Period */
+#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x4300141CUL) /**< \brief (TC6) COUNT8 Compare and Capture 0 */
+#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x4300141DUL) /**< \brief (TC6) COUNT8 Compare and Capture 1 */
+#define REG_TC6_COUNT8_PERBUF (*(RwReg8 *)0x4300142FUL) /**< \brief (TC6) COUNT8 Period Buffer */
+#define REG_TC6_COUNT8_CCBUF0 (*(RwReg8 *)0x43001430UL) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT8_CCBUF1 (*(RwReg8 *)0x43001431UL) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC_NUM 2
+#define TC6_DMAC_ID_MC_0 63
+#define TC6_DMAC_ID_MC_1 64
+#define TC6_DMAC_ID_MC_LSB 63
+#define TC6_DMAC_ID_MC_MSB 64
+#define TC6_DMAC_ID_MC_SIZE 2
+#define TC6_DMAC_ID_OVF 62 // Indexes of DMA Overflow trigger
+#define TC6_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC6_GCLK_ID 39 // Index of Generic Clock
+#define TC6_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC6_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC6_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tc7.h b/GPIO/ATSAME54/include/instance/tc7.h
new file mode 100644
index 0000000..fce0086
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tc7.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TC7_INSTANCE_
+#define _SAME54_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA (0x43001800) /**< \brief (TC7) Control A */
+#define REG_TC7_CTRLBCLR (0x43001804) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET (0x43001805) /**< \brief (TC7) Control B Set */
+#define REG_TC7_EVCTRL (0x43001806) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR (0x43001808) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET (0x43001809) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG (0x4300180A) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS (0x4300180B) /**< \brief (TC7) Status */
+#define REG_TC7_WAVE (0x4300180C) /**< \brief (TC7) Waveform Generation Control */
+#define REG_TC7_DRVCTRL (0x4300180D) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL (0x4300180F) /**< \brief (TC7) Debug Control */
+#define REG_TC7_SYNCBUSY (0x43001810) /**< \brief (TC7) Synchronization Status */
+#define REG_TC7_COUNT16_COUNT (0x43001814) /**< \brief (TC7) COUNT16 Count */
+#define REG_TC7_COUNT16_CC0 (0x4300181C) /**< \brief (TC7) COUNT16 Compare and Capture 0 */
+#define REG_TC7_COUNT16_CC1 (0x4300181E) /**< \brief (TC7) COUNT16 Compare and Capture 1 */
+#define REG_TC7_COUNT16_CCBUF0 (0x43001830) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT16_CCBUF1 (0x43001832) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT32_COUNT (0x43001814) /**< \brief (TC7) COUNT32 Count */
+#define REG_TC7_COUNT32_CC0 (0x4300181C) /**< \brief (TC7) COUNT32 Compare and Capture 0 */
+#define REG_TC7_COUNT32_CC1 (0x43001820) /**< \brief (TC7) COUNT32 Compare and Capture 1 */
+#define REG_TC7_COUNT32_CCBUF0 (0x43001830) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT32_CCBUF1 (0x43001834) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT8_COUNT (0x43001814) /**< \brief (TC7) COUNT8 Count */
+#define REG_TC7_COUNT8_PER (0x4300181B) /**< \brief (TC7) COUNT8 Period */
+#define REG_TC7_COUNT8_CC0 (0x4300181C) /**< \brief (TC7) COUNT8 Compare and Capture 0 */
+#define REG_TC7_COUNT8_CC1 (0x4300181D) /**< \brief (TC7) COUNT8 Compare and Capture 1 */
+#define REG_TC7_COUNT8_PERBUF (0x4300182F) /**< \brief (TC7) COUNT8 Period Buffer */
+#define REG_TC7_COUNT8_CCBUF0 (0x43001830) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT8_CCBUF1 (0x43001831) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC7_CTRLA (*(RwReg *)0x43001800UL) /**< \brief (TC7) Control A */
+#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x43001804UL) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET (*(RwReg8 *)0x43001805UL) /**< \brief (TC7) Control B Set */
+#define REG_TC7_EVCTRL (*(RwReg16*)0x43001806UL) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR (*(RwReg8 *)0x43001808UL) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET (*(RwReg8 *)0x43001809UL) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG (*(RwReg8 *)0x4300180AUL) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS (*(RwReg8 *)0x4300180BUL) /**< \brief (TC7) Status */
+#define REG_TC7_WAVE (*(RwReg8 *)0x4300180CUL) /**< \brief (TC7) Waveform Generation Control */
+#define REG_TC7_DRVCTRL (*(RwReg8 *)0x4300180DUL) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL (*(RwReg8 *)0x4300180FUL) /**< \brief (TC7) Debug Control */
+#define REG_TC7_SYNCBUSY (*(RoReg *)0x43001810UL) /**< \brief (TC7) Synchronization Status */
+#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x43001814UL) /**< \brief (TC7) COUNT16 Count */
+#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x4300181CUL) /**< \brief (TC7) COUNT16 Compare and Capture 0 */
+#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x4300181EUL) /**< \brief (TC7) COUNT16 Compare and Capture 1 */
+#define REG_TC7_COUNT16_CCBUF0 (*(RwReg16*)0x43001830UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT16_CCBUF1 (*(RwReg16*)0x43001832UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x43001814UL) /**< \brief (TC7) COUNT32 Count */
+#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x4300181CUL) /**< \brief (TC7) COUNT32 Compare and Capture 0 */
+#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x43001820UL) /**< \brief (TC7) COUNT32 Compare and Capture 1 */
+#define REG_TC7_COUNT32_CCBUF0 (*(RwReg *)0x43001830UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT32_CCBUF1 (*(RwReg *)0x43001834UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x43001814UL) /**< \brief (TC7) COUNT8 Count */
+#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x4300181BUL) /**< \brief (TC7) COUNT8 Period */
+#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x4300181CUL) /**< \brief (TC7) COUNT8 Compare and Capture 0 */
+#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x4300181DUL) /**< \brief (TC7) COUNT8 Compare and Capture 1 */
+#define REG_TC7_COUNT8_PERBUF (*(RwReg8 *)0x4300182FUL) /**< \brief (TC7) COUNT8 Period Buffer */
+#define REG_TC7_COUNT8_CCBUF0 (*(RwReg8 *)0x43001830UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT8_CCBUF1 (*(RwReg8 *)0x43001831UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC_NUM 2
+#define TC7_DMAC_ID_MC_0 66
+#define TC7_DMAC_ID_MC_1 67
+#define TC7_DMAC_ID_MC_LSB 66
+#define TC7_DMAC_ID_MC_MSB 67
+#define TC7_DMAC_ID_MC_SIZE 2
+#define TC7_DMAC_ID_OVF 65 // Indexes of DMA Overflow trigger
+#define TC7_EXT 0 // Coding of implemented extended features (keep 0 value)
+#define TC7_GCLK_ID 39 // Index of Generic Clock
+#define TC7_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC7_OW_NUM 2 // Number of Output Waveforms
+
+#endif /* _SAME54_TC7_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tcc0.h b/GPIO/ATSAME54/include/instance/tcc0.h
new file mode 100644
index 0000000..17c20ad
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tcc0.h
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC0_INSTANCE_
+#define _SAME54_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA (0x41016000) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (0x41016004) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (0x41016005) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (0x41016008) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (0x4101600C) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB (0x41016010) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL (0x41016014) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (0x41016018) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL (0x4101601E) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (0x41016020) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (0x41016024) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (0x41016028) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (0x4101602C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (0x41016030) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (0x41016034) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (0x41016038) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (0x4101603C) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (0x41016040) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (0x41016044) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (0x41016048) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (0x4101604C) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (0x41016050) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_CC4 (0x41016054) /**< \brief (TCC0) Compare and Capture 4 */
+#define REG_TCC0_CC5 (0x41016058) /**< \brief (TCC0) Compare and Capture 5 */
+#define REG_TCC0_PATTBUF (0x41016064) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_PERBUF (0x4101606C) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCBUF0 (0x41016070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCBUF1 (0x41016074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCBUF2 (0x41016078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCBUF3 (0x4101607C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#define REG_TCC0_CCBUF4 (0x41016080) /**< \brief (TCC0) Compare and Capture Buffer 4 */
+#define REG_TCC0_CCBUF5 (0x41016084) /**< \brief (TCC0) Compare and Capture Buffer 5 */
+#else
+#define REG_TCC0_CTRLA (*(RwReg *)0x41016000UL) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x41016004UL) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x41016005UL) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (*(RoReg *)0x41016008UL) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (*(RwReg *)0x4101600CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB (*(RwReg *)0x41016010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL (*(RwReg *)0x41016014UL) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (*(RwReg *)0x41016018UL) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4101601EUL) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (*(RwReg *)0x41016020UL) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (*(RwReg *)0x41016024UL) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (*(RwReg *)0x41016028UL) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (*(RwReg *)0x4101602CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (*(RwReg *)0x41016030UL) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (*(RwReg *)0x41016034UL) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (*(RwReg16*)0x41016038UL) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (*(RwReg *)0x4101603CUL) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (*(RwReg *)0x41016040UL) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (*(RwReg *)0x41016044UL) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (*(RwReg *)0x41016048UL) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (*(RwReg *)0x4101604CUL) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (*(RwReg *)0x41016050UL) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_CC4 (*(RwReg *)0x41016054UL) /**< \brief (TCC0) Compare and Capture 4 */
+#define REG_TCC0_CC5 (*(RwReg *)0x41016058UL) /**< \brief (TCC0) Compare and Capture 5 */
+#define REG_TCC0_PATTBUF (*(RwReg16*)0x41016064UL) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_PERBUF (*(RwReg *)0x4101606CUL) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCBUF0 (*(RwReg *)0x41016070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCBUF1 (*(RwReg *)0x41016074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCBUF2 (*(RwReg *)0x41016078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCBUF3 (*(RwReg *)0x4101607CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#define REG_TCC0_CCBUF4 (*(RwReg *)0x41016080UL) /**< \brief (TCC0) Compare and Capture Buffer 4 */
+#define REG_TCC0_CCBUF5 (*(RwReg *)0x41016084UL) /**< \brief (TCC0) Compare and Capture Buffer 5 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM 6 // Number of Compare/Capture units
+#define TCC0_DITHERING 1 // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0 23
+#define TCC0_DMAC_ID_MC_1 24
+#define TCC0_DMAC_ID_MC_2 25
+#define TCC0_DMAC_ID_MC_3 26
+#define TCC0_DMAC_ID_MC_4 27
+#define TCC0_DMAC_ID_MC_5 28
+#define TCC0_DMAC_ID_MC_LSB 23
+#define TCC0_DMAC_ID_MC_MSB 28
+#define TCC0_DMAC_ID_MC_SIZE 6
+#define TCC0_DMAC_ID_OVF 22 // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
+#define TCC0_EXT 31 // Coding of implemented extended features
+#define TCC0_GCLK_ID 25 // Index of Generic Clock
+#define TCC0_MASTER_SLAVE_MODE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC0_OTMX 1 // Output Matrix feature implemented
+#define TCC0_OW_NUM 8 // Number of Output Waveforms
+#define TCC0_PG 1 // Pattern Generation feature implemented
+#define TCC0_SIZE 24
+#define TCC0_SWAP 1 // DTI outputs swap feature implemented
+
+#endif /* _SAME54_TCC0_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tcc1.h b/GPIO/ATSAME54/include/instance/tcc1.h
new file mode 100644
index 0000000..2e69cc1
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tcc1.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC1_INSTANCE_
+#define _SAME54_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA (0x41018000) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR (0x41018004) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET (0x41018005) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY (0x41018008) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA (0x4101800C) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB (0x41018010) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_WEXCTRL (0x41018014) /**< \brief (TCC1) Waveform Extension Configuration */
+#define REG_TCC1_DRVCTRL (0x41018018) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL (0x4101801E) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL (0x41018020) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR (0x41018024) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET (0x41018028) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG (0x4101802C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS (0x41018030) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT (0x41018034) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT (0x41018038) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE (0x4101803C) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER (0x41018040) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0 (0x41018044) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1 (0x41018048) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_CC2 (0x4101804C) /**< \brief (TCC1) Compare and Capture 2 */
+#define REG_TCC1_CC3 (0x41018050) /**< \brief (TCC1) Compare and Capture 3 */
+#define REG_TCC1_PATTBUF (0x41018064) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_PERBUF (0x4101806C) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCBUF0 (0x41018070) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCBUF1 (0x41018074) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#define REG_TCC1_CCBUF2 (0x41018078) /**< \brief (TCC1) Compare and Capture Buffer 2 */
+#define REG_TCC1_CCBUF3 (0x4101807C) /**< \brief (TCC1) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC1_CTRLA (*(RwReg *)0x41018000UL) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL) /**< \brief (TCC1) Waveform Extension Configuration */
+#define REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET (*(RwReg *)0x41018028UL) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS (*(RwReg *)0x41018030UL) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT (*(RwReg *)0x41018034UL) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT (*(RwReg16*)0x41018038UL) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE (*(RwReg *)0x4101803CUL) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER (*(RwReg *)0x41018040UL) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0 (*(RwReg *)0x41018044UL) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1 (*(RwReg *)0x41018048UL) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_CC2 (*(RwReg *)0x4101804CUL) /**< \brief (TCC1) Compare and Capture 2 */
+#define REG_TCC1_CC3 (*(RwReg *)0x41018050UL) /**< \brief (TCC1) Compare and Capture 3 */
+#define REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#define REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL) /**< \brief (TCC1) Compare and Capture Buffer 2 */
+#define REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL) /**< \brief (TCC1) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM 4 // Number of Compare/Capture units
+#define TCC1_DITHERING 1 // Dithering feature implemented
+#define TCC1_DMAC_ID_MC_0 30
+#define TCC1_DMAC_ID_MC_1 31
+#define TCC1_DMAC_ID_MC_2 32
+#define TCC1_DMAC_ID_MC_3 33
+#define TCC1_DMAC_ID_MC_LSB 30
+#define TCC1_DMAC_ID_MC_MSB 33
+#define TCC1_DMAC_ID_MC_SIZE 4
+#define TCC1_DMAC_ID_OVF 29 // DMA overflow/underflow/retrigger trigger
+#define TCC1_DTI 1 // Dead-Time-Insertion feature implemented
+#define TCC1_EXT 31 // Coding of implemented extended features
+#define TCC1_GCLK_ID 25 // Index of Generic Clock
+#define TCC1_MASTER_SLAVE_MODE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC1_OTMX 1 // Output Matrix feature implemented
+#define TCC1_OW_NUM 8 // Number of Output Waveforms
+#define TCC1_PG 1 // Pattern Generation feature implemented
+#define TCC1_SIZE 24
+#define TCC1_SWAP 1 // DTI outputs swap feature implemented
+
+#endif /* _SAME54_TCC1_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tcc2.h b/GPIO/ATSAME54/include/instance/tcc2.h
new file mode 100644
index 0000000..846bef6
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tcc2.h
@@ -0,0 +1,106 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC2_INSTANCE_
+#define _SAME54_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA (0x42000C00) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR (0x42000C04) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET (0x42000C05) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY (0x42000C08) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA (0x42000C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB (0x42000C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_WEXCTRL (0x42000C14) /**< \brief (TCC2) Waveform Extension Configuration */
+#define REG_TCC2_DRVCTRL (0x42000C18) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL (0x42000C1E) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL (0x42000C20) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR (0x42000C24) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET (0x42000C28) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG (0x42000C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS (0x42000C30) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT (0x42000C34) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE (0x42000C3C) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER (0x42000C40) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0 (0x42000C44) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1 (0x42000C48) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_CC2 (0x42000C4C) /**< \brief (TCC2) Compare and Capture 2 */
+#define REG_TCC2_PERBUF (0x42000C6C) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCBUF0 (0x42000C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCBUF1 (0x42000C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#define REG_TCC2_CCBUF2 (0x42000C78) /**< \brief (TCC2) Compare and Capture Buffer 2 */
+#else
+#define REG_TCC2_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42000C04UL) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42000C05UL) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42000C08UL) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA (*(RwReg *)0x42000C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB (*(RwReg *)0x42000C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_WEXCTRL (*(RwReg *)0x42000C14UL) /**< \brief (TCC2) Waveform Extension Configuration */
+#define REG_TCC2_DRVCTRL (*(RwReg *)0x42000C18UL) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42000C1EUL) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL (*(RwReg *)0x42000C20UL) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR (*(RwReg *)0x42000C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET (*(RwReg *)0x42000C28UL) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG (*(RwReg *)0x42000C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS (*(RwReg *)0x42000C30UL) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT (*(RwReg *)0x42000C34UL) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE (*(RwReg *)0x42000C3CUL) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER (*(RwReg *)0x42000C40UL) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0 (*(RwReg *)0x42000C44UL) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1 (*(RwReg *)0x42000C48UL) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_CC2 (*(RwReg *)0x42000C4CUL) /**< \brief (TCC2) Compare and Capture 2 */
+#define REG_TCC2_PERBUF (*(RwReg *)0x42000C6CUL) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCBUF0 (*(RwReg *)0x42000C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCBUF1 (*(RwReg *)0x42000C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#define REG_TCC2_CCBUF2 (*(RwReg *)0x42000C78UL) /**< \brief (TCC2) Compare and Capture Buffer 2 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM 3 // Number of Compare/Capture units
+#define TCC2_DITHERING 0 // Dithering feature implemented
+#define TCC2_DMAC_ID_MC_0 35
+#define TCC2_DMAC_ID_MC_1 36
+#define TCC2_DMAC_ID_MC_2 37
+#define TCC2_DMAC_ID_MC_LSB 35
+#define TCC2_DMAC_ID_MC_MSB 37
+#define TCC2_DMAC_ID_MC_SIZE 3
+#define TCC2_DMAC_ID_OVF 34 // DMA overflow/underflow/retrigger trigger
+#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
+#define TCC2_EXT 1 // Coding of implemented extended features
+#define TCC2_GCLK_ID 29 // Index of Generic Clock
+#define TCC2_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC2_OTMX 1 // Output Matrix feature implemented
+#define TCC2_OW_NUM 3 // Number of Output Waveforms
+#define TCC2_PG 0 // Pattern Generation feature implemented
+#define TCC2_SIZE 16
+#define TCC2_SWAP 0 // DTI outputs swap feature implemented
+
+#endif /* _SAME54_TCC2_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tcc3.h b/GPIO/ATSAME54/include/instance/tcc3.h
new file mode 100644
index 0000000..522527e
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tcc3.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC3
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC3_INSTANCE_
+#define _SAME54_TCC3_INSTANCE_
+
+/* ========== Register definition for TCC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC3_CTRLA (0x42001000) /**< \brief (TCC3) Control A */
+#define REG_TCC3_CTRLBCLR (0x42001004) /**< \brief (TCC3) Control B Clear */
+#define REG_TCC3_CTRLBSET (0x42001005) /**< \brief (TCC3) Control B Set */
+#define REG_TCC3_SYNCBUSY (0x42001008) /**< \brief (TCC3) Synchronization Busy */
+#define REG_TCC3_FCTRLA (0x4200100C) /**< \brief (TCC3) Recoverable Fault A Configuration */
+#define REG_TCC3_FCTRLB (0x42001010) /**< \brief (TCC3) Recoverable Fault B Configuration */
+#define REG_TCC3_DRVCTRL (0x42001018) /**< \brief (TCC3) Driver Control */
+#define REG_TCC3_DBGCTRL (0x4200101E) /**< \brief (TCC3) Debug Control */
+#define REG_TCC3_EVCTRL (0x42001020) /**< \brief (TCC3) Event Control */
+#define REG_TCC3_INTENCLR (0x42001024) /**< \brief (TCC3) Interrupt Enable Clear */
+#define REG_TCC3_INTENSET (0x42001028) /**< \brief (TCC3) Interrupt Enable Set */
+#define REG_TCC3_INTFLAG (0x4200102C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
+#define REG_TCC3_STATUS (0x42001030) /**< \brief (TCC3) Status */
+#define REG_TCC3_COUNT (0x42001034) /**< \brief (TCC3) Count */
+#define REG_TCC3_WAVE (0x4200103C) /**< \brief (TCC3) Waveform Control */
+#define REG_TCC3_PER (0x42001040) /**< \brief (TCC3) Period */
+#define REG_TCC3_CC0 (0x42001044) /**< \brief (TCC3) Compare and Capture 0 */
+#define REG_TCC3_CC1 (0x42001048) /**< \brief (TCC3) Compare and Capture 1 */
+#define REG_TCC3_PERBUF (0x4200106C) /**< \brief (TCC3) Period Buffer */
+#define REG_TCC3_CCBUF0 (0x42001070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
+#define REG_TCC3_CCBUF1 (0x42001074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC3_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (TCC3) Control A */
+#define REG_TCC3_CTRLBCLR (*(RwReg8 *)0x42001004UL) /**< \brief (TCC3) Control B Clear */
+#define REG_TCC3_CTRLBSET (*(RwReg8 *)0x42001005UL) /**< \brief (TCC3) Control B Set */
+#define REG_TCC3_SYNCBUSY (*(RoReg *)0x42001008UL) /**< \brief (TCC3) Synchronization Busy */
+#define REG_TCC3_FCTRLA (*(RwReg *)0x4200100CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
+#define REG_TCC3_FCTRLB (*(RwReg *)0x42001010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
+#define REG_TCC3_DRVCTRL (*(RwReg *)0x42001018UL) /**< \brief (TCC3) Driver Control */
+#define REG_TCC3_DBGCTRL (*(RwReg8 *)0x4200101EUL) /**< \brief (TCC3) Debug Control */
+#define REG_TCC3_EVCTRL (*(RwReg *)0x42001020UL) /**< \brief (TCC3) Event Control */
+#define REG_TCC3_INTENCLR (*(RwReg *)0x42001024UL) /**< \brief (TCC3) Interrupt Enable Clear */
+#define REG_TCC3_INTENSET (*(RwReg *)0x42001028UL) /**< \brief (TCC3) Interrupt Enable Set */
+#define REG_TCC3_INTFLAG (*(RwReg *)0x4200102CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
+#define REG_TCC3_STATUS (*(RwReg *)0x42001030UL) /**< \brief (TCC3) Status */
+#define REG_TCC3_COUNT (*(RwReg *)0x42001034UL) /**< \brief (TCC3) Count */
+#define REG_TCC3_WAVE (*(RwReg *)0x4200103CUL) /**< \brief (TCC3) Waveform Control */
+#define REG_TCC3_PER (*(RwReg *)0x42001040UL) /**< \brief (TCC3) Period */
+#define REG_TCC3_CC0 (*(RwReg *)0x42001044UL) /**< \brief (TCC3) Compare and Capture 0 */
+#define REG_TCC3_CC1 (*(RwReg *)0x42001048UL) /**< \brief (TCC3) Compare and Capture 1 */
+#define REG_TCC3_PERBUF (*(RwReg *)0x4200106CUL) /**< \brief (TCC3) Period Buffer */
+#define REG_TCC3_CCBUF0 (*(RwReg *)0x42001070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
+#define REG_TCC3_CCBUF1 (*(RwReg *)0x42001074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC3 peripheral ========== */
+#define TCC3_CC_NUM 2 // Number of Compare/Capture units
+#define TCC3_DITHERING 0 // Dithering feature implemented
+#define TCC3_DMAC_ID_MC_0 39
+#define TCC3_DMAC_ID_MC_1 40
+#define TCC3_DMAC_ID_MC_LSB 39
+#define TCC3_DMAC_ID_MC_MSB 40
+#define TCC3_DMAC_ID_MC_SIZE 2
+#define TCC3_DMAC_ID_OVF 38 // DMA overflow/underflow/retrigger trigger
+#define TCC3_DTI 0 // Dead-Time-Insertion feature implemented
+#define TCC3_EXT 0 // Coding of implemented extended features
+#define TCC3_GCLK_ID 29 // Index of Generic Clock
+#define TCC3_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC3_OTMX 0 // Output Matrix feature implemented
+#define TCC3_OW_NUM 2 // Number of Output Waveforms
+#define TCC3_PG 0 // Pattern Generation feature implemented
+#define TCC3_SIZE 16
+#define TCC3_SWAP 0 // DTI outputs swap feature implemented
+
+#endif /* _SAME54_TCC3_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/tcc4.h b/GPIO/ATSAME54/include/instance/tcc4.h
new file mode 100644
index 0000000..06880f2
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/tcc4.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC4
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TCC4_INSTANCE_
+#define _SAME54_TCC4_INSTANCE_
+
+/* ========== Register definition for TCC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC4_CTRLA (0x43001000) /**< \brief (TCC4) Control A */
+#define REG_TCC4_CTRLBCLR (0x43001004) /**< \brief (TCC4) Control B Clear */
+#define REG_TCC4_CTRLBSET (0x43001005) /**< \brief (TCC4) Control B Set */
+#define REG_TCC4_SYNCBUSY (0x43001008) /**< \brief (TCC4) Synchronization Busy */
+#define REG_TCC4_FCTRLA (0x4300100C) /**< \brief (TCC4) Recoverable Fault A Configuration */
+#define REG_TCC4_FCTRLB (0x43001010) /**< \brief (TCC4) Recoverable Fault B Configuration */
+#define REG_TCC4_DRVCTRL (0x43001018) /**< \brief (TCC4) Driver Control */
+#define REG_TCC4_DBGCTRL (0x4300101E) /**< \brief (TCC4) Debug Control */
+#define REG_TCC4_EVCTRL (0x43001020) /**< \brief (TCC4) Event Control */
+#define REG_TCC4_INTENCLR (0x43001024) /**< \brief (TCC4) Interrupt Enable Clear */
+#define REG_TCC4_INTENSET (0x43001028) /**< \brief (TCC4) Interrupt Enable Set */
+#define REG_TCC4_INTFLAG (0x4300102C) /**< \brief (TCC4) Interrupt Flag Status and Clear */
+#define REG_TCC4_STATUS (0x43001030) /**< \brief (TCC4) Status */
+#define REG_TCC4_COUNT (0x43001034) /**< \brief (TCC4) Count */
+#define REG_TCC4_WAVE (0x4300103C) /**< \brief (TCC4) Waveform Control */
+#define REG_TCC4_PER (0x43001040) /**< \brief (TCC4) Period */
+#define REG_TCC4_CC0 (0x43001044) /**< \brief (TCC4) Compare and Capture 0 */
+#define REG_TCC4_CC1 (0x43001048) /**< \brief (TCC4) Compare and Capture 1 */
+#define REG_TCC4_PERBUF (0x4300106C) /**< \brief (TCC4) Period Buffer */
+#define REG_TCC4_CCBUF0 (0x43001070) /**< \brief (TCC4) Compare and Capture Buffer 0 */
+#define REG_TCC4_CCBUF1 (0x43001074) /**< \brief (TCC4) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC4_CTRLA (*(RwReg *)0x43001000UL) /**< \brief (TCC4) Control A */
+#define REG_TCC4_CTRLBCLR (*(RwReg8 *)0x43001004UL) /**< \brief (TCC4) Control B Clear */
+#define REG_TCC4_CTRLBSET (*(RwReg8 *)0x43001005UL) /**< \brief (TCC4) Control B Set */
+#define REG_TCC4_SYNCBUSY (*(RoReg *)0x43001008UL) /**< \brief (TCC4) Synchronization Busy */
+#define REG_TCC4_FCTRLA (*(RwReg *)0x4300100CUL) /**< \brief (TCC4) Recoverable Fault A Configuration */
+#define REG_TCC4_FCTRLB (*(RwReg *)0x43001010UL) /**< \brief (TCC4) Recoverable Fault B Configuration */
+#define REG_TCC4_DRVCTRL (*(RwReg *)0x43001018UL) /**< \brief (TCC4) Driver Control */
+#define REG_TCC4_DBGCTRL (*(RwReg8 *)0x4300101EUL) /**< \brief (TCC4) Debug Control */
+#define REG_TCC4_EVCTRL (*(RwReg *)0x43001020UL) /**< \brief (TCC4) Event Control */
+#define REG_TCC4_INTENCLR (*(RwReg *)0x43001024UL) /**< \brief (TCC4) Interrupt Enable Clear */
+#define REG_TCC4_INTENSET (*(RwReg *)0x43001028UL) /**< \brief (TCC4) Interrupt Enable Set */
+#define REG_TCC4_INTFLAG (*(RwReg *)0x4300102CUL) /**< \brief (TCC4) Interrupt Flag Status and Clear */
+#define REG_TCC4_STATUS (*(RwReg *)0x43001030UL) /**< \brief (TCC4) Status */
+#define REG_TCC4_COUNT (*(RwReg *)0x43001034UL) /**< \brief (TCC4) Count */
+#define REG_TCC4_WAVE (*(RwReg *)0x4300103CUL) /**< \brief (TCC4) Waveform Control */
+#define REG_TCC4_PER (*(RwReg *)0x43001040UL) /**< \brief (TCC4) Period */
+#define REG_TCC4_CC0 (*(RwReg *)0x43001044UL) /**< \brief (TCC4) Compare and Capture 0 */
+#define REG_TCC4_CC1 (*(RwReg *)0x43001048UL) /**< \brief (TCC4) Compare and Capture 1 */
+#define REG_TCC4_PERBUF (*(RwReg *)0x4300106CUL) /**< \brief (TCC4) Period Buffer */
+#define REG_TCC4_CCBUF0 (*(RwReg *)0x43001070UL) /**< \brief (TCC4) Compare and Capture Buffer 0 */
+#define REG_TCC4_CCBUF1 (*(RwReg *)0x43001074UL) /**< \brief (TCC4) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC4 peripheral ========== */
+#define TCC4_CC_NUM 2 // Number of Compare/Capture units
+#define TCC4_DITHERING 0 // Dithering feature implemented
+#define TCC4_DMAC_ID_MC_0 42
+#define TCC4_DMAC_ID_MC_1 43
+#define TCC4_DMAC_ID_MC_LSB 42
+#define TCC4_DMAC_ID_MC_MSB 43
+#define TCC4_DMAC_ID_MC_SIZE 2
+#define TCC4_DMAC_ID_OVF 41 // DMA overflow/underflow/retrigger trigger
+#define TCC4_DTI 0 // Dead-Time-Insertion feature implemented
+#define TCC4_EXT 0 // Coding of implemented extended features
+#define TCC4_GCLK_ID 38 // Index of Generic Clock
+#define TCC4_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC4_OTMX 0 // Output Matrix feature implemented
+#define TCC4_OW_NUM 2 // Number of Output Waveforms
+#define TCC4_PG 0 // Pattern Generation feature implemented
+#define TCC4_SIZE 16
+#define TCC4_SWAP 0 // DTI outputs swap feature implemented
+
+#endif /* _SAME54_TCC4_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/trng.h b/GPIO/ATSAME54/include/instance/trng.h
new file mode 100644
index 0000000..24b5a66
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/trng.h
@@ -0,0 +1,51 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TRNG
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_TRNG_INSTANCE_
+#define _SAME54_TRNG_INSTANCE_
+
+/* ========== Register definition for TRNG peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TRNG_CTRLA (0x42002800) /**< \brief (TRNG) Control A */
+#define REG_TRNG_EVCTRL (0x42002804) /**< \brief (TRNG) Event Control */
+#define REG_TRNG_INTENCLR (0x42002808) /**< \brief (TRNG) Interrupt Enable Clear */
+#define REG_TRNG_INTENSET (0x42002809) /**< \brief (TRNG) Interrupt Enable Set */
+#define REG_TRNG_INTFLAG (0x4200280A) /**< \brief (TRNG) Interrupt Flag Status and Clear */
+#define REG_TRNG_DATA (0x42002820) /**< \brief (TRNG) Output Data */
+#else
+#define REG_TRNG_CTRLA (*(RwReg8 *)0x42002800UL) /**< \brief (TRNG) Control A */
+#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42002804UL) /**< \brief (TRNG) Event Control */
+#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42002808UL) /**< \brief (TRNG) Interrupt Enable Clear */
+#define REG_TRNG_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TRNG) Interrupt Enable Set */
+#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200280AUL) /**< \brief (TRNG) Interrupt Flag Status and Clear */
+#define REG_TRNG_DATA (*(RoReg *)0x42002820UL) /**< \brief (TRNG) Output Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME54_TRNG_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/usb.h b/GPIO/ATSAME54/include/instance/usb.h
new file mode 100644
index 0000000..c7b9098
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/usb.h
@@ -0,0 +1,343 @@
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_USB_INSTANCE_
+#define _SAME54_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA (0x41000000) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (0x41000002) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL (0x41000003) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS (0x4100000D) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (0x41000024) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (0x41000028) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (0x41000008) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (0x4100000A) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (0x4100000C) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB (0x41000008) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC (0x4100000A) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS (0x4100000C) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM (0x41000010) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH (0x41000012) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR (0x41000014) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET (0x41000018) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG (0x4100001C) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY (0x41000020) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0 (0x41000100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41000103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41000104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41000105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41000106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41000107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41000108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41000109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1 (0x41000120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41000123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41000124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41000125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41000126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41000127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41000128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41000129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2 (0x41000140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41000143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41000144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41000145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41000146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41000147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41000148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41000149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3 (0x41000160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41000163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41000164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41000165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41000166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41000167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41000168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41000169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4 (0x41000180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41000183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41000184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41000185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41000186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41000187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41000188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41000189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5 (0x410001A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410001A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410001A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410001A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410001A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410001A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410001A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410001A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6 (0x410001C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410001C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410001C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410001C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410001C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410001C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410001C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410001C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7 (0x410001E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410001E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410001E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410001E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410001E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410001E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410001E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410001E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (*(RwReg *)0x41000024UL) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100000CUL) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM (*(RwReg16*)0x41000010UL) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41000012UL) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41000103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41000123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41000143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41000163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41000183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410001A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410001C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410001E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_AHB_2_USB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...)
+#define USB_AHB_2_USB_RD_DATA_BITS 8 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
+#define USB_AHB_2_USB_WR_DATA_BITS 32 // 8, 16 or 32 : here, AHB transfer is made in word mode
+#define USB_AHB_2_USB_WR_THRESHOLD 2 // as soon as there are N bytes-free inside the fifo, ahb read transfer is requested
+#define USB_DATA_BUS_16_8 0 // UTMI/SIE data bus size : 0 -> 8 bits, 1 -> 16 bits
+#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM
+#define USB_EPT_NUM 8 // Number of USB end points
+#define USB_GCLK_ID 10 // Index of Generic Clock
+#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value
+#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value
+#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented
+#define USB_PIPE_NUM 8 // Number of USB pipes
+#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system
+#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...)
+#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
+#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested
+#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode
+
+#endif /* _SAME54_USB_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/instance/wdt.h b/GPIO/ATSAME54/include/instance/wdt.h
new file mode 100644
index 0000000..2c03d70
--- /dev/null
+++ b/GPIO/ATSAME54/include/instance/wdt.h
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_WDT_INSTANCE_
+#define _SAME54_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */
+#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */
+#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME54_WDT_INSTANCE_ */
diff --git a/GPIO/ATSAME54/include/pio/same54n19a.h b/GPIO/ATSAME54/include/pio/same54n19a.h
new file mode 100644
index 0000000..7fbc483
--- /dev/null
+++ b/GPIO/ATSAME54/include/pio/same54n19a.h
@@ -0,0 +1,2693 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME54N19A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54N19A_PIO_
+#define _SAME54N19A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB18 50 /**< \brief Pin Number for PB18 */
+#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */
+#define PIN_PB19 51 /**< \brief Pin Number for PB19 */
+#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */
+#define PIN_PB20 52 /**< \brief Pin Number for PB20 */
+#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */
+#define PIN_PB21 53 /**< \brief Pin Number for PB21 */
+#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB24 56 /**< \brief Pin Number for PB24 */
+#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */
+#define PIN_PB25 57 /**< \brief Pin Number for PB25 */
+#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */
+#define PIN_PC00 64 /**< \brief Pin Number for PC00 */
+#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */
+#define PIN_PC01 65 /**< \brief Pin Number for PC01 */
+#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */
+#define PIN_PC02 66 /**< \brief Pin Number for PC02 */
+#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */
+#define PIN_PC03 67 /**< \brief Pin Number for PC03 */
+#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */
+#define PIN_PC05 69 /**< \brief Pin Number for PC05 */
+#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */
+#define PIN_PC06 70 /**< \brief Pin Number for PC06 */
+#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */
+#define PIN_PC07 71 /**< \brief Pin Number for PC07 */
+#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */
+#define PIN_PC10 74 /**< \brief Pin Number for PC10 */
+#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */
+#define PIN_PC11 75 /**< \brief Pin Number for PC11 */
+#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */
+#define PIN_PC12 76 /**< \brief Pin Number for PC12 */
+#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */
+#define PIN_PC13 77 /**< \brief Pin Number for PC13 */
+#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */
+#define PIN_PC14 78 /**< \brief Pin Number for PC14 */
+#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */
+#define PIN_PC15 79 /**< \brief Pin Number for PC15 */
+#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */
+#define PIN_PC16 80 /**< \brief Pin Number for PC16 */
+#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */
+#define PIN_PC17 81 /**< \brief Pin Number for PC17 */
+#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */
+#define PIN_PC18 82 /**< \brief Pin Number for PC18 */
+#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */
+#define PIN_PC19 83 /**< \brief Pin Number for PC19 */
+#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */
+#define PIN_PC20 84 /**< \brief Pin Number for PC20 */
+#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */
+#define PIN_PC21 85 /**< \brief Pin Number for PC21 */
+#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */
+#define PIN_PC24 88 /**< \brief Pin Number for PC24 */
+#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */
+#define PIN_PC25 89 /**< \brief Pin Number for PC25 */
+#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */
+#define PIN_PC26 90 /**< \brief Pin Number for PC26 */
+#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */
+#define PIN_PC27 91 /**< \brief Pin Number for PC27 */
+#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */
+#define PIN_PC28 92 /**< \brief Pin Number for PC28 */
+#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
+#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
+#define MUX_PC27M_CM4_SWO _L_(12)
+#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
+#define PORT_PC27M_CM4_SWO (_UL_(1) << 27)
+#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO _L_(7)
+#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
+#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
+#define MUX_PC27H_CM4_TRACECLK _L_(7)
+#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
+#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27)
+#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
+#define MUX_PC28H_CM4_TRACEDATA0 _L_(7)
+#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
+#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28)
+#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
+#define MUX_PC26H_CM4_TRACEDATA1 _L_(7)
+#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
+#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26)
+#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
+#define MUX_PC25H_CM4_TRACEDATA2 _L_(7)
+#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
+#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25)
+#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
+#define MUX_PC24H_CM4_TRACEDATA3 _L_(7)
+#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
+#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0 _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
+#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1 _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
+#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2 _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0 _L_(12)
+#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0 _L_(12)
+#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0 _L_(12)
+#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0 _L_(12)
+#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1 _L_(12)
+#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1 _L_(12)
+#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1 _L_(12)
+#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1 _L_(12)
+#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2 _L_(12)
+#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2 _L_(12)
+#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3 _L_(12)
+#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3 _L_(12)
+#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4 _L_(12)
+#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4 _L_(12)
+#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
+#define MUX_PB18M_GCLK_IO4 _L_(12)
+#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
+#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18)
+#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5 _L_(12)
+#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5 _L_(12)
+#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
+#define MUX_PB19M_GCLK_IO5 _L_(12)
+#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
+#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19)
+#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6 _L_(12)
+#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
+#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
+#define MUX_PB20M_GCLK_IO6 _L_(12)
+#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
+#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20)
+#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7 _L_(12)
+#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
+#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
+#define MUX_PB21M_GCLK_IO7 _L_(12)
+#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
+#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
+#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
+#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
+#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
+#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
+#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
+#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
+#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
+#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
+#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
+#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
+#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
+#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
+#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
+#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
+#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
+#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7)
+#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
+#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
+#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
+#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
+#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26)
+#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
+#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
+#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
+#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
+#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28)
+#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI _L_(0)
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
+#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
+#define MUX_PC17D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
+#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17)
+#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
+#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24)
+#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
+#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
+#define MUX_PC16D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
+#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16)
+#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
+#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25)
+#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
+#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
+#define MUX_PC18D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
+#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18)
+#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
+#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24)
+#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
+#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
+#define MUX_PC19D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
+#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19)
+#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
+#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
+#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
+#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
+#define MUX_PC27C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
+#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27)
+#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
+#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
+#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
+#define MUX_PC28C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
+#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28)
+#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0 _L_(4)
+#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
+#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0 _L_(4)
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
+#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0 _L_(4)
+#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1 _L_(4)
+#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
+#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1 _L_(4)
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
+#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1 _L_(4)
+#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0 _L_(4)
+#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
+#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0 _L_(4)
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1 _L_(4)
+#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
+#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1 _L_(4)
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM _L_(7)
+#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP _L_(7)
+#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
+#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
+#define MUX_PB25D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
+#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25)
+#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
+#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
+#define MUX_PB24D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
+#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24)
+#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
+#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
+#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24)
+#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
+#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
+#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25)
+#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0 _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
+#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20)
+#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1 _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
+#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21)
+#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0 _L_(6)
+#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0 _L_(6)
+#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0 _L_(5)
+#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
+#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
+#define MUX_PC10F_TCC0_WO0 _L_(5)
+#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
+#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10)
+#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
+#define MUX_PC16F_TCC0_WO0 _L_(5)
+#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
+#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16)
+#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1 _L_(6)
+#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1 _L_(6)
+#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1 _L_(5)
+#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
+#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
+#define MUX_PC11F_TCC0_WO1 _L_(5)
+#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
+#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11)
+#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
+#define MUX_PC17F_TCC0_WO1 _L_(5)
+#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
+#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17)
+#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2 _L_(6)
+#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2 _L_(6)
+#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 _L_(5)
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
+#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
+#define MUX_PC12F_TCC0_WO2 _L_(5)
+#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
+#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12)
+#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
+#define MUX_PC18F_TCC0_WO2 _L_(5)
+#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
+#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18)
+#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3 _L_(6)
+#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3 _L_(6)
+#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 _L_(5)
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
+#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
+#define MUX_PC13F_TCC0_WO3 _L_(5)
+#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
+#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13)
+#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
+#define MUX_PC19F_TCC0_WO3 _L_(5)
+#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
+#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19)
+#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4 _L_(6)
+#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4 _L_(6)
+#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 _L_(5)
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
+#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
+#define MUX_PC14F_TCC0_WO4 _L_(5)
+#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
+#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14)
+#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
+#define MUX_PC20F_TCC0_WO4 _L_(5)
+#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
+#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20)
+#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5 _L_(6)
+#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5 _L_(6)
+#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 _L_(5)
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
+#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
+#define MUX_PC15F_TCC0_WO5 _L_(5)
+#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
+#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15)
+#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
+#define MUX_PC21F_TCC0_WO5 _L_(5)
+#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
+#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21)
+#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6 _L_(6)
+#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6 _L_(6)
+#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 _L_(5)
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7 _L_(6)
+#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7 _L_(6)
+#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 _L_(5)
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0 _L_(6)
+#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
+#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
+#define MUX_PC14G_TCC1_WO0 _L_(6)
+#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
+#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14)
+#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0 _L_(5)
+#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
+#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC1_WO0 _L_(5)
+#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
+#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18)
+#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1 _L_(6)
+#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
+#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
+#define MUX_PC15G_TCC1_WO1 _L_(6)
+#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
+#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15)
+#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1 _L_(5)
+#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
+#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC1_WO1 _L_(5)
+#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
+#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19)
+#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2 _L_(6)
+#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2 _L_(6)
+#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2 _L_(5)
+#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
+#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC1_WO2 _L_(5)
+#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
+#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20)
+#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3 _L_(6)
+#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3 _L_(6)
+#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3 _L_(5)
+#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
+#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC1_WO3 _L_(5)
+#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
+#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21)
+#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4 _L_(6)
+#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
+#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
+#define MUX_PC10G_TCC1_WO4 _L_(6)
+#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
+#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10)
+#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4 _L_(5)
+#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5 _L_(6)
+#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
+#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
+#define MUX_PC11G_TCC1_WO5 _L_(6)
+#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
+#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11)
+#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5 _L_(5)
+#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6 _L_(6)
+#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
+#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
+#define MUX_PC12G_TCC1_WO6 _L_(6)
+#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
+#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12)
+#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6 _L_(5)
+#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7 _L_(6)
+#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
+#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
+#define MUX_PC13G_TCC1_WO7 _L_(6)
+#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
+#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13)
+#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7 _L_(5)
+#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0 _L_(4)
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0 _L_(4)
+#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0 _L_(4)
+#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
+#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1 _L_(4)
+#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
+#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1 _L_(4)
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1 _L_(4)
+#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 _L_(4)
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 _L_(4)
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 _L_(4)
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 _L_(4)
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
+/* ========== PORT definition for TAL peripheral ========== */
+#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */
+#define MUX_PA27H_TAL_BRK _L_(7)
+#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK)
+#define PORT_PA27H_TAL_BRK (_UL_(1) << 27)
+#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */
+#define MUX_PB31H_TAL_BRK _L_(7)
+#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK)
+#define PORT_PB31H_TAL_BRK (_UL_(1) << 31)
+/* ========== PORT definition for CAN0 peripheral ========== */
+#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */
+#define MUX_PA23I_CAN0_RX _L_(8)
+#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX)
+#define PORT_PA23I_CAN0_RX (_UL_(1) << 23)
+#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */
+#define MUX_PA25I_CAN0_RX _L_(8)
+#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX)
+#define PORT_PA25I_CAN0_RX (_UL_(1) << 25)
+#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */
+#define MUX_PA22I_CAN0_TX _L_(8)
+#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX)
+#define PORT_PA22I_CAN0_TX (_UL_(1) << 22)
+#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */
+#define MUX_PA24I_CAN0_TX _L_(8)
+#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX)
+#define PORT_PA24I_CAN0_TX (_UL_(1) << 24)
+/* ========== PORT definition for CAN1 peripheral ========== */
+#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */
+#define MUX_PB13H_CAN1_RX _L_(7)
+#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX)
+#define PORT_PB13H_CAN1_RX (_UL_(1) << 13)
+#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */
+#define MUX_PB15H_CAN1_RX _L_(7)
+#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX)
+#define PORT_PB15H_CAN1_RX (_UL_(1) << 15)
+#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */
+#define MUX_PB12H_CAN1_TX _L_(7)
+#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX)
+#define PORT_PB12H_CAN1_TX (_UL_(1) << 12)
+#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */
+#define MUX_PB14H_CAN1_TX _L_(7)
+#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX)
+#define PORT_PB14H_CAN1_TX (_UL_(1) << 14)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
+#define MUX_PC21L_GMAC_GCOL _L_(11)
+#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
+#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21)
+#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14)
+#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
+#define MUX_PC11L_GMAC_GMDC _L_(11)
+#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
+#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11)
+#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15)
+#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
+#define MUX_PC12L_GMAC_GMDIO _L_(11)
+#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
+#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12)
+#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0 _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1 _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12)
+#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
+#define MUX_PC15L_GMAC_GRX2 _L_(11)
+#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
+#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15)
+#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
+#define MUX_PC14L_GMAC_GRX3 _L_(11)
+#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
+#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14)
+#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
+#define MUX_PC18L_GMAC_GRXCK _L_(11)
+#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
+#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18)
+#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
+#define MUX_PC20L_GMAC_GRXDV _L_(11)
+#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
+#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20)
+#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0 _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1 _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19)
+#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
+#define MUX_PC16L_GMAC_GTX2 _L_(11)
+#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
+#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16)
+#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
+#define MUX_PC17L_GMAC_GTX3 _L_(11)
+#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
+#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17)
+#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17)
+#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
+#define MUX_PC19L_GMAC_GTXER _L_(11)
+#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
+#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0 _L_(5)
+#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0 _L_(5)
+#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1 _L_(5)
+#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1 _L_(5)
+#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2 _L_(5)
+#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2 _L_(5)
+#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0 _L_(5)
+#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0 _L_(5)
+#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1 _L_(5)
+#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1 _L_(5)
+#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 _L_(4)
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 _L_(4)
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
+#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 _L_(4)
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 _L_(4)
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 _L_(4)
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
+#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 _L_(4)
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 _L_(4)
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 _L_(4)
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 _L_(4)
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 _L_(4)
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 _L_(4)
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 _L_(4)
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
+#define MUX_PB18G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
+#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18)
+#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
+#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
+#define MUX_PC16G_PDEC_QDI0 _L_(6)
+#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
+#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16)
+#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0 _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
+#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
+#define MUX_PB19G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
+#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19)
+#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
+#define MUX_PB24G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
+#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24)
+#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
+#define MUX_PC17G_PDEC_QDI1 _L_(6)
+#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
+#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17)
+#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1 _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
+#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
+#define MUX_PB20G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
+#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20)
+#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
+#define MUX_PB25G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
+#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25)
+#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
+#define MUX_PC18G_PDEC_QDI2 _L_(6)
+#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
+#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18)
+#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 _L_(1)
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
+#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 _L_(1)
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
+#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 _L_(1)
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
+#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 _L_(1)
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
+#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0 _L_(12)
+#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0 _L_(12)
+#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
+#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
+#define MUX_PB24M_AC_CMP0 _L_(12)
+#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
+#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24)
+#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1 _L_(12)
+#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1 _L_(12)
+#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
+#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
+#define MUX_PB25M_AC_CMP1 _L_(12)
+#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
+#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS _L_(7)
+#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0 _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
+#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1 _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
+#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2 _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3 _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK _L_(7)
+#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0 _L_(13)
+#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
+#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0 _L_(13)
+#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0 _L_(13)
+#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1 _L_(13)
+#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
+#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1 _L_(13)
+#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1 _L_(13)
+#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
+#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2 _L_(13)
+#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
+#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2 _L_(13)
+#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2 _L_(13)
+#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
+#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3 _L_(13)
+#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
+#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3 _L_(13)
+#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4 _L_(13)
+#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
+#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
+#define MUX_PC27N_CCL_IN4 _L_(13)
+#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
+#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27)
+#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5 _L_(13)
+#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
+#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
+#define MUX_PC28N_CCL_IN5 _L_(13)
+#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
+#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28)
+#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6 _L_(13)
+#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6 _L_(13)
+#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
+#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7 _L_(13)
+#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7 _L_(13)
+#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
+#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8 _L_(13)
+#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8 _L_(13)
+#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
+#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9 _L_(13)
+#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
+#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
+#define MUX_PC20N_CCL_IN9 _L_(13)
+#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
+#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20)
+#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10 _L_(13)
+#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
+#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
+#define MUX_PC21N_CCL_IN10 _L_(13)
+#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
+#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21)
+#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11 _L_(13)
+#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11 _L_(13)
+#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0 _L_(13)
+#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
+#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0 _L_(13)
+#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0 _L_(13)
+#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
+#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0 _L_(13)
+#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1 _L_(13)
+#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1 _L_(13)
+#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1 _L_(13)
+#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2 _L_(13)
+#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2 _L_(13)
+#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
+#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3 _L_(13)
+#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
+#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
+#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
+#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
+#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
+#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
+#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18)
+#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
+#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
+#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM6 peripheral ========== */
+#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
+#define MUX_PC13D_SERCOM6_PAD0 _L_(3)
+#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
+#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13)
+#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
+#define MUX_PC16C_SERCOM6_PAD0 _L_(2)
+#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
+#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16)
+#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
+#define MUX_PC12D_SERCOM6_PAD1 _L_(3)
+#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
+#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12)
+#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
+#define MUX_PC05C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
+#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5)
+#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
+#define MUX_PC17C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
+#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17)
+#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
+#define MUX_PC14D_SERCOM6_PAD2 _L_(3)
+#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
+#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14)
+#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
+#define MUX_PC06C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
+#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6)
+#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
+#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10)
+#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
+#define MUX_PC18C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
+#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18)
+#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
+#define MUX_PC15D_SERCOM6_PAD3 _L_(3)
+#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
+#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15)
+#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
+#define MUX_PC07C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
+#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7)
+#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
+#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11)
+#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
+#define MUX_PC19C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
+#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM7 peripheral ========== */
+#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
+#define MUX_PB21D_SERCOM7_PAD0 _L_(3)
+#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
+#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21)
+#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
+#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30)
+#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
+#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12)
+#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
+#define MUX_PB20D_SERCOM7_PAD1 _L_(3)
+#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
+#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20)
+#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
+#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31)
+#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
+#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13)
+#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
+#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18)
+#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
+#define MUX_PC10D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
+#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10)
+#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
+#define MUX_PC14C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
+#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14)
+#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
+#define MUX_PA30C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
+#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30)
+#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
+#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19)
+#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
+#define MUX_PC11D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
+#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11)
+#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
+#define MUX_PC15C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
+#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15)
+#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
+#define MUX_PA31C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
+#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0 _L_(5)
+#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0 _L_(5)
+#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1 _L_(5)
+#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1 _L_(5)
+#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TC6_WO0 _L_(4)
+#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
+#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30)
+#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 _L_(4)
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2)
+#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 _L_(4)
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16)
+#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TC6_WO1 _L_(4)
+#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
+#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31)
+#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 _L_(4)
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3)
+#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 _L_(4)
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 _L_(4)
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20)
+#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 _L_(4)
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0)
+#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 _L_(4)
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22)
+#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 _L_(4)
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21)
+#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 _L_(4)
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1)
+#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 _L_(4)
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0 _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
+#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1 _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2 _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3 _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4 _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
+#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5 _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
+#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6 _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7 _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8 _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9 _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10 _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11 _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12 _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13 _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
+#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14 _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15 _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
+#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0 _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
+#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1 _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
+#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2 _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
+#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3 _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
+#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4 _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
+#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5 _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
+#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6 _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
+#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7 _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
+#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8 _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9 _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10 _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11 _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12 _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13 _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14 _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15 _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16 _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17 _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18 _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19 _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20 _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
+#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21 _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
+#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22 _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
+#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23 _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
+#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24 _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
+#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25 _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
+#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26 _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27 _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28 _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29 _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30 _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
+#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31 _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
+#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0 _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1 _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2 _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3 _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
+#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4 _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5 _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6 _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7 _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8 _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9 _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10 _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11 _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
+#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13 _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14 _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15 _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16 _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17 _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18 _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19 _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20 _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21 _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
+#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22 _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
+#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23 _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
+#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24 _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
+#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25 _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
+#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26 _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27 _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28 _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29 _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30 _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31 _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0 _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
+#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1 _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
+#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2 _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
+#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3 _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
+#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
+#define MUX_PC02B_ADC1_AIN4 _L_(1)
+#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
+#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2)
+#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
+#define MUX_PC03B_ADC1_AIN5 _L_(1)
+#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
+#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3)
+#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6 _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
+#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7 _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
+#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8 _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
+#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9 _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
+#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
+#define MUX_PC00B_ADC1_AIN10 _L_(1)
+#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
+#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0)
+#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
+#define MUX_PC01B_ADC1_AIN11 _L_(1)
+#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
+#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0 _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
+#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1 _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0 _L_(9)
+#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
+#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0 _L_(9)
+#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1 _L_(9)
+#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1 _L_(9)
+#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0 _L_(9)
+#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
+#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0 _L_(9)
+#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1 _L_(9)
+#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0 _L_(9)
+#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0 _L_(9)
+#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1 _L_(9)
+#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI _L_(9)
+#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI _L_(9)
+#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO _L_(9)
+#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO _L_(9)
+#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK _L_(10)
+#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0 _L_(10)
+#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1 _L_(10)
+#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2 _L_(10)
+#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3 _L_(10)
+#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4 _L_(10)
+#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5 _L_(10)
+#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6 _L_(10)
+#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7 _L_(10)
+#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8 _L_(10)
+#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9 _L_(10)
+#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
+#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
+#define MUX_PC12K_PCC_DATA10 _L_(10)
+#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
+#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12)
+#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
+#define MUX_PC13K_PCC_DATA11 _L_(10)
+#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
+#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13)
+#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
+#define MUX_PC14K_PCC_DATA12 _L_(10)
+#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
+#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14)
+#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
+#define MUX_PC15K_PCC_DATA13 _L_(10)
+#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
+#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1 _L_(10)
+#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2 _L_(10)
+#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
+#define MUX_PC06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
+#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
+#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
+#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
+#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
+#define MUX_PC07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
+#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7)
+/* ========== PORT definition for SDHC1 peripheral ========== */
+#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
+#define MUX_PB16I_SDHC1_SDCD _L_(8)
+#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
+#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16)
+#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
+#define MUX_PC20I_SDHC1_SDCD _L_(8)
+#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
+#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20)
+#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
+#define MUX_PA21I_SDHC1_SDCK _L_(8)
+#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
+#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21)
+#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
+#define MUX_PA20I_SDHC1_SDCMD _L_(8)
+#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
+#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20)
+#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
+#define MUX_PB18I_SDHC1_SDDAT0 _L_(8)
+#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
+#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18)
+#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
+#define MUX_PB19I_SDHC1_SDDAT1 _L_(8)
+#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
+#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19)
+#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
+#define MUX_PB20I_SDHC1_SDDAT2 _L_(8)
+#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
+#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20)
+#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
+#define MUX_PB21I_SDHC1_SDDAT3 _L_(8)
+#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
+#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21)
+#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
+#define MUX_PB17I_SDHC1_SDWP _L_(8)
+#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
+#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17)
+#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
+#define MUX_PC21I_SDHC1_SDWP _L_(8)
+#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
+#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21)
+
+#endif /* _SAME54N19A_PIO_ */
diff --git a/GPIO/ATSAME54/include/pio/same54n20a.h b/GPIO/ATSAME54/include/pio/same54n20a.h
new file mode 100644
index 0000000..892f9cb
--- /dev/null
+++ b/GPIO/ATSAME54/include/pio/same54n20a.h
@@ -0,0 +1,2693 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME54N20A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54N20A_PIO_
+#define _SAME54N20A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB18 50 /**< \brief Pin Number for PB18 */
+#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */
+#define PIN_PB19 51 /**< \brief Pin Number for PB19 */
+#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */
+#define PIN_PB20 52 /**< \brief Pin Number for PB20 */
+#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */
+#define PIN_PB21 53 /**< \brief Pin Number for PB21 */
+#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB24 56 /**< \brief Pin Number for PB24 */
+#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */
+#define PIN_PB25 57 /**< \brief Pin Number for PB25 */
+#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */
+#define PIN_PC00 64 /**< \brief Pin Number for PC00 */
+#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */
+#define PIN_PC01 65 /**< \brief Pin Number for PC01 */
+#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */
+#define PIN_PC02 66 /**< \brief Pin Number for PC02 */
+#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */
+#define PIN_PC03 67 /**< \brief Pin Number for PC03 */
+#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */
+#define PIN_PC05 69 /**< \brief Pin Number for PC05 */
+#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */
+#define PIN_PC06 70 /**< \brief Pin Number for PC06 */
+#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */
+#define PIN_PC07 71 /**< \brief Pin Number for PC07 */
+#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */
+#define PIN_PC10 74 /**< \brief Pin Number for PC10 */
+#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */
+#define PIN_PC11 75 /**< \brief Pin Number for PC11 */
+#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */
+#define PIN_PC12 76 /**< \brief Pin Number for PC12 */
+#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */
+#define PIN_PC13 77 /**< \brief Pin Number for PC13 */
+#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */
+#define PIN_PC14 78 /**< \brief Pin Number for PC14 */
+#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */
+#define PIN_PC15 79 /**< \brief Pin Number for PC15 */
+#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */
+#define PIN_PC16 80 /**< \brief Pin Number for PC16 */
+#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */
+#define PIN_PC17 81 /**< \brief Pin Number for PC17 */
+#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */
+#define PIN_PC18 82 /**< \brief Pin Number for PC18 */
+#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */
+#define PIN_PC19 83 /**< \brief Pin Number for PC19 */
+#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */
+#define PIN_PC20 84 /**< \brief Pin Number for PC20 */
+#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */
+#define PIN_PC21 85 /**< \brief Pin Number for PC21 */
+#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */
+#define PIN_PC24 88 /**< \brief Pin Number for PC24 */
+#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */
+#define PIN_PC25 89 /**< \brief Pin Number for PC25 */
+#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */
+#define PIN_PC26 90 /**< \brief Pin Number for PC26 */
+#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */
+#define PIN_PC27 91 /**< \brief Pin Number for PC27 */
+#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */
+#define PIN_PC28 92 /**< \brief Pin Number for PC28 */
+#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
+#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
+#define MUX_PC27M_CM4_SWO _L_(12)
+#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
+#define PORT_PC27M_CM4_SWO (_UL_(1) << 27)
+#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO _L_(7)
+#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
+#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
+#define MUX_PC27H_CM4_TRACECLK _L_(7)
+#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
+#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27)
+#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
+#define MUX_PC28H_CM4_TRACEDATA0 _L_(7)
+#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
+#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28)
+#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
+#define MUX_PC26H_CM4_TRACEDATA1 _L_(7)
+#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
+#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26)
+#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
+#define MUX_PC25H_CM4_TRACEDATA2 _L_(7)
+#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
+#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25)
+#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
+#define MUX_PC24H_CM4_TRACEDATA3 _L_(7)
+#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
+#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0 _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
+#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1 _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
+#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2 _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0 _L_(12)
+#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0 _L_(12)
+#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0 _L_(12)
+#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0 _L_(12)
+#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1 _L_(12)
+#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1 _L_(12)
+#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1 _L_(12)
+#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1 _L_(12)
+#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2 _L_(12)
+#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2 _L_(12)
+#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3 _L_(12)
+#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3 _L_(12)
+#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4 _L_(12)
+#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4 _L_(12)
+#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
+#define MUX_PB18M_GCLK_IO4 _L_(12)
+#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
+#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18)
+#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5 _L_(12)
+#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5 _L_(12)
+#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
+#define MUX_PB19M_GCLK_IO5 _L_(12)
+#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
+#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19)
+#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6 _L_(12)
+#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
+#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
+#define MUX_PB20M_GCLK_IO6 _L_(12)
+#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
+#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20)
+#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7 _L_(12)
+#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
+#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
+#define MUX_PB21M_GCLK_IO7 _L_(12)
+#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
+#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
+#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
+#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
+#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
+#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
+#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
+#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
+#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
+#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
+#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
+#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
+#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
+#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
+#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
+#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
+#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
+#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7)
+#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
+#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
+#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
+#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
+#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26)
+#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
+#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
+#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
+#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
+#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28)
+#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI _L_(0)
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
+#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
+#define MUX_PC17D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
+#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17)
+#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
+#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24)
+#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
+#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
+#define MUX_PC16D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
+#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16)
+#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
+#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25)
+#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
+#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
+#define MUX_PC18D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
+#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18)
+#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
+#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24)
+#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
+#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
+#define MUX_PC19D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
+#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19)
+#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
+#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
+#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
+#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
+#define MUX_PC27C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
+#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27)
+#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
+#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
+#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
+#define MUX_PC28C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
+#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28)
+#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0 _L_(4)
+#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
+#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0 _L_(4)
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
+#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0 _L_(4)
+#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1 _L_(4)
+#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
+#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1 _L_(4)
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
+#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1 _L_(4)
+#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0 _L_(4)
+#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
+#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0 _L_(4)
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1 _L_(4)
+#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
+#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1 _L_(4)
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM _L_(7)
+#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP _L_(7)
+#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
+#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
+#define MUX_PB25D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
+#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25)
+#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
+#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
+#define MUX_PB24D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
+#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24)
+#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
+#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
+#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24)
+#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
+#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
+#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25)
+#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0 _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
+#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20)
+#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1 _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
+#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21)
+#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0 _L_(6)
+#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0 _L_(6)
+#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0 _L_(5)
+#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
+#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
+#define MUX_PC10F_TCC0_WO0 _L_(5)
+#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
+#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10)
+#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
+#define MUX_PC16F_TCC0_WO0 _L_(5)
+#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
+#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16)
+#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1 _L_(6)
+#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1 _L_(6)
+#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1 _L_(5)
+#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
+#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
+#define MUX_PC11F_TCC0_WO1 _L_(5)
+#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
+#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11)
+#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
+#define MUX_PC17F_TCC0_WO1 _L_(5)
+#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
+#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17)
+#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2 _L_(6)
+#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2 _L_(6)
+#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 _L_(5)
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
+#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
+#define MUX_PC12F_TCC0_WO2 _L_(5)
+#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
+#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12)
+#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
+#define MUX_PC18F_TCC0_WO2 _L_(5)
+#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
+#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18)
+#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3 _L_(6)
+#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3 _L_(6)
+#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 _L_(5)
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
+#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
+#define MUX_PC13F_TCC0_WO3 _L_(5)
+#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
+#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13)
+#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
+#define MUX_PC19F_TCC0_WO3 _L_(5)
+#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
+#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19)
+#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4 _L_(6)
+#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4 _L_(6)
+#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 _L_(5)
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
+#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
+#define MUX_PC14F_TCC0_WO4 _L_(5)
+#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
+#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14)
+#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
+#define MUX_PC20F_TCC0_WO4 _L_(5)
+#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
+#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20)
+#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5 _L_(6)
+#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5 _L_(6)
+#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 _L_(5)
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
+#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
+#define MUX_PC15F_TCC0_WO5 _L_(5)
+#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
+#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15)
+#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
+#define MUX_PC21F_TCC0_WO5 _L_(5)
+#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
+#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21)
+#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6 _L_(6)
+#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6 _L_(6)
+#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 _L_(5)
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7 _L_(6)
+#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7 _L_(6)
+#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 _L_(5)
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0 _L_(6)
+#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
+#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
+#define MUX_PC14G_TCC1_WO0 _L_(6)
+#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
+#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14)
+#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0 _L_(5)
+#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
+#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC1_WO0 _L_(5)
+#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
+#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18)
+#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1 _L_(6)
+#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
+#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
+#define MUX_PC15G_TCC1_WO1 _L_(6)
+#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
+#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15)
+#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1 _L_(5)
+#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
+#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC1_WO1 _L_(5)
+#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
+#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19)
+#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2 _L_(6)
+#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2 _L_(6)
+#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2 _L_(5)
+#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
+#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC1_WO2 _L_(5)
+#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
+#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20)
+#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3 _L_(6)
+#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3 _L_(6)
+#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3 _L_(5)
+#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
+#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC1_WO3 _L_(5)
+#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
+#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21)
+#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4 _L_(6)
+#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
+#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
+#define MUX_PC10G_TCC1_WO4 _L_(6)
+#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
+#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10)
+#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4 _L_(5)
+#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5 _L_(6)
+#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
+#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
+#define MUX_PC11G_TCC1_WO5 _L_(6)
+#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
+#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11)
+#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5 _L_(5)
+#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6 _L_(6)
+#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
+#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
+#define MUX_PC12G_TCC1_WO6 _L_(6)
+#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
+#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12)
+#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6 _L_(5)
+#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7 _L_(6)
+#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
+#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
+#define MUX_PC13G_TCC1_WO7 _L_(6)
+#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
+#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13)
+#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7 _L_(5)
+#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0 _L_(4)
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0 _L_(4)
+#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0 _L_(4)
+#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
+#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1 _L_(4)
+#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
+#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1 _L_(4)
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1 _L_(4)
+#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 _L_(4)
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 _L_(4)
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 _L_(4)
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 _L_(4)
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
+/* ========== PORT definition for TAL peripheral ========== */
+#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */
+#define MUX_PA27H_TAL_BRK _L_(7)
+#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK)
+#define PORT_PA27H_TAL_BRK (_UL_(1) << 27)
+#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */
+#define MUX_PB31H_TAL_BRK _L_(7)
+#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK)
+#define PORT_PB31H_TAL_BRK (_UL_(1) << 31)
+/* ========== PORT definition for CAN0 peripheral ========== */
+#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */
+#define MUX_PA23I_CAN0_RX _L_(8)
+#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX)
+#define PORT_PA23I_CAN0_RX (_UL_(1) << 23)
+#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */
+#define MUX_PA25I_CAN0_RX _L_(8)
+#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX)
+#define PORT_PA25I_CAN0_RX (_UL_(1) << 25)
+#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */
+#define MUX_PA22I_CAN0_TX _L_(8)
+#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX)
+#define PORT_PA22I_CAN0_TX (_UL_(1) << 22)
+#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */
+#define MUX_PA24I_CAN0_TX _L_(8)
+#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX)
+#define PORT_PA24I_CAN0_TX (_UL_(1) << 24)
+/* ========== PORT definition for CAN1 peripheral ========== */
+#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */
+#define MUX_PB13H_CAN1_RX _L_(7)
+#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX)
+#define PORT_PB13H_CAN1_RX (_UL_(1) << 13)
+#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */
+#define MUX_PB15H_CAN1_RX _L_(7)
+#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX)
+#define PORT_PB15H_CAN1_RX (_UL_(1) << 15)
+#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */
+#define MUX_PB12H_CAN1_TX _L_(7)
+#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX)
+#define PORT_PB12H_CAN1_TX (_UL_(1) << 12)
+#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */
+#define MUX_PB14H_CAN1_TX _L_(7)
+#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX)
+#define PORT_PB14H_CAN1_TX (_UL_(1) << 14)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
+#define MUX_PC21L_GMAC_GCOL _L_(11)
+#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
+#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21)
+#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14)
+#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
+#define MUX_PC11L_GMAC_GMDC _L_(11)
+#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
+#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11)
+#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15)
+#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
+#define MUX_PC12L_GMAC_GMDIO _L_(11)
+#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
+#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12)
+#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0 _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1 _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12)
+#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
+#define MUX_PC15L_GMAC_GRX2 _L_(11)
+#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
+#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15)
+#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
+#define MUX_PC14L_GMAC_GRX3 _L_(11)
+#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
+#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14)
+#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
+#define MUX_PC18L_GMAC_GRXCK _L_(11)
+#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
+#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18)
+#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
+#define MUX_PC20L_GMAC_GRXDV _L_(11)
+#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
+#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20)
+#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0 _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1 _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19)
+#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
+#define MUX_PC16L_GMAC_GTX2 _L_(11)
+#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
+#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16)
+#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
+#define MUX_PC17L_GMAC_GTX3 _L_(11)
+#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
+#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17)
+#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17)
+#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
+#define MUX_PC19L_GMAC_GTXER _L_(11)
+#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
+#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0 _L_(5)
+#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0 _L_(5)
+#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1 _L_(5)
+#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1 _L_(5)
+#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2 _L_(5)
+#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2 _L_(5)
+#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0 _L_(5)
+#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0 _L_(5)
+#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1 _L_(5)
+#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1 _L_(5)
+#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 _L_(4)
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 _L_(4)
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
+#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 _L_(4)
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 _L_(4)
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 _L_(4)
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
+#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 _L_(4)
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 _L_(4)
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 _L_(4)
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 _L_(4)
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 _L_(4)
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 _L_(4)
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 _L_(4)
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
+#define MUX_PB18G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
+#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18)
+#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
+#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
+#define MUX_PC16G_PDEC_QDI0 _L_(6)
+#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
+#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16)
+#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0 _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
+#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
+#define MUX_PB19G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
+#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19)
+#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
+#define MUX_PB24G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
+#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24)
+#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
+#define MUX_PC17G_PDEC_QDI1 _L_(6)
+#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
+#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17)
+#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1 _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
+#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
+#define MUX_PB20G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
+#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20)
+#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
+#define MUX_PB25G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
+#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25)
+#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
+#define MUX_PC18G_PDEC_QDI2 _L_(6)
+#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
+#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18)
+#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 _L_(1)
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
+#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 _L_(1)
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
+#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 _L_(1)
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
+#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 _L_(1)
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
+#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0 _L_(12)
+#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0 _L_(12)
+#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
+#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
+#define MUX_PB24M_AC_CMP0 _L_(12)
+#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
+#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24)
+#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1 _L_(12)
+#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1 _L_(12)
+#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
+#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
+#define MUX_PB25M_AC_CMP1 _L_(12)
+#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
+#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS _L_(7)
+#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0 _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
+#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1 _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
+#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2 _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3 _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK _L_(7)
+#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0 _L_(13)
+#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
+#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0 _L_(13)
+#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0 _L_(13)
+#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1 _L_(13)
+#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
+#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1 _L_(13)
+#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1 _L_(13)
+#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
+#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2 _L_(13)
+#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
+#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2 _L_(13)
+#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2 _L_(13)
+#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
+#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3 _L_(13)
+#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
+#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3 _L_(13)
+#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4 _L_(13)
+#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
+#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
+#define MUX_PC27N_CCL_IN4 _L_(13)
+#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
+#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27)
+#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5 _L_(13)
+#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
+#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
+#define MUX_PC28N_CCL_IN5 _L_(13)
+#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
+#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28)
+#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6 _L_(13)
+#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6 _L_(13)
+#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
+#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7 _L_(13)
+#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7 _L_(13)
+#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
+#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8 _L_(13)
+#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8 _L_(13)
+#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
+#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9 _L_(13)
+#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
+#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
+#define MUX_PC20N_CCL_IN9 _L_(13)
+#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
+#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20)
+#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10 _L_(13)
+#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
+#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
+#define MUX_PC21N_CCL_IN10 _L_(13)
+#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
+#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21)
+#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11 _L_(13)
+#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11 _L_(13)
+#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0 _L_(13)
+#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
+#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0 _L_(13)
+#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0 _L_(13)
+#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
+#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0 _L_(13)
+#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1 _L_(13)
+#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1 _L_(13)
+#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1 _L_(13)
+#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2 _L_(13)
+#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2 _L_(13)
+#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
+#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3 _L_(13)
+#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
+#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
+#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
+#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
+#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
+#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
+#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18)
+#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
+#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
+#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM6 peripheral ========== */
+#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
+#define MUX_PC13D_SERCOM6_PAD0 _L_(3)
+#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
+#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13)
+#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
+#define MUX_PC16C_SERCOM6_PAD0 _L_(2)
+#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
+#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16)
+#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
+#define MUX_PC12D_SERCOM6_PAD1 _L_(3)
+#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
+#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12)
+#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
+#define MUX_PC05C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
+#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5)
+#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
+#define MUX_PC17C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
+#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17)
+#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
+#define MUX_PC14D_SERCOM6_PAD2 _L_(3)
+#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
+#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14)
+#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
+#define MUX_PC06C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
+#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6)
+#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
+#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10)
+#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
+#define MUX_PC18C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
+#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18)
+#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
+#define MUX_PC15D_SERCOM6_PAD3 _L_(3)
+#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
+#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15)
+#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
+#define MUX_PC07C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
+#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7)
+#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
+#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11)
+#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
+#define MUX_PC19C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
+#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM7 peripheral ========== */
+#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
+#define MUX_PB21D_SERCOM7_PAD0 _L_(3)
+#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
+#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21)
+#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
+#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30)
+#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
+#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12)
+#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
+#define MUX_PB20D_SERCOM7_PAD1 _L_(3)
+#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
+#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20)
+#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
+#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31)
+#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
+#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13)
+#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
+#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18)
+#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
+#define MUX_PC10D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
+#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10)
+#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
+#define MUX_PC14C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
+#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14)
+#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
+#define MUX_PA30C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
+#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30)
+#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
+#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19)
+#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
+#define MUX_PC11D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
+#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11)
+#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
+#define MUX_PC15C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
+#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15)
+#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
+#define MUX_PA31C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
+#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0 _L_(5)
+#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0 _L_(5)
+#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1 _L_(5)
+#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1 _L_(5)
+#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TC6_WO0 _L_(4)
+#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
+#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30)
+#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 _L_(4)
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2)
+#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 _L_(4)
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16)
+#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TC6_WO1 _L_(4)
+#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
+#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31)
+#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 _L_(4)
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3)
+#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 _L_(4)
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 _L_(4)
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20)
+#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 _L_(4)
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0)
+#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 _L_(4)
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22)
+#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 _L_(4)
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21)
+#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 _L_(4)
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1)
+#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 _L_(4)
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0 _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
+#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1 _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2 _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3 _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4 _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
+#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5 _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
+#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6 _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7 _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8 _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9 _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10 _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11 _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12 _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13 _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
+#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14 _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15 _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
+#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0 _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
+#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1 _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
+#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2 _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
+#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3 _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
+#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4 _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
+#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5 _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
+#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6 _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
+#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7 _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
+#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8 _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9 _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10 _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11 _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12 _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13 _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14 _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15 _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16 _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17 _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18 _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19 _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20 _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
+#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21 _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
+#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22 _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
+#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23 _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
+#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24 _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
+#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25 _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
+#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26 _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27 _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28 _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29 _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30 _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
+#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31 _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
+#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0 _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1 _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2 _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3 _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
+#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4 _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5 _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6 _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7 _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8 _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9 _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10 _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11 _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
+#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13 _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14 _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15 _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16 _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17 _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18 _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19 _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20 _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21 _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
+#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22 _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
+#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23 _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
+#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24 _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
+#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25 _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
+#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26 _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27 _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28 _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29 _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30 _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31 _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0 _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
+#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1 _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
+#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2 _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
+#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3 _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
+#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
+#define MUX_PC02B_ADC1_AIN4 _L_(1)
+#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
+#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2)
+#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
+#define MUX_PC03B_ADC1_AIN5 _L_(1)
+#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
+#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3)
+#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6 _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
+#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7 _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
+#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8 _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
+#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9 _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
+#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
+#define MUX_PC00B_ADC1_AIN10 _L_(1)
+#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
+#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0)
+#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
+#define MUX_PC01B_ADC1_AIN11 _L_(1)
+#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
+#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0 _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
+#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1 _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0 _L_(9)
+#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
+#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0 _L_(9)
+#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1 _L_(9)
+#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1 _L_(9)
+#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0 _L_(9)
+#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
+#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0 _L_(9)
+#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1 _L_(9)
+#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0 _L_(9)
+#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0 _L_(9)
+#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1 _L_(9)
+#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI _L_(9)
+#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI _L_(9)
+#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO _L_(9)
+#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO _L_(9)
+#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK _L_(10)
+#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0 _L_(10)
+#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1 _L_(10)
+#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2 _L_(10)
+#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3 _L_(10)
+#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4 _L_(10)
+#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5 _L_(10)
+#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6 _L_(10)
+#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7 _L_(10)
+#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8 _L_(10)
+#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9 _L_(10)
+#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
+#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
+#define MUX_PC12K_PCC_DATA10 _L_(10)
+#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
+#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12)
+#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
+#define MUX_PC13K_PCC_DATA11 _L_(10)
+#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
+#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13)
+#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
+#define MUX_PC14K_PCC_DATA12 _L_(10)
+#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
+#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14)
+#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
+#define MUX_PC15K_PCC_DATA13 _L_(10)
+#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
+#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1 _L_(10)
+#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2 _L_(10)
+#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
+#define MUX_PC06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
+#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
+#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
+#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
+#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
+#define MUX_PC07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
+#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7)
+/* ========== PORT definition for SDHC1 peripheral ========== */
+#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
+#define MUX_PB16I_SDHC1_SDCD _L_(8)
+#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
+#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16)
+#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
+#define MUX_PC20I_SDHC1_SDCD _L_(8)
+#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
+#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20)
+#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
+#define MUX_PA21I_SDHC1_SDCK _L_(8)
+#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
+#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21)
+#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
+#define MUX_PA20I_SDHC1_SDCMD _L_(8)
+#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
+#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20)
+#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
+#define MUX_PB18I_SDHC1_SDDAT0 _L_(8)
+#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
+#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18)
+#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
+#define MUX_PB19I_SDHC1_SDDAT1 _L_(8)
+#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
+#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19)
+#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
+#define MUX_PB20I_SDHC1_SDDAT2 _L_(8)
+#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
+#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20)
+#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
+#define MUX_PB21I_SDHC1_SDDAT3 _L_(8)
+#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
+#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21)
+#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
+#define MUX_PB17I_SDHC1_SDWP _L_(8)
+#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
+#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17)
+#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
+#define MUX_PC21I_SDHC1_SDWP _L_(8)
+#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
+#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21)
+
+#endif /* _SAME54N20A_PIO_ */
diff --git a/GPIO/ATSAME54/include/pio/same54p19a.h b/GPIO/ATSAME54/include/pio/same54p19a.h
new file mode 100644
index 0000000..844ca8c
--- /dev/null
+++ b/GPIO/ATSAME54/include/pio/same54p19a.h
@@ -0,0 +1,3015 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME54P19A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54P19A_PIO_
+#define _SAME54P19A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB18 50 /**< \brief Pin Number for PB18 */
+#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */
+#define PIN_PB19 51 /**< \brief Pin Number for PB19 */
+#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */
+#define PIN_PB20 52 /**< \brief Pin Number for PB20 */
+#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */
+#define PIN_PB21 53 /**< \brief Pin Number for PB21 */
+#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB24 56 /**< \brief Pin Number for PB24 */
+#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */
+#define PIN_PB25 57 /**< \brief Pin Number for PB25 */
+#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */
+#define PIN_PB26 58 /**< \brief Pin Number for PB26 */
+#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */
+#define PIN_PB27 59 /**< \brief Pin Number for PB27 */
+#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */
+#define PIN_PB28 60 /**< \brief Pin Number for PB28 */
+#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */
+#define PIN_PB29 61 /**< \brief Pin Number for PB29 */
+#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */
+#define PIN_PC00 64 /**< \brief Pin Number for PC00 */
+#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */
+#define PIN_PC01 65 /**< \brief Pin Number for PC01 */
+#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */
+#define PIN_PC02 66 /**< \brief Pin Number for PC02 */
+#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */
+#define PIN_PC03 67 /**< \brief Pin Number for PC03 */
+#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */
+#define PIN_PC04 68 /**< \brief Pin Number for PC04 */
+#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */
+#define PIN_PC05 69 /**< \brief Pin Number for PC05 */
+#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */
+#define PIN_PC06 70 /**< \brief Pin Number for PC06 */
+#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */
+#define PIN_PC07 71 /**< \brief Pin Number for PC07 */
+#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */
+#define PIN_PC10 74 /**< \brief Pin Number for PC10 */
+#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */
+#define PIN_PC11 75 /**< \brief Pin Number for PC11 */
+#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */
+#define PIN_PC12 76 /**< \brief Pin Number for PC12 */
+#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */
+#define PIN_PC13 77 /**< \brief Pin Number for PC13 */
+#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */
+#define PIN_PC14 78 /**< \brief Pin Number for PC14 */
+#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */
+#define PIN_PC15 79 /**< \brief Pin Number for PC15 */
+#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */
+#define PIN_PC16 80 /**< \brief Pin Number for PC16 */
+#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */
+#define PIN_PC17 81 /**< \brief Pin Number for PC17 */
+#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */
+#define PIN_PC18 82 /**< \brief Pin Number for PC18 */
+#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */
+#define PIN_PC19 83 /**< \brief Pin Number for PC19 */
+#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */
+#define PIN_PC20 84 /**< \brief Pin Number for PC20 */
+#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */
+#define PIN_PC21 85 /**< \brief Pin Number for PC21 */
+#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */
+#define PIN_PC22 86 /**< \brief Pin Number for PC22 */
+#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */
+#define PIN_PC23 87 /**< \brief Pin Number for PC23 */
+#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */
+#define PIN_PC24 88 /**< \brief Pin Number for PC24 */
+#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */
+#define PIN_PC25 89 /**< \brief Pin Number for PC25 */
+#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */
+#define PIN_PC26 90 /**< \brief Pin Number for PC26 */
+#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */
+#define PIN_PC27 91 /**< \brief Pin Number for PC27 */
+#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */
+#define PIN_PC28 92 /**< \brief Pin Number for PC28 */
+#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */
+#define PIN_PC30 94 /**< \brief Pin Number for PC30 */
+#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */
+#define PIN_PC31 95 /**< \brief Pin Number for PC31 */
+#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */
+#define PIN_PD00 96 /**< \brief Pin Number for PD00 */
+#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */
+#define PIN_PD01 97 /**< \brief Pin Number for PD01 */
+#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */
+#define PIN_PD08 104 /**< \brief Pin Number for PD08 */
+#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */
+#define PIN_PD09 105 /**< \brief Pin Number for PD09 */
+#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */
+#define PIN_PD10 106 /**< \brief Pin Number for PD10 */
+#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */
+#define PIN_PD11 107 /**< \brief Pin Number for PD11 */
+#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */
+#define PIN_PD12 108 /**< \brief Pin Number for PD12 */
+#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */
+#define PIN_PD20 116 /**< \brief Pin Number for PD20 */
+#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */
+#define PIN_PD21 117 /**< \brief Pin Number for PD21 */
+#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
+#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
+#define MUX_PC27M_CM4_SWO _L_(12)
+#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
+#define PORT_PC27M_CM4_SWO (_UL_(1) << 27)
+#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO _L_(7)
+#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
+#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
+#define MUX_PC27H_CM4_TRACECLK _L_(7)
+#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
+#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27)
+#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
+#define MUX_PC28H_CM4_TRACEDATA0 _L_(7)
+#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
+#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28)
+#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
+#define MUX_PC26H_CM4_TRACEDATA1 _L_(7)
+#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
+#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26)
+#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
+#define MUX_PC25H_CM4_TRACEDATA2 _L_(7)
+#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
+#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25)
+#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
+#define MUX_PC24H_CM4_TRACEDATA3 _L_(7)
+#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
+#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0 _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
+#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1 _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
+#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2 _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0 _L_(12)
+#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0 _L_(12)
+#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0 _L_(12)
+#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0 _L_(12)
+#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1 _L_(12)
+#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1 _L_(12)
+#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1 _L_(12)
+#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1 _L_(12)
+#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2 _L_(12)
+#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2 _L_(12)
+#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3 _L_(12)
+#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3 _L_(12)
+#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4 _L_(12)
+#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4 _L_(12)
+#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
+#define MUX_PB18M_GCLK_IO4 _L_(12)
+#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
+#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18)
+#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5 _L_(12)
+#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5 _L_(12)
+#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
+#define MUX_PB19M_GCLK_IO5 _L_(12)
+#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
+#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19)
+#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6 _L_(12)
+#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
+#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
+#define MUX_PB20M_GCLK_IO6 _L_(12)
+#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
+#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20)
+#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7 _L_(12)
+#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
+#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
+#define MUX_PB21M_GCLK_IO7 _L_(12)
+#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
+#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
+#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
+#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */
+#define MUX_PD00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0)
+#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
+#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
+#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */
+#define MUX_PD01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1)
+#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
+#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
+#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
+#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
+#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
+#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */
+#define MUX_PD08A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3)
+#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8)
+#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
+#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */
+#define MUX_PC04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4)
+#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */
+#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
+#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
+#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */
+#define MUX_PD09A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4)
+#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9)
+#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
+#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
+#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
+#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
+#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */
+#define MUX_PD10A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5)
+#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10)
+#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
+#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */
+#define MUX_PC22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6)
+#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */
+#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */
+#define MUX_PD11A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6)
+#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11)
+#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */
+#define MUX_PC23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7)
+#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */
+#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */
+#define MUX_PD12A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7)
+#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12)
+#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
+#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
+#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
+#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
+#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
+#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7)
+#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
+#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
+#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
+#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
+#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26)
+#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
+#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */
+#define MUX_PD20A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10)
+#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20)
+#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
+#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
+#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
+#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */
+#define MUX_PD21A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11)
+#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21)
+#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */
+#define MUX_PB26A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12)
+#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26)
+#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */
+#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
+#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
+#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28)
+#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */
+#define MUX_PB27A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13)
+#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27)
+#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */
+#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */
+#define MUX_PB28A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14)
+#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28)
+#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
+#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */
+#define MUX_PC30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14)
+#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */
+#define MUX_PB29A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15)
+#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29)
+#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
+#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */
+#define MUX_PC31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15)
+#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI _L_(0)
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
+#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
+#define MUX_PC17D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
+#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17)
+#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
+#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24)
+#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
+#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
+#define MUX_PC16D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
+#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16)
+#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
+#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25)
+#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
+#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
+#define MUX_PC18D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
+#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18)
+#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
+#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24)
+#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
+#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
+#define MUX_PC19D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
+#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19)
+#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
+#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
+#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
+#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */
+#define MUX_PC22C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0)
+#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22)
+#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
+#define MUX_PC27C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
+#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27)
+#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
+#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
+#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */
+#define MUX_PC23C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1)
+#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23)
+#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
+#define MUX_PC28C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
+#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28)
+#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
+#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */
+#define MUX_PD20C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2)
+#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20)
+#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
+#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */
+#define MUX_PD21C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3)
+#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0 _L_(4)
+#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
+#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0 _L_(4)
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
+#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0 _L_(4)
+#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1 _L_(4)
+#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
+#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1 _L_(4)
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
+#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1 _L_(4)
+#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0 _L_(4)
+#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
+#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0 _L_(4)
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1 _L_(4)
+#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
+#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1 _L_(4)
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM _L_(7)
+#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP _L_(7)
+#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
+#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
+#define MUX_PB25D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
+#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25)
+#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
+#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */
+#define MUX_PB26C_SERCOM2_PAD0 _L_(2)
+#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0)
+#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26)
+#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
+#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
+#define MUX_PB24D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
+#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24)
+#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
+#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */
+#define MUX_PB27C_SERCOM2_PAD1 _L_(2)
+#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1)
+#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27)
+#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
+#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
+#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24)
+#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */
+#define MUX_PB28C_SERCOM2_PAD2 _L_(2)
+#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2)
+#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28)
+#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
+#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
+#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25)
+#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */
+#define MUX_PB29C_SERCOM2_PAD3 _L_(2)
+#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3)
+#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29)
+#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0 _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
+#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */
+#define MUX_PC23D_SERCOM3_PAD0 _L_(3)
+#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0)
+#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23)
+#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
+#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20)
+#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1 _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
+#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */
+#define MUX_PC22D_SERCOM3_PAD1 _L_(3)
+#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1)
+#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22)
+#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
+#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21)
+#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
+#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */
+#define MUX_PD20D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2)
+#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
+#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */
+#define MUX_PD21D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3)
+#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0 _L_(6)
+#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0 _L_(6)
+#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0 _L_(5)
+#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
+#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */
+#define MUX_PC04F_TCC0_WO0 _L_(5)
+#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0)
+#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4)
+#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
+#define MUX_PC10F_TCC0_WO0 _L_(5)
+#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
+#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10)
+#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
+#define MUX_PC16F_TCC0_WO0 _L_(5)
+#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
+#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16)
+#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1 _L_(6)
+#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1 _L_(6)
+#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1 _L_(5)
+#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
+#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
+#define MUX_PC11F_TCC0_WO1 _L_(5)
+#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
+#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11)
+#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
+#define MUX_PC17F_TCC0_WO1 _L_(5)
+#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
+#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17)
+#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */
+#define MUX_PD08F_TCC0_WO1 _L_(5)
+#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1)
+#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8)
+#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2 _L_(6)
+#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2 _L_(6)
+#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 _L_(5)
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
+#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
+#define MUX_PC12F_TCC0_WO2 _L_(5)
+#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
+#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12)
+#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
+#define MUX_PC18F_TCC0_WO2 _L_(5)
+#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
+#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18)
+#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */
+#define MUX_PD09F_TCC0_WO2 _L_(5)
+#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2)
+#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9)
+#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3 _L_(6)
+#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3 _L_(6)
+#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 _L_(5)
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
+#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
+#define MUX_PC13F_TCC0_WO3 _L_(5)
+#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
+#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13)
+#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
+#define MUX_PC19F_TCC0_WO3 _L_(5)
+#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
+#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19)
+#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */
+#define MUX_PD10F_TCC0_WO3 _L_(5)
+#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3)
+#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10)
+#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4 _L_(6)
+#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4 _L_(6)
+#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 _L_(5)
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
+#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
+#define MUX_PC14F_TCC0_WO4 _L_(5)
+#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
+#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14)
+#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
+#define MUX_PC20F_TCC0_WO4 _L_(5)
+#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
+#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20)
+#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */
+#define MUX_PD11F_TCC0_WO4 _L_(5)
+#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4)
+#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11)
+#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5 _L_(6)
+#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5 _L_(6)
+#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 _L_(5)
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
+#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
+#define MUX_PC15F_TCC0_WO5 _L_(5)
+#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
+#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15)
+#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
+#define MUX_PC21F_TCC0_WO5 _L_(5)
+#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
+#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21)
+#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */
+#define MUX_PD12F_TCC0_WO5 _L_(5)
+#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5)
+#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12)
+#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6 _L_(6)
+#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6 _L_(6)
+#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 _L_(5)
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
+#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */
+#define MUX_PC22F_TCC0_WO6 _L_(5)
+#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6)
+#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22)
+#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7 _L_(6)
+#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7 _L_(6)
+#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 _L_(5)
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
+#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */
+#define MUX_PC23F_TCC0_WO7 _L_(5)
+#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7)
+#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0 _L_(6)
+#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
+#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
+#define MUX_PC14G_TCC1_WO0 _L_(6)
+#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
+#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14)
+#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0 _L_(5)
+#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
+#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC1_WO0 _L_(5)
+#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
+#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18)
+#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */
+#define MUX_PD20F_TCC1_WO0 _L_(5)
+#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0)
+#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20)
+#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1 _L_(6)
+#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
+#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
+#define MUX_PC15G_TCC1_WO1 _L_(6)
+#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
+#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15)
+#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1 _L_(5)
+#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
+#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC1_WO1 _L_(5)
+#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
+#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19)
+#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */
+#define MUX_PD21F_TCC1_WO1 _L_(5)
+#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1)
+#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21)
+#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2 _L_(6)
+#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2 _L_(6)
+#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2 _L_(5)
+#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
+#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC1_WO2 _L_(5)
+#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
+#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20)
+#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */
+#define MUX_PB26F_TCC1_WO2 _L_(5)
+#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2)
+#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26)
+#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3 _L_(6)
+#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3 _L_(6)
+#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3 _L_(5)
+#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
+#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC1_WO3 _L_(5)
+#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
+#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21)
+#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */
+#define MUX_PB27F_TCC1_WO3 _L_(5)
+#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3)
+#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27)
+#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4 _L_(6)
+#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
+#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
+#define MUX_PC10G_TCC1_WO4 _L_(6)
+#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
+#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10)
+#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4 _L_(5)
+#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
+#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */
+#define MUX_PB28F_TCC1_WO4 _L_(5)
+#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4)
+#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28)
+#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5 _L_(6)
+#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
+#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
+#define MUX_PC11G_TCC1_WO5 _L_(6)
+#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
+#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11)
+#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5 _L_(5)
+#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
+#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */
+#define MUX_PB29F_TCC1_WO5 _L_(5)
+#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5)
+#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29)
+#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6 _L_(6)
+#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
+#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
+#define MUX_PC12G_TCC1_WO6 _L_(6)
+#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
+#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12)
+#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6 _L_(5)
+#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7 _L_(6)
+#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
+#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
+#define MUX_PC13G_TCC1_WO7 _L_(6)
+#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
+#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13)
+#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7 _L_(5)
+#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0 _L_(4)
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0 _L_(4)
+#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0 _L_(4)
+#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
+#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1 _L_(4)
+#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
+#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1 _L_(4)
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1 _L_(4)
+#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 _L_(4)
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 _L_(4)
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 _L_(4)
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 _L_(4)
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
+/* ========== PORT definition for TAL peripheral ========== */
+#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */
+#define MUX_PA27H_TAL_BRK _L_(7)
+#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK)
+#define PORT_PA27H_TAL_BRK (_UL_(1) << 27)
+#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */
+#define MUX_PB31H_TAL_BRK _L_(7)
+#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK)
+#define PORT_PB31H_TAL_BRK (_UL_(1) << 31)
+/* ========== PORT definition for CAN0 peripheral ========== */
+#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */
+#define MUX_PA23I_CAN0_RX _L_(8)
+#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX)
+#define PORT_PA23I_CAN0_RX (_UL_(1) << 23)
+#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */
+#define MUX_PA25I_CAN0_RX _L_(8)
+#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX)
+#define PORT_PA25I_CAN0_RX (_UL_(1) << 25)
+#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */
+#define MUX_PA22I_CAN0_TX _L_(8)
+#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX)
+#define PORT_PA22I_CAN0_TX (_UL_(1) << 22)
+#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */
+#define MUX_PA24I_CAN0_TX _L_(8)
+#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX)
+#define PORT_PA24I_CAN0_TX (_UL_(1) << 24)
+/* ========== PORT definition for CAN1 peripheral ========== */
+#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */
+#define MUX_PB13H_CAN1_RX _L_(7)
+#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX)
+#define PORT_PB13H_CAN1_RX (_UL_(1) << 13)
+#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */
+#define MUX_PB15H_CAN1_RX _L_(7)
+#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX)
+#define PORT_PB15H_CAN1_RX (_UL_(1) << 15)
+#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */
+#define MUX_PB12H_CAN1_TX _L_(7)
+#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX)
+#define PORT_PB12H_CAN1_TX (_UL_(1) << 12)
+#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */
+#define MUX_PB14H_CAN1_TX _L_(7)
+#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX)
+#define PORT_PB14H_CAN1_TX (_UL_(1) << 14)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
+#define MUX_PC21L_GMAC_GCOL _L_(11)
+#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
+#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21)
+#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14)
+#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
+#define MUX_PC11L_GMAC_GMDC _L_(11)
+#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
+#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11)
+#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */
+#define MUX_PC22L_GMAC_GMDC _L_(11)
+#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC)
+#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22)
+#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15)
+#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
+#define MUX_PC12L_GMAC_GMDIO _L_(11)
+#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
+#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12)
+#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */
+#define MUX_PC23L_GMAC_GMDIO _L_(11)
+#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO)
+#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23)
+#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0 _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1 _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12)
+#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
+#define MUX_PC15L_GMAC_GRX2 _L_(11)
+#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
+#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15)
+#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
+#define MUX_PC14L_GMAC_GRX3 _L_(11)
+#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
+#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14)
+#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
+#define MUX_PC18L_GMAC_GRXCK _L_(11)
+#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
+#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18)
+#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
+#define MUX_PC20L_GMAC_GRXDV _L_(11)
+#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
+#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20)
+#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0 _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1 _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19)
+#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
+#define MUX_PC16L_GMAC_GTX2 _L_(11)
+#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
+#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16)
+#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
+#define MUX_PC17L_GMAC_GTX3 _L_(11)
+#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
+#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17)
+#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17)
+#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
+#define MUX_PC19L_GMAC_GTXER _L_(11)
+#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
+#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0 _L_(5)
+#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0 _L_(5)
+#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1 _L_(5)
+#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1 _L_(5)
+#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2 _L_(5)
+#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2 _L_(5)
+#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0 _L_(5)
+#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0 _L_(5)
+#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1 _L_(5)
+#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1 _L_(5)
+#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 _L_(4)
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 _L_(4)
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
+#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 _L_(4)
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 _L_(4)
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 _L_(4)
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
+#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 _L_(4)
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 _L_(4)
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 _L_(4)
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 _L_(4)
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 _L_(4)
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 _L_(4)
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 _L_(4)
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
+#define MUX_PB18G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
+#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18)
+#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
+#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
+#define MUX_PC16G_PDEC_QDI0 _L_(6)
+#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
+#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16)
+#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0 _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
+#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
+#define MUX_PB19G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
+#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19)
+#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
+#define MUX_PB24G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
+#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24)
+#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
+#define MUX_PC17G_PDEC_QDI1 _L_(6)
+#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
+#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17)
+#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1 _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
+#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
+#define MUX_PB20G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
+#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20)
+#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
+#define MUX_PB25G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
+#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25)
+#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
+#define MUX_PC18G_PDEC_QDI2 _L_(6)
+#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
+#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18)
+#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 _L_(1)
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
+#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 _L_(1)
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
+#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 _L_(1)
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
+#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 _L_(1)
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
+#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0 _L_(12)
+#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0 _L_(12)
+#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
+#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
+#define MUX_PB24M_AC_CMP0 _L_(12)
+#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
+#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24)
+#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1 _L_(12)
+#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1 _L_(12)
+#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
+#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
+#define MUX_PB25M_AC_CMP1 _L_(12)
+#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
+#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS _L_(7)
+#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0 _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
+#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1 _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
+#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2 _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3 _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK _L_(7)
+#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0 _L_(13)
+#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
+#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0 _L_(13)
+#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0 _L_(13)
+#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1 _L_(13)
+#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
+#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1 _L_(13)
+#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1 _L_(13)
+#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
+#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2 _L_(13)
+#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
+#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2 _L_(13)
+#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2 _L_(13)
+#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
+#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3 _L_(13)
+#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
+#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3 _L_(13)
+#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4 _L_(13)
+#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
+#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
+#define MUX_PC27N_CCL_IN4 _L_(13)
+#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
+#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27)
+#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5 _L_(13)
+#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
+#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
+#define MUX_PC28N_CCL_IN5 _L_(13)
+#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
+#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28)
+#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6 _L_(13)
+#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6 _L_(13)
+#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
+#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7 _L_(13)
+#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7 _L_(13)
+#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
+#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8 _L_(13)
+#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8 _L_(13)
+#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
+#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9 _L_(13)
+#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
+#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
+#define MUX_PC20N_CCL_IN9 _L_(13)
+#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
+#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20)
+#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10 _L_(13)
+#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
+#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
+#define MUX_PC21N_CCL_IN10 _L_(13)
+#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
+#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21)
+#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11 _L_(13)
+#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11 _L_(13)
+#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0 _L_(13)
+#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
+#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0 _L_(13)
+#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0 _L_(13)
+#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
+#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0 _L_(13)
+#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1 _L_(13)
+#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1 _L_(13)
+#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1 _L_(13)
+#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2 _L_(13)
+#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2 _L_(13)
+#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
+#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3 _L_(13)
+#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
+#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */
+#define MUX_PB27D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0)
+#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27)
+#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
+#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */
+#define MUX_PB26D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1)
+#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26)
+#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
+#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */
+#define MUX_PB28D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2)
+#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28)
+#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
+#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */
+#define MUX_PB29D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3)
+#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29)
+#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
+#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
+#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
+#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
+#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18)
+#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
+#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
+#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM6 peripheral ========== */
+#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */
+#define MUX_PD09D_SERCOM6_PAD0 _L_(3)
+#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0)
+#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9)
+#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
+#define MUX_PC13D_SERCOM6_PAD0 _L_(3)
+#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
+#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13)
+#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */
+#define MUX_PC04C_SERCOM6_PAD0 _L_(2)
+#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0)
+#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4)
+#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
+#define MUX_PC16C_SERCOM6_PAD0 _L_(2)
+#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
+#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16)
+#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */
+#define MUX_PD08D_SERCOM6_PAD1 _L_(3)
+#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1)
+#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8)
+#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
+#define MUX_PC12D_SERCOM6_PAD1 _L_(3)
+#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
+#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12)
+#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
+#define MUX_PC05C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
+#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5)
+#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
+#define MUX_PC17C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
+#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17)
+#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
+#define MUX_PC14D_SERCOM6_PAD2 _L_(3)
+#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
+#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14)
+#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */
+#define MUX_PD10D_SERCOM6_PAD2 _L_(3)
+#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2)
+#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10)
+#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
+#define MUX_PC06C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
+#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6)
+#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
+#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10)
+#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
+#define MUX_PC18C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
+#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18)
+#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
+#define MUX_PC15D_SERCOM6_PAD3 _L_(3)
+#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
+#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15)
+#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */
+#define MUX_PD11D_SERCOM6_PAD3 _L_(3)
+#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3)
+#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11)
+#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
+#define MUX_PC07C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
+#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7)
+#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
+#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11)
+#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
+#define MUX_PC19C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
+#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM7 peripheral ========== */
+#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
+#define MUX_PB21D_SERCOM7_PAD0 _L_(3)
+#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
+#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21)
+#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */
+#define MUX_PD08C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0)
+#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8)
+#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
+#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30)
+#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
+#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12)
+#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
+#define MUX_PB20D_SERCOM7_PAD1 _L_(3)
+#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
+#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20)
+#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */
+#define MUX_PD09C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1)
+#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9)
+#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
+#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31)
+#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
+#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13)
+#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
+#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18)
+#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
+#define MUX_PC10D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
+#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10)
+#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
+#define MUX_PC14C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
+#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14)
+#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */
+#define MUX_PD10C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2)
+#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10)
+#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
+#define MUX_PA30C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
+#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30)
+#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
+#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19)
+#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
+#define MUX_PC11D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
+#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11)
+#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
+#define MUX_PC15C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
+#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15)
+#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */
+#define MUX_PD11C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3)
+#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11)
+#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
+#define MUX_PA31C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
+#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0 _L_(5)
+#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0 _L_(5)
+#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1 _L_(5)
+#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1 _L_(5)
+#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TC6_WO0 _L_(4)
+#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
+#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30)
+#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 _L_(4)
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2)
+#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 _L_(4)
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16)
+#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TC6_WO1 _L_(4)
+#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
+#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31)
+#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 _L_(4)
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3)
+#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 _L_(4)
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 _L_(4)
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20)
+#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 _L_(4)
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0)
+#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 _L_(4)
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22)
+#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 _L_(4)
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21)
+#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 _L_(4)
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1)
+#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 _L_(4)
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0 _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
+#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1 _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2 _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3 _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4 _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
+#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5 _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
+#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6 _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7 _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8 _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9 _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10 _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11 _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12 _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13 _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
+#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14 _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15 _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
+#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0 _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
+#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1 _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
+#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2 _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
+#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3 _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
+#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4 _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
+#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5 _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
+#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6 _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
+#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7 _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
+#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8 _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9 _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10 _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11 _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12 _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13 _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14 _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15 _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16 _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17 _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18 _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19 _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20 _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
+#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21 _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
+#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22 _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
+#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23 _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
+#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24 _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
+#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25 _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
+#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26 _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27 _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28 _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29 _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30 _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
+#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31 _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
+#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0 _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1 _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2 _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3 _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
+#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4 _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5 _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6 _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7 _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8 _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9 _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10 _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11 _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
+#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13 _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14 _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15 _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16 _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17 _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18 _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19 _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20 _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21 _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
+#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22 _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
+#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23 _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
+#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24 _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
+#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25 _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
+#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26 _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27 _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28 _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29 _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30 _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31 _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0 _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
+#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1 _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
+#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2 _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
+#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3 _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
+#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
+#define MUX_PC02B_ADC1_AIN4 _L_(1)
+#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
+#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2)
+#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
+#define MUX_PC03B_ADC1_AIN5 _L_(1)
+#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
+#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3)
+#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6 _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
+#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7 _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
+#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8 _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
+#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9 _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
+#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
+#define MUX_PC00B_ADC1_AIN10 _L_(1)
+#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
+#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0)
+#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
+#define MUX_PC01B_ADC1_AIN11 _L_(1)
+#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
+#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1)
+#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */
+#define MUX_PC30B_ADC1_AIN12 _L_(1)
+#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12)
+#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30)
+#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */
+#define MUX_PC31B_ADC1_AIN13 _L_(1)
+#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13)
+#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31)
+#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */
+#define MUX_PD00B_ADC1_AIN14 _L_(1)
+#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14)
+#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0)
+#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */
+#define MUX_PD01B_ADC1_AIN15 _L_(1)
+#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15)
+#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0 _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
+#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1 _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0 _L_(9)
+#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
+#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0 _L_(9)
+#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1 _L_(9)
+#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1 _L_(9)
+#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0 _L_(9)
+#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
+#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0 _L_(9)
+#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
+#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */
+#define MUX_PB29J_I2S_MCK1 _L_(9)
+#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1)
+#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29)
+#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1 _L_(9)
+#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0 _L_(9)
+#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0 _L_(9)
+#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
+#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */
+#define MUX_PB28J_I2S_SCK1 _L_(9)
+#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1)
+#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28)
+#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1 _L_(9)
+#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI _L_(9)
+#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI _L_(9)
+#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO _L_(9)
+#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO _L_(9)
+#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK _L_(10)
+#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0 _L_(10)
+#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1 _L_(10)
+#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2 _L_(10)
+#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3 _L_(10)
+#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4 _L_(10)
+#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5 _L_(10)
+#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6 _L_(10)
+#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7 _L_(10)
+#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8 _L_(10)
+#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9 _L_(10)
+#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
+#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
+#define MUX_PC12K_PCC_DATA10 _L_(10)
+#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
+#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12)
+#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
+#define MUX_PC13K_PCC_DATA11 _L_(10)
+#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
+#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13)
+#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
+#define MUX_PC14K_PCC_DATA12 _L_(10)
+#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
+#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14)
+#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
+#define MUX_PC15K_PCC_DATA13 _L_(10)
+#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
+#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1 _L_(10)
+#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2 _L_(10)
+#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
+#define MUX_PC06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
+#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
+#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
+#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
+#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
+#define MUX_PC07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
+#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7)
+/* ========== PORT definition for SDHC1 peripheral ========== */
+#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
+#define MUX_PB16I_SDHC1_SDCD _L_(8)
+#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
+#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16)
+#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
+#define MUX_PC20I_SDHC1_SDCD _L_(8)
+#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
+#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20)
+#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */
+#define MUX_PD20I_SDHC1_SDCD _L_(8)
+#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD)
+#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20)
+#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
+#define MUX_PA21I_SDHC1_SDCK _L_(8)
+#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
+#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21)
+#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
+#define MUX_PA20I_SDHC1_SDCMD _L_(8)
+#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
+#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20)
+#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
+#define MUX_PB18I_SDHC1_SDDAT0 _L_(8)
+#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
+#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18)
+#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
+#define MUX_PB19I_SDHC1_SDDAT1 _L_(8)
+#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
+#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19)
+#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
+#define MUX_PB20I_SDHC1_SDDAT2 _L_(8)
+#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
+#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20)
+#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
+#define MUX_PB21I_SDHC1_SDDAT3 _L_(8)
+#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
+#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21)
+#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
+#define MUX_PB17I_SDHC1_SDWP _L_(8)
+#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
+#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17)
+#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
+#define MUX_PC21I_SDHC1_SDWP _L_(8)
+#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
+#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21)
+#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */
+#define MUX_PD21I_SDHC1_SDWP _L_(8)
+#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP)
+#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21)
+
+#endif /* _SAME54P19A_PIO_ */
diff --git a/GPIO/ATSAME54/include/pio/same54p20a.h b/GPIO/ATSAME54/include/pio/same54p20a.h
new file mode 100644
index 0000000..d03722d
--- /dev/null
+++ b/GPIO/ATSAME54/include/pio/same54p20a.h
@@ -0,0 +1,3015 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME54P20A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54P20A_PIO_
+#define _SAME54P20A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB18 50 /**< \brief Pin Number for PB18 */
+#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */
+#define PIN_PB19 51 /**< \brief Pin Number for PB19 */
+#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */
+#define PIN_PB20 52 /**< \brief Pin Number for PB20 */
+#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */
+#define PIN_PB21 53 /**< \brief Pin Number for PB21 */
+#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB24 56 /**< \brief Pin Number for PB24 */
+#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */
+#define PIN_PB25 57 /**< \brief Pin Number for PB25 */
+#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */
+#define PIN_PB26 58 /**< \brief Pin Number for PB26 */
+#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */
+#define PIN_PB27 59 /**< \brief Pin Number for PB27 */
+#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */
+#define PIN_PB28 60 /**< \brief Pin Number for PB28 */
+#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */
+#define PIN_PB29 61 /**< \brief Pin Number for PB29 */
+#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */
+#define PIN_PC00 64 /**< \brief Pin Number for PC00 */
+#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */
+#define PIN_PC01 65 /**< \brief Pin Number for PC01 */
+#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */
+#define PIN_PC02 66 /**< \brief Pin Number for PC02 */
+#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */
+#define PIN_PC03 67 /**< \brief Pin Number for PC03 */
+#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */
+#define PIN_PC04 68 /**< \brief Pin Number for PC04 */
+#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */
+#define PIN_PC05 69 /**< \brief Pin Number for PC05 */
+#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */
+#define PIN_PC06 70 /**< \brief Pin Number for PC06 */
+#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */
+#define PIN_PC07 71 /**< \brief Pin Number for PC07 */
+#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */
+#define PIN_PC10 74 /**< \brief Pin Number for PC10 */
+#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */
+#define PIN_PC11 75 /**< \brief Pin Number for PC11 */
+#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */
+#define PIN_PC12 76 /**< \brief Pin Number for PC12 */
+#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */
+#define PIN_PC13 77 /**< \brief Pin Number for PC13 */
+#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */
+#define PIN_PC14 78 /**< \brief Pin Number for PC14 */
+#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */
+#define PIN_PC15 79 /**< \brief Pin Number for PC15 */
+#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */
+#define PIN_PC16 80 /**< \brief Pin Number for PC16 */
+#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */
+#define PIN_PC17 81 /**< \brief Pin Number for PC17 */
+#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */
+#define PIN_PC18 82 /**< \brief Pin Number for PC18 */
+#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */
+#define PIN_PC19 83 /**< \brief Pin Number for PC19 */
+#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */
+#define PIN_PC20 84 /**< \brief Pin Number for PC20 */
+#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */
+#define PIN_PC21 85 /**< \brief Pin Number for PC21 */
+#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */
+#define PIN_PC22 86 /**< \brief Pin Number for PC22 */
+#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */
+#define PIN_PC23 87 /**< \brief Pin Number for PC23 */
+#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */
+#define PIN_PC24 88 /**< \brief Pin Number for PC24 */
+#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */
+#define PIN_PC25 89 /**< \brief Pin Number for PC25 */
+#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */
+#define PIN_PC26 90 /**< \brief Pin Number for PC26 */
+#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */
+#define PIN_PC27 91 /**< \brief Pin Number for PC27 */
+#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */
+#define PIN_PC28 92 /**< \brief Pin Number for PC28 */
+#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */
+#define PIN_PC30 94 /**< \brief Pin Number for PC30 */
+#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */
+#define PIN_PC31 95 /**< \brief Pin Number for PC31 */
+#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */
+#define PIN_PD00 96 /**< \brief Pin Number for PD00 */
+#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */
+#define PIN_PD01 97 /**< \brief Pin Number for PD01 */
+#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */
+#define PIN_PD08 104 /**< \brief Pin Number for PD08 */
+#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */
+#define PIN_PD09 105 /**< \brief Pin Number for PD09 */
+#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */
+#define PIN_PD10 106 /**< \brief Pin Number for PD10 */
+#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */
+#define PIN_PD11 107 /**< \brief Pin Number for PD11 */
+#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */
+#define PIN_PD12 108 /**< \brief Pin Number for PD12 */
+#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */
+#define PIN_PD20 116 /**< \brief Pin Number for PD20 */
+#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */
+#define PIN_PD21 117 /**< \brief Pin Number for PD21 */
+#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
+#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
+#define MUX_PC27M_CM4_SWO _L_(12)
+#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
+#define PORT_PC27M_CM4_SWO (_UL_(1) << 27)
+#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO _L_(7)
+#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
+#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
+#define MUX_PC27H_CM4_TRACECLK _L_(7)
+#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
+#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27)
+#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
+#define MUX_PC28H_CM4_TRACEDATA0 _L_(7)
+#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
+#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28)
+#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
+#define MUX_PC26H_CM4_TRACEDATA1 _L_(7)
+#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
+#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26)
+#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
+#define MUX_PC25H_CM4_TRACEDATA2 _L_(7)
+#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
+#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25)
+#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
+#define MUX_PC24H_CM4_TRACEDATA3 _L_(7)
+#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
+#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0 _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
+#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1 _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
+#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2 _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0 _L_(12)
+#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0 _L_(12)
+#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0 _L_(12)
+#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0 _L_(12)
+#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1 _L_(12)
+#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1 _L_(12)
+#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1 _L_(12)
+#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1 _L_(12)
+#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2 _L_(12)
+#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2 _L_(12)
+#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3 _L_(12)
+#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3 _L_(12)
+#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4 _L_(12)
+#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4 _L_(12)
+#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
+#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
+#define MUX_PB18M_GCLK_IO4 _L_(12)
+#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
+#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18)
+#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5 _L_(12)
+#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5 _L_(12)
+#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
+#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
+#define MUX_PB19M_GCLK_IO5 _L_(12)
+#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
+#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19)
+#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6 _L_(12)
+#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
+#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
+#define MUX_PB20M_GCLK_IO6 _L_(12)
+#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
+#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20)
+#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7 _L_(12)
+#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
+#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
+#define MUX_PB21M_GCLK_IO7 _L_(12)
+#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
+#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
+#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
+#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */
+#define MUX_PD00A_EIC_EXTINT0 _L_(0)
+#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0)
+#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0)
+#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
+#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
+#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */
+#define MUX_PD01A_EIC_EXTINT1 _L_(0)
+#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1)
+#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1)
+#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
+#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2)
+#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
+#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT2 _L_(0)
+#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
+#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3)
+#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
+#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
+#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */
+#define MUX_PD08A_EIC_EXTINT3 _L_(0)
+#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3)
+#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8)
+#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
+#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */
+#define MUX_PC04A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4)
+#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4)
+#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */
+#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
+#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20)
+#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
+#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */
+#define MUX_PD09A_EIC_EXTINT4 _L_(0)
+#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4)
+#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9)
+#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
+#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5)
+#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
+#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
+#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21)
+#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
+#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */
+#define MUX_PD10A_EIC_EXTINT5 _L_(0)
+#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5)
+#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10)
+#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6)
+#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
+#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */
+#define MUX_PC22A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6)
+#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22)
+#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */
+#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */
+#define MUX_PD11A_EIC_EXTINT6 _L_(0)
+#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6)
+#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11)
+#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
+#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */
+#define MUX_PC23A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7)
+#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23)
+#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */
+#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */
+#define MUX_PD12A_EIC_EXTINT7 _L_(0)
+#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7)
+#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12)
+#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
+#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
+#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT8 _L_(0)
+#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
+#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24)
+#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
+#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
+#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
+#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7)
+#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
+#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT9 _L_(0)
+#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
+#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25)
+#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
+#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
+#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26)
+#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
+#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */
+#define MUX_PD20A_EIC_EXTINT10 _L_(0)
+#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10)
+#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20)
+#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
+#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
+#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27)
+#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
+#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */
+#define MUX_PD21A_EIC_EXTINT11 _L_(0)
+#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11)
+#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21)
+#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */
+#define MUX_PB26A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12)
+#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26)
+#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */
+#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
+#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT12 _L_(0)
+#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
+#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28)
+#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */
+#define MUX_PB27A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13)
+#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27)
+#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */
+#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT13 _L_(0)
+#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */
+#define MUX_PB28A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14)
+#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28)
+#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
+#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */
+#define MUX_PC30A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14)
+#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30)
+#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */
+#define MUX_PB29A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15)
+#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29)
+#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
+#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */
+#define MUX_PC31A_EIC_EXTINT15 _L_(0)
+#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15)
+#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31)
+#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI _L_(0)
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
+#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
+#define MUX_PC17D_SERCOM0_PAD0 _L_(3)
+#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
+#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17)
+#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
+#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0 _L_(2)
+#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24)
+#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
+#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
+#define MUX_PC16D_SERCOM0_PAD1 _L_(3)
+#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
+#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16)
+#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
+#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1 _L_(2)
+#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25)
+#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
+#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
+#define MUX_PC18D_SERCOM0_PAD2 _L_(3)
+#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
+#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18)
+#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
+#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2 _L_(2)
+#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24)
+#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
+#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
+#define MUX_PC19D_SERCOM0_PAD3 _L_(3)
+#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
+#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19)
+#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
+#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3 _L_(2)
+#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
+#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
+#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */
+#define MUX_PC22C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0)
+#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22)
+#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
+#define MUX_PC27C_SERCOM1_PAD0 _L_(2)
+#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
+#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27)
+#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
+#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
+#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */
+#define MUX_PC23C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1)
+#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23)
+#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
+#define MUX_PC28C_SERCOM1_PAD1 _L_(2)
+#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
+#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28)
+#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
+#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */
+#define MUX_PD20C_SERCOM1_PAD2 _L_(2)
+#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2)
+#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20)
+#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
+#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */
+#define MUX_PD21C_SERCOM1_PAD3 _L_(2)
+#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3)
+#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0 _L_(4)
+#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
+#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0 _L_(4)
+#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
+#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0 _L_(4)
+#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1 _L_(4)
+#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
+#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1 _L_(4)
+#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
+#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1 _L_(4)
+#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0 _L_(4)
+#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
+#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0 _L_(4)
+#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1 _L_(4)
+#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
+#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1 _L_(4)
+#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM _L_(7)
+#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP _L_(7)
+#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
+#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
+#define MUX_PB25D_SERCOM2_PAD0 _L_(3)
+#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
+#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25)
+#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
+#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */
+#define MUX_PB26C_SERCOM2_PAD0 _L_(2)
+#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0)
+#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26)
+#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
+#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
+#define MUX_PB24D_SERCOM2_PAD1 _L_(3)
+#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
+#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24)
+#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
+#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */
+#define MUX_PB27C_SERCOM2_PAD1 _L_(2)
+#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1)
+#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27)
+#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
+#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM2_PAD2 _L_(3)
+#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
+#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24)
+#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */
+#define MUX_PB28C_SERCOM2_PAD2 _L_(2)
+#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2)
+#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28)
+#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
+#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM2_PAD3 _L_(3)
+#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
+#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25)
+#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */
+#define MUX_PB29C_SERCOM2_PAD3 _L_(2)
+#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3)
+#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29)
+#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0 _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
+#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */
+#define MUX_PC23D_SERCOM3_PAD0 _L_(3)
+#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0)
+#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23)
+#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
+#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0 _L_(2)
+#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20)
+#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1 _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
+#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */
+#define MUX_PC22D_SERCOM3_PAD1 _L_(3)
+#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1)
+#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22)
+#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
+#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1 _L_(2)
+#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21)
+#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
+#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */
+#define MUX_PD20D_SERCOM3_PAD2 _L_(3)
+#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2)
+#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
+#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */
+#define MUX_PD21D_SERCOM3_PAD3 _L_(3)
+#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3)
+#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0 _L_(6)
+#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0 _L_(6)
+#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0 _L_(5)
+#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
+#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */
+#define MUX_PC04F_TCC0_WO0 _L_(5)
+#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0)
+#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4)
+#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
+#define MUX_PC10F_TCC0_WO0 _L_(5)
+#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
+#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10)
+#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
+#define MUX_PC16F_TCC0_WO0 _L_(5)
+#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
+#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16)
+#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1 _L_(6)
+#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1 _L_(6)
+#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1 _L_(5)
+#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
+#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
+#define MUX_PC11F_TCC0_WO1 _L_(5)
+#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
+#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11)
+#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
+#define MUX_PC17F_TCC0_WO1 _L_(5)
+#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
+#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17)
+#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */
+#define MUX_PD08F_TCC0_WO1 _L_(5)
+#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1)
+#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8)
+#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2 _L_(6)
+#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2 _L_(6)
+#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 _L_(5)
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
+#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
+#define MUX_PC12F_TCC0_WO2 _L_(5)
+#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
+#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12)
+#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
+#define MUX_PC18F_TCC0_WO2 _L_(5)
+#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
+#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18)
+#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */
+#define MUX_PD09F_TCC0_WO2 _L_(5)
+#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2)
+#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9)
+#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3 _L_(6)
+#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3 _L_(6)
+#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 _L_(5)
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
+#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
+#define MUX_PC13F_TCC0_WO3 _L_(5)
+#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
+#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13)
+#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
+#define MUX_PC19F_TCC0_WO3 _L_(5)
+#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
+#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19)
+#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */
+#define MUX_PD10F_TCC0_WO3 _L_(5)
+#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3)
+#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10)
+#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4 _L_(6)
+#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4 _L_(6)
+#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 _L_(5)
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
+#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
+#define MUX_PC14F_TCC0_WO4 _L_(5)
+#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
+#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14)
+#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
+#define MUX_PC20F_TCC0_WO4 _L_(5)
+#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
+#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20)
+#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */
+#define MUX_PD11F_TCC0_WO4 _L_(5)
+#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4)
+#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11)
+#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5 _L_(6)
+#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5 _L_(6)
+#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 _L_(5)
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
+#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
+#define MUX_PC15F_TCC0_WO5 _L_(5)
+#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
+#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15)
+#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
+#define MUX_PC21F_TCC0_WO5 _L_(5)
+#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
+#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21)
+#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */
+#define MUX_PD12F_TCC0_WO5 _L_(5)
+#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5)
+#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12)
+#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6 _L_(6)
+#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6 _L_(6)
+#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 _L_(5)
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
+#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */
+#define MUX_PC22F_TCC0_WO6 _L_(5)
+#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6)
+#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22)
+#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7 _L_(6)
+#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7 _L_(6)
+#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 _L_(5)
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
+#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */
+#define MUX_PC23F_TCC0_WO7 _L_(5)
+#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7)
+#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0 _L_(6)
+#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
+#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
+#define MUX_PC14G_TCC1_WO0 _L_(6)
+#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
+#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14)
+#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0 _L_(5)
+#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
+#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC1_WO0 _L_(5)
+#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
+#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18)
+#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */
+#define MUX_PD20F_TCC1_WO0 _L_(5)
+#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0)
+#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20)
+#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1 _L_(6)
+#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
+#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
+#define MUX_PC15G_TCC1_WO1 _L_(6)
+#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
+#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15)
+#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1 _L_(5)
+#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
+#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC1_WO1 _L_(5)
+#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
+#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19)
+#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */
+#define MUX_PD21F_TCC1_WO1 _L_(5)
+#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1)
+#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21)
+#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2 _L_(6)
+#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2 _L_(6)
+#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2 _L_(5)
+#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
+#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC1_WO2 _L_(5)
+#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
+#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20)
+#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */
+#define MUX_PB26F_TCC1_WO2 _L_(5)
+#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2)
+#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26)
+#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3 _L_(6)
+#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3 _L_(6)
+#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3 _L_(5)
+#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
+#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC1_WO3 _L_(5)
+#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
+#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21)
+#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */
+#define MUX_PB27F_TCC1_WO3 _L_(5)
+#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3)
+#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27)
+#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4 _L_(6)
+#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
+#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
+#define MUX_PC10G_TCC1_WO4 _L_(6)
+#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
+#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10)
+#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4 _L_(5)
+#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
+#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */
+#define MUX_PB28F_TCC1_WO4 _L_(5)
+#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4)
+#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28)
+#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5 _L_(6)
+#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
+#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
+#define MUX_PC11G_TCC1_WO5 _L_(6)
+#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
+#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11)
+#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5 _L_(5)
+#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
+#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */
+#define MUX_PB29F_TCC1_WO5 _L_(5)
+#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5)
+#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29)
+#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6 _L_(6)
+#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
+#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
+#define MUX_PC12G_TCC1_WO6 _L_(6)
+#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
+#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12)
+#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6 _L_(5)
+#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7 _L_(6)
+#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
+#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
+#define MUX_PC13G_TCC1_WO7 _L_(6)
+#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
+#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13)
+#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7 _L_(5)
+#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0 _L_(4)
+#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0 _L_(4)
+#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0 _L_(4)
+#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
+#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1 _L_(4)
+#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
+#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1 _L_(4)
+#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1 _L_(4)
+#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 _L_(4)
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 _L_(4)
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 _L_(4)
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 _L_(4)
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
+/* ========== PORT definition for TAL peripheral ========== */
+#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */
+#define MUX_PA27H_TAL_BRK _L_(7)
+#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK)
+#define PORT_PA27H_TAL_BRK (_UL_(1) << 27)
+#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */
+#define MUX_PB31H_TAL_BRK _L_(7)
+#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK)
+#define PORT_PB31H_TAL_BRK (_UL_(1) << 31)
+/* ========== PORT definition for CAN0 peripheral ========== */
+#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */
+#define MUX_PA23I_CAN0_RX _L_(8)
+#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX)
+#define PORT_PA23I_CAN0_RX (_UL_(1) << 23)
+#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */
+#define MUX_PA25I_CAN0_RX _L_(8)
+#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX)
+#define PORT_PA25I_CAN0_RX (_UL_(1) << 25)
+#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */
+#define MUX_PA22I_CAN0_TX _L_(8)
+#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX)
+#define PORT_PA22I_CAN0_TX (_UL_(1) << 22)
+#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */
+#define MUX_PA24I_CAN0_TX _L_(8)
+#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX)
+#define PORT_PA24I_CAN0_TX (_UL_(1) << 24)
+/* ========== PORT definition for CAN1 peripheral ========== */
+#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */
+#define MUX_PB13H_CAN1_RX _L_(7)
+#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX)
+#define PORT_PB13H_CAN1_RX (_UL_(1) << 13)
+#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */
+#define MUX_PB15H_CAN1_RX _L_(7)
+#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX)
+#define PORT_PB15H_CAN1_RX (_UL_(1) << 15)
+#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */
+#define MUX_PB12H_CAN1_TX _L_(7)
+#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX)
+#define PORT_PB12H_CAN1_TX (_UL_(1) << 12)
+#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */
+#define MUX_PB14H_CAN1_TX _L_(7)
+#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX)
+#define PORT_PB14H_CAN1_TX (_UL_(1) << 14)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
+#define MUX_PC21L_GMAC_GCOL _L_(11)
+#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
+#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21)
+#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14)
+#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
+#define MUX_PC11L_GMAC_GMDC _L_(11)
+#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
+#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11)
+#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */
+#define MUX_PC22L_GMAC_GMDC _L_(11)
+#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC)
+#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22)
+#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15)
+#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
+#define MUX_PC12L_GMAC_GMDIO _L_(11)
+#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
+#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12)
+#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */
+#define MUX_PC23L_GMAC_GMDIO _L_(11)
+#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO)
+#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23)
+#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0 _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1 _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12)
+#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
+#define MUX_PC15L_GMAC_GRX2 _L_(11)
+#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
+#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15)
+#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
+#define MUX_PC14L_GMAC_GRX3 _L_(11)
+#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
+#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14)
+#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
+#define MUX_PC18L_GMAC_GRXCK _L_(11)
+#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
+#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18)
+#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
+#define MUX_PC20L_GMAC_GRXDV _L_(11)
+#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
+#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20)
+#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0 _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1 _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19)
+#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
+#define MUX_PC16L_GMAC_GTX2 _L_(11)
+#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
+#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16)
+#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
+#define MUX_PC17L_GMAC_GTX3 _L_(11)
+#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
+#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17)
+#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17)
+#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
+#define MUX_PC19L_GMAC_GTXER _L_(11)
+#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
+#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0 _L_(5)
+#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0 _L_(5)
+#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1 _L_(5)
+#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1 _L_(5)
+#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2 _L_(5)
+#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2 _L_(5)
+#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0 _L_(5)
+#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0 _L_(5)
+#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1 _L_(5)
+#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1 _L_(5)
+#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 _L_(4)
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 _L_(4)
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
+#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 _L_(4)
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 _L_(4)
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 _L_(4)
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
+#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 _L_(4)
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 _L_(4)
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 _L_(4)
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 _L_(4)
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 _L_(4)
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 _L_(4)
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 _L_(4)
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
+#define MUX_PB18G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
+#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18)
+#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0 _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
+#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
+#define MUX_PC16G_PDEC_QDI0 _L_(6)
+#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
+#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16)
+#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0 _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
+#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
+#define MUX_PB19G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
+#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19)
+#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
+#define MUX_PB24G_PDEC_QDI1 _L_(6)
+#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
+#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24)
+#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
+#define MUX_PC17G_PDEC_QDI1 _L_(6)
+#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
+#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17)
+#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1 _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
+#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
+#define MUX_PB20G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
+#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20)
+#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
+#define MUX_PB25G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
+#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25)
+#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
+#define MUX_PC18G_PDEC_QDI2 _L_(6)
+#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
+#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18)
+#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2 _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 _L_(1)
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
+#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 _L_(1)
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
+#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 _L_(1)
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
+#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 _L_(1)
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
+#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0 _L_(12)
+#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0 _L_(12)
+#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
+#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
+#define MUX_PB24M_AC_CMP0 _L_(12)
+#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
+#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24)
+#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1 _L_(12)
+#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1 _L_(12)
+#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
+#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
+#define MUX_PB25M_AC_CMP1 _L_(12)
+#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
+#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS _L_(7)
+#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0 _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
+#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1 _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
+#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2 _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3 _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK _L_(7)
+#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0 _L_(13)
+#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
+#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0 _L_(13)
+#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0 _L_(13)
+#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1 _L_(13)
+#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
+#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1 _L_(13)
+#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1 _L_(13)
+#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
+#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2 _L_(13)
+#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
+#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2 _L_(13)
+#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2 _L_(13)
+#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
+#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3 _L_(13)
+#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
+#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3 _L_(13)
+#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4 _L_(13)
+#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
+#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
+#define MUX_PC27N_CCL_IN4 _L_(13)
+#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
+#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27)
+#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5 _L_(13)
+#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
+#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
+#define MUX_PC28N_CCL_IN5 _L_(13)
+#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
+#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28)
+#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6 _L_(13)
+#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6 _L_(13)
+#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
+#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7 _L_(13)
+#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7 _L_(13)
+#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
+#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8 _L_(13)
+#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8 _L_(13)
+#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
+#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9 _L_(13)
+#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
+#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
+#define MUX_PC20N_CCL_IN9 _L_(13)
+#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
+#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20)
+#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10 _L_(13)
+#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
+#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
+#define MUX_PC21N_CCL_IN10 _L_(13)
+#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
+#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21)
+#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11 _L_(13)
+#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11 _L_(13)
+#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0 _L_(13)
+#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
+#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0 _L_(13)
+#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0 _L_(13)
+#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
+#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0 _L_(13)
+#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1 _L_(13)
+#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1 _L_(13)
+#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1 _L_(13)
+#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2 _L_(13)
+#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2 _L_(13)
+#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
+#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3 _L_(13)
+#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
+#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */
+#define MUX_PB27D_SERCOM4_PAD0 _L_(3)
+#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0)
+#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27)
+#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
+#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */
+#define MUX_PB26D_SERCOM4_PAD1 _L_(3)
+#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1)
+#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26)
+#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
+#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */
+#define MUX_PB28D_SERCOM4_PAD2 _L_(3)
+#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2)
+#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28)
+#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
+#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */
+#define MUX_PB29D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3)
+#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29)
+#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
+#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0 _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
+#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1 _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
+#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
+#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2 _L_(2)
+#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18)
+#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
+#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
+#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3 _L_(2)
+#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM6 peripheral ========== */
+#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */
+#define MUX_PD09D_SERCOM6_PAD0 _L_(3)
+#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0)
+#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9)
+#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
+#define MUX_PC13D_SERCOM6_PAD0 _L_(3)
+#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
+#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13)
+#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */
+#define MUX_PC04C_SERCOM6_PAD0 _L_(2)
+#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0)
+#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4)
+#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
+#define MUX_PC16C_SERCOM6_PAD0 _L_(2)
+#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
+#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16)
+#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */
+#define MUX_PD08D_SERCOM6_PAD1 _L_(3)
+#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1)
+#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8)
+#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
+#define MUX_PC12D_SERCOM6_PAD1 _L_(3)
+#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
+#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12)
+#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
+#define MUX_PC05C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
+#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5)
+#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
+#define MUX_PC17C_SERCOM6_PAD1 _L_(2)
+#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
+#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17)
+#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
+#define MUX_PC14D_SERCOM6_PAD2 _L_(3)
+#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
+#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14)
+#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */
+#define MUX_PD10D_SERCOM6_PAD2 _L_(3)
+#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2)
+#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10)
+#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
+#define MUX_PC06C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
+#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6)
+#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
+#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10)
+#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
+#define MUX_PC18C_SERCOM6_PAD2 _L_(2)
+#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
+#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18)
+#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
+#define MUX_PC15D_SERCOM6_PAD3 _L_(3)
+#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
+#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15)
+#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */
+#define MUX_PD11D_SERCOM6_PAD3 _L_(3)
+#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3)
+#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11)
+#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
+#define MUX_PC07C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
+#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7)
+#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
+#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11)
+#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
+#define MUX_PC19C_SERCOM6_PAD3 _L_(2)
+#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
+#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM7 peripheral ========== */
+#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
+#define MUX_PB21D_SERCOM7_PAD0 _L_(3)
+#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
+#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21)
+#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */
+#define MUX_PD08C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0)
+#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8)
+#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
+#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30)
+#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM7_PAD0 _L_(2)
+#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
+#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12)
+#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
+#define MUX_PB20D_SERCOM7_PAD1 _L_(3)
+#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
+#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20)
+#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */
+#define MUX_PD09C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1)
+#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9)
+#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
+#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31)
+#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM7_PAD1 _L_(2)
+#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
+#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13)
+#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
+#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18)
+#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
+#define MUX_PC10D_SERCOM7_PAD2 _L_(3)
+#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
+#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10)
+#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
+#define MUX_PC14C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
+#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14)
+#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */
+#define MUX_PD10C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2)
+#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10)
+#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
+#define MUX_PA30C_SERCOM7_PAD2 _L_(2)
+#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
+#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30)
+#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
+#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19)
+#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
+#define MUX_PC11D_SERCOM7_PAD3 _L_(3)
+#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
+#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11)
+#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
+#define MUX_PC15C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
+#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15)
+#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */
+#define MUX_PD11C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3)
+#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11)
+#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
+#define MUX_PA31C_SERCOM7_PAD3 _L_(2)
+#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
+#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0 _L_(5)
+#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0 _L_(5)
+#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1 _L_(5)
+#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1 _L_(5)
+#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TC6_WO0 _L_(4)
+#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
+#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30)
+#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 _L_(4)
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2)
+#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 _L_(4)
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16)
+#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TC6_WO1 _L_(4)
+#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
+#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31)
+#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 _L_(4)
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3)
+#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 _L_(4)
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 _L_(4)
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20)
+#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 _L_(4)
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0)
+#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 _L_(4)
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22)
+#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 _L_(4)
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21)
+#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 _L_(4)
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1)
+#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 _L_(4)
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0 _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
+#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1 _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2 _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3 _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4 _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
+#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5 _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
+#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6 _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7 _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8 _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9 _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10 _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11 _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12 _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13 _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
+#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14 _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15 _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
+#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0 _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
+#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1 _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
+#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2 _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
+#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3 _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
+#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4 _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
+#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5 _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
+#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6 _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
+#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7 _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
+#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8 _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9 _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10 _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11 _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12 _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13 _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14 _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15 _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16 _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17 _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18 _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19 _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20 _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
+#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21 _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
+#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22 _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
+#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23 _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
+#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24 _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
+#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25 _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
+#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26 _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27 _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28 _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29 _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30 _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
+#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31 _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
+#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0 _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
+#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1 _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
+#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2 _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
+#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3 _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
+#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4 _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
+#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5 _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
+#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6 _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
+#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7 _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
+#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8 _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9 _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10 _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11 _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
+#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13 _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14 _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15 _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16 _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17 _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18 _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19 _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20 _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
+#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21 _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
+#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22 _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
+#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23 _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
+#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24 _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
+#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25 _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
+#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26 _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27 _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28 _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29 _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30 _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
+#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31 _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0 _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
+#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1 _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
+#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2 _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
+#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3 _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
+#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
+#define MUX_PC02B_ADC1_AIN4 _L_(1)
+#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
+#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2)
+#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
+#define MUX_PC03B_ADC1_AIN5 _L_(1)
+#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
+#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3)
+#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6 _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
+#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7 _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
+#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8 _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
+#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9 _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
+#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
+#define MUX_PC00B_ADC1_AIN10 _L_(1)
+#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
+#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0)
+#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
+#define MUX_PC01B_ADC1_AIN11 _L_(1)
+#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
+#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1)
+#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */
+#define MUX_PC30B_ADC1_AIN12 _L_(1)
+#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12)
+#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30)
+#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */
+#define MUX_PC31B_ADC1_AIN13 _L_(1)
+#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13)
+#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31)
+#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */
+#define MUX_PD00B_ADC1_AIN14 _L_(1)
+#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14)
+#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0)
+#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */
+#define MUX_PD01B_ADC1_AIN15 _L_(1)
+#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15)
+#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0 _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
+#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1 _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0 _L_(9)
+#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
+#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0 _L_(9)
+#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1 _L_(9)
+#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1 _L_(9)
+#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0 _L_(9)
+#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
+#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0 _L_(9)
+#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
+#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */
+#define MUX_PB29J_I2S_MCK1 _L_(9)
+#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1)
+#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29)
+#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1 _L_(9)
+#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0 _L_(9)
+#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0 _L_(9)
+#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
+#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */
+#define MUX_PB28J_I2S_SCK1 _L_(9)
+#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1)
+#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28)
+#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1 _L_(9)
+#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI _L_(9)
+#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI _L_(9)
+#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO _L_(9)
+#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO _L_(9)
+#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK _L_(10)
+#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0 _L_(10)
+#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1 _L_(10)
+#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2 _L_(10)
+#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3 _L_(10)
+#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4 _L_(10)
+#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5 _L_(10)
+#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6 _L_(10)
+#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7 _L_(10)
+#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8 _L_(10)
+#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9 _L_(10)
+#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
+#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
+#define MUX_PC12K_PCC_DATA10 _L_(10)
+#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
+#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12)
+#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
+#define MUX_PC13K_PCC_DATA11 _L_(10)
+#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
+#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13)
+#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
+#define MUX_PC14K_PCC_DATA12 _L_(10)
+#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
+#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14)
+#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
+#define MUX_PC15K_PCC_DATA13 _L_(10)
+#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
+#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1 _L_(10)
+#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2 _L_(10)
+#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
+#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
+#define MUX_PC06I_SDHC0_SDCD _L_(8)
+#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
+#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6)
+#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
+#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
+#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
+#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
+#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
+#define MUX_PC07I_SDHC0_SDWP _L_(8)
+#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
+#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7)
+/* ========== PORT definition for SDHC1 peripheral ========== */
+#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
+#define MUX_PB16I_SDHC1_SDCD _L_(8)
+#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
+#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16)
+#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
+#define MUX_PC20I_SDHC1_SDCD _L_(8)
+#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
+#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20)
+#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */
+#define MUX_PD20I_SDHC1_SDCD _L_(8)
+#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD)
+#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20)
+#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
+#define MUX_PA21I_SDHC1_SDCK _L_(8)
+#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
+#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21)
+#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
+#define MUX_PA20I_SDHC1_SDCMD _L_(8)
+#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
+#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20)
+#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
+#define MUX_PB18I_SDHC1_SDDAT0 _L_(8)
+#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
+#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18)
+#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
+#define MUX_PB19I_SDHC1_SDDAT1 _L_(8)
+#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
+#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19)
+#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
+#define MUX_PB20I_SDHC1_SDDAT2 _L_(8)
+#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
+#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20)
+#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
+#define MUX_PB21I_SDHC1_SDDAT3 _L_(8)
+#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
+#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21)
+#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
+#define MUX_PB17I_SDHC1_SDWP _L_(8)
+#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
+#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17)
+#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
+#define MUX_PC21I_SDHC1_SDWP _L_(8)
+#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
+#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21)
+#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */
+#define MUX_PD21I_SDHC1_SDWP _L_(8)
+#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP)
+#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21)
+
+#endif /* _SAME54P20A_PIO_ */
diff --git a/GPIO/ATSAME54/include/same54.h b/GPIO/ATSAME54/include/same54.h
new file mode 100644
index 0000000..e152e50
--- /dev/null
+++ b/GPIO/ATSAME54/include/same54.h
@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief Top header file for SAME54
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54_
+#define _SAME54_
+
+/**
+ * \defgroup SAME54_definitions SAME54 Device Definitions
+ * \brief SAME54 CMSIS Definitions.
+ */
+
+#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__)
+ #include "same54n19a.h"
+#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__)
+ #include "same54n20a.h"
+#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__)
+ #include "same54p19a.h"
+#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__)
+ #include "same54p20a.h"
+#else
+ #error Library does not support the specified device.
+#endif
+
+#endif /* _SAME54_ */
diff --git a/GPIO/ATSAME54/include/same54n19a.h b/GPIO/ATSAME54/include/same54n19a.h
new file mode 100644
index 0000000..b99de27
--- /dev/null
+++ b/GPIO/ATSAME54/include/same54n19a.h
@@ -0,0 +1,1149 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME54N19A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54N19A_
+#define _SAME54N19A_
+
+/**
+ * \ingroup SAME54_definitions
+ * \addtogroup SAME54N19A_definitions SAME54N19A definitions
+ * This file defines all structures and symbols for SAME54N19A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+ #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L_(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x) x /**< Assembler: Long integer literal constant value */
+#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+/** \defgroup SAME54N19A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAME54N19A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */
+ MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */
+ OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+ OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */
+ SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+ SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */
+ WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */
+ RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */
+ EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_15 */
+ FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */
+ NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+ PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */
+ TAL_0_IRQn = 42, /**< 42 SAME54N19A Trigger Allocator (TAL): TAL_BRK */
+ TAL_1_IRQn = 43, /**< 43 SAME54N19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */
+ RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */
+ SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+ CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */
+ CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */
+ USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+ USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB): USB_SOF_HSOF */
+ USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+ USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+ GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */
+ TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+ TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+ TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+ TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+ TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+ TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */
+ TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */
+ TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */
+ TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */
+ TC3_IRQn = 110, /**< 110 SAME54N19A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 111, /**< 111 SAME54N19A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */
+ PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+ PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC): PDEC_MC_0 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC): PDEC_MC_1 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */
+ ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */
+ ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */
+ ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */
+ AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */
+ DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+ DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */
+ DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */
+ DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */
+ DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */
+ I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */
+ PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */
+ AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */
+ TRNG_IRQn = 131, /**< 131 SAME54N19A True Random Generator (TRNG) */
+ ICM_IRQn = 132, /**< 132 SAME54N19A Integrity Check Monitor (ICM) */
+ PUKCC_IRQn = 133, /**< 133 SAME54N19A PUblic-Key Cryptography Controller (PUKCC) */
+ QSPI_IRQn = 134, /**< 134 SAME54N19A Quad SPI interface (QSPI) */
+ SDHC0_IRQn = 135, /**< 135 SAME54N19A SD/MMC Host Controller 0 (SDHC0) */
+ SDHC1_IRQn = 136, /**< 136 SAME54N19A SD/MMC Host Controller 1 (SDHC1) */
+
+ PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnMCLK_Handler; /* 1 Main Clock */
+ void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
+ void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
+ void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
+ void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
+ void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
+ void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
+ void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
+ void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
+ void* pfnWDT_Handler; /* 10 Watchdog Timer */
+ void* pfnRTC_Handler; /* 11 Real-Time Counter */
+ void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
+ void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
+ void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
+ void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
+ void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
+ void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
+ void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
+ void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
+ void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
+ void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
+ void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
+ void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
+ void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
+ void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
+ void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
+ void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
+ void* pfnFREQM_Handler; /* 28 Frequency Meter */
+ void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
+ void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
+ void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
+ void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
+ void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
+ void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
+ void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
+ void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
+ void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
+ void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
+ void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
+ void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
+ void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
+ void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */
+ void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */
+ void* pvReserved44;
+ void* pfnRAMECC_Handler; /* 45 RAM ECC */
+ void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
+ void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
+ void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
+ void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
+ void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
+ void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
+ void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
+ void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
+ void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
+ void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
+ void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
+ void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
+ void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
+ void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
+ void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
+ void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
+ void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
+ void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
+ void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
+ void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
+ void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
+ void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
+ void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
+ void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
+ void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
+ void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
+ void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
+ void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
+ void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
+ void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
+ void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
+ void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
+ void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
+ void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
+ void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
+ void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
+ void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
+ void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
+ void* pfnGMAC_Handler; /* 84 Ethernet MAC */
+ void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
+ void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
+ void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
+ void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
+ void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
+ void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
+ void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
+ void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
+ void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
+ void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
+ void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
+ void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
+ void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
+ void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
+ void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
+ void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
+ void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
+ void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
+ void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
+ void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
+ void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
+ void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
+ void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
+ void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
+ void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
+ void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
+ void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
+ void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
+ void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
+ void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
+ void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
+ void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
+ void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
+ void* pfnAC_Handler; /* 122 Analog Comparators */
+ void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
+ void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
+ void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
+ void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
+ void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
+ void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
+ void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
+ void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
+ void* pfnTRNG_Handler; /* 131 True Random Generator */
+ void* pfnICM_Handler; /* 132 Integrity Check Monitor */
+ void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
+ void* pfnQSPI_Handler; /* 134 Quad SPI interface */
+ void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
+ void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void MCLK_Handler ( void );
+void OSCCTRL_0_Handler ( void );
+void OSCCTRL_1_Handler ( void );
+void OSCCTRL_2_Handler ( void );
+void OSCCTRL_3_Handler ( void );
+void OSCCTRL_4_Handler ( void );
+void OSC32KCTRL_Handler ( void );
+void SUPC_0_Handler ( void );
+void SUPC_1_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_0_Handler ( void );
+void EIC_1_Handler ( void );
+void EIC_2_Handler ( void );
+void EIC_3_Handler ( void );
+void EIC_4_Handler ( void );
+void EIC_5_Handler ( void );
+void EIC_6_Handler ( void );
+void EIC_7_Handler ( void );
+void EIC_8_Handler ( void );
+void EIC_9_Handler ( void );
+void EIC_10_Handler ( void );
+void EIC_11_Handler ( void );
+void EIC_12_Handler ( void );
+void EIC_13_Handler ( void );
+void EIC_14_Handler ( void );
+void EIC_15_Handler ( void );
+void FREQM_Handler ( void );
+void NVMCTRL_0_Handler ( void );
+void NVMCTRL_1_Handler ( void );
+void DMAC_0_Handler ( void );
+void DMAC_1_Handler ( void );
+void DMAC_2_Handler ( void );
+void DMAC_3_Handler ( void );
+void DMAC_4_Handler ( void );
+void EVSYS_0_Handler ( void );
+void EVSYS_1_Handler ( void );
+void EVSYS_2_Handler ( void );
+void EVSYS_3_Handler ( void );
+void EVSYS_4_Handler ( void );
+void PAC_Handler ( void );
+void TAL_0_Handler ( void );
+void TAL_1_Handler ( void );
+void RAMECC_Handler ( void );
+void SERCOM0_0_Handler ( void );
+void SERCOM0_1_Handler ( void );
+void SERCOM0_2_Handler ( void );
+void SERCOM0_3_Handler ( void );
+void SERCOM1_0_Handler ( void );
+void SERCOM1_1_Handler ( void );
+void SERCOM1_2_Handler ( void );
+void SERCOM1_3_Handler ( void );
+void SERCOM2_0_Handler ( void );
+void SERCOM2_1_Handler ( void );
+void SERCOM2_2_Handler ( void );
+void SERCOM2_3_Handler ( void );
+void SERCOM3_0_Handler ( void );
+void SERCOM3_1_Handler ( void );
+void SERCOM3_2_Handler ( void );
+void SERCOM3_3_Handler ( void );
+void SERCOM4_0_Handler ( void );
+void SERCOM4_1_Handler ( void );
+void SERCOM4_2_Handler ( void );
+void SERCOM4_3_Handler ( void );
+void SERCOM5_0_Handler ( void );
+void SERCOM5_1_Handler ( void );
+void SERCOM5_2_Handler ( void );
+void SERCOM5_3_Handler ( void );
+void SERCOM6_0_Handler ( void );
+void SERCOM6_1_Handler ( void );
+void SERCOM6_2_Handler ( void );
+void SERCOM6_3_Handler ( void );
+void SERCOM7_0_Handler ( void );
+void SERCOM7_1_Handler ( void );
+void SERCOM7_2_Handler ( void );
+void SERCOM7_3_Handler ( void );
+void CAN0_Handler ( void );
+void CAN1_Handler ( void );
+void USB_0_Handler ( void );
+void USB_1_Handler ( void );
+void USB_2_Handler ( void );
+void USB_3_Handler ( void );
+void GMAC_Handler ( void );
+void TCC0_0_Handler ( void );
+void TCC0_1_Handler ( void );
+void TCC0_2_Handler ( void );
+void TCC0_3_Handler ( void );
+void TCC0_4_Handler ( void );
+void TCC0_5_Handler ( void );
+void TCC0_6_Handler ( void );
+void TCC1_0_Handler ( void );
+void TCC1_1_Handler ( void );
+void TCC1_2_Handler ( void );
+void TCC1_3_Handler ( void );
+void TCC1_4_Handler ( void );
+void TCC2_0_Handler ( void );
+void TCC2_1_Handler ( void );
+void TCC2_2_Handler ( void );
+void TCC2_3_Handler ( void );
+void TCC3_0_Handler ( void );
+void TCC3_1_Handler ( void );
+void TCC3_2_Handler ( void );
+void TCC4_0_Handler ( void );
+void TCC4_1_Handler ( void );
+void TCC4_2_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void PDEC_0_Handler ( void );
+void PDEC_1_Handler ( void );
+void PDEC_2_Handler ( void );
+void ADC0_0_Handler ( void );
+void ADC0_1_Handler ( void );
+void ADC1_0_Handler ( void );
+void ADC1_1_Handler ( void );
+void AC_Handler ( void );
+void DAC_0_Handler ( void );
+void DAC_1_Handler ( void );
+void DAC_2_Handler ( void );
+void DAC_3_Handler ( void );
+void DAC_4_Handler ( void );
+void I2S_Handler ( void );
+void PCC_Handler ( void );
+void AES_Handler ( void );
+void TRNG_Handler ( void );
+void ICM_Handler ( void );
+void PUKCC_Handler ( void );
+void QSPI_Handler ( void );
+void SDHC0_Handler ( void );
+void SDHC1_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM4_REV 1 /*!< Core revision r0p1 */
+#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same54.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */
+/* ************************************************************************** */
+/** \defgroup SAME54N19A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tal.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+/** \defgroup SAME54N19A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sdhc1.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sercom6.h"
+#include "instance/sercom7.h"
+#include "instance/supc.h"
+#include "instance/tal.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+/** \defgroup SAME54N19A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT 36 /**< \brief Port Module (PORT) */
+#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */
+#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
+#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */
+#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC 72 /**< \brief Analog Comparators (AC) */
+#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
+#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
+#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
+#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */
+
+#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+/** \defgroup SAME54N19A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES (0x42002400) /**< \brief (AES) APB Base Address */
+#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
+#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */
+#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */
+#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
+#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */
+#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
+
+#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
+#define AES_INSTS { AES } /**< \brief (AES) Instances List */
+
+#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
+#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */
+#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
+#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
+
+#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
+#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
+
+#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
+
+#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
+
+#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */
+
+#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
+#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
+
+#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
+
+#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
+#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
+
+#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
+
+#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
+
+#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
+
+#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
+
+#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
+#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
+#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
+
+#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */
+#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */
+#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */
+
+#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
+
+#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+/** \defgroup SAME54N19A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same54n19a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */
+#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */
+#define FLASH_PAGE_SIZE 512
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 512
+#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL_(0x61840003)
+#define ADC0_TOUCH_LINES_NUM 32
+#define PORT_GROUPS 3
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAME54N19A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME54N19A_H */
diff --git a/GPIO/ATSAME54/include/same54n20a.h b/GPIO/ATSAME54/include/same54n20a.h
new file mode 100644
index 0000000..299fec2
--- /dev/null
+++ b/GPIO/ATSAME54/include/same54n20a.h
@@ -0,0 +1,1149 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME54N20A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54N20A_
+#define _SAME54N20A_
+
+/**
+ * \ingroup SAME54_definitions
+ * \addtogroup SAME54N20A_definitions SAME54N20A definitions
+ * This file defines all structures and symbols for SAME54N20A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+ #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L_(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x) x /**< Assembler: Long integer literal constant value */
+#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+/** \defgroup SAME54N20A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAME54N20A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAME54N20A Power Manager (PM) */
+ MCLK_IRQn = 1, /**< 1 SAME54N20A Main Clock (MCLK) */
+ OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+ OSC32KCTRL_IRQn = 7, /**< 7 SAME54N20A 32kHz Oscillators Control (OSC32KCTRL) */
+ SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+ SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */
+ WDT_IRQn = 10, /**< 10 SAME54N20A Watchdog Timer (WDT) */
+ RTC_IRQn = 11, /**< 11 SAME54N20A Real-Time Counter (RTC) */
+ EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_15 */
+ FREQM_IRQn = 28, /**< 28 SAME54N20A Frequency Meter (FREQM) */
+ NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+ PAC_IRQn = 41, /**< 41 SAME54N20A Peripheral Access Controller (PAC) */
+ TAL_0_IRQn = 42, /**< 42 SAME54N20A Trigger Allocator (TAL): TAL_BRK */
+ TAL_1_IRQn = 43, /**< 43 SAME54N20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */
+ RAMECC_IRQn = 45, /**< 45 SAME54N20A RAM ECC (RAMECC) */
+ SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+ CAN0_IRQn = 78, /**< 78 SAME54N20A Control Area Network 0 (CAN0) */
+ CAN1_IRQn = 79, /**< 79 SAME54N20A Control Area Network 1 (CAN1) */
+ USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+ USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB): USB_SOF_HSOF */
+ USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+ USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+ GMAC_IRQn = 84, /**< 84 SAME54N20A Ethernet MAC (GMAC) */
+ TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+ TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+ TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+ TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+ TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+ TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */
+ TC0_IRQn = 107, /**< 107 SAME54N20A Basic Timer Counter 0 (TC0) */
+ TC1_IRQn = 108, /**< 108 SAME54N20A Basic Timer Counter 1 (TC1) */
+ TC2_IRQn = 109, /**< 109 SAME54N20A Basic Timer Counter 2 (TC2) */
+ TC3_IRQn = 110, /**< 110 SAME54N20A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 111, /**< 111 SAME54N20A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 112, /**< 112 SAME54N20A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 113, /**< 113 SAME54N20A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 114, /**< 114 SAME54N20A Basic Timer Counter 7 (TC7) */
+ PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+ PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC): PDEC_MC_0 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC): PDEC_MC_1 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */
+ ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */
+ ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */
+ ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */
+ AC_IRQn = 122, /**< 122 SAME54N20A Analog Comparators (AC) */
+ DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+ DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */
+ DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */
+ DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */
+ DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */
+ I2S_IRQn = 128, /**< 128 SAME54N20A Inter-IC Sound Interface (I2S) */
+ PCC_IRQn = 129, /**< 129 SAME54N20A Parallel Capture Controller (PCC) */
+ AES_IRQn = 130, /**< 130 SAME54N20A Advanced Encryption Standard (AES) */
+ TRNG_IRQn = 131, /**< 131 SAME54N20A True Random Generator (TRNG) */
+ ICM_IRQn = 132, /**< 132 SAME54N20A Integrity Check Monitor (ICM) */
+ PUKCC_IRQn = 133, /**< 133 SAME54N20A PUblic-Key Cryptography Controller (PUKCC) */
+ QSPI_IRQn = 134, /**< 134 SAME54N20A Quad SPI interface (QSPI) */
+ SDHC0_IRQn = 135, /**< 135 SAME54N20A SD/MMC Host Controller 0 (SDHC0) */
+ SDHC1_IRQn = 136, /**< 136 SAME54N20A SD/MMC Host Controller 1 (SDHC1) */
+
+ PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnMCLK_Handler; /* 1 Main Clock */
+ void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
+ void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
+ void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
+ void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
+ void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
+ void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
+ void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
+ void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
+ void* pfnWDT_Handler; /* 10 Watchdog Timer */
+ void* pfnRTC_Handler; /* 11 Real-Time Counter */
+ void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
+ void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
+ void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
+ void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
+ void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
+ void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
+ void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
+ void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
+ void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
+ void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
+ void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
+ void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
+ void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
+ void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
+ void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
+ void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
+ void* pfnFREQM_Handler; /* 28 Frequency Meter */
+ void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
+ void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
+ void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
+ void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
+ void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
+ void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
+ void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
+ void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
+ void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
+ void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
+ void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
+ void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
+ void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
+ void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */
+ void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */
+ void* pvReserved44;
+ void* pfnRAMECC_Handler; /* 45 RAM ECC */
+ void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
+ void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
+ void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
+ void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
+ void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
+ void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
+ void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
+ void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
+ void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
+ void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
+ void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
+ void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
+ void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
+ void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
+ void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
+ void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
+ void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
+ void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
+ void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
+ void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
+ void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
+ void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
+ void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
+ void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
+ void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
+ void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
+ void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
+ void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
+ void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
+ void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
+ void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
+ void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
+ void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
+ void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
+ void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
+ void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
+ void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
+ void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
+ void* pfnGMAC_Handler; /* 84 Ethernet MAC */
+ void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
+ void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
+ void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
+ void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
+ void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
+ void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
+ void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
+ void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
+ void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
+ void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
+ void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
+ void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
+ void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
+ void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
+ void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
+ void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
+ void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
+ void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
+ void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
+ void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
+ void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
+ void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
+ void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
+ void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
+ void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
+ void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
+ void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
+ void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
+ void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
+ void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
+ void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
+ void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
+ void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
+ void* pfnAC_Handler; /* 122 Analog Comparators */
+ void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
+ void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
+ void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
+ void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
+ void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
+ void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
+ void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
+ void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
+ void* pfnTRNG_Handler; /* 131 True Random Generator */
+ void* pfnICM_Handler; /* 132 Integrity Check Monitor */
+ void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
+ void* pfnQSPI_Handler; /* 134 Quad SPI interface */
+ void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
+ void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void MCLK_Handler ( void );
+void OSCCTRL_0_Handler ( void );
+void OSCCTRL_1_Handler ( void );
+void OSCCTRL_2_Handler ( void );
+void OSCCTRL_3_Handler ( void );
+void OSCCTRL_4_Handler ( void );
+void OSC32KCTRL_Handler ( void );
+void SUPC_0_Handler ( void );
+void SUPC_1_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_0_Handler ( void );
+void EIC_1_Handler ( void );
+void EIC_2_Handler ( void );
+void EIC_3_Handler ( void );
+void EIC_4_Handler ( void );
+void EIC_5_Handler ( void );
+void EIC_6_Handler ( void );
+void EIC_7_Handler ( void );
+void EIC_8_Handler ( void );
+void EIC_9_Handler ( void );
+void EIC_10_Handler ( void );
+void EIC_11_Handler ( void );
+void EIC_12_Handler ( void );
+void EIC_13_Handler ( void );
+void EIC_14_Handler ( void );
+void EIC_15_Handler ( void );
+void FREQM_Handler ( void );
+void NVMCTRL_0_Handler ( void );
+void NVMCTRL_1_Handler ( void );
+void DMAC_0_Handler ( void );
+void DMAC_1_Handler ( void );
+void DMAC_2_Handler ( void );
+void DMAC_3_Handler ( void );
+void DMAC_4_Handler ( void );
+void EVSYS_0_Handler ( void );
+void EVSYS_1_Handler ( void );
+void EVSYS_2_Handler ( void );
+void EVSYS_3_Handler ( void );
+void EVSYS_4_Handler ( void );
+void PAC_Handler ( void );
+void TAL_0_Handler ( void );
+void TAL_1_Handler ( void );
+void RAMECC_Handler ( void );
+void SERCOM0_0_Handler ( void );
+void SERCOM0_1_Handler ( void );
+void SERCOM0_2_Handler ( void );
+void SERCOM0_3_Handler ( void );
+void SERCOM1_0_Handler ( void );
+void SERCOM1_1_Handler ( void );
+void SERCOM1_2_Handler ( void );
+void SERCOM1_3_Handler ( void );
+void SERCOM2_0_Handler ( void );
+void SERCOM2_1_Handler ( void );
+void SERCOM2_2_Handler ( void );
+void SERCOM2_3_Handler ( void );
+void SERCOM3_0_Handler ( void );
+void SERCOM3_1_Handler ( void );
+void SERCOM3_2_Handler ( void );
+void SERCOM3_3_Handler ( void );
+void SERCOM4_0_Handler ( void );
+void SERCOM4_1_Handler ( void );
+void SERCOM4_2_Handler ( void );
+void SERCOM4_3_Handler ( void );
+void SERCOM5_0_Handler ( void );
+void SERCOM5_1_Handler ( void );
+void SERCOM5_2_Handler ( void );
+void SERCOM5_3_Handler ( void );
+void SERCOM6_0_Handler ( void );
+void SERCOM6_1_Handler ( void );
+void SERCOM6_2_Handler ( void );
+void SERCOM6_3_Handler ( void );
+void SERCOM7_0_Handler ( void );
+void SERCOM7_1_Handler ( void );
+void SERCOM7_2_Handler ( void );
+void SERCOM7_3_Handler ( void );
+void CAN0_Handler ( void );
+void CAN1_Handler ( void );
+void USB_0_Handler ( void );
+void USB_1_Handler ( void );
+void USB_2_Handler ( void );
+void USB_3_Handler ( void );
+void GMAC_Handler ( void );
+void TCC0_0_Handler ( void );
+void TCC0_1_Handler ( void );
+void TCC0_2_Handler ( void );
+void TCC0_3_Handler ( void );
+void TCC0_4_Handler ( void );
+void TCC0_5_Handler ( void );
+void TCC0_6_Handler ( void );
+void TCC1_0_Handler ( void );
+void TCC1_1_Handler ( void );
+void TCC1_2_Handler ( void );
+void TCC1_3_Handler ( void );
+void TCC1_4_Handler ( void );
+void TCC2_0_Handler ( void );
+void TCC2_1_Handler ( void );
+void TCC2_2_Handler ( void );
+void TCC2_3_Handler ( void );
+void TCC3_0_Handler ( void );
+void TCC3_1_Handler ( void );
+void TCC3_2_Handler ( void );
+void TCC4_0_Handler ( void );
+void TCC4_1_Handler ( void );
+void TCC4_2_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void PDEC_0_Handler ( void );
+void PDEC_1_Handler ( void );
+void PDEC_2_Handler ( void );
+void ADC0_0_Handler ( void );
+void ADC0_1_Handler ( void );
+void ADC1_0_Handler ( void );
+void ADC1_1_Handler ( void );
+void AC_Handler ( void );
+void DAC_0_Handler ( void );
+void DAC_1_Handler ( void );
+void DAC_2_Handler ( void );
+void DAC_3_Handler ( void );
+void DAC_4_Handler ( void );
+void I2S_Handler ( void );
+void PCC_Handler ( void );
+void AES_Handler ( void );
+void TRNG_Handler ( void );
+void ICM_Handler ( void );
+void PUKCC_Handler ( void );
+void QSPI_Handler ( void );
+void SDHC0_Handler ( void );
+void SDHC1_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM4_REV 1 /*!< Core revision r0p1 */
+#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same54.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */
+/* ************************************************************************** */
+/** \defgroup SAME54N20A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tal.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+/** \defgroup SAME54N20A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sdhc1.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sercom6.h"
+#include "instance/sercom7.h"
+#include "instance/supc.h"
+#include "instance/tal.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+/** \defgroup SAME54N20A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT 36 /**< \brief Port Module (PORT) */
+#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */
+#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
+#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */
+#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC 72 /**< \brief Analog Comparators (AC) */
+#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
+#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
+#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
+#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */
+
+#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+/** \defgroup SAME54N20A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES (0x42002400) /**< \brief (AES) APB Base Address */
+#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
+#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */
+#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */
+#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
+#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */
+#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
+
+#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
+#define AES_INSTS { AES } /**< \brief (AES) Instances List */
+
+#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
+#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */
+#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
+#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
+
+#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
+#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
+
+#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
+
+#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
+
+#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */
+
+#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
+#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
+
+#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
+
+#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
+#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
+
+#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
+
+#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
+
+#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
+
+#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
+
+#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
+#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
+#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
+
+#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */
+#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */
+#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */
+
+#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
+
+#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+/** \defgroup SAME54N20A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same54n20a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */
+#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */
+#define FLASH_PAGE_SIZE 512
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 512
+#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL_(0x61840002)
+#define ADC0_TOUCH_LINES_NUM 32
+#define PORT_GROUPS 3
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAME54N20A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME54N20A_H */
diff --git a/GPIO/ATSAME54/include/same54p19a.h b/GPIO/ATSAME54/include/same54p19a.h
new file mode 100644
index 0000000..83e147f
--- /dev/null
+++ b/GPIO/ATSAME54/include/same54p19a.h
@@ -0,0 +1,1149 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME54P19A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54P19A_
+#define _SAME54P19A_
+
+/**
+ * \ingroup SAME54_definitions
+ * \addtogroup SAME54P19A_definitions SAME54P19A definitions
+ * This file defines all structures and symbols for SAME54P19A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+ #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L_(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x) x /**< Assembler: Long integer literal constant value */
+#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+/** \defgroup SAME54P19A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAME54P19A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAME54P19A Power Manager (PM) */
+ MCLK_IRQn = 1, /**< 1 SAME54P19A Main Clock (MCLK) */
+ OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+ OSC32KCTRL_IRQn = 7, /**< 7 SAME54P19A 32kHz Oscillators Control (OSC32KCTRL) */
+ SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+ SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */
+ WDT_IRQn = 10, /**< 10 SAME54P19A Watchdog Timer (WDT) */
+ RTC_IRQn = 11, /**< 11 SAME54P19A Real-Time Counter (RTC) */
+ EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_15 */
+ FREQM_IRQn = 28, /**< 28 SAME54P19A Frequency Meter (FREQM) */
+ NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+ PAC_IRQn = 41, /**< 41 SAME54P19A Peripheral Access Controller (PAC) */
+ TAL_0_IRQn = 42, /**< 42 SAME54P19A Trigger Allocator (TAL): TAL_BRK */
+ TAL_1_IRQn = 43, /**< 43 SAME54P19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */
+ RAMECC_IRQn = 45, /**< 45 SAME54P19A RAM ECC (RAMECC) */
+ SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+ CAN0_IRQn = 78, /**< 78 SAME54P19A Control Area Network 0 (CAN0) */
+ CAN1_IRQn = 79, /**< 79 SAME54P19A Control Area Network 1 (CAN1) */
+ USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+ USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB): USB_SOF_HSOF */
+ USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+ USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+ GMAC_IRQn = 84, /**< 84 SAME54P19A Ethernet MAC (GMAC) */
+ TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+ TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+ TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+ TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+ TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+ TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */
+ TC0_IRQn = 107, /**< 107 SAME54P19A Basic Timer Counter 0 (TC0) */
+ TC1_IRQn = 108, /**< 108 SAME54P19A Basic Timer Counter 1 (TC1) */
+ TC2_IRQn = 109, /**< 109 SAME54P19A Basic Timer Counter 2 (TC2) */
+ TC3_IRQn = 110, /**< 110 SAME54P19A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 111, /**< 111 SAME54P19A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 112, /**< 112 SAME54P19A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 113, /**< 113 SAME54P19A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 114, /**< 114 SAME54P19A Basic Timer Counter 7 (TC7) */
+ PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+ PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC): PDEC_MC_0 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC): PDEC_MC_1 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */
+ ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */
+ ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */
+ ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */
+ AC_IRQn = 122, /**< 122 SAME54P19A Analog Comparators (AC) */
+ DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+ DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */
+ DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */
+ DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */
+ DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */
+ I2S_IRQn = 128, /**< 128 SAME54P19A Inter-IC Sound Interface (I2S) */
+ PCC_IRQn = 129, /**< 129 SAME54P19A Parallel Capture Controller (PCC) */
+ AES_IRQn = 130, /**< 130 SAME54P19A Advanced Encryption Standard (AES) */
+ TRNG_IRQn = 131, /**< 131 SAME54P19A True Random Generator (TRNG) */
+ ICM_IRQn = 132, /**< 132 SAME54P19A Integrity Check Monitor (ICM) */
+ PUKCC_IRQn = 133, /**< 133 SAME54P19A PUblic-Key Cryptography Controller (PUKCC) */
+ QSPI_IRQn = 134, /**< 134 SAME54P19A Quad SPI interface (QSPI) */
+ SDHC0_IRQn = 135, /**< 135 SAME54P19A SD/MMC Host Controller 0 (SDHC0) */
+ SDHC1_IRQn = 136, /**< 136 SAME54P19A SD/MMC Host Controller 1 (SDHC1) */
+
+ PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnMCLK_Handler; /* 1 Main Clock */
+ void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
+ void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
+ void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
+ void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
+ void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
+ void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
+ void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
+ void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
+ void* pfnWDT_Handler; /* 10 Watchdog Timer */
+ void* pfnRTC_Handler; /* 11 Real-Time Counter */
+ void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
+ void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
+ void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
+ void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
+ void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
+ void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
+ void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
+ void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
+ void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
+ void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
+ void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
+ void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
+ void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
+ void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
+ void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
+ void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
+ void* pfnFREQM_Handler; /* 28 Frequency Meter */
+ void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
+ void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
+ void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
+ void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
+ void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
+ void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
+ void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
+ void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
+ void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
+ void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
+ void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
+ void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
+ void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
+ void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */
+ void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */
+ void* pvReserved44;
+ void* pfnRAMECC_Handler; /* 45 RAM ECC */
+ void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
+ void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
+ void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
+ void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
+ void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
+ void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
+ void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
+ void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
+ void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
+ void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
+ void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
+ void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
+ void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
+ void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
+ void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
+ void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
+ void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
+ void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
+ void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
+ void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
+ void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
+ void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
+ void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
+ void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
+ void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
+ void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
+ void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
+ void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
+ void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
+ void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
+ void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
+ void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
+ void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
+ void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
+ void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
+ void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
+ void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
+ void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
+ void* pfnGMAC_Handler; /* 84 Ethernet MAC */
+ void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
+ void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
+ void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
+ void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
+ void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
+ void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
+ void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
+ void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
+ void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
+ void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
+ void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
+ void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
+ void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
+ void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
+ void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
+ void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
+ void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
+ void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
+ void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
+ void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
+ void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
+ void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
+ void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
+ void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
+ void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
+ void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
+ void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
+ void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
+ void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
+ void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
+ void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
+ void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
+ void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
+ void* pfnAC_Handler; /* 122 Analog Comparators */
+ void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
+ void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
+ void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
+ void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
+ void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
+ void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
+ void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
+ void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
+ void* pfnTRNG_Handler; /* 131 True Random Generator */
+ void* pfnICM_Handler; /* 132 Integrity Check Monitor */
+ void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
+ void* pfnQSPI_Handler; /* 134 Quad SPI interface */
+ void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
+ void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void MCLK_Handler ( void );
+void OSCCTRL_0_Handler ( void );
+void OSCCTRL_1_Handler ( void );
+void OSCCTRL_2_Handler ( void );
+void OSCCTRL_3_Handler ( void );
+void OSCCTRL_4_Handler ( void );
+void OSC32KCTRL_Handler ( void );
+void SUPC_0_Handler ( void );
+void SUPC_1_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_0_Handler ( void );
+void EIC_1_Handler ( void );
+void EIC_2_Handler ( void );
+void EIC_3_Handler ( void );
+void EIC_4_Handler ( void );
+void EIC_5_Handler ( void );
+void EIC_6_Handler ( void );
+void EIC_7_Handler ( void );
+void EIC_8_Handler ( void );
+void EIC_9_Handler ( void );
+void EIC_10_Handler ( void );
+void EIC_11_Handler ( void );
+void EIC_12_Handler ( void );
+void EIC_13_Handler ( void );
+void EIC_14_Handler ( void );
+void EIC_15_Handler ( void );
+void FREQM_Handler ( void );
+void NVMCTRL_0_Handler ( void );
+void NVMCTRL_1_Handler ( void );
+void DMAC_0_Handler ( void );
+void DMAC_1_Handler ( void );
+void DMAC_2_Handler ( void );
+void DMAC_3_Handler ( void );
+void DMAC_4_Handler ( void );
+void EVSYS_0_Handler ( void );
+void EVSYS_1_Handler ( void );
+void EVSYS_2_Handler ( void );
+void EVSYS_3_Handler ( void );
+void EVSYS_4_Handler ( void );
+void PAC_Handler ( void );
+void TAL_0_Handler ( void );
+void TAL_1_Handler ( void );
+void RAMECC_Handler ( void );
+void SERCOM0_0_Handler ( void );
+void SERCOM0_1_Handler ( void );
+void SERCOM0_2_Handler ( void );
+void SERCOM0_3_Handler ( void );
+void SERCOM1_0_Handler ( void );
+void SERCOM1_1_Handler ( void );
+void SERCOM1_2_Handler ( void );
+void SERCOM1_3_Handler ( void );
+void SERCOM2_0_Handler ( void );
+void SERCOM2_1_Handler ( void );
+void SERCOM2_2_Handler ( void );
+void SERCOM2_3_Handler ( void );
+void SERCOM3_0_Handler ( void );
+void SERCOM3_1_Handler ( void );
+void SERCOM3_2_Handler ( void );
+void SERCOM3_3_Handler ( void );
+void SERCOM4_0_Handler ( void );
+void SERCOM4_1_Handler ( void );
+void SERCOM4_2_Handler ( void );
+void SERCOM4_3_Handler ( void );
+void SERCOM5_0_Handler ( void );
+void SERCOM5_1_Handler ( void );
+void SERCOM5_2_Handler ( void );
+void SERCOM5_3_Handler ( void );
+void SERCOM6_0_Handler ( void );
+void SERCOM6_1_Handler ( void );
+void SERCOM6_2_Handler ( void );
+void SERCOM6_3_Handler ( void );
+void SERCOM7_0_Handler ( void );
+void SERCOM7_1_Handler ( void );
+void SERCOM7_2_Handler ( void );
+void SERCOM7_3_Handler ( void );
+void CAN0_Handler ( void );
+void CAN1_Handler ( void );
+void USB_0_Handler ( void );
+void USB_1_Handler ( void );
+void USB_2_Handler ( void );
+void USB_3_Handler ( void );
+void GMAC_Handler ( void );
+void TCC0_0_Handler ( void );
+void TCC0_1_Handler ( void );
+void TCC0_2_Handler ( void );
+void TCC0_3_Handler ( void );
+void TCC0_4_Handler ( void );
+void TCC0_5_Handler ( void );
+void TCC0_6_Handler ( void );
+void TCC1_0_Handler ( void );
+void TCC1_1_Handler ( void );
+void TCC1_2_Handler ( void );
+void TCC1_3_Handler ( void );
+void TCC1_4_Handler ( void );
+void TCC2_0_Handler ( void );
+void TCC2_1_Handler ( void );
+void TCC2_2_Handler ( void );
+void TCC2_3_Handler ( void );
+void TCC3_0_Handler ( void );
+void TCC3_1_Handler ( void );
+void TCC3_2_Handler ( void );
+void TCC4_0_Handler ( void );
+void TCC4_1_Handler ( void );
+void TCC4_2_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void PDEC_0_Handler ( void );
+void PDEC_1_Handler ( void );
+void PDEC_2_Handler ( void );
+void ADC0_0_Handler ( void );
+void ADC0_1_Handler ( void );
+void ADC1_0_Handler ( void );
+void ADC1_1_Handler ( void );
+void AC_Handler ( void );
+void DAC_0_Handler ( void );
+void DAC_1_Handler ( void );
+void DAC_2_Handler ( void );
+void DAC_3_Handler ( void );
+void DAC_4_Handler ( void );
+void I2S_Handler ( void );
+void PCC_Handler ( void );
+void AES_Handler ( void );
+void TRNG_Handler ( void );
+void ICM_Handler ( void );
+void PUKCC_Handler ( void );
+void QSPI_Handler ( void );
+void SDHC0_Handler ( void );
+void SDHC1_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM4_REV 1 /*!< Core revision r0p1 */
+#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same54.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */
+/* ************************************************************************** */
+/** \defgroup SAME54P19A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tal.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+/** \defgroup SAME54P19A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sdhc1.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sercom6.h"
+#include "instance/sercom7.h"
+#include "instance/supc.h"
+#include "instance/tal.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+/** \defgroup SAME54P19A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT 36 /**< \brief Port Module (PORT) */
+#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */
+#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
+#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */
+#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC 72 /**< \brief Analog Comparators (AC) */
+#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
+#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
+#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
+#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */
+
+#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+/** \defgroup SAME54P19A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES (0x42002400) /**< \brief (AES) APB Base Address */
+#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
+#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */
+#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */
+#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
+#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */
+#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
+
+#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
+#define AES_INSTS { AES } /**< \brief (AES) Instances List */
+
+#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
+#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */
+#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
+#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
+
+#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
+#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
+
+#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
+
+#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
+
+#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */
+
+#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
+#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
+
+#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
+
+#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
+#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
+
+#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
+
+#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
+
+#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
+
+#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
+
+#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
+#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
+#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
+
+#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */
+#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */
+#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */
+
+#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
+
+#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+/** \defgroup SAME54P19A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same54p19a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */
+#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */
+#define FLASH_PAGE_SIZE 512
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 512
+#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL_(0x61840001)
+#define ADC0_TOUCH_LINES_NUM 32
+#define PORT_GROUPS 4
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAME54P19A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME54P19A_H */
diff --git a/GPIO/ATSAME54/include/same54p20a.h b/GPIO/ATSAME54/include/same54p20a.h
new file mode 100644
index 0000000..bd502c4
--- /dev/null
+++ b/GPIO/ATSAME54/include/same54p20a.h
@@ -0,0 +1,1149 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME54P20A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME54P20A_
+#define _SAME54P20A_
+
+/**
+ * \ingroup SAME54_definitions
+ * \addtogroup SAME54P20A_definitions SAME54P20A definitions
+ * This file defines all structures and symbols for SAME54P20A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+ #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L_(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x) x /**< Assembler: Long integer literal constant value */
+#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+/** \defgroup SAME54P20A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAME54P20A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAME54P20A Power Manager (PM) */
+ MCLK_IRQn = 1, /**< 1 SAME54P20A Main Clock (MCLK) */
+ OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+ OSC32KCTRL_IRQn = 7, /**< 7 SAME54P20A 32kHz Oscillators Control (OSC32KCTRL) */
+ SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+ SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */
+ WDT_IRQn = 10, /**< 10 SAME54P20A Watchdog Timer (WDT) */
+ RTC_IRQn = 11, /**< 11 SAME54P20A Real-Time Counter (RTC) */
+ EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_15 */
+ FREQM_IRQn = 28, /**< 28 SAME54P20A Frequency Meter (FREQM) */
+ NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+ PAC_IRQn = 41, /**< 41 SAME54P20A Peripheral Access Controller (PAC) */
+ TAL_0_IRQn = 42, /**< 42 SAME54P20A Trigger Allocator (TAL): TAL_BRK */
+ TAL_1_IRQn = 43, /**< 43 SAME54P20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */
+ RAMECC_IRQn = 45, /**< 45 SAME54P20A RAM ECC (RAMECC) */
+ SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+ CAN0_IRQn = 78, /**< 78 SAME54P20A Control Area Network 0 (CAN0) */
+ CAN1_IRQn = 79, /**< 79 SAME54P20A Control Area Network 1 (CAN1) */
+ USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+ USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB): USB_SOF_HSOF */
+ USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+ USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+ GMAC_IRQn = 84, /**< 84 SAME54P20A Ethernet MAC (GMAC) */
+ TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+ TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+ TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+ TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+ TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+ TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */
+ TC0_IRQn = 107, /**< 107 SAME54P20A Basic Timer Counter 0 (TC0) */
+ TC1_IRQn = 108, /**< 108 SAME54P20A Basic Timer Counter 1 (TC1) */
+ TC2_IRQn = 109, /**< 109 SAME54P20A Basic Timer Counter 2 (TC2) */
+ TC3_IRQn = 110, /**< 110 SAME54P20A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 111, /**< 111 SAME54P20A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 112, /**< 112 SAME54P20A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 113, /**< 113 SAME54P20A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 114, /**< 114 SAME54P20A Basic Timer Counter 7 (TC7) */
+ PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+ PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC): PDEC_MC_0 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC): PDEC_MC_1 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */
+ ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */
+ ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */
+ ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */
+ AC_IRQn = 122, /**< 122 SAME54P20A Analog Comparators (AC) */
+ DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+ DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */
+ DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */
+ DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */
+ DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */
+ I2S_IRQn = 128, /**< 128 SAME54P20A Inter-IC Sound Interface (I2S) */
+ PCC_IRQn = 129, /**< 129 SAME54P20A Parallel Capture Controller (PCC) */
+ AES_IRQn = 130, /**< 130 SAME54P20A Advanced Encryption Standard (AES) */
+ TRNG_IRQn = 131, /**< 131 SAME54P20A True Random Generator (TRNG) */
+ ICM_IRQn = 132, /**< 132 SAME54P20A Integrity Check Monitor (ICM) */
+ PUKCC_IRQn = 133, /**< 133 SAME54P20A PUblic-Key Cryptography Controller (PUKCC) */
+ QSPI_IRQn = 134, /**< 134 SAME54P20A Quad SPI interface (QSPI) */
+ SDHC0_IRQn = 135, /**< 135 SAME54P20A SD/MMC Host Controller 0 (SDHC0) */
+ SDHC1_IRQn = 136, /**< 136 SAME54P20A SD/MMC Host Controller 1 (SDHC1) */
+
+ PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnMCLK_Handler; /* 1 Main Clock */
+ void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
+ void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
+ void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
+ void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
+ void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
+ void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
+ void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
+ void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
+ void* pfnWDT_Handler; /* 10 Watchdog Timer */
+ void* pfnRTC_Handler; /* 11 Real-Time Counter */
+ void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
+ void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
+ void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
+ void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
+ void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
+ void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
+ void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
+ void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
+ void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
+ void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
+ void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
+ void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
+ void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
+ void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
+ void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
+ void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
+ void* pfnFREQM_Handler; /* 28 Frequency Meter */
+ void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
+ void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
+ void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
+ void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
+ void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
+ void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
+ void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
+ void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
+ void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
+ void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
+ void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
+ void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
+ void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
+ void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */
+ void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */
+ void* pvReserved44;
+ void* pfnRAMECC_Handler; /* 45 RAM ECC */
+ void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
+ void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
+ void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
+ void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
+ void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
+ void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
+ void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
+ void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
+ void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
+ void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
+ void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
+ void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
+ void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
+ void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
+ void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
+ void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
+ void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
+ void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
+ void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
+ void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
+ void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
+ void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
+ void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
+ void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
+ void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
+ void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
+ void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
+ void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
+ void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
+ void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
+ void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
+ void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
+ void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
+ void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
+ void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
+ void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
+ void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
+ void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
+ void* pfnGMAC_Handler; /* 84 Ethernet MAC */
+ void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
+ void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
+ void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
+ void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
+ void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
+ void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
+ void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
+ void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
+ void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
+ void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
+ void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
+ void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
+ void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
+ void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
+ void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
+ void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
+ void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
+ void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
+ void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
+ void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
+ void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
+ void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
+ void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
+ void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
+ void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
+ void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
+ void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
+ void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
+ void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
+ void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
+ void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
+ void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
+ void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
+ void* pfnAC_Handler; /* 122 Analog Comparators */
+ void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
+ void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
+ void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
+ void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
+ void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
+ void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
+ void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
+ void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
+ void* pfnTRNG_Handler; /* 131 True Random Generator */
+ void* pfnICM_Handler; /* 132 Integrity Check Monitor */
+ void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
+ void* pfnQSPI_Handler; /* 134 Quad SPI interface */
+ void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
+ void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void MCLK_Handler ( void );
+void OSCCTRL_0_Handler ( void );
+void OSCCTRL_1_Handler ( void );
+void OSCCTRL_2_Handler ( void );
+void OSCCTRL_3_Handler ( void );
+void OSCCTRL_4_Handler ( void );
+void OSC32KCTRL_Handler ( void );
+void SUPC_0_Handler ( void );
+void SUPC_1_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_0_Handler ( void );
+void EIC_1_Handler ( void );
+void EIC_2_Handler ( void );
+void EIC_3_Handler ( void );
+void EIC_4_Handler ( void );
+void EIC_5_Handler ( void );
+void EIC_6_Handler ( void );
+void EIC_7_Handler ( void );
+void EIC_8_Handler ( void );
+void EIC_9_Handler ( void );
+void EIC_10_Handler ( void );
+void EIC_11_Handler ( void );
+void EIC_12_Handler ( void );
+void EIC_13_Handler ( void );
+void EIC_14_Handler ( void );
+void EIC_15_Handler ( void );
+void FREQM_Handler ( void );
+void NVMCTRL_0_Handler ( void );
+void NVMCTRL_1_Handler ( void );
+void DMAC_0_Handler ( void );
+void DMAC_1_Handler ( void );
+void DMAC_2_Handler ( void );
+void DMAC_3_Handler ( void );
+void DMAC_4_Handler ( void );
+void EVSYS_0_Handler ( void );
+void EVSYS_1_Handler ( void );
+void EVSYS_2_Handler ( void );
+void EVSYS_3_Handler ( void );
+void EVSYS_4_Handler ( void );
+void PAC_Handler ( void );
+void TAL_0_Handler ( void );
+void TAL_1_Handler ( void );
+void RAMECC_Handler ( void );
+void SERCOM0_0_Handler ( void );
+void SERCOM0_1_Handler ( void );
+void SERCOM0_2_Handler ( void );
+void SERCOM0_3_Handler ( void );
+void SERCOM1_0_Handler ( void );
+void SERCOM1_1_Handler ( void );
+void SERCOM1_2_Handler ( void );
+void SERCOM1_3_Handler ( void );
+void SERCOM2_0_Handler ( void );
+void SERCOM2_1_Handler ( void );
+void SERCOM2_2_Handler ( void );
+void SERCOM2_3_Handler ( void );
+void SERCOM3_0_Handler ( void );
+void SERCOM3_1_Handler ( void );
+void SERCOM3_2_Handler ( void );
+void SERCOM3_3_Handler ( void );
+void SERCOM4_0_Handler ( void );
+void SERCOM4_1_Handler ( void );
+void SERCOM4_2_Handler ( void );
+void SERCOM4_3_Handler ( void );
+void SERCOM5_0_Handler ( void );
+void SERCOM5_1_Handler ( void );
+void SERCOM5_2_Handler ( void );
+void SERCOM5_3_Handler ( void );
+void SERCOM6_0_Handler ( void );
+void SERCOM6_1_Handler ( void );
+void SERCOM6_2_Handler ( void );
+void SERCOM6_3_Handler ( void );
+void SERCOM7_0_Handler ( void );
+void SERCOM7_1_Handler ( void );
+void SERCOM7_2_Handler ( void );
+void SERCOM7_3_Handler ( void );
+void CAN0_Handler ( void );
+void CAN1_Handler ( void );
+void USB_0_Handler ( void );
+void USB_1_Handler ( void );
+void USB_2_Handler ( void );
+void USB_3_Handler ( void );
+void GMAC_Handler ( void );
+void TCC0_0_Handler ( void );
+void TCC0_1_Handler ( void );
+void TCC0_2_Handler ( void );
+void TCC0_3_Handler ( void );
+void TCC0_4_Handler ( void );
+void TCC0_5_Handler ( void );
+void TCC0_6_Handler ( void );
+void TCC1_0_Handler ( void );
+void TCC1_1_Handler ( void );
+void TCC1_2_Handler ( void );
+void TCC1_3_Handler ( void );
+void TCC1_4_Handler ( void );
+void TCC2_0_Handler ( void );
+void TCC2_1_Handler ( void );
+void TCC2_2_Handler ( void );
+void TCC2_3_Handler ( void );
+void TCC3_0_Handler ( void );
+void TCC3_1_Handler ( void );
+void TCC3_2_Handler ( void );
+void TCC4_0_Handler ( void );
+void TCC4_1_Handler ( void );
+void TCC4_2_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void PDEC_0_Handler ( void );
+void PDEC_1_Handler ( void );
+void PDEC_2_Handler ( void );
+void ADC0_0_Handler ( void );
+void ADC0_1_Handler ( void );
+void ADC1_0_Handler ( void );
+void ADC1_1_Handler ( void );
+void AC_Handler ( void );
+void DAC_0_Handler ( void );
+void DAC_1_Handler ( void );
+void DAC_2_Handler ( void );
+void DAC_3_Handler ( void );
+void DAC_4_Handler ( void );
+void I2S_Handler ( void );
+void PCC_Handler ( void );
+void AES_Handler ( void );
+void TRNG_Handler ( void );
+void ICM_Handler ( void );
+void PUKCC_Handler ( void );
+void QSPI_Handler ( void );
+void SDHC0_Handler ( void );
+void SDHC1_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM4_REV 1 /*!< Core revision r0p1 */
+#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same54.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */
+/* ************************************************************************** */
+/** \defgroup SAME54P20A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/can.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tal.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+/** \defgroup SAME54P20A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/can0.h"
+#include "instance/can1.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sdhc1.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sercom6.h"
+#include "instance/sercom7.h"
+#include "instance/supc.h"
+#include "instance/tal.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+/** \defgroup SAME54P20A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT 36 /**< \brief Port Module (PORT) */
+#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */
+#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
+#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */
+#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC 72 /**< \brief Analog Comparators (AC) */
+#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
+#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
+#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
+#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */
+
+#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+/** \defgroup SAME54P20A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES (0x42002400) /**< \brief (AES) APB Base Address */
+#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
+#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */
+#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */
+#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
+#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */
+#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
+
+#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
+#define AES_INSTS { AES } /**< \brief (AES) Instances List */
+
+#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
+#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */
+#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
+#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
+
+#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
+#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
+
+#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
+
+#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
+
+#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */
+
+#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
+#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
+
+#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */
+#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */
+#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */
+#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */
+#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */
+#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */
+#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */
+#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */
+#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */
+#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */
+#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */
+#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */
+#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */
+#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */
+#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */
+#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */
+#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
+#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
+#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
+#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
+#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
+#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
+#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
+#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
+#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
+
+#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
+#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
+
+#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
+
+#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
+
+#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
+
+#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
+
+#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
+#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
+#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
+
+#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */
+#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */
+#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */
+
+#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
+
+#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+/** \defgroup SAME54P20A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same54p20a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */
+#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */
+#define FLASH_PAGE_SIZE 512
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 512
+#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL_(0x61840000)
+#define ADC0_TOUCH_LINES_NUM 32
+#define PORT_GROUPS 4
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAME54P20A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME54P20A_H */
diff --git a/GPIO/ATSAME54/linker/same54p20a.ld b/GPIO/ATSAME54/linker/same54p20a.ld
new file mode 100644
index 0000000..a677a17
--- /dev/null
+++ b/GPIO/ATSAME54/linker/same54p20a.ld
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2017, Alex Taradov <alex@taradov.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 /* 1M */
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 /* 256k */
+ bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x2000 /* 8k */
+ qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x1000000 /* 16M */
+}
+
+__top_flash = ORIGIN(flash) + LENGTH(flash);
+__top_ram = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(irq_handler_reset)
+
+SECTIONS
+{
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.vectors))
+ *(.text*)
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(4);
+ } > flash
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > ram
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(.ramfunc .ramfunc.*);
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4);
+ _edata = .;
+ } > ram AT > flash
+
+ .bkupram (NOLOAD):
+ {
+ . = ALIGN(16);
+ _bkupram = .;
+ *(.bkupram .bkupram.*);
+ . = ALIGN(16);
+ _ebkupram = .;
+ } > bkupram
+
+ .qspi (NOLOAD):
+ {
+ . = ALIGN(16);
+ _qspi = .;
+ *(.qspi .qspi.*);
+ . = ALIGN(16);
+ _eqspi = .;
+ } > qspi
+
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ PROVIDE(_end = .);
+ } > ram
+
+ PROVIDE(_stack_top = __top_ram - 0);
+}
+
diff --git a/GPIO/ATSAME54/main.c b/GPIO/ATSAME54/main.c
new file mode 100644
index 0000000..85bea1e
--- /dev/null
+++ b/GPIO/ATSAME54/main.c
@@ -0,0 +1,124 @@
+//-----------------------------------------------------------------------------
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "same54.h"
+
+//-----------------------------------------------------------------------------
+static void sys_init(void)
+{
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_RWS(5);
+
+ OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE | OSC32KCTRL_XOSC32K_XTALEN |
+ OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_RUNSTDBY | OSC32KCTRL_XOSC32K_STARTUP(7);
+ while (0 == OSC32KCTRL->STATUS.bit.XOSC32KRDY);
+
+ #define LDR (((unsigned long)F_CPU * 32) / 32768)
+
+ GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_XOSC32K) | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
+
+ GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN;
+ while (0 == (GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg & GCLK_PCHCTRL_CHEN));
+
+ GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL032K].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN;
+ while (0 == (GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL032K].reg & GCLK_PCHCTRL_CHEN));
+
+ OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR % 32) |
+ OSCCTRL_DPLLRATIO_LDR((LDR / 32) - 1);
+ OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 |
+ OSCCTRL_DPLLCTRLB_DIV(1) | OSCCTRL_DPLLCTRLB_WUF | OSCCTRL_DPLLCTRLB_LBYPASS;
+ OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE | OSCCTRL_DPLLCTRLA_RUNSTDBY;
+
+ while (0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK);
+
+ GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_DPLL0) |
+ GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
+}
+
+
+//-----------------------------------------------------------------------------
+__attribute__ ((noinline, section(".ramfunc")))
+void ram_test(void)
+{
+ asm(".align 5");
+// asm("nop");
+// asm("nop");
+
+ while (1)
+ {
+ if (PORT->Group[1].IN.reg & (1 << 4))
+ PORT->Group[0].OUTCLR.reg = (1 << 6);
+ else
+ PORT->Group[0].OUTSET.reg = (1 << 6);
+ }
+}
+
+//-----------------------------------------------------------------------------
+__attribute__ ((noinline, section(".ramfunc")))
+void ram_test1(void)
+{
+ asm(".align 5");
+// asm("nop");
+/*
+ asm("nop");
+ asm("nop");
+ asm("nop");
+*/
+ while (1)
+ {
+ PORT->Group[0].OUTTGL.reg = (1 << 6);
+ }
+}
+
+//-----------------------------------------------------------------------------
+int main(void)
+{
+ sys_init();
+
+ // OUT - A6
+ // IN - B4
+
+ PORT->Group[0].DIRSET.reg = (1 << 6);
+ //PORT->Group[0].CTRL.reg = 0xffffffff;
+ //PORT->Group[0].PINCFG[6].reg = PORT_PINCFG_DRVSTR;
+
+ PORT->Group[1].DIRCLR.reg = (1 << 4);
+ PORT->Group[1].PINCFG[4].reg = PORT_PINCFG_INEN;
+ //PORT->Group[1].CTRL.reg = 0xffffffff;
+
+ CMCC->CTRL.reg = CMCC_CTRL_CEN;
+
+ ram_test();
+
+ asm("nop");
+ asm("nop");
+ asm("nop");
+
+ asm(".align 5");
+// asm("nop");
+// asm("nop");
+ asm("nop");
+ asm("nop");
+
+ asm("nop");
+// asm("nop");
+
+#if 1
+ while (1)
+ {
+ if (PORT->Group[1].IN.reg & (1 << 4))
+ PORT->Group[0].OUTCLR.reg = (1 << 6);
+ else
+ PORT->Group[0].OUTSET.reg = (1 << 6);
+ }
+#else
+ while (1)
+ {
+ PORT->Group[0].OUTTGL.reg = (1 << 6);
+ }
+#endif
+
+ return 0;
+}
+
diff --git a/GPIO/ATSAME54/make/Makefile b/GPIO/ATSAME54/make/Makefile
new file mode 100644
index 0000000..ccbd802
--- /dev/null
+++ b/GPIO/ATSAME54/make/Makefile
@@ -0,0 +1,78 @@
+##############################################################################
+BUILD = build
+BIN = Demo
+
+##############################################################################
+.PHONY: all directory clean size
+
+CC = arm-none-eabi-gcc
+OBJCOPY = arm-none-eabi-objcopy
+SIZE = arm-none-eabi-size
+
+ifeq ($(OS), Windows_NT)
+ MKDIR = gmkdir
+else
+ MKDIR = mkdir
+endif
+
+CFLAGS += -W -Wall --std=gnu11 -Os
+CFLAGS += -fno-diagnostics-show-caret
+CFLAGS += -fdata-sections -ffunction-sections
+CFLAGS += -funsigned-char -funsigned-bitfields
+CFLAGS += -mcpu=cortex-m4 -mthumb
+CFLAGS += -mfloat-abi=softfp -mfpu=fpv4-sp-d16
+CFLAGS += -MD -MP -MT $(BUILD)/$(*F).o -MF $(BUILD)/$(@F).d
+
+LDFLAGS += -mcpu=cortex-m4 -mthumb
+LDFLAGS += -mfloat-abi=softfp -mfpu=fpv4-sp-d16
+LDFLAGS += -Wl,--gc-sections
+LDFLAGS += -Wl,--script=../linker/same54p20a.ld
+
+INCLUDES += \
+ -I../include \
+ -I..
+
+SRCS += \
+ ../main.c \
+ ../startup_same54.c
+
+DEFINES += \
+ -D__SAME54P20A__ \
+ -DDONT_USE_CMSIS_INIT \
+ -DF_CPU=120000000
+
+CFLAGS += $(INCLUDES) $(DEFINES)
+
+OBJS = $(addprefix $(BUILD)/, $(notdir %/$(subst .c,.o, $(SRCS))))
+
+all: directory $(BUILD)/$(BIN).elf $(BUILD)/$(BIN).hex $(BUILD)/$(BIN).bin size
+
+$(BUILD)/$(BIN).elf: $(OBJS)
+ @echo LD $@
+ @$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o $@
+
+$(BUILD)/$(BIN).hex: $(BUILD)/$(BIN).elf
+ @echo OBJCOPY $@
+ @$(OBJCOPY) -O ihex $^ $@
+
+$(BUILD)/$(BIN).bin: $(BUILD)/$(BIN).elf
+ @echo OBJCOPY $@
+ @$(OBJCOPY) -O binary $^ $@
+
+%.o:
+ @echo CC $@
+ @$(CC) $(CFLAGS) $(filter %/$(subst .o,.c,$(notdir $@)), $(SRCS)) -c -o $@
+
+directory:
+ @$(MKDIR) -p $(BUILD)
+
+size: $(BUILD)/$(BIN).elf
+ @echo size:
+ @$(SIZE) -t $^
+
+clean:
+ @echo clean
+ @-rm -rf $(BUILD)
+
+-include $(wildcard $(BUILD)/*.d)
+
diff --git a/GPIO/ATSAME54/startup_same54.c b/GPIO/ATSAME54/startup_same54.c
new file mode 100644
index 0000000..2b13579
--- /dev/null
+++ b/GPIO/ATSAME54/startup_same54.c
@@ -0,0 +1,398 @@
+/*
+ * Copyright (c) 2017, Alex Taradov <alex@taradov.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*- Includes ----------------------------------------------------------------*/
+#include "same54.h"
+
+/*- Definitions -------------------------------------------------------------*/
+#define DUMMY __attribute__ ((weak, alias ("irq_handler_dummy")))
+
+/*- Prototypes --------------------------------------------------------------*/
+void irq_handler_reset(void);
+DUMMY void irq_handler_nmi(void);
+DUMMY void irq_handler_hard_fault(void);
+DUMMY void irq_handler_mm_fault(void);
+DUMMY void irq_handler_bus_fault(void);
+DUMMY void irq_handler_usage_fault(void);
+DUMMY void irq_handler_sv_call(void);
+DUMMY void irq_handler_debug_mon(void);
+DUMMY void irq_handler_pend_sv(void);
+DUMMY void irq_handler_sys_tick(void);
+
+DUMMY void irq_handler_pm(void);
+DUMMY void irq_handler_mclk(void);
+DUMMY void irq_handler_oscctrl_0(void);
+DUMMY void irq_handler_oscctrl_1(void);
+DUMMY void irq_handler_oscctrl_2(void);
+DUMMY void irq_handler_oscctrl_3(void);
+DUMMY void irq_handler_oscctrl_4(void);
+DUMMY void irq_handler_osc32kctrl(void);
+DUMMY void irq_handler_supc_0(void);
+DUMMY void irq_handler_supc_1(void);
+DUMMY void irq_handler_wdt(void);
+DUMMY void irq_handler_rtc(void);
+DUMMY void irq_handler_eic_0(void);
+DUMMY void irq_handler_eic_1(void);
+DUMMY void irq_handler_eic_2(void);
+DUMMY void irq_handler_eic_3(void);
+DUMMY void irq_handler_eic_4(void);
+DUMMY void irq_handler_eic_5(void);
+DUMMY void irq_handler_eic_6(void);
+DUMMY void irq_handler_eic_7(void);
+DUMMY void irq_handler_eic_8(void);
+DUMMY void irq_handler_eic_9(void);
+DUMMY void irq_handler_eic_10(void);
+DUMMY void irq_handler_eic_11(void);
+DUMMY void irq_handler_eic_12(void);
+DUMMY void irq_handler_eic_13(void);
+DUMMY void irq_handler_eic_14(void);
+DUMMY void irq_handler_eic_15(void);
+DUMMY void irq_handler_freqm(void);
+DUMMY void irq_handler_nvmctrl_0(void);
+DUMMY void irq_handler_nvmctrl_1(void);
+DUMMY void irq_handler_dmac_0(void);
+DUMMY void irq_handler_dmac_1(void);
+DUMMY void irq_handler_dmac_2(void);
+DUMMY void irq_handler_dmac_3(void);
+DUMMY void irq_handler_dmac_4(void);
+DUMMY void irq_handler_evsys_0(void);
+DUMMY void irq_handler_evsys_1(void);
+DUMMY void irq_handler_evsys_2(void);
+DUMMY void irq_handler_evsys_3(void);
+DUMMY void irq_handler_evsys_4(void);
+DUMMY void irq_handler_pac(void);
+DUMMY void irq_handler_ramecc(void);
+DUMMY void irq_handler_sercom0_0(void);
+DUMMY void irq_handler_sercom0_1(void);
+DUMMY void irq_handler_sercom0_2(void);
+DUMMY void irq_handler_sercom0_3(void);
+DUMMY void irq_handler_sercom1_0(void);
+DUMMY void irq_handler_sercom1_1(void);
+DUMMY void irq_handler_sercom1_2(void);
+DUMMY void irq_handler_sercom1_3(void);
+DUMMY void irq_handler_sercom2_0(void);
+DUMMY void irq_handler_sercom2_1(void);
+DUMMY void irq_handler_sercom2_2(void);
+DUMMY void irq_handler_sercom2_3(void);
+DUMMY void irq_handler_sercom3_0(void);
+DUMMY void irq_handler_sercom3_1(void);
+DUMMY void irq_handler_sercom3_2(void);
+DUMMY void irq_handler_sercom3_3(void);
+DUMMY void irq_handler_sercom4_0(void);
+DUMMY void irq_handler_sercom4_1(void);
+DUMMY void irq_handler_sercom4_2(void);
+DUMMY void irq_handler_sercom4_3(void);
+DUMMY void irq_handler_sercom5_0(void);
+DUMMY void irq_handler_sercom5_1(void);
+DUMMY void irq_handler_sercom5_2(void);
+DUMMY void irq_handler_sercom5_3(void);
+DUMMY void irq_handler_sercom6_0(void);
+DUMMY void irq_handler_sercom6_1(void);
+DUMMY void irq_handler_sercom6_2(void);
+DUMMY void irq_handler_sercom6_3(void);
+DUMMY void irq_handler_sercom7_0(void);
+DUMMY void irq_handler_sercom7_1(void);
+DUMMY void irq_handler_sercom7_2(void);
+DUMMY void irq_handler_sercom7_3(void);
+DUMMY void irq_handler_can0(void);
+DUMMY void irq_handler_can1(void);
+DUMMY void irq_handler_usb_0(void);
+DUMMY void irq_handler_usb_1(void);
+DUMMY void irq_handler_usb_2(void);
+DUMMY void irq_handler_usb_3(void);
+DUMMY void irq_handler_gmac(void);
+DUMMY void irq_handler_tcc0_0(void);
+DUMMY void irq_handler_tcc0_1(void);
+DUMMY void irq_handler_tcc0_2(void);
+DUMMY void irq_handler_tcc0_3(void);
+DUMMY void irq_handler_tcc0_4(void);
+DUMMY void irq_handler_tcc0_5(void);
+DUMMY void irq_handler_tcc0_6(void);
+DUMMY void irq_handler_tcc1_0(void);
+DUMMY void irq_handler_tcc1_1(void);
+DUMMY void irq_handler_tcc1_2(void);
+DUMMY void irq_handler_tcc1_3(void);
+DUMMY void irq_handler_tcc1_4(void);
+DUMMY void irq_handler_tcc2_0(void);
+DUMMY void irq_handler_tcc2_1(void);
+DUMMY void irq_handler_tcc2_2(void);
+DUMMY void irq_handler_tcc2_3(void);
+DUMMY void irq_handler_tcc3_0(void);
+DUMMY void irq_handler_tcc3_1(void);
+DUMMY void irq_handler_tcc3_2(void);
+DUMMY void irq_handler_tcc4_0(void);
+DUMMY void irq_handler_tcc4_1(void);
+DUMMY void irq_handler_tcc4_2(void);
+DUMMY void irq_handler_tc0(void);
+DUMMY void irq_handler_tc1(void);
+DUMMY void irq_handler_tc2(void);
+DUMMY void irq_handler_tc3(void);
+DUMMY void irq_handler_tc4(void);
+DUMMY void irq_handler_tc5(void);
+DUMMY void irq_handler_tc6(void);
+DUMMY void irq_handler_tc7(void);
+DUMMY void irq_handler_pdec_0(void);
+DUMMY void irq_handler_pdec_1(void);
+DUMMY void irq_handler_pdec_2(void);
+DUMMY void irq_handler_adc0_0(void);
+DUMMY void irq_handler_adc0_1(void);
+DUMMY void irq_handler_adc1_0(void);
+DUMMY void irq_handler_adc1_1(void);
+DUMMY void irq_handler_ac(void);
+DUMMY void irq_handler_dac_0(void);
+DUMMY void irq_handler_dac_1(void);
+DUMMY void irq_handler_dac_2(void);
+DUMMY void irq_handler_dac_3(void);
+DUMMY void irq_handler_dac_4(void);
+DUMMY void irq_handler_i2s(void);
+DUMMY void irq_handler_pcc(void);
+DUMMY void irq_handler_aes(void);
+DUMMY void irq_handler_trng(void);
+DUMMY void irq_handler_icm(void);
+DUMMY void irq_handler_pukcc(void);
+DUMMY void irq_handler_qspi(void);
+DUMMY void irq_handler_sdhc0(void);
+DUMMY void irq_handler_sdhc1(void);
+
+int main(void);
+
+extern void _stack_top(void);
+extern unsigned int _etext;
+extern unsigned int _data;
+extern unsigned int _edata;
+extern unsigned int _bss;
+extern unsigned int _ebss;
+
+/*- Variables ---------------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+__attribute__ ((used, section(".vectors")))
+void (* const vectors[])(void) =
+{
+ &_stack_top, // 0 - Initial Stack Pointer Value
+
+ // Cortex-M4 handlers
+ irq_handler_reset, // 1 - Reset
+ irq_handler_nmi, // 2 - NMI
+ irq_handler_hard_fault, // 3 - Hard Fault
+ irq_handler_mm_fault, // 4 - MM Fault
+ irq_handler_bus_fault, // 5 - Bus Fault
+ irq_handler_usage_fault, // 6 - Usage Fault
+ 0, // 7 - Reserved
+ 0, // 8 - Reserved
+ 0, // 9 - Reserved
+ 0, // 10 - Reserved
+ irq_handler_sv_call, // 11 - SVCall
+ irq_handler_debug_mon, // 12 - Debug
+ 0, // 13 - Reserved
+ irq_handler_pend_sv, // 14 - PendSV
+ irq_handler_sys_tick, // 15 - SysTick
+
+ // Peripheral handlers
+ irq_handler_pm, // 0 - Power Manager
+ irq_handler_mclk, // 1 - Main Clock
+ irq_handler_oscctrl_0, // 2 - Oscillators Control 0 (XOSCFAIL 0, XOSCRDY 0)
+ irq_handler_oscctrl_1, // 3 - Oscillators Control 1 (XOSCFAIL 1, XOSCRDY 1)
+ irq_handler_oscctrl_2, // 4 - Oscillators Control 2 (DFLLLOCKC, DFLLLOCKF,
+ // DFLLOOB, DFLLRCS DFLLRDY)
+ irq_handler_oscctrl_3, // 5 - Oscillators Control 3 (DPLLLCKF 0, DPLLLCKR 0,
+ // DPLLLDRTO 0, DPLLLTO 0)
+ irq_handler_oscctrl_4, // 6 - Oscillators Control 4 (DPLLLCKF 1, DPLLLCKR 1,
+ // DPLLLDRTO 1, DPLLLTO 1)
+ irq_handler_osc32kctrl, // 7 - 32kHz Oscillators Control
+ irq_handler_supc_0, // 8 - Supply Controller 0 (B12SRDY, B33SRDY, BOD12RDY,
+ // BOD33RDY, VCORERDY, VREGRDY)
+ irq_handler_supc_1, // 9 - Supply Controller 1 (BOD12DET, BOD33DET)
+ irq_handler_wdt, // 10 - Watchdog Timer
+ irq_handler_rtc, // 11 - Real-Time Counter
+ irq_handler_eic_0, // 12 - External Interrupt Controller (EXTINT 0)
+ irq_handler_eic_1, // 13 - External Interrupt Controller (EXTINT 1)
+ irq_handler_eic_2, // 14 - External Interrupt Controller (EXTINT 2)
+ irq_handler_eic_3, // 15 - External Interrupt Controller (EXTINT 3)
+ irq_handler_eic_4, // 16 - External Interrupt Controller (EXTINT 4)
+ irq_handler_eic_5, // 17 - External Interrupt Controller (EXTINT 5)
+ irq_handler_eic_6, // 18 - External Interrupt Controller (EXTINT 6)
+ irq_handler_eic_7, // 19 - External Interrupt Controller (EXTINT 7)
+ irq_handler_eic_8, // 20 - External Interrupt Controller (EXTINT 8)
+ irq_handler_eic_9, // 21 - External Interrupt Controller (EXTINT 9)
+ irq_handler_eic_10, // 22 - External Interrupt Controller (EXTINT 10)
+ irq_handler_eic_11, // 23 - External Interrupt Controller (EXTINT 11)
+ irq_handler_eic_12, // 24 - External Interrupt Controller (EXTINT 12)
+ irq_handler_eic_13, // 25 - External Interrupt Controller (EXTINT 13)
+ irq_handler_eic_14, // 26 - External Interrupt Controller (EXTINT 14)
+ irq_handler_eic_15, // 27 - External Interrupt Controller (EXTINT 15)
+ irq_handler_freqm, // 28 - Frequency Meter
+ irq_handler_nvmctrl_0, // 29 - Non-Volatile Memory Controller (0-7)
+ irq_handler_nvmctrl_1, // 30 - Non-Volatile Memory Controller (8-10)
+ irq_handler_dmac_0, // 31 - Direct Memory Access Controller (SUSP_0, TCMPL_0, TERR_0)
+ irq_handler_dmac_1, // 32 - Direct Memory Access Controller (SUSP_1, TCMPL_1, TERR_1)
+ irq_handler_dmac_2, // 33 - Direct Memory Access Controller (SUSP_2, TCMPL_2, TERR_2)
+ irq_handler_dmac_3, // 34 - Direct Memory Access Controller (SUSP_3, TCMPL_3, TERR_3)
+ irq_handler_dmac_4, // 35 - Direct Memory Access Controller (SUSP_x, TCMPL_x, TERR_x)
+ irq_handler_evsys_0, // 36 - Event System Interface (EVD_0, OVR_0)
+ irq_handler_evsys_1, // 37 - Event System Interface (EVD_1, OVR_1)
+ irq_handler_evsys_2, // 38 - Event System Interface (EVD_2, OVR_2)
+ irq_handler_evsys_3, // 39 - Event System Interface (EVD_3, OVR_3)
+ irq_handler_evsys_4, // 40 - Event System Interface (EVD_x, OVR_x)
+ irq_handler_pac, // 41 - Peripheral Access Controller
+ 0, // 42 - Reserved
+ 0, // 43 - Reserved
+ 0, // 44 - Reserved
+ irq_handler_ramecc, // 45 - RAM ECC
+ irq_handler_sercom0_0, // 46 - Serial Communication Interface 0 (0)
+ irq_handler_sercom0_1, // 47 - Serial Communication Interface 0 (1)
+ irq_handler_sercom0_2, // 48 - Serial Communication Interface 0 (2)
+ irq_handler_sercom0_3, // 49 - Serial Communication Interface 0 (3-6)
+ irq_handler_sercom1_0, // 50 - Serial Communication Interface 1 (0)
+ irq_handler_sercom1_1, // 51 - Serial Communication Interface 1 (1)
+ irq_handler_sercom1_2, // 52 - Serial Communication Interface 1 (2)
+ irq_handler_sercom1_3, // 53 - Serial Communication Interface 1 (3-6)
+ irq_handler_sercom2_0, // 54 - Serial Communication Interface 2 (0)
+ irq_handler_sercom2_1, // 55 - Serial Communication Interface 2 (1)
+ irq_handler_sercom2_2, // 56 - Serial Communication Interface 2 (2)
+ irq_handler_sercom2_3, // 57 - Serial Communication Interface 2 (3-6)
+ irq_handler_sercom3_0, // 58 - Serial Communication Interface 3 (0)
+ irq_handler_sercom3_1, // 59 - Serial Communication Interface 3 (1)
+ irq_handler_sercom3_2, // 60 - Serial Communication Interface 3 (2)
+ irq_handler_sercom3_3, // 61 - Serial Communication Interface 3 (3-6)
+ irq_handler_sercom4_0, // 62 - Serial Communication Interface 4 (0)
+ irq_handler_sercom4_1, // 63 - Serial Communication Interface 4 (1)
+ irq_handler_sercom4_2, // 64 - Serial Communication Interface 4 (2)
+ irq_handler_sercom4_3, // 65 - Serial Communication Interface 4 (3-6)
+ irq_handler_sercom5_0, // 66 - Serial Communication Interface 5 (0)
+ irq_handler_sercom5_1, // 67 - Serial Communication Interface 5 (1)
+ irq_handler_sercom5_2, // 68 - Serial Communication Interface 5 (2)
+ irq_handler_sercom5_3, // 69 - Serial Communication Interface 5 (3-6)
+ irq_handler_sercom6_0, // 70 - Serial Communication Interface 6 (0)
+ irq_handler_sercom6_1, // 71 - Serial Communication Interface 6 (1)
+ irq_handler_sercom6_2, // 72 - Serial Communication Interface 6 (2)
+ irq_handler_sercom6_3, // 73 - Serial Communication Interface 6 (3-6)
+ irq_handler_sercom7_0, // 74 - Serial Communication Interface 7 (0)
+ irq_handler_sercom7_1, // 75 - Serial Communication Interface 7 (1)
+ irq_handler_sercom7_2, // 76 - Serial Communication Interface 7 (2)
+ irq_handler_sercom7_3, // 77 - Serial Communication Interface 7 (3-6)
+ irq_handler_can0, // 78 - Control Area Network 0
+ irq_handler_can1, // 79 - Control Area Network 1
+ irq_handler_usb_0, // 80 - Universal Serial Bus (EORSM_DNRSM, EORST_RST,
+ // LPMSUSP_DDISC, LPM_DCONN, MSOF, RAMACER,
+ // RXSTP_TXSTP_x, STALL0_STALL_x, STALL1_x, SUSPEND,
+ // TRFAIL0_TRFAIL_x, TRFAIL1_PERR_x, UPRSM, WAKEUP)
+ irq_handler_usb_1, // 81 - Universal Serial Bus (SOF_HSOF)
+ irq_handler_usb_2, // 82 - Universal Serial Bus (TRCPT0_x)
+ irq_handler_usb_3, // 83 - Universal Serial Bus (TRCPT1_x)
+ irq_handler_gmac, // 84 - Ethernet MAC
+ irq_handler_tcc0_0, // 85 - Timer Counter Control 0
+ irq_handler_tcc0_1, // 86 - Timer Counter Control 0 (MC 0)
+ irq_handler_tcc0_2, // 87 - Timer Counter Control 0 (MC 1)
+ irq_handler_tcc0_3, // 88 - Timer Counter Control 0 (MC 2)
+ irq_handler_tcc0_4, // 89 - Timer Counter Control 0 (MC 3)
+ irq_handler_tcc0_5, // 90 - Timer Counter Control 0 (MC 4)
+ irq_handler_tcc0_6, // 91 - Timer Counter Control 0 (MC 5)
+ irq_handler_tcc1_0, // 92 - Timer Counter Control 1
+ irq_handler_tcc1_1, // 93 - Timer Counter Control 1 (MC 0)
+ irq_handler_tcc1_2, // 94 - Timer Counter Control 1 (MC 1)
+ irq_handler_tcc1_3, // 95 - Timer Counter Control 1 (MC 2)
+ irq_handler_tcc1_4, // 96 - Timer Counter Control 1 (MC 3)
+ irq_handler_tcc2_0, // 97 - Timer Counter Control 2
+ irq_handler_tcc2_1, // 98 - Timer Counter Control 2 (MC 0)
+ irq_handler_tcc2_2, // 99 - Timer Counter Control 2 (MC 1)
+ irq_handler_tcc2_3, // 100 - Timer Counter Control 2 (MC 2)
+ irq_handler_tcc3_0, // 101 - Timer Counter Control 3
+ irq_handler_tcc3_1, // 102 - Timer Counter Control 3 (MC 0)
+ irq_handler_tcc3_2, // 103 - Timer Counter Control 3 (MC 1)
+ irq_handler_tcc4_0, // 104 - Timer Counter Control 3
+ irq_handler_tcc4_1, // 105 - Timer Counter Control 3 (MC 0)
+ irq_handler_tcc4_2, // 106 - Timer Counter Control 3 (MC 1)
+ irq_handler_tc0, // 107 - Basic Timer Counter 0
+ irq_handler_tc1, // 108 - Basic Timer Counter 1
+ irq_handler_tc2, // 109 - Basic Timer Counter 2
+ irq_handler_tc3, // 110 - Basic Timer Counter 3
+ irq_handler_tc4, // 111 - Basic Timer Counter 4
+ irq_handler_tc5, // 112 - Basic Timer Counter 5
+ irq_handler_tc6, // 113 - Basic Timer Counter 6
+ irq_handler_tc7, // 114 - Basic Timer Counter 7
+ irq_handler_pdec_0, // 115 - Quadrature Decoder (DIR_A, ERR_A, OVF, VLC_A)
+ irq_handler_pdec_1, // 116 - Quadrature Decoder (MC 0)
+ irq_handler_pdec_2, // 117 - Quadrature Decoder (MC 1)
+ irq_handler_adc0_0, // 118 - Analog to Digital Converter 0 (OVERRUN, WINMON)
+ irq_handler_adc0_1, // 119 - Analog to Digital Converter 0 (RESRDY)
+ irq_handler_adc1_0, // 120 - Analog to Digital Converter 0 (OVERRUN, WINMON)
+ irq_handler_adc1_1, // 121 - Analog to Digital Converter 0 (RESRDY)
+ irq_handler_ac, // 122 - Analog Comparators
+ irq_handler_dac_0, // 123 - Digital to Analog Converter (OVERRUN_A_x, UNDERRUN_A_x)
+ irq_handler_dac_1, // 124 - Digital to Analog Converter (EMPTY 0)
+ irq_handler_dac_2, // 125 - Digital to Analog Converter (EMPTY 1)
+ irq_handler_dac_3, // 126 - Digital to Analog Converter (RESRDY 0)
+ irq_handler_dac_4, // 127 - Digital to Analog Converter (RESRDY 1)
+ irq_handler_i2s, // 128 - Inter-IC Sound Interface
+ irq_handler_pcc, // 129 - Parallel Capture Controller
+ irq_handler_aes, // 130 - Advanced Encryption Standard
+ irq_handler_trng, // 131 - True Random Generator
+ irq_handler_icm, // 132 - Integrity Check Monitor
+ irq_handler_pukcc, // 133 - PUblic-Key Cryptography Controller
+ irq_handler_qspi, // 134 Quad SPI interface
+ irq_handler_sdhc0, // 135 SD/MMC Host Controller 0
+ irq_handler_sdhc1, // 136 SD/MMC Host Controller 1
+};
+
+/*- Implementations ---------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+void irq_handler_reset(void)
+{
+ unsigned int *src, *dst;
+
+ src = &_etext;
+ dst = &_data;
+ while (dst < &_edata)
+ *dst++ = *src++;
+
+ dst = &_bss;
+ while (dst < &_ebss)
+ *dst++ = 0;
+
+ SCB->VTOR = (uint32_t)vectors;
+
+ // Enable FPU
+ SCB->CPACR |= (0xf << 20);
+ __DSB();
+ __ISB();
+
+ SCB->VTOR = (uint32_t)vectors;
+
+ main();
+
+ while (1);
+}
+
+//-----------------------------------------------------------------------------
+void irq_handler_dummy(void)
+{
+ while (1);
+}
+
diff --git a/index.html b/index.html
index d6df097..e67330e 100644
--- a/index.html
+++ b/index.html
@@ -46,6 +46,13 @@ The GPIO test measures how quickly pins can communicate with a processor core; t
<td>March, 2019</td>
</tr>
+<tr>
+<td>4.616</td>
+<td>ATSAME54</td>
+<td><a href=GPIO/ATSAME54/>SRAM aligned</a></td>
+<td>January, 2021</td>
+</tr>
+
<tr>
<td>4.000</td>
<td>ATxmega8E5</td>
--
GitLab