diff --git a/GPIO/iCE40/README.md b/GPIO/iCE40/README.md deleted file mode 100644 index 5a8c15dbb121aa82ac57307affbd5ba8cd0dda6a..0000000000000000000000000000000000000000 --- a/GPIO/iCE40/README.md +++ /dev/null @@ -1,41 +0,0 @@ -# iCE40 Ring Oscillator Test - -## Dependencies - -- [IceStorm tools](https://github.com/YosysHQ/icestorm) -- [yosys](http://www.clifford.at/yosys/download.html) -- [nextpnr](https://github.com/YosysHQ/nextpnr) - -Install instructions for all of the above tools can be found on the [IceStorm -website](http://bygone.clairexen.net/icestorm/). - -## Building - -The default `make` target synthesizes the design and runs a timing analysis. The target `prog` -programs an available iCEBreaker via USB. - -## Results - -When clocking the FPGA at 24MHz, the resulting ring oscillation is still identifiable as a square -wave. - - - -By 111MHz, it's more of a triangle wave. But still stable and nearly rail to rail. This is the -fastest clock speed that `icetime` approves. - - - -Despite not passing the timing analysis, when the FPGA is clocked at 120MHz no problems seems to -occur. - - - -Even at 129MHz, stable ring oscillation can occur. I (Erik) thought that the first time I ran it I -got a chaotic, aperiodic signal. But I haven't been able to reproduce this so I might have made a -mistake. Still, I'll hold off on declaring this result official. - - - -At faster clock speeds things start to go wrong. Usually there's still a periodic ring oscillation, -just much slower than one would hope. diff --git a/GPIO/iCE40/notes.html b/GPIO/iCE40/notes.html new file mode 100644 index 0000000000000000000000000000000000000000..0124ea590065174e295092e422f5db650b08b524 --- /dev/null +++ b/GPIO/iCE40/notes.html @@ -0,0 +1,92 @@ +<!DOCTYPE html> +<html lang="en"> +<head> +<meta charset="utf-8"> +<title>iCE40 Ring Oscillation Test Notes</title> +</head> +<body link="black" alink="black" vlink="black"> +<font face="bitstream vera sans,arial,helvetica,sans-serif"></font> + +<div style="margin-left:2.5%;margin-right:2.5%"> + + +<center> +<h1>iCE40 Ring Oscillation Test Notes</h1> +</center> + + +<center> +<h2>Dependencies</h2> +</center> + +<ul> + <li><a href="https://github.com/YosysHQ/icestorm">IceStorm tools</a></li> + <li><a href="http://www.clifford.at/yosys/download.html">yosys</a></li> + <li><a href="https://github.com/YosysHQ/nextpnr">nextpnr</a></li> +</ul> + +<p> +Install instructions for all of the above tools can be found on the +<a href="http://bygone.clairexen.net/icestorm/">IceStorm website</a>. +</p> + + + +<center> +<h2>Building</h2> +</center> + +<p> +The default make target synthesizes the design and runs a timing analysis. The target prog programs +an available iCEBreaker via USB. +</p> + + +<center> +<h2>Results</h2> +</center> + +<p> +When clocking the FPGA at 24MHz, the resulting ring oscillation is still identifiable as a square +wave. +</p> + +<center> +<img src="./img/ring_12mhz.png" alt="12MHz"> +</center> + +<p> +By 111MHz, it's more of a triangle wave. But still stable and nearly rail to rail. This is the +fastest clock speed that `icetime` approves. +</p> + +<center> +<img src="./img/ring_55mhz.png" alt="55.5MHz"> +</center> + +<p> +Despite not passing the timing analysis, when the FPGA is clocked at 120MHz no problems seems to +occur. +</p> + +<center> +<img src="./img/ring_60mhz.png" alt="60MHz"> +</center> + +<p> +Even at 129MHz, stable ring oscillation can occur. I (Erik) thought that the first time I ran it I +got a chaotic, aperiodic signal. But I haven't been able to reproduce this so I might have made a +mistake. Still, I'll hold off on declaring this result official. +</p> + +<center> +<img src="./img/ring_64mhz.png" alt="64.5MHz"> +</center> + +<p> +At faster clock speeds things start to go wrong. Usually there's still a periodic ring oscillation, +just much slower than one would hope. +</p> + +</div> +</body> diff --git a/index.html b/index.html index 846ab29c45f0a270b4afb1d359e23543c853bd5a..cbb337138d0dfae6ad62d9d0b93dd7b5a52c66ca 100644 --- a/index.html +++ b/index.html @@ -42,7 +42,7 @@ The GPIO test measures how quickly pins can communicate with a processor core; t <tr> <td>60.00</td> <td>iCE40UP5K</td> -<td>iCEBreaker V1.0e, 120 MHz, <a href=GPIO/iCE40/ring.v>Verilog</a> (<a href=GPIO/iCE40/README.md>notes</a>)</td> +<td>iCEBreaker V1.0e, 120 MHz, <a href=GPIO/iCE40/ring.v>Verilog</a> (<a href=GPIO/iCE40/notes.html>notes</a>)</td> <td>September 2021</td> </tr>