diff --git a/PIDMotorController/.vs/PIDMotorController/v14/.atsuo b/PIDMotorController/.vs/PIDMotorController/v14/.atsuo
index e86d2f4627dd84e8039771b41c0f4239f10a6a1f..15e1fd4c77a8aad4e513a1f0c1022ce8a128d574 100644
Binary files a/PIDMotorController/.vs/PIDMotorController/v14/.atsuo and b/PIDMotorController/.vs/PIDMotorController/v14/.atsuo differ
diff --git a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.elf b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.elf
index d3327ee3bbfa55c8983584d53c4b6749bcd35ff2..41f79f7e01a53f5fe39a7c3bbb76f4c72a0ee6ab 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.elf and b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.elf differ
diff --git a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.hex b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.hex
index 3ef6d9940ed81bc7a41c5fbf62c25ba17b39c632..cd474bb8f794f9ef213d324d1e368f8e886c4284 100644
--- a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.hex
+++ b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.hex
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:00000001FF
diff --git a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.lss b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.lss
index 1376024a6cfd17332ef07dbee3bc32d808a5733c..569b57da114c81ce29fca0cb8090b41934688511 100644
--- a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.lss
+++ b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.lss
@@ -3,31 +3,31 @@ PIDMotorController.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
- 0 .text 000016dc 00000000 00000000 00000074 2**1
+ 0 .text 0000170c 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 1 .data 00000000 00802000 00802000 00001750 2**0
+ 1 .data 00000000 00802000 00802000 00001780 2**0
CONTENTS, ALLOC, LOAD, DATA
- 2 .bss 0000008f 00802000 00802000 00001750 2**0
+ 2 .bss 0000008b 00802000 00802000 00001780 2**0
ALLOC
- 3 .comment 00000030 00000000 00000000 00001750 2**0
+ 3 .comment 00000030 00000000 00000000 00001780 2**0
CONTENTS, READONLY
- 4 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 00001780 2**2
+ 4 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 000017b0 2**2
CONTENTS, READONLY
- 5 .debug_aranges 00000248 00000000 00000000 000017c0 2**0
+ 5 .debug_aranges 00000248 00000000 00000000 000017f0 2**0
CONTENTS, READONLY, DEBUGGING
- 6 .debug_info 00008229 00000000 00000000 00001a08 2**0
+ 6 .debug_info 00008273 00000000 00000000 00001a38 2**0
CONTENTS, READONLY, DEBUGGING
- 7 .debug_abbrev 0000403f 00000000 00000000 00009c31 2**0
+ 7 .debug_abbrev 0000405b 00000000 00000000 00009cab 2**0
CONTENTS, READONLY, DEBUGGING
- 8 .debug_line 000016e5 00000000 00000000 0000dc70 2**0
+ 8 .debug_line 000016cb 00000000 00000000 0000dd06 2**0
CONTENTS, READONLY, DEBUGGING
- 9 .debug_frame 00000620 00000000 00000000 0000f358 2**2
+ 9 .debug_frame 00000628 00000000 00000000 0000f3d4 2**2
CONTENTS, READONLY, DEBUGGING
- 10 .debug_str 000039b1 00000000 00000000 0000f978 2**0
+ 10 .debug_str 000039b4 00000000 00000000 0000f9fc 2**0
CONTENTS, READONLY, DEBUGGING
- 11 .debug_loc 00001369 00000000 00000000 00013329 2**0
+ 11 .debug_loc 000013c2 00000000 00000000 000133b0 2**0
CONTENTS, READONLY, DEBUGGING
- 12 .debug_ranges 00000198 00000000 00000000 00014692 2**0
+ 12 .debug_ranges 00000198 00000000 00000000 00014772 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
@@ -35,8 +35,8 @@ Disassembly of section .text:
00000000 <__vectors>:
0: 0c 94 fe 00 jmp 0x1fc ; 0x1fc <__ctors_end>
4: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
- 8: 0c 94 28 02 jmp 0x450 ; 0x450 <__vector_2>
- c: 0c 94 4d 02 jmp 0x49a ; 0x49a <__vector_3>
+ 8: 0c 94 22 02 jmp 0x444 ; 0x444 <__vector_2>
+ c: 0c 94 47 02 jmp 0x48e ; 0x48e <__vector_3>
10: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
14: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
18: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
@@ -53,7 +53,7 @@ Disassembly of section .text:
44: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
48: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
4c: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
- 50: 0c 94 da 05 jmp 0xbb4 ; 0xbb4 <__vector_20>
+ 50: 0c 94 0b 06 jmp 0xc16 ; 0xc16 <__vector_20>
54: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
58: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
5c: 0c 94 12 01 jmp 0x224 ; 0x224 <__bad_interrupt>
@@ -181,11 +181,11 @@ Disassembly of section .text:
214: 1d 92 st X+, r1
00000216 <.do_clear_bss_start>:
- 216: af 38 cpi r26, 0x8F ; 143
+ 216: ab 38 cpi r26, 0x8B ; 139
218: b2 07 cpc r27, r18
21a: e1 f7 brne .-8 ; 0x214 <.do_clear_bss_loop>
- 21c: 0e 94 0e 05 call 0xa1c ; 0xa1c <main>
- 220: 0c 94 6c 0b jmp 0x16d8 ; 0x16d8 <_exit>
+ 21c: 0e 94 32 05 call 0xa64 ; 0xa64 <main>
+ 220: 0c 94 84 0b jmp 0x1708 ; 0x1708 <_exit>
00000224 <__bad_interrupt>:
224: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
@@ -213,2945 +213,3024 @@ Disassembly of section .text:
adc->CTRLA= 1<<0;//enable ADC
23a: 81 e0 ldi r24, 0x01 ; 1
23c: 80 83 st Z, r24
- adc->CTRLB= ADC_RESOLUTION_12BIT_gc;
- 23e: 11 82 std Z+1, r1 ; 0x01
+ adc->CTRLB= ADC_RESOLUTION_12BIT_gc | ADC_FREERUN_bm;
+ 23e: 88 e0 ldi r24, 0x08 ; 8
+ 240: 81 83 std Z+1, r24 ; 0x01
adc->REFCTRL= ADC_REFSEL_INTVCC_gc;
- 240: 80 e1 ldi r24, 0x10 ; 16
- 242: 82 83 std Z+2, r24 ; 0x02
- adc->PRESCALER= ADC_PRESCALER_DIV128_gc;
- 244: 85 e0 ldi r24, 0x05 ; 5
- 246: 84 83 std Z+4, r24 ; 0x04
+ 242: 80 e1 ldi r24, 0x10 ; 16
+ 244: 82 83 std Z+2, r24 ; 0x02
+ adc->PRESCALER= ADC_PRESCALER_DIV512_gc;
+ 246: 87 e0 ldi r24, 0x07 ; 7
+ 248: 84 83 std Z+4, r24 ; 0x04
//setup ADCChannel
ch->CTRL=ADC_CH_INPUTMODE_DIFFWGAIN_gc | ADC_CH_GAIN_DIV2_gc;
- 248: 8f e1 ldi r24, 0x1F ; 31
- 24a: fa 01 movw r30, r20
- 24c: 80 83 st Z, r24
+ 24a: 8f e1 ldi r24, 0x1F ; 31
+ 24c: fa 01 movw r30, r20
+ 24e: 80 83 st Z, r24
ch->MUXCTRL = ADC_CH_MUXNEG_GND_MODE4_gc | posPin;
- 24e: 27 60 ori r18, 0x07 ; 7
- 250: 21 83 std Z+1, r18 ; 0x01
- 252: 08 95 ret
+ 250: 27 60 ori r18, 0x07 ; 7
+ 252: 21 83 std Z+1, r18 ; 0x01
+ 254: 08 95 ret
-00000254 <r_adc_scan>:
+00000256 <r_adc_scan>:
+ //ch->CTRL = ADC
}
uint16_t r_adc_scan(r_adc_t *r_adc){
- 254: cf 93 push r28
- 256: df 93 push r29
- 258: fc 01 movw r30, r24
- r_adc->ch->CTRL |= 1<<7; //start scan
- 25a: a2 81 ldd r26, Z+2 ; 0x02
- 25c: b3 81 ldd r27, Z+3 ; 0x03
- 25e: 9c 91 ld r25, X
- 260: 90 68 ori r25, 0x80 ; 128
- 262: 9c 93 st X, r25
- while(r_adc->ch->CTRL & (1<<7));//wait for scan to end
- 264: c2 81 ldd r28, Z+2 ; 0x02
- 266: d3 81 ldd r29, Z+3 ; 0x03
- 268: 88 81 ld r24, Y
- 26a: 88 23 and r24, r24
- 26c: ec f3 brlt .-6 ; 0x268 <r_adc_scan+0x14>
- return CONSTRAIN( ((r_adc->ch->RESH<<8) + r_adc->ch->RESL -2018)*1.35 , 0,4095);
- 26e: 6d 81 ldd r22, Y+5 ; 0x05
- 270: 8c 81 ldd r24, Y+4 ; 0x04
- 272: 70 e0 ldi r23, 0x00 ; 0
- 274: 76 2f mov r23, r22
- 276: 66 27 eor r22, r22
- 278: 68 0f add r22, r24
- 27a: 71 1d adc r23, r1
- 27c: 62 5e subi r22, 0xE2 ; 226
- 27e: 77 40 sbci r23, 0x07 ; 7
- 280: 07 2e mov r0, r23
- 282: 00 0c add r0, r0
- 284: 88 0b sbc r24, r24
- 286: 99 0b sbc r25, r25
- 288: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 28c: 2d ec ldi r18, 0xCD ; 205
- 28e: 3c ec ldi r19, 0xCC ; 204
- 290: 4c ea ldi r20, 0xAC ; 172
- 292: 5f e3 ldi r21, 0x3F ; 63
- 294: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 298: 20 e0 ldi r18, 0x00 ; 0
- 29a: 30 e0 ldi r19, 0x00 ; 0
- 29c: a9 01 movw r20, r18
- 29e: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 2a2: 88 23 and r24, r24
- 2a4: b4 f1 brlt .+108 ; 0x312 <r_adc_scan+0xbe>
- 2a6: 6d 81 ldd r22, Y+5 ; 0x05
- 2a8: 8c 81 ldd r24, Y+4 ; 0x04
- 2aa: 70 e0 ldi r23, 0x00 ; 0
- 2ac: 76 2f mov r23, r22
- 2ae: 66 27 eor r22, r22
- 2b0: 68 0f add r22, r24
- 2b2: 71 1d adc r23, r1
- 2b4: 62 5e subi r22, 0xE2 ; 226
- 2b6: 77 40 sbci r23, 0x07 ; 7
- 2b8: 07 2e mov r0, r23
- 2ba: 00 0c add r0, r0
- 2bc: 88 0b sbc r24, r24
- 2be: 99 0b sbc r25, r25
- 2c0: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 2c4: 2d ec ldi r18, 0xCD ; 205
- 2c6: 3c ec ldi r19, 0xCC ; 204
- 2c8: 4c ea ldi r20, 0xAC ; 172
- 2ca: 5f e3 ldi r21, 0x3F ; 63
- 2cc: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 2d0: 20 e0 ldi r18, 0x00 ; 0
- 2d2: 30 ef ldi r19, 0xF0 ; 240
- 2d4: 4f e7 ldi r20, 0x7F ; 127
- 2d6: 55 e4 ldi r21, 0x45 ; 69
- 2d8: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- 2dc: 18 16 cp r1, r24
- 2de: e4 f0 brlt .+56 ; 0x318 <r_adc_scan+0xc4>
- 2e0: 6d 81 ldd r22, Y+5 ; 0x05
- 2e2: 8c 81 ldd r24, Y+4 ; 0x04
- 2e4: 70 e0 ldi r23, 0x00 ; 0
- 2e6: 76 2f mov r23, r22
- 2e8: 66 27 eor r22, r22
- 2ea: 68 0f add r22, r24
- 2ec: 71 1d adc r23, r1
- 2ee: 62 5e subi r22, 0xE2 ; 226
- 2f0: 77 40 sbci r23, 0x07 ; 7
- 2f2: 07 2e mov r0, r23
- 2f4: 00 0c add r0, r0
- 2f6: 88 0b sbc r24, r24
- 2f8: 99 0b sbc r25, r25
- 2fa: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 2fe: 2d ec ldi r18, 0xCD ; 205
- 300: 3c ec ldi r19, 0xCC ; 204
- 302: 4c ea ldi r20, 0xAC ; 172
- 304: 5f e3 ldi r21, 0x3F ; 63
- 306: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 30a: 0e 94 f1 09 call 0x13e2 ; 0x13e2 <__fixunssfsi>
- 30e: cb 01 movw r24, r22
- 310: 05 c0 rjmp .+10 ; 0x31c <r_adc_scan+0xc8>
- 312: 80 e0 ldi r24, 0x00 ; 0
- 314: 90 e0 ldi r25, 0x00 ; 0
- 316: 02 c0 rjmp .+4 ; 0x31c <r_adc_scan+0xc8>
- 318: 8f ef ldi r24, 0xFF ; 255
- 31a: 9f e0 ldi r25, 0x0F ; 15
- 31c: df 91 pop r29
- 31e: cf 91 pop r28
- 320: 08 95 ret
-
-00000322 <clock_init>:
+ 256: cf 93 push r28
+ 258: df 93 push r29
+ //r_adc->ch->CTRL |= 1<<7; //start scan
+ //while(r_adc->ch->CTRL & (1<<7));//wait for scan to end
+ return CONSTRAIN( ((r_adc->ch->RESH<<8) + r_adc->ch->RESL -2018)*1.35 , 1,4095);
+ 25a: fc 01 movw r30, r24
+ 25c: c2 81 ldd r28, Z+2 ; 0x02
+ 25e: d3 81 ldd r29, Z+3 ; 0x03
+ 260: 6d 81 ldd r22, Y+5 ; 0x05
+ 262: 8c 81 ldd r24, Y+4 ; 0x04
+ 264: 70 e0 ldi r23, 0x00 ; 0
+ 266: 76 2f mov r23, r22
+ 268: 66 27 eor r22, r22
+ 26a: 68 0f add r22, r24
+ 26c: 71 1d adc r23, r1
+ 26e: 62 5e subi r22, 0xE2 ; 226
+ 270: 77 40 sbci r23, 0x07 ; 7
+ 272: 07 2e mov r0, r23
+ 274: 00 0c add r0, r0
+ 276: 88 0b sbc r24, r24
+ 278: 99 0b sbc r25, r25
+ 27a: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 27e: 2d ec ldi r18, 0xCD ; 205
+ 280: 3c ec ldi r19, 0xCC ; 204
+ 282: 4c ea ldi r20, 0xAC ; 172
+ 284: 5f e3 ldi r21, 0x3F ; 63
+ 286: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 28a: 20 e0 ldi r18, 0x00 ; 0
+ 28c: 30 e0 ldi r19, 0x00 ; 0
+ 28e: 40 e8 ldi r20, 0x80 ; 128
+ 290: 5f e3 ldi r21, 0x3F ; 63
+ 292: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 296: 88 23 and r24, r24
+ 298: b4 f1 brlt .+108 ; 0x306 <r_adc_scan+0xb0>
+ 29a: 6d 81 ldd r22, Y+5 ; 0x05
+ 29c: 8c 81 ldd r24, Y+4 ; 0x04
+ 29e: 70 e0 ldi r23, 0x00 ; 0
+ 2a0: 76 2f mov r23, r22
+ 2a2: 66 27 eor r22, r22
+ 2a4: 68 0f add r22, r24
+ 2a6: 71 1d adc r23, r1
+ 2a8: 62 5e subi r22, 0xE2 ; 226
+ 2aa: 77 40 sbci r23, 0x07 ; 7
+ 2ac: 07 2e mov r0, r23
+ 2ae: 00 0c add r0, r0
+ 2b0: 88 0b sbc r24, r24
+ 2b2: 99 0b sbc r25, r25
+ 2b4: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 2b8: 2d ec ldi r18, 0xCD ; 205
+ 2ba: 3c ec ldi r19, 0xCC ; 204
+ 2bc: 4c ea ldi r20, 0xAC ; 172
+ 2be: 5f e3 ldi r21, 0x3F ; 63
+ 2c0: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 2c4: 20 e0 ldi r18, 0x00 ; 0
+ 2c6: 30 ef ldi r19, 0xF0 ; 240
+ 2c8: 4f e7 ldi r20, 0x7F ; 127
+ 2ca: 55 e4 ldi r21, 0x45 ; 69
+ 2cc: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 2d0: 18 16 cp r1, r24
+ 2d2: e4 f0 brlt .+56 ; 0x30c <r_adc_scan+0xb6>
+ 2d4: 6d 81 ldd r22, Y+5 ; 0x05
+ 2d6: 8c 81 ldd r24, Y+4 ; 0x04
+ 2d8: 70 e0 ldi r23, 0x00 ; 0
+ 2da: 76 2f mov r23, r22
+ 2dc: 66 27 eor r22, r22
+ 2de: 68 0f add r22, r24
+ 2e0: 71 1d adc r23, r1
+ 2e2: 62 5e subi r22, 0xE2 ; 226
+ 2e4: 77 40 sbci r23, 0x07 ; 7
+ 2e6: 07 2e mov r0, r23
+ 2e8: 00 0c add r0, r0
+ 2ea: 88 0b sbc r24, r24
+ 2ec: 99 0b sbc r25, r25
+ 2ee: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 2f2: 2d ec ldi r18, 0xCD ; 205
+ 2f4: 3c ec ldi r19, 0xCC ; 204
+ 2f6: 4c ea ldi r20, 0xAC ; 172
+ 2f8: 5f e3 ldi r21, 0x3F ; 63
+ 2fa: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 2fe: 0e 94 09 0a call 0x1412 ; 0x1412 <__fixunssfsi>
+ 302: cb 01 movw r24, r22
+ 304: 05 c0 rjmp .+10 ; 0x310 <r_adc_scan+0xba>
+ 306: 81 e0 ldi r24, 0x01 ; 1
+ 308: 90 e0 ldi r25, 0x00 ; 0
+ 30a: 02 c0 rjmp .+4 ; 0x310 <r_adc_scan+0xba>
+ 30c: 8f ef ldi r24, 0xFF ; 255
+ 30e: 9f e0 ldi r25, 0x0F ; 15
+ 310: df 91 pop r29
+ 312: cf 91 pop r28
+ 314: 08 95 ret
+
+00000316 <clock_init>:
#include <avr/io.h>
#include "ATKCLK.h"
void clock_init(void){
OSC.XOSCCTRL = OSC_XOSCSEL_XTAL_256CLK_gc | OSC_FRQRANGE_12TO16_gc; // select external source
- 322: e0 e5 ldi r30, 0x50 ; 80
- 324: f0 e0 ldi r31, 0x00 ; 0
- 326: 83 ec ldi r24, 0xC3 ; 195
- 328: 82 83 std Z+2, r24 ; 0x02
+ 316: e0 e5 ldi r30, 0x50 ; 80
+ 318: f0 e0 ldi r31, 0x00 ; 0
+ 31a: 83 ec ldi r24, 0xC3 ; 195
+ 31c: 82 83 std Z+2, r24 ; 0x02
OSC.CTRL = OSC_XOSCEN_bm; // enable external source
- 32a: 88 e0 ldi r24, 0x08 ; 8
- 32c: 80 83 st Z, r24
+ 31e: 88 e0 ldi r24, 0x08 ; 8
+ 320: 80 83 st Z, r24
while(!(OSC.STATUS & OSC_XOSCRDY_bm)); // wait for external
- 32e: 81 81 ldd r24, Z+1 ; 0x01
- 330: 83 ff sbrs r24, 3
- 332: fd cf rjmp .-6 ; 0x32e <clock_init+0xc>
+ 322: 81 81 ldd r24, Z+1 ; 0x01
+ 324: 83 ff sbrs r24, 3
+ 326: fd cf rjmp .-6 ; 0x322 <clock_init+0xc>
OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | OSC_PLLFAC0_bm | OSC_PLLFAC1_bm; // select external osc for pll, do pll = source * 3
- 334: e0 e5 ldi r30, 0x50 ; 80
- 336: f0 e0 ldi r31, 0x00 ; 0
- 338: 83 ec ldi r24, 0xC3 ; 195
- 33a: 85 83 std Z+5, r24 ; 0x05
+ 328: e0 e5 ldi r30, 0x50 ; 80
+ 32a: f0 e0 ldi r31, 0x00 ; 0
+ 32c: 83 ec ldi r24, 0xC3 ; 195
+ 32e: 85 83 std Z+5, r24 ; 0x05
//OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | OSC_PLLFAC1_bm; // pll = source * 2 for 32MHz std clock
OSC.CTRL |= OSC_PLLEN_bm; // enable PLL
- 33c: 80 81 ld r24, Z
- 33e: 80 61 ori r24, 0x10 ; 16
- 340: 80 83 st Z, r24
+ 330: 80 81 ld r24, Z
+ 332: 80 61 ori r24, 0x10 ; 16
+ 334: 80 83 st Z, r24
while (!(OSC.STATUS & OSC_PLLRDY_bm)); // wait for PLL to be ready
- 342: 81 81 ldd r24, Z+1 ; 0x01
- 344: 84 ff sbrs r24, 4
- 346: fd cf rjmp .-6 ; 0x342 <clock_init+0x20>
+ 336: 81 81 ldd r24, Z+1 ; 0x01
+ 338: 84 ff sbrs r24, 4
+ 33a: fd cf rjmp .-6 ; 0x336 <clock_init+0x20>
CCP = CCP_IOREG_gc; // enable protected register change
- 348: 88 ed ldi r24, 0xD8 ; 216
- 34a: 84 bf out 0x34, r24 ; 52
+ 33c: 88 ed ldi r24, 0xD8 ; 216
+ 33e: 84 bf out 0x34, r24 ; 52
CLK.CTRL = CLK_SCLKSEL_PLL_gc; // switch to PLL for main clock
- 34c: 84 e0 ldi r24, 0x04 ; 4
- 34e: 80 93 40 00 sts 0x0040, r24 ; 0x800040 <__TEXT_REGION_LENGTH__+0x700040>
- 352: 08 95 ret
+ 340: 84 e0 ldi r24, 0x04 ; 4
+ 342: 80 93 40 00 sts 0x0040, r24 ; 0x800040 <__TEXT_REGION_LENGTH__+0x700040>
+ 346: 08 95 ret
-00000354 <set_dac>:
+00000348 <set_dac>:
}
void set_dac( ATK_DAC_CHANNEL_sel channel, uint16_t val){ //set 12 bit dac value
if(channel & ATK_DAC_CHANNEL_0){
- 354: 80 ff sbrs r24, 0
- 356: 09 c0 rjmp .+18 ; 0x36a <set_dac+0x16>
+ 348: 80 ff sbrs r24, 0
+ 34a: 09 c0 rjmp .+18 ; 0x35e <set_dac+0x16>
while(!(DACB.STATUS & DAC_CH0DRE_bm));
- 358: e0 e2 ldi r30, 0x20 ; 32
- 35a: f3 e0 ldi r31, 0x03 ; 3
- 35c: 95 81 ldd r25, Z+5 ; 0x05
- 35e: 90 ff sbrs r25, 0
- 360: fd cf rjmp .-6 ; 0x35c <set_dac+0x8>
+ 34c: e0 e2 ldi r30, 0x20 ; 32
+ 34e: f3 e0 ldi r31, 0x03 ; 3
+ 350: 95 81 ldd r25, Z+5 ; 0x05
+ 352: 90 ff sbrs r25, 0
+ 354: fd cf rjmp .-6 ; 0x350 <set_dac+0x8>
DACB.CH0DATA = val;
- 362: 60 93 38 03 sts 0x0338, r22 ; 0x800338 <__TEXT_REGION_LENGTH__+0x700338>
- 366: 70 93 39 03 sts 0x0339, r23 ; 0x800339 <__TEXT_REGION_LENGTH__+0x700339>
+ 356: 60 93 38 03 sts 0x0338, r22 ; 0x800338 <__TEXT_REGION_LENGTH__+0x700338>
+ 35a: 70 93 39 03 sts 0x0339, r23 ; 0x800339 <__TEXT_REGION_LENGTH__+0x700339>
}
if(channel & ATK_DAC_CHANNEL_1){
- 36a: 81 ff sbrs r24, 1
- 36c: 09 c0 rjmp .+18 ; 0x380 <set_dac+0x2c>
+ 35e: 81 ff sbrs r24, 1
+ 360: 09 c0 rjmp .+18 ; 0x374 <set_dac+0x2c>
while(!(DACB.STATUS & DAC_CH1DRE_bm));
- 36e: e0 e2 ldi r30, 0x20 ; 32
- 370: f3 e0 ldi r31, 0x03 ; 3
- 372: 85 81 ldd r24, Z+5 ; 0x05
- 374: 81 ff sbrs r24, 1
- 376: fd cf rjmp .-6 ; 0x372 <set_dac+0x1e>
+ 362: e0 e2 ldi r30, 0x20 ; 32
+ 364: f3 e0 ldi r31, 0x03 ; 3
+ 366: 85 81 ldd r24, Z+5 ; 0x05
+ 368: 81 ff sbrs r24, 1
+ 36a: fd cf rjmp .-6 ; 0x366 <set_dac+0x1e>
DACB.CH1DATA = val;
- 378: 60 93 3a 03 sts 0x033A, r22 ; 0x80033a <__TEXT_REGION_LENGTH__+0x70033a>
- 37c: 70 93 3b 03 sts 0x033B, r23 ; 0x80033b <__TEXT_REGION_LENGTH__+0x70033b>
- 380: 08 95 ret
+ 36c: 60 93 3a 03 sts 0x033A, r22 ; 0x80033a <__TEXT_REGION_LENGTH__+0x70033a>
+ 370: 70 93 3b 03 sts 0x033B, r23 ; 0x80033b <__TEXT_REGION_LENGTH__+0x70033b>
+ 374: 08 95 ret
-00000382 <dac_begin>:
+00000376 <dac_begin>:
* Author: Ruben Castro
*/
#include <avr/io.h>
#include "ATKDAC.h"
void dac_begin( ATK_DAC_CHANNEL_sel channel){
- 382: cf 93 push r28
- 384: c8 2f mov r28, r24
+ 376: cf 93 push r28
+ 378: c8 2f mov r28, r24
DACB.CTRLC = DAC_REFSEL_AVCC_gc;
- 386: 88 e0 ldi r24, 0x08 ; 8
- 388: 80 93 22 03 sts 0x0322, r24 ; 0x800322 <__TEXT_REGION_LENGTH__+0x700322>
+ 37a: 88 e0 ldi r24, 0x08 ; 8
+ 37c: 80 93 22 03 sts 0x0322, r24 ; 0x800322 <__TEXT_REGION_LENGTH__+0x700322>
if(channel == ATK_DAC_DUAL_CHANNEL){
- 38c: c2 30 cpi r28, 0x02 ; 2
- 38e: 21 f4 brne .+8 ; 0x398 <dac_begin+0x16>
+ 380: c2 30 cpi r28, 0x02 ; 2
+ 382: 21 f4 brne .+8 ; 0x38c <dac_begin+0x16>
DACB.CTRLB = DAC_CHSEL_DUAL_gc;
- 390: 80 e4 ldi r24, 0x40 ; 64
- 392: 80 93 21 03 sts 0x0321, r24 ; 0x800321 <__TEXT_REGION_LENGTH__+0x700321>
- 396: 07 c0 rjmp .+14 ; 0x3a6 <dac_begin+0x24>
+ 384: 80 e4 ldi r24, 0x40 ; 64
+ 386: 80 93 21 03 sts 0x0321, r24 ; 0x800321 <__TEXT_REGION_LENGTH__+0x700321>
+ 38a: 07 c0 rjmp .+14 ; 0x39a <dac_begin+0x24>
}else{
DACB.CTRLB = DAC_CHSEL_SINGLE_gc;
- 398: 10 92 21 03 sts 0x0321, r1 ; 0x800321 <__TEXT_REGION_LENGTH__+0x700321>
+ 38c: 10 92 21 03 sts 0x0321, r1 ; 0x800321 <__TEXT_REGION_LENGTH__+0x700321>
}
if(channel & ATK_DAC_CHANNEL_0 || channel & ATK_DAC_DUAL_CHANNEL){
- 39c: c0 fd sbrc r28, 0
- 39e: 03 c0 rjmp .+6 ; 0x3a6 <dac_begin+0x24>
- 3a0: c1 ff sbrs r28, 1
- 3a2: 23 c0 rjmp .+70 ; 0x3ea <dac_begin+0x68>
- 3a4: 17 c0 rjmp .+46 ; 0x3d4 <dac_begin+0x52>
+ 390: c0 fd sbrc r28, 0
+ 392: 03 c0 rjmp .+6 ; 0x39a <dac_begin+0x24>
+ 394: c1 ff sbrs r28, 1
+ 396: 23 c0 rjmp .+70 ; 0x3de <dac_begin+0x68>
+ 398: 17 c0 rjmp .+46 ; 0x3c8 <dac_begin+0x52>
DACB.CTRLA |= DAC_CH0EN_bm | DAC_ENABLE_bm; //enable output pin 0 - PB2
- 3a6: e0 e2 ldi r30, 0x20 ; 32
- 3a8: f3 e0 ldi r31, 0x03 ; 3
- 3aa: 80 81 ld r24, Z
- 3ac: 85 60 ori r24, 0x05 ; 5
- 3ae: 80 83 st Z, r24
+ 39a: e0 e2 ldi r30, 0x20 ; 32
+ 39c: f3 e0 ldi r31, 0x03 ; 3
+ 39e: 80 81 ld r24, Z
+ 3a0: 85 60 ori r24, 0x05 ; 5
+ 3a2: 80 83 st Z, r24
set_dac(ATK_DAC_CHANNEL_0, 0);
- 3b0: 60 e0 ldi r22, 0x00 ; 0
- 3b2: 70 e0 ldi r23, 0x00 ; 0
- 3b4: 81 e0 ldi r24, 0x01 ; 1
- 3b6: 0e 94 aa 01 call 0x354 ; 0x354 <set_dac>
+ 3a4: 60 e0 ldi r22, 0x00 ; 0
+ 3a6: 70 e0 ldi r23, 0x00 ; 0
+ 3a8: 81 e0 ldi r24, 0x01 ; 1
+ 3aa: 0e 94 a4 01 call 0x348 ; 0x348 <set_dac>
}
if(channel & ATK_DAC_CHANNEL_1 || channel & ATK_DAC_DUAL_CHANNEL){
- 3ba: c1 ff sbrs r28, 1
- 3bc: 16 c0 rjmp .+44 ; 0x3ea <dac_begin+0x68>
+ 3ae: c1 ff sbrs r28, 1
+ 3b0: 16 c0 rjmp .+44 ; 0x3de <dac_begin+0x68>
DACB.CTRLA |= DAC_CH1EN_bm | DAC_ENABLE_bm; //enable output pin 1 - PB3
- 3be: e0 e2 ldi r30, 0x20 ; 32
- 3c0: f3 e0 ldi r31, 0x03 ; 3
- 3c2: 80 81 ld r24, Z
- 3c4: 89 60 ori r24, 0x09 ; 9
- 3c6: 80 83 st Z, r24
+ 3b2: e0 e2 ldi r30, 0x20 ; 32
+ 3b4: f3 e0 ldi r31, 0x03 ; 3
+ 3b6: 80 81 ld r24, Z
+ 3b8: 89 60 ori r24, 0x09 ; 9
+ 3ba: 80 83 st Z, r24
set_dac(ATK_DAC_CHANNEL_1, 0);
- 3c8: 60 e0 ldi r22, 0x00 ; 0
- 3ca: 70 e0 ldi r23, 0x00 ; 0
- 3cc: 82 e0 ldi r24, 0x02 ; 2
- 3ce: 0e 94 aa 01 call 0x354 ; 0x354 <set_dac>
+ 3bc: 60 e0 ldi r22, 0x00 ; 0
+ 3be: 70 e0 ldi r23, 0x00 ; 0
+ 3c0: 82 e0 ldi r24, 0x02 ; 2
+ 3c2: 0e 94 a4 01 call 0x348 ; 0x348 <set_dac>
}
}
- 3d2: 0b c0 rjmp .+22 ; 0x3ea <dac_begin+0x68>
+ 3c6: 0b c0 rjmp .+22 ; 0x3de <dac_begin+0x68>
}else{
DACB.CTRLB = DAC_CHSEL_SINGLE_gc;
}
if(channel & ATK_DAC_CHANNEL_0 || channel & ATK_DAC_DUAL_CHANNEL){
DACB.CTRLA |= DAC_CH0EN_bm | DAC_ENABLE_bm; //enable output pin 0 - PB2
- 3d4: e0 e2 ldi r30, 0x20 ; 32
- 3d6: f3 e0 ldi r31, 0x03 ; 3
- 3d8: 80 81 ld r24, Z
- 3da: 85 60 ori r24, 0x05 ; 5
- 3dc: 80 83 st Z, r24
+ 3c8: e0 e2 ldi r30, 0x20 ; 32
+ 3ca: f3 e0 ldi r31, 0x03 ; 3
+ 3cc: 80 81 ld r24, Z
+ 3ce: 85 60 ori r24, 0x05 ; 5
+ 3d0: 80 83 st Z, r24
set_dac(ATK_DAC_CHANNEL_0, 0);
- 3de: 60 e0 ldi r22, 0x00 ; 0
- 3e0: 70 e0 ldi r23, 0x00 ; 0
- 3e2: 81 e0 ldi r24, 0x01 ; 1
- 3e4: 0e 94 aa 01 call 0x354 ; 0x354 <set_dac>
- 3e8: ea cf rjmp .-44 ; 0x3be <dac_begin+0x3c>
+ 3d2: 60 e0 ldi r22, 0x00 ; 0
+ 3d4: 70 e0 ldi r23, 0x00 ; 0
+ 3d6: 81 e0 ldi r24, 0x01 ; 1
+ 3d8: 0e 94 a4 01 call 0x348 ; 0x348 <set_dac>
+ 3dc: ea cf rjmp .-44 ; 0x3b2 <dac_begin+0x3c>
DACB.CTRLA |= DAC_CH1EN_bm | DAC_ENABLE_bm; //enable output pin 1 - PB3
set_dac(ATK_DAC_CHANNEL_1, 0);
}
}
- 3ea: cf 91 pop r28
- 3ec: 08 95 ret
+ 3de: cf 91 pop r28
+ 3e0: 08 95 ret
-000003ee <ATKEncoder_begin>:
+000003e2 <ATKEncoder_begin>:
tPV = tickPerV;
}
int ATK_EN_getCounter(){
return counter;
}
- 3ee: e1 e4 ldi r30, 0x41 ; 65
- 3f0: f6 e0 ldi r31, 0x06 ; 6
- 3f2: 20 81 ld r18, Z
- 3f4: 29 7f andi r18, 0xF9 ; 249
- 3f6: 20 83 st Z, r18
- 3f8: e0 e4 ldi r30, 0x40 ; 64
- 3fa: f6 e0 ldi r31, 0x06 ; 6
- 3fc: 24 e0 ldi r18, 0x04 ; 4
- 3fe: 21 87 std Z+9, r18 ; 0x09
- 400: 32 e0 ldi r19, 0x02 ; 2
- 402: 32 87 std Z+10, r19 ; 0x0a
- 404: 31 8b std Z+17, r19 ; 0x11
- 406: 23 87 std Z+11, r18 ; 0x0b
- 408: 21 e0 ldi r18, 0x01 ; 1
- 40a: 22 8b std Z+18, r18 ; 0x12
- 40c: 10 92 02 20 sts 0x2002, r1 ; 0x802002 <counter>
- 410: 10 92 03 20 sts 0x2003, r1 ; 0x802003 <counter+0x1>
- 414: 60 93 04 20 sts 0x2004, r22 ; 0x802004 <tPV>
- 418: 70 93 05 20 sts 0x2005, r23 ; 0x802005 <tPV+0x1>
- 41c: 80 93 06 20 sts 0x2006, r24 ; 0x802006 <tPV+0x2>
- 420: 90 93 07 20 sts 0x2007, r25 ; 0x802007 <tPV+0x3>
- 424: 08 95 ret
-
-00000426 <ATK_EN_getValue>:
+ 3e2: e1 e4 ldi r30, 0x41 ; 65
+ 3e4: f6 e0 ldi r31, 0x06 ; 6
+ 3e6: 20 81 ld r18, Z
+ 3e8: 29 7f andi r18, 0xF9 ; 249
+ 3ea: 20 83 st Z, r18
+ 3ec: e0 e4 ldi r30, 0x40 ; 64
+ 3ee: f6 e0 ldi r31, 0x06 ; 6
+ 3f0: 24 e0 ldi r18, 0x04 ; 4
+ 3f2: 21 87 std Z+9, r18 ; 0x09
+ 3f4: 32 e0 ldi r19, 0x02 ; 2
+ 3f6: 32 87 std Z+10, r19 ; 0x0a
+ 3f8: 31 8b std Z+17, r19 ; 0x11
+ 3fa: 23 87 std Z+11, r18 ; 0x0b
+ 3fc: 21 e0 ldi r18, 0x01 ; 1
+ 3fe: 22 8b std Z+18, r18 ; 0x12
+ 400: 10 92 02 20 sts 0x2002, r1 ; 0x802002 <counter>
+ 404: 10 92 03 20 sts 0x2003, r1 ; 0x802003 <counter+0x1>
+ 408: 60 93 04 20 sts 0x2004, r22 ; 0x802004 <tPV>
+ 40c: 70 93 05 20 sts 0x2005, r23 ; 0x802005 <tPV+0x1>
+ 410: 80 93 06 20 sts 0x2006, r24 ; 0x802006 <tPV+0x2>
+ 414: 90 93 07 20 sts 0x2007, r25 ; 0x802007 <tPV+0x3>
+ 418: 08 95 ret
+
+0000041a <ATK_EN_getValue>:
double ATK_EN_getValue(){
return (double)counter/tPV;
- 426: 60 91 02 20 lds r22, 0x2002 ; 0x802002 <counter>
- 42a: 70 91 03 20 lds r23, 0x2003 ; 0x802003 <counter+0x1>
- 42e: 07 2e mov r0, r23
- 430: 00 0c add r0, r0
- 432: 88 0b sbc r24, r24
- 434: 99 0b sbc r25, r25
- 436: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 43a: 20 91 04 20 lds r18, 0x2004 ; 0x802004 <tPV>
- 43e: 30 91 05 20 lds r19, 0x2005 ; 0x802005 <tPV+0x1>
- 442: 40 91 06 20 lds r20, 0x2006 ; 0x802006 <tPV+0x2>
- 446: 50 91 07 20 lds r21, 0x2007 ; 0x802007 <tPV+0x3>
- 44a: 0e 94 78 09 call 0x12f0 ; 0x12f0 <__divsf3>
+ 41a: 60 91 02 20 lds r22, 0x2002 ; 0x802002 <counter>
+ 41e: 70 91 03 20 lds r23, 0x2003 ; 0x802003 <counter+0x1>
+ 422: 07 2e mov r0, r23
+ 424: 00 0c add r0, r0
+ 426: 88 0b sbc r24, r24
+ 428: 99 0b sbc r25, r25
+ 42a: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 42e: 20 91 04 20 lds r18, 0x2004 ; 0x802004 <tPV>
+ 432: 30 91 05 20 lds r19, 0x2005 ; 0x802005 <tPV+0x1>
+ 436: 40 91 06 20 lds r20, 0x2006 ; 0x802006 <tPV+0x2>
+ 43a: 50 91 07 20 lds r21, 0x2007 ; 0x802007 <tPV+0x3>
+ 43e: 0e 94 90 09 call 0x1320 ; 0x1320 <__divsf3>
}
- 44e: 08 95 ret
+ 442: 08 95 ret
-00000450 <__vector_2>:
+00000444 <__vector_2>:
//PC1 is Rising -1
ISR(PORTC_INT0_vect)
{
- 450: 1f 92 push r1
- 452: 0f 92 push r0
- 454: 0f b6 in r0, 0x3f ; 63
- 456: 0f 92 push r0
- 458: 11 24 eor r1, r1
- 45a: 8f 93 push r24
- 45c: 9f 93 push r25
+ 444: 1f 92 push r1
+ 446: 0f 92 push r0
+ 448: 0f b6 in r0, 0x3f ; 63
+ 44a: 0f 92 push r0
+ 44c: 11 24 eor r1, r1
+ 44e: 8f 93 push r24
+ 450: 9f 93 push r25
if(!(PORTC_IN & PIN2_bm)){
- 45e: 80 91 48 06 lds r24, 0x0648 ; 0x800648 <__TEXT_REGION_LENGTH__+0x700648>
- 462: 82 fd sbrc r24, 2
- 464: 0a c0 rjmp .+20 ; 0x47a <__vector_2+0x2a>
+ 452: 80 91 48 06 lds r24, 0x0648 ; 0x800648 <__TEXT_REGION_LENGTH__+0x700648>
+ 456: 82 fd sbrc r24, 2
+ 458: 0a c0 rjmp .+20 ; 0x46e <__vector_2+0x2a>
counter+=10;
- 466: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
- 46a: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
- 46e: 0a 96 adiw r24, 0x0a ; 10
- 470: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
- 474: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
- 478: 09 c0 rjmp .+18 ; 0x48c <__vector_2+0x3c>
+ 45a: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
+ 45e: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
+ 462: 0a 96 adiw r24, 0x0a ; 10
+ 464: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
+ 468: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
+ 46c: 09 c0 rjmp .+18 ; 0x480 <__vector_2+0x3c>
}else{
counter-=10;
- 47a: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
- 47e: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
- 482: 0a 97 sbiw r24, 0x0a ; 10
- 484: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
- 488: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
+ 46e: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
+ 472: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
+ 476: 0a 97 sbiw r24, 0x0a ; 10
+ 478: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
+ 47c: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
}
}
- 48c: 9f 91 pop r25
- 48e: 8f 91 pop r24
- 490: 0f 90 pop r0
- 492: 0f be out 0x3f, r0 ; 63
- 494: 0f 90 pop r0
- 496: 1f 90 pop r1
- 498: 18 95 reti
+ 480: 9f 91 pop r25
+ 482: 8f 91 pop r24
+ 484: 0f 90 pop r0
+ 486: 0f be out 0x3f, r0 ; 63
+ 488: 0f 90 pop r0
+ 48a: 1f 90 pop r1
+ 48c: 18 95 reti
-0000049a <__vector_3>:
+0000048e <__vector_3>:
//PC2 is falling -0
ISR(PORTC_INT1_vect)
{
- 49a: 1f 92 push r1
- 49c: 0f 92 push r0
- 49e: 0f b6 in r0, 0x3f ; 63
- 4a0: 0f 92 push r0
- 4a2: 11 24 eor r1, r1
- 4a4: 8f 93 push r24
- 4a6: 9f 93 push r25
+ 48e: 1f 92 push r1
+ 490: 0f 92 push r0
+ 492: 0f b6 in r0, 0x3f ; 63
+ 494: 0f 92 push r0
+ 496: 11 24 eor r1, r1
+ 498: 8f 93 push r24
+ 49a: 9f 93 push r25
if((PORTC_IN & PIN1_bm)){
- 4a8: 80 91 48 06 lds r24, 0x0648 ; 0x800648 <__TEXT_REGION_LENGTH__+0x700648>
- 4ac: 81 ff sbrs r24, 1
- 4ae: 0a c0 rjmp .+20 ; 0x4c4 <__vector_3+0x2a>
+ 49c: 80 91 48 06 lds r24, 0x0648 ; 0x800648 <__TEXT_REGION_LENGTH__+0x700648>
+ 4a0: 81 ff sbrs r24, 1
+ 4a2: 0a c0 rjmp .+20 ; 0x4b8 <__vector_3+0x2a>
counter+=10;
- 4b0: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
- 4b4: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
- 4b8: 0a 96 adiw r24, 0x0a ; 10
- 4ba: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
- 4be: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
- 4c2: 09 c0 rjmp .+18 ; 0x4d6 <__vector_3+0x3c>
+ 4a4: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
+ 4a8: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
+ 4ac: 0a 96 adiw r24, 0x0a ; 10
+ 4ae: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
+ 4b2: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
+ 4b6: 09 c0 rjmp .+18 ; 0x4ca <__vector_3+0x3c>
}else{
counter-=10;
- 4c4: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
- 4c8: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
- 4cc: 0a 97 sbiw r24, 0x0a ; 10
- 4ce: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
- 4d2: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
+ 4b8: 80 91 02 20 lds r24, 0x2002 ; 0x802002 <counter>
+ 4bc: 90 91 03 20 lds r25, 0x2003 ; 0x802003 <counter+0x1>
+ 4c0: 0a 97 sbiw r24, 0x0a ; 10
+ 4c2: 80 93 02 20 sts 0x2002, r24 ; 0x802002 <counter>
+ 4c6: 90 93 03 20 sts 0x2003, r25 ; 0x802003 <counter+0x1>
}
}
- 4d6: 9f 91 pop r25
- 4d8: 8f 91 pop r24
- 4da: 0f 90 pop r0
- 4dc: 0f be out 0x3f, r0 ; 63
- 4de: 0f 90 pop r0
- 4e0: 1f 90 pop r1
- 4e2: 18 95 reti
-
-000004e4 <currentc_crunch>:
- }
+ 4ca: 9f 91 pop r25
+ 4cc: 8f 91 pop r24
+ 4ce: 0f 90 pop r0
+ 4d0: 0f be out 0x3f, r0 ; 63
+ 4d2: 0f 90 pop r0
+ 4d4: 1f 90 pop r1
+ 4d6: 18 95 reti
+
+000004d8 <currentc_crunch>:
+ #include "ATKBBBIO/RBasic.h"
+ #include "ATKBBBIO/ATKDAC.h"
+ #include <stdlib.h>
+
+
+ double currentc_crunch(currentc_t *cc, double input){
+ 4d8: 2f 92 push r2
+ 4da: 3f 92 push r3
+ 4dc: 4f 92 push r4
+ 4de: 5f 92 push r5
+ 4e0: 6f 92 push r6
+ 4e2: 7f 92 push r7
+ 4e4: 8f 92 push r8
+ 4e6: 9f 92 push r9
+ 4e8: af 92 push r10
+ 4ea: bf 92 push r11
+ 4ec: cf 92 push r12
+ 4ee: df 92 push r13
+ 4f0: ef 92 push r14
+ 4f2: ff 92 push r15
+ 4f4: 0f 93 push r16
+ 4f6: 1f 93 push r17
+ 4f8: cf 93 push r28
+ 4fa: df 93 push r29
+ 4fc: ec 01 movw r28, r24
+ double pValue, iValue;
+ cc->currentError = cc->setpoint - input;
+ 4fe: 9a 01 movw r18, r20
+ 500: ab 01 movw r20, r22
+ 502: 68 a5 ldd r22, Y+40 ; 0x28
+ 504: 79 a5 ldd r23, Y+41 ; 0x29
+ 506: 8a a5 ldd r24, Y+42 ; 0x2a
+ 508: 9b a5 ldd r25, Y+43 ; 0x2b
+ 50a: 0e 94 1e 09 call 0x123c ; 0x123c <__subsf3>
+ 50e: 6b 01 movw r12, r22
+ 510: 7c 01 movw r14, r24
+ 512: 68 8f std Y+24, r22 ; 0x18
+ 514: 79 8f std Y+25, r23 ; 0x19
+ 516: 8a 8f std Y+26, r24 ; 0x1a
+ 518: 9b 8f std Y+27, r25 ; 0x1b
+
+
+ cc->totalError+=cc->currentError* cc->dt;
+ 51a: 28 85 ldd r18, Y+8 ; 0x08
+ 51c: 39 85 ldd r19, Y+9 ; 0x09
+ 51e: 4a 85 ldd r20, Y+10 ; 0x0a
+ 520: 5b 85 ldd r21, Y+11 ; 0x0b
+ 522: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 526: 2c 8d ldd r18, Y+28 ; 0x1c
+ 528: 3d 8d ldd r19, Y+29 ; 0x1d
+ 52a: 4e 8d ldd r20, Y+30 ; 0x1e
+ 52c: 5f 8d ldd r21, Y+31 ; 0x1f
+ 52e: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ 532: 16 2f mov r17, r22
+ 534: 07 2f mov r16, r23
+ 536: b8 2e mov r11, r24
+ 538: a9 2e mov r10, r25
+ cc->totalError = CONSTRAIN(cc->totalError, cc->minTotalError , cc->maxtotalError);
+ 53a: 9c a0 ldd r9, Y+36 ; 0x24
+ 53c: 8d a0 ldd r8, Y+37 ; 0x25
+ 53e: 3e a0 ldd r3, Y+38 ; 0x26
+ 540: 2f a0 ldd r2, Y+39 ; 0x27
+ 542: 29 2d mov r18, r9
+ 544: 38 2d mov r19, r8
+ 546: 43 2d mov r20, r3
+ 548: 52 2d mov r21, r2
+ 54a: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 54e: 88 23 and r24, r24
+ 550: a4 f0 brlt .+40 ; 0x57a <currentc_crunch+0xa2>
+ 552: 98 a0 ldd r9, Y+32 ; 0x20
+ 554: 89 a0 ldd r8, Y+33 ; 0x21
+ 556: 3a a0 ldd r3, Y+34 ; 0x22
+ 558: 2b a0 ldd r2, Y+35 ; 0x23
+ 55a: 29 2d mov r18, r9
+ 55c: 38 2d mov r19, r8
+ 55e: 43 2d mov r20, r3
+ 560: 52 2d mov r21, r2
+ 562: 61 2f mov r22, r17
+ 564: 70 2f mov r23, r16
+ 566: 8b 2d mov r24, r11
+ 568: 9a 2d mov r25, r10
+ 56a: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 56e: 18 16 cp r1, r24
+ 570: 24 f0 brlt .+8 ; 0x57a <currentc_crunch+0xa2>
+ 572: 91 2e mov r9, r17
+ 574: 80 2e mov r8, r16
+ 576: 3b 2c mov r3, r11
+ 578: 2a 2c mov r2, r10
+ 57a: 89 2d mov r24, r9
+ 57c: 98 2d mov r25, r8
+ 57e: a3 2d mov r26, r3
+ 580: b2 2d mov r27, r2
+ 582: 8c 8f std Y+28, r24 ; 0x1c
+ 584: 9d 8f std Y+29, r25 ; 0x1d
+ 586: ae 8f std Y+30, r26 ; 0x1e
+ 588: bf 8f std Y+31, r27 ; 0x1f
+
+ //pValue = Math.abs(currentError) < acceptableRange ? 0: p * currentError;
+ pValue = cc->P * cc->currentError;
+ 58a: 28 81 ld r18, Y
+ 58c: 39 81 ldd r19, Y+1 ; 0x01
+ 58e: 4a 81 ldd r20, Y+2 ; 0x02
+ 590: 5b 81 ldd r21, Y+3 ; 0x03
+ 592: c7 01 movw r24, r14
+ 594: b6 01 movw r22, r12
+ 596: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 59a: 2b 01 movw r4, r22
+ 59c: 3c 01 movw r6, r24
+ iValue = cc->I * cc->totalError;
+ 59e: 2c 81 ldd r18, Y+4 ; 0x04
+ 5a0: 3d 81 ldd r19, Y+5 ; 0x05
+ 5a2: 4e 81 ldd r20, Y+6 ; 0x06
+ 5a4: 5f 81 ldd r21, Y+7 ; 0x07
+ 5a6: 69 2d mov r22, r9
+ 5a8: 78 2d mov r23, r8
+ 5aa: 83 2d mov r24, r3
+ 5ac: 92 2d mov r25, r2
+ 5ae: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 5b2: 4b 01 movw r8, r22
+ 5b4: 5c 01 movw r10, r24
+
- uint8_t currentc_onTarget(currentc_t *cc){ // if on target for more than 50 millis
+ cc->prevError = cc->currentError;
+ 5b6: cc 8a std Y+20, r12 ; 0x14
+ 5b8: dd 8a std Y+21, r13 ; 0x15
+ 5ba: ee 8a std Y+22, r14 ; 0x16
+ 5bc: ff 8a std Y+23, r15 ; 0x17
+ //return pValue + iValue + dValue;
+
+ //check if on target
+ if(abs(cc->currentError) < cc->acceptableRange){
+ 5be: c7 01 movw r24, r14
+ 5c0: b6 01 movw r22, r12
+ 5c2: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ 5c6: 9b 01 movw r18, r22
+ 5c8: 77 23 and r23, r23
+ 5ca: 24 f4 brge .+8 ; 0x5d4 <currentc_crunch+0xfc>
+ 5cc: 22 27 eor r18, r18
+ 5ce: 33 27 eor r19, r19
+ 5d0: 26 1b sub r18, r22
+ 5d2: 37 0b sbc r19, r23
+ 5d4: b9 01 movw r22, r18
+ 5d6: 33 0f add r19, r19
+ 5d8: 88 0b sbc r24, r24
+ 5da: 99 0b sbc r25, r25
+ 5dc: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 5e0: 2c a5 ldd r18, Y+44 ; 0x2c
+ 5e2: 3d a5 ldd r19, Y+45 ; 0x2d
+ 5e4: 4e a5 ldd r20, Y+46 ; 0x2e
+ 5e6: 5f a5 ldd r21, Y+47 ; 0x2f
+ 5e8: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 5ec: 88 23 and r24, r24
+ 5ee: 34 f4 brge .+12 ; 0x5fc <currentc_crunch+0x124>
+ cc->onTargetTicks++;
+ 5f0: 88 a9 ldd r24, Y+48 ; 0x30
+ 5f2: 99 a9 ldd r25, Y+49 ; 0x31
+ 5f4: 01 96 adiw r24, 0x01 ; 1
+ 5f6: 88 ab std Y+48, r24 ; 0x30
+ 5f8: 99 ab std Y+49, r25 ; 0x31
+ 5fa: 02 c0 rjmp .+4 ; 0x600 <currentc_crunch+0x128>
+ }else{
+ cc->onTargetTicks=0;
+ 5fc: 18 aa std Y+48, r1 ; 0x30
+ 5fe: 19 aa std Y+49, r1 ; 0x31
+ }
- return cc->onTargetTicks * cc->dt >0.1;
+
+ return CONSTRAIN(pValue + iValue ,cc->MIN_OUT, cc->MAX_OUT);
+ 600: a5 01 movw r20, r10
+ 602: 94 01 movw r18, r8
+ 604: c3 01 movw r24, r6
+ 606: b2 01 movw r22, r4
+ 608: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ 60c: 16 2f mov r17, r22
+ 60e: 07 2f mov r16, r23
+ 610: b8 2e mov r11, r24
+ 612: a9 2e mov r10, r25
+ 614: 6a 89 ldd r22, Y+18 ; 0x12
+ 616: 7b 89 ldd r23, Y+19 ; 0x13
+ 618: 07 2e mov r0, r23
+ 61a: 00 0c add r0, r0
+ 61c: 88 0b sbc r24, r24
+ 61e: 99 0b sbc r25, r25
+ 620: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 624: d6 2e mov r13, r22
+ 626: e7 2e mov r14, r23
+ 628: f8 2e mov r15, r24
+ 62a: c9 2e mov r12, r25
+ 62c: 26 2f mov r18, r22
+ 62e: 37 2f mov r19, r23
+ 630: 48 2f mov r20, r24
+ 632: 59 2f mov r21, r25
+ 634: 61 2f mov r22, r17
+ 636: 70 2f mov r23, r16
+ 638: 8b 2d mov r24, r11
+ 63a: 9a 2d mov r25, r10
+ 63c: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 640: 88 23 and r24, r24
+ 642: e4 f0 brlt .+56 ; 0x67c <currentc_crunch+0x1a4>
+ 644: 68 89 ldd r22, Y+16 ; 0x10
+ 646: 79 89 ldd r23, Y+17 ; 0x11
+ 648: 07 2e mov r0, r23
+ 64a: 00 0c add r0, r0
+ 64c: 88 0b sbc r24, r24
+ 64e: 99 0b sbc r25, r25
+ 650: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 654: d6 2e mov r13, r22
+ 656: e7 2e mov r14, r23
+ 658: f8 2e mov r15, r24
+ 65a: c9 2e mov r12, r25
+ 65c: 26 2f mov r18, r22
+ 65e: 37 2f mov r19, r23
+ 660: 48 2f mov r20, r24
+ 662: 59 2f mov r21, r25
+ 664: 61 2f mov r22, r17
+ 666: 70 2f mov r23, r16
+ 668: 8b 2d mov r24, r11
+ 66a: 9a 2d mov r25, r10
+ 66c: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 670: 18 16 cp r1, r24
+ 672: 24 f0 brlt .+8 ; 0x67c <currentc_crunch+0x1a4>
+ 674: d1 2e mov r13, r17
+ 676: e0 2e mov r14, r16
+ 678: fb 2c mov r15, r11
+ 67a: ca 2c mov r12, r10
}
- 4e4: 2f 92 push r2
- 4e6: 3f 92 push r3
- 4e8: 4f 92 push r4
- 4ea: 5f 92 push r5
- 4ec: 6f 92 push r6
- 4ee: 7f 92 push r7
- 4f0: 8f 92 push r8
- 4f2: 9f 92 push r9
- 4f4: af 92 push r10
- 4f6: bf 92 push r11
- 4f8: cf 92 push r12
- 4fa: df 92 push r13
- 4fc: ef 92 push r14
- 4fe: ff 92 push r15
- 500: 0f 93 push r16
- 502: 1f 93 push r17
- 504: cf 93 push r28
- 506: df 93 push r29
- 508: ec 01 movw r28, r24
- 50a: 9a 01 movw r18, r20
- 50c: ab 01 movw r20, r22
- 50e: 68 a5 ldd r22, Y+40 ; 0x28
- 510: 79 a5 ldd r23, Y+41 ; 0x29
- 512: 8a a5 ldd r24, Y+42 ; 0x2a
- 514: 9b a5 ldd r25, Y+43 ; 0x2b
- 516: 0e 94 06 09 call 0x120c ; 0x120c <__subsf3>
- 51a: 6b 01 movw r12, r22
- 51c: 7c 01 movw r14, r24
- 51e: 68 8f std Y+24, r22 ; 0x18
- 520: 79 8f std Y+25, r23 ; 0x19
- 522: 8a 8f std Y+26, r24 ; 0x1a
- 524: 9b 8f std Y+27, r25 ; 0x1b
- 526: 28 85 ldd r18, Y+8 ; 0x08
- 528: 39 85 ldd r19, Y+9 ; 0x09
- 52a: 4a 85 ldd r20, Y+10 ; 0x0a
- 52c: 5b 85 ldd r21, Y+11 ; 0x0b
- 52e: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 532: 2c 8d ldd r18, Y+28 ; 0x1c
- 534: 3d 8d ldd r19, Y+29 ; 0x1d
- 536: 4e 8d ldd r20, Y+30 ; 0x1e
- 538: 5f 8d ldd r21, Y+31 ; 0x1f
- 53a: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- 53e: 16 2f mov r17, r22
- 540: 07 2f mov r16, r23
- 542: b8 2e mov r11, r24
- 544: a9 2e mov r10, r25
- 546: 9c a0 ldd r9, Y+36 ; 0x24
- 548: 8d a0 ldd r8, Y+37 ; 0x25
- 54a: 3e a0 ldd r3, Y+38 ; 0x26
- 54c: 2f a0 ldd r2, Y+39 ; 0x27
- 54e: 29 2d mov r18, r9
- 550: 38 2d mov r19, r8
- 552: 43 2d mov r20, r3
- 554: 52 2d mov r21, r2
- 556: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 55a: 88 23 and r24, r24
- 55c: a4 f0 brlt .+40 ; 0x586 <currentc_crunch+0xa2>
- 55e: 98 a0 ldd r9, Y+32 ; 0x20
- 560: 89 a0 ldd r8, Y+33 ; 0x21
- 562: 3a a0 ldd r3, Y+34 ; 0x22
- 564: 2b a0 ldd r2, Y+35 ; 0x23
- 566: 29 2d mov r18, r9
- 568: 38 2d mov r19, r8
- 56a: 43 2d mov r20, r3
- 56c: 52 2d mov r21, r2
- 56e: 61 2f mov r22, r17
- 570: 70 2f mov r23, r16
- 572: 8b 2d mov r24, r11
- 574: 9a 2d mov r25, r10
- 576: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- 57a: 18 16 cp r1, r24
- 57c: 24 f0 brlt .+8 ; 0x586 <currentc_crunch+0xa2>
- 57e: 91 2e mov r9, r17
- 580: 80 2e mov r8, r16
- 582: 3b 2c mov r3, r11
- 584: 2a 2c mov r2, r10
- 586: 89 2d mov r24, r9
- 588: 98 2d mov r25, r8
- 58a: a3 2d mov r26, r3
- 58c: b2 2d mov r27, r2
- 58e: 8c 8f std Y+28, r24 ; 0x1c
- 590: 9d 8f std Y+29, r25 ; 0x1d
- 592: ae 8f std Y+30, r26 ; 0x1e
- 594: bf 8f std Y+31, r27 ; 0x1f
- 596: 28 81 ld r18, Y
- 598: 39 81 ldd r19, Y+1 ; 0x01
- 59a: 4a 81 ldd r20, Y+2 ; 0x02
- 59c: 5b 81 ldd r21, Y+3 ; 0x03
- 59e: c7 01 movw r24, r14
- 5a0: b6 01 movw r22, r12
- 5a2: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 5a6: 2b 01 movw r4, r22
- 5a8: 3c 01 movw r6, r24
- 5aa: 2c 81 ldd r18, Y+4 ; 0x04
- 5ac: 3d 81 ldd r19, Y+5 ; 0x05
- 5ae: 4e 81 ldd r20, Y+6 ; 0x06
- 5b0: 5f 81 ldd r21, Y+7 ; 0x07
- 5b2: 69 2d mov r22, r9
- 5b4: 78 2d mov r23, r8
- 5b6: 83 2d mov r24, r3
- 5b8: 92 2d mov r25, r2
- 5ba: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 5be: 4b 01 movw r8, r22
- 5c0: 5c 01 movw r10, r24
- 5c2: cc 8a std Y+20, r12 ; 0x14
- 5c4: dd 8a std Y+21, r13 ; 0x15
- 5c6: ee 8a std Y+22, r14 ; 0x16
- 5c8: ff 8a std Y+23, r15 ; 0x17
- 5ca: c7 01 movw r24, r14
- 5cc: b6 01 movw r22, r12
- 5ce: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- 5d2: 9b 01 movw r18, r22
- 5d4: 77 23 and r23, r23
- 5d6: 24 f4 brge .+8 ; 0x5e0 <currentc_crunch+0xfc>
- 5d8: 22 27 eor r18, r18
- 5da: 33 27 eor r19, r19
- 5dc: 26 1b sub r18, r22
- 5de: 37 0b sbc r19, r23
- 5e0: b9 01 movw r22, r18
- 5e2: 33 0f add r19, r19
- 5e4: 88 0b sbc r24, r24
- 5e6: 99 0b sbc r25, r25
- 5e8: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 5ec: 2c a5 ldd r18, Y+44 ; 0x2c
- 5ee: 3d a5 ldd r19, Y+45 ; 0x2d
- 5f0: 4e a5 ldd r20, Y+46 ; 0x2e
- 5f2: 5f a5 ldd r21, Y+47 ; 0x2f
- 5f4: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 5f8: 88 23 and r24, r24
- 5fa: 34 f4 brge .+12 ; 0x608 <currentc_crunch+0x124>
- 5fc: 88 a9 ldd r24, Y+48 ; 0x30
- 5fe: 99 a9 ldd r25, Y+49 ; 0x31
- 600: 01 96 adiw r24, 0x01 ; 1
- 602: 88 ab std Y+48, r24 ; 0x30
- 604: 99 ab std Y+49, r25 ; 0x31
- 606: 02 c0 rjmp .+4 ; 0x60c <currentc_crunch+0x128>
- 608: 18 aa std Y+48, r1 ; 0x30
- 60a: 19 aa std Y+49, r1 ; 0x31
- 60c: a5 01 movw r20, r10
- 60e: 94 01 movw r18, r8
- 610: c3 01 movw r24, r6
- 612: b2 01 movw r22, r4
- 614: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- 618: 16 2f mov r17, r22
- 61a: 07 2f mov r16, r23
- 61c: b8 2e mov r11, r24
- 61e: a9 2e mov r10, r25
- 620: 6a 89 ldd r22, Y+18 ; 0x12
- 622: 7b 89 ldd r23, Y+19 ; 0x13
- 624: 07 2e mov r0, r23
- 626: 00 0c add r0, r0
- 628: 88 0b sbc r24, r24
- 62a: 99 0b sbc r25, r25
- 62c: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 630: d6 2e mov r13, r22
- 632: e7 2e mov r14, r23
- 634: f8 2e mov r15, r24
- 636: c9 2e mov r12, r25
- 638: 26 2f mov r18, r22
- 63a: 37 2f mov r19, r23
- 63c: 48 2f mov r20, r24
- 63e: 59 2f mov r21, r25
- 640: 61 2f mov r22, r17
- 642: 70 2f mov r23, r16
- 644: 8b 2d mov r24, r11
- 646: 9a 2d mov r25, r10
- 648: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 64c: 88 23 and r24, r24
- 64e: e4 f0 brlt .+56 ; 0x688 <currentc_crunch+0x1a4>
- 650: 68 89 ldd r22, Y+16 ; 0x10
- 652: 79 89 ldd r23, Y+17 ; 0x11
- 654: 07 2e mov r0, r23
- 656: 00 0c add r0, r0
- 658: 88 0b sbc r24, r24
- 65a: 99 0b sbc r25, r25
- 65c: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 660: d6 2e mov r13, r22
- 662: e7 2e mov r14, r23
- 664: f8 2e mov r15, r24
- 666: c9 2e mov r12, r25
- 668: 26 2f mov r18, r22
- 66a: 37 2f mov r19, r23
- 66c: 48 2f mov r20, r24
- 66e: 59 2f mov r21, r25
- 670: 61 2f mov r22, r17
- 672: 70 2f mov r23, r16
- 674: 8b 2d mov r24, r11
- 676: 9a 2d mov r25, r10
- 678: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- 67c: 18 16 cp r1, r24
- 67e: 24 f0 brlt .+8 ; 0x688 <currentc_crunch+0x1a4>
- 680: d1 2e mov r13, r17
- 682: e0 2e mov r14, r16
- 684: fb 2c mov r15, r11
- 686: ca 2c mov r12, r10
- 688: 6d 2d mov r22, r13
- 68a: 7e 2d mov r23, r14
- 68c: 8f 2d mov r24, r15
- 68e: 9c 2d mov r25, r12
- 690: df 91 pop r29
- 692: cf 91 pop r28
- 694: 1f 91 pop r17
- 696: 0f 91 pop r16
- 698: ff 90 pop r15
- 69a: ef 90 pop r14
- 69c: df 90 pop r13
- 69e: cf 90 pop r12
- 6a0: bf 90 pop r11
- 6a2: af 90 pop r10
- 6a4: 9f 90 pop r9
- 6a6: 8f 90 pop r8
- 6a8: 7f 90 pop r7
- 6aa: 6f 90 pop r6
- 6ac: 5f 90 pop r5
- 6ae: 4f 90 pop r4
- 6b0: 3f 90 pop r3
- 6b2: 2f 90 pop r2
+ 67c: 6d 2d mov r22, r13
+ 67e: 7e 2d mov r23, r14
+ 680: 8f 2d mov r24, r15
+ 682: 9c 2d mov r25, r12
+ 684: df 91 pop r29
+ 686: cf 91 pop r28
+ 688: 1f 91 pop r17
+ 68a: 0f 91 pop r16
+ 68c: ff 90 pop r15
+ 68e: ef 90 pop r14
+ 690: df 90 pop r13
+ 692: cf 90 pop r12
+ 694: bf 90 pop r11
+ 696: af 90 pop r10
+ 698: 9f 90 pop r9
+ 69a: 8f 90 pop r8
+ 69c: 7f 90 pop r7
+ 69e: 6f 90 pop r6
+ 6a0: 5f 90 pop r5
+ 6a2: 4f 90 pop r4
+ 6a4: 3f 90 pop r3
+ 6a6: 2f 90 pop r2
+ 6a8: 08 95 ret
+
+000006aa <currentc_setSetpoint>:
+
+
+ void currentc_setSetpoint(currentc_t *cc, double val){
+ cc->setpoint=val;
+ 6aa: fc 01 movw r30, r24
+ 6ac: 40 a7 std Z+40, r20 ; 0x28
+ 6ae: 51 a7 std Z+41, r21 ; 0x29
+ 6b0: 62 a7 std Z+42, r22 ; 0x2a
+ 6b2: 73 a7 std Z+43, r23 ; 0x2b
6b4: 08 95 ret
-000006b6 <currentc_setSetpoint>:
+000006b6 <currentc_setAcceptableRange>:
+ }
+
+ void currentc_setAcceptableRange(currentc_t *cc, double range){
+ cc->acceptableRange=range;
6b6: fc 01 movw r30, r24
- 6b8: 40 a7 std Z+40, r20 ; 0x28
- 6ba: 51 a7 std Z+41, r21 ; 0x29
- 6bc: 62 a7 std Z+42, r22 ; 0x2a
- 6be: 73 a7 std Z+43, r23 ; 0x2b
+ 6b8: 44 a7 std Z+44, r20 ; 0x2c
+ 6ba: 55 a7 std Z+45, r21 ; 0x2d
+ 6bc: 66 a7 std Z+46, r22 ; 0x2e
+ 6be: 77 a7 std Z+47, r23 ; 0x2f
6c0: 08 95 ret
-000006c2 <currentc_setAcceptableRange>:
- 6c2: fc 01 movw r30, r24
- 6c4: 44 a7 std Z+44, r20 ; 0x2c
- 6c6: 55 a7 std Z+45, r21 ; 0x2d
- 6c8: 66 a7 std Z+46, r22 ; 0x2e
- 6ca: 77 a7 std Z+47, r23 ; 0x2f
- 6cc: 08 95 ret
+000006c2 <currentc_onTarget>:
+ }
+
+ uint8_t currentc_onTarget(currentc_t *cc){ // if on target for more than 50 millis
+ 6c2: cf 93 push r28
+ 6c4: df 93 push r29
+ 6c6: ec 01 movw r28, r24
+
+ return cc->onTargetTicks * cc->dt >0.1;
+ 6c8: 68 a9 ldd r22, Y+48 ; 0x30
+ 6ca: 79 a9 ldd r23, Y+49 ; 0x31
+ 6cc: 07 2e mov r0, r23
+ 6ce: 00 0c add r0, r0
+ 6d0: 88 0b sbc r24, r24
+ 6d2: 99 0b sbc r25, r25
+ 6d4: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 6d8: 28 85 ldd r18, Y+8 ; 0x08
+ 6da: 39 85 ldd r19, Y+9 ; 0x09
+ 6dc: 4a 85 ldd r20, Y+10 ; 0x0a
+ 6de: 5b 85 ldd r21, Y+11 ; 0x0b
+ 6e0: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 6e4: c1 e0 ldi r28, 0x01 ; 1
+ 6e6: 2d ec ldi r18, 0xCD ; 205
+ 6e8: 3c ec ldi r19, 0xCC ; 204
+ 6ea: 4c ec ldi r20, 0xCC ; 204
+ 6ec: 5d e3 ldi r21, 0x3D ; 61
+ 6ee: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 6f2: 18 16 cp r1, r24
+ 6f4: 0c f0 brlt .+2 ; 0x6f8 <currentc_onTarget+0x36>
+ 6f6: c0 e0 ldi r28, 0x00 ; 0
+ }
+ 6f8: 8c 2f mov r24, r28
+ 6fa: df 91 pop r29
+ 6fc: cf 91 pop r28
+ 6fe: 08 95 ret
-000006ce <currentc_init>:
+00000700 <currentc_init>:
void currentc_init(currentc_t *cc, double P, double I, double dt, int MIN_IN, int MAX_IN, int MIN_OUT, int MAX_OUT){
- 6ce: 2f 92 push r2
- 6d0: 3f 92 push r3
- 6d2: 4f 92 push r4
- 6d4: 5f 92 push r5
- 6d6: 6f 92 push r6
- 6d8: 7f 92 push r7
- 6da: 8f 92 push r8
- 6dc: 9f 92 push r9
- 6de: af 92 push r10
- 6e0: bf 92 push r11
- 6e2: cf 92 push r12
- 6e4: df 92 push r13
- 6e6: ef 92 push r14
- 6e8: ff 92 push r15
- 6ea: 0f 93 push r16
- 6ec: 1f 93 push r17
- 6ee: cf 93 push r28
- 6f0: df 93 push r29
- 6f2: cd b7 in r28, 0x3d ; 61
- 6f4: de b7 in r29, 0x3e ; 62
- 6f6: 3c 01 movw r6, r24
- 6f8: 18 01 movw r2, r16
- 6fa: 29 01 movw r4, r18
- 6fc: 8e 89 ldd r24, Y+22 ; 0x16
- 6fe: 9f 89 ldd r25, Y+23 ; 0x17
- 700: 08 8d ldd r16, Y+24 ; 0x18
- 702: 19 8d ldd r17, Y+25 ; 0x19
+ 700: 2f 92 push r2
+ 702: 3f 92 push r3
+ 704: 4f 92 push r4
+ 706: 5f 92 push r5
+ 708: 6f 92 push r6
+ 70a: 7f 92 push r7
+ 70c: 8f 92 push r8
+ 70e: 9f 92 push r9
+ 710: af 92 push r10
+ 712: bf 92 push r11
+ 714: cf 92 push r12
+ 716: df 92 push r13
+ 718: ef 92 push r14
+ 71a: ff 92 push r15
+ 71c: 0f 93 push r16
+ 71e: 1f 93 push r17
+ 720: cf 93 push r28
+ 722: df 93 push r29
+ 724: cd b7 in r28, 0x3d ; 61
+ 726: de b7 in r29, 0x3e ; 62
+ 728: 3c 01 movw r6, r24
+ 72a: 18 01 movw r2, r16
+ 72c: 29 01 movw r4, r18
+ 72e: 8e 89 ldd r24, Y+22 ; 0x16
+ 730: 9f 89 ldd r25, Y+23 ; 0x17
+ 732: 08 8d ldd r16, Y+24 ; 0x18
+ 734: 19 8d ldd r17, Y+25 ; 0x19
cc->P = P;
- 704: f3 01 movw r30, r6
- 706: 40 83 st Z, r20
- 708: 51 83 std Z+1, r21 ; 0x01
- 70a: 62 83 std Z+2, r22 ; 0x02
- 70c: 73 83 std Z+3, r23 ; 0x03
+ 736: f3 01 movw r30, r6
+ 738: 40 83 st Z, r20
+ 73a: 51 83 std Z+1, r21 ; 0x01
+ 73c: 62 83 std Z+2, r22 ; 0x02
+ 73e: 73 83 std Z+3, r23 ; 0x03
cc->I=I;
- 70e: 24 82 std Z+4, r2 ; 0x04
- 710: 35 82 std Z+5, r3 ; 0x05
- 712: 46 82 std Z+6, r4 ; 0x06
- 714: 57 82 std Z+7, r5 ; 0x07
+ 740: 24 82 std Z+4, r2 ; 0x04
+ 742: 35 82 std Z+5, r3 ; 0x05
+ 744: 46 82 std Z+6, r4 ; 0x06
+ 746: 57 82 std Z+7, r5 ; 0x07
cc->dt=dt;
- 716: c0 86 std Z+8, r12 ; 0x08
- 718: d1 86 std Z+9, r13 ; 0x09
- 71a: e2 86 std Z+10, r14 ; 0x0a
- 71c: f3 86 std Z+11, r15 ; 0x0b
+ 748: c0 86 std Z+8, r12 ; 0x08
+ 74a: d1 86 std Z+9, r13 ; 0x09
+ 74c: e2 86 std Z+10, r14 ; 0x0a
+ 74e: f3 86 std Z+11, r15 ; 0x0b
cc->MIN_IN=MIN_IN;
- 71e: a6 86 std Z+14, r10 ; 0x0e
- 720: b7 86 std Z+15, r11 ; 0x0f
+ 750: a6 86 std Z+14, r10 ; 0x0e
+ 752: b7 86 std Z+15, r11 ; 0x0f
cc->MAX_IN=MAX_IN;
- 722: 84 86 std Z+12, r8 ; 0x0c
- 724: 95 86 std Z+13, r9 ; 0x0d
+ 754: 84 86 std Z+12, r8 ; 0x0c
+ 756: 95 86 std Z+13, r9 ; 0x0d
cc->MIN_OUT=MIN_OUT;
- 726: 82 8b std Z+18, r24 ; 0x12
- 728: 93 8b std Z+19, r25 ; 0x13
+ 758: 82 8b std Z+18, r24 ; 0x12
+ 75a: 93 8b std Z+19, r25 ; 0x13
cc->MAX_OUT=MAX_OUT;
- 72a: 00 8b std Z+16, r16 ; 0x10
- 72c: 11 8b std Z+17, r17 ; 0x11
+ 75c: 00 8b std Z+16, r16 ; 0x10
+ 75e: 11 8b std Z+17, r17 ; 0x11
cc->minTotalError = MIN_OUT/ I;
- 72e: bc 01 movw r22, r24
- 730: 99 0f add r25, r25
- 732: 88 0b sbc r24, r24
- 734: 99 0b sbc r25, r25
- 736: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 73a: a2 01 movw r20, r4
- 73c: 91 01 movw r18, r2
- 73e: 0e 94 78 09 call 0x12f0 ; 0x12f0 <__divsf3>
- 742: f3 01 movw r30, r6
- 744: 64 a3 std Z+36, r22 ; 0x24
- 746: 75 a3 std Z+37, r23 ; 0x25
- 748: 86 a3 std Z+38, r24 ; 0x26
- 74a: 97 a3 std Z+39, r25 ; 0x27
+ 760: bc 01 movw r22, r24
+ 762: 99 0f add r25, r25
+ 764: 88 0b sbc r24, r24
+ 766: 99 0b sbc r25, r25
+ 768: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 76c: a2 01 movw r20, r4
+ 76e: 91 01 movw r18, r2
+ 770: 0e 94 90 09 call 0x1320 ; 0x1320 <__divsf3>
+ 774: f3 01 movw r30, r6
+ 776: 64 a3 std Z+36, r22 ; 0x24
+ 778: 75 a3 std Z+37, r23 ; 0x25
+ 77a: 86 a3 std Z+38, r24 ; 0x26
+ 77c: 97 a3 std Z+39, r25 ; 0x27
cc->maxtotalError = MAX_OUT/ I;
- 74c: b8 01 movw r22, r16
- 74e: 11 0f add r17, r17
- 750: 88 0b sbc r24, r24
- 752: 99 0b sbc r25, r25
- 754: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 758: a2 01 movw r20, r4
- 75a: 91 01 movw r18, r2
- 75c: 0e 94 78 09 call 0x12f0 ; 0x12f0 <__divsf3>
- 760: f3 01 movw r30, r6
- 762: 60 a3 std Z+32, r22 ; 0x20
- 764: 71 a3 std Z+33, r23 ; 0x21
- 766: 82 a3 std Z+34, r24 ; 0x22
- 768: 93 a3 std Z+35, r25 ; 0x23
+ 77e: b8 01 movw r22, r16
+ 780: 11 0f add r17, r17
+ 782: 88 0b sbc r24, r24
+ 784: 99 0b sbc r25, r25
+ 786: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 78a: a2 01 movw r20, r4
+ 78c: 91 01 movw r18, r2
+ 78e: 0e 94 90 09 call 0x1320 ; 0x1320 <__divsf3>
+ 792: f3 01 movw r30, r6
+ 794: 60 a3 std Z+32, r22 ; 0x20
+ 796: 71 a3 std Z+33, r23 ; 0x21
+ 798: 82 a3 std Z+34, r24 ; 0x22
+ 79a: 93 a3 std Z+35, r25 ; 0x23
cc->prevError=0;
- 76a: 14 8a std Z+20, r1 ; 0x14
- 76c: 15 8a std Z+21, r1 ; 0x15
- 76e: 16 8a std Z+22, r1 ; 0x16
- 770: 17 8a std Z+23, r1 ; 0x17
+ 79c: 14 8a std Z+20, r1 ; 0x14
+ 79e: 15 8a std Z+21, r1 ; 0x15
+ 7a0: 16 8a std Z+22, r1 ; 0x16
+ 7a2: 17 8a std Z+23, r1 ; 0x17
cc->currentError=0;
- 772: 10 8e std Z+24, r1 ; 0x18
- 774: 11 8e std Z+25, r1 ; 0x19
- 776: 12 8e std Z+26, r1 ; 0x1a
- 778: 13 8e std Z+27, r1 ; 0x1b
+ 7a4: 10 8e std Z+24, r1 ; 0x18
+ 7a6: 11 8e std Z+25, r1 ; 0x19
+ 7a8: 12 8e std Z+26, r1 ; 0x1a
+ 7aa: 13 8e std Z+27, r1 ; 0x1b
cc->totalError=0;
- 77a: 14 8e std Z+28, r1 ; 0x1c
- 77c: 15 8e std Z+29, r1 ; 0x1d
- 77e: 16 8e std Z+30, r1 ; 0x1e
- 780: 17 8e std Z+31, r1 ; 0x1f
+ 7ac: 14 8e std Z+28, r1 ; 0x1c
+ 7ae: 15 8e std Z+29, r1 ; 0x1d
+ 7b0: 16 8e std Z+30, r1 ; 0x1e
+ 7b2: 17 8e std Z+31, r1 ; 0x1f
cc->setpoint=0;
- 782: 10 a6 std Z+40, r1 ; 0x28
- 784: 11 a6 std Z+41, r1 ; 0x29
- 786: 12 a6 std Z+42, r1 ; 0x2a
- 788: 13 a6 std Z+43, r1 ; 0x2b
- cc->acceptableRange=30;
- 78a: 80 e0 ldi r24, 0x00 ; 0
- 78c: 90 e0 ldi r25, 0x00 ; 0
- 78e: a0 ef ldi r26, 0xF0 ; 240
- 790: b1 e4 ldi r27, 0x41 ; 65
- 792: 84 a7 std Z+44, r24 ; 0x2c
- 794: 95 a7 std Z+45, r25 ; 0x2d
- 796: a6 a7 std Z+46, r26 ; 0x2e
- 798: b7 a7 std Z+47, r27 ; 0x2f
+ 7b4: 10 a6 std Z+40, r1 ; 0x28
+ 7b6: 11 a6 std Z+41, r1 ; 0x29
+ 7b8: 12 a6 std Z+42, r1 ; 0x2a
+ 7ba: 13 a6 std Z+43, r1 ; 0x2b
+ cc->acceptableRange=20;
+ 7bc: 80 e0 ldi r24, 0x00 ; 0
+ 7be: 90 e0 ldi r25, 0x00 ; 0
+ 7c0: a0 ea ldi r26, 0xA0 ; 160
+ 7c2: b1 e4 ldi r27, 0x41 ; 65
+ 7c4: 84 a7 std Z+44, r24 ; 0x2c
+ 7c6: 95 a7 std Z+45, r25 ; 0x2d
+ 7c8: a6 a7 std Z+46, r26 ; 0x2e
+ 7ca: b7 a7 std Z+47, r27 ; 0x2f
cc->onTargetTicks=0;
- 79a: 10 aa std Z+48, r1 ; 0x30
- 79c: 11 aa std Z+49, r1 ; 0x31
- 79e: df 91 pop r29
- 7a0: cf 91 pop r28
- 7a2: 1f 91 pop r17
- 7a4: 0f 91 pop r16
- 7a6: ff 90 pop r15
- 7a8: ef 90 pop r14
- 7aa: df 90 pop r13
- 7ac: cf 90 pop r12
- 7ae: bf 90 pop r11
- 7b0: af 90 pop r10
- 7b2: 9f 90 pop r9
- 7b4: 8f 90 pop r8
- 7b6: 7f 90 pop r7
- 7b8: 6f 90 pop r6
- 7ba: 5f 90 pop r5
- 7bc: 4f 90 pop r4
- 7be: 3f 90 pop r3
- 7c0: 2f 90 pop r2
- 7c2: 08 95 ret
-
-000007c4 <l_filter>:
+ 7cc: 10 aa std Z+48, r1 ; 0x30
+ 7ce: 11 aa std Z+49, r1 ; 0x31
+ 7d0: df 91 pop r29
+ 7d2: cf 91 pop r28
+ 7d4: 1f 91 pop r17
+ 7d6: 0f 91 pop r16
+ 7d8: ff 90 pop r15
+ 7da: ef 90 pop r14
+ 7dc: df 90 pop r13
+ 7de: cf 90 pop r12
+ 7e0: bf 90 pop r11
+ 7e2: af 90 pop r10
+ 7e4: 9f 90 pop r9
+ 7e6: 8f 90 pop r8
+ 7e8: 7f 90 pop r7
+ 7ea: 6f 90 pop r6
+ 7ec: 5f 90 pop r5
+ 7ee: 4f 90 pop r4
+ 7f0: 3f 90 pop r3
+ 7f2: 2f 90 pop r2
+ 7f4: 08 95 ret
+
+000007f6 <l_filter>:
*/
#include "l_filter.h"
#include <avr/io.h>
- uint16_t l_filter(l_filter_t *filter, int input){
- 7c4: cf 92 push r12
- 7c6: df 92 push r13
- 7c8: ef 92 push r14
- 7ca: ff 92 push r15
- 7cc: fc 01 movw r30, r24
- filter->filter_reg = (filter->filter_reg) - ((filter->filter_reg) >> filter->K) +(input>>filter->K); // y(n) = (1-2^-k)(y(n-1)) + (2^-k)(x(n))
- 7ce: 81 81 ldd r24, Z+1 ; 0x01
- 7d0: 92 81 ldd r25, Z+2 ; 0x02
- 7d2: a3 81 ldd r26, Z+3 ; 0x03
- 7d4: b4 81 ldd r27, Z+4 ; 0x04
- 7d6: 20 81 ld r18, Z
- 7d8: 6c 01 movw r12, r24
- 7da: 7d 01 movw r14, r26
- 7dc: 02 2e mov r0, r18
- 7de: 04 c0 rjmp .+8 ; 0x7e8 <l_filter+0x24>
- 7e0: f5 94 asr r15
- 7e2: e7 94 ror r14
- 7e4: d7 94 ror r13
- 7e6: c7 94 ror r12
- 7e8: 0a 94 dec r0
- 7ea: d2 f7 brpl .-12 ; 0x7e0 <l_filter+0x1c>
- 7ec: 8c 19 sub r24, r12
- 7ee: 9d 09 sbc r25, r13
- 7f0: ae 09 sbc r26, r14
- 7f2: bf 09 sbc r27, r15
- 7f4: ab 01 movw r20, r22
- 7f6: 02 c0 rjmp .+4 ; 0x7fc <l_filter+0x38>
- 7f8: 55 95 asr r21
- 7fa: 47 95 ror r20
- 7fc: 2a 95 dec r18
- 7fe: e2 f7 brpl .-8 ; 0x7f8 <l_filter+0x34>
- 800: 05 2e mov r0, r21
- 802: 00 0c add r0, r0
- 804: 66 0b sbc r22, r22
- 806: 77 0b sbc r23, r23
- 808: 84 0f add r24, r20
- 80a: 95 1f adc r25, r21
- 80c: a6 1f adc r26, r22
- 80e: b7 1f adc r27, r23
- 810: 81 83 std Z+1, r24 ; 0x01
- 812: 92 83 std Z+2, r25 ; 0x02
- 814: a3 83 std Z+3, r26 ; 0x03
- 816: b4 83 std Z+4, r27 ; 0x04
+ int l_filter(l_filter_t *filter, int input){
+ 7f6: cf 92 push r12
+ 7f8: df 92 push r13
+ 7fa: ef 92 push r14
+ 7fc: ff 92 push r15
+ 7fe: 0f 93 push r16
+ 800: 1f 93 push r17
+ 802: cf 93 push r28
+ 804: df 93 push r29
+ 806: 8c 01 movw r16, r24
+ 808: eb 01 movw r28, r22
+ //filter->filter_reg = (filter->filter_reg) - ((filter->filter_reg) >> filter->K) +(input>>filter->K); // y(n) = (1-2^-k)(y(n-1)) + (2^-k)(x(n))
+ filter->filter_reg = filter->filter_reg*0.985 + 0.015*input;
+ 80a: fc 01 movw r30, r24
+ 80c: 61 81 ldd r22, Z+1 ; 0x01
+ 80e: 72 81 ldd r23, Z+2 ; 0x02
+ 810: 07 2e mov r0, r23
+ 812: 00 0c add r0, r0
+ 814: 88 0b sbc r24, r24
+ 816: 99 0b sbc r25, r25
+ 818: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 81c: 26 ef ldi r18, 0xF6 ; 246
+ 81e: 38 e2 ldi r19, 0x28 ; 40
+ 820: 4c e7 ldi r20, 0x7C ; 124
+ 822: 5f e3 ldi r21, 0x3F ; 63
+ 824: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 828: 6b 01 movw r12, r22
+ 82a: 7c 01 movw r14, r24
+ 82c: be 01 movw r22, r28
+ 82e: dd 0f add r29, r29
+ 830: 88 0b sbc r24, r24
+ 832: 99 0b sbc r25, r25
+ 834: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 838: 2f e8 ldi r18, 0x8F ; 143
+ 83a: 32 ec ldi r19, 0xC2 ; 194
+ 83c: 45 e7 ldi r20, 0x75 ; 117
+ 83e: 5c e3 ldi r21, 0x3C ; 60
+ 840: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 844: 9b 01 movw r18, r22
+ 846: ac 01 movw r20, r24
+ 848: c7 01 movw r24, r14
+ 84a: b6 01 movw r22, r12
+ 84c: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ 850: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ 854: f8 01 movw r30, r16
+ 856: 61 83 std Z+1, r22 ; 0x01
+ 858: 72 83 std Z+2, r23 ; 0x02
return filter->filter_reg;
};
- 818: ff 90 pop r15
- 81a: ef 90 pop r14
- 81c: df 90 pop r13
- 81e: cf 90 pop r12
- 820: 08 95 ret
-
-00000822 <l_filter_init>:
+ 85a: cb 01 movw r24, r22
+ 85c: df 91 pop r29
+ 85e: cf 91 pop r28
+ 860: 1f 91 pop r17
+ 862: 0f 91 pop r16
+ 864: ff 90 pop r15
+ 866: ef 90 pop r14
+ 868: df 90 pop r13
+ 86a: cf 90 pop r12
+ 86c: 08 95 ret
+
+0000086e <l_filter_init>:
void l_filter_init(l_filter_t *filter, uint8_t K){
filter->filter_reg=0;
- 822: fc 01 movw r30, r24
- 824: 11 82 std Z+1, r1 ; 0x01
- 826: 12 82 std Z+2, r1 ; 0x02
- 828: 13 82 std Z+3, r1 ; 0x03
- 82a: 14 82 std Z+4, r1 ; 0x04
+ 86e: fc 01 movw r30, r24
+ 870: 11 82 std Z+1, r1 ; 0x01
+ 872: 12 82 std Z+2, r1 ; 0x02
filter->K = K;
- 82c: 60 83 st Z, r22
- 82e: 08 95 ret
+ 874: 60 83 st Z, r22
+ 876: 08 95 ret
-00000830 <pwm_set>:
+00000878 <pwm_set>:
void pwm_set_dutycycle(pwm_t *pwm, double val){ //setPWM to value between 0 and 100
uint16_t pwm_val = (CONSTRAIN(val,0.0,100.0)/100.0) * per;
pwm_set(pwm,pwm_val);
}
void pwm_set(pwm_t *pwm, uint16_t val){
- 830: fc 01 movw r30, r24
+ 878: fc 01 movw r30, r24
uint8_t vall = (uint8_t) val;
uint8_t valh = (uint8_t) (val >> 8);
uint8_t channel = pwm->pwm_channel;
- 832: 83 81 ldd r24, Z+3 ; 0x03
-
+ 87a: 83 81 ldd r24, Z+3 ; 0x03
if(channel & (TC0_CCAEN_bm)){
- 834: 84 ff sbrs r24, 4
- 836: 09 c0 rjmp .+18 ; 0x84a <pwm_set+0x1a>
+ 87c: 84 ff sbrs r24, 4
+ 87e: 09 c0 rjmp .+18 ; 0x892 <pwm_set+0x1a>
pwm->timer->CCABUFH = valh;
- 838: a0 81 ld r26, Z
- 83a: b1 81 ldd r27, Z+1 ; 0x01
- 83c: d9 96 adiw r26, 0x39 ; 57
- 83e: 7c 93 st X, r23
+ 880: a0 81 ld r26, Z
+ 882: b1 81 ldd r27, Z+1 ; 0x01
+ 884: d9 96 adiw r26, 0x39 ; 57
+ 886: 7c 93 st X, r23
pwm->timer->CCABUFL = vall;
- 840: 01 90 ld r0, Z+
- 842: f0 81 ld r31, Z
- 844: e0 2d mov r30, r0
- 846: 60 af std Z+56, r22 ; 0x38
- 848: 08 95 ret
+ 888: 01 90 ld r0, Z+
+ 88a: f0 81 ld r31, Z
+ 88c: e0 2d mov r30, r0
+ 88e: 60 af std Z+56, r22 ; 0x38
+ 890: 08 95 ret
}else if(channel & (TC0_CCBEN_bm)){
- 84a: 85 ff sbrs r24, 5
- 84c: 09 c0 rjmp .+18 ; 0x860 <pwm_set+0x30>
+ 892: 85 ff sbrs r24, 5
+ 894: 09 c0 rjmp .+18 ; 0x8a8 <pwm_set+0x30>
pwm->timer->CCBBUFH = valh;
- 84e: a0 81 ld r26, Z
- 850: b1 81 ldd r27, Z+1 ; 0x01
- 852: db 96 adiw r26, 0x3b ; 59
- 854: 7c 93 st X, r23
+ 896: a0 81 ld r26, Z
+ 898: b1 81 ldd r27, Z+1 ; 0x01
+ 89a: db 96 adiw r26, 0x3b ; 59
+ 89c: 7c 93 st X, r23
pwm->timer->CCBBUFL = vall;
- 856: 01 90 ld r0, Z+
- 858: f0 81 ld r31, Z
- 85a: e0 2d mov r30, r0
- 85c: 62 af std Z+58, r22 ; 0x3a
- 85e: 08 95 ret
+ 89e: 01 90 ld r0, Z+
+ 8a0: f0 81 ld r31, Z
+ 8a2: e0 2d mov r30, r0
+ 8a4: 62 af std Z+58, r22 ; 0x3a
+ 8a6: 08 95 ret
}else if(channel & (TC0_CCCEN_bm)){
- 860: 86 ff sbrs r24, 6
- 862: 09 c0 rjmp .+18 ; 0x876 <pwm_set+0x46>
+ 8a8: 86 ff sbrs r24, 6
+ 8aa: 09 c0 rjmp .+18 ; 0x8be <pwm_set+0x46>
pwm->timer->CCCBUFH = valh;
- 864: a0 81 ld r26, Z
- 866: b1 81 ldd r27, Z+1 ; 0x01
- 868: dd 96 adiw r26, 0x3d ; 61
- 86a: 7c 93 st X, r23
+ 8ac: a0 81 ld r26, Z
+ 8ae: b1 81 ldd r27, Z+1 ; 0x01
+ 8b0: dd 96 adiw r26, 0x3d ; 61
+ 8b2: 7c 93 st X, r23
pwm->timer->CCCBUFL = vall;
- 86c: 01 90 ld r0, Z+
- 86e: f0 81 ld r31, Z
- 870: e0 2d mov r30, r0
- 872: 64 af std Z+60, r22 ; 0x3c
- 874: 08 95 ret
+ 8b4: 01 90 ld r0, Z+
+ 8b6: f0 81 ld r31, Z
+ 8b8: e0 2d mov r30, r0
+ 8ba: 64 af std Z+60, r22 ; 0x3c
+ 8bc: 08 95 ret
}else if(channel & (TC0_CCDEN_bm)){
- 876: 88 23 and r24, r24
- 878: 44 f4 brge .+16 ; 0x88a <pwm_set+0x5a>
+ 8be: 88 23 and r24, r24
+ 8c0: 44 f4 brge .+16 ; 0x8d2 <pwm_set+0x5a>
pwm->timer->CCDBUFH = valh;
- 87a: a0 81 ld r26, Z
- 87c: b1 81 ldd r27, Z+1 ; 0x01
- 87e: df 96 adiw r26, 0x3f ; 63
- 880: 7c 93 st X, r23
+ 8c2: a0 81 ld r26, Z
+ 8c4: b1 81 ldd r27, Z+1 ; 0x01
+ 8c6: df 96 adiw r26, 0x3f ; 63
+ 8c8: 7c 93 st X, r23
pwm->timer->CCDBUFL = vall;
- 882: 01 90 ld r0, Z+
- 884: f0 81 ld r31, Z
- 886: e0 2d mov r30, r0
- 888: 66 af std Z+62, r22 ; 0x3e
- 88a: 08 95 ret
+ 8ca: 01 90 ld r0, Z+
+ 8cc: f0 81 ld r31, Z
+ 8ce: e0 2d mov r30, r0
+ 8d0: 66 af std Z+62, r22 ; 0x3e
+ 8d2: 08 95 ret
-0000088c <pwm_set_dutycycle>:
+000008d4 <pwm_set_dutycycle>:
#include <math.h>
uint16_t per;
void pwm_set_dutycycle(pwm_t *pwm, double val){ //setPWM to value between 0 and 100
- 88c: cf 92 push r12
- 88e: df 92 push r13
- 890: ef 92 push r14
- 892: ff 92 push r15
- 894: cf 93 push r28
- 896: df 93 push r29
- 898: ec 01 movw r28, r24
- 89a: 6a 01 movw r12, r20
- 89c: 7b 01 movw r14, r22
+ 8d4: cf 92 push r12
+ 8d6: df 92 push r13
+ 8d8: ef 92 push r14
+ 8da: ff 92 push r15
+ 8dc: cf 93 push r28
+ 8de: df 93 push r29
+ 8e0: ec 01 movw r28, r24
+ 8e2: 6a 01 movw r12, r20
+ 8e4: 7b 01 movw r14, r22
uint16_t pwm_val = (CONSTRAIN(val,0.0,100.0)/100.0) * per;
- 89e: 20 e0 ldi r18, 0x00 ; 0
- 8a0: 30 e0 ldi r19, 0x00 ; 0
- 8a2: a9 01 movw r20, r18
- 8a4: c7 01 movw r24, r14
- 8a6: b6 01 movw r22, r12
- 8a8: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 8ac: 88 23 and r24, r24
- 8ae: ac f0 brlt .+42 ; 0x8da <pwm_set_dutycycle+0x4e>
- 8b0: 20 e0 ldi r18, 0x00 ; 0
- 8b2: 30 e0 ldi r19, 0x00 ; 0
- 8b4: 48 ec ldi r20, 0xC8 ; 200
- 8b6: 52 e4 ldi r21, 0x42 ; 66
- 8b8: c7 01 movw r24, r14
- 8ba: b6 01 movw r22, r12
- 8bc: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- 8c0: 18 16 cp r1, r24
- 8c2: 7c f0 brlt .+30 ; 0x8e2 <pwm_set_dutycycle+0x56>
- 8c4: 20 e0 ldi r18, 0x00 ; 0
- 8c6: 30 e0 ldi r19, 0x00 ; 0
- 8c8: 48 ec ldi r20, 0xC8 ; 200
- 8ca: 52 e4 ldi r21, 0x42 ; 66
- 8cc: c7 01 movw r24, r14
- 8ce: b6 01 movw r22, r12
- 8d0: 0e 94 78 09 call 0x12f0 ; 0x12f0 <__divsf3>
- 8d4: 6b 01 movw r12, r22
- 8d6: 7c 01 movw r14, r24
- 8d8: 0c c0 rjmp .+24 ; 0x8f2 <pwm_set_dutycycle+0x66>
- 8da: c1 2c mov r12, r1
- 8dc: d1 2c mov r13, r1
- 8de: 76 01 movw r14, r12
- 8e0: 08 c0 rjmp .+16 ; 0x8f2 <pwm_set_dutycycle+0x66>
- 8e2: 0f 2e mov r0, r31
- 8e4: c1 2c mov r12, r1
- 8e6: d1 2c mov r13, r1
- 8e8: f0 e8 ldi r31, 0x80 ; 128
- 8ea: ef 2e mov r14, r31
- 8ec: ff e3 ldi r31, 0x3F ; 63
- 8ee: ff 2e mov r15, r31
- 8f0: f0 2d mov r31, r0
+ 8e6: 20 e0 ldi r18, 0x00 ; 0
+ 8e8: 30 e0 ldi r19, 0x00 ; 0
+ 8ea: a9 01 movw r20, r18
+ 8ec: c7 01 movw r24, r14
+ 8ee: b6 01 movw r22, r12
+ 8f0: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 8f4: 88 23 and r24, r24
+ 8f6: ac f0 brlt .+42 ; 0x922 <pwm_set_dutycycle+0x4e>
+ 8f8: 20 e0 ldi r18, 0x00 ; 0
+ 8fa: 30 e0 ldi r19, 0x00 ; 0
+ 8fc: 48 ec ldi r20, 0xC8 ; 200
+ 8fe: 52 e4 ldi r21, 0x42 ; 66
+ 900: c7 01 movw r24, r14
+ 902: b6 01 movw r22, r12
+ 904: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 908: 18 16 cp r1, r24
+ 90a: 7c f0 brlt .+30 ; 0x92a <pwm_set_dutycycle+0x56>
+ 90c: 20 e0 ldi r18, 0x00 ; 0
+ 90e: 30 e0 ldi r19, 0x00 ; 0
+ 910: 48 ec ldi r20, 0xC8 ; 200
+ 912: 52 e4 ldi r21, 0x42 ; 66
+ 914: c7 01 movw r24, r14
+ 916: b6 01 movw r22, r12
+ 918: 0e 94 90 09 call 0x1320 ; 0x1320 <__divsf3>
+ 91c: 6b 01 movw r12, r22
+ 91e: 7c 01 movw r14, r24
+ 920: 0c c0 rjmp .+24 ; 0x93a <pwm_set_dutycycle+0x66>
+ 922: c1 2c mov r12, r1
+ 924: d1 2c mov r13, r1
+ 926: 76 01 movw r14, r12
+ 928: 08 c0 rjmp .+16 ; 0x93a <pwm_set_dutycycle+0x66>
+ 92a: 0f 2e mov r0, r31
+ 92c: c1 2c mov r12, r1
+ 92e: d1 2c mov r13, r1
+ 930: f0 e8 ldi r31, 0x80 ; 128
+ 932: ef 2e mov r14, r31
+ 934: ff e3 ldi r31, 0x3F ; 63
+ 936: ff 2e mov r15, r31
+ 938: f0 2d mov r31, r0
pwm_set(pwm,pwm_val);
- 8f2: 60 91 08 20 lds r22, 0x2008 ; 0x802008 <per>
- 8f6: 70 91 09 20 lds r23, 0x2009 ; 0x802009 <per+0x1>
- 8fa: 80 e0 ldi r24, 0x00 ; 0
- 8fc: 90 e0 ldi r25, 0x00 ; 0
- 8fe: 0e 94 20 0a call 0x1440 ; 0x1440 <__floatunsisf>
- 902: a7 01 movw r20, r14
- 904: 96 01 movw r18, r12
- 906: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 90a: 0e 94 f1 09 call 0x13e2 ; 0x13e2 <__fixunssfsi>
- 90e: ce 01 movw r24, r28
- 910: 0e 94 18 04 call 0x830 ; 0x830 <pwm_set>
+ 93a: 60 91 08 20 lds r22, 0x2008 ; 0x802008 <per>
+ 93e: 70 91 09 20 lds r23, 0x2009 ; 0x802009 <per+0x1>
+ 942: 80 e0 ldi r24, 0x00 ; 0
+ 944: 90 e0 ldi r25, 0x00 ; 0
+ 946: 0e 94 38 0a call 0x1470 ; 0x1470 <__floatunsisf>
+ 94a: a7 01 movw r20, r14
+ 94c: 96 01 movw r18, r12
+ 94e: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 952: 0e 94 09 0a call 0x1412 ; 0x1412 <__fixunssfsi>
+ 956: ce 01 movw r24, r28
+ 958: 0e 94 3c 04 call 0x878 ; 0x878 <pwm_set>
}
- 914: df 91 pop r29
- 916: cf 91 pop r28
- 918: ff 90 pop r15
- 91a: ef 90 pop r14
- 91c: df 90 pop r13
- 91e: cf 90 pop r12
- 920: 08 95 ret
-
-00000922 <pwm_init>:
+ 95c: df 91 pop r29
+ 95e: cf 91 pop r28
+ 960: ff 90 pop r15
+ 962: ef 90 pop r14
+ 964: df 90 pop r13
+ 966: cf 90 pop r12
+ 968: 08 95 ret
+
+0000096a <pwm_init>:
}
//frequencies are limited due to prescalar and 16 bit numbers
int pwm_init(pwm_t *pwm, TC0_t *timer, TC_CLKSEL_t prescalar, uint8_t pwm_channel,
uint16_t base_frequency, uint16_t desiredFrequency){//frequency in khz
- 922: ef 92 push r14
- 924: ff 92 push r15
- 926: 0f 93 push r16
- 928: 1f 93 push r17
- 92a: cf 93 push r28
- 92c: df 93 push r29
- 92e: fc 01 movw r30, r24
- 930: eb 01 movw r28, r22
- 932: c8 01 movw r24, r16
- 934: b7 01 movw r22, r14
+ 96a: ef 92 push r14
+ 96c: ff 92 push r15
+ 96e: 0f 93 push r16
+ 970: 1f 93 push r17
+ 972: cf 93 push r28
+ 974: df 93 push r29
+ 976: fc 01 movw r30, r24
+ 978: eb 01 movw r28, r22
+ 97a: c8 01 movw r24, r16
+ 97c: b7 01 movw r22, r14
pwm->timer = timer;
- 936: c0 83 st Z, r28
- 938: d1 83 std Z+1, r29 ; 0x01
+ 97e: c0 83 st Z, r28
+ 980: d1 83 std Z+1, r29 ; 0x01
pwm->prescalar=prescalar;
- 93a: 42 83 std Z+2, r20 ; 0x02
+ 982: 42 83 std Z+2, r20 ; 0x02
pwm->pwm_channel=pwm_channel;
- 93c: 23 83 std Z+3, r18 ; 0x03
+ 984: 23 83 std Z+3, r18 ; 0x03
pwm->base_frequency = base_frequency;
- 93e: 04 83 std Z+4, r16 ; 0x04
- 940: 15 83 std Z+5, r17 ; 0x05
+ 986: 04 83 std Z+4, r16 ; 0x04
+ 988: 15 83 std Z+5, r17 ; 0x05
pwm->desired_frequency = desiredFrequency;
- 942: e6 82 std Z+6, r14 ; 0x06
- 944: f7 82 std Z+7, r15 ; 0x07
+ 98a: e6 82 std Z+6, r14 ; 0x06
+ 98c: f7 82 std Z+7, r15 ; 0x07
timer->CTRLA = prescalar;
- 946: 48 83 st Y, r20
+ 98e: 48 83 st Y, r20
timer->CTRLB = TC_WGMODE_SINGLESLOPE_gc | pwm_channel;//wave generation mode single slope, enabling CCA open port OC
- 948: 23 60 ori r18, 0x03 ; 3
- 94a: 29 83 std Y+1, r18 ; 0x01
+ 990: 23 60 ori r18, 0x03 ; 3
+ 992: 29 83 std Y+1, r18 ; 0x01
int prescalardiv= pow(2,prescalar-1);//gets division from prescalar - taking advantage of way TC_CLKSEL_t is written
prescalardiv=1;
per = (base_frequency/prescalardiv)/(desiredFrequency); // x = (BF/p)/DF Base Frequency, prescalar, desired frequency
- 94c: 0e 94 44 0b call 0x1688 ; 0x1688 <__udivmodhi4>
- 950: 60 93 08 20 sts 0x2008, r22 ; 0x802008 <per>
- 954: 70 93 09 20 sts 0x2009, r23 ; 0x802009 <per+0x1>
+ 994: 0e 94 5c 0b call 0x16b8 ; 0x16b8 <__udivmodhi4>
+ 998: 60 93 08 20 sts 0x2008, r22 ; 0x802008 <per>
+ 99c: 70 93 09 20 sts 0x2009, r23 ; 0x802009 <per+0x1>
}
uint8_t perl = (uint8_t) per;
uint8_t perh = (uint8_t) (per >> 8);
timer->PERBUFL = perl;//for the waveform period - controls TOP value
- 958: 6e ab std Y+54, r22 ; 0x36
+ 9a0: 6e ab std Y+54, r22 ; 0x36
timer->PERBUFH = perh;
- 95a: 7f ab std Y+55, r23 ; 0x37
+ 9a2: 7f ab std Y+55, r23 ; 0x37
pwm_set(pwm,0);
- 95c: 60 e0 ldi r22, 0x00 ; 0
- 95e: 70 e0 ldi r23, 0x00 ; 0
- 960: cf 01 movw r24, r30
- 962: 0e 94 18 04 call 0x830 ; 0x830 <pwm_set>
+ 9a4: 60 e0 ldi r22, 0x00 ; 0
+ 9a6: 70 e0 ldi r23, 0x00 ; 0
+ 9a8: cf 01 movw r24, r30
+ 9aa: 0e 94 3c 04 call 0x878 ; 0x878 <pwm_set>
return 0;
- 966: 80 e0 ldi r24, 0x00 ; 0
- 968: 90 e0 ldi r25, 0x00 ; 0
- 96a: df 91 pop r29
- 96c: cf 91 pop r28
- 96e: 1f 91 pop r17
- 970: 0f 91 pop r16
- 972: ff 90 pop r15
- 974: ef 90 pop r14
- 976: 08 95 ret
-
-00000978 <motor_init>:
+ 9ae: 80 e0 ldi r24, 0x00 ; 0
+ 9b0: 90 e0 ldi r25, 0x00 ; 0
+ 9b2: df 91 pop r29
+ 9b4: cf 91 pop r28
+ 9b6: 1f 91 pop r17
+ 9b8: 0f 91 pop r16
+ 9ba: ff 90 pop r15
+ 9bc: ef 90 pop r14
+ 9be: 08 95 ret
+
+000009c0 <motor_init>:
#include "motor.h"
void motor_init(motor_t *motor, pin_t *INA_pin, pin_t *INB_pin, pwm_t *PWM) {
- 978: cf 93 push r28
- 97a: df 93 push r29
- 97c: ec 01 movw r28, r24
- 97e: cb 01 movw r24, r22
+ 9c0: cf 93 push r28
+ 9c2: df 93 push r29
+ 9c4: ec 01 movw r28, r24
+ 9c6: cb 01 movw r24, r22
motor->INA_pin = INA_pin;
- 980: 68 83 st Y, r22
- 982: 79 83 std Y+1, r23 ; 0x01
+ 9c8: 68 83 st Y, r22
+ 9ca: 79 83 std Y+1, r23 ; 0x01
motor->INB_pin = INB_pin;
- 984: 4a 83 std Y+2, r20 ; 0x02
- 986: 5b 83 std Y+3, r21 ; 0x03
+ 9cc: 4a 83 std Y+2, r20 ; 0x02
+ 9ce: 5b 83 std Y+3, r21 ; 0x03
motor->PWM = PWM;
- 988: 2c 83 std Y+4, r18 ; 0x04
- 98a: 3d 83 std Y+5, r19 ; 0x05
+ 9d0: 2c 83 std Y+4, r18 ; 0x04
+ 9d2: 3d 83 std Y+5, r19 ; 0x05
+
pin_set(motor->INA_pin);
- 98c: 0e 94 ce 06 call 0xd9c ; 0xd9c <pin_set>
+ 9d4: 0e 94 e6 06 call 0xdcc ; 0xdcc <pin_set>
pin_clear(motor->INB_pin);
- 990: 8a 81 ldd r24, Y+2 ; 0x02
- 992: 9b 81 ldd r25, Y+3 ; 0x03
- 994: 0e 94 d6 06 call 0xdac ; 0xdac <pin_clear>
+ 9d8: 8a 81 ldd r24, Y+2 ; 0x02
+ 9da: 9b 81 ldd r25, Y+3 ; 0x03
+ 9dc: 0e 94 ee 06 call 0xddc ; 0xddc <pin_clear>
}
- 998: df 91 pop r29
- 99a: cf 91 pop r28
- 99c: 08 95 ret
+ 9e0: df 91 pop r29
+ 9e2: cf 91 pop r28
+ 9e4: 08 95 ret
-0000099e <motor_set>:
+000009e6 <motor_set>:
void motor_set(motor_t *motor, double val){
- 99e: cf 92 push r12
- 9a0: df 92 push r13
- 9a2: ef 92 push r14
- 9a4: ff 92 push r15
- 9a6: cf 93 push r28
- 9a8: df 93 push r29
- 9aa: ec 01 movw r28, r24
- 9ac: 6a 01 movw r12, r20
- 9ae: 7b 01 movw r14, r22
+ 9e6: cf 92 push r12
+ 9e8: df 92 push r13
+ 9ea: ef 92 push r14
+ 9ec: ff 92 push r15
+ 9ee: cf 93 push r28
+ 9f0: df 93 push r29
+ 9f2: ec 01 movw r28, r24
+ 9f4: 6a 01 movw r12, r20
+ 9f6: 7b 01 movw r14, r22
if(val<0){
- 9b0: 20 e0 ldi r18, 0x00 ; 0
- 9b2: 30 e0 ldi r19, 0x00 ; 0
- 9b4: a9 01 movw r20, r18
- 9b6: c7 01 movw r24, r14
- 9b8: b6 01 movw r22, r12
- 9ba: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 9be: 88 23 and r24, r24
- 9c0: 6c f4 brge .+26 ; 0x9dc <motor_set+0x3e>
+ 9f8: 20 e0 ldi r18, 0x00 ; 0
+ 9fa: 30 e0 ldi r19, 0x00 ; 0
+ 9fc: a9 01 movw r20, r18
+ 9fe: c7 01 movw r24, r14
+ a00: b6 01 movw r22, r12
+ a02: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ a06: 88 23 and r24, r24
+ a08: 6c f4 brge .+26 ; 0xa24 <motor_set+0x3e>
val*=-1;
- 9c2: f7 fa bst r15, 7
- 9c4: f0 94 com r15
- 9c6: f7 f8 bld r15, 7
- 9c8: f0 94 com r15
+ a0a: f7 fa bst r15, 7
+ a0c: f0 94 com r15
+ a0e: f7 f8 bld r15, 7
+ a10: f0 94 com r15
pin_set(motor->INA_pin);
- 9ca: 88 81 ld r24, Y
- 9cc: 99 81 ldd r25, Y+1 ; 0x01
- 9ce: 0e 94 ce 06 call 0xd9c ; 0xd9c <pin_set>
+ a12: 88 81 ld r24, Y
+ a14: 99 81 ldd r25, Y+1 ; 0x01
+ a16: 0e 94 e6 06 call 0xdcc ; 0xdcc <pin_set>
pin_clear(motor->INB_pin);
- 9d2: 8a 81 ldd r24, Y+2 ; 0x02
- 9d4: 9b 81 ldd r25, Y+3 ; 0x03
- 9d6: 0e 94 d6 06 call 0xdac ; 0xdac <pin_clear>
- 9da: 08 c0 rjmp .+16 ; 0x9ec <motor_set+0x4e>
+ a1a: 8a 81 ldd r24, Y+2 ; 0x02
+ a1c: 9b 81 ldd r25, Y+3 ; 0x03
+ a1e: 0e 94 ee 06 call 0xddc ; 0xddc <pin_clear>
+ a22: 08 c0 rjmp .+16 ; 0xa34 <motor_set+0x4e>
}else{
pin_set(motor->INB_pin);
- 9dc: 8a 81 ldd r24, Y+2 ; 0x02
- 9de: 9b 81 ldd r25, Y+3 ; 0x03
- 9e0: 0e 94 ce 06 call 0xd9c ; 0xd9c <pin_set>
+ a24: 8a 81 ldd r24, Y+2 ; 0x02
+ a26: 9b 81 ldd r25, Y+3 ; 0x03
+ a28: 0e 94 e6 06 call 0xdcc ; 0xdcc <pin_set>
pin_clear(motor->INA_pin);
- 9e4: 88 81 ld r24, Y
- 9e6: 99 81 ldd r25, Y+1 ; 0x01
- 9e8: 0e 94 d6 06 call 0xdac ; 0xdac <pin_clear>
+ a2c: 88 81 ld r24, Y
+ a2e: 99 81 ldd r25, Y+1 ; 0x01
+ a30: 0e 94 ee 06 call 0xddc ; 0xddc <pin_clear>
}
pwm_set_dutycycle(motor->PWM, val);
- 9ec: b7 01 movw r22, r14
- 9ee: a6 01 movw r20, r12
- 9f0: 8c 81 ldd r24, Y+4 ; 0x04
- 9f2: 9d 81 ldd r25, Y+5 ; 0x05
- 9f4: 0e 94 46 04 call 0x88c ; 0x88c <pwm_set_dutycycle>
+ a34: b7 01 movw r22, r14
+ a36: a6 01 movw r20, r12
+ a38: 8c 81 ldd r24, Y+4 ; 0x04
+ a3a: 9d 81 ldd r25, Y+5 ; 0x05
+ a3c: 0e 94 6a 04 call 0x8d4 ; 0x8d4 <pwm_set_dutycycle>
}
- 9f8: df 91 pop r29
- 9fa: cf 91 pop r28
- 9fc: ff 90 pop r15
- 9fe: ef 90 pop r14
- a00: df 90 pop r13
- a02: cf 90 pop r12
- a04: 08 95 ret
-
-00000a06 <timing_interrupts_init>:
+ a40: df 91 pop r29
+ a42: cf 91 pop r28
+ a44: ff 90 pop r15
+ a46: ef 90 pop r14
+ a48: df 90 pop r13
+ a4a: cf 90 pop r12
+ a4c: 08 95 ret
+
+00000a4e <timing_interrupts_init>:
}
}
void timing_interrupts_init(){
TCC1.CTRLA = TC_CLKSEL_DIV1_gc;
- a06: e0 e4 ldi r30, 0x40 ; 64
- a08: f8 e0 ldi r31, 0x08 ; 8
- a0a: 81 e0 ldi r24, 0x01 ; 1
- a0c: 80 83 st Z, r24
+ a4e: e0 e4 ldi r30, 0x40 ; 64
+ a50: f8 e0 ldi r31, 0x08 ; 8
+ a52: 81 e0 ldi r24, 0x01 ; 1
+ a54: 80 83 st Z, r24
uint16_t pera = 24000; // 2khz (48MHZ/24000)
uint8_t peral = (uint8_t) pera;
uint8_t perah = (uint8_t) (pera >> 8);
TCC1.PERBUFL = peral;
- a0e: 80 ec ldi r24, 0xC0 ; 192
- a10: 86 ab std Z+54, r24 ; 0x36
+ a56: 80 ec ldi r24, 0xC0 ; 192
+ a58: 86 ab std Z+54, r24 ; 0x36
TCC1.PERBUFH = perah;
- a12: 8d e5 ldi r24, 0x5D ; 93
- a14: 87 ab std Z+55, r24 ; 0x37
+ a5a: 8d e5 ldi r24, 0x5D ; 93
+ a5c: 87 ab std Z+55, r24 ; 0x37
TCC1.INTCTRLA = TC_OVFINTLVL_MED_gc;
- a16: 82 e0 ldi r24, 0x02 ; 2
- a18: 86 83 std Z+6, r24 ; 0x06
- a1a: 08 95 ret
+ a5e: 82 e0 ldi r24, 0x02 ; 2
+ a60: 86 83 std Z+6, r24 ; 0x06
+ a62: 08 95 ret
-00000a1c <main>:
+00000a64 <main>:
int main(void)
{
//initialize Clock to 48 Mhz
clock_init();
- a1c: 0e 94 91 01 call 0x322 ; 0x322 <clock_init>
+ a64: 0e 94 8b 01 call 0x316 ; 0x316 <clock_init>
//initialize interrupts
sei();
- a20: 78 94 sei
+ a68: 78 94 sei
PMIC.CTRL |= PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
- a22: e0 ea ldi r30, 0xA0 ; 160
- a24: f0 e0 ldi r31, 0x00 ; 0
- a26: 82 81 ldd r24, Z+2 ; 0x02
- a28: 87 60 ori r24, 0x07 ; 7
- a2a: 82 83 std Z+2, r24 ; 0x02
+ a6a: e0 ea ldi r30, 0xA0 ; 160
+ a6c: f0 e0 ldi r31, 0x00 ; 0
+ a6e: 82 81 ldd r24, Z+2 ; 0x02
+ a70: 87 60 ori r24, 0x07 ; 7
+ a72: 82 83 std Z+2, r24 ; 0x02
- PORTE.DIRSET |= PIN3_bm;
- a2c: e0 e8 ldi r30, 0x80 ; 128
- a2e: f6 e0 ldi r31, 0x06 ; 6
- a30: 81 81 ldd r24, Z+1 ; 0x01
- a32: 88 60 ori r24, 0x08 ; 8
- a34: 81 83 std Z+1, r24 ; 0x01
+ PORTE.DIRSET |= PIN3_bm | PIN2_bm;
+ a74: e0 e8 ldi r30, 0x80 ; 128
+ a76: f6 e0 ldi r31, 0x06 ; 6
+ a78: 81 81 ldd r24, Z+1 ; 0x01
+ a7a: 8c 60 ori r24, 0x0C ; 12
+ a7c: 81 83 std Z+1, r24 ; 0x01
//start DAC, PWM, and Encoder
dac_begin(ATK_DAC_DUAL_CHANNEL);
- a36: 82 e0 ldi r24, 0x02 ; 2
- a38: 0e 94 c1 01 call 0x382 ; 0x382 <dac_begin>
+ a7e: 82 e0 ldi r24, 0x02 ; 2
+ a80: 0e 94 bb 01 call 0x376 ; 0x376 <dac_begin>
ATKEncoder_begin(1);//1 tick/unit
- a3c: 60 e0 ldi r22, 0x00 ; 0
- a3e: 70 e0 ldi r23, 0x00 ; 0
- a40: 80 e8 ldi r24, 0x80 ; 128
- a42: 9f e3 ldi r25, 0x3F ; 63
- a44: 0e 94 f7 01 call 0x3ee ; 0x3ee <ATKEncoder_begin>
+ a84: 60 e0 ldi r22, 0x00 ; 0
+ a86: 70 e0 ldi r23, 0x00 ; 0
+ a88: 80 e8 ldi r24, 0x80 ; 128
+ a8a: 9f e3 ldi r25, 0x3F ; 63
+ a8c: 0e 94 f1 01 call 0x3e2 ; 0x3e2 <ATKEncoder_begin>
//initialize motor H bridge pins
PORTC.DIRSET |= PIN0_bm || PIN4_bm || PIN3_bm;
- a48: e0 e4 ldi r30, 0x40 ; 64
- a4a: f6 e0 ldi r31, 0x06 ; 6
- a4c: 81 81 ldd r24, Z+1 ; 0x01
- a4e: 81 60 ori r24, 0x01 ; 1
- a50: 81 83 std Z+1, r24 ; 0x01
+ a90: e0 e4 ldi r30, 0x40 ; 64
+ a92: f6 e0 ldi r31, 0x06 ; 6
+ a94: 81 81 ldd r24, Z+1 ; 0x01
+ a96: 81 60 ori r24, 0x01 ; 1
+ a98: 81 83 std Z+1, r24 ; 0x01
+ PORTC_DIRSET |= PIN5_bm;
+ a9a: e1 e4 ldi r30, 0x41 ; 65
+ a9c: f6 e0 ldi r31, 0x06 ; 6
+ a9e: 80 81 ld r24, Z
+ aa0: 80 62 ori r24, 0x20 ; 32
+ aa2: 80 83 st Z, r24
+ PORTC_OUTSET |= PIN5_bm;
+ aa4: e5 e4 ldi r30, 0x45 ; 69
+ aa6: f6 e0 ldi r31, 0x06 ; 6
+ aa8: 80 81 ld r24, Z
+ aaa: 80 62 ori r24, 0x20 ; 32
+ aac: 80 83 st Z, r24
pin_init(&M_INA, &PORTC, PIN4_bm,1,1);
- a52: 01 e0 ldi r16, 0x01 ; 1
- a54: 21 e0 ldi r18, 0x01 ; 1
- a56: 40 e1 ldi r20, 0x10 ; 16
- a58: 60 e4 ldi r22, 0x40 ; 64
- a5a: 76 e0 ldi r23, 0x06 ; 6
- a5c: 86 e8 ldi r24, 0x86 ; 134
- a5e: 90 e2 ldi r25, 0x20 ; 32
- a60: 0e 94 bf 06 call 0xd7e ; 0xd7e <pin_init>
+ aae: 01 e0 ldi r16, 0x01 ; 1
+ ab0: 21 e0 ldi r18, 0x01 ; 1
+ ab2: 40 e1 ldi r20, 0x10 ; 16
+ ab4: 60 e4 ldi r22, 0x40 ; 64
+ ab6: 76 e0 ldi r23, 0x06 ; 6
+ ab8: 84 e8 ldi r24, 0x84 ; 132
+ aba: 90 e2 ldi r25, 0x20 ; 32
+ abc: 0e 94 d7 06 call 0xdae ; 0xdae <pin_init>
pin_init(&M_INB, &PORTC, PIN3_bm,0,1);
- a64: 20 e0 ldi r18, 0x00 ; 0
- a66: 48 e0 ldi r20, 0x08 ; 8
- a68: 60 e4 ldi r22, 0x40 ; 64
- a6a: 76 e0 ldi r23, 0x06 ; 6
- a6c: 82 e4 ldi r24, 0x42 ; 66
- a6e: 90 e2 ldi r25, 0x20 ; 32
- a70: 0e 94 bf 06 call 0xd7e ; 0xd7e <pin_init>
- pwm_init(&M_PWM, &TCC0,TC_CLKSEL_DIV1_gc,TC0_CCAEN_bm,48000,20);
- a74: 0f 2e mov r0, r31
- a76: f4 e1 ldi r31, 0x14 ; 20
- a78: ef 2e mov r14, r31
- a7a: f1 2c mov r15, r1
- a7c: f0 2d mov r31, r0
- a7e: 00 e8 ldi r16, 0x80 ; 128
- a80: 1b eb ldi r17, 0xBB ; 187
- a82: 20 e1 ldi r18, 0x10 ; 16
- a84: 41 e0 ldi r20, 0x01 ; 1
- a86: 60 e0 ldi r22, 0x00 ; 0
- a88: 78 e0 ldi r23, 0x08 ; 8
- a8a: 8c e4 ldi r24, 0x4C ; 76
- a8c: 90 e2 ldi r25, 0x20 ; 32
- a8e: 0e 94 91 04 call 0x922 ; 0x922 <pwm_init>
+ ac0: 20 e0 ldi r18, 0x00 ; 0
+ ac2: 48 e0 ldi r20, 0x08 ; 8
+ ac4: 60 e4 ldi r22, 0x40 ; 64
+ ac6: 76 e0 ldi r23, 0x06 ; 6
+ ac8: 80 e4 ldi r24, 0x40 ; 64
+ aca: 90 e2 ldi r25, 0x20 ; 32
+ acc: 0e 94 d7 06 call 0xdae ; 0xdae <pin_init>
+ pwm_init(&M_PWM, &TCC0,TC_CLKSEL_DIV1_gc,TC0_CCAEN_bm,48000,10);
+ ad0: 0f 2e mov r0, r31
+ ad2: fa e0 ldi r31, 0x0A ; 10
+ ad4: ef 2e mov r14, r31
+ ad6: f1 2c mov r15, r1
+ ad8: f0 2d mov r31, r0
+ ada: 00 e8 ldi r16, 0x80 ; 128
+ adc: 1b eb ldi r17, 0xBB ; 187
+ ade: 20 e1 ldi r18, 0x10 ; 16
+ ae0: 41 e0 ldi r20, 0x01 ; 1
+ ae2: 60 e0 ldi r22, 0x00 ; 0
+ ae4: 78 e0 ldi r23, 0x08 ; 8
+ ae6: 8a e4 ldi r24, 0x4A ; 74
+ ae8: 90 e2 ldi r25, 0x20 ; 32
+ aea: 0e 94 b5 04 call 0x96a ; 0x96a <pwm_init>
motor_init(&M_1,&M_INA,&M_INB,&M_PWM);
- a92: 2c e4 ldi r18, 0x4C ; 76
- a94: 30 e2 ldi r19, 0x20 ; 32
- a96: 42 e4 ldi r20, 0x42 ; 66
- a98: 50 e2 ldi r21, 0x20 ; 32
- a9a: 66 e8 ldi r22, 0x86 ; 134
- a9c: 70 e2 ldi r23, 0x20 ; 32
- a9e: 86 e4 ldi r24, 0x46 ; 70
- aa0: 90 e2 ldi r25, 0x20 ; 32
- aa2: 0e 94 bc 04 call 0x978 ; 0x978 <motor_init>
+ aee: 2a e4 ldi r18, 0x4A ; 74
+ af0: 30 e2 ldi r19, 0x20 ; 32
+ af2: 40 e4 ldi r20, 0x40 ; 64
+ af4: 50 e2 ldi r21, 0x20 ; 32
+ af6: 64 e8 ldi r22, 0x84 ; 132
+ af8: 70 e2 ldi r23, 0x20 ; 32
+ afa: 84 e4 ldi r24, 0x44 ; 68
+ afc: 90 e2 ldi r25, 0x20 ; 32
+ afe: 0e 94 e0 04 call 0x9c0 ; 0x9c0 <motor_init>
//initialize current controller
+ PORTB_DIRCLR |= PIN0_bm;
+ b02: e2 e2 ldi r30, 0x22 ; 34
+ b04: f6 e0 ldi r31, 0x06 ; 6
+ b06: 80 81 ld r24, Z
+ b08: 81 60 ori r24, 0x01 ; 1
+ b0a: 80 83 st Z, r24
r_adc_init(&ADC_CS, &ADCB, &ADCB.CH0, ADC_CH_MUXPOS_PIN0_gc);
- aa6: 20 e0 ldi r18, 0x00 ; 0
- aa8: 40 e6 ldi r20, 0x60 ; 96
- aaa: 52 e0 ldi r21, 0x02 ; 2
- aac: 60 e4 ldi r22, 0x40 ; 64
- aae: 72 e0 ldi r23, 0x02 ; 2
- ab0: 8a e0 ldi r24, 0x0A ; 10
- ab2: 90 e2 ldi r25, 0x20 ; 32
- ab4: 0e 94 14 01 call 0x228 ; 0x228 <r_adc_init>
+ b0c: 20 e0 ldi r18, 0x00 ; 0
+ b0e: 40 e6 ldi r20, 0x60 ; 96
+ b10: 52 e0 ldi r21, 0x02 ; 2
+ b12: 60 e4 ldi r22, 0x40 ; 64
+ b14: 72 e0 ldi r23, 0x02 ; 2
+ b16: 8a e0 ldi r24, 0x0A ; 10
+ b18: 90 e2 ldi r25, 0x20 ; 32
+ b1a: 0e 94 14 01 call 0x228 ; 0x228 <r_adc_init>
currentc_init(&CC, 2.0,8.0,0.0005,0,5000,0,100);
- ab8: 1f 92 push r1
- aba: 84 e6 ldi r24, 0x64 ; 100
- abc: 8f 93 push r24
- abe: 1f 92 push r1
- ac0: 1f 92 push r1
- ac2: 0f 2e mov r0, r31
- ac4: f8 e8 ldi r31, 0x88 ; 136
- ac6: 8f 2e mov r8, r31
- ac8: f3 e1 ldi r31, 0x13 ; 19
- aca: 9f 2e mov r9, r31
- acc: f0 2d mov r31, r0
- ace: a1 2c mov r10, r1
- ad0: b1 2c mov r11, r1
- ad2: 0f 2e mov r0, r31
- ad4: ff e6 ldi r31, 0x6F ; 111
- ad6: cf 2e mov r12, r31
- ad8: f2 e1 ldi r31, 0x12 ; 18
- ada: df 2e mov r13, r31
- adc: f3 e0 ldi r31, 0x03 ; 3
- ade: ef 2e mov r14, r31
- ae0: fa e3 ldi r31, 0x3A ; 58
- ae2: ff 2e mov r15, r31
- ae4: f0 2d mov r31, r0
- ae6: 00 e0 ldi r16, 0x00 ; 0
- ae8: 10 e0 ldi r17, 0x00 ; 0
- aea: 20 e0 ldi r18, 0x00 ; 0
- aec: 31 e4 ldi r19, 0x41 ; 65
- aee: 40 e0 ldi r20, 0x00 ; 0
- af0: 50 e0 ldi r21, 0x00 ; 0
- af2: 60 e0 ldi r22, 0x00 ; 0
- af4: 70 e4 ldi r23, 0x40 ; 64
- af6: 84 e5 ldi r24, 0x54 ; 84
- af8: 90 e2 ldi r25, 0x20 ; 32
- afa: 0e 94 67 03 call 0x6ce ; 0x6ce <currentc_init>
+ b1e: 1f 92 push r1
+ b20: 84 e6 ldi r24, 0x64 ; 100
+ b22: 8f 93 push r24
+ b24: 1f 92 push r1
+ b26: 1f 92 push r1
+ b28: 0f 2e mov r0, r31
+ b2a: f8 e8 ldi r31, 0x88 ; 136
+ b2c: 8f 2e mov r8, r31
+ b2e: f3 e1 ldi r31, 0x13 ; 19
+ b30: 9f 2e mov r9, r31
+ b32: f0 2d mov r31, r0
+ b34: a1 2c mov r10, r1
+ b36: b1 2c mov r11, r1
+ b38: 0f 2e mov r0, r31
+ b3a: ff e6 ldi r31, 0x6F ; 111
+ b3c: cf 2e mov r12, r31
+ b3e: f2 e1 ldi r31, 0x12 ; 18
+ b40: df 2e mov r13, r31
+ b42: f3 e0 ldi r31, 0x03 ; 3
+ b44: ef 2e mov r14, r31
+ b46: fa e3 ldi r31, 0x3A ; 58
+ b48: ff 2e mov r15, r31
+ b4a: f0 2d mov r31, r0
+ b4c: 00 e0 ldi r16, 0x00 ; 0
+ b4e: 10 e0 ldi r17, 0x00 ; 0
+ b50: 20 e0 ldi r18, 0x00 ; 0
+ b52: 31 e4 ldi r19, 0x41 ; 65
+ b54: 40 e0 ldi r20, 0x00 ; 0
+ b56: 50 e0 ldi r21, 0x00 ; 0
+ b58: 60 e0 ldi r22, 0x00 ; 0
+ b5a: 70 e4 ldi r23, 0x40 ; 64
+ b5c: 82 e5 ldi r24, 0x52 ; 82
+ b5e: 90 e2 ldi r25, 0x20 ; 32
+ b60: 0e 94 80 03 call 0x700 ; 0x700 <currentc_init>
currentc_setSetpoint(&CC, OTHERSETPOINT);
- afe: 40 e0 ldi r20, 0x00 ; 0
- b00: 50 e0 ldi r21, 0x00 ; 0
- b02: 6a ef ldi r22, 0xFA ; 250
- b04: 73 e4 ldi r23, 0x43 ; 67
- b06: 84 e5 ldi r24, 0x54 ; 84
- b08: 90 e2 ldi r25, 0x20 ; 32
- b0a: 0e 94 5b 03 call 0x6b6 ; 0x6b6 <currentc_setSetpoint>
+ b64: 40 e0 ldi r20, 0x00 ; 0
+ b66: 50 e0 ldi r21, 0x00 ; 0
+ b68: 6a ef ldi r22, 0xFA ; 250
+ b6a: 73 e4 ldi r23, 0x43 ; 67
+ b6c: 82 e5 ldi r24, 0x52 ; 82
+ b6e: 90 e2 ldi r25, 0x20 ; 32
+ b70: 0e 94 55 03 call 0x6aa ; 0x6aa <currentc_setSetpoint>
currentc_setAcceptableRange(&CC, 50);
- b0e: 40 e0 ldi r20, 0x00 ; 0
- b10: 50 e0 ldi r21, 0x00 ; 0
- b12: 68 e4 ldi r22, 0x48 ; 72
- b14: 72 e4 ldi r23, 0x42 ; 66
- b16: 84 e5 ldi r24, 0x54 ; 84
- b18: 90 e2 ldi r25, 0x20 ; 32
- b1a: 0e 94 61 03 call 0x6c2 ; 0x6c2 <currentc_setAcceptableRange>
+ b74: 40 e0 ldi r20, 0x00 ; 0
+ b76: 50 e0 ldi r21, 0x00 ; 0
+ b78: 68 e4 ldi r22, 0x48 ; 72
+ b7a: 72 e4 ldi r23, 0x42 ; 66
+ b7c: 82 e5 ldi r24, 0x52 ; 82
+ b7e: 90 e2 ldi r25, 0x20 ; 32
+ b80: 0e 94 5b 03 call 0x6b6 ; 0x6b6 <currentc_setAcceptableRange>
l_filter_init(&CS_filter, 6);
- b1e: 66 e0 ldi r22, 0x06 ; 6
- b20: 8a e8 ldi r24, 0x8A ; 138
- b22: 90 e2 ldi r25, 0x20 ; 32
- b24: 0e 94 11 04 call 0x822 ; 0x822 <l_filter_init>
+ b84: 66 e0 ldi r22, 0x06 ; 6
+ b86: 88 e8 ldi r24, 0x88 ; 136
+ b88: 90 e2 ldi r25, 0x20 ; 32
+ b8a: 0e 94 37 04 call 0x86e ; 0x86e <l_filter_init>
//initialize PID
- RPID_init(&M_1_pid,20,5.0, 0.0 ,0.00016,0, 0,0,-300,300, 6);
- b28: 86 e0 ldi r24, 0x06 ; 6
- b2a: 8f 93 push r24
- b2c: 81 e0 ldi r24, 0x01 ; 1
- b2e: 8f 93 push r24
- b30: 8c e2 ldi r24, 0x2C ; 44
- b32: 8f 93 push r24
- b34: 8e ef ldi r24, 0xFE ; 254
- b36: 8f 93 push r24
- b38: 84 ed ldi r24, 0xD4 ; 212
- b3a: 8f 93 push r24
- b3c: 1f 92 push r1
- b3e: 1f 92 push r1
- b40: 1f 92 push r1
- b42: 1f 92 push r1
- b44: 1f 92 push r1
- b46: 0f 2e mov r0, r31
- b48: fc ea ldi r31, 0xAC ; 172
- b4a: 8f 2e mov r8, r31
- b4c: f5 ec ldi r31, 0xC5 ; 197
- b4e: 9f 2e mov r9, r31
- b50: f7 e2 ldi r31, 0x27 ; 39
- b52: af 2e mov r10, r31
- b54: f9 e3 ldi r31, 0x39 ; 57
- b56: bf 2e mov r11, r31
- b58: f0 2d mov r31, r0
- b5a: c1 2c mov r12, r1
- b5c: d1 2c mov r13, r1
- b5e: 76 01 movw r14, r12
- b60: 00 e0 ldi r16, 0x00 ; 0
- b62: 10 e0 ldi r17, 0x00 ; 0
- b64: 20 ea ldi r18, 0xA0 ; 160
- b66: 30 e4 ldi r19, 0x40 ; 64
- b68: 40 e0 ldi r20, 0x00 ; 0
- b6a: 50 e0 ldi r21, 0x00 ; 0
- b6c: 60 ea ldi r22, 0xA0 ; 160
- b6e: 71 e4 ldi r23, 0x41 ; 65
- b70: 8e e0 ldi r24, 0x0E ; 14
- b72: 90 e2 ldi r25, 0x20 ; 32
- b74: 0e 94 a6 08 call 0x114c ; 0x114c <RPID_init>
+ RPID_init(&M_1_pid,5.0,0.0, 0.0 ,0.00016,0, 0,0,-300,300, 6);
+ b8e: 86 e0 ldi r24, 0x06 ; 6
+ b90: 8f 93 push r24
+ b92: 81 e0 ldi r24, 0x01 ; 1
+ b94: 8f 93 push r24
+ b96: 8c e2 ldi r24, 0x2C ; 44
+ b98: 8f 93 push r24
+ b9a: 8e ef ldi r24, 0xFE ; 254
+ b9c: 8f 93 push r24
+ b9e: 84 ed ldi r24, 0xD4 ; 212
+ ba0: 8f 93 push r24
+ ba2: 1f 92 push r1
+ ba4: 1f 92 push r1
+ ba6: 1f 92 push r1
+ ba8: 1f 92 push r1
+ baa: 1f 92 push r1
+ bac: 0f 2e mov r0, r31
+ bae: fc ea ldi r31, 0xAC ; 172
+ bb0: 8f 2e mov r8, r31
+ bb2: f5 ec ldi r31, 0xC5 ; 197
+ bb4: 9f 2e mov r9, r31
+ bb6: f7 e2 ldi r31, 0x27 ; 39
+ bb8: af 2e mov r10, r31
+ bba: f9 e3 ldi r31, 0x39 ; 57
+ bbc: bf 2e mov r11, r31
+ bbe: f0 2d mov r31, r0
+ bc0: c1 2c mov r12, r1
+ bc2: d1 2c mov r13, r1
+ bc4: 76 01 movw r14, r12
+ bc6: 97 01 movw r18, r14
+ bc8: 86 01 movw r16, r12
+ bca: 40 e0 ldi r20, 0x00 ; 0
+ bcc: 50 e0 ldi r21, 0x00 ; 0
+ bce: 60 ea ldi r22, 0xA0 ; 160
+ bd0: 70 e4 ldi r23, 0x40 ; 64
+ bd2: 8e e0 ldi r24, 0x0E ; 14
+ bd4: 90 e2 ldi r25, 0x20 ; 32
+ bd6: 0e 94 be 08 call 0x117c ; 0x117c <RPID_init>
//initialize debugging DACs
PORTB.DIRSET |= PIN2_bm | PIN3_bm;
- b78: e0 e2 ldi r30, 0x20 ; 32
- b7a: f6 e0 ldi r31, 0x06 ; 6
- b7c: 81 81 ldd r24, Z+1 ; 0x01
- b7e: 8c 60 ori r24, 0x0C ; 12
- b80: 81 83 std Z+1, r24 ; 0x01
+ bda: e0 e2 ldi r30, 0x20 ; 32
+ bdc: f6 e0 ldi r31, 0x06 ; 6
+ bde: 81 81 ldd r24, Z+1 ; 0x01
+ be0: 8c 60 ori r24, 0x0C ; 12
+ be2: 81 83 std Z+1, r24 ; 0x01
//set_dac(ATK_DAC_CHANNEL_0, 1000);
//set_dac(ATK_DAC_CHANNEL_1, 1000);
pwm_set(&M_PWM,1000);
- b82: 68 ee ldi r22, 0xE8 ; 232
- b84: 73 e0 ldi r23, 0x03 ; 3
- b86: 8c e4 ldi r24, 0x4C ; 76
- b88: 90 e2 ldi r25, 0x20 ; 32
- b8a: 0e 94 18 04 call 0x830 ; 0x830 <pwm_set>
+ be4: 68 ee ldi r22, 0xE8 ; 232
+ be6: 73 e0 ldi r23, 0x03 ; 3
+ be8: 8a e4 ldi r24, 0x4A ; 74
+ bea: 90 e2 ldi r25, 0x20 ; 32
+ bec: 0e 94 3c 04 call 0x878 ; 0x878 <pwm_set>
PORTE_DIRSET = PIN2_bm | PIN3_bm;
- b8e: 8c e0 ldi r24, 0x0C ; 12
- b90: 80 93 81 06 sts 0x0681, r24 ; 0x800681 <__TEXT_REGION_LENGTH__+0x700681>
+ bf0: 8c e0 ldi r24, 0x0C ; 12
+ bf2: 80 93 81 06 sts 0x0681, r24 ; 0x800681 <__TEXT_REGION_LENGTH__+0x700681>
RPID_setSetpoint(&M_1_pid, 46);
- b94: 40 e0 ldi r20, 0x00 ; 0
- b96: 50 e0 ldi r21, 0x00 ; 0
- b98: 68 e3 ldi r22, 0x38 ; 56
- b9a: 72 e4 ldi r23, 0x42 ; 66
- b9c: 8e e0 ldi r24, 0x0E ; 14
- b9e: 90 e2 ldi r25, 0x20 ; 32
- ba0: 0e 94 81 08 call 0x1102 ; 0x1102 <RPID_setSetpoint>
+ bf6: 40 e0 ldi r20, 0x00 ; 0
+ bf8: 50 e0 ldi r21, 0x00 ; 0
+ bfa: 68 e3 ldi r22, 0x38 ; 56
+ bfc: 72 e4 ldi r23, 0x42 ; 66
+ bfe: 8e e0 ldi r24, 0x0E ; 14
+ c00: 90 e2 ldi r25, 0x20 ; 32
+ c02: 0e 94 99 08 call 0x1132 ; 0x1132 <RPID_setSetpoint>
//initialize tickets
timing_interrupts_init();
- ba4: 0e 94 03 05 call 0xa06 ; 0xa06 <timing_interrupts_init>
- ba8: 8d b7 in r24, 0x3d ; 61
- baa: 9e b7 in r25, 0x3e ; 62
- bac: 0e 96 adiw r24, 0x0e ; 14
- bae: 8d bf out 0x3d, r24 ; 61
- bb0: 9e bf out 0x3e, r25 ; 62
- bb2: ff cf rjmp .-2 ; 0xbb2 <main+0x196>
-
-00000bb4 <__vector_20>:
+ c06: 0e 94 27 05 call 0xa4e ; 0xa4e <timing_interrupts_init>
+ c0a: 8d b7 in r24, 0x3d ; 61
+ c0c: 9e b7 in r25, 0x3e ; 62
+ c0e: 0e 96 adiw r24, 0x0e ; 14
+ c10: 8d bf out 0x3d, r24 ; 61
+ c12: 9e bf out 0x3e, r25 ; 62
+ c14: ff cf rjmp .-2 ; 0xc14 <main+0x1b0>
+
+00000c16 <__vector_20>:
int i=0;
ISR(TCC1_OVF_vect){
- bb4: 1f 92 push r1
- bb6: 0f 92 push r0
- bb8: 0f b6 in r0, 0x3f ; 63
- bba: 0f 92 push r0
- bbc: 11 24 eor r1, r1
- bbe: 0b b6 in r0, 0x3b ; 59
- bc0: 0f 92 push r0
- bc2: 8f 92 push r8
- bc4: 9f 92 push r9
- bc6: af 92 push r10
- bc8: bf 92 push r11
- bca: cf 92 push r12
- bcc: df 92 push r13
- bce: ef 92 push r14
- bd0: ff 92 push r15
- bd2: 2f 93 push r18
- bd4: 3f 93 push r19
- bd6: 4f 93 push r20
- bd8: 5f 93 push r21
- bda: 6f 93 push r22
- bdc: 7f 93 push r23
- bde: 8f 93 push r24
- be0: 9f 93 push r25
- be2: af 93 push r26
- be4: bf 93 push r27
- be6: ef 93 push r30
- be8: ff 93 push r31
+ c16: 1f 92 push r1
+ c18: 0f 92 push r0
+ c1a: 0f b6 in r0, 0x3f ; 63
+ c1c: 0f 92 push r0
+ c1e: 11 24 eor r1, r1
+ c20: 0b b6 in r0, 0x3b ; 59
+ c22: 0f 92 push r0
+ c24: cf 92 push r12
+ c26: df 92 push r13
+ c28: ef 92 push r14
+ c2a: ff 92 push r15
+ c2c: 2f 93 push r18
+ c2e: 3f 93 push r19
+ c30: 4f 93 push r20
+ c32: 5f 93 push r21
+ c34: 6f 93 push r22
+ c36: 7f 93 push r23
+ c38: 8f 93 push r24
+ c3a: 9f 93 push r25
+ c3c: af 93 push r26
+ c3e: bf 93 push r27
+ c40: cf 93 push r28
+ c42: df 93 push r29
+ c44: ef 93 push r30
+ c46: ff 93 push r31
i++;
- bea: 80 91 00 20 lds r24, 0x2000 ; 0x802000 <_edata>
- bee: 90 91 01 20 lds r25, 0x2001 ; 0x802001 <_edata+0x1>
- bf2: 01 96 adiw r24, 0x01 ; 1
- bf4: 80 93 00 20 sts 0x2000, r24 ; 0x802000 <_edata>
- bf8: 90 93 01 20 sts 0x2001, r25 ; 0x802001 <_edata+0x1>
+ c48: 80 91 00 20 lds r24, 0x2000 ; 0x802000 <_edata>
+ c4c: 90 91 01 20 lds r25, 0x2001 ; 0x802001 <_edata+0x1>
+ c50: 01 96 adiw r24, 0x01 ; 1
+ c52: 80 93 00 20 sts 0x2000, r24 ; 0x802000 <_edata>
+ c56: 90 93 01 20 sts 0x2001, r25 ; 0x802001 <_edata+0x1>
if(!(i%1000)){ //blink per second
- bfc: 68 ee ldi r22, 0xE8 ; 232
- bfe: 73 e0 ldi r23, 0x03 ; 3
- c00: 0e 94 58 0b call 0x16b0 ; 0x16b0 <__divmodhi4>
- c04: 89 2b or r24, r25
- c06: 19 f4 brne .+6 ; 0xc0e <__vector_20+0x5a>
+ c5a: 68 ee ldi r22, 0xE8 ; 232
+ c5c: 73 e0 ldi r23, 0x03 ; 3
+ c5e: 0e 94 70 0b call 0x16e0 ; 0x16e0 <__divmodhi4>
+ c62: 89 2b or r24, r25
+ c64: 19 f4 brne .+6 ; 0xc6c <__vector_20+0x56>
PORTE_DIRTGL = PIN2_bm;
- c08: 84 e0 ldi r24, 0x04 ; 4
- c0a: 80 93 83 06 sts 0x0683, r24 ; 0x800683 <__TEXT_REGION_LENGTH__+0x700683>
- //set_dac(ATK_DAC_CHANNEL_0, -M_1_pid.filter.filter_reg +2048);
- //set_dac(ATK_DAC_CHANNEL_0, 2048);
-
- //set_dac(ATK_DAC_CHANNEL_0, M_1_pid.setpoint);
-
- set_dac(ATK_DAC_CHANNEL_0, ATK_EN_getValue() +256);
- c0e: 0e 94 13 02 call 0x426 ; 0x426 <ATK_EN_getValue>
- c12: 20 e0 ldi r18, 0x00 ; 0
- c14: 30 e0 ldi r19, 0x00 ; 0
- c16: 40 e8 ldi r20, 0x80 ; 128
- c18: 53 e4 ldi r21, 0x43 ; 67
- c1a: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- c1e: 0e 94 f1 09 call 0x13e2 ; 0x13e2 <__fixunssfsi>
- c22: 81 e0 ldi r24, 0x01 ; 1
- c24: 0e 94 aa 01 call 0x354 ; 0x354 <set_dac>
+ c66: 84 e0 ldi r24, 0x04 ; 4
+ c68: 80 93 83 06 sts 0x0683, r24 ; 0x800683 <__TEXT_REGION_LENGTH__+0x700683>
//set_dac(ATK_DAC_CHANNEL_1, M_1_pid.setpoint + 256);
//set_dac(ATK_DAC_CHANNEL_1, CC.setpoint);
//16.8763 degrees to side 977 ticks per rev 2.7ticks per degree 36 is 0 degree 290 is 90deg
if(RPID_onTarget(&M_1_pid)){
- c28: 8e e0 ldi r24, 0x0E ; 14
- c2a: 90 e2 ldi r25, 0x20 ; 32
- c2c: 0e 94 87 08 call 0x110e ; 0x110e <RPID_onTarget>
- c30: 88 23 and r24, r24
- c32: 21 f1 breq .+72 ; 0xc7c <__vector_20+0xc8>
- PORTE_DIRTGL = PIN3_bm;
- c34: 88 e0 ldi r24, 0x08 ; 8
- c36: 80 93 83 06 sts 0x0683, r24 ; 0x800683 <__TEXT_REGION_LENGTH__+0x700683>
+ c6c: 8e e0 ldi r24, 0x0E ; 14
+ c6e: 90 e2 ldi r25, 0x20 ; 32
+ c70: 0e 94 9f 08 call 0x113e ; 0x113e <RPID_onTarget>
+ c74: 88 23 and r24, r24
+ c76: 09 f1 breq .+66 ; 0xcba <__vector_20+0xa4>
+ //PORTE_DIRTGL = PIN3_bm;
if(M_1_pid.setpoint == OTHERSETPOINT){
- c3a: 20 e0 ldi r18, 0x00 ; 0
- c3c: 30 e0 ldi r19, 0x00 ; 0
- c3e: 4a ef ldi r20, 0xFA ; 250
- c40: 53 e4 ldi r21, 0x43 ; 67
- c42: 60 91 33 20 lds r22, 0x2033 ; 0x802033 <M_1_pid+0x25>
- c46: 70 91 34 20 lds r23, 0x2034 ; 0x802034 <M_1_pid+0x26>
- c4a: 80 91 35 20 lds r24, 0x2035 ; 0x802035 <M_1_pid+0x27>
- c4e: 90 91 36 20 lds r25, 0x2036 ; 0x802036 <M_1_pid+0x28>
- c52: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- c56: 81 11 cpse r24, r1
- c58: 09 c0 rjmp .+18 ; 0xc6c <__vector_20+0xb8>
- RPID_setSetpoint(&M_1_pid, 30);
- c5a: 40 e0 ldi r20, 0x00 ; 0
- c5c: 50 e0 ldi r21, 0x00 ; 0
- c5e: 60 ef ldi r22, 0xF0 ; 240
- c60: 71 e4 ldi r23, 0x41 ; 65
- c62: 8e e0 ldi r24, 0x0E ; 14
- c64: 90 e2 ldi r25, 0x20 ; 32
- c66: 0e 94 81 08 call 0x1102 ; 0x1102 <RPID_setSetpoint>
- c6a: 08 c0 rjmp .+16 ; 0xc7c <__vector_20+0xc8>
- }else{
+ c78: 20 e0 ldi r18, 0x00 ; 0
+ c7a: 30 e0 ldi r19, 0x00 ; 0
+ c7c: 4a ef ldi r20, 0xFA ; 250
+ c7e: 53 e4 ldi r21, 0x43 ; 67
+ c80: 60 91 33 20 lds r22, 0x2033 ; 0x802033 <M_1_pid+0x25>
+ c84: 70 91 34 20 lds r23, 0x2034 ; 0x802034 <M_1_pid+0x26>
+ c88: 80 91 35 20 lds r24, 0x2035 ; 0x802035 <M_1_pid+0x27>
+ c8c: 90 91 36 20 lds r25, 0x2036 ; 0x802036 <M_1_pid+0x28>
+ c90: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ c94: 81 11 cpse r24, r1
+ c96: 09 c0 rjmp .+18 ; 0xcaa <__vector_20+0x94>
+ RPID_setSetpoint(&M_1_pid, 30);
+ c98: 40 e0 ldi r20, 0x00 ; 0
+ c9a: 50 e0 ldi r21, 0x00 ; 0
+ c9c: 60 ef ldi r22, 0xF0 ; 240
+ c9e: 71 e4 ldi r23, 0x41 ; 65
+ ca0: 8e e0 ldi r24, 0x0E ; 14
+ ca2: 90 e2 ldi r25, 0x20 ; 32
+ ca4: 0e 94 99 08 call 0x1132 ; 0x1132 <RPID_setSetpoint>
+ ca8: 08 c0 rjmp .+16 ; 0xcba <__vector_20+0xa4>
+ }else{
RPID_setSetpoint(&M_1_pid, OTHERSETPOINT);
- c6c: 40 e0 ldi r20, 0x00 ; 0
- c6e: 50 e0 ldi r21, 0x00 ; 0
- c70: 6a ef ldi r22, 0xFA ; 250
- c72: 73 e4 ldi r23, 0x43 ; 67
- c74: 8e e0 ldi r24, 0x0E ; 14
- c76: 90 e2 ldi r25, 0x20 ; 32
- c78: 0e 94 81 08 call 0x1102 ; 0x1102 <RPID_setSetpoint>
+ caa: 40 e0 ldi r20, 0x00 ; 0
+ cac: 50 e0 ldi r21, 0x00 ; 0
+ cae: 6a ef ldi r22, 0xFA ; 250
+ cb0: 73 e4 ldi r23, 0x43 ; 67
+ cb2: 8e e0 ldi r24, 0x0E ; 14
+ cb4: 90 e2 ldi r25, 0x20 ; 32
+ cb6: 0e 94 99 08 call 0x1132 ; 0x1132 <RPID_setSetpoint>
}
}
double V_val = RPID_crunch(&M_1_pid, ATK_EN_getValue());
- c7c: 0e 94 13 02 call 0x426 ; 0x426 <ATK_EN_getValue>
- c80: ab 01 movw r20, r22
- c82: bc 01 movw r22, r24
- c84: 8e e0 ldi r24, 0x0E ; 14
- c86: 90 e2 ldi r25, 0x20 ; 32
- c88: 0e 94 de 06 call 0xdbc ; 0xdbc <RPID_crunch>
- c8c: 4b 01 movw r8, r22
- c8e: 5c 01 movw r10, r24
+ cba: 0e 94 0d 02 call 0x41a ; 0x41a <ATK_EN_getValue>
+ cbe: ab 01 movw r20, r22
+ cc0: bc 01 movw r22, r24
+ cc2: 8e e0 ldi r24, 0x0E ; 14
+ cc4: 90 e2 ldi r25, 0x20 ; 32
+ cc6: 0e 94 f6 06 call 0xdec ; 0xdec <RPID_crunch>
+ V_val = 100;
currentc_setSetpoint(&CC, abs(V_val));
- c90: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- c94: 9b 01 movw r18, r22
- c96: 77 23 and r23, r23
- c98: 24 f4 brge .+8 ; 0xca2 <__vector_20+0xee>
- c9a: 22 27 eor r18, r18
- c9c: 33 27 eor r19, r19
- c9e: 26 1b sub r18, r22
- ca0: 37 0b sbc r19, r23
- ca2: b9 01 movw r22, r18
- ca4: 33 0f add r19, r19
- ca6: 88 0b sbc r24, r24
- ca8: 99 0b sbc r25, r25
- caa: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- cae: ab 01 movw r20, r22
- cb0: bc 01 movw r22, r24
- cb2: 84 e5 ldi r24, 0x54 ; 84
- cb4: 90 e2 ldi r25, 0x20 ; 32
- cb6: 0e 94 5b 03 call 0x6b6 ; 0x6b6 <currentc_setSetpoint>
+ cca: 40 e0 ldi r20, 0x00 ; 0
+ ccc: 50 e0 ldi r21, 0x00 ; 0
+ cce: 68 ec ldi r22, 0xC8 ; 200
+ cd0: 72 e4 ldi r23, 0x42 ; 66
+ cd2: 82 e5 ldi r24, 0x52 ; 82
+ cd4: 90 e2 ldi r25, 0x20 ; 32
+ cd6: 0e 94 55 03 call 0x6aa ; 0x6aa <currentc_setSetpoint>
+ //}else {
+ //currentc_setSetpoint(&CC, OTHERSETPOINT);
+ //}
//}
+ if(currentc_onTarget(&CC)){
+ cda: 82 e5 ldi r24, 0x52 ; 82
+ cdc: 90 e2 ldi r25, 0x20 ; 32
+ cde: 0e 94 61 03 call 0x6c2 ; 0x6c2 <currentc_onTarget>
+ ce2: 88 23 and r24, r24
+ ce4: 21 f0 breq .+8 ; 0xcee <__vector_20+0xd8>
+ PORTE_OUTCLR = PIN3_bm;
+ ce6: 88 e0 ldi r24, 0x08 ; 8
+ ce8: 80 93 86 06 sts 0x0686, r24 ; 0x800686 <__TEXT_REGION_LENGTH__+0x700686>
+ cec: 03 c0 rjmp .+6 ; 0xcf4 <__vector_20+0xde>
+ }else{
+ PORTE_OUTSET = PIN3_bm;
+ cee: 88 e0 ldi r24, 0x08 ; 8
+ cf0: 80 93 85 06 sts 0x0685, r24 ; 0x800685 <__TEXT_REGION_LENGTH__+0x700685>
+ }
//value of 4096 is 3.3v
//uint16_t input = l_filter(&CS_filter, r_adc_scan(&ADC_CS));
- int input = l_filter(&CS_filter, r_adc_scan(&ADC_CS)*5.75);//3300mV/ 4096units * unitsmeasured / 0.140mV/mA == MilliAMPS being pulled
- cba: 8a e0 ldi r24, 0x0A ; 10
- cbc: 90 e2 ldi r25, 0x20 ; 32
- cbe: 0e 94 2a 01 call 0x254 ; 0x254 <r_adc_scan>
- cc2: bc 01 movw r22, r24
- cc4: 80 e0 ldi r24, 0x00 ; 0
- cc6: 90 e0 ldi r25, 0x00 ; 0
- cc8: 0e 94 20 0a call 0x1440 ; 0x1440 <__floatunsisf>
- ccc: 20 e0 ldi r18, 0x00 ; 0
- cce: 30 e0 ldi r19, 0x00 ; 0
- cd0: 48 eb ldi r20, 0xB8 ; 184
- cd2: 50 e4 ldi r21, 0x40 ; 64
- cd4: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- cd8: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- cdc: 8a e8 ldi r24, 0x8A ; 138
- cde: 90 e2 ldi r25, 0x20 ; 32
- ce0: 0e 94 e2 03 call 0x7c4 ; 0x7c4 <l_filter>
- //input =150;
+ int unfiltered = r_adc_scan(&ADC_CS)*5.75;
+ cf4: 8a e0 ldi r24, 0x0A ; 10
+ cf6: 90 e2 ldi r25, 0x20 ; 32
+ cf8: 0e 94 2b 01 call 0x256 ; 0x256 <r_adc_scan>
+ cfc: bc 01 movw r22, r24
+ cfe: 80 e0 ldi r24, 0x00 ; 0
+ d00: 90 e0 ldi r25, 0x00 ; 0
+ d02: 0e 94 38 0a call 0x1470 ; 0x1470 <__floatunsisf>
+ d06: 20 e0 ldi r18, 0x00 ; 0
+ d08: 30 e0 ldi r19, 0x00 ; 0
+ d0a: 48 eb ldi r20, 0xB8 ; 184
+ d0c: 50 e4 ldi r21, 0x40 ; 64
+ d0e: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ d12: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ d16: 6b 01 movw r12, r22
+ d18: 7c 01 movw r14, r24
+ uint16_t input = l_filter(&CS_filter, unfiltered);//3300mV/ 4096units * unitsmeasured / 0.140mV/mA == MilliAMPS being pulled
+ d1a: 88 e8 ldi r24, 0x88 ; 136
+ d1c: 90 e2 ldi r25, 0x20 ; 32
+ d1e: 0e 94 fb 03 call 0x7f6 ; 0x7f6 <l_filter>
+ d22: ec 01 movw r28, r24
+ //int input =100;
//set_dac(ATK_DAC_CHANNEL_0, input);
double C_val = currentc_crunch(&CC, input);//value of 4096 is 3.3v
- ce4: bc 01 movw r22, r24
- ce6: 99 0f add r25, r25
- ce8: 88 0b sbc r24, r24
- cea: 99 0b sbc r25, r25
- cec: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- cf0: ab 01 movw r20, r22
- cf2: bc 01 movw r22, r24
- cf4: 84 e5 ldi r24, 0x54 ; 84
- cf6: 90 e2 ldi r25, 0x20 ; 32
- cf8: 0e 94 72 02 call 0x4e4 ; 0x4e4 <currentc_crunch>
- cfc: 6b 01 movw r12, r22
- cfe: 7c 01 movw r14, r24
- set_dac(ATK_DAC_CHANNEL_1, C_val*31 + 550);
- d00: 20 e0 ldi r18, 0x00 ; 0
- d02: 30 e0 ldi r19, 0x00 ; 0
- d04: 48 ef ldi r20, 0xF8 ; 248
- d06: 51 e4 ldi r21, 0x41 ; 65
- d08: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- d0c: 20 e0 ldi r18, 0x00 ; 0
- d0e: 30 e8 ldi r19, 0x80 ; 128
- d10: 49 e0 ldi r20, 0x09 ; 9
- d12: 54 e4 ldi r21, 0x44 ; 68
- d14: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- d18: 0e 94 f1 09 call 0x13e2 ; 0x13e2 <__fixunssfsi>
- d1c: 82 e0 ldi r24, 0x02 ; 2
- d1e: 0e 94 aa 01 call 0x354 ; 0x354 <set_dac>
- motor_set(&M_1, V_val >0? C_val:-C_val);
- d22: 20 e0 ldi r18, 0x00 ; 0
- d24: 30 e0 ldi r19, 0x00 ; 0
- d26: a9 01 movw r20, r18
- d28: c5 01 movw r24, r10
- d2a: b4 01 movw r22, r8
- d2c: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- d30: 18 16 cp r1, r24
- d32: 24 f0 brlt .+8 ; 0xd3c <__vector_20+0x188>
- d34: b7 01 movw r22, r14
- d36: a6 01 movw r20, r12
- d38: 70 58 subi r23, 0x80 ; 128
- d3a: 02 c0 rjmp .+4 ; 0xd40 <__vector_20+0x18c>
- d3c: b7 01 movw r22, r14
- d3e: a6 01 movw r20, r12
- d40: 86 e4 ldi r24, 0x46 ; 70
- d42: 90 e2 ldi r25, 0x20 ; 32
- d44: 0e 94 cf 04 call 0x99e ; 0x99e <motor_set>
+ d24: bc 01 movw r22, r24
+ d26: 80 e0 ldi r24, 0x00 ; 0
+ d28: 90 e0 ldi r25, 0x00 ; 0
+ d2a: 0e 94 38 0a call 0x1470 ; 0x1470 <__floatunsisf>
+ d2e: ab 01 movw r20, r22
+ d30: bc 01 movw r22, r24
+ d32: 82 e5 ldi r24, 0x52 ; 82
+ d34: 90 e2 ldi r25, 0x20 ; 32
+ d36: 0e 94 6c 02 call 0x4d8 ; 0x4d8 <currentc_crunch>
+ //set_dac(ATK_DAC_CHANNEL_1, C_val*31 + 620);//1% = 25mV
+ set_dac(ATK_DAC_CHANNEL_1, unfiltered*6 + 620);//100mA = 250mV
+ d3a: b6 01 movw r22, r12
+ d3c: 66 0f add r22, r22
+ d3e: 77 1f adc r23, r23
+ d40: c6 0e add r12, r22
+ d42: d7 1e adc r13, r23
+ d44: cc 0c add r12, r12
+ d46: dd 1c adc r13, r13
+ d48: b6 01 movw r22, r12
+ d4a: 64 59 subi r22, 0x94 ; 148
+ d4c: 7d 4f sbci r23, 0xFD ; 253
+ d4e: 82 e0 ldi r24, 0x02 ; 2
+ d50: 0e 94 a4 01 call 0x348 ; 0x348 <set_dac>
+ set_dac(ATK_DAC_CHANNEL_0, input*6 + 620);//1mA = 5mV
+ d54: be 01 movw r22, r28
+ d56: 66 0f add r22, r22
+ d58: 77 1f adc r23, r23
+ d5a: 6c 0f add r22, r28
+ d5c: 7d 1f adc r23, r29
+ d5e: 66 0f add r22, r22
+ d60: 77 1f adc r23, r23
+ d62: 64 59 subi r22, 0x94 ; 148
+ d64: 7d 4f sbci r23, 0xFD ; 253
+ d66: 81 e0 ldi r24, 0x01 ; 1
+ d68: 0e 94 a4 01 call 0x348 ; 0x348 <set_dac>
+ //set_dac(ATK_DAC_CHANNEL_0, CONSTRAIN(-20, 0,4096)*20 +620);
+ //set_dac(ATK_DAC_CHANNEL_1, 620);//100mA = 250mV
+
+ //motor_set(&M_1, C_val); //use for current control only mode
+ //motor_set(&M_1, V_val >0? C_val:-C_val);//use for position mode
+ motor_set(&M_1, 40);
+ d6c: 40 e0 ldi r20, 0x00 ; 0
+ d6e: 50 e0 ldi r21, 0x00 ; 0
+ d70: 60 e2 ldi r22, 0x20 ; 32
+ d72: 72 e4 ldi r23, 0x42 ; 66
+ d74: 84 e4 ldi r24, 0x44 ; 68
+ d76: 90 e2 ldi r25, 0x20 ; 32
+ d78: 0e 94 f3 04 call 0x9e6 ; 0x9e6 <motor_set>
//
//set_dac(ATK_DAC_CHANNEL_0, 3000); //0 is blue 1 is red
//set_dac(ATK_DAC_CHANNEL_1, 500);
}
- d48: ff 91 pop r31
- d4a: ef 91 pop r30
- d4c: bf 91 pop r27
- d4e: af 91 pop r26
- d50: 9f 91 pop r25
- d52: 8f 91 pop r24
- d54: 7f 91 pop r23
- d56: 6f 91 pop r22
- d58: 5f 91 pop r21
- d5a: 4f 91 pop r20
- d5c: 3f 91 pop r19
- d5e: 2f 91 pop r18
- d60: ff 90 pop r15
- d62: ef 90 pop r14
- d64: df 90 pop r13
- d66: cf 90 pop r12
- d68: bf 90 pop r11
- d6a: af 90 pop r10
- d6c: 9f 90 pop r9
- d6e: 8f 90 pop r8
- d70: 0f 90 pop r0
- d72: 0b be out 0x3b, r0 ; 59
- d74: 0f 90 pop r0
- d76: 0f be out 0x3f, r0 ; 63
- d78: 0f 90 pop r0
- d7a: 1f 90 pop r1
- d7c: 18 95 reti
-
-00000d7e <pin_init>:
+ d7c: ff 91 pop r31
+ d7e: ef 91 pop r30
+ d80: df 91 pop r29
+ d82: cf 91 pop r28
+ d84: bf 91 pop r27
+ d86: af 91 pop r26
+ d88: 9f 91 pop r25
+ d8a: 8f 91 pop r24
+ d8c: 7f 91 pop r23
+ d8e: 6f 91 pop r22
+ d90: 5f 91 pop r21
+ d92: 4f 91 pop r20
+ d94: 3f 91 pop r19
+ d96: 2f 91 pop r18
+ d98: ff 90 pop r15
+ d9a: ef 90 pop r14
+ d9c: df 90 pop r13
+ d9e: cf 90 pop r12
+ da0: 0f 90 pop r0
+ da2: 0b be out 0x3b, r0 ; 59
+ da4: 0f 90 pop r0
+ da6: 0f be out 0x3f, r0 ; 63
+ da8: 0f 90 pop r0
+ daa: 1f 90 pop r1
+ dac: 18 95 reti
+
+00000dae <pin_init>:
pin_input(pin);
}
}
void pin_output(pin_t *pin){
pin->port->DIRSET = pin->pin_bm;
- d7e: 0f 93 push r16
- d80: fc 01 movw r30, r24
- d82: 60 83 st Z, r22
- d84: 71 83 std Z+1, r23 ; 0x01
- d86: 42 83 std Z+2, r20 ; 0x02
- d88: 23 83 std Z+3, r18 ; 0x03
- d8a: 00 23 and r16, r16
- d8c: 19 f0 breq .+6 ; 0xd94 <pin_init+0x16>
- d8e: fb 01 movw r30, r22
- d90: 41 83 std Z+1, r20 ; 0x01
- d92: 02 c0 rjmp .+4 ; 0xd98 <pin_init+0x1a>
- d94: fb 01 movw r30, r22
- d96: 42 83 std Z+2, r20 ; 0x02
- d98: 0f 91 pop r16
- d9a: 08 95 ret
-
-00000d9c <pin_set>:
+ dae: 0f 93 push r16
+ db0: fc 01 movw r30, r24
+ db2: 60 83 st Z, r22
+ db4: 71 83 std Z+1, r23 ; 0x01
+ db6: 42 83 std Z+2, r20 ; 0x02
+ db8: 23 83 std Z+3, r18 ; 0x03
+ dba: 00 23 and r16, r16
+ dbc: 19 f0 breq .+6 ; 0xdc4 <pin_init+0x16>
+ dbe: fb 01 movw r30, r22
+ dc0: 41 83 std Z+1, r20 ; 0x01
+ dc2: 02 c0 rjmp .+4 ; 0xdc8 <pin_init+0x1a>
+ dc4: fb 01 movw r30, r22
+ dc6: 42 83 std Z+2, r20 ; 0x02
+ dc8: 0f 91 pop r16
+ dca: 08 95 ret
+
+00000dcc <pin_set>:
}
void pin_set(pin_t *pin){
pin->port->OUTSET = pin->pin_bm;
- d9c: dc 01 movw r26, r24
- d9e: ed 91 ld r30, X+
- da0: fc 91 ld r31, X
- da2: 11 97 sbiw r26, 0x01 ; 1
- da4: 12 96 adiw r26, 0x02 ; 2
- da6: 8c 91 ld r24, X
- da8: 85 83 std Z+5, r24 ; 0x05
- daa: 08 95 ret
-
-00000dac <pin_clear>:
+ dcc: dc 01 movw r26, r24
+ dce: ed 91 ld r30, X+
+ dd0: fc 91 ld r31, X
+ dd2: 11 97 sbiw r26, 0x01 ; 1
+ dd4: 12 96 adiw r26, 0x02 ; 2
+ dd6: 8c 91 ld r24, X
+ dd8: 85 83 std Z+5, r24 ; 0x05
+ dda: 08 95 ret
+
+00000ddc <pin_clear>:
}
void pin_clear(pin_t *pin){
pin->port->OUTCLR = pin->pin_bm;
- dac: dc 01 movw r26, r24
- dae: ed 91 ld r30, X+
- db0: fc 91 ld r31, X
- db2: 11 97 sbiw r26, 0x01 ; 1
- db4: 12 96 adiw r26, 0x02 ; 2
- db6: 8c 91 ld r24, X
- db8: 86 83 std Z+6, r24 ; 0x06
- dba: 08 95 ret
-
-00000dbc <RPID_crunch>:
+ ddc: dc 01 movw r26, r24
+ dde: ed 91 ld r30, X+
+ de0: fc 91 ld r31, X
+ de2: 11 97 sbiw r26, 0x01 ; 1
+ de4: 12 96 adiw r26, 0x02 ; 2
+ de6: 8c 91 ld r24, X
+ de8: 86 83 std Z+6, r24 ; 0x06
+ dea: 08 95 ret
+
+00000dec <RPID_crunch>:
void RPID_setSetpoint(RPID_t *pid, double val){
pid->setpoint=val;
}
void RPID_setAcceptableRange(RPID_t *pid, double range){
pid->acceptableRange=range;
- dbc: 4f 92 push r4
- dbe: 5f 92 push r5
- dc0: 6f 92 push r6
- dc2: 7f 92 push r7
- dc4: 8f 92 push r8
- dc6: 9f 92 push r9
- dc8: af 92 push r10
- dca: bf 92 push r11
- dcc: cf 92 push r12
- dce: df 92 push r13
- dd0: ef 92 push r14
- dd2: ff 92 push r15
- dd4: cf 93 push r28
- dd6: df 93 push r29
- dd8: 00 d0 rcall .+0 ; 0xdda <RPID_crunch+0x1e>
- dda: 00 d0 rcall .+0 ; 0xddc <RPID_crunch+0x20>
- ddc: cd b7 in r28, 0x3d ; 61
- dde: de b7 in r29, 0x3e ; 62
- de0: 8d 83 std Y+5, r24 ; 0x05
- de2: 9e 83 std Y+6, r25 ; 0x06
- de4: 9a 01 movw r18, r20
- de6: ab 01 movw r20, r22
- de8: fc 01 movw r30, r24
- dea: 65 a1 ldd r22, Z+37 ; 0x25
- dec: 76 a1 ldd r23, Z+38 ; 0x26
- dee: 87 a1 ldd r24, Z+39 ; 0x27
- df0: 90 a5 ldd r25, Z+40 ; 0x28
- df2: 0e 94 06 09 call 0x120c ; 0x120c <__subsf3>
- df6: 6b 01 movw r12, r22
- df8: 7c 01 movw r14, r24
- dfa: ed 81 ldd r30, Y+5 ; 0x05
- dfc: fe 81 ldd r31, Y+6 ; 0x06
- dfe: 65 8f std Z+29, r22 ; 0x1d
- e00: 76 8f std Z+30, r23 ; 0x1e
- e02: 87 8f std Z+31, r24 ; 0x1f
- e04: 90 a3 std Z+32, r25 ; 0x20
- e06: 80 89 ldd r24, Z+16 ; 0x10
- e08: 80 ff sbrs r24, 0
- e0a: 5e c0 rjmp .+188 ; 0xec8 <RPID_crunch+0x10c>
- e0c: 81 88 ldd r8, Z+17 ; 0x11
- e0e: 92 88 ldd r9, Z+18 ; 0x12
- e10: a3 88 ldd r10, Z+19 ; 0x13
- e12: b4 88 ldd r11, Z+20 ; 0x14
- e14: c7 01 movw r24, r14
- e16: b6 01 movw r22, r12
- e18: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- e1c: 9b 01 movw r18, r22
- e1e: 77 23 and r23, r23
- e20: 24 f4 brge .+8 ; 0xe2a <RPID_crunch+0x6e>
- e22: 22 27 eor r18, r18
- e24: 33 27 eor r19, r19
- e26: 26 1b sub r18, r22
- e28: 37 0b sbc r19, r23
- e2a: a4 01 movw r20, r8
- e2c: 4a 19 sub r20, r10
- e2e: 5b 09 sbc r21, r11
- e30: ca 01 movw r24, r20
- e32: 99 23 and r25, r25
- e34: 0c f4 brge .+2 ; 0xe38 <RPID_crunch+0x7c>
- e36: 01 96 adiw r24, 0x01 ; 1
- e38: 95 95 asr r25
- e3a: 87 95 ror r24
- e3c: 82 17 cp r24, r18
- e3e: 93 07 cpc r25, r19
- e40: 0c f0 brlt .+2 ; 0xe44 <RPID_crunch+0x88>
- e42: 42 c0 rjmp .+132 ; 0xec8 <RPID_crunch+0x10c>
- e44: 20 e0 ldi r18, 0x00 ; 0
- e46: 30 e0 ldi r19, 0x00 ; 0
- e48: a9 01 movw r20, r18
- e4a: c7 01 movw r24, r14
- e4c: b6 01 movw r22, r12
- e4e: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- e52: 18 16 cp r1, r24
- e54: dc f4 brge .+54 ; 0xe8c <RPID_crunch+0xd0>
- e56: b4 01 movw r22, r8
- e58: 99 0c add r9, r9
- e5a: 88 0b sbc r24, r24
- e5c: 99 0b sbc r25, r25
- e5e: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- e62: 9b 01 movw r18, r22
- e64: ac 01 movw r20, r24
- e66: c7 01 movw r24, r14
- e68: b6 01 movw r22, r12
- e6a: 0e 94 06 09 call 0x120c ; 0x120c <__subsf3>
- e6e: 6b 01 movw r12, r22
- e70: 7c 01 movw r14, r24
- e72: b5 01 movw r22, r10
- e74: bb 0c add r11, r11
- e76: 88 0b sbc r24, r24
- e78: 99 0b sbc r25, r25
- e7a: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- e7e: 9b 01 movw r18, r22
- e80: ac 01 movw r20, r24
- e82: c7 01 movw r24, r14
- e84: b6 01 movw r22, r12
- e86: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- e8a: 18 c0 rjmp .+48 ; 0xebc <RPID_crunch+0x100>
- e8c: b4 01 movw r22, r8
- e8e: 99 0c add r9, r9
- e90: 88 0b sbc r24, r24
- e92: 99 0b sbc r25, r25
- e94: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- e98: a7 01 movw r20, r14
- e9a: 96 01 movw r18, r12
- e9c: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- ea0: 6b 01 movw r12, r22
- ea2: 7c 01 movw r14, r24
- ea4: b5 01 movw r22, r10
- ea6: bb 0c add r11, r11
- ea8: 88 0b sbc r24, r24
- eaa: 99 0b sbc r25, r25
- eac: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- eb0: 9b 01 movw r18, r22
- eb2: ac 01 movw r20, r24
- eb4: c7 01 movw r24, r14
- eb6: b6 01 movw r22, r12
- eb8: 0e 94 06 09 call 0x120c ; 0x120c <__subsf3>
- ebc: ed 81 ldd r30, Y+5 ; 0x05
- ebe: fe 81 ldd r31, Y+6 ; 0x06
- ec0: 65 8f std Z+29, r22 ; 0x1d
- ec2: 76 8f std Z+30, r23 ; 0x1e
- ec4: 87 8f std Z+31, r24 ; 0x1f
- ec6: 90 a3 std Z+32, r25 ; 0x20
- ec8: ed 81 ldd r30, Y+5 ; 0x05
- eca: fe 81 ldd r31, Y+6 ; 0x06
- ecc: 85 8c ldd r8, Z+29 ; 0x1d
- ece: 96 8c ldd r9, Z+30 ; 0x1e
- ed0: a7 8c ldd r10, Z+31 ; 0x1f
- ed2: b0 a0 ldd r11, Z+32 ; 0x20
- ed4: 20 81 ld r18, Z
- ed6: 31 81 ldd r19, Z+1 ; 0x01
- ed8: 42 81 ldd r20, Z+2 ; 0x02
- eda: 53 81 ldd r21, Z+3 ; 0x03
- edc: c5 01 movw r24, r10
- ede: b4 01 movw r22, r8
- ee0: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- ee4: 6b 01 movw r12, r22
- ee6: 7c 01 movw r14, r24
- ee8: ed 81 ldd r30, Y+5 ; 0x05
- eea: fe 81 ldd r31, Y+6 ; 0x06
- eec: 65 89 ldd r22, Z+21 ; 0x15
- eee: 76 89 ldd r23, Z+22 ; 0x16
- ef0: 07 2e mov r0, r23
- ef2: 00 0c add r0, r0
- ef4: 88 0b sbc r24, r24
- ef6: 99 0b sbc r25, r25
- ef8: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- efc: 9b 01 movw r18, r22
- efe: ac 01 movw r20, r24
- f00: c7 01 movw r24, r14
- f02: b6 01 movw r22, r12
- f04: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- f08: 88 23 and r24, r24
- f0a: 1c f5 brge .+70 ; 0xf52 <RPID_crunch+0x196>
- f0c: ed 81 ldd r30, Y+5 ; 0x05
- f0e: fe 81 ldd r31, Y+6 ; 0x06
- f10: 67 89 ldd r22, Z+23 ; 0x17
- f12: 70 8d ldd r23, Z+24 ; 0x18
- f14: 07 2e mov r0, r23
- f16: 00 0c add r0, r0
- f18: 88 0b sbc r24, r24
- f1a: 99 0b sbc r25, r25
- f1c: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- f20: 9b 01 movw r18, r22
- f22: ac 01 movw r20, r24
- f24: c7 01 movw r24, r14
- f26: b6 01 movw r22, r12
- f28: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- f2c: 18 16 cp r1, r24
- f2e: 8c f4 brge .+34 ; 0xf52 <RPID_crunch+0x196>
- f30: a5 01 movw r20, r10
- f32: 94 01 movw r18, r8
- f34: ed 81 ldd r30, Y+5 ; 0x05
- f36: fe 81 ldd r31, Y+6 ; 0x06
- f38: 61 a1 ldd r22, Z+33 ; 0x21
- f3a: 72 a1 ldd r23, Z+34 ; 0x22
- f3c: 83 a1 ldd r24, Z+35 ; 0x23
- f3e: 94 a1 ldd r25, Z+36 ; 0x24
- f40: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- f44: ed 81 ldd r30, Y+5 ; 0x05
- f46: fe 81 ldd r31, Y+6 ; 0x06
- f48: 61 a3 std Z+33, r22 ; 0x21
- f4a: 72 a3 std Z+34, r23 ; 0x22
- f4c: 83 a3 std Z+35, r24 ; 0x23
- f4e: 94 a3 std Z+36, r25 ; 0x24
- f50: 06 c0 rjmp .+12 ; 0xf5e <RPID_crunch+0x1a2>
- f52: ed 81 ldd r30, Y+5 ; 0x05
- f54: fe 81 ldd r31, Y+6 ; 0x06
- f56: 11 a2 std Z+33, r1 ; 0x21
- f58: 12 a2 std Z+34, r1 ; 0x22
- f5a: 13 a2 std Z+35, r1 ; 0x23
- f5c: 14 a2 std Z+36, r1 ; 0x24
- f5e: ed 81 ldd r30, Y+5 ; 0x05
- f60: fe 81 ldd r31, Y+6 ; 0x06
- f62: 44 84 ldd r4, Z+12 ; 0x0c
- f64: 55 84 ldd r5, Z+13 ; 0x0d
- f66: 66 84 ldd r6, Z+14 ; 0x0e
- f68: 77 84 ldd r7, Z+15 ; 0x0f
- f6a: 21 a1 ldd r18, Z+33 ; 0x21
- f6c: 32 a1 ldd r19, Z+34 ; 0x22
- f6e: 43 a1 ldd r20, Z+35 ; 0x23
- f70: 54 a1 ldd r21, Z+36 ; 0x24
- f72: 64 81 ldd r22, Z+4 ; 0x04
- f74: 75 81 ldd r23, Z+5 ; 0x05
- f76: 86 81 ldd r24, Z+6 ; 0x06
- f78: 97 81 ldd r25, Z+7 ; 0x07
- f7a: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- f7e: a3 01 movw r20, r6
- f80: 92 01 movw r18, r4
- f82: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- f86: 69 83 std Y+1, r22 ; 0x01
- f88: 7a 83 std Y+2, r23 ; 0x02
- f8a: 8b 83 std Y+3, r24 ; 0x03
- f8c: 9c 83 std Y+4, r25 ; 0x04
+ dec: 4f 92 push r4
+ dee: 5f 92 push r5
+ df0: 6f 92 push r6
+ df2: 7f 92 push r7
+ df4: 8f 92 push r8
+ df6: 9f 92 push r9
+ df8: af 92 push r10
+ dfa: bf 92 push r11
+ dfc: cf 92 push r12
+ dfe: df 92 push r13
+ e00: ef 92 push r14
+ e02: ff 92 push r15
+ e04: cf 93 push r28
+ e06: df 93 push r29
+ e08: 00 d0 rcall .+0 ; 0xe0a <RPID_crunch+0x1e>
+ e0a: 00 d0 rcall .+0 ; 0xe0c <RPID_crunch+0x20>
+ e0c: cd b7 in r28, 0x3d ; 61
+ e0e: de b7 in r29, 0x3e ; 62
+ e10: 8d 83 std Y+5, r24 ; 0x05
+ e12: 9e 83 std Y+6, r25 ; 0x06
+ e14: 9a 01 movw r18, r20
+ e16: ab 01 movw r20, r22
+ e18: fc 01 movw r30, r24
+ e1a: 65 a1 ldd r22, Z+37 ; 0x25
+ e1c: 76 a1 ldd r23, Z+38 ; 0x26
+ e1e: 87 a1 ldd r24, Z+39 ; 0x27
+ e20: 90 a5 ldd r25, Z+40 ; 0x28
+ e22: 0e 94 1e 09 call 0x123c ; 0x123c <__subsf3>
+ e26: 6b 01 movw r12, r22
+ e28: 7c 01 movw r14, r24
+ e2a: ed 81 ldd r30, Y+5 ; 0x05
+ e2c: fe 81 ldd r31, Y+6 ; 0x06
+ e2e: 65 8f std Z+29, r22 ; 0x1d
+ e30: 76 8f std Z+30, r23 ; 0x1e
+ e32: 87 8f std Z+31, r24 ; 0x1f
+ e34: 90 a3 std Z+32, r25 ; 0x20
+ e36: 80 89 ldd r24, Z+16 ; 0x10
+ e38: 80 ff sbrs r24, 0
+ e3a: 5e c0 rjmp .+188 ; 0xef8 <RPID_crunch+0x10c>
+ e3c: 81 88 ldd r8, Z+17 ; 0x11
+ e3e: 92 88 ldd r9, Z+18 ; 0x12
+ e40: a3 88 ldd r10, Z+19 ; 0x13
+ e42: b4 88 ldd r11, Z+20 ; 0x14
+ e44: c7 01 movw r24, r14
+ e46: b6 01 movw r22, r12
+ e48: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ e4c: 9b 01 movw r18, r22
+ e4e: 77 23 and r23, r23
+ e50: 24 f4 brge .+8 ; 0xe5a <RPID_crunch+0x6e>
+ e52: 22 27 eor r18, r18
+ e54: 33 27 eor r19, r19
+ e56: 26 1b sub r18, r22
+ e58: 37 0b sbc r19, r23
+ e5a: a4 01 movw r20, r8
+ e5c: 4a 19 sub r20, r10
+ e5e: 5b 09 sbc r21, r11
+ e60: ca 01 movw r24, r20
+ e62: 99 23 and r25, r25
+ e64: 0c f4 brge .+2 ; 0xe68 <RPID_crunch+0x7c>
+ e66: 01 96 adiw r24, 0x01 ; 1
+ e68: 95 95 asr r25
+ e6a: 87 95 ror r24
+ e6c: 82 17 cp r24, r18
+ e6e: 93 07 cpc r25, r19
+ e70: 0c f0 brlt .+2 ; 0xe74 <RPID_crunch+0x88>
+ e72: 42 c0 rjmp .+132 ; 0xef8 <RPID_crunch+0x10c>
+ e74: 20 e0 ldi r18, 0x00 ; 0
+ e76: 30 e0 ldi r19, 0x00 ; 0
+ e78: a9 01 movw r20, r18
+ e7a: c7 01 movw r24, r14
+ e7c: b6 01 movw r22, r12
+ e7e: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ e82: 18 16 cp r1, r24
+ e84: dc f4 brge .+54 ; 0xebc <RPID_crunch+0xd0>
+ e86: b4 01 movw r22, r8
+ e88: 99 0c add r9, r9
+ e8a: 88 0b sbc r24, r24
+ e8c: 99 0b sbc r25, r25
+ e8e: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ e92: 9b 01 movw r18, r22
+ e94: ac 01 movw r20, r24
+ e96: c7 01 movw r24, r14
+ e98: b6 01 movw r22, r12
+ e9a: 0e 94 1e 09 call 0x123c ; 0x123c <__subsf3>
+ e9e: 6b 01 movw r12, r22
+ ea0: 7c 01 movw r14, r24
+ ea2: b5 01 movw r22, r10
+ ea4: bb 0c add r11, r11
+ ea6: 88 0b sbc r24, r24
+ ea8: 99 0b sbc r25, r25
+ eaa: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ eae: 9b 01 movw r18, r22
+ eb0: ac 01 movw r20, r24
+ eb2: c7 01 movw r24, r14
+ eb4: b6 01 movw r22, r12
+ eb6: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ eba: 18 c0 rjmp .+48 ; 0xeec <RPID_crunch+0x100>
+ ebc: b4 01 movw r22, r8
+ ebe: 99 0c add r9, r9
+ ec0: 88 0b sbc r24, r24
+ ec2: 99 0b sbc r25, r25
+ ec4: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ ec8: a7 01 movw r20, r14
+ eca: 96 01 movw r18, r12
+ ecc: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ ed0: 6b 01 movw r12, r22
+ ed2: 7c 01 movw r14, r24
+ ed4: b5 01 movw r22, r10
+ ed6: bb 0c add r11, r11
+ ed8: 88 0b sbc r24, r24
+ eda: 99 0b sbc r25, r25
+ edc: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ ee0: 9b 01 movw r18, r22
+ ee2: ac 01 movw r20, r24
+ ee4: c7 01 movw r24, r14
+ ee6: b6 01 movw r22, r12
+ ee8: 0e 94 1e 09 call 0x123c ; 0x123c <__subsf3>
+ eec: ed 81 ldd r30, Y+5 ; 0x05
+ eee: fe 81 ldd r31, Y+6 ; 0x06
+ ef0: 65 8f std Z+29, r22 ; 0x1d
+ ef2: 76 8f std Z+30, r23 ; 0x1e
+ ef4: 87 8f std Z+31, r24 ; 0x1f
+ ef6: 90 a3 std Z+32, r25 ; 0x20
+ ef8: ed 81 ldd r30, Y+5 ; 0x05
+ efa: fe 81 ldd r31, Y+6 ; 0x06
+ efc: 85 8c ldd r8, Z+29 ; 0x1d
+ efe: 96 8c ldd r9, Z+30 ; 0x1e
+ f00: a7 8c ldd r10, Z+31 ; 0x1f
+ f02: b0 a0 ldd r11, Z+32 ; 0x20
+ f04: 20 81 ld r18, Z
+ f06: 31 81 ldd r19, Z+1 ; 0x01
+ f08: 42 81 ldd r20, Z+2 ; 0x02
+ f0a: 53 81 ldd r21, Z+3 ; 0x03
+ f0c: c5 01 movw r24, r10
+ f0e: b4 01 movw r22, r8
+ f10: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ f14: 6b 01 movw r12, r22
+ f16: 7c 01 movw r14, r24
+ f18: ed 81 ldd r30, Y+5 ; 0x05
+ f1a: fe 81 ldd r31, Y+6 ; 0x06
+ f1c: 65 89 ldd r22, Z+21 ; 0x15
+ f1e: 76 89 ldd r23, Z+22 ; 0x16
+ f20: 07 2e mov r0, r23
+ f22: 00 0c add r0, r0
+ f24: 88 0b sbc r24, r24
+ f26: 99 0b sbc r25, r25
+ f28: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ f2c: 9b 01 movw r18, r22
+ f2e: ac 01 movw r20, r24
+ f30: c7 01 movw r24, r14
+ f32: b6 01 movw r22, r12
+ f34: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ f38: 88 23 and r24, r24
+ f3a: 1c f5 brge .+70 ; 0xf82 <RPID_crunch+0x196>
+ f3c: ed 81 ldd r30, Y+5 ; 0x05
+ f3e: fe 81 ldd r31, Y+6 ; 0x06
+ f40: 67 89 ldd r22, Z+23 ; 0x17
+ f42: 70 8d ldd r23, Z+24 ; 0x18
+ f44: 07 2e mov r0, r23
+ f46: 00 0c add r0, r0
+ f48: 88 0b sbc r24, r24
+ f4a: 99 0b sbc r25, r25
+ f4c: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ f50: 9b 01 movw r18, r22
+ f52: ac 01 movw r20, r24
+ f54: c7 01 movw r24, r14
+ f56: b6 01 movw r22, r12
+ f58: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ f5c: 18 16 cp r1, r24
+ f5e: 8c f4 brge .+34 ; 0xf82 <RPID_crunch+0x196>
+ f60: a5 01 movw r20, r10
+ f62: 94 01 movw r18, r8
+ f64: ed 81 ldd r30, Y+5 ; 0x05
+ f66: fe 81 ldd r31, Y+6 ; 0x06
+ f68: 61 a1 ldd r22, Z+33 ; 0x21
+ f6a: 72 a1 ldd r23, Z+34 ; 0x22
+ f6c: 83 a1 ldd r24, Z+35 ; 0x23
+ f6e: 94 a1 ldd r25, Z+36 ; 0x24
+ f70: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ f74: ed 81 ldd r30, Y+5 ; 0x05
+ f76: fe 81 ldd r31, Y+6 ; 0x06
+ f78: 61 a3 std Z+33, r22 ; 0x21
+ f7a: 72 a3 std Z+34, r23 ; 0x22
+ f7c: 83 a3 std Z+35, r24 ; 0x23
+ f7e: 94 a3 std Z+36, r25 ; 0x24
+ f80: 06 c0 rjmp .+12 ; 0xf8e <RPID_crunch+0x1a2>
+ f82: ed 81 ldd r30, Y+5 ; 0x05
+ f84: fe 81 ldd r31, Y+6 ; 0x06
+ f86: 11 a2 std Z+33, r1 ; 0x21
+ f88: 12 a2 std Z+34, r1 ; 0x22
+ f8a: 13 a2 std Z+35, r1 ; 0x23
+ f8c: 14 a2 std Z+36, r1 ; 0x24
f8e: ed 81 ldd r30, Y+5 ; 0x05
f90: fe 81 ldd r31, Y+6 ; 0x06
- f92: 21 8d ldd r18, Z+25 ; 0x19
- f94: 32 8d ldd r19, Z+26 ; 0x1a
- f96: 43 8d ldd r20, Z+27 ; 0x1b
- f98: 54 8d ldd r21, Z+28 ; 0x1c
- f9a: c5 01 movw r24, r10
- f9c: b4 01 movw r22, r8
- f9e: 0e 94 06 09 call 0x120c ; 0x120c <__subsf3>
- fa2: a3 01 movw r20, r6
- fa4: 92 01 movw r18, r4
- fa6: 0e 94 78 09 call 0x12f0 ; 0x12f0 <__divsf3>
- faa: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- fae: 8d 81 ldd r24, Y+5 ; 0x05
- fb0: 9e 81 ldd r25, Y+6 ; 0x06
- fb2: 8f 96 adiw r24, 0x2f ; 47
- fb4: 0e 94 e2 03 call 0x7c4 ; 0x7c4 <l_filter>
- fb8: bc 01 movw r22, r24
- fba: 99 0f add r25, r25
- fbc: 88 0b sbc r24, r24
- fbe: 99 0b sbc r25, r25
- fc0: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- fc4: ed 81 ldd r30, Y+5 ; 0x05
- fc6: fe 81 ldd r31, Y+6 ; 0x06
- fc8: 20 85 ldd r18, Z+8 ; 0x08
- fca: 31 85 ldd r19, Z+9 ; 0x09
- fcc: 42 85 ldd r20, Z+10 ; 0x0a
- fce: 53 85 ldd r21, Z+11 ; 0x0b
- fd0: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- fd4: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- fd8: 07 2e mov r0, r23
- fda: 00 0c add r0, r0
- fdc: 88 0b sbc r24, r24
- fde: 99 0b sbc r25, r25
- fe0: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- fe4: 4b 01 movw r8, r22
- fe6: 5c 01 movw r10, r24
- fe8: ed 81 ldd r30, Y+5 ; 0x05
- fea: fe 81 ldd r31, Y+6 ; 0x06
- fec: 65 8d ldd r22, Z+29 ; 0x1d
- fee: 76 8d ldd r23, Z+30 ; 0x1e
- ff0: 87 8d ldd r24, Z+31 ; 0x1f
- ff2: 90 a1 ldd r25, Z+32 ; 0x20
- ff4: 61 8f std Z+25, r22 ; 0x19
- ff6: 72 8f std Z+26, r23 ; 0x1a
- ff8: 83 8f std Z+27, r24 ; 0x1b
- ffa: 94 8f std Z+28, r25 ; 0x1c
- ffc: 0e 94 ea 09 call 0x13d4 ; 0x13d4 <__fixsfsi>
- 1000: 9b 01 movw r18, r22
- 1002: 77 23 and r23, r23
- 1004: 24 f4 brge .+8 ; 0x100e <RPID_crunch+0x252>
- 1006: 22 27 eor r18, r18
- 1008: 33 27 eor r19, r19
- 100a: 26 1b sub r18, r22
- 100c: 37 0b sbc r19, r23
- 100e: b9 01 movw r22, r18
- 1010: 33 0f add r19, r19
- 1012: 88 0b sbc r24, r24
- 1014: 99 0b sbc r25, r25
- 1016: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 101a: ed 81 ldd r30, Y+5 ; 0x05
- 101c: fe 81 ldd r31, Y+6 ; 0x06
- 101e: 21 a5 ldd r18, Z+41 ; 0x29
- 1020: 32 a5 ldd r19, Z+42 ; 0x2a
- 1022: 43 a5 ldd r20, Z+43 ; 0x2b
- 1024: 54 a5 ldd r21, Z+44 ; 0x2c
- 1026: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 102a: 88 23 and r24, r24
- 102c: 44 f4 brge .+16 ; 0x103e <RPID_crunch+0x282>
- 102e: ed 81 ldd r30, Y+5 ; 0x05
- 1030: fe 81 ldd r31, Y+6 ; 0x06
- 1032: 85 a5 ldd r24, Z+45 ; 0x2d
- 1034: 96 a5 ldd r25, Z+46 ; 0x2e
- 1036: 01 96 adiw r24, 0x01 ; 1
- 1038: 85 a7 std Z+45, r24 ; 0x2d
- 103a: 96 a7 std Z+46, r25 ; 0x2e
- 103c: 04 c0 rjmp .+8 ; 0x1046 <RPID_crunch+0x28a>
- 103e: ed 81 ldd r30, Y+5 ; 0x05
- 1040: fe 81 ldd r31, Y+6 ; 0x06
- 1042: 15 a6 std Z+45, r1 ; 0x2d
- 1044: 16 a6 std Z+46, r1 ; 0x2e
- 1046: 29 81 ldd r18, Y+1 ; 0x01
- 1048: 3a 81 ldd r19, Y+2 ; 0x02
- 104a: 4b 81 ldd r20, Y+3 ; 0x03
- 104c: 5c 81 ldd r21, Y+4 ; 0x04
- 104e: c7 01 movw r24, r14
- 1050: b6 01 movw r22, r12
- 1052: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- 1056: a5 01 movw r20, r10
- 1058: 94 01 movw r18, r8
- 105a: 0e 94 07 09 call 0x120e ; 0x120e <__addsf3>
- 105e: b6 2e mov r11, r22
- 1060: a7 2e mov r10, r23
- 1062: 98 2e mov r9, r24
- 1064: 89 2e mov r8, r25
- 1066: ed 81 ldd r30, Y+5 ; 0x05
- 1068: fe 81 ldd r31, Y+6 ; 0x06
- 106a: 67 89 ldd r22, Z+23 ; 0x17
- 106c: 70 8d ldd r23, Z+24 ; 0x18
- 106e: 07 2e mov r0, r23
- 1070: 00 0c add r0, r0
- 1072: 88 0b sbc r24, r24
- 1074: 99 0b sbc r25, r25
- 1076: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 107a: d6 2e mov r13, r22
- 107c: e7 2e mov r14, r23
- 107e: f8 2e mov r15, r24
- 1080: c9 2e mov r12, r25
- 1082: 26 2f mov r18, r22
- 1084: 37 2f mov r19, r23
- 1086: 48 2f mov r20, r24
- 1088: 59 2f mov r21, r25
- 108a: 6b 2d mov r22, r11
- 108c: 7a 2d mov r23, r10
- 108e: 89 2d mov r24, r9
- 1090: 98 2d mov r25, r8
- 1092: 0e 94 73 09 call 0x12e6 ; 0x12e6 <__cmpsf2>
- 1096: 88 23 and r24, r24
- 1098: f4 f0 brlt .+60 ; 0x10d6 <RPID_crunch+0x31a>
- 109a: ed 81 ldd r30, Y+5 ; 0x05
- 109c: fe 81 ldd r31, Y+6 ; 0x06
- 109e: 65 89 ldd r22, Z+21 ; 0x15
- 10a0: 76 89 ldd r23, Z+22 ; 0x16
- 10a2: 07 2e mov r0, r23
- 10a4: 00 0c add r0, r0
- 10a6: 88 0b sbc r24, r24
- 10a8: 99 0b sbc r25, r25
- 10aa: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 10ae: d6 2e mov r13, r22
- 10b0: e7 2e mov r14, r23
- 10b2: f8 2e mov r15, r24
- 10b4: c9 2e mov r12, r25
- 10b6: 26 2f mov r18, r22
- 10b8: 37 2f mov r19, r23
- 10ba: 48 2f mov r20, r24
- 10bc: 59 2f mov r21, r25
- 10be: 6b 2d mov r22, r11
- 10c0: 7a 2d mov r23, r10
- 10c2: 89 2d mov r24, r9
- 10c4: 98 2d mov r25, r8
- 10c6: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- 10ca: 18 16 cp r1, r24
- 10cc: 24 f0 brlt .+8 ; 0x10d6 <RPID_crunch+0x31a>
- 10ce: db 2c mov r13, r11
- 10d0: ea 2c mov r14, r10
- 10d2: f9 2c mov r15, r9
- 10d4: c8 2c mov r12, r8
- 10d6: 6d 2d mov r22, r13
- 10d8: 7e 2d mov r23, r14
- 10da: 8f 2d mov r24, r15
- 10dc: 9c 2d mov r25, r12
- 10de: 26 96 adiw r28, 0x06 ; 6
- 10e0: cd bf out 0x3d, r28 ; 61
- 10e2: de bf out 0x3e, r29 ; 62
- 10e4: df 91 pop r29
- 10e6: cf 91 pop r28
- 10e8: ff 90 pop r15
- 10ea: ef 90 pop r14
- 10ec: df 90 pop r13
- 10ee: cf 90 pop r12
- 10f0: bf 90 pop r11
- 10f2: af 90 pop r10
- 10f4: 9f 90 pop r9
- 10f6: 8f 90 pop r8
- 10f8: 7f 90 pop r7
- 10fa: 6f 90 pop r6
- 10fc: 5f 90 pop r5
- 10fe: 4f 90 pop r4
- 1100: 08 95 ret
-
-00001102 <RPID_setSetpoint>:
- 1102: fc 01 movw r30, r24
- 1104: 45 a3 std Z+37, r20 ; 0x25
- 1106: 56 a3 std Z+38, r21 ; 0x26
- 1108: 67 a3 std Z+39, r22 ; 0x27
- 110a: 70 a7 std Z+40, r23 ; 0x28
- 110c: 08 95 ret
-
-0000110e <RPID_onTarget>:
+ f92: 44 84 ldd r4, Z+12 ; 0x0c
+ f94: 55 84 ldd r5, Z+13 ; 0x0d
+ f96: 66 84 ldd r6, Z+14 ; 0x0e
+ f98: 77 84 ldd r7, Z+15 ; 0x0f
+ f9a: 21 a1 ldd r18, Z+33 ; 0x21
+ f9c: 32 a1 ldd r19, Z+34 ; 0x22
+ f9e: 43 a1 ldd r20, Z+35 ; 0x23
+ fa0: 54 a1 ldd r21, Z+36 ; 0x24
+ fa2: 64 81 ldd r22, Z+4 ; 0x04
+ fa4: 75 81 ldd r23, Z+5 ; 0x05
+ fa6: 86 81 ldd r24, Z+6 ; 0x06
+ fa8: 97 81 ldd r25, Z+7 ; 0x07
+ faa: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ fae: a3 01 movw r20, r6
+ fb0: 92 01 movw r18, r4
+ fb2: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ fb6: 69 83 std Y+1, r22 ; 0x01
+ fb8: 7a 83 std Y+2, r23 ; 0x02
+ fba: 8b 83 std Y+3, r24 ; 0x03
+ fbc: 9c 83 std Y+4, r25 ; 0x04
+ fbe: ed 81 ldd r30, Y+5 ; 0x05
+ fc0: fe 81 ldd r31, Y+6 ; 0x06
+ fc2: 21 8d ldd r18, Z+25 ; 0x19
+ fc4: 32 8d ldd r19, Z+26 ; 0x1a
+ fc6: 43 8d ldd r20, Z+27 ; 0x1b
+ fc8: 54 8d ldd r21, Z+28 ; 0x1c
+ fca: c5 01 movw r24, r10
+ fcc: b4 01 movw r22, r8
+ fce: 0e 94 1e 09 call 0x123c ; 0x123c <__subsf3>
+ fd2: a3 01 movw r20, r6
+ fd4: 92 01 movw r18, r4
+ fd6: 0e 94 90 09 call 0x1320 ; 0x1320 <__divsf3>
+ fda: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ fde: 8d 81 ldd r24, Y+5 ; 0x05
+ fe0: 9e 81 ldd r25, Y+6 ; 0x06
+ fe2: 8f 96 adiw r24, 0x2f ; 47
+ fe4: 0e 94 fb 03 call 0x7f6 ; 0x7f6 <l_filter>
+ fe8: bc 01 movw r22, r24
+ fea: 99 0f add r25, r25
+ fec: 88 0b sbc r24, r24
+ fee: 99 0b sbc r25, r25
+ ff0: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ ff4: ed 81 ldd r30, Y+5 ; 0x05
+ ff6: fe 81 ldd r31, Y+6 ; 0x06
+ ff8: 20 85 ldd r18, Z+8 ; 0x08
+ ffa: 31 85 ldd r19, Z+9 ; 0x09
+ ffc: 42 85 ldd r20, Z+10 ; 0x0a
+ ffe: 53 85 ldd r21, Z+11 ; 0x0b
+ 1000: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 1004: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ 1008: 07 2e mov r0, r23
+ 100a: 00 0c add r0, r0
+ 100c: 88 0b sbc r24, r24
+ 100e: 99 0b sbc r25, r25
+ 1010: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 1014: 4b 01 movw r8, r22
+ 1016: 5c 01 movw r10, r24
+ 1018: ed 81 ldd r30, Y+5 ; 0x05
+ 101a: fe 81 ldd r31, Y+6 ; 0x06
+ 101c: 65 8d ldd r22, Z+29 ; 0x1d
+ 101e: 76 8d ldd r23, Z+30 ; 0x1e
+ 1020: 87 8d ldd r24, Z+31 ; 0x1f
+ 1022: 90 a1 ldd r25, Z+32 ; 0x20
+ 1024: 61 8f std Z+25, r22 ; 0x19
+ 1026: 72 8f std Z+26, r23 ; 0x1a
+ 1028: 83 8f std Z+27, r24 ; 0x1b
+ 102a: 94 8f std Z+28, r25 ; 0x1c
+ 102c: 0e 94 02 0a call 0x1404 ; 0x1404 <__fixsfsi>
+ 1030: 9b 01 movw r18, r22
+ 1032: 77 23 and r23, r23
+ 1034: 24 f4 brge .+8 ; 0x103e <RPID_crunch+0x252>
+ 1036: 22 27 eor r18, r18
+ 1038: 33 27 eor r19, r19
+ 103a: 26 1b sub r18, r22
+ 103c: 37 0b sbc r19, r23
+ 103e: b9 01 movw r22, r18
+ 1040: 33 0f add r19, r19
+ 1042: 88 0b sbc r24, r24
+ 1044: 99 0b sbc r25, r25
+ 1046: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 104a: ed 81 ldd r30, Y+5 ; 0x05
+ 104c: fe 81 ldd r31, Y+6 ; 0x06
+ 104e: 21 a5 ldd r18, Z+41 ; 0x29
+ 1050: 32 a5 ldd r19, Z+42 ; 0x2a
+ 1052: 43 a5 ldd r20, Z+43 ; 0x2b
+ 1054: 54 a5 ldd r21, Z+44 ; 0x2c
+ 1056: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 105a: 88 23 and r24, r24
+ 105c: 44 f4 brge .+16 ; 0x106e <RPID_crunch+0x282>
+ 105e: ed 81 ldd r30, Y+5 ; 0x05
+ 1060: fe 81 ldd r31, Y+6 ; 0x06
+ 1062: 85 a5 ldd r24, Z+45 ; 0x2d
+ 1064: 96 a5 ldd r25, Z+46 ; 0x2e
+ 1066: 01 96 adiw r24, 0x01 ; 1
+ 1068: 85 a7 std Z+45, r24 ; 0x2d
+ 106a: 96 a7 std Z+46, r25 ; 0x2e
+ 106c: 04 c0 rjmp .+8 ; 0x1076 <RPID_crunch+0x28a>
+ 106e: ed 81 ldd r30, Y+5 ; 0x05
+ 1070: fe 81 ldd r31, Y+6 ; 0x06
+ 1072: 15 a6 std Z+45, r1 ; 0x2d
+ 1074: 16 a6 std Z+46, r1 ; 0x2e
+ 1076: 29 81 ldd r18, Y+1 ; 0x01
+ 1078: 3a 81 ldd r19, Y+2 ; 0x02
+ 107a: 4b 81 ldd r20, Y+3 ; 0x03
+ 107c: 5c 81 ldd r21, Y+4 ; 0x04
+ 107e: c7 01 movw r24, r14
+ 1080: b6 01 movw r22, r12
+ 1082: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ 1086: a5 01 movw r20, r10
+ 1088: 94 01 movw r18, r8
+ 108a: 0e 94 1f 09 call 0x123e ; 0x123e <__addsf3>
+ 108e: b6 2e mov r11, r22
+ 1090: a7 2e mov r10, r23
+ 1092: 98 2e mov r9, r24
+ 1094: 89 2e mov r8, r25
+ 1096: ed 81 ldd r30, Y+5 ; 0x05
+ 1098: fe 81 ldd r31, Y+6 ; 0x06
+ 109a: 67 89 ldd r22, Z+23 ; 0x17
+ 109c: 70 8d ldd r23, Z+24 ; 0x18
+ 109e: 07 2e mov r0, r23
+ 10a0: 00 0c add r0, r0
+ 10a2: 88 0b sbc r24, r24
+ 10a4: 99 0b sbc r25, r25
+ 10a6: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 10aa: d6 2e mov r13, r22
+ 10ac: e7 2e mov r14, r23
+ 10ae: f8 2e mov r15, r24
+ 10b0: c9 2e mov r12, r25
+ 10b2: 26 2f mov r18, r22
+ 10b4: 37 2f mov r19, r23
+ 10b6: 48 2f mov r20, r24
+ 10b8: 59 2f mov r21, r25
+ 10ba: 6b 2d mov r22, r11
+ 10bc: 7a 2d mov r23, r10
+ 10be: 89 2d mov r24, r9
+ 10c0: 98 2d mov r25, r8
+ 10c2: 0e 94 8b 09 call 0x1316 ; 0x1316 <__cmpsf2>
+ 10c6: 88 23 and r24, r24
+ 10c8: f4 f0 brlt .+60 ; 0x1106 <RPID_crunch+0x31a>
+ 10ca: ed 81 ldd r30, Y+5 ; 0x05
+ 10cc: fe 81 ldd r31, Y+6 ; 0x06
+ 10ce: 65 89 ldd r22, Z+21 ; 0x15
+ 10d0: 76 89 ldd r23, Z+22 ; 0x16
+ 10d2: 07 2e mov r0, r23
+ 10d4: 00 0c add r0, r0
+ 10d6: 88 0b sbc r24, r24
+ 10d8: 99 0b sbc r25, r25
+ 10da: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 10de: d6 2e mov r13, r22
+ 10e0: e7 2e mov r14, r23
+ 10e2: f8 2e mov r15, r24
+ 10e4: c9 2e mov r12, r25
+ 10e6: 26 2f mov r18, r22
+ 10e8: 37 2f mov r19, r23
+ 10ea: 48 2f mov r20, r24
+ 10ec: 59 2f mov r21, r25
+ 10ee: 6b 2d mov r22, r11
+ 10f0: 7a 2d mov r23, r10
+ 10f2: 89 2d mov r24, r9
+ 10f4: 98 2d mov r25, r8
+ 10f6: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 10fa: 18 16 cp r1, r24
+ 10fc: 24 f0 brlt .+8 ; 0x1106 <RPID_crunch+0x31a>
+ 10fe: db 2c mov r13, r11
+ 1100: ea 2c mov r14, r10
+ 1102: f9 2c mov r15, r9
+ 1104: c8 2c mov r12, r8
+ 1106: 6d 2d mov r22, r13
+ 1108: 7e 2d mov r23, r14
+ 110a: 8f 2d mov r24, r15
+ 110c: 9c 2d mov r25, r12
+ 110e: 26 96 adiw r28, 0x06 ; 6
+ 1110: cd bf out 0x3d, r28 ; 61
+ 1112: de bf out 0x3e, r29 ; 62
+ 1114: df 91 pop r29
+ 1116: cf 91 pop r28
+ 1118: ff 90 pop r15
+ 111a: ef 90 pop r14
+ 111c: df 90 pop r13
+ 111e: cf 90 pop r12
+ 1120: bf 90 pop r11
+ 1122: af 90 pop r10
+ 1124: 9f 90 pop r9
+ 1126: 8f 90 pop r8
+ 1128: 7f 90 pop r7
+ 112a: 6f 90 pop r6
+ 112c: 5f 90 pop r5
+ 112e: 4f 90 pop r4
+ 1130: 08 95 ret
+
+00001132 <RPID_setSetpoint>:
+ 1132: fc 01 movw r30, r24
+ 1134: 45 a3 std Z+37, r20 ; 0x25
+ 1136: 56 a3 std Z+38, r21 ; 0x26
+ 1138: 67 a3 std Z+39, r22 ; 0x27
+ 113a: 70 a7 std Z+40, r23 ; 0x28
+ 113c: 08 95 ret
+
+0000113e <RPID_onTarget>:
}
uint8_t RPID_onTarget(RPID_t *pid){ // if on target for more than 50 millis
- 110e: cf 93 push r28
- 1110: df 93 push r29
- 1112: ec 01 movw r28, r24
+ 113e: cf 93 push r28
+ 1140: df 93 push r29
+ 1142: ec 01 movw r28, r24
return pid->onTargetTicks * pid->dt >0.15;
- 1114: 6d a5 ldd r22, Y+45 ; 0x2d
- 1116: 7e a5 ldd r23, Y+46 ; 0x2e
- 1118: 07 2e mov r0, r23
- 111a: 00 0c add r0, r0
- 111c: 88 0b sbc r24, r24
- 111e: 99 0b sbc r25, r25
- 1120: 0e 94 22 0a call 0x1444 ; 0x1444 <__floatsisf>
- 1124: 2c 85 ldd r18, Y+12 ; 0x0c
- 1126: 3d 85 ldd r19, Y+13 ; 0x0d
- 1128: 4e 85 ldd r20, Y+14 ; 0x0e
- 112a: 5f 85 ldd r21, Y+15 ; 0x0f
- 112c: 0e 94 d7 0a call 0x15ae ; 0x15ae <__mulsf3>
- 1130: c1 e0 ldi r28, 0x01 ; 1
- 1132: 2a e9 ldi r18, 0x9A ; 154
- 1134: 39 e9 ldi r19, 0x99 ; 153
- 1136: 49 e1 ldi r20, 0x19 ; 25
- 1138: 5e e3 ldi r21, 0x3E ; 62
- 113a: 0e 94 d2 0a call 0x15a4 ; 0x15a4 <__gesf2>
- 113e: 18 16 cp r1, r24
- 1140: 0c f0 brlt .+2 ; 0x1144 <RPID_onTarget+0x36>
- 1142: c0 e0 ldi r28, 0x00 ; 0
+ 1144: 6d a5 ldd r22, Y+45 ; 0x2d
+ 1146: 7e a5 ldd r23, Y+46 ; 0x2e
+ 1148: 07 2e mov r0, r23
+ 114a: 00 0c add r0, r0
+ 114c: 88 0b sbc r24, r24
+ 114e: 99 0b sbc r25, r25
+ 1150: 0e 94 3a 0a call 0x1474 ; 0x1474 <__floatsisf>
+ 1154: 2c 85 ldd r18, Y+12 ; 0x0c
+ 1156: 3d 85 ldd r19, Y+13 ; 0x0d
+ 1158: 4e 85 ldd r20, Y+14 ; 0x0e
+ 115a: 5f 85 ldd r21, Y+15 ; 0x0f
+ 115c: 0e 94 ef 0a call 0x15de ; 0x15de <__mulsf3>
+ 1160: c1 e0 ldi r28, 0x01 ; 1
+ 1162: 2a e9 ldi r18, 0x9A ; 154
+ 1164: 39 e9 ldi r19, 0x99 ; 153
+ 1166: 49 e1 ldi r20, 0x19 ; 25
+ 1168: 5e e3 ldi r21, 0x3E ; 62
+ 116a: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__gesf2>
+ 116e: 18 16 cp r1, r24
+ 1170: 0c f0 brlt .+2 ; 0x1174 <RPID_onTarget+0x36>
+ 1172: c0 e0 ldi r28, 0x00 ; 0
}
- 1144: 8c 2f mov r24, r28
- 1146: df 91 pop r29
- 1148: cf 91 pop r28
- 114a: 08 95 ret
+ 1174: 8c 2f mov r24, r28
+ 1176: df 91 pop r29
+ 1178: cf 91 pop r28
+ 117a: 08 95 ret
-0000114c <RPID_init>:
+0000117c <RPID_init>:
void RPID_init(RPID_t *pid, double P, double I, double D, double dt,
uint8_t CONT, int MIN_IN, int MAX_IN, int MIN_OUT, int MAX_OUT, uint8_t K){
- 114c: 8f 92 push r8
- 114e: 9f 92 push r9
- 1150: af 92 push r10
- 1152: bf 92 push r11
- 1154: cf 92 push r12
- 1156: df 92 push r13
- 1158: ef 92 push r14
- 115a: ff 92 push r15
- 115c: 0f 93 push r16
- 115e: 1f 93 push r17
- 1160: cf 93 push r28
- 1162: df 93 push r29
- 1164: cd b7 in r28, 0x3d ; 61
- 1166: de b7 in r29, 0x3e ; 62
- 1168: fc 01 movw r30, r24
+ 117c: 8f 92 push r8
+ 117e: 9f 92 push r9
+ 1180: af 92 push r10
+ 1182: bf 92 push r11
+ 1184: cf 92 push r12
+ 1186: df 92 push r13
+ 1188: ef 92 push r14
+ 118a: ff 92 push r15
+ 118c: 0f 93 push r16
+ 118e: 1f 93 push r17
+ 1190: cf 93 push r28
+ 1192: df 93 push r29
+ 1194: cd b7 in r28, 0x3d ; 61
+ 1196: de b7 in r29, 0x3e ; 62
+ 1198: fc 01 movw r30, r24
pid->P = P;
- 116a: 40 83 st Z, r20
- 116c: 51 83 std Z+1, r21 ; 0x01
- 116e: 62 83 std Z+2, r22 ; 0x02
- 1170: 73 83 std Z+3, r23 ; 0x03
+ 119a: 40 83 st Z, r20
+ 119c: 51 83 std Z+1, r21 ; 0x01
+ 119e: 62 83 std Z+2, r22 ; 0x02
+ 11a0: 73 83 std Z+3, r23 ; 0x03
pid->I=I;
- 1172: 04 83 std Z+4, r16 ; 0x04
- 1174: 15 83 std Z+5, r17 ; 0x05
- 1176: 26 83 std Z+6, r18 ; 0x06
- 1178: 37 83 std Z+7, r19 ; 0x07
+ 11a2: 04 83 std Z+4, r16 ; 0x04
+ 11a4: 15 83 std Z+5, r17 ; 0x05
+ 11a6: 26 83 std Z+6, r18 ; 0x06
+ 11a8: 37 83 std Z+7, r19 ; 0x07
pid->D=D;
- 117a: c0 86 std Z+8, r12 ; 0x08
- 117c: d1 86 std Z+9, r13 ; 0x09
- 117e: e2 86 std Z+10, r14 ; 0x0a
- 1180: f3 86 std Z+11, r15 ; 0x0b
+ 11aa: c0 86 std Z+8, r12 ; 0x08
+ 11ac: d1 86 std Z+9, r13 ; 0x09
+ 11ae: e2 86 std Z+10, r14 ; 0x0a
+ 11b0: f3 86 std Z+11, r15 ; 0x0b
pid->dt=dt;
- 1182: 84 86 std Z+12, r8 ; 0x0c
- 1184: 95 86 std Z+13, r9 ; 0x0d
- 1186: a6 86 std Z+14, r10 ; 0x0e
- 1188: b7 86 std Z+15, r11 ; 0x0f
+ 11b2: 84 86 std Z+12, r8 ; 0x0c
+ 11b4: 95 86 std Z+13, r9 ; 0x0d
+ 11b6: a6 86 std Z+14, r10 ; 0x0e
+ 11b8: b7 86 std Z+15, r11 ; 0x0f
pid->CONT=CONT;
- 118a: 80 89 ldd r24, Z+16 ; 0x10
- 118c: 98 89 ldd r25, Y+16 ; 0x10
- 118e: 90 fb bst r25, 0
- 1190: 80 f9 bld r24, 0
- 1192: 80 8b std Z+16, r24 ; 0x10
+ 11ba: 80 89 ldd r24, Z+16 ; 0x10
+ 11bc: 98 89 ldd r25, Y+16 ; 0x10
+ 11be: 90 fb bst r25, 0
+ 11c0: 80 f9 bld r24, 0
+ 11c2: 80 8b std Z+16, r24 ; 0x10
pid->MIN_IN=MIN_IN;
- 1194: 89 89 ldd r24, Y+17 ; 0x11
- 1196: 9a 89 ldd r25, Y+18 ; 0x12
- 1198: 83 8b std Z+19, r24 ; 0x13
- 119a: 94 8b std Z+20, r25 ; 0x14
+ 11c4: 89 89 ldd r24, Y+17 ; 0x11
+ 11c6: 9a 89 ldd r25, Y+18 ; 0x12
+ 11c8: 83 8b std Z+19, r24 ; 0x13
+ 11ca: 94 8b std Z+20, r25 ; 0x14
pid->MAX_IN=MAX_IN;
- 119c: 8b 89 ldd r24, Y+19 ; 0x13
- 119e: 9c 89 ldd r25, Y+20 ; 0x14
- 11a0: 81 8b std Z+17, r24 ; 0x11
- 11a2: 92 8b std Z+18, r25 ; 0x12
+ 11cc: 8b 89 ldd r24, Y+19 ; 0x13
+ 11ce: 9c 89 ldd r25, Y+20 ; 0x14
+ 11d0: 81 8b std Z+17, r24 ; 0x11
+ 11d2: 92 8b std Z+18, r25 ; 0x12
pid->MIN_OUT=MIN_OUT;
- 11a4: 8d 89 ldd r24, Y+21 ; 0x15
- 11a6: 9e 89 ldd r25, Y+22 ; 0x16
- 11a8: 87 8b std Z+23, r24 ; 0x17
- 11aa: 90 8f std Z+24, r25 ; 0x18
+ 11d4: 8d 89 ldd r24, Y+21 ; 0x15
+ 11d6: 9e 89 ldd r25, Y+22 ; 0x16
+ 11d8: 87 8b std Z+23, r24 ; 0x17
+ 11da: 90 8f std Z+24, r25 ; 0x18
pid->MAX_OUT=MAX_OUT;
- 11ac: 8f 89 ldd r24, Y+23 ; 0x17
- 11ae: 98 8d ldd r25, Y+24 ; 0x18
- 11b0: 85 8b std Z+21, r24 ; 0x15
- 11b2: 96 8b std Z+22, r25 ; 0x16
+ 11dc: 8f 89 ldd r24, Y+23 ; 0x17
+ 11de: 98 8d ldd r25, Y+24 ; 0x18
+ 11e0: 85 8b std Z+21, r24 ; 0x15
+ 11e2: 96 8b std Z+22, r25 ; 0x16
pid->prevError=0;
- 11b4: 11 8e std Z+25, r1 ; 0x19
- 11b6: 12 8e std Z+26, r1 ; 0x1a
- 11b8: 13 8e std Z+27, r1 ; 0x1b
- 11ba: 14 8e std Z+28, r1 ; 0x1c
+ 11e4: 11 8e std Z+25, r1 ; 0x19
+ 11e6: 12 8e std Z+26, r1 ; 0x1a
+ 11e8: 13 8e std Z+27, r1 ; 0x1b
+ 11ea: 14 8e std Z+28, r1 ; 0x1c
pid->currentError=0;
- 11bc: 15 8e std Z+29, r1 ; 0x1d
- 11be: 16 8e std Z+30, r1 ; 0x1e
- 11c0: 17 8e std Z+31, r1 ; 0x1f
- 11c2: 10 a2 std Z+32, r1 ; 0x20
+ 11ec: 15 8e std Z+29, r1 ; 0x1d
+ 11ee: 16 8e std Z+30, r1 ; 0x1e
+ 11f0: 17 8e std Z+31, r1 ; 0x1f
+ 11f2: 10 a2 std Z+32, r1 ; 0x20
pid->totalError=0;
- 11c4: 11 a2 std Z+33, r1 ; 0x21
- 11c6: 12 a2 std Z+34, r1 ; 0x22
- 11c8: 13 a2 std Z+35, r1 ; 0x23
- 11ca: 14 a2 std Z+36, r1 ; 0x24
+ 11f4: 11 a2 std Z+33, r1 ; 0x21
+ 11f6: 12 a2 std Z+34, r1 ; 0x22
+ 11f8: 13 a2 std Z+35, r1 ; 0x23
+ 11fa: 14 a2 std Z+36, r1 ; 0x24
pid->setpoint=0;
- 11cc: 15 a2 std Z+37, r1 ; 0x25
- 11ce: 16 a2 std Z+38, r1 ; 0x26
- 11d0: 17 a2 std Z+39, r1 ; 0x27
- 11d2: 10 a6 std Z+40, r1 ; 0x28
+ 11fc: 15 a2 std Z+37, r1 ; 0x25
+ 11fe: 16 a2 std Z+38, r1 ; 0x26
+ 1200: 17 a2 std Z+39, r1 ; 0x27
+ 1202: 10 a6 std Z+40, r1 ; 0x28
pid->acceptableRange=50;
- 11d4: 80 e0 ldi r24, 0x00 ; 0
- 11d6: 90 e0 ldi r25, 0x00 ; 0
- 11d8: a8 e4 ldi r26, 0x48 ; 72
- 11da: b2 e4 ldi r27, 0x42 ; 66
- 11dc: 81 a7 std Z+41, r24 ; 0x29
- 11de: 92 a7 std Z+42, r25 ; 0x2a
- 11e0: a3 a7 std Z+43, r26 ; 0x2b
- 11e2: b4 a7 std Z+44, r27 ; 0x2c
+ 1204: 80 e0 ldi r24, 0x00 ; 0
+ 1206: 90 e0 ldi r25, 0x00 ; 0
+ 1208: a8 e4 ldi r26, 0x48 ; 72
+ 120a: b2 e4 ldi r27, 0x42 ; 66
+ 120c: 81 a7 std Z+41, r24 ; 0x29
+ 120e: 92 a7 std Z+42, r25 ; 0x2a
+ 1210: a3 a7 std Z+43, r26 ; 0x2b
+ 1212: b4 a7 std Z+44, r27 ; 0x2c
pid->onTargetTicks=0;
- 11e4: 15 a6 std Z+45, r1 ; 0x2d
- 11e6: 16 a6 std Z+46, r1 ; 0x2e
+ 1214: 15 a6 std Z+45, r1 ; 0x2d
+ 1216: 16 a6 std Z+46, r1 ; 0x2e
l_filter_init(&pid->filter, K);
- 11e8: 69 8d ldd r22, Y+25 ; 0x19
- 11ea: cf 01 movw r24, r30
- 11ec: 8f 96 adiw r24, 0x2f ; 47
- 11ee: 0e 94 11 04 call 0x822 ; 0x822 <l_filter_init>
- 11f2: df 91 pop r29
- 11f4: cf 91 pop r28
- 11f6: 1f 91 pop r17
- 11f8: 0f 91 pop r16
- 11fa: ff 90 pop r15
- 11fc: ef 90 pop r14
- 11fe: df 90 pop r13
- 1200: cf 90 pop r12
- 1202: bf 90 pop r11
- 1204: af 90 pop r10
- 1206: 9f 90 pop r9
- 1208: 8f 90 pop r8
- 120a: 08 95 ret
-
-0000120c <__subsf3>:
- 120c: 50 58 subi r21, 0x80 ; 128
-
-0000120e <__addsf3>:
- 120e: bb 27 eor r27, r27
- 1210: aa 27 eor r26, r26
- 1212: 0e 94 1e 09 call 0x123c ; 0x123c <__addsf3x>
- 1216: 0c 94 98 0a jmp 0x1530 ; 0x1530 <__fp_round>
- 121a: 0e 94 8a 0a call 0x1514 ; 0x1514 <__fp_pscA>
- 121e: 38 f0 brcs .+14 ; 0x122e <__addsf3+0x20>
- 1220: 0e 94 91 0a call 0x1522 ; 0x1522 <__fp_pscB>
- 1224: 20 f0 brcs .+8 ; 0x122e <__addsf3+0x20>
- 1226: 39 f4 brne .+14 ; 0x1236 <__addsf3+0x28>
- 1228: 9f 3f cpi r25, 0xFF ; 255
- 122a: 19 f4 brne .+6 ; 0x1232 <__addsf3+0x24>
- 122c: 26 f4 brtc .+8 ; 0x1236 <__addsf3+0x28>
- 122e: 0c 94 87 0a jmp 0x150e ; 0x150e <__fp_nan>
- 1232: 0e f4 brtc .+2 ; 0x1236 <__addsf3+0x28>
- 1234: e0 95 com r30
- 1236: e7 fb bst r30, 7
- 1238: 0c 94 81 0a jmp 0x1502 ; 0x1502 <__fp_inf>
-
-0000123c <__addsf3x>:
- 123c: e9 2f mov r30, r25
- 123e: 0e 94 a9 0a call 0x1552 ; 0x1552 <__fp_split3>
- 1242: 58 f3 brcs .-42 ; 0x121a <__addsf3+0xc>
- 1244: ba 17 cp r27, r26
- 1246: 62 07 cpc r22, r18
- 1248: 73 07 cpc r23, r19
- 124a: 84 07 cpc r24, r20
- 124c: 95 07 cpc r25, r21
- 124e: 20 f0 brcs .+8 ; 0x1258 <__addsf3x+0x1c>
- 1250: 79 f4 brne .+30 ; 0x1270 <__addsf3x+0x34>
- 1252: a6 f5 brtc .+104 ; 0x12bc <__addsf3x+0x80>
- 1254: 0c 94 cb 0a jmp 0x1596 ; 0x1596 <__fp_zero>
- 1258: 0e f4 brtc .+2 ; 0x125c <__addsf3x+0x20>
- 125a: e0 95 com r30
- 125c: 0b 2e mov r0, r27
- 125e: ba 2f mov r27, r26
- 1260: a0 2d mov r26, r0
- 1262: 0b 01 movw r0, r22
- 1264: b9 01 movw r22, r18
- 1266: 90 01 movw r18, r0
- 1268: 0c 01 movw r0, r24
- 126a: ca 01 movw r24, r20
- 126c: a0 01 movw r20, r0
- 126e: 11 24 eor r1, r1
- 1270: ff 27 eor r31, r31
- 1272: 59 1b sub r21, r25
- 1274: 99 f0 breq .+38 ; 0x129c <__addsf3x+0x60>
- 1276: 59 3f cpi r21, 0xF9 ; 249
- 1278: 50 f4 brcc .+20 ; 0x128e <__addsf3x+0x52>
- 127a: 50 3e cpi r21, 0xE0 ; 224
- 127c: 68 f1 brcs .+90 ; 0x12d8 <__addsf3x+0x9c>
- 127e: 1a 16 cp r1, r26
- 1280: f0 40 sbci r31, 0x00 ; 0
- 1282: a2 2f mov r26, r18
- 1284: 23 2f mov r18, r19
- 1286: 34 2f mov r19, r20
- 1288: 44 27 eor r20, r20
- 128a: 58 5f subi r21, 0xF8 ; 248
- 128c: f3 cf rjmp .-26 ; 0x1274 <__addsf3x+0x38>
- 128e: 46 95 lsr r20
- 1290: 37 95 ror r19
- 1292: 27 95 ror r18
- 1294: a7 95 ror r26
- 1296: f0 40 sbci r31, 0x00 ; 0
- 1298: 53 95 inc r21
- 129a: c9 f7 brne .-14 ; 0x128e <__addsf3x+0x52>
- 129c: 7e f4 brtc .+30 ; 0x12bc <__addsf3x+0x80>
- 129e: 1f 16 cp r1, r31
- 12a0: ba 0b sbc r27, r26
- 12a2: 62 0b sbc r22, r18
- 12a4: 73 0b sbc r23, r19
- 12a6: 84 0b sbc r24, r20
- 12a8: ba f0 brmi .+46 ; 0x12d8 <__addsf3x+0x9c>
- 12aa: 91 50 subi r25, 0x01 ; 1
- 12ac: a1 f0 breq .+40 ; 0x12d6 <__addsf3x+0x9a>
- 12ae: ff 0f add r31, r31
- 12b0: bb 1f adc r27, r27
- 12b2: 66 1f adc r22, r22
- 12b4: 77 1f adc r23, r23
- 12b6: 88 1f adc r24, r24
- 12b8: c2 f7 brpl .-16 ; 0x12aa <__addsf3x+0x6e>
- 12ba: 0e c0 rjmp .+28 ; 0x12d8 <__addsf3x+0x9c>
- 12bc: ba 0f add r27, r26
- 12be: 62 1f adc r22, r18
- 12c0: 73 1f adc r23, r19
- 12c2: 84 1f adc r24, r20
- 12c4: 48 f4 brcc .+18 ; 0x12d8 <__addsf3x+0x9c>
- 12c6: 87 95 ror r24
- 12c8: 77 95 ror r23
- 12ca: 67 95 ror r22
- 12cc: b7 95 ror r27
- 12ce: f7 95 ror r31
- 12d0: 9e 3f cpi r25, 0xFE ; 254
- 12d2: 08 f0 brcs .+2 ; 0x12d6 <__addsf3x+0x9a>
- 12d4: b0 cf rjmp .-160 ; 0x1236 <__addsf3+0x28>
- 12d6: 93 95 inc r25
- 12d8: 88 0f add r24, r24
- 12da: 08 f0 brcs .+2 ; 0x12de <__addsf3x+0xa2>
- 12dc: 99 27 eor r25, r25
- 12de: ee 0f add r30, r30
- 12e0: 97 95 ror r25
- 12e2: 87 95 ror r24
- 12e4: 08 95 ret
-
-000012e6 <__cmpsf2>:
- 12e6: 0e 94 5d 0a call 0x14ba ; 0x14ba <__fp_cmp>
- 12ea: 08 f4 brcc .+2 ; 0x12ee <__cmpsf2+0x8>
- 12ec: 81 e0 ldi r24, 0x01 ; 1
- 12ee: 08 95 ret
-
-000012f0 <__divsf3>:
- 12f0: 0e 94 8c 09 call 0x1318 ; 0x1318 <__divsf3x>
- 12f4: 0c 94 98 0a jmp 0x1530 ; 0x1530 <__fp_round>
- 12f8: 0e 94 91 0a call 0x1522 ; 0x1522 <__fp_pscB>
- 12fc: 58 f0 brcs .+22 ; 0x1314 <__divsf3+0x24>
- 12fe: 0e 94 8a 0a call 0x1514 ; 0x1514 <__fp_pscA>
- 1302: 40 f0 brcs .+16 ; 0x1314 <__divsf3+0x24>
- 1304: 29 f4 brne .+10 ; 0x1310 <__divsf3+0x20>
- 1306: 5f 3f cpi r21, 0xFF ; 255
- 1308: 29 f0 breq .+10 ; 0x1314 <__divsf3+0x24>
- 130a: 0c 94 81 0a jmp 0x1502 ; 0x1502 <__fp_inf>
- 130e: 51 11 cpse r21, r1
- 1310: 0c 94 cc 0a jmp 0x1598 ; 0x1598 <__fp_szero>
- 1314: 0c 94 87 0a jmp 0x150e ; 0x150e <__fp_nan>
-
-00001318 <__divsf3x>:
- 1318: 0e 94 a9 0a call 0x1552 ; 0x1552 <__fp_split3>
- 131c: 68 f3 brcs .-38 ; 0x12f8 <__divsf3+0x8>
-
-0000131e <__divsf3_pse>:
- 131e: 99 23 and r25, r25
- 1320: b1 f3 breq .-20 ; 0x130e <__divsf3+0x1e>
- 1322: 55 23 and r21, r21
- 1324: 91 f3 breq .-28 ; 0x130a <__divsf3+0x1a>
- 1326: 95 1b sub r25, r21
- 1328: 55 0b sbc r21, r21
- 132a: bb 27 eor r27, r27
- 132c: aa 27 eor r26, r26
- 132e: 62 17 cp r22, r18
- 1330: 73 07 cpc r23, r19
- 1332: 84 07 cpc r24, r20
- 1334: 38 f0 brcs .+14 ; 0x1344 <__divsf3_pse+0x26>
- 1336: 9f 5f subi r25, 0xFF ; 255
- 1338: 5f 4f sbci r21, 0xFF ; 255
- 133a: 22 0f add r18, r18
- 133c: 33 1f adc r19, r19
- 133e: 44 1f adc r20, r20
- 1340: aa 1f adc r26, r26
- 1342: a9 f3 breq .-22 ; 0x132e <__divsf3_pse+0x10>
- 1344: 35 d0 rcall .+106 ; 0x13b0 <__divsf3_pse+0x92>
- 1346: 0e 2e mov r0, r30
- 1348: 3a f0 brmi .+14 ; 0x1358 <__divsf3_pse+0x3a>
- 134a: e0 e8 ldi r30, 0x80 ; 128
- 134c: 32 d0 rcall .+100 ; 0x13b2 <__divsf3_pse+0x94>
- 134e: 91 50 subi r25, 0x01 ; 1
- 1350: 50 40 sbci r21, 0x00 ; 0
- 1352: e6 95 lsr r30
- 1354: 00 1c adc r0, r0
- 1356: ca f7 brpl .-14 ; 0x134a <__divsf3_pse+0x2c>
- 1358: 2b d0 rcall .+86 ; 0x13b0 <__divsf3_pse+0x92>
- 135a: fe 2f mov r31, r30
- 135c: 29 d0 rcall .+82 ; 0x13b0 <__divsf3_pse+0x92>
- 135e: 66 0f add r22, r22
- 1360: 77 1f adc r23, r23
- 1362: 88 1f adc r24, r24
- 1364: bb 1f adc r27, r27
- 1366: 26 17 cp r18, r22
- 1368: 37 07 cpc r19, r23
- 136a: 48 07 cpc r20, r24
- 136c: ab 07 cpc r26, r27
- 136e: b0 e8 ldi r27, 0x80 ; 128
- 1370: 09 f0 breq .+2 ; 0x1374 <__divsf3_pse+0x56>
- 1372: bb 0b sbc r27, r27
- 1374: 80 2d mov r24, r0
- 1376: bf 01 movw r22, r30
- 1378: ff 27 eor r31, r31
- 137a: 93 58 subi r25, 0x83 ; 131
- 137c: 5f 4f sbci r21, 0xFF ; 255
- 137e: 3a f0 brmi .+14 ; 0x138e <__divsf3_pse+0x70>
- 1380: 9e 3f cpi r25, 0xFE ; 254
- 1382: 51 05 cpc r21, r1
- 1384: 78 f0 brcs .+30 ; 0x13a4 <__divsf3_pse+0x86>
- 1386: 0c 94 81 0a jmp 0x1502 ; 0x1502 <__fp_inf>
- 138a: 0c 94 cc 0a jmp 0x1598 ; 0x1598 <__fp_szero>
- 138e: 5f 3f cpi r21, 0xFF ; 255
- 1390: e4 f3 brlt .-8 ; 0x138a <__divsf3_pse+0x6c>
- 1392: 98 3e cpi r25, 0xE8 ; 232
- 1394: d4 f3 brlt .-12 ; 0x138a <__divsf3_pse+0x6c>
- 1396: 86 95 lsr r24
- 1398: 77 95 ror r23
- 139a: 67 95 ror r22
- 139c: b7 95 ror r27
- 139e: f7 95 ror r31
- 13a0: 9f 5f subi r25, 0xFF ; 255
- 13a2: c9 f7 brne .-14 ; 0x1396 <__divsf3_pse+0x78>
- 13a4: 88 0f add r24, r24
- 13a6: 91 1d adc r25, r1
- 13a8: 96 95 lsr r25
- 13aa: 87 95 ror r24
- 13ac: 97 f9 bld r25, 7
- 13ae: 08 95 ret
- 13b0: e1 e0 ldi r30, 0x01 ; 1
- 13b2: 66 0f add r22, r22
- 13b4: 77 1f adc r23, r23
- 13b6: 88 1f adc r24, r24
- 13b8: bb 1f adc r27, r27
- 13ba: 62 17 cp r22, r18
- 13bc: 73 07 cpc r23, r19
- 13be: 84 07 cpc r24, r20
- 13c0: ba 07 cpc r27, r26
- 13c2: 20 f0 brcs .+8 ; 0x13cc <__divsf3_pse+0xae>
- 13c4: 62 1b sub r22, r18
- 13c6: 73 0b sbc r23, r19
- 13c8: 84 0b sbc r24, r20
- 13ca: ba 0b sbc r27, r26
- 13cc: ee 1f adc r30, r30
- 13ce: 88 f7 brcc .-30 ; 0x13b2 <__divsf3_pse+0x94>
- 13d0: e0 95 com r30
- 13d2: 08 95 ret
-
-000013d4 <__fixsfsi>:
- 13d4: 0e 94 f1 09 call 0x13e2 ; 0x13e2 <__fixunssfsi>
- 13d8: 68 94 set
- 13da: b1 11 cpse r27, r1
- 13dc: 0c 94 cc 0a jmp 0x1598 ; 0x1598 <__fp_szero>
- 13e0: 08 95 ret
-
-000013e2 <__fixunssfsi>:
- 13e2: 0e 94 b1 0a call 0x1562 ; 0x1562 <__fp_splitA>
- 13e6: 88 f0 brcs .+34 ; 0x140a <__fixunssfsi+0x28>
- 13e8: 9f 57 subi r25, 0x7F ; 127
- 13ea: 98 f0 brcs .+38 ; 0x1412 <__fixunssfsi+0x30>
- 13ec: b9 2f mov r27, r25
- 13ee: 99 27 eor r25, r25
- 13f0: b7 51 subi r27, 0x17 ; 23
- 13f2: b0 f0 brcs .+44 ; 0x1420 <__fixunssfsi+0x3e>
- 13f4: e1 f0 breq .+56 ; 0x142e <__fixunssfsi+0x4c>
- 13f6: 66 0f add r22, r22
- 13f8: 77 1f adc r23, r23
- 13fa: 88 1f adc r24, r24
- 13fc: 99 1f adc r25, r25
- 13fe: 1a f0 brmi .+6 ; 0x1406 <__fixunssfsi+0x24>
- 1400: ba 95 dec r27
- 1402: c9 f7 brne .-14 ; 0x13f6 <__fixunssfsi+0x14>
- 1404: 14 c0 rjmp .+40 ; 0x142e <__fixunssfsi+0x4c>
- 1406: b1 30 cpi r27, 0x01 ; 1
- 1408: 91 f0 breq .+36 ; 0x142e <__fixunssfsi+0x4c>
- 140a: 0e 94 cb 0a call 0x1596 ; 0x1596 <__fp_zero>
- 140e: b1 e0 ldi r27, 0x01 ; 1
+ 1218: 69 8d ldd r22, Y+25 ; 0x19
+ 121a: cf 01 movw r24, r30
+ 121c: 8f 96 adiw r24, 0x2f ; 47
+ 121e: 0e 94 37 04 call 0x86e ; 0x86e <l_filter_init>
+ 1222: df 91 pop r29
+ 1224: cf 91 pop r28
+ 1226: 1f 91 pop r17
+ 1228: 0f 91 pop r16
+ 122a: ff 90 pop r15
+ 122c: ef 90 pop r14
+ 122e: df 90 pop r13
+ 1230: cf 90 pop r12
+ 1232: bf 90 pop r11
+ 1234: af 90 pop r10
+ 1236: 9f 90 pop r9
+ 1238: 8f 90 pop r8
+ 123a: 08 95 ret
+
+0000123c <__subsf3>:
+ 123c: 50 58 subi r21, 0x80 ; 128
+
+0000123e <__addsf3>:
+ 123e: bb 27 eor r27, r27
+ 1240: aa 27 eor r26, r26
+ 1242: 0e 94 36 09 call 0x126c ; 0x126c <__addsf3x>
+ 1246: 0c 94 b0 0a jmp 0x1560 ; 0x1560 <__fp_round>
+ 124a: 0e 94 a2 0a call 0x1544 ; 0x1544 <__fp_pscA>
+ 124e: 38 f0 brcs .+14 ; 0x125e <__addsf3+0x20>
+ 1250: 0e 94 a9 0a call 0x1552 ; 0x1552 <__fp_pscB>
+ 1254: 20 f0 brcs .+8 ; 0x125e <__addsf3+0x20>
+ 1256: 39 f4 brne .+14 ; 0x1266 <__addsf3+0x28>
+ 1258: 9f 3f cpi r25, 0xFF ; 255
+ 125a: 19 f4 brne .+6 ; 0x1262 <__addsf3+0x24>
+ 125c: 26 f4 brtc .+8 ; 0x1266 <__addsf3+0x28>
+ 125e: 0c 94 9f 0a jmp 0x153e ; 0x153e <__fp_nan>
+ 1262: 0e f4 brtc .+2 ; 0x1266 <__addsf3+0x28>
+ 1264: e0 95 com r30
+ 1266: e7 fb bst r30, 7
+ 1268: 0c 94 99 0a jmp 0x1532 ; 0x1532 <__fp_inf>
+
+0000126c <__addsf3x>:
+ 126c: e9 2f mov r30, r25
+ 126e: 0e 94 c1 0a call 0x1582 ; 0x1582 <__fp_split3>
+ 1272: 58 f3 brcs .-42 ; 0x124a <__addsf3+0xc>
+ 1274: ba 17 cp r27, r26
+ 1276: 62 07 cpc r22, r18
+ 1278: 73 07 cpc r23, r19
+ 127a: 84 07 cpc r24, r20
+ 127c: 95 07 cpc r25, r21
+ 127e: 20 f0 brcs .+8 ; 0x1288 <__addsf3x+0x1c>
+ 1280: 79 f4 brne .+30 ; 0x12a0 <__addsf3x+0x34>
+ 1282: a6 f5 brtc .+104 ; 0x12ec <__addsf3x+0x80>
+ 1284: 0c 94 e3 0a jmp 0x15c6 ; 0x15c6 <__fp_zero>
+ 1288: 0e f4 brtc .+2 ; 0x128c <__addsf3x+0x20>
+ 128a: e0 95 com r30
+ 128c: 0b 2e mov r0, r27
+ 128e: ba 2f mov r27, r26
+ 1290: a0 2d mov r26, r0
+ 1292: 0b 01 movw r0, r22
+ 1294: b9 01 movw r22, r18
+ 1296: 90 01 movw r18, r0
+ 1298: 0c 01 movw r0, r24
+ 129a: ca 01 movw r24, r20
+ 129c: a0 01 movw r20, r0
+ 129e: 11 24 eor r1, r1
+ 12a0: ff 27 eor r31, r31
+ 12a2: 59 1b sub r21, r25
+ 12a4: 99 f0 breq .+38 ; 0x12cc <__addsf3x+0x60>
+ 12a6: 59 3f cpi r21, 0xF9 ; 249
+ 12a8: 50 f4 brcc .+20 ; 0x12be <__addsf3x+0x52>
+ 12aa: 50 3e cpi r21, 0xE0 ; 224
+ 12ac: 68 f1 brcs .+90 ; 0x1308 <__addsf3x+0x9c>
+ 12ae: 1a 16 cp r1, r26
+ 12b0: f0 40 sbci r31, 0x00 ; 0
+ 12b2: a2 2f mov r26, r18
+ 12b4: 23 2f mov r18, r19
+ 12b6: 34 2f mov r19, r20
+ 12b8: 44 27 eor r20, r20
+ 12ba: 58 5f subi r21, 0xF8 ; 248
+ 12bc: f3 cf rjmp .-26 ; 0x12a4 <__addsf3x+0x38>
+ 12be: 46 95 lsr r20
+ 12c0: 37 95 ror r19
+ 12c2: 27 95 ror r18
+ 12c4: a7 95 ror r26
+ 12c6: f0 40 sbci r31, 0x00 ; 0
+ 12c8: 53 95 inc r21
+ 12ca: c9 f7 brne .-14 ; 0x12be <__addsf3x+0x52>
+ 12cc: 7e f4 brtc .+30 ; 0x12ec <__addsf3x+0x80>
+ 12ce: 1f 16 cp r1, r31
+ 12d0: ba 0b sbc r27, r26
+ 12d2: 62 0b sbc r22, r18
+ 12d4: 73 0b sbc r23, r19
+ 12d6: 84 0b sbc r24, r20
+ 12d8: ba f0 brmi .+46 ; 0x1308 <__addsf3x+0x9c>
+ 12da: 91 50 subi r25, 0x01 ; 1
+ 12dc: a1 f0 breq .+40 ; 0x1306 <__addsf3x+0x9a>
+ 12de: ff 0f add r31, r31
+ 12e0: bb 1f adc r27, r27
+ 12e2: 66 1f adc r22, r22
+ 12e4: 77 1f adc r23, r23
+ 12e6: 88 1f adc r24, r24
+ 12e8: c2 f7 brpl .-16 ; 0x12da <__addsf3x+0x6e>
+ 12ea: 0e c0 rjmp .+28 ; 0x1308 <__addsf3x+0x9c>
+ 12ec: ba 0f add r27, r26
+ 12ee: 62 1f adc r22, r18
+ 12f0: 73 1f adc r23, r19
+ 12f2: 84 1f adc r24, r20
+ 12f4: 48 f4 brcc .+18 ; 0x1308 <__addsf3x+0x9c>
+ 12f6: 87 95 ror r24
+ 12f8: 77 95 ror r23
+ 12fa: 67 95 ror r22
+ 12fc: b7 95 ror r27
+ 12fe: f7 95 ror r31
+ 1300: 9e 3f cpi r25, 0xFE ; 254
+ 1302: 08 f0 brcs .+2 ; 0x1306 <__addsf3x+0x9a>
+ 1304: b0 cf rjmp .-160 ; 0x1266 <__addsf3+0x28>
+ 1306: 93 95 inc r25
+ 1308: 88 0f add r24, r24
+ 130a: 08 f0 brcs .+2 ; 0x130e <__addsf3x+0xa2>
+ 130c: 99 27 eor r25, r25
+ 130e: ee 0f add r30, r30
+ 1310: 97 95 ror r25
+ 1312: 87 95 ror r24
+ 1314: 08 95 ret
+
+00001316 <__cmpsf2>:
+ 1316: 0e 94 75 0a call 0x14ea ; 0x14ea <__fp_cmp>
+ 131a: 08 f4 brcc .+2 ; 0x131e <__cmpsf2+0x8>
+ 131c: 81 e0 ldi r24, 0x01 ; 1
+ 131e: 08 95 ret
+
+00001320 <__divsf3>:
+ 1320: 0e 94 a4 09 call 0x1348 ; 0x1348 <__divsf3x>
+ 1324: 0c 94 b0 0a jmp 0x1560 ; 0x1560 <__fp_round>
+ 1328: 0e 94 a9 0a call 0x1552 ; 0x1552 <__fp_pscB>
+ 132c: 58 f0 brcs .+22 ; 0x1344 <__divsf3+0x24>
+ 132e: 0e 94 a2 0a call 0x1544 ; 0x1544 <__fp_pscA>
+ 1332: 40 f0 brcs .+16 ; 0x1344 <__divsf3+0x24>
+ 1334: 29 f4 brne .+10 ; 0x1340 <__divsf3+0x20>
+ 1336: 5f 3f cpi r21, 0xFF ; 255
+ 1338: 29 f0 breq .+10 ; 0x1344 <__divsf3+0x24>
+ 133a: 0c 94 99 0a jmp 0x1532 ; 0x1532 <__fp_inf>
+ 133e: 51 11 cpse r21, r1
+ 1340: 0c 94 e4 0a jmp 0x15c8 ; 0x15c8 <__fp_szero>
+ 1344: 0c 94 9f 0a jmp 0x153e ; 0x153e <__fp_nan>
+
+00001348 <__divsf3x>:
+ 1348: 0e 94 c1 0a call 0x1582 ; 0x1582 <__fp_split3>
+ 134c: 68 f3 brcs .-38 ; 0x1328 <__divsf3+0x8>
+
+0000134e <__divsf3_pse>:
+ 134e: 99 23 and r25, r25
+ 1350: b1 f3 breq .-20 ; 0x133e <__divsf3+0x1e>
+ 1352: 55 23 and r21, r21
+ 1354: 91 f3 breq .-28 ; 0x133a <__divsf3+0x1a>
+ 1356: 95 1b sub r25, r21
+ 1358: 55 0b sbc r21, r21
+ 135a: bb 27 eor r27, r27
+ 135c: aa 27 eor r26, r26
+ 135e: 62 17 cp r22, r18
+ 1360: 73 07 cpc r23, r19
+ 1362: 84 07 cpc r24, r20
+ 1364: 38 f0 brcs .+14 ; 0x1374 <__divsf3_pse+0x26>
+ 1366: 9f 5f subi r25, 0xFF ; 255
+ 1368: 5f 4f sbci r21, 0xFF ; 255
+ 136a: 22 0f add r18, r18
+ 136c: 33 1f adc r19, r19
+ 136e: 44 1f adc r20, r20
+ 1370: aa 1f adc r26, r26
+ 1372: a9 f3 breq .-22 ; 0x135e <__divsf3_pse+0x10>
+ 1374: 35 d0 rcall .+106 ; 0x13e0 <__divsf3_pse+0x92>
+ 1376: 0e 2e mov r0, r30
+ 1378: 3a f0 brmi .+14 ; 0x1388 <__divsf3_pse+0x3a>
+ 137a: e0 e8 ldi r30, 0x80 ; 128
+ 137c: 32 d0 rcall .+100 ; 0x13e2 <__divsf3_pse+0x94>
+ 137e: 91 50 subi r25, 0x01 ; 1
+ 1380: 50 40 sbci r21, 0x00 ; 0
+ 1382: e6 95 lsr r30
+ 1384: 00 1c adc r0, r0
+ 1386: ca f7 brpl .-14 ; 0x137a <__divsf3_pse+0x2c>
+ 1388: 2b d0 rcall .+86 ; 0x13e0 <__divsf3_pse+0x92>
+ 138a: fe 2f mov r31, r30
+ 138c: 29 d0 rcall .+82 ; 0x13e0 <__divsf3_pse+0x92>
+ 138e: 66 0f add r22, r22
+ 1390: 77 1f adc r23, r23
+ 1392: 88 1f adc r24, r24
+ 1394: bb 1f adc r27, r27
+ 1396: 26 17 cp r18, r22
+ 1398: 37 07 cpc r19, r23
+ 139a: 48 07 cpc r20, r24
+ 139c: ab 07 cpc r26, r27
+ 139e: b0 e8 ldi r27, 0x80 ; 128
+ 13a0: 09 f0 breq .+2 ; 0x13a4 <__divsf3_pse+0x56>
+ 13a2: bb 0b sbc r27, r27
+ 13a4: 80 2d mov r24, r0
+ 13a6: bf 01 movw r22, r30
+ 13a8: ff 27 eor r31, r31
+ 13aa: 93 58 subi r25, 0x83 ; 131
+ 13ac: 5f 4f sbci r21, 0xFF ; 255
+ 13ae: 3a f0 brmi .+14 ; 0x13be <__divsf3_pse+0x70>
+ 13b0: 9e 3f cpi r25, 0xFE ; 254
+ 13b2: 51 05 cpc r21, r1
+ 13b4: 78 f0 brcs .+30 ; 0x13d4 <__divsf3_pse+0x86>
+ 13b6: 0c 94 99 0a jmp 0x1532 ; 0x1532 <__fp_inf>
+ 13ba: 0c 94 e4 0a jmp 0x15c8 ; 0x15c8 <__fp_szero>
+ 13be: 5f 3f cpi r21, 0xFF ; 255
+ 13c0: e4 f3 brlt .-8 ; 0x13ba <__divsf3_pse+0x6c>
+ 13c2: 98 3e cpi r25, 0xE8 ; 232
+ 13c4: d4 f3 brlt .-12 ; 0x13ba <__divsf3_pse+0x6c>
+ 13c6: 86 95 lsr r24
+ 13c8: 77 95 ror r23
+ 13ca: 67 95 ror r22
+ 13cc: b7 95 ror r27
+ 13ce: f7 95 ror r31
+ 13d0: 9f 5f subi r25, 0xFF ; 255
+ 13d2: c9 f7 brne .-14 ; 0x13c6 <__divsf3_pse+0x78>
+ 13d4: 88 0f add r24, r24
+ 13d6: 91 1d adc r25, r1
+ 13d8: 96 95 lsr r25
+ 13da: 87 95 ror r24
+ 13dc: 97 f9 bld r25, 7
+ 13de: 08 95 ret
+ 13e0: e1 e0 ldi r30, 0x01 ; 1
+ 13e2: 66 0f add r22, r22
+ 13e4: 77 1f adc r23, r23
+ 13e6: 88 1f adc r24, r24
+ 13e8: bb 1f adc r27, r27
+ 13ea: 62 17 cp r22, r18
+ 13ec: 73 07 cpc r23, r19
+ 13ee: 84 07 cpc r24, r20
+ 13f0: ba 07 cpc r27, r26
+ 13f2: 20 f0 brcs .+8 ; 0x13fc <__divsf3_pse+0xae>
+ 13f4: 62 1b sub r22, r18
+ 13f6: 73 0b sbc r23, r19
+ 13f8: 84 0b sbc r24, r20
+ 13fa: ba 0b sbc r27, r26
+ 13fc: ee 1f adc r30, r30
+ 13fe: 88 f7 brcc .-30 ; 0x13e2 <__divsf3_pse+0x94>
+ 1400: e0 95 com r30
+ 1402: 08 95 ret
+
+00001404 <__fixsfsi>:
+ 1404: 0e 94 09 0a call 0x1412 ; 0x1412 <__fixunssfsi>
+ 1408: 68 94 set
+ 140a: b1 11 cpse r27, r1
+ 140c: 0c 94 e4 0a jmp 0x15c8 ; 0x15c8 <__fp_szero>
1410: 08 95 ret
- 1412: 0c 94 cb 0a jmp 0x1596 ; 0x1596 <__fp_zero>
- 1416: 67 2f mov r22, r23
- 1418: 78 2f mov r23, r24
- 141a: 88 27 eor r24, r24
- 141c: b8 5f subi r27, 0xF8 ; 248
- 141e: 39 f0 breq .+14 ; 0x142e <__fixunssfsi+0x4c>
- 1420: b9 3f cpi r27, 0xF9 ; 249
- 1422: cc f3 brlt .-14 ; 0x1416 <__fixunssfsi+0x34>
- 1424: 86 95 lsr r24
- 1426: 77 95 ror r23
- 1428: 67 95 ror r22
- 142a: b3 95 inc r27
- 142c: d9 f7 brne .-10 ; 0x1424 <__fixunssfsi+0x42>
- 142e: 3e f4 brtc .+14 ; 0x143e <__fixunssfsi+0x5c>
- 1430: 90 95 com r25
- 1432: 80 95 com r24
- 1434: 70 95 com r23
- 1436: 61 95 neg r22
- 1438: 7f 4f sbci r23, 0xFF ; 255
- 143a: 8f 4f sbci r24, 0xFF ; 255
- 143c: 9f 4f sbci r25, 0xFF ; 255
- 143e: 08 95 ret
-
-00001440 <__floatunsisf>:
- 1440: e8 94 clt
- 1442: 09 c0 rjmp .+18 ; 0x1456 <__floatsisf+0x12>
-
-00001444 <__floatsisf>:
- 1444: 97 fb bst r25, 7
- 1446: 3e f4 brtc .+14 ; 0x1456 <__floatsisf+0x12>
- 1448: 90 95 com r25
- 144a: 80 95 com r24
- 144c: 70 95 com r23
- 144e: 61 95 neg r22
- 1450: 7f 4f sbci r23, 0xFF ; 255
- 1452: 8f 4f sbci r24, 0xFF ; 255
- 1454: 9f 4f sbci r25, 0xFF ; 255
- 1456: 99 23 and r25, r25
- 1458: a9 f0 breq .+42 ; 0x1484 <__floatsisf+0x40>
- 145a: f9 2f mov r31, r25
- 145c: 96 e9 ldi r25, 0x96 ; 150
- 145e: bb 27 eor r27, r27
- 1460: 93 95 inc r25
- 1462: f6 95 lsr r31
- 1464: 87 95 ror r24
- 1466: 77 95 ror r23
- 1468: 67 95 ror r22
- 146a: b7 95 ror r27
- 146c: f1 11 cpse r31, r1
- 146e: f8 cf rjmp .-16 ; 0x1460 <__floatsisf+0x1c>
- 1470: fa f4 brpl .+62 ; 0x14b0 <__floatsisf+0x6c>
- 1472: bb 0f add r27, r27
- 1474: 11 f4 brne .+4 ; 0x147a <__floatsisf+0x36>
- 1476: 60 ff sbrs r22, 0
- 1478: 1b c0 rjmp .+54 ; 0x14b0 <__floatsisf+0x6c>
- 147a: 6f 5f subi r22, 0xFF ; 255
- 147c: 7f 4f sbci r23, 0xFF ; 255
- 147e: 8f 4f sbci r24, 0xFF ; 255
- 1480: 9f 4f sbci r25, 0xFF ; 255
- 1482: 16 c0 rjmp .+44 ; 0x14b0 <__floatsisf+0x6c>
- 1484: 88 23 and r24, r24
- 1486: 11 f0 breq .+4 ; 0x148c <__floatsisf+0x48>
- 1488: 96 e9 ldi r25, 0x96 ; 150
- 148a: 11 c0 rjmp .+34 ; 0x14ae <__floatsisf+0x6a>
- 148c: 77 23 and r23, r23
- 148e: 21 f0 breq .+8 ; 0x1498 <__floatsisf+0x54>
- 1490: 9e e8 ldi r25, 0x8E ; 142
- 1492: 87 2f mov r24, r23
- 1494: 76 2f mov r23, r22
- 1496: 05 c0 rjmp .+10 ; 0x14a2 <__floatsisf+0x5e>
- 1498: 66 23 and r22, r22
- 149a: 71 f0 breq .+28 ; 0x14b8 <__floatsisf+0x74>
- 149c: 96 e8 ldi r25, 0x86 ; 134
- 149e: 86 2f mov r24, r22
- 14a0: 70 e0 ldi r23, 0x00 ; 0
- 14a2: 60 e0 ldi r22, 0x00 ; 0
- 14a4: 2a f0 brmi .+10 ; 0x14b0 <__floatsisf+0x6c>
- 14a6: 9a 95 dec r25
- 14a8: 66 0f add r22, r22
- 14aa: 77 1f adc r23, r23
- 14ac: 88 1f adc r24, r24
- 14ae: da f7 brpl .-10 ; 0x14a6 <__floatsisf+0x62>
- 14b0: 88 0f add r24, r24
- 14b2: 96 95 lsr r25
- 14b4: 87 95 ror r24
- 14b6: 97 f9 bld r25, 7
- 14b8: 08 95 ret
-
-000014ba <__fp_cmp>:
- 14ba: 99 0f add r25, r25
- 14bc: 00 08 sbc r0, r0
- 14be: 55 0f add r21, r21
- 14c0: aa 0b sbc r26, r26
- 14c2: e0 e8 ldi r30, 0x80 ; 128
- 14c4: fe ef ldi r31, 0xFE ; 254
- 14c6: 16 16 cp r1, r22
- 14c8: 17 06 cpc r1, r23
- 14ca: e8 07 cpc r30, r24
- 14cc: f9 07 cpc r31, r25
- 14ce: c0 f0 brcs .+48 ; 0x1500 <__fp_cmp+0x46>
- 14d0: 12 16 cp r1, r18
- 14d2: 13 06 cpc r1, r19
- 14d4: e4 07 cpc r30, r20
- 14d6: f5 07 cpc r31, r21
- 14d8: 98 f0 brcs .+38 ; 0x1500 <__fp_cmp+0x46>
- 14da: 62 1b sub r22, r18
- 14dc: 73 0b sbc r23, r19
- 14de: 84 0b sbc r24, r20
- 14e0: 95 0b sbc r25, r21
- 14e2: 39 f4 brne .+14 ; 0x14f2 <__fp_cmp+0x38>
- 14e4: 0a 26 eor r0, r26
- 14e6: 61 f0 breq .+24 ; 0x1500 <__fp_cmp+0x46>
- 14e8: 23 2b or r18, r19
- 14ea: 24 2b or r18, r20
- 14ec: 25 2b or r18, r21
- 14ee: 21 f4 brne .+8 ; 0x14f8 <__fp_cmp+0x3e>
- 14f0: 08 95 ret
- 14f2: 0a 26 eor r0, r26
- 14f4: 09 f4 brne .+2 ; 0x14f8 <__fp_cmp+0x3e>
- 14f6: a1 40 sbci r26, 0x01 ; 1
- 14f8: a6 95 lsr r26
- 14fa: 8f ef ldi r24, 0xFF ; 255
- 14fc: 81 1d adc r24, r1
- 14fe: 81 1d adc r24, r1
- 1500: 08 95 ret
-
-00001502 <__fp_inf>:
- 1502: 97 f9 bld r25, 7
- 1504: 9f 67 ori r25, 0x7F ; 127
- 1506: 80 e8 ldi r24, 0x80 ; 128
- 1508: 70 e0 ldi r23, 0x00 ; 0
- 150a: 60 e0 ldi r22, 0x00 ; 0
- 150c: 08 95 ret
-
-0000150e <__fp_nan>:
- 150e: 9f ef ldi r25, 0xFF ; 255
- 1510: 80 ec ldi r24, 0xC0 ; 192
- 1512: 08 95 ret
-
-00001514 <__fp_pscA>:
- 1514: 00 24 eor r0, r0
- 1516: 0a 94 dec r0
- 1518: 16 16 cp r1, r22
- 151a: 17 06 cpc r1, r23
- 151c: 18 06 cpc r1, r24
- 151e: 09 06 cpc r0, r25
- 1520: 08 95 ret
-00001522 <__fp_pscB>:
- 1522: 00 24 eor r0, r0
- 1524: 0a 94 dec r0
- 1526: 12 16 cp r1, r18
- 1528: 13 06 cpc r1, r19
- 152a: 14 06 cpc r1, r20
- 152c: 05 06 cpc r0, r21
- 152e: 08 95 ret
-
-00001530 <__fp_round>:
- 1530: 09 2e mov r0, r25
- 1532: 03 94 inc r0
- 1534: 00 0c add r0, r0
- 1536: 11 f4 brne .+4 ; 0x153c <__fp_round+0xc>
- 1538: 88 23 and r24, r24
- 153a: 52 f0 brmi .+20 ; 0x1550 <__fp_round+0x20>
- 153c: bb 0f add r27, r27
- 153e: 40 f4 brcc .+16 ; 0x1550 <__fp_round+0x20>
- 1540: bf 2b or r27, r31
- 1542: 11 f4 brne .+4 ; 0x1548 <__fp_round+0x18>
- 1544: 60 ff sbrs r22, 0
- 1546: 04 c0 rjmp .+8 ; 0x1550 <__fp_round+0x20>
- 1548: 6f 5f subi r22, 0xFF ; 255
- 154a: 7f 4f sbci r23, 0xFF ; 255
- 154c: 8f 4f sbci r24, 0xFF ; 255
- 154e: 9f 4f sbci r25, 0xFF ; 255
+00001412 <__fixunssfsi>:
+ 1412: 0e 94 c9 0a call 0x1592 ; 0x1592 <__fp_splitA>
+ 1416: 88 f0 brcs .+34 ; 0x143a <__fixunssfsi+0x28>
+ 1418: 9f 57 subi r25, 0x7F ; 127
+ 141a: 98 f0 brcs .+38 ; 0x1442 <__fixunssfsi+0x30>
+ 141c: b9 2f mov r27, r25
+ 141e: 99 27 eor r25, r25
+ 1420: b7 51 subi r27, 0x17 ; 23
+ 1422: b0 f0 brcs .+44 ; 0x1450 <__fixunssfsi+0x3e>
+ 1424: e1 f0 breq .+56 ; 0x145e <__fixunssfsi+0x4c>
+ 1426: 66 0f add r22, r22
+ 1428: 77 1f adc r23, r23
+ 142a: 88 1f adc r24, r24
+ 142c: 99 1f adc r25, r25
+ 142e: 1a f0 brmi .+6 ; 0x1436 <__fixunssfsi+0x24>
+ 1430: ba 95 dec r27
+ 1432: c9 f7 brne .-14 ; 0x1426 <__fixunssfsi+0x14>
+ 1434: 14 c0 rjmp .+40 ; 0x145e <__fixunssfsi+0x4c>
+ 1436: b1 30 cpi r27, 0x01 ; 1
+ 1438: 91 f0 breq .+36 ; 0x145e <__fixunssfsi+0x4c>
+ 143a: 0e 94 e3 0a call 0x15c6 ; 0x15c6 <__fp_zero>
+ 143e: b1 e0 ldi r27, 0x01 ; 1
+ 1440: 08 95 ret
+ 1442: 0c 94 e3 0a jmp 0x15c6 ; 0x15c6 <__fp_zero>
+ 1446: 67 2f mov r22, r23
+ 1448: 78 2f mov r23, r24
+ 144a: 88 27 eor r24, r24
+ 144c: b8 5f subi r27, 0xF8 ; 248
+ 144e: 39 f0 breq .+14 ; 0x145e <__fixunssfsi+0x4c>
+ 1450: b9 3f cpi r27, 0xF9 ; 249
+ 1452: cc f3 brlt .-14 ; 0x1446 <__fixunssfsi+0x34>
+ 1454: 86 95 lsr r24
+ 1456: 77 95 ror r23
+ 1458: 67 95 ror r22
+ 145a: b3 95 inc r27
+ 145c: d9 f7 brne .-10 ; 0x1454 <__fixunssfsi+0x42>
+ 145e: 3e f4 brtc .+14 ; 0x146e <__fixunssfsi+0x5c>
+ 1460: 90 95 com r25
+ 1462: 80 95 com r24
+ 1464: 70 95 com r23
+ 1466: 61 95 neg r22
+ 1468: 7f 4f sbci r23, 0xFF ; 255
+ 146a: 8f 4f sbci r24, 0xFF ; 255
+ 146c: 9f 4f sbci r25, 0xFF ; 255
+ 146e: 08 95 ret
+
+00001470 <__floatunsisf>:
+ 1470: e8 94 clt
+ 1472: 09 c0 rjmp .+18 ; 0x1486 <__floatsisf+0x12>
+
+00001474 <__floatsisf>:
+ 1474: 97 fb bst r25, 7
+ 1476: 3e f4 brtc .+14 ; 0x1486 <__floatsisf+0x12>
+ 1478: 90 95 com r25
+ 147a: 80 95 com r24
+ 147c: 70 95 com r23
+ 147e: 61 95 neg r22
+ 1480: 7f 4f sbci r23, 0xFF ; 255
+ 1482: 8f 4f sbci r24, 0xFF ; 255
+ 1484: 9f 4f sbci r25, 0xFF ; 255
+ 1486: 99 23 and r25, r25
+ 1488: a9 f0 breq .+42 ; 0x14b4 <__floatsisf+0x40>
+ 148a: f9 2f mov r31, r25
+ 148c: 96 e9 ldi r25, 0x96 ; 150
+ 148e: bb 27 eor r27, r27
+ 1490: 93 95 inc r25
+ 1492: f6 95 lsr r31
+ 1494: 87 95 ror r24
+ 1496: 77 95 ror r23
+ 1498: 67 95 ror r22
+ 149a: b7 95 ror r27
+ 149c: f1 11 cpse r31, r1
+ 149e: f8 cf rjmp .-16 ; 0x1490 <__floatsisf+0x1c>
+ 14a0: fa f4 brpl .+62 ; 0x14e0 <__floatsisf+0x6c>
+ 14a2: bb 0f add r27, r27
+ 14a4: 11 f4 brne .+4 ; 0x14aa <__floatsisf+0x36>
+ 14a6: 60 ff sbrs r22, 0
+ 14a8: 1b c0 rjmp .+54 ; 0x14e0 <__floatsisf+0x6c>
+ 14aa: 6f 5f subi r22, 0xFF ; 255
+ 14ac: 7f 4f sbci r23, 0xFF ; 255
+ 14ae: 8f 4f sbci r24, 0xFF ; 255
+ 14b0: 9f 4f sbci r25, 0xFF ; 255
+ 14b2: 16 c0 rjmp .+44 ; 0x14e0 <__floatsisf+0x6c>
+ 14b4: 88 23 and r24, r24
+ 14b6: 11 f0 breq .+4 ; 0x14bc <__floatsisf+0x48>
+ 14b8: 96 e9 ldi r25, 0x96 ; 150
+ 14ba: 11 c0 rjmp .+34 ; 0x14de <__floatsisf+0x6a>
+ 14bc: 77 23 and r23, r23
+ 14be: 21 f0 breq .+8 ; 0x14c8 <__floatsisf+0x54>
+ 14c0: 9e e8 ldi r25, 0x8E ; 142
+ 14c2: 87 2f mov r24, r23
+ 14c4: 76 2f mov r23, r22
+ 14c6: 05 c0 rjmp .+10 ; 0x14d2 <__floatsisf+0x5e>
+ 14c8: 66 23 and r22, r22
+ 14ca: 71 f0 breq .+28 ; 0x14e8 <__floatsisf+0x74>
+ 14cc: 96 e8 ldi r25, 0x86 ; 134
+ 14ce: 86 2f mov r24, r22
+ 14d0: 70 e0 ldi r23, 0x00 ; 0
+ 14d2: 60 e0 ldi r22, 0x00 ; 0
+ 14d4: 2a f0 brmi .+10 ; 0x14e0 <__floatsisf+0x6c>
+ 14d6: 9a 95 dec r25
+ 14d8: 66 0f add r22, r22
+ 14da: 77 1f adc r23, r23
+ 14dc: 88 1f adc r24, r24
+ 14de: da f7 brpl .-10 ; 0x14d6 <__floatsisf+0x62>
+ 14e0: 88 0f add r24, r24
+ 14e2: 96 95 lsr r25
+ 14e4: 87 95 ror r24
+ 14e6: 97 f9 bld r25, 7
+ 14e8: 08 95 ret
+
+000014ea <__fp_cmp>:
+ 14ea: 99 0f add r25, r25
+ 14ec: 00 08 sbc r0, r0
+ 14ee: 55 0f add r21, r21
+ 14f0: aa 0b sbc r26, r26
+ 14f2: e0 e8 ldi r30, 0x80 ; 128
+ 14f4: fe ef ldi r31, 0xFE ; 254
+ 14f6: 16 16 cp r1, r22
+ 14f8: 17 06 cpc r1, r23
+ 14fa: e8 07 cpc r30, r24
+ 14fc: f9 07 cpc r31, r25
+ 14fe: c0 f0 brcs .+48 ; 0x1530 <__fp_cmp+0x46>
+ 1500: 12 16 cp r1, r18
+ 1502: 13 06 cpc r1, r19
+ 1504: e4 07 cpc r30, r20
+ 1506: f5 07 cpc r31, r21
+ 1508: 98 f0 brcs .+38 ; 0x1530 <__fp_cmp+0x46>
+ 150a: 62 1b sub r22, r18
+ 150c: 73 0b sbc r23, r19
+ 150e: 84 0b sbc r24, r20
+ 1510: 95 0b sbc r25, r21
+ 1512: 39 f4 brne .+14 ; 0x1522 <__fp_cmp+0x38>
+ 1514: 0a 26 eor r0, r26
+ 1516: 61 f0 breq .+24 ; 0x1530 <__fp_cmp+0x46>
+ 1518: 23 2b or r18, r19
+ 151a: 24 2b or r18, r20
+ 151c: 25 2b or r18, r21
+ 151e: 21 f4 brne .+8 ; 0x1528 <__fp_cmp+0x3e>
+ 1520: 08 95 ret
+ 1522: 0a 26 eor r0, r26
+ 1524: 09 f4 brne .+2 ; 0x1528 <__fp_cmp+0x3e>
+ 1526: a1 40 sbci r26, 0x01 ; 1
+ 1528: a6 95 lsr r26
+ 152a: 8f ef ldi r24, 0xFF ; 255
+ 152c: 81 1d adc r24, r1
+ 152e: 81 1d adc r24, r1
+ 1530: 08 95 ret
+
+00001532 <__fp_inf>:
+ 1532: 97 f9 bld r25, 7
+ 1534: 9f 67 ori r25, 0x7F ; 127
+ 1536: 80 e8 ldi r24, 0x80 ; 128
+ 1538: 70 e0 ldi r23, 0x00 ; 0
+ 153a: 60 e0 ldi r22, 0x00 ; 0
+ 153c: 08 95 ret
+
+0000153e <__fp_nan>:
+ 153e: 9f ef ldi r25, 0xFF ; 255
+ 1540: 80 ec ldi r24, 0xC0 ; 192
+ 1542: 08 95 ret
+
+00001544 <__fp_pscA>:
+ 1544: 00 24 eor r0, r0
+ 1546: 0a 94 dec r0
+ 1548: 16 16 cp r1, r22
+ 154a: 17 06 cpc r1, r23
+ 154c: 18 06 cpc r1, r24
+ 154e: 09 06 cpc r0, r25
1550: 08 95 ret
-00001552 <__fp_split3>:
- 1552: 57 fd sbrc r21, 7
- 1554: 90 58 subi r25, 0x80 ; 128
- 1556: 44 0f add r20, r20
- 1558: 55 1f adc r21, r21
- 155a: 59 f0 breq .+22 ; 0x1572 <__fp_splitA+0x10>
- 155c: 5f 3f cpi r21, 0xFF ; 255
- 155e: 71 f0 breq .+28 ; 0x157c <__fp_splitA+0x1a>
- 1560: 47 95 ror r20
-
-00001562 <__fp_splitA>:
- 1562: 88 0f add r24, r24
- 1564: 97 fb bst r25, 7
- 1566: 99 1f adc r25, r25
- 1568: 61 f0 breq .+24 ; 0x1582 <__fp_splitA+0x20>
- 156a: 9f 3f cpi r25, 0xFF ; 255
- 156c: 79 f0 breq .+30 ; 0x158c <__fp_splitA+0x2a>
- 156e: 87 95 ror r24
- 1570: 08 95 ret
- 1572: 12 16 cp r1, r18
- 1574: 13 06 cpc r1, r19
- 1576: 14 06 cpc r1, r20
- 1578: 55 1f adc r21, r21
- 157a: f2 cf rjmp .-28 ; 0x1560 <__fp_split3+0xe>
- 157c: 46 95 lsr r20
- 157e: f1 df rcall .-30 ; 0x1562 <__fp_splitA>
- 1580: 08 c0 rjmp .+16 ; 0x1592 <__fp_splitA+0x30>
- 1582: 16 16 cp r1, r22
- 1584: 17 06 cpc r1, r23
- 1586: 18 06 cpc r1, r24
- 1588: 99 1f adc r25, r25
- 158a: f1 cf rjmp .-30 ; 0x156e <__fp_splitA+0xc>
- 158c: 86 95 lsr r24
- 158e: 71 05 cpc r23, r1
- 1590: 61 05 cpc r22, r1
- 1592: 08 94 sec
- 1594: 08 95 ret
-
-00001596 <__fp_zero>:
- 1596: e8 94 clt
-
-00001598 <__fp_szero>:
- 1598: bb 27 eor r27, r27
- 159a: 66 27 eor r22, r22
- 159c: 77 27 eor r23, r23
- 159e: cb 01 movw r24, r22
- 15a0: 97 f9 bld r25, 7
- 15a2: 08 95 ret
-
-000015a4 <__gesf2>:
- 15a4: 0e 94 5d 0a call 0x14ba ; 0x14ba <__fp_cmp>
- 15a8: 08 f4 brcc .+2 ; 0x15ac <__gesf2+0x8>
- 15aa: 8f ef ldi r24, 0xFF ; 255
- 15ac: 08 95 ret
-
-000015ae <__mulsf3>:
- 15ae: 0e 94 ea 0a call 0x15d4 ; 0x15d4 <__mulsf3x>
- 15b2: 0c 94 98 0a jmp 0x1530 ; 0x1530 <__fp_round>
- 15b6: 0e 94 8a 0a call 0x1514 ; 0x1514 <__fp_pscA>
- 15ba: 38 f0 brcs .+14 ; 0x15ca <__mulsf3+0x1c>
- 15bc: 0e 94 91 0a call 0x1522 ; 0x1522 <__fp_pscB>
- 15c0: 20 f0 brcs .+8 ; 0x15ca <__mulsf3+0x1c>
- 15c2: 95 23 and r25, r21
- 15c4: 11 f0 breq .+4 ; 0x15ca <__mulsf3+0x1c>
- 15c6: 0c 94 81 0a jmp 0x1502 ; 0x1502 <__fp_inf>
- 15ca: 0c 94 87 0a jmp 0x150e ; 0x150e <__fp_nan>
- 15ce: 11 24 eor r1, r1
- 15d0: 0c 94 cc 0a jmp 0x1598 ; 0x1598 <__fp_szero>
-
-000015d4 <__mulsf3x>:
- 15d4: 0e 94 a9 0a call 0x1552 ; 0x1552 <__fp_split3>
- 15d8: 70 f3 brcs .-36 ; 0x15b6 <__mulsf3+0x8>
-
-000015da <__mulsf3_pse>:
- 15da: 95 9f mul r25, r21
- 15dc: c1 f3 breq .-16 ; 0x15ce <__mulsf3+0x20>
- 15de: 95 0f add r25, r21
- 15e0: 50 e0 ldi r21, 0x00 ; 0
- 15e2: 55 1f adc r21, r21
- 15e4: 62 9f mul r22, r18
- 15e6: f0 01 movw r30, r0
- 15e8: 72 9f mul r23, r18
- 15ea: bb 27 eor r27, r27
- 15ec: f0 0d add r31, r0
- 15ee: b1 1d adc r27, r1
- 15f0: 63 9f mul r22, r19
- 15f2: aa 27 eor r26, r26
- 15f4: f0 0d add r31, r0
- 15f6: b1 1d adc r27, r1
- 15f8: aa 1f adc r26, r26
- 15fa: 64 9f mul r22, r20
- 15fc: 66 27 eor r22, r22
- 15fe: b0 0d add r27, r0
- 1600: a1 1d adc r26, r1
- 1602: 66 1f adc r22, r22
- 1604: 82 9f mul r24, r18
- 1606: 22 27 eor r18, r18
- 1608: b0 0d add r27, r0
- 160a: a1 1d adc r26, r1
- 160c: 62 1f adc r22, r18
- 160e: 73 9f mul r23, r19
- 1610: b0 0d add r27, r0
- 1612: a1 1d adc r26, r1
- 1614: 62 1f adc r22, r18
- 1616: 83 9f mul r24, r19
- 1618: a0 0d add r26, r0
- 161a: 61 1d adc r22, r1
- 161c: 22 1f adc r18, r18
- 161e: 74 9f mul r23, r20
- 1620: 33 27 eor r19, r19
- 1622: a0 0d add r26, r0
- 1624: 61 1d adc r22, r1
- 1626: 23 1f adc r18, r19
- 1628: 84 9f mul r24, r20
- 162a: 60 0d add r22, r0
- 162c: 21 1d adc r18, r1
- 162e: 82 2f mov r24, r18
- 1630: 76 2f mov r23, r22
- 1632: 6a 2f mov r22, r26
- 1634: 11 24 eor r1, r1
- 1636: 9f 57 subi r25, 0x7F ; 127
- 1638: 50 40 sbci r21, 0x00 ; 0
- 163a: 9a f0 brmi .+38 ; 0x1662 <__mulsf3_pse+0x88>
- 163c: f1 f0 breq .+60 ; 0x167a <__mulsf3_pse+0xa0>
- 163e: 88 23 and r24, r24
- 1640: 4a f0 brmi .+18 ; 0x1654 <__mulsf3_pse+0x7a>
- 1642: ee 0f add r30, r30
- 1644: ff 1f adc r31, r31
- 1646: bb 1f adc r27, r27
- 1648: 66 1f adc r22, r22
- 164a: 77 1f adc r23, r23
- 164c: 88 1f adc r24, r24
- 164e: 91 50 subi r25, 0x01 ; 1
- 1650: 50 40 sbci r21, 0x00 ; 0
- 1652: a9 f7 brne .-22 ; 0x163e <__mulsf3_pse+0x64>
- 1654: 9e 3f cpi r25, 0xFE ; 254
- 1656: 51 05 cpc r21, r1
- 1658: 80 f0 brcs .+32 ; 0x167a <__mulsf3_pse+0xa0>
- 165a: 0c 94 81 0a jmp 0x1502 ; 0x1502 <__fp_inf>
- 165e: 0c 94 cc 0a jmp 0x1598 ; 0x1598 <__fp_szero>
- 1662: 5f 3f cpi r21, 0xFF ; 255
- 1664: e4 f3 brlt .-8 ; 0x165e <__mulsf3_pse+0x84>
- 1666: 98 3e cpi r25, 0xE8 ; 232
- 1668: d4 f3 brlt .-12 ; 0x165e <__mulsf3_pse+0x84>
- 166a: 86 95 lsr r24
- 166c: 77 95 ror r23
- 166e: 67 95 ror r22
- 1670: b7 95 ror r27
- 1672: f7 95 ror r31
- 1674: e7 95 ror r30
- 1676: 9f 5f subi r25, 0xFF ; 255
- 1678: c1 f7 brne .-16 ; 0x166a <__mulsf3_pse+0x90>
- 167a: fe 2b or r31, r30
- 167c: 88 0f add r24, r24
- 167e: 91 1d adc r25, r1
- 1680: 96 95 lsr r25
- 1682: 87 95 ror r24
- 1684: 97 f9 bld r25, 7
- 1686: 08 95 ret
-
-00001688 <__udivmodhi4>:
- 1688: aa 1b sub r26, r26
- 168a: bb 1b sub r27, r27
- 168c: 51 e1 ldi r21, 0x11 ; 17
- 168e: 07 c0 rjmp .+14 ; 0x169e <__udivmodhi4_ep>
-
-00001690 <__udivmodhi4_loop>:
- 1690: aa 1f adc r26, r26
- 1692: bb 1f adc r27, r27
- 1694: a6 17 cp r26, r22
- 1696: b7 07 cpc r27, r23
- 1698: 10 f0 brcs .+4 ; 0x169e <__udivmodhi4_ep>
- 169a: a6 1b sub r26, r22
- 169c: b7 0b sbc r27, r23
-
-0000169e <__udivmodhi4_ep>:
- 169e: 88 1f adc r24, r24
- 16a0: 99 1f adc r25, r25
- 16a2: 5a 95 dec r21
- 16a4: a9 f7 brne .-22 ; 0x1690 <__udivmodhi4_loop>
- 16a6: 80 95 com r24
- 16a8: 90 95 com r25
- 16aa: bc 01 movw r22, r24
- 16ac: cd 01 movw r24, r26
- 16ae: 08 95 ret
-
-000016b0 <__divmodhi4>:
- 16b0: 97 fb bst r25, 7
- 16b2: 07 2e mov r0, r23
- 16b4: 16 f4 brtc .+4 ; 0x16ba <__divmodhi4+0xa>
- 16b6: 00 94 com r0
- 16b8: 07 d0 rcall .+14 ; 0x16c8 <__divmodhi4_neg1>
- 16ba: 77 fd sbrc r23, 7
- 16bc: 09 d0 rcall .+18 ; 0x16d0 <__divmodhi4_neg2>
- 16be: 0e 94 44 0b call 0x1688 ; 0x1688 <__udivmodhi4>
- 16c2: 07 fc sbrc r0, 7
- 16c4: 05 d0 rcall .+10 ; 0x16d0 <__divmodhi4_neg2>
- 16c6: 3e f4 brtc .+14 ; 0x16d6 <__divmodhi4_exit>
-
-000016c8 <__divmodhi4_neg1>:
- 16c8: 90 95 com r25
- 16ca: 81 95 neg r24
- 16cc: 9f 4f sbci r25, 0xFF ; 255
- 16ce: 08 95 ret
-
-000016d0 <__divmodhi4_neg2>:
- 16d0: 70 95 com r23
- 16d2: 61 95 neg r22
- 16d4: 7f 4f sbci r23, 0xFF ; 255
-
-000016d6 <__divmodhi4_exit>:
- 16d6: 08 95 ret
-
-000016d8 <_exit>:
- 16d8: f8 94 cli
-
-000016da <__stop_program>:
- 16da: ff cf rjmp .-2 ; 0x16da <__stop_program>
+00001552 <__fp_pscB>:
+ 1552: 00 24 eor r0, r0
+ 1554: 0a 94 dec r0
+ 1556: 12 16 cp r1, r18
+ 1558: 13 06 cpc r1, r19
+ 155a: 14 06 cpc r1, r20
+ 155c: 05 06 cpc r0, r21
+ 155e: 08 95 ret
+
+00001560 <__fp_round>:
+ 1560: 09 2e mov r0, r25
+ 1562: 03 94 inc r0
+ 1564: 00 0c add r0, r0
+ 1566: 11 f4 brne .+4 ; 0x156c <__fp_round+0xc>
+ 1568: 88 23 and r24, r24
+ 156a: 52 f0 brmi .+20 ; 0x1580 <__fp_round+0x20>
+ 156c: bb 0f add r27, r27
+ 156e: 40 f4 brcc .+16 ; 0x1580 <__fp_round+0x20>
+ 1570: bf 2b or r27, r31
+ 1572: 11 f4 brne .+4 ; 0x1578 <__fp_round+0x18>
+ 1574: 60 ff sbrs r22, 0
+ 1576: 04 c0 rjmp .+8 ; 0x1580 <__fp_round+0x20>
+ 1578: 6f 5f subi r22, 0xFF ; 255
+ 157a: 7f 4f sbci r23, 0xFF ; 255
+ 157c: 8f 4f sbci r24, 0xFF ; 255
+ 157e: 9f 4f sbci r25, 0xFF ; 255
+ 1580: 08 95 ret
+
+00001582 <__fp_split3>:
+ 1582: 57 fd sbrc r21, 7
+ 1584: 90 58 subi r25, 0x80 ; 128
+ 1586: 44 0f add r20, r20
+ 1588: 55 1f adc r21, r21
+ 158a: 59 f0 breq .+22 ; 0x15a2 <__fp_splitA+0x10>
+ 158c: 5f 3f cpi r21, 0xFF ; 255
+ 158e: 71 f0 breq .+28 ; 0x15ac <__fp_splitA+0x1a>
+ 1590: 47 95 ror r20
+
+00001592 <__fp_splitA>:
+ 1592: 88 0f add r24, r24
+ 1594: 97 fb bst r25, 7
+ 1596: 99 1f adc r25, r25
+ 1598: 61 f0 breq .+24 ; 0x15b2 <__fp_splitA+0x20>
+ 159a: 9f 3f cpi r25, 0xFF ; 255
+ 159c: 79 f0 breq .+30 ; 0x15bc <__fp_splitA+0x2a>
+ 159e: 87 95 ror r24
+ 15a0: 08 95 ret
+ 15a2: 12 16 cp r1, r18
+ 15a4: 13 06 cpc r1, r19
+ 15a6: 14 06 cpc r1, r20
+ 15a8: 55 1f adc r21, r21
+ 15aa: f2 cf rjmp .-28 ; 0x1590 <__fp_split3+0xe>
+ 15ac: 46 95 lsr r20
+ 15ae: f1 df rcall .-30 ; 0x1592 <__fp_splitA>
+ 15b0: 08 c0 rjmp .+16 ; 0x15c2 <__fp_splitA+0x30>
+ 15b2: 16 16 cp r1, r22
+ 15b4: 17 06 cpc r1, r23
+ 15b6: 18 06 cpc r1, r24
+ 15b8: 99 1f adc r25, r25
+ 15ba: f1 cf rjmp .-30 ; 0x159e <__fp_splitA+0xc>
+ 15bc: 86 95 lsr r24
+ 15be: 71 05 cpc r23, r1
+ 15c0: 61 05 cpc r22, r1
+ 15c2: 08 94 sec
+ 15c4: 08 95 ret
+
+000015c6 <__fp_zero>:
+ 15c6: e8 94 clt
+
+000015c8 <__fp_szero>:
+ 15c8: bb 27 eor r27, r27
+ 15ca: 66 27 eor r22, r22
+ 15cc: 77 27 eor r23, r23
+ 15ce: cb 01 movw r24, r22
+ 15d0: 97 f9 bld r25, 7
+ 15d2: 08 95 ret
+
+000015d4 <__gesf2>:
+ 15d4: 0e 94 75 0a call 0x14ea ; 0x14ea <__fp_cmp>
+ 15d8: 08 f4 brcc .+2 ; 0x15dc <__gesf2+0x8>
+ 15da: 8f ef ldi r24, 0xFF ; 255
+ 15dc: 08 95 ret
+
+000015de <__mulsf3>:
+ 15de: 0e 94 02 0b call 0x1604 ; 0x1604 <__mulsf3x>
+ 15e2: 0c 94 b0 0a jmp 0x1560 ; 0x1560 <__fp_round>
+ 15e6: 0e 94 a2 0a call 0x1544 ; 0x1544 <__fp_pscA>
+ 15ea: 38 f0 brcs .+14 ; 0x15fa <__mulsf3+0x1c>
+ 15ec: 0e 94 a9 0a call 0x1552 ; 0x1552 <__fp_pscB>
+ 15f0: 20 f0 brcs .+8 ; 0x15fa <__mulsf3+0x1c>
+ 15f2: 95 23 and r25, r21
+ 15f4: 11 f0 breq .+4 ; 0x15fa <__mulsf3+0x1c>
+ 15f6: 0c 94 99 0a jmp 0x1532 ; 0x1532 <__fp_inf>
+ 15fa: 0c 94 9f 0a jmp 0x153e ; 0x153e <__fp_nan>
+ 15fe: 11 24 eor r1, r1
+ 1600: 0c 94 e4 0a jmp 0x15c8 ; 0x15c8 <__fp_szero>
+
+00001604 <__mulsf3x>:
+ 1604: 0e 94 c1 0a call 0x1582 ; 0x1582 <__fp_split3>
+ 1608: 70 f3 brcs .-36 ; 0x15e6 <__mulsf3+0x8>
+
+0000160a <__mulsf3_pse>:
+ 160a: 95 9f mul r25, r21
+ 160c: c1 f3 breq .-16 ; 0x15fe <__mulsf3+0x20>
+ 160e: 95 0f add r25, r21
+ 1610: 50 e0 ldi r21, 0x00 ; 0
+ 1612: 55 1f adc r21, r21
+ 1614: 62 9f mul r22, r18
+ 1616: f0 01 movw r30, r0
+ 1618: 72 9f mul r23, r18
+ 161a: bb 27 eor r27, r27
+ 161c: f0 0d add r31, r0
+ 161e: b1 1d adc r27, r1
+ 1620: 63 9f mul r22, r19
+ 1622: aa 27 eor r26, r26
+ 1624: f0 0d add r31, r0
+ 1626: b1 1d adc r27, r1
+ 1628: aa 1f adc r26, r26
+ 162a: 64 9f mul r22, r20
+ 162c: 66 27 eor r22, r22
+ 162e: b0 0d add r27, r0
+ 1630: a1 1d adc r26, r1
+ 1632: 66 1f adc r22, r22
+ 1634: 82 9f mul r24, r18
+ 1636: 22 27 eor r18, r18
+ 1638: b0 0d add r27, r0
+ 163a: a1 1d adc r26, r1
+ 163c: 62 1f adc r22, r18
+ 163e: 73 9f mul r23, r19
+ 1640: b0 0d add r27, r0
+ 1642: a1 1d adc r26, r1
+ 1644: 62 1f adc r22, r18
+ 1646: 83 9f mul r24, r19
+ 1648: a0 0d add r26, r0
+ 164a: 61 1d adc r22, r1
+ 164c: 22 1f adc r18, r18
+ 164e: 74 9f mul r23, r20
+ 1650: 33 27 eor r19, r19
+ 1652: a0 0d add r26, r0
+ 1654: 61 1d adc r22, r1
+ 1656: 23 1f adc r18, r19
+ 1658: 84 9f mul r24, r20
+ 165a: 60 0d add r22, r0
+ 165c: 21 1d adc r18, r1
+ 165e: 82 2f mov r24, r18
+ 1660: 76 2f mov r23, r22
+ 1662: 6a 2f mov r22, r26
+ 1664: 11 24 eor r1, r1
+ 1666: 9f 57 subi r25, 0x7F ; 127
+ 1668: 50 40 sbci r21, 0x00 ; 0
+ 166a: 9a f0 brmi .+38 ; 0x1692 <__mulsf3_pse+0x88>
+ 166c: f1 f0 breq .+60 ; 0x16aa <__mulsf3_pse+0xa0>
+ 166e: 88 23 and r24, r24
+ 1670: 4a f0 brmi .+18 ; 0x1684 <__mulsf3_pse+0x7a>
+ 1672: ee 0f add r30, r30
+ 1674: ff 1f adc r31, r31
+ 1676: bb 1f adc r27, r27
+ 1678: 66 1f adc r22, r22
+ 167a: 77 1f adc r23, r23
+ 167c: 88 1f adc r24, r24
+ 167e: 91 50 subi r25, 0x01 ; 1
+ 1680: 50 40 sbci r21, 0x00 ; 0
+ 1682: a9 f7 brne .-22 ; 0x166e <__mulsf3_pse+0x64>
+ 1684: 9e 3f cpi r25, 0xFE ; 254
+ 1686: 51 05 cpc r21, r1
+ 1688: 80 f0 brcs .+32 ; 0x16aa <__mulsf3_pse+0xa0>
+ 168a: 0c 94 99 0a jmp 0x1532 ; 0x1532 <__fp_inf>
+ 168e: 0c 94 e4 0a jmp 0x15c8 ; 0x15c8 <__fp_szero>
+ 1692: 5f 3f cpi r21, 0xFF ; 255
+ 1694: e4 f3 brlt .-8 ; 0x168e <__mulsf3_pse+0x84>
+ 1696: 98 3e cpi r25, 0xE8 ; 232
+ 1698: d4 f3 brlt .-12 ; 0x168e <__mulsf3_pse+0x84>
+ 169a: 86 95 lsr r24
+ 169c: 77 95 ror r23
+ 169e: 67 95 ror r22
+ 16a0: b7 95 ror r27
+ 16a2: f7 95 ror r31
+ 16a4: e7 95 ror r30
+ 16a6: 9f 5f subi r25, 0xFF ; 255
+ 16a8: c1 f7 brne .-16 ; 0x169a <__mulsf3_pse+0x90>
+ 16aa: fe 2b or r31, r30
+ 16ac: 88 0f add r24, r24
+ 16ae: 91 1d adc r25, r1
+ 16b0: 96 95 lsr r25
+ 16b2: 87 95 ror r24
+ 16b4: 97 f9 bld r25, 7
+ 16b6: 08 95 ret
+
+000016b8 <__udivmodhi4>:
+ 16b8: aa 1b sub r26, r26
+ 16ba: bb 1b sub r27, r27
+ 16bc: 51 e1 ldi r21, 0x11 ; 17
+ 16be: 07 c0 rjmp .+14 ; 0x16ce <__udivmodhi4_ep>
+
+000016c0 <__udivmodhi4_loop>:
+ 16c0: aa 1f adc r26, r26
+ 16c2: bb 1f adc r27, r27
+ 16c4: a6 17 cp r26, r22
+ 16c6: b7 07 cpc r27, r23
+ 16c8: 10 f0 brcs .+4 ; 0x16ce <__udivmodhi4_ep>
+ 16ca: a6 1b sub r26, r22
+ 16cc: b7 0b sbc r27, r23
+
+000016ce <__udivmodhi4_ep>:
+ 16ce: 88 1f adc r24, r24
+ 16d0: 99 1f adc r25, r25
+ 16d2: 5a 95 dec r21
+ 16d4: a9 f7 brne .-22 ; 0x16c0 <__udivmodhi4_loop>
+ 16d6: 80 95 com r24
+ 16d8: 90 95 com r25
+ 16da: bc 01 movw r22, r24
+ 16dc: cd 01 movw r24, r26
+ 16de: 08 95 ret
+
+000016e0 <__divmodhi4>:
+ 16e0: 97 fb bst r25, 7
+ 16e2: 07 2e mov r0, r23
+ 16e4: 16 f4 brtc .+4 ; 0x16ea <__divmodhi4+0xa>
+ 16e6: 00 94 com r0
+ 16e8: 07 d0 rcall .+14 ; 0x16f8 <__divmodhi4_neg1>
+ 16ea: 77 fd sbrc r23, 7
+ 16ec: 09 d0 rcall .+18 ; 0x1700 <__divmodhi4_neg2>
+ 16ee: 0e 94 5c 0b call 0x16b8 ; 0x16b8 <__udivmodhi4>
+ 16f2: 07 fc sbrc r0, 7
+ 16f4: 05 d0 rcall .+10 ; 0x1700 <__divmodhi4_neg2>
+ 16f6: 3e f4 brtc .+14 ; 0x1706 <__divmodhi4_exit>
+
+000016f8 <__divmodhi4_neg1>:
+ 16f8: 90 95 com r25
+ 16fa: 81 95 neg r24
+ 16fc: 9f 4f sbci r25, 0xFF ; 255
+ 16fe: 08 95 ret
+
+00001700 <__divmodhi4_neg2>:
+ 1700: 70 95 com r23
+ 1702: 61 95 neg r22
+ 1704: 7f 4f sbci r23, 0xFF ; 255
+
+00001706 <__divmodhi4_exit>:
+ 1706: 08 95 ret
+
+00001708 <_exit>:
+ 1708: f8 94 cli
+
+0000170a <__stop_program>:
+ 170a: ff cf rjmp .-2 ; 0x170a <__stop_program>
diff --git a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.map b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.map
index 515187073bc1aaf84f912993a59234ed3375efda..de18e13f86991deed1abfac6c497fdbf96bc4b18 100644
--- a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.map
+++ b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.map
@@ -52,7 +52,7 @@ Common symbol size file
per 0x2 pwm.o
ADC_CS 0x4 main.o
-M_1_pid 0x34 main.o
+M_1_pid 0x32 main.o
M_INB 0x4 main.o
M_1 0x6 main.o
M_PWM 0x8 main.o
@@ -60,7 +60,7 @@ counter 0x2 ATKBBBIO/ATKEncoder.o
CC 0x32 main.o
tPV 0x4 ATKBBBIO/ATKEncoder.o
M_INA 0x4 main.o
-CS_filter 0x5 main.o
+CS_filter 0x3 main.o
Discarded input sections
@@ -89,8 +89,6 @@ Discarded input sections
.text 0x00000000 0x0 current_controller.o
.data 0x00000000 0x0 current_controller.o
.bss 0x00000000 0x0 current_controller.o
- .text.currentc_onTarget
- 0x00000000 0x3e current_controller.o
.text 0x00000000 0x0 kinematics.o
.data 0x00000000 0x0 kinematics.o
.bss 0x00000000 0x0 kinematics.o
@@ -384,7 +382,7 @@ END GROUP
.rela.plt
*(.rela.plt)
-.text 0x00000000 0x16dc
+.text 0x00000000 0x170c
*(.vectors)
.vectors 0x00000000 0x1fc C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAA_DFP/1.1.68/gcc/dev/atxmega256a3u/avrxmega6/crtatxmega256a3u.o
0x00000000 __vector_default
@@ -568,171 +566,174 @@ END GROUP
0x00000228 . = ALIGN (0x2)
*(.text.*)
.text.r_adc_init
- 0x00000228 0x2c r_adc.o
+ 0x00000228 0x2e r_adc.o
0x00000228 r_adc_init
.text.r_adc_scan
- 0x00000254 0xce r_adc.o
- 0x00000254 r_adc_scan
+ 0x00000256 0xc0 r_adc.o
+ 0x00000256 r_adc_scan
.text.clock_init
- 0x00000322 0x32 ATKBBBIO/ATKCLK.o
- 0x00000322 clock_init
- .text.set_dac 0x00000354 0x2e ATKBBBIO/ATKDAC.o
- 0x00000354 set_dac
+ 0x00000316 0x32 ATKBBBIO/ATKCLK.o
+ 0x00000316 clock_init
+ .text.set_dac 0x00000348 0x2e ATKBBBIO/ATKDAC.o
+ 0x00000348 set_dac
.text.dac_begin
- 0x00000382 0x6c ATKBBBIO/ATKDAC.o
- 0x00000382 dac_begin
+ 0x00000376 0x6c ATKBBBIO/ATKDAC.o
+ 0x00000376 dac_begin
.text.ATKEncoder_begin
- 0x000003ee 0x38 ATKBBBIO/ATKEncoder.o
- 0x000003ee ATKEncoder_begin
+ 0x000003e2 0x38 ATKBBBIO/ATKEncoder.o
+ 0x000003e2 ATKEncoder_begin
.text.ATK_EN_getValue
- 0x00000426 0x2a ATKBBBIO/ATKEncoder.o
- 0x00000426 ATK_EN_getValue
+ 0x0000041a 0x2a ATKBBBIO/ATKEncoder.o
+ 0x0000041a ATK_EN_getValue
.text.__vector_2
- 0x00000450 0x4a ATKBBBIO/ATKEncoder.o
- 0x00000450 __vector_2
+ 0x00000444 0x4a ATKBBBIO/ATKEncoder.o
+ 0x00000444 __vector_2
.text.__vector_3
- 0x0000049a 0x4a ATKBBBIO/ATKEncoder.o
- 0x0000049a __vector_3
+ 0x0000048e 0x4a ATKBBBIO/ATKEncoder.o
+ 0x0000048e __vector_3
.text.currentc_crunch
- 0x000004e4 0x1d2 current_controller.o
- 0x000004e4 currentc_crunch
+ 0x000004d8 0x1d2 current_controller.o
+ 0x000004d8 currentc_crunch
.text.currentc_setSetpoint
- 0x000006b6 0xc current_controller.o
- 0x000006b6 currentc_setSetpoint
+ 0x000006aa 0xc current_controller.o
+ 0x000006aa currentc_setSetpoint
.text.currentc_setAcceptableRange
- 0x000006c2 0xc current_controller.o
- 0x000006c2 currentc_setAcceptableRange
+ 0x000006b6 0xc current_controller.o
+ 0x000006b6 currentc_setAcceptableRange
+ .text.currentc_onTarget
+ 0x000006c2 0x3e current_controller.o
+ 0x000006c2 currentc_onTarget
.text.currentc_init
- 0x000006ce 0xf6 current_controller.o
- 0x000006ce currentc_init
+ 0x00000700 0xf6 current_controller.o
+ 0x00000700 currentc_init
.text.l_filter
- 0x000007c4 0x5e l_filter.o
- 0x000007c4 l_filter
+ 0x000007f6 0x78 l_filter.o
+ 0x000007f6 l_filter
.text.l_filter_init
- 0x00000822 0xe l_filter.o
- 0x00000822 l_filter_init
- .text.pwm_set 0x00000830 0x5c pwm.o
- 0x00000830 pwm_set
+ 0x0000086e 0xa l_filter.o
+ 0x0000086e l_filter_init
+ .text.pwm_set 0x00000878 0x5c pwm.o
+ 0x00000878 pwm_set
.text.pwm_set_dutycycle
- 0x0000088c 0x96 pwm.o
- 0x0000088c pwm_set_dutycycle
+ 0x000008d4 0x96 pwm.o
+ 0x000008d4 pwm_set_dutycycle
.text.pwm_init
- 0x00000922 0x56 pwm.o
- 0x00000922 pwm_init
+ 0x0000096a 0x56 pwm.o
+ 0x0000096a pwm_init
.text.motor_init
- 0x00000978 0x26 motor.o
- 0x00000978 motor_init
+ 0x000009c0 0x26 motor.o
+ 0x000009c0 motor_init
.text.motor_set
- 0x0000099e 0x68 motor.o
- 0x0000099e motor_set
+ 0x000009e6 0x68 motor.o
+ 0x000009e6 motor_set
.text.timing_interrupts_init
- 0x00000a06 0x16 main.o
- 0x00000a06 timing_interrupts_init
- .text.main 0x00000a1c 0x198 main.o
- 0x00000a1c main
+ 0x00000a4e 0x16 main.o
+ 0x00000a4e timing_interrupts_init
+ .text.main 0x00000a64 0x1b2 main.o
+ 0x00000a64 main
.text.__vector_20
- 0x00000bb4 0x1ca main.o
- 0x00000bb4 __vector_20
+ 0x00000c16 0x198 main.o
+ 0x00000c16 __vector_20
.text.pin_init
- 0x00000d7e 0x1e pin.o
- 0x00000d7e pin_init
- .text.pin_set 0x00000d9c 0x10 pin.o
- 0x00000d9c pin_set
+ 0x00000dae 0x1e pin.o
+ 0x00000dae pin_init
+ .text.pin_set 0x00000dcc 0x10 pin.o
+ 0x00000dcc pin_set
.text.pin_clear
- 0x00000dac 0x10 pin.o
- 0x00000dac pin_clear
+ 0x00000ddc 0x10 pin.o
+ 0x00000ddc pin_clear
.text.RPID_crunch
- 0x00000dbc 0x346 RPID.o
- 0x00000dbc RPID_crunch
+ 0x00000dec 0x346 RPID.o
+ 0x00000dec RPID_crunch
.text.RPID_setSetpoint
- 0x00001102 0xc RPID.o
- 0x00001102 RPID_setSetpoint
+ 0x00001132 0xc RPID.o
+ 0x00001132 RPID_setSetpoint
.text.RPID_onTarget
- 0x0000110e 0x3e RPID.o
- 0x0000110e RPID_onTarget
+ 0x0000113e 0x3e RPID.o
+ 0x0000113e RPID_onTarget
.text.RPID_init
- 0x0000114c 0xc0 RPID.o
- 0x0000114c RPID_init
+ 0x0000117c 0xc0 RPID.o
+ 0x0000117c RPID_init
.text.avr-libc.fplib
- 0x0000120c 0xe c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega6\libm.a(addsf3.o)
- 0x0000120c __subsf3
- 0x0000120e __addsf3
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- .debug_loc 0x00000b8e 0x25f main.o
- .debug_loc 0x00000ded 0x163 pin.o
- .debug_loc 0x00000f50 0x419 RPID.o
+ .debug_loc 0x000005e2 0xeb l_filter.o
+ .debug_loc 0x000006cd 0x371 pwm.o
+ .debug_loc 0x00000a3e 0x1ca motor.o
+ .debug_loc 0x00000c08 0x241 main.o
+ .debug_loc 0x00000e49 0x163 pin.o
+ .debug_loc 0x00000fac 0x416 RPID.o
.debug_macinfo
*(.debug_macinfo)
diff --git a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.srec b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.srec
index ce1cb4957f1a7edecb47c8b84f84f6f4d456ad47..e640895c59e037f5b0824a161bbbbd670a402f3b 100644
--- a/PIDMotorController/PIDMotorController/Debug/PIDMotorController.srec
+++ b/PIDMotorController/PIDMotorController/Debug/PIDMotorController.srec
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diff --git a/PIDMotorController/PIDMotorController/Debug/RPID.o b/PIDMotorController/PIDMotorController/Debug/RPID.o
index 77a5163281941354efadb4837e0f77f0981c1195..25d005179c5dbe3d3b8f785ab4d82a5a26f0b92d 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/RPID.o and b/PIDMotorController/PIDMotorController/Debug/RPID.o differ
diff --git a/PIDMotorController/PIDMotorController/Debug/current_controller.o b/PIDMotorController/PIDMotorController/Debug/current_controller.o
index 16f67e9218c01b75dff3d0f15d8ab67dc7bd398f..cc052fc7f289fdb288f1549fb508f7337bf39a7e 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/current_controller.o and b/PIDMotorController/PIDMotorController/Debug/current_controller.o differ
diff --git a/PIDMotorController/PIDMotorController/Debug/l_filter.o b/PIDMotorController/PIDMotorController/Debug/l_filter.o
index d1ac247ee8022188bc31f29f694fc1326131cbdf..4c0979e628f44ffc8768b9078ce15ef1aba68093 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/l_filter.o and b/PIDMotorController/PIDMotorController/Debug/l_filter.o differ
diff --git a/PIDMotorController/PIDMotorController/Debug/main.o b/PIDMotorController/PIDMotorController/Debug/main.o
index bb9991553e5085c8d9fcab692e0b3f73260225d6..37e7800727c815a76243476e45d391dd00e58cbe 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/main.o and b/PIDMotorController/PIDMotorController/Debug/main.o differ
diff --git a/PIDMotorController/PIDMotorController/Debug/motor.o b/PIDMotorController/PIDMotorController/Debug/motor.o
index d0d8a3d84da96fe20a0b1b84ae9436f72db34a35..51eae610878c6c488f955e267607af86c66b793a 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/motor.o and b/PIDMotorController/PIDMotorController/Debug/motor.o differ
diff --git a/PIDMotorController/PIDMotorController/Debug/pwm.o b/PIDMotorController/PIDMotorController/Debug/pwm.o
index ba7979d92d74bd3c0a35b40d360482b62d52e3d4..432faec90e0ebfe4ebeb9ac9afb070aaf505d149 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/pwm.o and b/PIDMotorController/PIDMotorController/Debug/pwm.o differ
diff --git a/PIDMotorController/PIDMotorController/Debug/r_adc.o b/PIDMotorController/PIDMotorController/Debug/r_adc.o
index 603bde618651e089d61ea3e50ec91777a2fd66d6..2322b15bb834af0304dc2f9e61743f92f91f4a33 100644
Binary files a/PIDMotorController/PIDMotorController/Debug/r_adc.o and b/PIDMotorController/PIDMotorController/Debug/r_adc.o differ
diff --git a/PIDMotorController/PIDMotorController/RBasic.h b/PIDMotorController/PIDMotorController/RBasic.h
index c6cb3fabaa589548575df4f40d6f69acb51481a9..391054608ed216fcf79cbc65df91d705308f9f8a 100644
--- a/PIDMotorController/PIDMotorController/RBasic.h
+++ b/PIDMotorController/PIDMotorController/RBasic.h
@@ -9,7 +9,7 @@
#ifndef RBasic_H_
#define RBasic_H_
-#define CONSTRAIN(a, min,max) (a<min? min: a>max? max: a)
+#define CONSTRAIN(a, min,max) (a<min? min: (a>max? max: a))
#define MAP(a,in_min, in_max, out_min, out_max) ((a-in_min)*(out_max-out_min/in_max-in_min) + out_min)
diff --git a/PIDMotorController/PIDMotorController/current_controller.c b/PIDMotorController/PIDMotorController/current_controller.c
index f166bcc438adb401c5c2f5a285da181112449959..2a144ec16f96610a0bf182fd2f4f0d20e0045e57 100644
--- a/PIDMotorController/PIDMotorController/current_controller.c
+++ b/PIDMotorController/PIDMotorController/current_controller.c
@@ -69,7 +69,7 @@
cc->currentError=0;
cc->totalError=0;
cc->setpoint=0;
- cc->acceptableRange=30;
+ cc->acceptableRange=20;
cc->onTargetTicks=0;
}
\ No newline at end of file
diff --git a/PIDMotorController/PIDMotorController/l_filter.c b/PIDMotorController/PIDMotorController/l_filter.c
index bb9889f3594e04a32ca1b5d3abb9042638cc6eba..36e25c40563e3543c502ebc123e180d747cc12e7 100644
--- a/PIDMotorController/PIDMotorController/l_filter.c
+++ b/PIDMotorController/PIDMotorController/l_filter.c
@@ -8,8 +8,9 @@
#include "l_filter.h"
#include <avr/io.h>
- uint16_t l_filter(l_filter_t *filter, int input){
- filter->filter_reg = (filter->filter_reg) - ((filter->filter_reg) >> filter->K) +(input>>filter->K); // y(n) = (1-2^-k)(y(n-1)) + (2^-k)(x(n))
+ int l_filter(l_filter_t *filter, int input){
+ //filter->filter_reg = (filter->filter_reg) - ((filter->filter_reg) >> filter->K) +(input>>filter->K); // y(n) = (1-2^-k)(y(n-1)) + (2^-k)(x(n))
+ filter->filter_reg = filter->filter_reg*0.985 + 0.015*input;
return filter->filter_reg;
};
diff --git a/PIDMotorController/PIDMotorController/l_filter.h b/PIDMotorController/PIDMotorController/l_filter.h
index b94a578f1481b898536c24dd9783d0583480f835..be74625a264ff5c32048eea864b68a25dd74a845 100644
--- a/PIDMotorController/PIDMotorController/l_filter.h
+++ b/PIDMotorController/PIDMotorController/l_filter.h
@@ -13,11 +13,11 @@
typedef struct{
uint8_t K;
- int32_t filter_reg;
+ int filter_reg;
}l_filter_t;
void l_filter_init(l_filter_t *filter, uint8_t K);
-uint16_t l_filter(l_filter_t *filter, int input);
+int l_filter(l_filter_t *filter, int input);
#endif // L_FILTER_H_
\ No newline at end of file
diff --git a/PIDMotorController/PIDMotorController/main.c b/PIDMotorController/PIDMotorController/main.c
index 8334004f522d55608257523ae7a3bb67ae465adc..c90aa39f720e8939a9693f36fab035fc6be64f90 100644
--- a/PIDMotorController/PIDMotorController/main.c
+++ b/PIDMotorController/PIDMotorController/main.c
@@ -43,7 +43,7 @@ int main(void)
sei();
PMIC.CTRL |= PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
- PORTE.DIRSET |= PIN3_bm;
+ PORTE.DIRSET |= PIN3_bm | PIN2_bm;
@@ -54,13 +54,16 @@ int main(void)
//initialize motor H bridge pins
PORTC.DIRSET |= PIN0_bm || PIN4_bm || PIN3_bm;
+ PORTC_DIRSET |= PIN5_bm;
+ PORTC_OUTSET |= PIN5_bm;
pin_init(&M_INA, &PORTC, PIN4_bm,1,1);
pin_init(&M_INB, &PORTC, PIN3_bm,0,1);
- pwm_init(&M_PWM, &TCC0,TC_CLKSEL_DIV1_gc,TC0_CCAEN_bm,48000,20);
+ pwm_init(&M_PWM, &TCC0,TC_CLKSEL_DIV1_gc,TC0_CCAEN_bm,48000,10);
motor_init(&M_1,&M_INA,&M_INB,&M_PWM);
//initialize current controller
+ PORTB_DIRCLR |= PIN0_bm;
r_adc_init(&ADC_CS, &ADCB, &ADCB.CH0, ADC_CH_MUXPOS_PIN0_gc);
currentc_init(&CC, 2.0,8.0,0.0005,0,5000,0,100);
currentc_setSetpoint(&CC, OTHERSETPOINT);
@@ -71,7 +74,7 @@ int main(void)
//initialize PID
- RPID_init(&M_1_pid,20,5.0, 0.0 ,0.00016,0, 0,0,-300,300, 6);
+ RPID_init(&M_1_pid,5.0,0.0, 0.0 ,0.00016,0, 0,0,-300,300, 6);
//initialize debugging DACs
PORTB.DIRSET |= PIN2_bm | PIN3_bm;
@@ -129,21 +132,22 @@ ISR(TCC1_OVF_vect){
//set_dac(ATK_DAC_CHANNEL_0, M_1_pid.setpoint);
- set_dac(ATK_DAC_CHANNEL_0, ATK_EN_getValue() +256);
+ //set_dac(ATK_DAC_CHANNEL_0, ATK_EN_getValue() +256);
//set_dac(ATK_DAC_CHANNEL_1, M_1_pid.setpoint + 256);
//set_dac(ATK_DAC_CHANNEL_1, CC.setpoint);
//16.8763 degrees to side 977 ticks per rev 2.7ticks per degree 36 is 0 degree 290 is 90deg
if(RPID_onTarget(&M_1_pid)){
- PORTE_DIRTGL = PIN3_bm;
+ //PORTE_DIRTGL = PIN3_bm;
if(M_1_pid.setpoint == OTHERSETPOINT){
- RPID_setSetpoint(&M_1_pid, 30);
- }else{
+ RPID_setSetpoint(&M_1_pid, 30);
+ }else{
RPID_setSetpoint(&M_1_pid, OTHERSETPOINT);
}
}
double V_val = RPID_crunch(&M_1_pid, ATK_EN_getValue());
+ V_val = 100;
currentc_setSetpoint(&CC, abs(V_val));
//if(currentc_onTarget(&CC) ){
@@ -155,15 +159,29 @@ ISR(TCC1_OVF_vect){
//}
//}
+ if(currentc_onTarget(&CC)){
+ PORTE_OUTCLR = PIN3_bm;
+ }else{
+ PORTE_OUTSET = PIN3_bm;
+ }
//value of 4096 is 3.3v
//uint16_t input = l_filter(&CS_filter, r_adc_scan(&ADC_CS));
- int input = l_filter(&CS_filter, r_adc_scan(&ADC_CS)*5.75);//3300mV/ 4096units * unitsmeasured / 0.140mV/mA == MilliAMPS being pulled
- //input =150;
+ int unfiltered = r_adc_scan(&ADC_CS)*5.75;
+ uint16_t input = l_filter(&CS_filter, unfiltered);//3300mV/ 4096units * unitsmeasured / 0.140mV/mA == MilliAMPS being pulled
+ //int input =100;
//set_dac(ATK_DAC_CHANNEL_0, input);
double C_val = currentc_crunch(&CC, input);//value of 4096 is 3.3v
- set_dac(ATK_DAC_CHANNEL_1, C_val*31 + 550);
- motor_set(&M_1, V_val >0? C_val:-C_val);
+ //set_dac(ATK_DAC_CHANNEL_1, C_val*31 + 620);//1% = 25mV
+ set_dac(ATK_DAC_CHANNEL_1, unfiltered*6 + 620);//100mA = 250mV
+ set_dac(ATK_DAC_CHANNEL_0, input*6 + 620);//1mA = 5mV
+ //set_dac(ATK_DAC_CHANNEL_0, CONSTRAIN(-20, 0,4096)*20 +620);
+ //set_dac(ATK_DAC_CHANNEL_1, 620);//100mA = 250mV
+
+ //motor_set(&M_1, C_val); //use for current control only mode
+ //motor_set(&M_1, V_val >0? C_val:-C_val);//use for position mode
+ motor_set(&M_1, 40);
+
//set_dac(ATK_DAC_CHANNEL_1, dac2);
//set_dac(ATK_DAC_CHANNEL_1, input/5.75 + 124);
diff --git a/PIDMotorController/PIDMotorController/motor.c b/PIDMotorController/PIDMotorController/motor.c
index 05b6145a7f371d811e3e3c7fe978997e2319b4c5..07bf4efdb9c63735c55f7ffc178027105acb0844 100644
--- a/PIDMotorController/PIDMotorController/motor.c
+++ b/PIDMotorController/PIDMotorController/motor.c
@@ -13,6 +13,7 @@ void motor_init(motor_t *motor, pin_t *INA_pin, pin_t *INB_pin, pwm_t *PWM) {
motor->INA_pin = INA_pin;
motor->INB_pin = INB_pin;
motor->PWM = PWM;
+
pin_set(motor->INA_pin);
pin_clear(motor->INB_pin);
diff --git a/PIDMotorController/PIDMotorController/r_adc.c b/PIDMotorController/PIDMotorController/r_adc.c
index 1c794c5cb90cbeafdd0974f56f15bf093a59d1e2..483789cb7a43506a37fd2d1c4c515535b63a419d 100644
--- a/PIDMotorController/PIDMotorController/r_adc.c
+++ b/PIDMotorController/PIDMotorController/r_adc.c
@@ -15,17 +15,18 @@
//setup ADC
adc->CTRLA= 1<<0;//enable ADC
- adc->CTRLB= ADC_RESOLUTION_12BIT_gc;
+ adc->CTRLB= ADC_RESOLUTION_12BIT_gc | ADC_FREERUN_bm;
adc->REFCTRL= ADC_REFSEL_INTVCC_gc;
- adc->PRESCALER= ADC_PRESCALER_DIV128_gc;
+ adc->PRESCALER= ADC_PRESCALER_DIV512_gc;
//setup ADCChannel
ch->CTRL=ADC_CH_INPUTMODE_DIFFWGAIN_gc | ADC_CH_GAIN_DIV2_gc;
ch->MUXCTRL = ADC_CH_MUXNEG_GND_MODE4_gc | posPin;
+ //ch->CTRL = ADC
}
uint16_t r_adc_scan(r_adc_t *r_adc){
- r_adc->ch->CTRL |= 1<<7; //start scan
- while(r_adc->ch->CTRL & (1<<7));//wait for scan to end
- return CONSTRAIN( ((r_adc->ch->RESH<<8) + r_adc->ch->RESL -2018)*1.35 , 0,4095);
+ //r_adc->ch->CTRL |= 1<<7; //start scan
+ //while(r_adc->ch->CTRL & (1<<7));//wait for scan to end
+ return CONSTRAIN( ((r_adc->ch->RESH<<8) + r_adc->ch->RESL -2018)*1.35 , 1,4095);
}
\ No newline at end of file