fix bridge

as5013-test/as5013-test.ko

@@ -87,39 +87,6 @@ class Header_FTDI(Component):
     vias = []
     shadow = s2d.rectangle(-.06,4/25.4,-.18,.28)
 
-class AS5510(Component):
-    #Austrian Microsystems AS5510 linear magnetic encoder
-    _pad_SOIC = s2d.rectangle(-0.041, 0.041, -0.015, 0.015)
-    pins = []
-    y = 0.075
-    for t in ['NC', 'VSS', 'ADR', 'VDD']:
-        pins.append(Pin(-0.14, y, _pad_SOIC, t))
-        y -= 0.05
-    for p in ['TEST', 'SDA', 'SCL', 'NC']:
-        y += 0.05
-        pins.append(Pin(0.14, y, _pad_SOIC, p))
-    del y
-    prefix = 'U'
-    w = 5/25.4#3.90/25.4; 
-    h = 4.9/25.4
-    vias = []
-class AS5510_Flipped(Component):
-    #Austrian Microsystems AS5510 linear magnetic encoder
-    _pad_SOIC = s2d.rectangle(-0.041, 0.041, -0.015, 0.015)
-    pins = []
-    y = 0.075
-    for t in ['NC', 'VSS', 'ADR', 'VDD']:
-        pins.append(Pin(0.14, y, _pad_SOIC, t))
-        y -= 0.05
-    for p in ['TEST', 'SDA', 'SCL', 'NC']:
-        y += 0.05
-        pins.append(Pin(-0.14, y, _pad_SOIC, p))
-    del y
-    prefix = 'U'
-    w = 5/25.4#3.90/25.4; 
-    h = 4.9/25.4
-    vias = [
-        Via(0,0,dogboned_rectangle_y(-.5*w,.5*w,-.5*h,.5*h,.016)) ]
 class Hole(Component):
     pins = [Pin(0,0,circle(0,0,0.01))]
     vias = [Via(0,0,circle(0,0,.5*2.1/25.4))]
@@ -164,9 +131,6 @@ def connectS(pin,dx,dy,width=.014):
 def connectM(pin1,pin2,dx,width=.014):
     pcb.connectD(pin1,[pin1.x+dx,pin1.y],pin2,width=width)
 
-#pcb.custom_cutout = chamfered_rectangle(0,width,.5*height-.25,.5*height+.25,.05)
-#pcb.custom_cutout += chamfered_rectangle(0,.6*width,0,height,.12)
-
 
 xmega = ATxmegaE5(.44,.68,90-45,'Xmega\n8E5')
 pcb += xmega
@@ -176,8 +140,6 @@ pcb += pdi
 
 
 pcb.connectD(xmega['RST/CLK'],[pdi['CLK'].x,pdi['CLK'].y+.05],pdi['CLK'],width=.014)
-#connectG(xmega['1 GND'],-.03,.05)
-#connectG(xmega['GND'],.07,.05)
 
 pcb.connectD(xmega['PDI/DATA'],[xmega['PDI/DATA'].x-.03,xmega['PDI/DATA'].y-.04],pdi['DAT'],width=.014)
 
@@ -243,8 +205,7 @@ pcb += RSCL
 RSDA = R_1206(RSCL.x+.09,hall['SDA'].y-.035,90,'RSDA',label_size=.03)
 pcb += RSDA
 
-pcb.connectD(Chall[0],[hall['VDD'].x+.05,Chall[0].y-.3],C1[0])
-
+pcb.connectD(Chall[0],[hall['VDD'].x+.05,Chall[0].y-.3],C1[1])
 
 pcb.connectH(C1[1],RSCL[1])
 pcb.connectH(C1[1],RSDA[1])