Commit 02203583 authored by Dean Camera's avatar Dean Camera
Browse files

Remove missed timer 0 init code in the ISP protocol handler in the AVRISP...

Remove missed timer 0 init code in the ISP protocol handler in the AVRISP project. Switch the XPROG protocol target communications handler over to using Timer 1 COMA/COMB ISRs for the two physical layers, rather than COMA/ICR1. Speed up bit-banged USART mode slightly.
parent 8cd7e118
...@@ -122,9 +122,6 @@ uint8_t ISPTarget_WaitForProgComplete(const uint8_t ProgrammingMode, const uint1 ...@@ -122,9 +122,6 @@ uint8_t ISPTarget_WaitForProgComplete(const uint8_t ProgrammingMode, const uint1
break; break;
case PROG_MODE_WORD_VALUE_MASK: case PROG_MODE_WORD_VALUE_MASK:
case PROG_MODE_PAGED_VALUE_MASK: case PROG_MODE_PAGED_VALUE_MASK:
TCNT0 = 0;
TIFR0 = (1 << OCF1A);
do do
{ {
SPI_SendByte(ReadMemCommand); SPI_SendByte(ReadMemCommand);
......
...@@ -57,13 +57,13 @@ ...@@ -57,13 +57,13 @@
/* Macros: */ /* Macros: */
/** Programmer ID string, returned to the host during the CMD_SIGN_ON command processing */ /** Programmer ID string, returned to the host during the CMD_SIGN_ON command processing */
#define PROGRAMMER_ID "AVRISP_MK2" #define PROGRAMMER_ID "AVRISP_MK2"
/** Timeout period for each issued command from the host before it is aborted */ /** Timeout period for each issued command from the host before it is aborted */
#define COMMAND_TIMEOUT_MS 200 #define COMMAND_TIMEOUT_MS 200
/** Command timeout counter register, GPIOR for speed */ /** Command timeout counter register, GPIOR for speed */
#define TimeoutMSRemaining GPIOR1 #define TimeoutMSRemaining GPIOR0
/* External Variables: */ /* External Variables: */
extern uint32_t CurrentAddress; extern uint32_t CurrentAddress;
......
...@@ -49,31 +49,31 @@ volatile uint16_t SoftUSART_Data; ...@@ -49,31 +49,31 @@ volatile uint16_t SoftUSART_Data;
#define SoftUSART_BitCount GPIOR2 #define SoftUSART_BitCount GPIOR2
/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */ /** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */
ISR(TIMER1_CAPT_vect, ISR_BLOCK) ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{ {
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */ /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK; BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK;
/* If not sending or receiving, just exit */ /* If not sending or receiving, just exit */
if (!(SoftUSART_BitCount)) if (!(SoftUSART_BitCount))
return; return;
/* Check to see if we are at a rising or falling edge of the clock */ /* Check to see if we are at a rising or falling edge of the clock */
if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK) if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK)
{ {
/* If at rising clock edge and we are in send mode, abort */ /* If at rising clock edge and we are in send mode, abort */
if (IsSending) if (IsSending)
return; return;
/* Wait for the start bit when receiving */ /* Wait for the start bit when receiving */
if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)) if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
return; return;
/* Shift in the bit one less than the frame size in position, so that the start bit will eventually /* Shift in the bit one less than the frame size in position, so that the start bit will eventually
* be discarded leaving the data to be byte-aligned for quick access */ * be discarded leaving the data to be byte-aligned for quick access */
if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK) if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1)); ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
SoftUSART_Data >>= 1; SoftUSART_Data >>= 1;
SoftUSART_BitCount--; SoftUSART_BitCount--;
...@@ -85,41 +85,41 @@ ISR(TIMER1_CAPT_vect, ISR_BLOCK) ...@@ -85,41 +85,41 @@ ISR(TIMER1_CAPT_vect, ISR_BLOCK)
return; return;
/* Set the data line to the next bit value */ /* Set the data line to the next bit value */
if (SoftUSART_Data & 0x01) if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK; BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
else else
BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK; BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
SoftUSART_Data >>= 1; SoftUSART_Data >>= 1;
SoftUSART_BitCount--; SoftUSART_BitCount--;
} }
} }
/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */ /** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */
ISR(TIMER1_COMPA_vect, ISR_BLOCK) ISR(TIMER1_COMPB_vect, ISR_BLOCK)
{ {
/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */ /* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
BITBANG_PDICLOCK_PIN |= BITBANG_PDICLOCK_MASK; BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;
/* If not sending or receiving, just exit */ /* If not sending or receiving, just exit */
if (!(SoftUSART_BitCount)) if (!(SoftUSART_BitCount))
return; return;
/* Check to see if we are at a rising or falling edge of the clock */ /* Check to see if we are at a rising or falling edge of the clock */
if (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK) if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
{ {
/* If at rising clock edge and we are in send mode, abort */ /* If at rising clock edge and we are in send mode, abort */
if (IsSending) if (IsSending)
return; return;
/* Wait for the start bit when receiving */ /* Wait for the start bit when receiving */
if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)) if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
return; return;
/* Shift in the bit one less than the frame size in position, so that the start bit will eventually /* Shift in the bit one less than the frame size in position, so that the start bit will eventually
* be discarded leaving the data to be byte-aligned for quick access */ * be discarded leaving the data to be byte-aligned for quick access */
if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK) if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1)); ((uint8_t*)&SoftUSART_Data)[1] |= (1 << (BITS_IN_USART_FRAME - 9));
SoftUSART_Data >>= 1; SoftUSART_Data >>= 1;
SoftUSART_BitCount--; SoftUSART_BitCount--;
...@@ -131,10 +131,10 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK) ...@@ -131,10 +131,10 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
return; return;
/* Set the data line to the next bit value */ /* Set the data line to the next bit value */
if (SoftUSART_Data & 0x01) if (((uint8_t*)&SoftUSART_Data)[0] & 0x01)
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK; BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
else else
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
SoftUSART_Data >>= 1; SoftUSART_Data >>= 1;
SoftUSART_BitCount--; SoftUSART_BitCount--;
...@@ -142,41 +142,42 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK) ...@@ -142,41 +142,42 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
} }
#endif #endif
/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */ /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
void XPROGTarget_EnableTargetTPI(void) void XPROGTarget_EnableTargetPDI(void)
{ {
/* Set /RESET line low for at least 90ns to enable TPI functionality */
RESET_LINE_DDR |= RESET_LINE_MASK;
RESET_LINE_PORT &= ~RESET_LINE_MASK;
asm volatile ("NOP"::);
asm volatile ("NOP"::);
#if defined(XPROG_VIA_HARDWARE_USART) #if defined(XPROG_VIA_HARDWARE_USART)
/* Set Tx and XCK as outputs, Rx as input */ /* Set Tx and XCK as outputs, Rx as input */
DDRD |= (1 << 5) | (1 << 3); DDRD |= (1 << 5) | (1 << 3);
DDRD &= ~(1 << 2); DDRD &= ~(1 << 2);
/* Set DATA line high for at least 90ns to disable /RESET functionality */
PORTD |= (1 << 3);
asm volatile ("NOP"::);
asm volatile ("NOP"::);
/* Set up the synchronous USART for XMEGA communications - /* Set up the synchronous USART for XMEGA communications -
8 data bits, even parity, 2 stop bits */ 8 data bits, even parity, 2 stop bits */
UBRR1 = (F_CPU / 1000000UL); UBRR1 = (F_CPU / 1000000UL);
UCSR1B = (1 << TXEN1); UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1); UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */ /* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
XPROGTarget_SendBreak(); XPROGTarget_SendBreak();
XPROGTarget_SendBreak(); XPROGTarget_SendBreak();
#else #else
/* Set DATA and CLOCK lines to outputs */ /* Set DATA and CLOCK lines to outputs */
BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK; BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK; BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
/* Set DATA line high for idle state */ /* Set DATA line high for at least 90ns to disable /RESET functionality */
BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK; BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
asm volatile ("NOP"::);
asm volatile ("NOP"::);
/* Fire timer capture ISR every 100 cycles to manage the software USART */ /* Fire timer compare channel A ISR every 90 cycles to manage the software USART */
OCR1A = 100; OCR1A = 90;
TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10); TCCR1B = (1 << WGM12) | (1 << CS10);
TIMSK1 = (1 << ICIE1); TIMSK1 = (1 << OCIE1A);
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */ /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
XPROGTarget_SendBreak(); XPROGTarget_SendBreak();
...@@ -184,42 +185,41 @@ void XPROGTarget_EnableTargetTPI(void) ...@@ -184,42 +185,41 @@ void XPROGTarget_EnableTargetTPI(void)
#endif #endif
} }
/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */ /** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
void XPROGTarget_EnableTargetPDI(void) void XPROGTarget_EnableTargetTPI(void)
{ {
/* Set /RESET line low for at least 90ns to enable TPI functionality */
RESET_LINE_DDR |= RESET_LINE_MASK;
RESET_LINE_PORT &= ~RESET_LINE_MASK;
asm volatile ("NOP"::);
asm volatile ("NOP"::);
#if defined(XPROG_VIA_HARDWARE_USART) #if defined(XPROG_VIA_HARDWARE_USART)
/* Set Tx and XCK as outputs, Rx as input */ /* Set Tx and XCK as outputs, Rx as input */
DDRD |= (1 << 5) | (1 << 3); DDRD |= (1 << 5) | (1 << 3);
DDRD &= ~(1 << 2); DDRD &= ~(1 << 2);
/* Set DATA line high for at least 90ns to disable /RESET functionality */
PORTD |= (1 << 3);
asm volatile ("NOP"::);
asm volatile ("NOP"::);
/* Set up the synchronous USART for XMEGA communications - /* Set up the synchronous USART for XMEGA communications -
8 data bits, even parity, 2 stop bits */ 8 data bits, even parity, 2 stop bits */
UBRR1 = (F_CPU / 1000000UL); UBRR1 = (F_CPU / 1000000UL);
UCSR1B = (1 << TXEN1); UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1); UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */ /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
XPROGTarget_SendBreak(); XPROGTarget_SendBreak();
XPROGTarget_SendBreak(); XPROGTarget_SendBreak();
#else #else
/* Set DATA and CLOCK lines to outputs */ /* Set DATA and CLOCK lines to outputs */
BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK; BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK; BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
/* Set DATA line high for at least 90ns to disable /RESET functionality */ /* Set DATA line high for idle state */
BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK; BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
asm volatile ("NOP"::);
asm volatile ("NOP"::);
/* Fire timer compare ISR every 100 cycles to manage the software USART */ /* Fire timer capture channel B ISR every 90 cycles to manage the software USART */
OCR1A = 100; OCR1B = 9;
TCCR1B = (1 << WGM12) | (1 << CS10); TCCR1B = (1 << WGM12) | (1 << CS10);
TIMSK1 = (1 << OCIE1A); TIMSK1 = (1 << OCIE1B);
/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */ /* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
XPROGTarget_SendBreak(); XPROGTarget_SendBreak();
...@@ -227,8 +227,8 @@ void XPROGTarget_EnableTargetPDI(void) ...@@ -227,8 +227,8 @@ void XPROGTarget_EnableTargetPDI(void)
#endif #endif
} }
/** Disables the target's TPI interface, exits programming mode and starts the target's application. */ /** Disables the target's PDI interface, exits programming mode and starts the target's application. */
void XPROGTarget_DisableTargetTPI(void) void XPROGTarget_DisableTargetPDI(void)
{ {
#if defined(XPROG_VIA_HARDWARE_USART) #if defined(XPROG_VIA_HARDWARE_USART)
/* Turn off receiver and transmitter of the USART, clear settings */ /* Turn off receiver and transmitter of the USART, clear settings */
...@@ -241,21 +241,17 @@ void XPROGTarget_DisableTargetTPI(void) ...@@ -241,21 +241,17 @@ void XPROGTarget_DisableTargetTPI(void)
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2)); PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
#else #else
/* Set DATA and CLOCK lines to inputs */ /* Set DATA and CLOCK lines to inputs */
BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK; BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK; BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
/* Tristate DATA and CLOCK lines */ /* Tristate DATA and CLOCK lines */
BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK; BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK; BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
#endif #endif
/* Tristate target /RESET line */
RESET_LINE_DDR &= ~RESET_LINE_MASK;
RESET_LINE_PORT &= ~RESET_LINE_MASK;
} }
/** Disables the target's PDI interface, exits programming mode and starts the target's application. */ /** Disables the target's TPI interface, exits programming mode and starts the target's application. */
void XPROGTarget_DisableTargetPDI(void) void XPROGTarget_DisableTargetTPI(void)
{ {
#if defined(XPROG_VIA_HARDWARE_USART) #if defined(XPROG_VIA_HARDWARE_USART)
/* Turn off receiver and transmitter of the USART, clear settings */ /* Turn off receiver and transmitter of the USART, clear settings */
...@@ -268,13 +264,17 @@ void XPROGTarget_DisableTargetPDI(void) ...@@ -268,13 +264,17 @@ void XPROGTarget_DisableTargetPDI(void)
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2)); PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
#else #else
/* Set DATA and CLOCK lines to inputs */ /* Set DATA and CLOCK lines to inputs */
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK; BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;
BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK; BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;
/* Tristate DATA and CLOCK lines */ /* Tristate DATA and CLOCK lines */
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK; BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK; BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;
#endif #endif
/* Tristate target /RESET line */
RESET_LINE_DDR &= ~RESET_LINE_MASK;
RESET_LINE_PORT &= ~RESET_LINE_MASK;
} }
/** Sends a byte via the USART. /** Sends a byte via the USART.
......
...@@ -56,7 +56,29 @@ ...@@ -56,7 +56,29 @@
/* Defines: */ /* Defines: */
#if ((BOARD == BOARD_XPLAIN) || (BOARD == BOARD_XPLAIN_REV1)) #if ((BOARD == BOARD_XPLAIN) || (BOARD == BOARD_XPLAIN_REV1))
#define XPROG_VIA_HARDWARE_USART // #define XPROG_VIA_HARDWARE_USART
#define BITBANG_PDIDATA_PORT PORTD
#define BITBANG_PDIDATA_DDR DDRD
#define BITBANG_PDIDATA_PIN PIND
#define BITBANG_PDIDATA_MASK (1 << 3)
#define BITBANG_PDICLOCK_PORT PORTD
#define BITBANG_PDICLOCK_DDR DDRD
#define BITBANG_PDICLOCK_PIN PIND
#define BITBANG_PDICLOCK_MASK (1 << 5)
#define BITBANG_TPIDATA_PORT PORTB
#define BITBANG_TPIDATA_DDR DDRB
#define BITBANG_TPIDATA_PIN PINB
#define BITBANG_TPIDATA_MASK (1 << 3)
#define BITBANG_TPICLOCK_PORT PORTB
#define BITBANG_TPICLOCK_DDR DDRB
#define BITBANG_TPICLOCK_PIN PINB
#define BITBANG_TPICLOCK_MASK (1 << 1)
#else #else
#define BITBANG_PDIDATA_PORT PORTB #define BITBANG_PDIDATA_PORT PORTB
#define BITBANG_PDIDATA_DDR DDRB #define BITBANG_PDIDATA_DDR DDRB
...@@ -130,10 +152,10 @@ ...@@ -130,10 +152,10 @@
#define TPI_POINTER_INDIRECT_PI (1 << 2) #define TPI_POINTER_INDIRECT_PI (1 << 2)
/* Function Prototypes: */ /* Function Prototypes: */
void XPROGTarget_EnableTargetTPI(void);
void XPROGTarget_EnableTargetPDI(void); void XPROGTarget_EnableTargetPDI(void);
void XPROGTarget_DisableTargetTPI(void); void XPROGTarget_EnableTargetTPI(void);
void XPROGTarget_DisableTargetPDI(void); void XPROGTarget_DisableTargetPDI(void);
void XPROGTarget_DisableTargetTPI(void);
void XPROGTarget_SendByte(const uint8_t Byte); void XPROGTarget_SendByte(const uint8_t Byte);
uint8_t XPROGTarget_ReceiveByte(void); uint8_t XPROGTarget_ReceiveByte(void);
void XPROGTarget_SendBreak(void); void XPROGTarget_SendBreak(void);
......
...@@ -60,7 +60,7 @@ ...@@ -60,7 +60,7 @@
# MCU name # MCU name
MCU = at90usb162 MCU = at90usb1287
# Target board (see library "Board Types" documentation, USER or blank for projects not requiring # Target board (see library "Board Types" documentation, USER or blank for projects not requiring
......
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