add code from mkstepper for atsamd51 utils

README.md

@@ -17,9 +17,9 @@ Eulagies aside, I am still motivated to do this. Brushless motors are the go-to
 
 I'm not intending to put myself in league with these people - these links are here because they are motivated by (similar) things.
 
-[ODrive](https://odriverobotics.com/shop)
-[VESC](http://vedder.se/2015/01/vesc-open-source-esc/)
-[Ben Katz](http://build-its-inprogress.blogspot.com/search/label/Motor%20Control)
+[ODrive](https://odriverobotics.com/shop)  
+[VESC](http://vedder.se/2015/01/vesc-open-source-esc/)  
+[Ben Katz](http://build-its-inprogress.blogspot.com/search/label/Motor%20Control)  
 
 #### A few things to understand: 
 

circuit/mkbldcdriver/eagle.epf

@@ -8,7 +8,6 @@ Desktop="Desktop"
 AutoSaveProject=1
 UsedLibraryUrn="urn:adsk.eagle:library:217"
 UsedLibraryUrn="urn:adsk.eagle:library:325"
-UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/atsam.lbr"
 UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/fab.lbr"
 UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/motors.lbr"
 UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/power.lbr"
@@ -41,7 +40,7 @@ Loc="0 0 1919 1016"
 State=1
 Number=2
 File="mkbldcdriver.sch"
-View="-35.6514 3.39373 207.983 95.5307"
+View="-127.358 -108.213 75.6708 -31.4319"
 WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524"
 PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
@@ -80,7 +79,7 @@ ArcDirection=0
 AddLevel=2
 PadsSameType=0
 Layer=91
-Views=" 1: -35.6514 3.39373 207.983 95.5307"
+Views=" 1: -127.358 -108.213 75.6708 -31.4319"
 Sheet="1"
 
 [Win_2]
@@ -89,7 +88,7 @@ Loc="0 0 1919 1016"
 State=1
 Number=1
 File="mkbldcdriver.brd"
-View="40.6143 32.1465 78.9523 33.3374"
+View="10.5389 56.9239 37.1626 57.7509"
 WireWidths=" 0.0762 0.1016 0.127 0.15 0.508 0.6096 0.8128 2.54 1.016 1.27 0.3048 0.254 0.2 0.4064 0.2032 0.1524"
 PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 PadDrills=" 0.2 0.25 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6 0.3"
@@ -136,7 +135,7 @@ State=1
 Number=0
 
 [Desktop]
-Screen="1920 1080"
+Screen="3840 1080"
 Window="Win_1"
 Window="Win_2"
 Window="Win_3"

embedded/mkbldcdriver-v03/mkbldcdriver-v03/Debug/Makefile

@@ -40,7 +40,12 @@ SUBDIRS :=  \
 C_SRCS +=  \
 ../Device_Startup/startup_samd51.c \
 ../Device_Startup/system_samd51.c \
-../main.c
+../main.c \
+../pin.c \
+../pwm_foc.c \
+../ringbuffer.c \
+../spiport.c \
+../uartport.c
 
 
 PREPROCESSING_SRCS += 
@@ -52,22 +57,42 @@ ASM_SRCS +=
 OBJS +=  \
 Device_Startup/startup_samd51.o \
 Device_Startup/system_samd51.o \
-main.o
+main.o \
+pin.o \
+pwm_foc.o \
+ringbuffer.o \
+spiport.o \
+uartport.o
 
 OBJS_AS_ARGS +=  \
 Device_Startup/startup_samd51.o \
 Device_Startup/system_samd51.o \
-main.o
+main.o \
+pin.o \
+pwm_foc.o \
+ringbuffer.o \
+spiport.o \
+uartport.o
 
 C_DEPS +=  \
 Device_Startup/startup_samd51.d \
 Device_Startup/system_samd51.d \
-main.d
+main.d \
+pin.d \
+pwm_foc.d \
+ringbuffer.d \
+spiport.d \
+uartport.d
 
 C_DEPS_AS_ARGS +=  \
 Device_Startup/startup_samd51.d \
 Device_Startup/system_samd51.d \
-main.d
+main.d \
+pin.d \
+pwm_foc.d \
+ringbuffer.d \
+spiport.d \
+uartport.d
 
 OUTPUT_FILE_PATH +=mkbldcdriver-v03.elf
 
@@ -92,6 +117,16 @@ LINKER_SCRIPT_DEP+=  \
 
 
 
+
+
+
+
+
+
+
+
+
+
 Device_Startup/%.o: ../Device_Startup/%.c
 	@echo Building file: $<
 	@echo Invoking: ARM/GNU C Compiler : 6.3.1

embedded/mkbldcdriver-v03/mkbldcdriver-v03/Debug/makedep.mk

@@ -8,3 +8,13 @@ Device_Startup\system_samd51.c
 
 main.c
 
+pin.c
+
+pwm_foc.c
+
+ringbuffer.c
+
+spiport.c
+
+uartport.c
+

embedded/mkbldcdriver-v03/mkbldcdriver-v03/hardware.h

+/*
+ * hardware.h
+ *
+ * Created: 2/17/2018 10:28:57 PM
+ *  Author: Jake
+ */ 
+
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+
+#include "pin.h"
+#include "ringbuffer.h"
+#include "uartport.h"
+#include "spiport.h"
+
+pin_t stlb;
+
+ringbuffer_t up1_rbrx;
+ringbuffer_t up1_rbtx;
+ringbuffer_t up2_rbrx;
+ringbuffer_t up2_rbtx;
+
+uartport_t up1;
+uartport_t up2;
+
+#endif /* HARDWARE_H_ */
\ No newline at end of file

embedded/mkbldcdriver-v03/mkbldcdriver-v03/main.c

@@ -7,160 +7,81 @@
 
 
 #include "sam.h"
+#include "pwm_foc.h"
+#include "pin.h"
+#include "hardware.h"
 #include <stdio.h>
 
 // stlb is PA23
 
-void pwmsetup(void){
-	/* TCC SETUP */
-	// from 49.6.2.1
-	// a few registers are protected - and can only be updated when
-	// TCCn.CTRLA.ENABLE = 0
-	// FCTRLA and FCTRLB, WEXCTRL, DRVCTRL, and EVCTRL
-	
-	// (4) Configure Output Pin with PORT->Group[n].DIRSET.reg
-	// PA8 PA9 PA10 PA12, PB10 PB11
-	// 32.9.13
-	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 8) | (uint32_t)(1 << 9) | (uint32_t)(1 << 10) | (uint32_t)(1 << 12);
-	PORT->Group[1].DIRSET.reg |= (uint32_t)(1 << 10) | (uint32_t)(1 << 11);
-	
-	// 1 lo / hi
-	PORT->Group[0].PINCFG[10].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[10>>1].reg |= PORT_PMUX_PMUXE(0x5);  // on peripheral F
-	PORT->Group[0].PINCFG[12].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[12>>1].reg |= PORT_PMUX_PMUXE(0x5); 
-	
-	// 2 lo / hi
-	PORT->Group[0].PINCFG[9].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[9>>1].reg |= PORT_PMUX_PMUXO(0x5);  // on peripheral F
-	PORT->Group[1].PINCFG[11].bit.PMUXEN = 1;
-	PORT->Group[1].PMUX[11>>1].reg |= PORT_PMUX_PMUXO(0x5);
-	
-	// 3 lo / hi
-	PORT->Group[0].PINCFG[8].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[8>>1].reg |= PORT_PMUX_PMUXE(0x5);  // on peripheral F
-	PORT->Group[1].PINCFG[10].bit.PMUXEN = 1;
-	PORT->Group[1].PMUX[10>>1].reg |= PORT_PMUX_PMUXE(0x5);
-	
-	// (1) enable the TCC Bus Clock - CLK_TCCn_APB
-	// https://www.eevblog.com/forum/microcontrollers/atmel-sam-d-tc-and-tcc-(no-asf)/
-	
-	TCC0->CTRLA.bit.ENABLE = 0;
-	
-	MCLK->APBBMASK.reg |= MCLK_APBBMASK_TCC0; // at 15.8.9
-	
-	GCLK->GENCTRL[5].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) | GCLK_GENCTRL_GENEN;
-	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5);
-	
-	GCLK->PCHCTRL[TCC0_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK5;
-	
-	TCC0->CTRLA.reg |= TCC_CTRLA_PRESCALER_DIV8 | TCC_CTRLA_PRESCSYNC_PRESC |TCC_CTRLA_RESOLUTION(0);
-	
-	// (2) Select Waveform Generation operation in the WAVE register WAVE.WAVEGEN
-	// we want dual slope pwm
-		
-	TCC0->WAVE.reg = TCC_WAVE_WAVEGEN_DSBOTH; // 'dual slope both' - updates on both hi and lo of slope ?
-		
-	// (3) We want OTMX - Output Matrix Channel Pin Routing Configuration - at 0x0
-	
-	TCC0->WEXCTRL.reg = TCC_WEXCTRL_DTHS(1) | TCC_WEXCTRL_DTLS(1) | 
-						TCC_WEXCTRL_DTIEN1 | TCC_WEXCTRL_DTIEN2 | TCC_WEXCTRL_DTIEN3 | TCC_WEXCTRL_DTIEN0 |
-						TCC_WEXCTRL_OTMX(0);
-						
-	TCC0->PER.reg = TCC_PER_PER(256); // 18 bit
-	
-	TCC0->COUNT.reg = 0;
-	
-	TCC0->CC[0].reg = 0; // '3'
-	TCC0->CC[1].reg = 0; // '2'
-	TCC0->CC[2].reg = 0; // '1'
-	TCC0->CC[3].reg = 0;
-	
-	// (4) Enable with CTRLA.ENABLE
-	
-	TCC0->CTRLA.bit.ENABLE = 1;
-	while(TCC0->SYNCBUSY.bit.ENABLE);
-}
-
-void pwmupdate(uint32_t one, uint32_t two, uint32_t three){
-	TCC0->CC[0].reg = three; // '3'
-	TCC0->CC[1].reg = two; // '2'
-	TCC0->CC[2].reg = one; // '1'
-}
-
 int main(void)
 {
     /* Initialize the SAM system */
     SystemInit();
-	
-	PORT->Group[1].DIRSET.reg |= (uint32_t)(1 << 9);
-	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 23);
-	
 	SysTick_Config(5000000);
 	
-	/* BEGIN SPI SETUP */
-	
-	// PA04, SER0-0, SPI_MISO
-	// PA05, SER0-1, SPI_SCK
-	// PA06, SER0-2, SPI_CSN
-	// PA07, SER0-3, SPI_MOSI
-	PORT->Group[0].DIRCLR.reg |= (uint32_t)(1 << 4); 
-	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 5) | (uint32_t)(1 << 6) | (uint32_t)(1 << 7);
-	
-	PORT->Group[0].PINCFG[4].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[4>>1].reg |= PORT_PMUX_PMUXE(0x3);  // on peripheral D
-	PORT->Group[0].PINCFG[5].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[5>>1].reg |= PORT_PMUX_PMUXO(0x3);  // on peripheral D
-	PORT->Group[0].PINCFG[6].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[6>>1].reg |= PORT_PMUX_PMUXE(0x3);  // on peripheral D
-	PORT->Group[0].PINCFG[7].bit.PMUXEN = 1;
-	PORT->Group[0].PMUX[7>>1].reg |= PORT_PMUX_PMUXO(0x3);  // on peripheral D
-	
-	// setup clocks to sercom
-	
-	MCLK->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; // at 15.8.9
-	
-	GCLK->GENCTRL[6].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) | GCLK_GENCTRL_GENEN;
-	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6);
-	
-	GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK6;
-	
-	// TCC0_GCLK_ID
-	
-	// Some registers can't be written unless CTRL.ENABLE = 0:
-	// CTRLA, CTRLB, BAD and ADDR
-	
-	// (1) set to master
-	
-	SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3); // 0x2 or 0x3, slave or master
-	
-	// SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL; // clock phase and polarity
-	
-	// (2) set pin configurations
-	
-	SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(0x0) | SERCOM_SPI_CTRLA_DOPO(0x2); // pin selections, see 35.8.1 bits 21:20 and 17:16, pg. 910
-	
-	// (3) set character size, data direction
-	
-	//SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; // 0 MSB, 1 LSB
-	//SERCOM0->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(0x0); // 8 bits character - 0x0, so no need to set
+	// LED
+	stlb = pin_new(&PORT->Group[0], 23);
+	pin_output(&stlb);
+	
+	// interrupts
+	__enable_irq();
+	NVIC_EnableIRQ(SERCOM4_0_IRQn); //up1tx
+	NVIC_EnableIRQ(SERCOM4_2_IRQn); //up1rx
+	NVIC_EnableIRQ(SERCOM5_0_IRQn);
+	NVIC_EnableIRQ(SERCOM5_2_IRQn);
+	
+	// Rinbuffers for UARTs
+	rb_init(&up1_rbrx);
+	rb_init(&up1_rbtx);
+	rb_init(&up1_rbrx);
+	rb_init(&up1_rbtx);
+	
+	// UARTS 
+	// UP1:
+	// SERCOM4 | RX: PB13 | TX: PB12
+	// UP2:
+	// SERCOM5 | RX: PB3 | TX: PB2
+	up1 = uart_new(SERCOM4, &PORT->Group[1], &up1_rbrx, &up1_rbtx, 12, 13, HARDWARE_IS_APBD, HARDWARE_ON_PERIPHERAL_C); 
+	MCLK->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
+	uart_init(&up1, 6, SERCOM4_GCLK_ID_CORE, 63018); // baud: 45402 for 921600, 63018 for 115200
+	up2 = uart_new(SERCOM5, &PORT->Group[1], &up2_rbrx, &up2_rbtx, 3, 2, HARDWARE_IS_APBD, HARDWARE_ON_PERIPHERAL_D);
+	MCLK->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
+	uart_init(&up2, 7, SERCOM5_GCLK_ID_CORE, 63018);
+		
+	// check all PWM lines
+	// pins for enable, fault, pwmmode, etc
 	
-	// (4) setup baud rate
-	// f_baud = f_ref / (2 * (BAUD +1)) so BAUD = f_ref / (2 * f_baud) - 1
+	// integrate SPI, test AS5147, library
 	
-	SERCOM0->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(126);
-	SERCOM0->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_RXEN; // slave select hardware yes
+	// do closed loop sinucommutate, following old ATSAMS70 code
+	// do BLDC closed, open loop
 	
-	SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	pwmsetup_foc();
 	
     while (1) 
     {
-		while(!(SERCOM0->SPI.INTFLAG.bit.DRE));
-		SERCOM0->SPI.DATA.reg = SERCOM_SPI_DATA_DATA(80);
-		PORT->Group[1].OUTTGL.reg = (uint32_t)(1 << 9); // i-v, to check we made it thru setup
+		pwmupdate_foc(126,126,126);
     }
 }
 
 void SysTick_Handler(void){
-	PORT->Group[0].OUTTGL.reg = (uint32_t)(1 << 23);
-}
\ No newline at end of file
+	pin_toggle(&stlb);
+	uart_sendchar_buffered(&up1, 125);
+}
+
+void SERCOM4_0_Handler(void){
+	uart_txhandler(&up1);
+}
+
+void SERCOM4_2_Handler(void){
+	uart_rxhandler(&up1);
+}
+
+void SERCOM5_0_Handler(void){
+	uart_txhandler(&up2);
+}
+
+void SERCOM5_2_Handler(void){
+	uart_rxhandler(&up2);
+}

embedded/mkbldcdriver-v03/mkbldcdriver-v03/mkbldcdriver-v03.cproj

@@ -30,15 +30,15 @@
     <EraseKey />
     <AsfFrameworkConfig>
       <framework-data xmlns="">
-  <options />
-  <configurations />
-  <files />
-  <documentation help="" />
-  <offline-documentation help="" />
-  <dependencies>
-    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.36.2" />
-  </dependencies>
-</framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.36.2" />
+        </dependencies>
+      </framework-data>
     </AsfFrameworkConfig>
     <avrtool>com.atmel.avrdbg.tool.atmelice</avrtool>
     <avrtoolserialnumber>J41800087098</avrtoolserialnumber>
@@ -165,9 +165,42 @@
     <Compile Include="Device_Startup\system_samd51.c">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="hardware.h">
+      <SubType>compile</SubType>
+    </Compile>
     <Compile Include="main.c">
       <SubType>compile</SubType>
     </Compile>
+    <Compile Include="pin.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="pin.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="pwm_foc.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="pwm_foc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="ringbuffer.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="ringbuffer.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="spiport.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="spiport.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="uartport.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="uartport.h">
+      <SubType>compile</SubType>
+    </Compile>
   </ItemGroup>
   <ItemGroup>
     <Folder Include="Device_Startup\" />

embedded/mkbldcdriver-v03/mkbldcdriver-v03/pin.c

+/*
+ * pin.c
+ *
+ * Created: 2/5/2018 11:21:37 PM
+ *  Author: Jake
+ */ 
+
+#include "pin.h"
+#include "sam.h"
+
+pin_t pin_new(PortGroup *port, uint32_t pin_number){
+	pin_t pin;
+	pin.port = port;
+	pin.bm = (uint32_t)(1 << pin_number);
+	return pin;
+}
+
+
+void pin_output(pin_t *pin){
+	pin->port->DIRSET.reg = pin->bm;
+	pin->port->OUTCLR.reg = pin->bm;
+}
+
+void pin_input(pin_t *pin){
+	pin->port->DIRCLR.reg = pin->bm;
+}
+
+void pin_set(pin_t *pin){
+	pin->port->OUTSET.reg = pin->bm;
+}
+
+void pin_clear(pin_t *pin){
+	pin->port->OUTCLR.reg = pin->bm;
+}
+
+void pin_toggle(pin_t *pin){
+	pin->port->OUTTGL.reg = pin->bm;
+}
+
+int pin_read(pin_t *pin){
+	return pin->port->IN.reg & pin->bm;
+}
\ No newline at end of file

embedded/mkbldcdriver-v03/mkbldcdriver-v03/pin.h

+/*
+ * pin.h
+ *
+ * Created: 2/5/2018 11:21:47 PM
+ *  Author: Jake
+ */ 
+
+
+#ifndef PIN_H_
+#define PIN_H_
+
+#include "sam.h"
+
+typedef struct {
+	PortGroup *port;
+	uint32_t bm; // bitmask
+} pin_t;
+
+pin_t pin_new(PortGroup *port, uint32_t pin);
+
+void pin_output(pin_t *pin);
+void pin_input(pin_t *pin);
+
+void pin_set(pin_t *pin);
+void pin_clear(pin_t *pin);
+void pin_toggle(pin_t *pin);
+
+int pin_read(pin_t *pin);
+
+#endif /* PIN_H_ */
\ No newline at end of file

embedded/mkbldcdriver-v03/mkbldcdriver-v03/pwm_foc.c

+/*
+ * pwm.c
+ *
+ * Created: 2/17/2018 10:22:16 PM
+ *  Author: Jake
+ */ 
+#include "pwm_foc.h"
+
+void pwmsetup_foc(void){
+	/* TCC SETUP */
+	// from 49.6.2.1
+	// a few registers are protected - and can only be updated when
+	// TCCn.CTRLA.ENABLE = 0
+	// FCTRLA and FCTRLB, WEXCTRL, DRVCTRL, and EVCTRL
+	
+	// (4) Configure Output Pin with PORT->Group[n].DIRSET.reg
+	// PA8 PA9 PA10 PA12, PB10 PB11
+	// 32.9.13
+	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 8) | (uint32_t)(1 << 9) | (uint32_t)(1 << 10) | (uint32_t)(1 << 12);
+	PORT->Group[1].DIRSET.reg |= (uint32_t)(1 << 10) | (uint32_t)(1 << 11);
+	
+	// 1 lo / hi
+	PORT->Group[0].PINCFG[10].bit.PMUXEN = 1;
+	PORT->Group[0].PMUX[10>>1].reg |= PORT_PMUX_PMUXE(0x5);  // on peripheral F
+	PORT->Group[0].PINCFG[12].bit.PMUXEN = 1;
+	PORT->Group[0].PMUX[12>>1].reg |= PORT_PMUX_PMUXE(0x5);
+	
+	// 2 lo / hi
+	PORT->Group[0].PINCFG[9].bit.PMUXEN = 1;
+	PORT->Group[0].PMUX[9>>1].reg |= PORT_PMUX_PMUXO(0x5);  // on peripheral F
+	PORT->Group[1].PINCFG[11].bit.PMUXEN = 1;
+	PORT->Group[1].PMUX[11>>1].reg |= PORT_PMUX_PMUXO(0x5);
+	
+	// 3 lo / hi
+	PORT->Group[0].PINCFG[8].bit.PMUXEN = 1;
+	PORT->Group[0].PMUX[8>>1].reg |= PORT_PMUX_PMUXE(0x5);  // on peripheral F
+	PORT->Group[1].PINCFG[10].bit.PMUXEN = 1;
+	PORT->Group[1].PMUX[10>>1].reg |= PORT_PMUX_PMUXE(0x5);
+	
+	// (1) enable the TCC Bus Clock - CLK_TCCn_APB
+	// https://www.eevblog.com/forum/microcontrollers/atmel-sam-d-tc-and-tcc-(no-asf)/
+	
+	TCC0->CTRLA.bit.ENABLE = 0;
+	
+	MCLK->APBBMASK.reg |= MCLK_APBBMASK_TCC0; // at 15.8.9
+	
+	GCLK->GENCTRL[5].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) | GCLK_GENCTRL_GENEN;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5);