usb running on COM with 120MHz clock as well

embedded/usb-adafruit-cdc/usb-adafruit-cdc/board_driver_usb.c

@@ -107,9 +107,9 @@ void USB_Init(void)
    * Put Generic Clock Generator 0 as source for Generic Clock Multiplexer 6 (USB reference)
    *
 	*/
-  GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
   MCLK->APBBMASK.reg |= MCLK_APBBMASK_USB;
-  while(GCLK->SYNCBUSY.bit.GENCTRL0)
+  while(GCLK->SYNCBUSY.bit.GENCTRL1)
   {
     /* Wait for synchronization */
   }

embedded/usb-adafruit-cdc/usb-adafruit-cdc/board_init.c

@@ -117,7 +117,7 @@ void board_init(void)
 	/* ----------------------------------------------------------------------------------------------
 	* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
 	*/
-	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) |
+	GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) |
 	GCLK_GENCTRL_IDC |
 	GCLK_GENCTRL_OE |
 	GCLK_GENCTRL_GENEN;
@@ -127,6 +127,24 @@ void board_init(void)
 		/* Wait for synchronization */
 	}
 	
+	// now we want a DPLL0 for MCLK
+	
+	// a reference, from the DFLL, for the DPLL0
+	GCLK->GENCTRL[5].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
+	while(GCLK->SYNCBUSY.bit.GENCTRL5);
+	
+	// the DPLL setup
+	GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
+	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59);
+	while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
+	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
+	while(OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0);
+	// set clock to use dpll0
+	
+	// this would switch the CPU clock to the DPLL0
+	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL0) | GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0);
 	
 	/* Turn on the digital interface clock */
 	//MCLK->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
@@ -137,3 +155,63 @@ void board_init(void)
 	*/
 	MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV_DIV1;
 }
+
+void clock_init(void){
+	// on Reset, the DFLL48< source clock is on and running at 48MHz
+	// GCLK0 uses DFLL48M as a source and generates GCLK_MAIN
+	// we want to use OSCCTRL to (1) set the DFLL48M to run on a reference clock, in closed-loop mode
+	// (20 then to prescale the DFLL48M such that it runs at 120MHz
+		
+	// for 120mhz do https://github.com/adafruit/ArduinoCore-samd/blob/samd51/cores/arduino/startup.c
+	
+	// something?
+	NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(0);
+	
+	// reset
+	GCLK->CTRLA.bit.SWRST = 1;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST);
+	
+	// Setup internal reference to gclk gen 3
+	GCLK->GENCTRL[3].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3);
+	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0);
+	
+	// enable DFLL48M clock
+	OSCCTRL->DFLLCTRLA.reg = 0;
+	OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP(0x1) | OSCCTRL_DFLLMUL_FSTEP(0x1) | OSCCTRL_DFLLMUL_MUL(0);
+	while(OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLMUL);
+	OSCCTRL->DFLLCTRLB.reg = 0;
+	while(OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLCTRLB);
+	OSCCTRL->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
+	while(OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_ENABLE);
+	OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_WAITLOCK | OSCCTRL_DFLLCTRLB_CCDIS | OSCCTRL_DFLLCTRLB_USBCRM;
+	while(!OSCCTRL->STATUS.bit.DFLLRDY);
+	
+	// a reference for the USB, 48MHz
+	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
+	GCLK_GENCTRL_IDC |
+	GCLK_GENCTRL_OE |
+	GCLK_GENCTRL_GENEN;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0);
+	
+	// this is generating a reference for our 120mhz
+	GCLK->GENCTRL[5].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
+	while(GCLK->SYNCBUSY.bit.GENCTRL5);
+	
+	/*
+	// setup DPLL0 to 120MHz
+	GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
+	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59);
+	while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
+	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
+	while(OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0);
+	// set clock to use dpll0
+	
+	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL0) | GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN;
+	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0);
+	*/
+	
+	MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV_DIV1;
+}
\ No newline at end of file