push log to log, add img of new

README.md

 ## Fab Stepper Driver
 
+Fab-Labbable (i.e. easy-to-pcb-mill) design for a networked stepper driver. 
+
+SAMD21E18 micro, 2x A4950 H-Bridges to drive, UART over RS485 network / bus connection. 
+
+## Status 
+
+**2021 06 15** 
+
+I have the D21 alive and running, and the 2x H-Bridges alive and stepping w/ microstepping via VREFs and a LUT. A previous design used TTL comms and the SPI peripheral, I have elected to re-do with UART over RS485. Those boards are in the mail, so I'll be testing / making-alive next month. I'm also interested in refining an embedded-level motion controller and networked interface. The D21 presents some (mostly RAM limited) programming challenges, and without an FPU I'm curious about how well lookahead will work. 
+
+[dev log](log/fab-step-log.md)
+
+## Images
+
+![route](log/2021-06-12_routed.png)
+![schem](log/2021-06-12_schem.png)
+
 ### BOM 
 
 | Part | PN | Count |
@@ -19,25 +36,3 @@
 | 120R 1206 | 541-4193-1-ND |
 | 10k 1206 | 541-3983-1-ND |
 | LED 1206 | 160-1403-1-ND | 
\ No newline at end of file
-
-## Log 
-
-## 2020 11 05 
-
-Started in, have the schematic mostly roughed out: this'll be 1.5 sided (solid GND below a routed layer). I think... the largest challenge is just getting things around themselves without using any vias. Found a tranciever as well. 
-
-## 2020 11 16
-
-Just routed out the program / power / data interface side of this. 
-
-![routing](2020-11-16_routing.png)
-
-Success going forward will rely on a a fortuitous alignment of the RS485 interface pins against a SERCOM port somewhere on 11-16... not at all sure if any such alignment exists. 
-
-## 2020 11 17
-
-Lucky me, those line up. I can put the SERCOM's TXPO at 0 (for TX on SER-0) and and RXPO at 3 (for RX on SER-3) and the middle two will do data enable and rx enable, just GPIO. 
-
-![routing](2020-11-17_routing.png)
-
-So, sorted that out. I think it works OK. I can make one of these in the fab-version, and can copy the schematic onto a smaller 2-layer board to fab lots of at a board house, having pins 17-20 free for an AS5047 on the back... same RS485 interface, maybe the QFN D21, and 0805s or smaller passives, pinch traces / spaces etc. 
\ No newline at end of file

log/fab-step-log.md

+## Log 
+
+## 2020 11 05 
+
+Started in, have the schematic mostly roughed out: this'll be 1.5 sided (solid GND below a routed layer). I think... the largest challenge is just getting things around themselves without using any vias. Found a tranciever as well. 
+
+## 2020 11 16
+
+Just routed out the program / power / data interface side of this. 
+
+![routing](2020-11-16_routing.png)
+
+Success going forward will rely on a a fortuitous alignment of the RS485 interface pins against a SERCOM port somewhere on 11-16... not at all sure if any such alignment exists. 
+
+## 2020 11 17
+
+Lucky me, those line up. I can put the SERCOM's TXPO at 0 (for TX on SER-0) and and RXPO at 3 (for RX on SER-3) and the middle two will do data enable and rx enable, just GPIO. 
+
+![routing](2020-11-17_routing.png)
+
+So, sorted that out. I think it works OK. I can make one of these in the fab-version, and can copy the schematic onto a smaller 2-layer board to fab lots of at a board house, having pins 17-20 free for an AS5047 on the back... same RS485 interface, maybe the QFN D21, and 0805s or smaller passives, pinch traces / spaces etc. 
+
+## 2021 06 12 
+
+Re-routed this for UCBus compatibility, still looks like the best option despite SPI availability: SPI interrupt handlers are minimum ~ 2us, meaning byte period of 2.6us (at 3MHz) is limiting, might as well use simplicity of UART, and ability / option for it to self-configure as P2P connection, etc. RS485 UART is same pin count as TTL SPI, would rather have noise / distance immunity. 
+
+I left off some pins (SERCOM0) to potentially add an encoder here, the routing for that would be tough but probably possible. 
+
+![route](2021-06-12_routed.png)
+![schem](2021-06-12_schem.png)
\ No newline at end of file