Skip to content
Snippets Groups Projects
Commit 34dd900a authored by Sam Calisch's avatar Sam Calisch
Browse files

added bc832 board using fab inventory parts

parent fe626518
Branches
No related tags found
No related merge requests found
Pipeline #
Show whitespace changes
Inline Side-by-side
bc832-ftdi/bc832-nrf-ftdi-fab-interior.png 0 → 100644
+ 0
− 0
View file @ 34dd900a
bc832-ftdi/bc832-nrf-ftdi-fab-interior.png

6.55 KiB

bc832-ftdi/bc832-nrf-ftdi-fab-layout.png 0 → 100644
+ 0
− 0
View file @ 34dd900a
bc832-ftdi/bc832-nrf-ftdi-fab-layout.png

130 KiB

bc832-ftdi/bc832-nrf-ftdi-fab-traces.png 0 → 100644
+ 0
− 0
View file @ 34dd900a
bc832-ftdi/bc832-nrf-ftdi-fab-traces.png

12.1 KiB

bc832-ftdi/bc832-nrf-ftdi-fab.ko 0 → 100644
+ 315
− 0
View file @ 34dd900a
from koko.lib.pcb import *
from koko.lib.sam import *
class TagConnectPDI(Component):
'''
'''
_pad = s2d.circle(0,0,.5*.031)
_via = s2d.circle(0,0,.5*.039)
pins = [
Pin(-.05,-.025,_pad,'CLK',label_size=.02),
Pin( .00,-.025,_pad,'NC',label_size=.02),
Pin( .05,-.025,_pad,'DAT',label_size=.02),
Pin(-.05,.025,_pad,'VCC',label_size=.02),
Pin( .00,.025,_pad,'NC',label_size=.02),
Pin( .05,.025,_pad,'GND',label_size=.02)
]
vias = [
Via(-.1,0,_via),
Via(.1,0.04,_via),
Via(.1,-.04,_via),
]
class R_0805_small(Component):
''' 0805 Resistor
'''
_pad_0805 = s2d.rectangle(-.017,.017, -.026, .026)
pins = [Pin(-0.04, 0, _pad_0805), Pin(0.04, 0, _pad_0805)]
prefix = 'R'
vias = []
class Button(Component):
''' SW262CT-ND
'''
rect = rectangle(-.75/25.4,.75/25.4,-.5/25.4,.5/25.4)
pins = [
Pin(-2/25.4,.8/25.4,rect),
Pin( 2/25.4,.8/25.4,rect),
Pin(-2/25.4,-.8/25.4,rect),
Pin( 2/25.4,-.8/25.4,rect)
]
prefix = 'button'
vias = []
shadow = rectangle(-2.1/25.4,2.1/25.4,-1.4/25.4,1.4/25.4)
class TagConnectSWD(Component):
'''
'''
_pad = s2d.circle(0,0,.5*.031)
_via = s2d.circle(0,0,.5*.039)
pins = [
Pin(-.05,-.025,_pad,'GND',label_size=.012),
Pin( .00,-.025,_pad,'NC',label_size=.012),
Pin( .05,-.025,_pad,'VCC',label_size=.012),
Pin(-.05,.025,_pad,'GND',label_size=.012),
Pin( .00,.025,_pad,'SWDIO',label_size=.012),
Pin( .05,.025,_pad,'SWDCLK',label_size=.012)
]
vias = [
Via(-.1,0,_via),
Via(.1,0.04,_via),
Via(.1,-.04,_via),
]
class Regulator_SOT23(Component):
''' SOT23 voltage regulator
'''
_pad_SOT23 = s2d.rectangle(-.02,.02,-.012,.012)
pins = [
Pin(-0.045, -0.0375, _pad_SOT23,'IN'),
Pin(-0.045, 0.0375, _pad_SOT23,'OUT'),
Pin(0.045, 0, _pad_SOT23,'GND')
]
prefix = 'U'
vias = []
class Crystal_FC135(Component):
''' CRYSTAL 32.7680KHZ 12.5PF SMT
'''
_pad = s2d.rectangle(-.5/25.4,.5/25.4,-.9/25.4,.9/25.4)
pins = [
Pin(-1.25/25.4, 0, _pad),
Pin( 1.25/25.4, 0, _pad),
]
prefix = 'U'
vias = []
class Header_FTDI(Component):
''' FTDI cable header
'''
_pad_header = chamfered_rectangle(-0.06, 0.08,-0.025, 0.025,.007)
pins = [
#Pin(0, -0.25, _pad_header, 'RTS'),
Pin(0, -0.15, _pad_header, 'RX'),
Pin(0, -0.05, _pad_header, 'TX'),
Pin(0, 0.05, _pad_header, 'VCC'),
Pin(0, 0.15, _pad_header, 'CTS'),
Pin(0, 0.25, _pad_header, 'GND')
]
prefix = 'J'
vias = []
shadow = s2d.rectangle(-.06,8/25.4,-.3,.3)
#shadow = s2d.rectangle(-.06,8/25.4,-.3,.2)
class Header_Daughter(Component):
''' FTDI cable header
'''
_pad_header = chamfered_rectangle(-0.03, 0.03,-0.015, 0.015,.002)
labels=['SDA','SCL','A4','A5']
pins = [ Pin(0,.05*(i-1.5),_pad_header,l) for i,l in enumerate(labels)]
prefix = 'J'
vias = [Via(p.x,p.y,circle(0,0,.017)) for p in pins]
shadow = s2d.rectangle(-.03,.03,-.1,.1)
def bot_chamfered_rectangle(x0,x1,y0,y1,c):
r = rectangle(x0,x1,y0,y1)
c1 = triangle(x0,y0,x0,y0+c,x0+c,y0)
c2 = triangle(x1,y1, x1, y1-c, x1-c, y1)
c3 = triangle(x0,y1, x0+c, y1, x0, y1-c)
c4 = triangle(x1,y0, x1-c, y0, x1, y0+c)
return r-c2-c3
class CR20XX(Component):
#coin cell battery, e.g. 2032
pins = [
Pin(0,0,circle(0,0,5./25.4),'-')
]
shadow = circle(0,0,10./25.4)
vias = []
class AAA(Component):
#AAA battery smd holder
pad = chamfered_rectangle(-.125,.125,-.12,.12,.05)
pins = [
Pin(1.21-.125,0,pad,'+',label_size=.08),
Pin(-1.21+.125,0,pad,'-',label_size=.08),
]
shadow = rectangle(-1.07,1.07,-.25,.25)
vias = [
Via(-1.21+.25,.209,circle(0,0,.039))
]
class MDBT42(Component):
#Raytach nrf52 module
p = .7/25.4
pad_hw = .15/25.4
pad_hh = .8/25.4
_padv = rectangle(-pad_hw,pad_hw,-pad_hh,pad_hh)
_padh = rectangle(-pad_hh,pad_hh,-pad_hw,pad_hw)
_padg = rectangle(-pad_hh,pad_hh,-.35/25.4,.4/25.4)
c= 5/25.4
start_y = 11.8/25.4
start_x = .8/25.4
y_os = .25
names = [
'GND1','SDA','SCL','P27','A4','A5','A6','A7','DEC4','DCC','VDD',
'GND2','XL1','XL2','P2','P3','P4','P5','P6','P7','P8','P9','P10','GND3',
'P11','P12','P13','P14','P15','P16','P17','P18','P19','P20','RESET','SWDCLK','SWDIO','P22','GND4'
]
pins = [Pin(-c,start_y-y_os,_padg,n,label_size=.018) for i,n in enumerate(names[:1])]
pins += [Pin(-c,start_y-3./25.4-i*p-y_os,_padh,n,label_size=.018) for i,n in enumerate(names[1:11])]
pins += [Pin(-c+start_x+i*p,-y_os,_padv,n,label_size=.018,label_rot=-90) for i,n in enumerate(names[11:24])]
pins += [Pin(c,start_y-.9/25.4-i*p-y_os,_padh,n,label_size=.018) for i,n in enumerate(names[24:38][::-1])]
pins += [Pin(c,start_y-y_os,_padg,n,label_size=.018) for i,n in enumerate(names[38:])]
vias = []
shadow = rectangle(-c,c,-y_os,start_y+4.2/25.4-y_os)
class BT832(Component):
#Fanstel BT832 nrf52 module
p = 1.1/25.4
pad_hw = .7/25.4
pad_hh = .35/25.4
_pad = rectangle(-pad_hw,pad_hw,-pad_hh,pad_hh)
c= 7/25.4
start_y = 1.1/25.4
y_os = .25
names = [
'SDA','SCL','XL1','XL2','AIN0','AIN1','NFC1','NFC2',
'VCC','GND','P13','P18','P20','RESET','SWDCLK','SWDIO'
]
pins = [Pin(-c,start_y+i*p-y_os,_pad,n,label_size=.018) for i,n in enumerate(names[:8][::-1])]
pins += [Pin(c,start_y+i*p-y_os,_pad,n,label_size=.018) for i,n in enumerate(names[8:16])]
vias = []
shadow = rectangle(-c,c,-y_os,16/25.4-y_os)
class BC832(Component):
#Fanstel BC832 micro nrf52 module
p = 1.1/25.4
pad_hw = .7/25.4
pad_hh = .34/25.4
_pad_lga = circle(0,0,.32/25.4)
_pad = rectangle(-pad_hw,pad_hw,-pad_hh,pad_hh)
c= 3.9/25.4
start_y = .618/25.4
y_os = .18
names = [
'GND','DFU','SWDIO','SWDCLK','P18','P13','P11','P12',
'A1','RESET','XL1','XL2','A0','P27','P26','VDD',
]
pins = [Pin(-c,start_y+i*p-y_os,_pad,n,label_size=.018) for i,n in enumerate(names[:8][::-1])]
pins += [Pin(c,start_y+i*p-y_os,_pad,n,label_size=.018) for i,n in enumerate(names[8:16])]
pins += [
Pin(-c+2.15/25.4,-y_os+.519/25.4,_pad_lga,'P8',label_size=.01),
Pin(-c+2.15/25.4,-y_os+(1.2+.519)/25.4,_pad_lga,'P6',label_size=.01)
]
vias = []
shadow = rectangle(-c,c,-y_os,8.8/25.4-y_os)
class Hole(Component):
pins = [Pin(0,0,circle(0,0,0.01))]
vias = [Via(0,0,circle(0,0,.5*2.1/25.4))]
tap = circle(0,0,.5*1.9/25.5)
width = .95
height = .7
pcb = PCB(0,0,width,height,chamfer_distance=.02)
def connectG(pin,dx,dy,width=.012):
'''
Convenience function for connecting to ground plane
'''
pcb.connectD(pin,[pin.x+dx,pin.y+dy],[pin.x+dx-.0001,pin.y+dy],width=width,sides=[0,1,1])
def connectS(pin,dx,dy,width=.012):
pcb.connectD(pin,[pin.x+dx+.0001,pin.y+dy],width=width)
def connectM(pin1,pin2,dx,width=.012):
pcb.connectD(pin1,[pin1.x+dx,pin1.y],pin2,width=width)
ftdi = Header_FTDI(.2,.33,180,'ftdi')
pcb += ftdi
reg = Regulator_SOT23(ftdi.x+.14,ftdi['GND'].y+.03,-90,'3.3v')
pcb += reg
pcb.connectV(ftdi['GND'],reg['GND'],width=.02)
pcb.connectD(reg['IN'],[reg['IN'].x,ftdi['VCC'].y-.03],ftdi['VCC'],width=.02)
C_in = C_1206(reg.x+.0,reg.y+.155,180,'Cin\n.1uF',label_size=.02)
pcb += C_in
C2 = C_1206(reg.x+.11,reg.y+.1,-90,'C2\n10uF',label_size=.02)
pcb += C2
pcb.connectV(C2[1],C_in[1],width=.02)
C_out = C_1206(C2.x+.06,C2.y-.15,0,'Cout\n.1uF',label_size=.02)
pcb += C_out
pcb.connectD(C_in[1],[C_in[1].x,C_in[1].y+.0],reg['GND'])
pcb.connectV(reg['IN'],C_in[0],width=.02)
pcb.connectH(reg['OUT'],C_out[0],width=.02)
pcb.connectH(reg['GND'],C_out[1],width=.02)
pcb.connectH(C2[0],C_out[0],width=.02)
mdb = BC832(ftdi.x+.57,ftdi.y+.1,-90,'Fanstel\nBC832\nNRF52')
pcb += mdb
pcb.connectD(mdb['P8'],[mdb['P8'].x-.01,mdb['P8'].y],[ftdi['TX'].x+.31,ftdi['TX'].y+.03],[ftdi['TX'].x+.03,ftdi['TX'].y-.019],ftdi['TX'],width=.014)
pcb.connectD(mdb['P6'],[mdb['P6'].x,mdb['P6'].y+.02],[mdb['P6'].x-.07,mdb['P6'].y+.035],[ftdi['RX'].x+.28,ftdi['RX'].y-.043],[ftdi['RX'].x+.1,ftdi['RX'].y-.088],[ftdi['RX'].x+.09,ftdi['RX'].y-.03],ftdi['RX'],width=.012)
swd = TagConnectSWD(ftdi.x+.17,mdb.y+.1,-90,'swd')
pcb += swd
pcb.connectD(swd['SWDCLK'],[swd['SWDCLK'].x+.02,swd['SWDCLK'].y],[mdb['SWDCLK'].x-.24,mdb['SWDCLK'].y+.01],[mdb['SWDCLK'].x-.02,mdb['SWDCLK'].y+.05],mdb['SWDCLK'],width=.012)
pcb.connectD(swd['SWDIO'],[swd['SWDIO'].x+.02,swd['SWDIO'].y],[mdb['SWDIO'].x-.32,mdb['SWDIO'].y+.04],[mdb['SWDIO'].x-.03,mdb['SWDIO'].y+.079],mdb['SWDIO'],width=.012)
#pcb.connectD(ftdi['RTS'],[ftdi['RTS'].x,ftdi['RTS'].y+.03],[mdb['DFU'].x-.05,mdb['DFU'].y+.12],mdb['DFU'],width=.014)
button = Button(ftdi.x-.01,ftdi.y+.26,0)
pcb += button
pcb.connectH(ftdi['GND'],[button[1].x-.07,button[1].y],button[1])
pcb.connectV(mdb['RESET'],[ftdi.x-.11,ftdi['TX'].y-.05],button[3],width=.014)
pcb.connectV(button[3],button[0])
pcb.connectV(button[1],button[2])
pcb.connectD(mdb['GND'],[mdb['GND'].x,mdb['GND'].y+.03],[button.x+.15,mdb['GND'].y+.108],button[2],width=.012)
pcb.connectV(mdb['VDD'],[C_out[0].x+.02,C_out[0].y-.02],C_out[0])
led = R_1206(mdb['XL2'].x+.05,mdb['XL1'].y-.17,0,'led',label_size=.03)
pcb += led
R_led = R_1206(led.x,led.y+.09,0,'1k',label_size=.03)
pcb += R_led
pcb.connectV(led[1],R_led[1])
pcb.connectV(mdb['VDD'],led[0])
pcb.connectV(mdb['P27'],R_led[0])
pcb.connectH(swd[4],swd[1])
pcb.connectD(swd[1],button[2])
R1 = R_1206(C2.x+.09,C2.y,90,'10k',label_size=.03)
pcb += R1
pcb.connectV(mdb['RESET'],[R1[0].x,R1[0].y+.06],R1[0])
pcb.connectH(C2[0],R1[1])
cad.shapes = pcb.layout()
#cad.shape = pcb.traces+(pcb.cutout-pcb.cutout)
#cad.shape = pcb.cutout+(pcb.traces-pcb.traces)
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment