Clean up HTML and link it in

comm/iCE40/notes.html

@@ -36,8 +36,8 @@ Install instructions for all of the above tools can be found on the
 </center>
 
 <p>
-The default `make` target synthesizes the design and runs a timing analysis. The target `prog`
-programs an available iCEBreaker via USB.
+The default make target synthesizes the design and runs a timing analysis. The target prog programs
+an available iCEBreaker via USB.
 </p>
 
 
@@ -59,17 +59,17 @@ reports times 256.)
 </center>
 
 <p>
-The fastest I can clock the FPGA while passing `icetime`'s analysis is 39.75MHz. This lets us use a
+The fastest I can clock the FPGA while passing icetime's analysis is 39.75MHz. This lets us use a
 baud rate of nearly 5Mbit (we want to use 8x oversampling when receiving data since the two FPGAs
 clocks aren't synchronized). At this speed, we see groups of 256 round trips happening at a rate of
 978Hz. So overall this means the individual round trip frequency is 250kHz.
 </p>
 
-<img src="./img/comm_ring_40mhz.png" alt="oscilloscope measurements">
+<img src="/img/comm_ring_40mhz.png" alt="oscilloscope measurements">
 
 <p>
 Out of curiosity, I tried running at 48MHz as well and it seemed to work. At 60MHz however it
-quickly drops a byte. So here it seems prudent to stay within `icetime`'s limits.
+quickly drops a byte. So here it seems prudent to stay within icetime's limits.
 </p>
 
 </div>

index.html

@@ -205,7 +205,7 @@ The communication test measures how quickly two nodes can exchange messages; thi
 
 <tr>
 <td>0.250</td>
-<td><a href=comm/iCE40/ring.v>iCE40, Verilog</a> (<a href=comm/iCE40/README.md>notes</a>)</td>
+<td><a href=comm/iCE40/ring.v>iCE40, Verilog</a> (<a href=comm/iCE40/notes.html>notes</a>)</td>
 <td>tx/rx jumpers (3.3V)</td>
 <td><a href=comm/iCE40/ring.v>iCE40, Verilog</a></td>
 <td>September 2021</td>