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Commit 9e473e61 authored by Erik Strand's avatar Erik Strand
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Make comment more informative

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...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
`default_nettype none `default_nettype none
module top ( module top (
input CLK_12MHZ, // system clock input CLK_12MHZ, // the iCEBreaker has an external 12MHz oscillator
output P1A1, output P1A1,
input P1A2, input P1A2,
); );
......
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