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Commit d15349cc authored by Erik Strand's avatar Erik Strand
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Use HTML instead of markdown (FPGA comm ring)

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# iCE40 Communication Ring Test <!DOCTYPE html>
<html lang="en">
<head>
<meta charset="utf-8">
<title>iCE40 Communication Ring Test Notes</title>
</head>
<body link="black" alink="black" vlink="black">
<font face="bitstream vera sans,arial,helvetica,sans-serif"></font>
## Dependencies <div style="margin-left:2.5%;margin-right:2.5%">
- [IceStorm tools](https://github.com/YosysHQ/icestorm)
- [yosys](http://www.clifford.at/yosys/download.html)
- [nextpnr](https://github.com/YosysHQ/nextpnr)
Install instructions for all of the above tools can be found on the [IceStorm <center>
website](http://bygone.clairexen.net/icestorm/). <h1>iCE40 Communication Ring Test Notes</h1>
</center>
## Building
<center>
<h2>Dependencies</h2>
</center>
<ul>
<li><a href="https://github.com/YosysHQ/icestorm">IceStorm tools</a></li>
<li><a href="http://www.clifford.at/yosys/download.html">yosys</a></li>
<li><a href="https://github.com/YosysHQ/nextpnr">nextpnr</a></li>
</ul>
<p>
Install instructions for all of the above tools can be found on the
<a href="http://bygone.clairexen.net/icestorm/">IceStorm website</a>.
</p>
<center>
<h2>Building</h2>
</center>
<p>
The default `make` target synthesizes the design and runs a timing analysis. The target `prog` The default `make` target synthesizes the design and runs a timing analysis. The target `prog`
programs an available iCEBreaker via USB. programs an available iCEBreaker via USB.
</p>
## Running <center>
<h2>Running</h2>
</center>
<p>
I used two iCEBreaker boards. Each board's P1A1 is connected to the other's P1A2. (If you connect I used two iCEBreaker boards. Each board's P1A1 is connected to the other's P1A2. (If you connect
the two P1A1 pins together, the drivers will fight each other until one burns out.) I monitored P1A4 the two P1A1 pins together, the drivers will fight each other until one burns out.) I monitored P1A4
on one of the boards with an oscilloscope. By triggering on this signal, I can time how long it on one of the boards with an oscilloscope. By triggering on this signal, I can time how long it
takes to send 256 packets round trip. (The result of the test is thus the frequency the oscilloscope takes to send 256 packets round trip. (The result of the test is thus the frequency the oscilloscope
reports times 256.) reports times 256.)
</p>
## Results
<center>
<h2>Results</h2>
</center>
<p>
The fastest I can clock the FPGA while passing `icetime`'s analysis is 39.75MHz. This lets us use a The fastest I can clock the FPGA while passing `icetime`'s analysis is 39.75MHz. This lets us use a
baud rate of nearly 5Mbit (we want to use 8x oversampling when receiving data since the two FPGAs baud rate of nearly 5Mbit (we want to use 8x oversampling when receiving data since the two FPGAs
clocks aren't synchronized). At this speed, we see groups of 256 round trips happening at a rate of clocks aren't synchronized). At this speed, we see groups of 256 round trips happening at a rate of
978Hz. So overall this means the individual round trip frequency is 250kHz. 978Hz. So overall this means the individual round trip frequency is 250kHz.
</p>
![64.5MHz](./img/comm_ring_40mhz.png) <img src="./img/comm_ring_40mhz.png" alt="oscilloscope measurements">
<p>
Out of curiosity, I tried running at 48MHz as well and it seemed to work. At 60MHz however it Out of curiosity, I tried running at 48MHz as well and it seemed to work. At 60MHz however it
quickly drops a byte. So here it seems prudent to stay within `icetime`'s limits. quickly drops a byte. So here it seems prudent to stay within `icetime`'s limits.
</p>
</div>
</body>
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