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Commit 90b97c65 authored by Sam Calisch's avatar Sam Calisch
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fix reset line

parent 7dc0327b
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as5013-test/nrf52-as5013-interior.png

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as5013-test/nrf52-as5013-interior.png

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as5013-test/nrf52-as5013-layout.png

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as5013-test/nrf52-as5013-traces.png

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......@@ -283,17 +283,14 @@ h = .16
hall = AS5013(.5*width,h,-180)
pcb += hall
#TODO: check bolt holes
pcb.connectD(hall['SDA'],[hall['SDA'].x+.07,hall['SDA'].y],bc['XL2'],width=.014)
pcb.connectD(hall['SCL'],[hall['SCL'].x+.05,hall['SCL'].y],bc['XL1'],width=.014)
#pcb.connectH(hall['SCL'],[hall['SCL'].x,hall['SCL'].y+.06],bc['XL1'])
#pcb.connectV(hall['RST'],[C2[0].x,C2[0].y-.06],C2[0])
RSDA = R_1206(bc['XL2'].x+.09,bc['XL2'].y-.08,0,'RSDA')
RSDA = R_1206(bc['XL2'].x+.12,bc['XL2'].y-.08,0,'RSDA')
pcb += RSDA
RSCL = R_1206(bc['XL1'].x+.045,RSDA.y-.1,0,'RSCL')
RSCL = R_1206(RSDA[1].x,RSDA.y-.09,0,'RSCL')
pcb += RSCL
pcb.connectH(RSCL[0],RSDA[0])
pcb.connectH(RSDA[0],bc['VDD'])
......@@ -308,7 +305,16 @@ pcb.connectD(C_hall[1],[C_hall[1].x,C_hall[1].y-.05],[hall['VSS'].x,hall['VSS'].
pcb.connectD(C_hall[0],[C_hall[0].x,C_hall[0].y+.1],C2[0])
pcb.connectD(C_hall[1],[C_hall[1].x,C_hall[1].y+.15],C_out[1])
pcb.connectV(C_hall[0],[C_hall.x-.15,C_hall.y+.1],[bc['VDD'].x,C_hall.y-.12],bc['VDD']).add_jumper([C_hall[1].x,C_hall.y+.1])
pcb.connectD(hall['SDA'],[RSDA[1].x-.07,hall['SDA'].y],RSDA[1],width=.014)
pcb.connectD(RSDA[1],[RSDA[1].x-.05,RSDA[1].y],bc['XL2'])
pcb.connectD(hall['SCL'],[RSCL[1].x-.03,hall['SCL'].y],RSCL[1],width=.014)
pcb.connectD(RSCL[1],bc['XL1'])
pcb.connectD(hall['RST'],[hall['RST'].x+.04,hall['RST'].y],[hall['RST'].x+.05,hall['RST'].y+.05],bc['A1'],width=.014)
pcb.connectD(C_hall[0],[C_hall[0].x,C_hall.y+.1],[C_hall.x-.15,C_hall.y+.1],[C_hall.x-.15,C_hall.y-.08],[bc['VDD'].x-.2,C_hall.y-.12],bc['VDD']).add_jumper([C_hall[1].x,C_hall.y+.1])
#pow = Header_Power(reg.x-.2,reg.y,0,'pow')
#pcb += pow
......
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