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Commit ee26fea8 authored by Erik Strand's avatar Erik Strand
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Change FPGA ring test notes to HTML

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GPIO/iCE40/README.md → GPIO/iCE40/notes.html
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# iCE40 Ring Oscillator Test
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="utf-8">
<title>iCE40 Ring Oscillation Test Notes</title>
</head>
<body link="black" alink="black" vlink="black">
<font face="bitstream vera sans,arial,helvetica,sans-serif"></font>
## Dependencies
<div style="margin-left:2.5%;margin-right:2.5%">
- [IceStorm tools](https://github.com/YosysHQ/icestorm)
- [yosys](http://www.clifford.at/yosys/download.html)
- [nextpnr](https://github.com/YosysHQ/nextpnr)
Install instructions for all of the above tools can be found on the [IceStorm
website](http://bygone.clairexen.net/icestorm/).
<center>
<h1>iCE40 Ring Oscillation Test Notes</h1>
</center>
## Building
The default `make` target synthesizes the design and runs a timing analysis. The target `prog`
programs an available iCEBreaker via USB.
<center>
<h2>Dependencies</h2>
</center>
## Results
<ul>
<li><a href="https://github.com/YosysHQ/icestorm">IceStorm tools</a></li>
<li><a href="http://www.clifford.at/yosys/download.html">yosys</a></li>
<li><a href="https://github.com/YosysHQ/nextpnr">nextpnr</a></li>
</ul>
<p>
Install instructions for all of the above tools can be found on the
<a href="http://bygone.clairexen.net/icestorm/">IceStorm website</a>.
</p>
<center>
<h2>Building</h2>
</center>
<p>
The default make target synthesizes the design and runs a timing analysis. The target prog programs
an available iCEBreaker via USB.
</p>
<center>
<h2>Results</h2>
</center>
<p>
When clocking the FPGA at 24MHz, the resulting ring oscillation is still identifiable as a square
wave.
</p>
![12MHz](./img/ring_12mhz.png)
<center>
<img src="./img/ring_12mhz.png" alt="12MHz">
</center>
<p>
By 111MHz, it's more of a triangle wave. But still stable and nearly rail to rail. This is the
fastest clock speed that `icetime` approves.
</p>
![55.5MHz](./img/ring_55mhz.png)
<center>
<img src="./img/ring_55mhz.png" alt="55.5MHz">
</center>
<p>
Despite not passing the timing analysis, when the FPGA is clocked at 120MHz no problems seems to
occur.
</p>
![60MHz](./img/ring_60mhz.png)
<center>
<img src="./img/ring_60mhz.png" alt="60MHz">
</center>
<p>
Even at 129MHz, stable ring oscillation can occur. I (Erik) thought that the first time I ran it I
got a chaotic, aperiodic signal. But I haven't been able to reproduce this so I might have made a
mistake. Still, I'll hold off on declaring this result official.
</p>
![64.5MHz](./img/ring_64mhz.png)
<center>
<img src="./img/ring_64mhz.png" alt="64.5MHz">
</center>
<p>
At faster clock speeds things start to go wrong. Usually there's still a periodic ring oscillation,
just much slower than one would hope.
</p>
</div>
</body>
index.html
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......@@ -42,7 +42,7 @@ The GPIO test measures how quickly pins can communicate with a processor core; t
<tr>
<td>60.00</td>
<td>iCE40UP5K</td>
<td>iCEBreaker V1.0e, 120 MHz, <a href=GPIO/iCE40/ring.v>Verilog</a> (<a href=GPIO/iCE40/README.md>notes</a>)</td>
<td>iCEBreaker V1.0e, 120 MHz, <a href=GPIO/iCE40/ring.v>Verilog</a> (<a href=GPIO/iCE40/notes.html>notes</a>)</td>
<td>September 2021</td>
</tr>
......
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